projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'iio-fixes-for-3.16c' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6-block.git] / drivers / gpu / drm / i2c / tda998x_drv.c
CommitLineData
e7792ce2
RC		 1/*
2 * Copyright (C) 2012 Texas Instruments
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18
19
893c3e53 20#include <linux/hdmi.h>
e7792ce2 21#include <linux/module.h>
12473b7d 22#include <linux/irq.h>
f0b33b28 23#include <sound/asoundef.h>
e7792ce2
RC		 24
25#include <drm/drmP.h>
26#include <drm/drm_crtc_helper.h>
27#include <drm/drm_encoder_slave.h>
28#include <drm/drm_edid.h>
c4c11dd1 29#include <drm/i2c/tda998x.h>
e7792ce2
RC		 30
31#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
32
33struct tda998x_priv {
34 struct i2c_client *cec;
2f7f730a 35 struct i2c_client *hdmi;
e7792ce2
RC		 36 uint16_t rev;
37 uint8_t current_page;
38 int dpms;
c4c11dd1 39 bool is_hdmi_sink;
5e74c22c
RK		 40 u8 vip_cntrl_0;
41 u8 vip_cntrl_1;
42 u8 vip_cntrl_2;
c4c11dd1 43 struct tda998x_encoder_params params;
12473b7d
JFM		 44
45 wait_queue_head_t wq_edid;
46 volatile int wq_edid_wait;
47 struct drm_encoder *encoder;
e7792ce2
RC		 48};
49
50#define to_tda998x_priv(x) ((struct tda998x_priv *)to_encoder_slave(x)->slave_priv)
51
52/* The TDA9988 series of devices use a paged register scheme.. to simplify
53 * things we encode the page # in upper bits of the register #. To read/
54 * write a given register, we need to make sure CURPAGE register is set
55 * appropriately. Which implies reads/writes are not atomic. Fun!
56 */
57
58#define REG(page, addr) (((page) << 8) | (addr))
59#define REG2ADDR(reg) ((reg) & 0xff)
60#define REG2PAGE(reg) (((reg) >> 8) & 0xff)
61
62#define REG_CURPAGE 0xff /* write */
63
64
65/* Page 00h: General Control */
66#define REG_VERSION_LSB REG(0x00, 0x00) /* read */
67#define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */
68# define MAIN_CNTRL0_SR (1 << 0)
69# define MAIN_CNTRL0_DECS (1 << 1)
70# define MAIN_CNTRL0_DEHS (1 << 2)
71# define MAIN_CNTRL0_CECS (1 << 3)
72# define MAIN_CNTRL0_CEHS (1 << 4)
73# define MAIN_CNTRL0_SCALER (1 << 7)
74#define REG_VERSION_MSB REG(0x00, 0x02) /* read */
75#define REG_SOFTRESET REG(0x00, 0x0a) /* write */
76# define SOFTRESET_AUDIO (1 << 0)
77# define SOFTRESET_I2C_MASTER (1 << 1)
78#define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */
79#define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */
80#define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */
81# define I2C_MASTER_DIS_MM (1 << 0)
82# define I2C_MASTER_DIS_FILT (1 << 1)
83# define I2C_MASTER_APP_STRT_LAT (1 << 2)
c4c11dd1
RK		 84#define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */
85# define FEAT_POWERDOWN_SPDIF (1 << 3)
e7792ce2
RC		 86#define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */
87#define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */
88#define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */
89# define INT_FLAGS_2_EDID_BLK_RD (1 << 1)
c4c11dd1 90#define REG_ENA_ACLK REG(0x00, 0x16) /* read/write */
e7792ce2
RC		 91#define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */
92#define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */
93#define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */
94#define REG_ENA_AP REG(0x00, 0x1e) /* read/write */
95#define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */
96# define VIP_CNTRL_0_MIRR_A (1 << 7)
97# define VIP_CNTRL_0_SWAP_A(x) (((x) & 7) << 4)
98# define VIP_CNTRL_0_MIRR_B (1 << 3)
99# define VIP_CNTRL_0_SWAP_B(x) (((x) & 7) << 0)
100#define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */
101# define VIP_CNTRL_1_MIRR_C (1 << 7)
102# define VIP_CNTRL_1_SWAP_C(x) (((x) & 7) << 4)
103# define VIP_CNTRL_1_MIRR_D (1 << 3)
104# define VIP_CNTRL_1_SWAP_D(x) (((x) & 7) << 0)
105#define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */
106# define VIP_CNTRL_2_MIRR_E (1 << 7)
107# define VIP_CNTRL_2_SWAP_E(x) (((x) & 7) << 4)
108# define VIP_CNTRL_2_MIRR_F (1 << 3)
109# define VIP_CNTRL_2_SWAP_F(x) (((x) & 7) << 0)
110#define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */
111# define VIP_CNTRL_3_X_TGL (1 << 0)
112# define VIP_CNTRL_3_H_TGL (1 << 1)
113# define VIP_CNTRL_3_V_TGL (1 << 2)
114# define VIP_CNTRL_3_EMB (1 << 3)
115# define VIP_CNTRL_3_SYNC_DE (1 << 4)
116# define VIP_CNTRL_3_SYNC_HS (1 << 5)
117# define VIP_CNTRL_3_DE_INT (1 << 6)
118# define VIP_CNTRL_3_EDGE (1 << 7)
119#define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */
120# define VIP_CNTRL_4_BLC(x) (((x) & 3) << 0)
121# define VIP_CNTRL_4_BLANKIT(x) (((x) & 3) << 2)
122# define VIP_CNTRL_4_CCIR656 (1 << 4)
123# define VIP_CNTRL_4_656_ALT (1 << 5)
124# define VIP_CNTRL_4_TST_656 (1 << 6)
125# define VIP_CNTRL_4_TST_PAT (1 << 7)
126#define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */
127# define VIP_CNTRL_5_CKCASE (1 << 0)
128# define VIP_CNTRL_5_SP_CNT(x) (((x) & 3) << 1)
c4c11dd1 129#define REG_MUX_AP REG(0x00, 0x26) /* read/write */
10df1a95
JFM		 130# define MUX_AP_SELECT_I2S 0x64
131# define MUX_AP_SELECT_SPDIF 0x40
bcb2481d 132#define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */
e7792ce2
RC		 133#define REG_MAT_CONTRL REG(0x00, 0x80) /* write */
134# define MAT_CONTRL_MAT_SC(x) (((x) & 3) << 0)
135# define MAT_CONTRL_MAT_BP (1 << 2)
136#define REG_VIDFORMAT REG(0x00, 0xa0) /* write */
137#define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */
138#define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */
139#define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */
140#define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */
141#define REG_NPIX_MSB REG(0x00, 0xa5) /* write */
142#define REG_NPIX_LSB REG(0x00, 0xa6) /* write */
143#define REG_NLINE_MSB REG(0x00, 0xa7) /* write */
144#define REG_NLINE_LSB REG(0x00, 0xa8) /* write */
145#define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */
146#define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */
147#define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */
148#define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */
149#define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */
150#define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */
151#define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */
152#define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */
088d61d1
SH		 153#define REG_VS_LINE_STRT_2_MSB REG(0x00, 0xb1) /* write */
154#define REG_VS_LINE_STRT_2_LSB REG(0x00, 0xb2) /* write */
e7792ce2
RC		 155#define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */
156#define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */
088d61d1
SH		 157#define REG_VS_LINE_END_2_MSB REG(0x00, 0xb5) /* write */
158#define REG_VS_LINE_END_2_LSB REG(0x00, 0xb6) /* write */
e7792ce2
RC		 159#define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */
160#define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */
161#define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */
162#define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */
163#define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */
164#define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */
165#define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */
166#define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */
167#define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */
168#define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */
088d61d1
SH		 169#define REG_VWIN_START_2_MSB REG(0x00, 0xc1) /* write */
170#define REG_VWIN_START_2_LSB REG(0x00, 0xc2) /* write */
171#define REG_VWIN_END_2_MSB REG(0x00, 0xc3) /* write */
172#define REG_VWIN_END_2_LSB REG(0x00, 0xc4) /* write */
e7792ce2
RC		 173#define REG_DE_START_MSB REG(0x00, 0xc5) /* write */
174#define REG_DE_START_LSB REG(0x00, 0xc6) /* write */
175#define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */
176#define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */
177#define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */
088d61d1
SH		 178# define TBG_CNTRL_0_TOP_TGL (1 << 0)
179# define TBG_CNTRL_0_TOP_SEL (1 << 1)
180# define TBG_CNTRL_0_DE_EXT (1 << 2)
181# define TBG_CNTRL_0_TOP_EXT (1 << 3)
e7792ce2
RC		 182# define TBG_CNTRL_0_FRAME_DIS (1 << 5)
183# define TBG_CNTRL_0_SYNC_MTHD (1 << 6)
184# define TBG_CNTRL_0_SYNC_ONCE (1 << 7)
185#define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */
088d61d1
SH		 186# define TBG_CNTRL_1_H_TGL (1 << 0)
187# define TBG_CNTRL_1_V_TGL (1 << 1)
188# define TBG_CNTRL_1_TGL_EN (1 << 2)
189# define TBG_CNTRL_1_X_EXT (1 << 3)
190# define TBG_CNTRL_1_H_EXT (1 << 4)
191# define TBG_CNTRL_1_V_EXT (1 << 5)
e7792ce2
RC		 192# define TBG_CNTRL_1_DWIN_DIS (1 << 6)
193#define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */
194#define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */
195# define HVF_CNTRL_0_SM (1 << 7)
196# define HVF_CNTRL_0_RWB (1 << 6)
197# define HVF_CNTRL_0_PREFIL(x) (((x) & 3) << 2)
198# define HVF_CNTRL_0_INTPOL(x) (((x) & 3) << 0)
199#define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */
200# define HVF_CNTRL_1_FOR (1 << 0)
201# define HVF_CNTRL_1_YUVBLK (1 << 1)
202# define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2)
203# define HVF_CNTRL_1_PAD(x) (((x) & 3) << 4)
204# define HVF_CNTRL_1_SEMI_PLANAR (1 << 6)
205#define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */
c4c11dd1
RK		 206#define REG_I2S_FORMAT REG(0x00, 0xfc) /* read/write */
207# define I2S_FORMAT(x) (((x) & 3) << 0)
208#define REG_AIP_CLKSEL REG(0x00, 0xfd) /* write */
10df1a95
JFM		 209# define AIP_CLKSEL_AIP_SPDIF (0 << 3)
210# define AIP_CLKSEL_AIP_I2S (1 << 3)
211# define AIP_CLKSEL_FS_ACLK (0 << 0)
212# define AIP_CLKSEL_FS_MCLK (1 << 0)
213# define AIP_CLKSEL_FS_FS64SPDIF (2 << 0)
e7792ce2
RC		 214
215/* Page 02h: PLL settings */
216#define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */
217# define PLL_SERIAL_1_SRL_FDN (1 << 0)
218# define PLL_SERIAL_1_SRL_IZ(x) (((x) & 3) << 1)
219# define PLL_SERIAL_1_SRL_MAN_IZ (1 << 6)
220#define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */
3ae471f7 221# define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0)
e7792ce2
RC		 222# define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4)
223#define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */
224# define PLL_SERIAL_3_SRL_CCIR (1 << 0)
225# define PLL_SERIAL_3_SRL_DE (1 << 2)
226# define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4)
227#define REG_SERIALIZER REG(0x02, 0x03) /* read/write */
228#define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */
229#define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */
230#define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */
231#define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */
232#define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */
233#define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */
234#define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */
235#define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */
c4c11dd1
RK		 236# define AUDIO_DIV_SERCLK_1 0
237# define AUDIO_DIV_SERCLK_2 1
238# define AUDIO_DIV_SERCLK_4 2
239# define AUDIO_DIV_SERCLK_8 3
240# define AUDIO_DIV_SERCLK_16 4
241# define AUDIO_DIV_SERCLK_32 5
e7792ce2
RC		 242#define REG_SEL_CLK REG(0x02, 0x11) /* read/write */
243# define SEL_CLK_SEL_CLK1 (1 << 0)
244# define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1)
245# define SEL_CLK_ENA_SC_CLK (1 << 3)
246#define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */
247
248
249/* Page 09h: EDID Control */
250#define REG_EDID_DATA_0 REG(0x09, 0x00) /* read */
251/* next 127 successive registers are the EDID block */
252#define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */
253#define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */
254#define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */
255#define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */
256#define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */
257
258
259/* Page 10h: information frames and packets */
c4c11dd1
RK		 260#define REG_IF1_HB0 REG(0x10, 0x20) /* read/write */
261#define REG_IF2_HB0 REG(0x10, 0x40) /* read/write */
262#define REG_IF3_HB0 REG(0x10, 0x60) /* read/write */
263#define REG_IF4_HB0 REG(0x10, 0x80) /* read/write */
264#define REG_IF5_HB0 REG(0x10, 0xa0) /* read/write */
e7792ce2
RC		 265
266
267/* Page 11h: audio settings and content info packets */
268#define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */
269# define AIP_CNTRL_0_RST_FIFO (1 << 0)
270# define AIP_CNTRL_0_SWAP (1 << 1)
271# define AIP_CNTRL_0_LAYOUT (1 << 2)
272# define AIP_CNTRL_0_ACR_MAN (1 << 5)
273# define AIP_CNTRL_0_RST_CTS (1 << 6)
c4c11dd1
RK		 274#define REG_CA_I2S REG(0x11, 0x01) /* read/write */
275# define CA_I2S_CA_I2S(x) (((x) & 31) << 0)
276# define CA_I2S_HBR_CHSTAT (1 << 6)
277#define REG_LATENCY_RD REG(0x11, 0x04) /* read/write */
278#define REG_ACR_CTS_0 REG(0x11, 0x05) /* read/write */
279#define REG_ACR_CTS_1 REG(0x11, 0x06) /* read/write */
280#define REG_ACR_CTS_2 REG(0x11, 0x07) /* read/write */
281#define REG_ACR_N_0 REG(0x11, 0x08) /* read/write */
282#define REG_ACR_N_1 REG(0x11, 0x09) /* read/write */
283#define REG_ACR_N_2 REG(0x11, 0x0a) /* read/write */
284#define REG_CTS_N REG(0x11, 0x0c) /* read/write */
285# define CTS_N_K(x) (((x) & 7) << 0)
286# define CTS_N_M(x) (((x) & 3) << 4)
e7792ce2
RC		 287#define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */
288# define ENC_CNTRL_RST_ENC (1 << 0)
289# define ENC_CNTRL_RST_SEL (1 << 1)
290# define ENC_CNTRL_CTL_CODE(x) (((x) & 3) << 2)
c4c11dd1
RK		 291#define REG_DIP_FLAGS REG(0x11, 0x0e) /* read/write */
292# define DIP_FLAGS_ACR (1 << 0)
293# define DIP_FLAGS_GC (1 << 1)
294#define REG_DIP_IF_FLAGS REG(0x11, 0x0f) /* read/write */
295# define DIP_IF_FLAGS_IF1 (1 << 1)
296# define DIP_IF_FLAGS_IF2 (1 << 2)
297# define DIP_IF_FLAGS_IF3 (1 << 3)
298# define DIP_IF_FLAGS_IF4 (1 << 4)
299# define DIP_IF_FLAGS_IF5 (1 << 5)
300#define REG_CH_STAT_B(x) REG(0x11, 0x14 + (x)) /* read/write */
e7792ce2
RC		 301
302
303/* Page 12h: HDCP and OTP */
304#define REG_TX3 REG(0x12, 0x9a) /* read/write */
063b472f
RK		 305#define REG_TX4 REG(0x12, 0x9b) /* read/write */
306# define TX4_PD_RAM (1 << 1)
e7792ce2
RC		 307#define REG_TX33 REG(0x12, 0xb8) /* read/write */
308# define TX33_HDMI (1 << 1)
309
310
311/* Page 13h: Gamut related metadata packets */
312
313
314
315/* CEC registers: (not paged)
316 */
12473b7d
JFM		 317#define REG_CEC_INTSTATUS 0xee /* read */
318# define CEC_INTSTATUS_CEC (1 << 0)
319# define CEC_INTSTATUS_HDMI (1 << 1)
e7792ce2
RC		 320#define REG_CEC_FRO_IM_CLK_CTRL 0xfb /* read/write */
321# define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7)
322# define CEC_FRO_IM_CLK_CTRL_ENA_OTP (1 << 6)
323# define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1)
324# define CEC_FRO_IM_CLK_CTRL_FRO_DIV (1 << 0)
12473b7d
JFM		 325#define REG_CEC_RXSHPDINTENA 0xfc /* read/write */
326#define REG_CEC_RXSHPDINT 0xfd /* read */
e7792ce2
RC		 327#define REG_CEC_RXSHPDLEV 0xfe /* read */
328# define CEC_RXSHPDLEV_RXSENS (1 << 0)
329# define CEC_RXSHPDLEV_HPD (1 << 1)
330
331#define REG_CEC_ENAMODS 0xff /* read/write */
332# define CEC_ENAMODS_DIS_FRO (1 << 6)
333# define CEC_ENAMODS_DIS_CCLK (1 << 5)
334# define CEC_ENAMODS_EN_RXSENS (1 << 2)
335# define CEC_ENAMODS_EN_HDMI (1 << 1)
336# define CEC_ENAMODS_EN_CEC (1 << 0)
337
338
339/* Device versions: */
340#define TDA9989N2 0x0101
341#define TDA19989 0x0201
342#define TDA19989N2 0x0202
343#define TDA19988 0x0301
344
345static void
2f7f730a 346cec_write(struct tda998x_priv *priv, uint16_t addr, uint8_t val)
e7792ce2 347{
2f7f730a 348 struct i2c_client *client = priv->cec;
e7792ce2
RC		 349 uint8_t buf[] = {addr, val};
350 int ret;
351
704d63f5 352 ret = i2c_master_send(client, buf, sizeof(buf));
e7792ce2
RC		 353 if (ret < 0)
354 dev_err(&client->dev, "Error %d writing to cec:0x%x\n", ret, addr);
355}
356
357static uint8_t
2f7f730a 358cec_read(struct tda998x_priv *priv, uint8_t addr)
e7792ce2 359{
2f7f730a 360 struct i2c_client *client = priv->cec;
e7792ce2
RC		 361 uint8_t val;
362 int ret;
363
364 ret = i2c_master_send(client, &addr, sizeof(addr));
365 if (ret < 0)
366 goto fail;
367
368 ret = i2c_master_recv(client, &val, sizeof(val));
369 if (ret < 0)
370 goto fail;
371
372 return val;
373
374fail:
375 dev_err(&client->dev, "Error %d reading from cec:0x%x\n", ret, addr);
376 return 0;
377}
378
7d2eadc9 379static int
2f7f730a 380set_page(struct tda998x_priv *priv, uint16_t reg)
e7792ce2 381{
e7792ce2 382 if (REG2PAGE(reg) != priv->current_page) {
2f7f730a 383 struct i2c_client *client = priv->hdmi;
e7792ce2
RC		 384 uint8_t buf[] = {
385 REG_CURPAGE, REG2PAGE(reg)
386 };
387 int ret = i2c_master_send(client, buf, sizeof(buf));
7d2eadc9 388 if (ret < 0) {
704d63f5
JFM		 389 dev_err(&client->dev, "setpage %04x err %d\n",
390 reg, ret);
7d2eadc9
JFM		 391 return ret;
392 }
e7792ce2
RC		 393
394 priv->current_page = REG2PAGE(reg);
395 }
7d2eadc9 396 return 0;
e7792ce2
RC		 397}
398
399static int
2f7f730a 400reg_read_range(struct tda998x_priv *priv, uint16_t reg, char *buf, int cnt)
e7792ce2 401{
2f7f730a 402 struct i2c_client *client = priv->hdmi;
e7792ce2
RC		 403 uint8_t addr = REG2ADDR(reg);
404 int ret;
405
7d2eadc9
JFM		 406 ret = set_page(priv, reg);
407 if (ret < 0)
408 return ret;
e7792ce2
RC		 409
410 ret = i2c_master_send(client, &addr, sizeof(addr));
411 if (ret < 0)
412 goto fail;
413
414 ret = i2c_master_recv(client, buf, cnt);
415 if (ret < 0)
416 goto fail;
417
418 return ret;
419
420fail:
421 dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg);
422 return ret;
423}
424
c4c11dd1 425static void
2f7f730a 426reg_write_range(struct tda998x_priv *priv, uint16_t reg, uint8_t *p, int cnt)
c4c11dd1 427{
2f7f730a 428 struct i2c_client *client = priv->hdmi;
c4c11dd1
RK		 429 uint8_t buf[cnt+1];
430 int ret;
431
432 buf[0] = REG2ADDR(reg);
433 memcpy(&buf[1], p, cnt);
434
7d2eadc9
JFM		 435 ret = set_page(priv, reg);
436 if (ret < 0)
437 return;
c4c11dd1
RK		 438
439 ret = i2c_master_send(client, buf, cnt + 1);
440 if (ret < 0)
441 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
442}
443
7d2eadc9 444static int
2f7f730a 445reg_read(struct tda998x_priv *priv, uint16_t reg)
e7792ce2
RC		 446{
447 uint8_t val = 0;
7d2eadc9
JFM		 448 int ret;
449
450 ret = reg_read_range(priv, reg, &val, sizeof(val));
451 if (ret < 0)
452 return ret;
e7792ce2
RC		 453 return val;
454}
455
456static void
2f7f730a 457reg_write(struct tda998x_priv *priv, uint16_t reg, uint8_t val)
e7792ce2 458{
2f7f730a 459 struct i2c_client *client = priv->hdmi;
e7792ce2
RC		 460 uint8_t buf[] = {REG2ADDR(reg), val};
461 int ret;
462
7d2eadc9
JFM		 463 ret = set_page(priv, reg);
464 if (ret < 0)
465 return;
e7792ce2 466
704d63f5 467 ret = i2c_master_send(client, buf, sizeof(buf));
e7792ce2
RC		 468 if (ret < 0)
469 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
470}
471
472static void
2f7f730a 473reg_write16(struct tda998x_priv *priv, uint16_t reg, uint16_t val)
e7792ce2 474{
2f7f730a 475 struct i2c_client *client = priv->hdmi;
e7792ce2
RC		 476 uint8_t buf[] = {REG2ADDR(reg), val >> 8, val};
477 int ret;
478
7d2eadc9
JFM		 479 ret = set_page(priv, reg);
480 if (ret < 0)
481 return;
e7792ce2 482
704d63f5 483 ret = i2c_master_send(client, buf, sizeof(buf));
e7792ce2
RC		 484 if (ret < 0)
485 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
486}
487
488static void
2f7f730a 489reg_set(struct tda998x_priv *priv, uint16_t reg, uint8_t val)
e7792ce2 490{
7d2eadc9
JFM		 491 int old_val;
492
493 old_val = reg_read(priv, reg);
494 if (old_val >= 0)
495 reg_write(priv, reg, old_val | val);
e7792ce2
RC		 496}
497
498static void
2f7f730a 499reg_clear(struct tda998x_priv *priv, uint16_t reg, uint8_t val)
e7792ce2 500{
7d2eadc9
JFM		 501 int old_val;
502
503 old_val = reg_read(priv, reg);
504 if (old_val >= 0)
505 reg_write(priv, reg, old_val & ~val);
e7792ce2
RC		 506}
507
508static void
2f7f730a 509tda998x_reset(struct tda998x_priv *priv)
e7792ce2
RC		 510{
511 /* reset audio and i2c master: */
81b53a16 512 reg_write(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER);
e7792ce2 513 msleep(50);
81b53a16 514 reg_write(priv, REG_SOFTRESET, 0);
e7792ce2
RC		 515 msleep(50);
516
517 /* reset transmitter: */
2f7f730a
JFM		 518 reg_set(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
519 reg_clear(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
e7792ce2
RC		 520
521 /* PLL registers common configuration */
2f7f730a
JFM		 522 reg_write(priv, REG_PLL_SERIAL_1, 0x00);
523 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1));
524 reg_write(priv, REG_PLL_SERIAL_3, 0x00);
525 reg_write(priv, REG_SERIALIZER, 0x00);
526 reg_write(priv, REG_BUFFER_OUT, 0x00);
527 reg_write(priv, REG_PLL_SCG1, 0x00);
528 reg_write(priv, REG_AUDIO_DIV, AUDIO_DIV_SERCLK_8);
529 reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
530 reg_write(priv, REG_PLL_SCGN1, 0xfa);
531 reg_write(priv, REG_PLL_SCGN2, 0x00);
532 reg_write(priv, REG_PLL_SCGR1, 0x5b);
533 reg_write(priv, REG_PLL_SCGR2, 0x00);
534 reg_write(priv, REG_PLL_SCG2, 0x10);
bcb2481d
RK		 535
536 /* Write the default value MUX register */
2f7f730a 537 reg_write(priv, REG_MUX_VP_VIP_OUT, 0x24);
e7792ce2
RC		 538}
539
12473b7d
JFM		 540/*
541 * only 2 interrupts may occur: screen plug/unplug and EDID read
542 */
543static irqreturn_t tda998x_irq_thread(int irq, void *data)
544{
545 struct tda998x_priv *priv = data;
546 u8 sta, cec, lvl, flag0, flag1, flag2;
547
548 if (!priv)
549 return IRQ_HANDLED;
550 sta = cec_read(priv, REG_CEC_INTSTATUS);
551 cec = cec_read(priv, REG_CEC_RXSHPDINT);
552 lvl = cec_read(priv, REG_CEC_RXSHPDLEV);
553 flag0 = reg_read(priv, REG_INT_FLAGS_0);
554 flag1 = reg_read(priv, REG_INT_FLAGS_1);
555 flag2 = reg_read(priv, REG_INT_FLAGS_2);
556 DRM_DEBUG_DRIVER(
557 "tda irq sta %02x cec %02x lvl %02x f0 %02x f1 %02x f2 %02x\n",
558 sta, cec, lvl, flag0, flag1, flag2);
559 if ((flag2 & INT_FLAGS_2_EDID_BLK_RD) && priv->wq_edid_wait) {
560 priv->wq_edid_wait = 0;
561 wake_up(&priv->wq_edid);
562 } else if (cec != 0) { /* HPD change */
563 if (priv->encoder && priv->encoder->dev)
564 drm_helper_hpd_irq_event(priv->encoder->dev);
565 }
566 return IRQ_HANDLED;
567}
568
c4c11dd1
RK		 569static uint8_t tda998x_cksum(uint8_t *buf, size_t bytes)
570{
8268bd48 571 int sum = 0;
c4c11dd1
RK		 572
573 while (bytes--)
8268bd48
DV		 574 sum -= *buf++;
575 return sum;
c4c11dd1
RK		 576}
577
578#define HB(x) (x)
579#define PB(x) (HB(2) + 1 + (x))
580
581static void
2f7f730a 582tda998x_write_if(struct tda998x_priv *priv, uint8_t bit, uint16_t addr,
c4c11dd1
RK		 583 uint8_t *buf, size_t size)
584{
585 buf[PB(0)] = tda998x_cksum(buf, size);
586
2f7f730a
JFM		 587 reg_clear(priv, REG_DIP_IF_FLAGS, bit);
588 reg_write_range(priv, addr, buf, size);
589 reg_set(priv, REG_DIP_IF_FLAGS, bit);
c4c11dd1
RK		 590}
591
592static void
2f7f730a 593tda998x_write_aif(struct tda998x_priv *priv, struct tda998x_encoder_params *p)
c4c11dd1 594{
9e541466 595 u8 buf[PB(HDMI_AUDIO_INFOFRAME_SIZE) + 1];
c4c11dd1 596
7288ca07 597 memset(buf, 0, sizeof(buf));
9e541466 598 buf[HB(0)] = HDMI_INFOFRAME_TYPE_AUDIO;
c4c11dd1 599 buf[HB(1)] = 0x01;
9e541466 600 buf[HB(2)] = HDMI_AUDIO_INFOFRAME_SIZE;
c4c11dd1
RK		 601 buf[PB(1)] = p->audio_frame[1] & 0x07; /* CC */
602 buf[PB(2)] = p->audio_frame[2] & 0x1c; /* SF */
603 buf[PB(4)] = p->audio_frame[4];
604 buf[PB(5)] = p->audio_frame[5] & 0xf8; /* DM_INH + LSV */
605
2f7f730a 606 tda998x_write_if(priv, DIP_IF_FLAGS_IF4, REG_IF4_HB0, buf,
c4c11dd1
RK		 607 sizeof(buf));
608}
609
610static void
2f7f730a 611tda998x_write_avi(struct tda998x_priv *priv, struct drm_display_mode *mode)
c4c11dd1 612{
9e541466 613 u8 buf[PB(HDMI_AVI_INFOFRAME_SIZE) + 1];
c4c11dd1
RK		 614
615 memset(buf, 0, sizeof(buf));
9e541466 616 buf[HB(0)] = HDMI_INFOFRAME_TYPE_AVI;
c4c11dd1 617 buf[HB(1)] = 0x02;
9e541466 618 buf[HB(2)] = HDMI_AVI_INFOFRAME_SIZE;
893c3e53 619 buf[PB(1)] = HDMI_SCAN_MODE_UNDERSCAN;
bdf6345b 620 buf[PB(2)] = HDMI_ACTIVE_ASPECT_PICTURE;
893c3e53 621 buf[PB(3)] = HDMI_QUANTIZATION_RANGE_FULL << 2;
c4c11dd1
RK		 622 buf[PB(4)] = drm_match_cea_mode(mode);
623
2f7f730a 624 tda998x_write_if(priv, DIP_IF_FLAGS_IF2, REG_IF2_HB0, buf,
c4c11dd1
RK		 625 sizeof(buf));
626}
627
2f7f730a 628static void tda998x_audio_mute(struct tda998x_priv *priv, bool on)
c4c11dd1
RK		 629{
630 if (on) {
2f7f730a
JFM		 631 reg_set(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
632 reg_clear(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
633 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
c4c11dd1 634 } else {
2f7f730a 635 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
c4c11dd1
RK		 636 }
637}
638
639static void
2f7f730a 640tda998x_configure_audio(struct tda998x_priv *priv,
c4c11dd1
RK		 641 struct drm_display_mode *mode, struct tda998x_encoder_params *p)
642{
85c988bb 643 uint8_t buf[6], clksel_aip, clksel_fs, cts_n, adiv;
c4c11dd1
RK		 644 uint32_t n;
645
646 /* Enable audio ports */
2f7f730a
JFM		 647 reg_write(priv, REG_ENA_AP, p->audio_cfg);
648 reg_write(priv, REG_ENA_ACLK, p->audio_clk_cfg);
c4c11dd1
RK		 649
650 /* Set audio input source */
651 switch (p->audio_format) {
652 case AFMT_SPDIF:
10df1a95
JFM		 653 reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_SPDIF);
654 clksel_aip = AIP_CLKSEL_AIP_SPDIF;
655 clksel_fs = AIP_CLKSEL_FS_FS64SPDIF;
c4c11dd1 656 cts_n = CTS_N_M(3) | CTS_N_K(3);
c4c11dd1
RK		 657 break;
658
659 case AFMT_I2S:
10df1a95
JFM		 660 reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_I2S);
661 clksel_aip = AIP_CLKSEL_AIP_I2S;
662 clksel_fs = AIP_CLKSEL_FS_ACLK;
c4c11dd1 663 cts_n = CTS_N_M(3) | CTS_N_K(3);
c4c11dd1 664 break;
3b28802e
DH		 665
666 default:
667 BUG();
668 return;
c4c11dd1
RK		 669 }
670
2f7f730a 671 reg_write(priv, REG_AIP_CLKSEL, clksel_aip);
a8b517e5
JFM		 672 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT |
673 AIP_CNTRL_0_ACR_MAN); /* auto CTS */
2f7f730a 674 reg_write(priv, REG_CTS_N, cts_n);
c4c11dd1
RK		 675
676 /*
677 * Audio input somehow depends on HDMI line rate which is
678 * related to pixclk. Testing showed that modes with pixclk
679 * >100MHz need a larger divider while <40MHz need the default.
680 * There is no detailed info in the datasheet, so we just
681 * assume 100MHz requires larger divider.
682 */
2470fecc 683 adiv = AUDIO_DIV_SERCLK_8;
c4c11dd1 684 if (mode->clock > 100000)
2470fecc
JFM		 685 adiv++; /* AUDIO_DIV_SERCLK_16 */
686
687 /* S/PDIF asks for a larger divider */
688 if (p->audio_format == AFMT_SPDIF)
689 adiv++; /* AUDIO_DIV_SERCLK_16 or _32 */
690
2f7f730a 691 reg_write(priv, REG_AUDIO_DIV, adiv);
c4c11dd1
RK		 692
693 /*
694 * This is the approximate value of N, which happens to be
695 * the recommended values for non-coherent clocks.
696 */
697 n = 128 * p->audio_sample_rate / 1000;
698
699 /* Write the CTS and N values */
700 buf[0] = 0x44;
701 buf[1] = 0x42;
702 buf[2] = 0x01;
703 buf[3] = n;
704 buf[4] = n >> 8;
705 buf[5] = n >> 16;
2f7f730a 706 reg_write_range(priv, REG_ACR_CTS_0, buf, 6);
c4c11dd1
RK		 707
708 /* Set CTS clock reference */
2f7f730a 709 reg_write(priv, REG_AIP_CLKSEL, clksel_aip | clksel_fs);
c4c11dd1
RK		 710
711 /* Reset CTS generator */
2f7f730a
JFM		 712 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
713 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
c4c11dd1
RK		 714
715 /* Write the channel status */
f0b33b28 716 buf[0] = IEC958_AES0_CON_NOT_COPYRIGHT;
c4c11dd1 717 buf[1] = 0x00;
f0b33b28
JFM		 718 buf[2] = IEC958_AES3_CON_FS_NOTID;
719 buf[3] = IEC958_AES4_CON_ORIGFS_NOTID |
720 IEC958_AES4_CON_MAX_WORDLEN_24;
2f7f730a 721 reg_write_range(priv, REG_CH_STAT_B(0), buf, 4);
c4c11dd1 722
2f7f730a 723 tda998x_audio_mute(priv, true);
73d5e253 724 msleep(20);
2f7f730a 725 tda998x_audio_mute(priv, false);
c4c11dd1
RK		 726
727 /* Write the audio information packet */
2f7f730a 728 tda998x_write_aif(priv, p);
c4c11dd1
RK		 729}
730
e7792ce2
RC		 731/* DRM encoder functions */
732
733static void
734tda998x_encoder_set_config(struct drm_encoder *encoder, void *params)
735{
c4c11dd1
RK		 736 struct tda998x_priv *priv = to_tda998x_priv(encoder);
737 struct tda998x_encoder_params *p = params;
738
739 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(p->swap_a) |
740 (p->mirr_a ? VIP_CNTRL_0_MIRR_A : 0) |
741 VIP_CNTRL_0_SWAP_B(p->swap_b) |
742 (p->mirr_b ? VIP_CNTRL_0_MIRR_B : 0);
743 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(p->swap_c) |
744 (p->mirr_c ? VIP_CNTRL_1_MIRR_C : 0) |
745 VIP_CNTRL_1_SWAP_D(p->swap_d) |
746 (p->mirr_d ? VIP_CNTRL_1_MIRR_D : 0);
747 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(p->swap_e) |
748 (p->mirr_e ? VIP_CNTRL_2_MIRR_E : 0) |
749 VIP_CNTRL_2_SWAP_F(p->swap_f) |
750 (p->mirr_f ? VIP_CNTRL_2_MIRR_F : 0);
751
752 priv->params = *p;
e7792ce2
RC		 753}
754
755static void
756tda998x_encoder_dpms(struct drm_encoder *encoder, int mode)
757{
758 struct tda998x_priv *priv = to_tda998x_priv(encoder);
759
760 /* we only care about on or off: */
761 if (mode != DRM_MODE_DPMS_ON)
762 mode = DRM_MODE_DPMS_OFF;
763
764 if (mode == priv->dpms)
765 return;
766
767 switch (mode) {
768 case DRM_MODE_DPMS_ON:
c4c11dd1 769 /* enable video ports, audio will be enabled later */
2f7f730a
JFM		 770 reg_write(priv, REG_ENA_VP_0, 0xff);
771 reg_write(priv, REG_ENA_VP_1, 0xff);
772 reg_write(priv, REG_ENA_VP_2, 0xff);
e7792ce2 773 /* set muxing after enabling ports: */
2f7f730a
JFM		 774 reg_write(priv, REG_VIP_CNTRL_0, priv->vip_cntrl_0);
775 reg_write(priv, REG_VIP_CNTRL_1, priv->vip_cntrl_1);
776 reg_write(priv, REG_VIP_CNTRL_2, priv->vip_cntrl_2);
e7792ce2
RC		 777 break;
778 case DRM_MODE_DPMS_OFF:
db6aaf4d 779 /* disable video ports */
2f7f730a
JFM		 780 reg_write(priv, REG_ENA_VP_0, 0x00);
781 reg_write(priv, REG_ENA_VP_1, 0x00);
782 reg_write(priv, REG_ENA_VP_2, 0x00);
e7792ce2
RC		 783 break;
784 }
785
786 priv->dpms = mode;
787}
788
789static void
790tda998x_encoder_save(struct drm_encoder *encoder)
791{
792 DBG("");
793}
794
795static void
796tda998x_encoder_restore(struct drm_encoder *encoder)
797{
798 DBG("");
799}
800
801static bool
802tda998x_encoder_mode_fixup(struct drm_encoder *encoder,
803 const struct drm_display_mode *mode,
804 struct drm_display_mode *adjusted_mode)
805{
806 return true;
807}
808
809static int
810tda998x_encoder_mode_valid(struct drm_encoder *encoder,
811 struct drm_display_mode *mode)
812{
92fbdfcd
RK		 813 if (mode->clock > 150000)
814 return MODE_CLOCK_HIGH;
815 if (mode->htotal >= BIT(13))
816 return MODE_BAD_HVALUE;
817 if (mode->vtotal >= BIT(11))
818 return MODE_BAD_VVALUE;
e7792ce2
RC		 819 return MODE_OK;
820}
821
822static void
823tda998x_encoder_mode_set(struct drm_encoder *encoder,
824 struct drm_display_mode *mode,
825 struct drm_display_mode *adjusted_mode)
826{
827 struct tda998x_priv *priv = to_tda998x_priv(encoder);
088d61d1
SH		 828 uint16_t ref_pix, ref_line, n_pix, n_line;
829 uint16_t hs_pix_s, hs_pix_e;
830 uint16_t vs1_pix_s, vs1_pix_e, vs1_line_s, vs1_line_e;
831 uint16_t vs2_pix_s, vs2_pix_e, vs2_line_s, vs2_line_e;
832 uint16_t vwin1_line_s, vwin1_line_e;
833 uint16_t vwin2_line_s, vwin2_line_e;
834 uint16_t de_pix_s, de_pix_e;
e7792ce2
RC		 835 uint8_t reg, div, rep;
836
088d61d1
SH		 837 /*
838 * Internally TDA998x is using ITU-R BT.656 style sync but
839 * we get VESA style sync. TDA998x is using a reference pixel
840 * relative to ITU to sync to the input frame and for output
841 * sync generation. Currently, we are using reference detection
842 * from HS/VS, i.e. REFPIX/REFLINE denote frame start sync point
843 * which is position of rising VS with coincident rising HS.
844 *
845 * Now there is some issues to take care of:
846 * - HDMI data islands require sync-before-active
847 * - TDA998x register values must be > 0 to be enabled
848 * - REFLINE needs an additional offset of +1
849 * - REFPIX needs an addtional offset of +1 for UYUV and +3 for RGB
850 *
851 * So we add +1 to all horizontal and vertical register values,
852 * plus an additional +3 for REFPIX as we are using RGB input only.
e7792ce2 853 */
088d61d1
SH		 854 n_pix = mode->htotal;
855 n_line = mode->vtotal;
856
857 hs_pix_e = mode->hsync_end - mode->hdisplay;
858 hs_pix_s = mode->hsync_start - mode->hdisplay;
859 de_pix_e = mode->htotal;
860 de_pix_s = mode->htotal - mode->hdisplay;
861 ref_pix = 3 + hs_pix_s;
862
179f1aa4
SH		 863 /*
864 * Attached LCD controllers may generate broken sync. Allow
865 * those to adjust the position of the rising VS edge by adding
866 * HSKEW to ref_pix.
867 */
868 if (adjusted_mode->flags & DRM_MODE_FLAG_HSKEW)
869 ref_pix += adjusted_mode->hskew;
870
088d61d1
SH		 871 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0) {
872 ref_line = 1 + mode->vsync_start - mode->vdisplay;
873 vwin1_line_s = mode->vtotal - mode->vdisplay - 1;
874 vwin1_line_e = vwin1_line_s + mode->vdisplay;
875 vs1_pix_s = vs1_pix_e = hs_pix_s;
876 vs1_line_s = mode->vsync_start - mode->vdisplay;
877 vs1_line_e = vs1_line_s +
878 mode->vsync_end - mode->vsync_start;
879 vwin2_line_s = vwin2_line_e = 0;
880 vs2_pix_s = vs2_pix_e = 0;
881 vs2_line_s = vs2_line_e = 0;
882 } else {
883 ref_line = 1 + (mode->vsync_start - mode->vdisplay)/2;
884 vwin1_line_s = (mode->vtotal - mode->vdisplay)/2;
885 vwin1_line_e = vwin1_line_s + mode->vdisplay/2;
886 vs1_pix_s = vs1_pix_e = hs_pix_s;
887 vs1_line_s = (mode->vsync_start - mode->vdisplay)/2;
888 vs1_line_e = vs1_line_s +
889 (mode->vsync_end - mode->vsync_start)/2;
890 vwin2_line_s = vwin1_line_s + mode->vtotal/2;
891 vwin2_line_e = vwin2_line_s + mode->vdisplay/2;
892 vs2_pix_s = vs2_pix_e = hs_pix_s + mode->htotal/2;
893 vs2_line_s = vs1_line_s + mode->vtotal/2 ;
894 vs2_line_e = vs2_line_s +
895 (mode->vsync_end - mode->vsync_start)/2;
896 }
e7792ce2
RC		 897
898 div = 148500 / mode->clock;
3ae471f7
JFM		 899 if (div != 0) {
900 div--;
901 if (div > 3)
902 div = 3;
903 }
e7792ce2 904
e7792ce2 905 /* mute the audio FIFO: */
2f7f730a 906 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
e7792ce2
RC		 907
908 /* set HDMI HDCP mode off: */
81b53a16 909 reg_write(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS);
2f7f730a
JFM		 910 reg_clear(priv, REG_TX33, TX33_HDMI);
911 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0));
e7792ce2 912
e7792ce2 913 /* no pre-filter or interpolator: */
2f7f730a 914 reg_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) |
e7792ce2 915 HVF_CNTRL_0_INTPOL(0));
2f7f730a
JFM		 916 reg_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0));
917 reg_write(priv, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) |
e7792ce2 918 VIP_CNTRL_4_BLC(0));
e7792ce2 919
2f7f730a 920 reg_clear(priv, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ);
a8b517e5
JFM		 921 reg_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR |
922 PLL_SERIAL_3_SRL_DE);
2f7f730a
JFM		 923 reg_write(priv, REG_SERIALIZER, 0);
924 reg_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0));
e7792ce2
RC		 925
926 /* TODO enable pixel repeat for pixel rates less than 25Msamp/s */
927 rep = 0;
2f7f730a
JFM		 928 reg_write(priv, REG_RPT_CNTRL, 0);
929 reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) |
e7792ce2
RC		 930 SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
931
2f7f730a 932 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) |
e7792ce2
RC		 933 PLL_SERIAL_2_SRL_PR(rep));
934
e7792ce2 935 /* set color matrix bypass flag: */
81b53a16
JFM		 936 reg_write(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP |
937 MAT_CONTRL_MAT_SC(1));
e7792ce2
RC		 938
939 /* set BIAS tmds value: */
2f7f730a 940 reg_write(priv, REG_ANA_GENERAL, 0x09);
e7792ce2 941
088d61d1
SH		 942 /*
943 * Sync on rising HSYNC/VSYNC
944 */
81b53a16 945 reg = VIP_CNTRL_3_SYNC_HS;
088d61d1
SH		 946
947 /*
948 * TDA19988 requires high-active sync at input stage,
949 * so invert low-active sync provided by master encoder here
950 */
951 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
81b53a16 952 reg |= VIP_CNTRL_3_H_TGL;
e7792ce2 953 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
81b53a16
JFM		 954 reg |= VIP_CNTRL_3_V_TGL;
955 reg_write(priv, REG_VIP_CNTRL_3, reg);
2f7f730a
JFM		 956
957 reg_write(priv, REG_VIDFORMAT, 0x00);
958 reg_write16(priv, REG_REFPIX_MSB, ref_pix);
959 reg_write16(priv, REG_REFLINE_MSB, ref_line);
960 reg_write16(priv, REG_NPIX_MSB, n_pix);
961 reg_write16(priv, REG_NLINE_MSB, n_line);
962 reg_write16(priv, REG_VS_LINE_STRT_1_MSB, vs1_line_s);
963 reg_write16(priv, REG_VS_PIX_STRT_1_MSB, vs1_pix_s);
964 reg_write16(priv, REG_VS_LINE_END_1_MSB, vs1_line_e);
965 reg_write16(priv, REG_VS_PIX_END_1_MSB, vs1_pix_e);
966 reg_write16(priv, REG_VS_LINE_STRT_2_MSB, vs2_line_s);
967 reg_write16(priv, REG_VS_PIX_STRT_2_MSB, vs2_pix_s);
968 reg_write16(priv, REG_VS_LINE_END_2_MSB, vs2_line_e);
969 reg_write16(priv, REG_VS_PIX_END_2_MSB, vs2_pix_e);
970 reg_write16(priv, REG_HS_PIX_START_MSB, hs_pix_s);
971 reg_write16(priv, REG_HS_PIX_STOP_MSB, hs_pix_e);
972 reg_write16(priv, REG_VWIN_START_1_MSB, vwin1_line_s);
973 reg_write16(priv, REG_VWIN_END_1_MSB, vwin1_line_e);
974 reg_write16(priv, REG_VWIN_START_2_MSB, vwin2_line_s);
975 reg_write16(priv, REG_VWIN_END_2_MSB, vwin2_line_e);
976 reg_write16(priv, REG_DE_START_MSB, de_pix_s);
977 reg_write16(priv, REG_DE_STOP_MSB, de_pix_e);
e7792ce2
RC		 978
979 if (priv->rev == TDA19988) {
980 /* let incoming pixels fill the active space (if any) */
2f7f730a 981 reg_write(priv, REG_ENABLE_SPACE, 0x00);
e7792ce2
RC		 982 }
983
81b53a16
JFM		 984 /*
985 * Always generate sync polarity relative to input sync and
986 * revert input stage toggled sync at output stage
987 */
988 reg = TBG_CNTRL_1_DWIN_DIS | TBG_CNTRL_1_TGL_EN;
989 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
990 reg |= TBG_CNTRL_1_H_TGL;
991 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
992 reg |= TBG_CNTRL_1_V_TGL;
993 reg_write(priv, REG_TBG_CNTRL_1, reg);
994
e7792ce2 995 /* must be last register set: */
81b53a16 996 reg_write(priv, REG_TBG_CNTRL_0, 0);
c4c11dd1
RK		 997
998 /* Only setup the info frames if the sink is HDMI */
999 if (priv->is_hdmi_sink) {
1000 /* We need to turn HDMI HDCP stuff on to get audio through */
81b53a16
JFM		 1001 reg &= ~TBG_CNTRL_1_DWIN_DIS;
1002 reg_write(priv, REG_TBG_CNTRL_1, reg);
2f7f730a
JFM		 1003 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1));
1004 reg_set(priv, REG_TX33, TX33_HDMI);
c4c11dd1 1005
2f7f730a 1006 tda998x_write_avi(priv, adjusted_mode);
c4c11dd1
RK		 1007
1008 if (priv->params.audio_cfg)
2f7f730a 1009 tda998x_configure_audio(priv, adjusted_mode,
c4c11dd1
RK		 1010 &priv->params);
1011 }
e7792ce2
RC		 1012}
1013
1014static enum drm_connector_status
1015tda998x_encoder_detect(struct drm_encoder *encoder,
1016 struct drm_connector *connector)
1017{
2f7f730a
JFM		 1018 struct tda998x_priv *priv = to_tda998x_priv(encoder);
1019 uint8_t val = cec_read(priv, REG_CEC_RXSHPDLEV);
1020
e7792ce2
RC		 1021 return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected :
1022 connector_status_disconnected;
1023}
1024
1025static int
1026read_edid_block(struct drm_encoder *encoder, uint8_t *buf, int blk)
1027{
2f7f730a 1028 struct tda998x_priv *priv = to_tda998x_priv(encoder);
e7792ce2
RC		 1029 uint8_t offset, segptr;
1030 int ret, i;
1031
e7792ce2
RC		 1032 offset = (blk & 1) ? 128 : 0;
1033 segptr = blk / 2;
1034
2f7f730a
JFM		 1035 reg_write(priv, REG_DDC_ADDR, 0xa0);
1036 reg_write(priv, REG_DDC_OFFS, offset);
1037 reg_write(priv, REG_DDC_SEGM_ADDR, 0x60);
1038 reg_write(priv, REG_DDC_SEGM, segptr);
e7792ce2
RC		 1039
1040 /* enable reading EDID: */
12473b7d 1041 priv->wq_edid_wait = 1;
2f7f730a 1042 reg_write(priv, REG_EDID_CTRL, 0x1);
e7792ce2
RC		 1043
1044 /* flag must be cleared by sw: */
2f7f730a 1045 reg_write(priv, REG_EDID_CTRL, 0x0);
e7792ce2
RC		 1046
1047 /* wait for block read to complete: */
12473b7d
JFM		 1048 if (priv->hdmi->irq) {
1049 i = wait_event_timeout(priv->wq_edid,
1050 !priv->wq_edid_wait,
1051 msecs_to_jiffies(100));
1052 if (i < 0) {
5e7fe2fe 1053 dev_err(&priv->hdmi->dev, "read edid wait err %d\n", i);
12473b7d
JFM		 1054 return i;
1055 }
1056 } else {
713456db
RK		 1057 for (i = 100; i > 0; i--) {
1058 msleep(1);
12473b7d
JFM		 1059 ret = reg_read(priv, REG_INT_FLAGS_2);
1060 if (ret < 0)
1061 return ret;
1062 if (ret & INT_FLAGS_2_EDID_BLK_RD)
1063 break;
1064 }
e7792ce2
RC		 1065 }
1066
12473b7d 1067 if (i == 0) {
5e7fe2fe 1068 dev_err(&priv->hdmi->dev, "read edid timeout\n");
e7792ce2 1069 return -ETIMEDOUT;
12473b7d 1070 }
e7792ce2 1071
2f7f730a 1072 ret = reg_read_range(priv, REG_EDID_DATA_0, buf, EDID_LENGTH);
e7792ce2 1073 if (ret != EDID_LENGTH) {
5e7fe2fe
RK		 1074 dev_err(&priv->hdmi->dev, "failed to read edid block %d: %d\n",
1075 blk, ret);
e7792ce2
RC		 1076 return ret;
1077 }
1078
e7792ce2
RC		 1079 return 0;
1080}
1081
1082static uint8_t *
1083do_get_edid(struct drm_encoder *encoder)
1084{
063b472f 1085 struct tda998x_priv *priv = to_tda998x_priv(encoder);
704d63f5 1086 int j, valid_extensions = 0;
e7792ce2
RC		 1087 uint8_t *block, *new;
1088 bool print_bad_edid = drm_debug & DRM_UT_KMS;
1089
1090 if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
1091 return NULL;
1092
063b472f 1093 if (priv->rev == TDA19988)
2f7f730a 1094 reg_clear(priv, REG_TX4, TX4_PD_RAM);
063b472f 1095
e7792ce2
RC		 1096 /* base block fetch */
1097 if (read_edid_block(encoder, block, 0))
1098 goto fail;
1099
1100 if (!drm_edid_block_valid(block, 0, print_bad_edid))
1101 goto fail;
1102
1103 /* if there's no extensions, we're done */
1104 if (block[0x7e] == 0)
063b472f 1105 goto done;
e7792ce2
RC		 1106
1107 new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL);
1108 if (!new)
1109 goto fail;
1110 block = new;
1111
1112 for (j = 1; j <= block[0x7e]; j++) {
1113 uint8_t *ext_block = block + (valid_extensions + 1) * EDID_LENGTH;
1114 if (read_edid_block(encoder, ext_block, j))
1115 goto fail;
1116
1117 if (!drm_edid_block_valid(ext_block, j, print_bad_edid))
1118 goto fail;
1119
1120 valid_extensions++;
1121 }
1122
1123 if (valid_extensions != block[0x7e]) {
1124 block[EDID_LENGTH-1] += block[0x7e] - valid_extensions;
1125 block[0x7e] = valid_extensions;
1126 new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1127 if (!new)
1128 goto fail;
1129 block = new;
1130 }
1131
063b472f
RK		 1132done:
1133 if (priv->rev == TDA19988)
2f7f730a 1134 reg_set(priv, REG_TX4, TX4_PD_RAM);
063b472f 1135
e7792ce2
RC		 1136 return block;
1137
1138fail:
063b472f 1139 if (priv->rev == TDA19988)
2f7f730a 1140 reg_set(priv, REG_TX4, TX4_PD_RAM);
5e7fe2fe 1141 dev_warn(&priv->hdmi->dev, "failed to read EDID\n");
e7792ce2
RC		 1142 kfree(block);
1143 return NULL;
1144}
1145
1146static int
1147tda998x_encoder_get_modes(struct drm_encoder *encoder,
1148 struct drm_connector *connector)
1149{
c4c11dd1 1150 struct tda998x_priv *priv = to_tda998x_priv(encoder);
e7792ce2
RC		 1151 struct edid *edid = (struct edid *)do_get_edid(encoder);
1152 int n = 0;
1153
1154 if (edid) {
1155 drm_mode_connector_update_edid_property(connector, edid);
1156 n = drm_add_edid_modes(connector, edid);
c4c11dd1 1157 priv->is_hdmi_sink = drm_detect_hdmi_monitor(edid);
e7792ce2
RC		 1158 kfree(edid);
1159 }
1160
1161 return n;
1162}
1163
1164static int
1165tda998x_encoder_create_resources(struct drm_encoder *encoder,
1166 struct drm_connector *connector)
1167{
12473b7d
JFM		 1168 struct tda998x_priv *priv = to_tda998x_priv(encoder);
1169
1170 if (priv->hdmi->irq)
1171 connector->polled = DRM_CONNECTOR_POLL_HPD;
1172 else
1173 connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1174 DRM_CONNECTOR_POLL_DISCONNECT;
e7792ce2
RC		 1175 return 0;
1176}
1177
1178static int
1179tda998x_encoder_set_property(struct drm_encoder *encoder,
1180 struct drm_connector *connector,
1181 struct drm_property *property,
1182 uint64_t val)
1183{
1184 DBG("");
1185 return 0;
1186}
1187
1188static void
1189tda998x_encoder_destroy(struct drm_encoder *encoder)
1190{
1191 struct tda998x_priv *priv = to_tda998x_priv(encoder);
12473b7d
JFM		 1192
1193 /* disable all IRQs and free the IRQ handler */
1194 cec_write(priv, REG_CEC_RXSHPDINTENA, 0);
1195 reg_clear(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
1196 if (priv->hdmi->irq)
1197 free_irq(priv->hdmi->irq, priv);
1198
fc275a74
JFM		 1199 if (priv->cec)
1200 i2c_unregister_device(priv->cec);
2e48cecb 1201 drm_i2c_encoder_destroy(encoder);
e7792ce2
RC		 1202 kfree(priv);
1203}
1204
1205static struct drm_encoder_slave_funcs tda998x_encoder_funcs = {
1206 .set_config = tda998x_encoder_set_config,
1207 .destroy = tda998x_encoder_destroy,
1208 .dpms = tda998x_encoder_dpms,
1209 .save = tda998x_encoder_save,
1210 .restore = tda998x_encoder_restore,
1211 .mode_fixup = tda998x_encoder_mode_fixup,
1212 .mode_valid = tda998x_encoder_mode_valid,
1213 .mode_set = tda998x_encoder_mode_set,
1214 .detect = tda998x_encoder_detect,
1215 .get_modes = tda998x_encoder_get_modes,
1216 .create_resources = tda998x_encoder_create_resources,
1217 .set_property = tda998x_encoder_set_property,
1218};
1219
1220/* I2C driver functions */
1221
1222static int
1223tda998x_probe(struct i2c_client *client, const struct i2c_device_id *id)
1224{
1225 return 0;
1226}
1227
1228static int
1229tda998x_remove(struct i2c_client *client)
1230{
1231 return 0;
1232}
1233
1234static int
1235tda998x_encoder_init(struct i2c_client *client,
1236 struct drm_device *dev,
1237 struct drm_encoder_slave *encoder_slave)
1238{
e7792ce2 1239 struct tda998x_priv *priv;
0d44ea19
JFM		 1240 struct device_node *np = client->dev.of_node;
1241 u32 video;
fb7544d7 1242 int rev_lo, rev_hi, ret;
e7792ce2
RC		 1243
1244 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1245 if (!priv)
1246 return -ENOMEM;
1247
5e74c22c
RK		 1248 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3);
1249 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1);
1250 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5);
1251
2eb4c7b1 1252 priv->current_page = 0xff;
2f7f730a 1253 priv->hdmi = client;
e7792ce2 1254 priv->cec = i2c_new_dummy(client->adapter, 0x34);
71c68c4f
DJ		 1255 if (!priv->cec) {
1256 kfree(priv);
6ae668cc 1257 return -ENODEV;
71c68c4f 1258 }
12473b7d
JFM		 1259
1260 priv->encoder = &encoder_slave->base;
e7792ce2
RC		 1261 priv->dpms = DRM_MODE_DPMS_OFF;
1262
1263 encoder_slave->slave_priv = priv;
1264 encoder_slave->slave_funcs = &tda998x_encoder_funcs;
1265
1266 /* wake up the device: */
2f7f730a 1267 cec_write(priv, REG_CEC_ENAMODS,
e7792ce2
RC		 1268 CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI);
1269
2f7f730a 1270 tda998x_reset(priv);
e7792ce2
RC		 1271
1272 /* read version: */
fb7544d7
RK		 1273 rev_lo = reg_read(priv, REG_VERSION_LSB);
1274 rev_hi = reg_read(priv, REG_VERSION_MSB);
1275 if (rev_lo < 0 || rev_hi < 0) {
1276 ret = rev_lo < 0 ? rev_lo : rev_hi;
7d2eadc9 1277 goto fail;
fb7544d7
RK		 1278 }
1279
1280 priv->rev = rev_lo | rev_hi << 8;
e7792ce2
RC		 1281
1282 /* mask off feature bits: */
1283 priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */
1284
1285 switch (priv->rev) {
b728fab7
JFM		 1286 case TDA9989N2:
1287 dev_info(&client->dev, "found TDA9989 n2");
1288 break;
1289 case TDA19989:
1290 dev_info(&client->dev, "found TDA19989");
1291 break;
1292 case TDA19989N2:
1293 dev_info(&client->dev, "found TDA19989 n2");
1294 break;
1295 case TDA19988:
1296 dev_info(&client->dev, "found TDA19988");
1297 break;
e7792ce2 1298 default:
b728fab7
JFM		 1299 dev_err(&client->dev, "found unsupported device: %04x\n",
1300 priv->rev);
e7792ce2
RC		 1301 goto fail;
1302 }
1303
1304 /* after reset, enable DDC: */
2f7f730a 1305 reg_write(priv, REG_DDC_DISABLE, 0x00);
e7792ce2
RC		 1306
1307 /* set clock on DDC channel: */
2f7f730a 1308 reg_write(priv, REG_TX3, 39);
e7792ce2
RC		 1309
1310 /* if necessary, disable multi-master: */
1311 if (priv->rev == TDA19989)
2f7f730a 1312 reg_set(priv, REG_I2C_MASTER, I2C_MASTER_DIS_MM);
e7792ce2 1313
2f7f730a 1314 cec_write(priv, REG_CEC_FRO_IM_CLK_CTRL,
e7792ce2
RC		 1315 CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL);
1316
12473b7d
JFM		 1317 /* initialize the optional IRQ */
1318 if (client->irq) {
1319 int irqf_trigger;
1320
1321 /* init read EDID waitqueue */
1322 init_waitqueue_head(&priv->wq_edid);
1323
1324 /* clear pending interrupts */
1325 reg_read(priv, REG_INT_FLAGS_0);
1326 reg_read(priv, REG_INT_FLAGS_1);
1327 reg_read(priv, REG_INT_FLAGS_2);
1328
1329 irqf_trigger =
1330 irqd_get_trigger_type(irq_get_irq_data(client->irq));
1331 ret = request_threaded_irq(client->irq, NULL,
1332 tda998x_irq_thread,
1333 irqf_trigger | IRQF_ONESHOT,
1334 "tda998x", priv);
1335 if (ret) {
1336 dev_err(&client->dev,
1337 "failed to request IRQ#%u: %d\n",
1338 client->irq, ret);
1339 goto fail;
1340 }
1341
1342 /* enable HPD irq */
1343 cec_write(priv, REG_CEC_RXSHPDINTENA, CEC_RXSHPDLEV_HPD);
1344 }
1345
e4782627
JFM		 1346 /* enable EDID read irq: */
1347 reg_set(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
1348
0d44ea19
JFM		 1349 if (!np)
1350 return 0; /* non-DT */
1351
1352 /* get the optional video properties */
1353 ret = of_property_read_u32(np, "video-ports", &video);
1354 if (ret == 0) {
1355 priv->vip_cntrl_0 = video >> 16;
1356 priv->vip_cntrl_1 = video >> 8;
1357 priv->vip_cntrl_2 = video;
1358 }
1359
e7792ce2
RC		 1360 return 0;
1361
1362fail:
1363 /* if encoder_init fails, the encoder slave is never registered,
1364 * so cleanup here:
1365 */
1366 if (priv->cec)
1367 i2c_unregister_device(priv->cec);
1368 kfree(priv);
1369 encoder_slave->slave_priv = NULL;
1370 encoder_slave->slave_funcs = NULL;
1371 return -ENXIO;
1372}
1373
0d44ea19
JFM		 1374#ifdef CONFIG_OF
1375static const struct of_device_id tda998x_dt_ids[] = {
1376 { .compatible = "nxp,tda998x", },
1377 { }
1378};
1379MODULE_DEVICE_TABLE(of, tda998x_dt_ids);
1380#endif
1381
e7792ce2
RC		 1382static struct i2c_device_id tda998x_ids[] = {
1383 { "tda998x", 0 },
1384 { }
1385};
1386MODULE_DEVICE_TABLE(i2c, tda998x_ids);
1387
1388static struct drm_i2c_encoder_driver tda998x_driver = {
1389 .i2c_driver = {
1390 .probe = tda998x_probe,
1391 .remove = tda998x_remove,
1392 .driver = {
1393 .name = "tda998x",
0d44ea19 1394 .of_match_table = of_match_ptr(tda998x_dt_ids),
e7792ce2
RC		 1395 },
1396 .id_table = tda998x_ids,
1397 },
1398 .encoder_init = tda998x_encoder_init,
1399};
1400
1401/* Module initialization */
1402
1403static int __init
1404tda998x_init(void)
1405{
1406 DBG("");
1407 return drm_i2c_encoder_register(THIS_MODULE, &tda998x_driver);
1408}
1409
1410static void __exit
1411tda998x_exit(void)
1412{
1413 DBG("");
1414 drm_i2c_encoder_unregister(&tda998x_driver);
1415}
1416
1417MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1418MODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder");
1419MODULE_LICENSE("GPL");
1420
1421module_init(tda998x_init);
1422module_exit(tda998x_exit);
Linux 6.x block layer and io_uring tree(s)