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Merge tag 'arm-fixes-6.11-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
[linux-2.6-block.git] / drivers / gpu / drm / gma500 / psb_drv.h
CommitLineData
a61127c2 1/* SPDX-License-Identifier: GPL-2.0-only */
5c49fd3a
AC		 2/**************************************************************************
3 * Copyright (c) 2007-2011, Intel Corporation.
4 * All Rights Reserved.
5 *
5c49fd3a
AC		 6 **************************************************************************/
7
8#ifndef _PSB_DRV_H_
9#define _PSB_DRV_H_
10
11#include <linux/kref.h>
0edf6813 12#include <linux/mm_types.h>
5c49fd3a 13
51474335 14#include <drm/drm_device.h>
d825c565 15
5c49fd3a 16#include "gtt.h"
0c7b178a 17#include "intel_bios.h"
ac1b01b0 18#include "mmu.h"
0c7b178a
SR		 19#include "oaktrail.h"
20#include "opregion.h"
21#include "power.h"
22#include "psb_intel_drv.h"
23#include "psb_reg.h"
5c49fd3a 24
f90cd811 25#define DRIVER_AUTHOR "Alan Cox <alan@linux.intel.com> and others"
f90cd811
AB		 26
27#define DRIVER_NAME "gma500"
28#define DRIVER_DESC "DRM driver for the Intel GMA500, GMA600, GMA3600, GMA3650"
29#define DRIVER_DATE "20140314"
30
31#define DRIVER_MAJOR 1
32#define DRIVER_MINOR 0
33#define DRIVER_PATCHLEVEL 0
34
5c49fd3a
AC		 35/* Append new drm mode definition here, align with libdrm definition */
36#define DRM_MODE_SCALE_NO_SCALE 2
37
a2c68495
TZ		 38#define IS_PSB(drm) ((to_pci_dev((drm)->dev)->device & 0xfffe) == 0x8108)
39#define IS_MRST(drm) ((to_pci_dev((drm)->dev)->device & 0xfff0) == 0x4100)
a2c68495 40#define IS_CDV(drm) ((to_pci_dev((drm)->dev)->device & 0xfff0) == 0x0be0)
5c49fd3a 41
9083eb38 42/* Hardware offsets */
5c49fd3a
AC		 43#define PSB_VDC_OFFSET 0x00000000
44#define PSB_VDC_SIZE 0x000080000
45#define MRST_MMIO_SIZE 0x0000C0000
5c49fd3a
AC		 46#define PSB_SGX_SIZE 0x8000
47#define PSB_SGX_OFFSET 0x00040000
48#define MRST_SGX_OFFSET 0x00080000
9083eb38
AB		 49
50/* PCI resource identifiers */
5c49fd3a 51#define PSB_MMIO_RESOURCE 0
2657929d 52#define PSB_AUX_RESOURCE 0
5c49fd3a
AC		 53#define PSB_GATT_RESOURCE 2
54#define PSB_GTT_RESOURCE 3
9083eb38
AB		 55
56/* PCI configuration */
5c49fd3a
AC		 57#define PSB_GMCH_CTRL 0x52
58#define PSB_BSM 0x5C
59#define _PSB_GMCH_ENABLED 0x4
60#define PSB_PGETBL_CTL 0x2020
61#define _PSB_PGETBL_ENABLED 0x00000001
62#define PSB_SGX_2D_SLAVE_PORT 0x4000
5a52b1f2 63#define PSB_LPC_GBA 0x44
5c49fd3a 64
9083eb38 65/* TODO: To get rid of */
5c49fd3a
AC		 66#define PSB_TT_PRIV0_LIMIT (256*1024*1024)
67#define PSB_TT_PRIV0_PLIMIT (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT)
68
9083eb38 69/* SGX side MMU definitions (these can probably go) */
5c49fd3a 70
9083eb38 71/* Flags for external memory type field */
5c49fd3a
AC		 72#define PSB_MMU_CACHED_MEMORY 0x0001 /* Bind to MMU only */
73#define PSB_MMU_RO_MEMORY 0x0002 /* MMU RO memory */
74#define PSB_MMU_WO_MEMORY 0x0004 /* MMU WO memory */
9083eb38
AB		 75
76/* PTE's and PDE's */
5c49fd3a
AC		 77#define PSB_PDE_MASK 0x003FFFFF
78#define PSB_PDE_SHIFT 22
79#define PSB_PTE_SHIFT 12
9083eb38
AB		 80
81/* Cache control */
5c49fd3a
AC		 82#define PSB_PTE_VALID 0x0001 /* PTE / PDE valid */
83#define PSB_PTE_WO 0x0002 /* Write only */
84#define PSB_PTE_RO 0x0004 /* Read only */
85#define PSB_PTE_CACHED 0x0008 /* CPU cache coherent */
86
9083eb38 87/* VDC registers and bits */
5c49fd3a
AC		 88#define PSB_MSVDX_CLOCKGATING 0x2064
89#define PSB_TOPAZ_CLOCKGATING 0x2068
90#define PSB_HWSTAM 0x2098
91#define PSB_INSTPM 0x20C0
92#define PSB_INT_IDENTITY_R 0x20A4
d839ede4 93#define _PSB_IRQ_ASLE (1<<0)
5c49fd3a
AC		 94#define _MDFLD_PIPEC_EVENT_FLAG (1<<2)
95#define _MDFLD_PIPEC_VBLANK_FLAG (1<<3)
96#define _PSB_DPST_PIPEB_FLAG (1<<4)
97#define _MDFLD_PIPEB_EVENT_FLAG (1<<4)
98#define _PSB_VSYNC_PIPEB_FLAG (1<<5)
99#define _PSB_DPST_PIPEA_FLAG (1<<6)
100#define _PSB_PIPEA_EVENT_FLAG (1<<6)
101#define _PSB_VSYNC_PIPEA_FLAG (1<<7)
68cb638f 102#define _PSB_IRQ_DISP_HOTSYNC (1<<17)
5c49fd3a
AC		 103#define _PSB_IRQ_SGX_FLAG (1<<18)
104#define _PSB_IRQ_MSVDX_FLAG (1<<19)
105#define _LNC_IRQ_TOPAZ_FLAG (1<<20)
106
700e59f6
PJ		 107#define _PSB_PIPE_EVENT_FLAG (_PSB_VSYNC_PIPEA_FLAG | \
108 _PSB_VSYNC_PIPEB_FLAG)
109
5c49fd3a
AC		 110#define PSB_INT_IDENTITY_R 0x20A4
111#define PSB_INT_MASK_R 0x20A8
112#define PSB_INT_ENABLE_R 0x20A0
113
114#define _PSB_MMU_ER_MASK 0x0001FF00
115#define _PSB_MMU_ER_HOST (1 << 16)
116#define GPIOA 0x5010
117#define GPIOB 0x5014
118#define GPIOC 0x5018
119#define GPIOD 0x501c
120#define GPIOE 0x5020
121#define GPIOF 0x5024
122#define GPIOG 0x5028
123#define GPIOH 0x502c
124#define GPIO_CLOCK_DIR_MASK (1 << 0)
125#define GPIO_CLOCK_DIR_IN (0 << 1)
126#define GPIO_CLOCK_DIR_OUT (1 << 1)
127#define GPIO_CLOCK_VAL_MASK (1 << 2)
128#define GPIO_CLOCK_VAL_OUT (1 << 3)
129#define GPIO_CLOCK_VAL_IN (1 << 4)
130#define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
131#define GPIO_DATA_DIR_MASK (1 << 8)
132#define GPIO_DATA_DIR_IN (0 << 9)
133#define GPIO_DATA_DIR_OUT (1 << 9)
134#define GPIO_DATA_VAL_MASK (1 << 10)
135#define GPIO_DATA_VAL_OUT (1 << 11)
136#define GPIO_DATA_VAL_IN (1 << 12)
137#define GPIO_DATA_PULLUP_DISABLE (1 << 13)
138
139#define VCLK_DIVISOR_VGA0 0x6000
140#define VCLK_DIVISOR_VGA1 0x6004
141#define VCLK_POST_DIV 0x6010
142
143#define PSB_COMM_2D (PSB_ENGINE_2D << 4)
144#define PSB_COMM_3D (PSB_ENGINE_3D << 4)
145#define PSB_COMM_TA (PSB_ENGINE_TA << 4)
146#define PSB_COMM_HP (PSB_ENGINE_HP << 4)
147#define PSB_COMM_USER_IRQ (1024 >> 2)
148#define PSB_COMM_USER_IRQ_LOST (PSB_COMM_USER_IRQ + 1)
149#define PSB_COMM_FW (2048 >> 2)
150
151#define PSB_UIRQ_VISTEST 1
152#define PSB_UIRQ_OOM_REPLY 2
153#define PSB_UIRQ_FIRE_TA_REPLY 3
154#define PSB_UIRQ_FIRE_RASTER_REPLY 4
155
156#define PSB_2D_SIZE (256*1024*1024)
157#define PSB_MAX_RELOC_PAGES 1024
158
159#define PSB_LOW_REG_OFFS 0x0204
160#define PSB_HIGH_REG_OFFS 0x0600
161
162#define PSB_NUM_VBLANKS 2
163
bfd8303a 164#define PSB_WATCHDOG_DELAY (HZ * 2)
5c49fd3a 165
1f90b123
HG		 166#define PSB_MAX_BRIGHTNESS 100
167
5c49fd3a
AC		 168#define PSB_PWR_STATE_ON 1
169#define PSB_PWR_STATE_OFF 2
170
171#define PSB_PMPOLICY_NOPM 0
172#define PSB_PMPOLICY_CLOCKGATING 1
173#define PSB_PMPOLICY_POWERDOWN 2
174
175#define PSB_PMSTATE_POWERUP 0
176#define PSB_PMSTATE_CLOCKGATED 1
177#define PSB_PMSTATE_POWERDOWN 2
178#define PSB_PCIx_MSI_ADDR_LOC 0x94
179#define PSB_PCIx_MSI_DATA_LOC 0x98
180
181/* Medfield crystal settings */
182#define KSEL_CRYSTAL_19 1
183#define KSEL_BYPASS_19 5
184#define KSEL_BYPASS_25 6
185#define KSEL_BYPASS_83_100 7
186
187struct opregion_header;
188struct opregion_acpi;
189struct opregion_swsci;
190struct opregion_asle;
191
192struct psb_intel_opregion {
193 struct opregion_header *header;
194 struct opregion_acpi *acpi;
195 struct opregion_swsci *swsci;
196 struct opregion_asle *asle;
1fb28e9e 197 void *vbt;
d839ede4 198 u32 __iomem *lid_state;
778e26de 199 struct work_struct asle_work;
5c49fd3a
AC		 200};
201
5736995b
PJ		 202struct sdvo_device_mapping {
203 u8 initialized;
204 u8 dvo_port;
205 u8 slave_addr;
206 u8 dvo_wiring;
207 u8 i2c_pin;
208 u8 i2c_speed;
209 u8 ddc_pin;
210};
211
5c0c1d50
PJ		 212struct intel_gmbus {
213 struct i2c_adapter adapter;
214 struct i2c_adapter *force_bit;
215 u32 reg0;
216};
217
9083eb38 218/* Register offset maps */
8512e074
AC		 219struct psb_offset {
220 u32 fp0;
221 u32 fp1;
222 u32 cntr;
223 u32 conf;
224 u32 src;
225 u32 dpll;
226 u32 dpll_md;
227 u32 htotal;
228 u32 hblank;
229 u32 hsync;
230 u32 vtotal;
231 u32 vblank;
232 u32 vsync;
233 u32 stride;
234 u32 size;
235 u32 pos;
236 u32 surf;
237 u32 addr;
238 u32 base;
239 u32 status;
240 u32 linoff;
241 u32 tileoff;
242 u32 palette;
243};
244
648a8e34
AC		 245/*
246 * Register save state. This is used to hold the context when the
247 * device is powered off. In the case of Oaktrail this can (but does not
248 * yet) include screen blank. Operations occuring during the save
249 * update the register cache instead.
250 */
6256304b 251
9083eb38 252/* Common status for pipes */
6256304b
AC		 253struct psb_pipe {
254 u32 fp0;
255 u32 fp1;
256 u32 cntr;
257 u32 conf;
258 u32 src;
259 u32 dpll;
260 u32 dpll_md;
261 u32 htotal;
262 u32 hblank;
263 u32 hsync;
264 u32 vtotal;
265 u32 vblank;
266 u32 vsync;
267 u32 stride;
268 u32 size;
269 u32 pos;
270 u32 base;
271 u32 surf;
272 u32 addr;
273 u32 status;
274 u32 linoff;
275 u32 tileoff;
276 u32 palette[256];
277};
278
648a8e34 279struct psb_state {
648a8e34
AC		 280 uint32_t saveVCLK_DIVISOR_VGA0;
281 uint32_t saveVCLK_DIVISOR_VGA1;
282 uint32_t saveVCLK_POST_DIV;
283 uint32_t saveVGACNTRL;
284 uint32_t saveADPA;
285 uint32_t saveLVDS;
286 uint32_t saveDVOA;
287 uint32_t saveDVOB;
288 uint32_t saveDVOC;
289 uint32_t savePP_ON;
290 uint32_t savePP_OFF;
291 uint32_t savePP_CONTROL;
292 uint32_t savePP_CYCLE;
293 uint32_t savePFIT_CONTROL;
648a8e34
AC		 294 uint32_t saveCLOCKGATING;
295 uint32_t saveDSPARB;
648a8e34
AC		 296 uint32_t savePFIT_AUTO_RATIOS;
297 uint32_t savePFIT_PGM_RATIOS;
298 uint32_t savePP_ON_DELAYS;
299 uint32_t savePP_OFF_DELAYS;
300 uint32_t savePP_DIVISOR;
648a8e34
AC		 301 uint32_t saveBCLRPAT_A;
302 uint32_t saveBCLRPAT_B;
648a8e34
AC		 303 uint32_t savePERF_MODE;
304 uint32_t saveDSPFW1;
305 uint32_t saveDSPFW2;
306 uint32_t saveDSPFW3;
307 uint32_t saveDSPFW4;
308 uint32_t saveDSPFW5;
309 uint32_t saveDSPFW6;
310 uint32_t saveCHICKENBIT;
311 uint32_t saveDSPACURSOR_CTRL;
312 uint32_t saveDSPBCURSOR_CTRL;
313 uint32_t saveDSPACURSOR_BASE;
314 uint32_t saveDSPBCURSOR_BASE;
315 uint32_t saveDSPACURSOR_POS;
316 uint32_t saveDSPBCURSOR_POS;
648a8e34
AC		 317 uint32_t saveOV_OVADD;
318 uint32_t saveOV_OGAMC0;
319 uint32_t saveOV_OGAMC1;
320 uint32_t saveOV_OGAMC2;
321 uint32_t saveOV_OGAMC3;
322 uint32_t saveOV_OGAMC4;
323 uint32_t saveOV_OGAMC5;
324 uint32_t saveOVC_OVADD;
325 uint32_t saveOVC_OGAMC0;
326 uint32_t saveOVC_OGAMC1;
327 uint32_t saveOVC_OGAMC2;
328 uint32_t saveOVC_OGAMC3;
329 uint32_t saveOVC_OGAMC4;
330 uint32_t saveOVC_OGAMC5;
331
332 /* DPST register save */
333 uint32_t saveHISTOGRAM_INT_CONTROL_REG;
334 uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG;
335 uint32_t savePWM_CONTROL_LOGIC;
336};
337
09016a11
AC		 338struct cdv_state {
339 uint32_t saveDSPCLK_GATE_D;
340 uint32_t saveRAMCLK_GATE_D;
341 uint32_t saveDSPARB;
342 uint32_t saveDSPFW[6];
343 uint32_t saveADPA;
344 uint32_t savePP_CONTROL;
345 uint32_t savePFIT_PGM_RATIOS;
346 uint32_t saveLVDS;
347 uint32_t savePFIT_CONTROL;
348 uint32_t savePP_ON_DELAYS;
349 uint32_t savePP_OFF_DELAYS;
350 uint32_t savePP_CYCLE;
351 uint32_t saveVGACNTRL;
352 uint32_t saveIER;
353 uint32_t saveIMR;
354 u8 saveLBB;
355};
356
c6265ff5 357struct psb_save_area {
6256304b 358 struct psb_pipe pipe[3];
c6265ff5
AC		 359 uint32_t saveBSM;
360 uint32_t saveVBT;
361 union {
362 struct psb_state psb;
09016a11 363 struct cdv_state cdv;
c6265ff5
AC		 364 };
365 uint32_t saveBLC_PWM_CTL2;
366 uint32_t saveBLC_PWM_CTL;
367};
368
5c49fd3a
AC		 369struct psb_ops;
370
04bd564f
AC		 371#define PSB_NUM_PIPE 3
372
bfc838f8
AS		 373struct intel_scu_ipc_dev;
374
5c49fd3a 375struct drm_psb_private {
c2f17e60
TZ		 376 struct drm_device dev;
377
2657929d 378 struct pci_dev *aux_pdev; /* Currently only used by mrst */
5a52b1f2 379 struct pci_dev *lpc_pdev; /* Currently only used by mrst */
5c49fd3a 380 const struct psb_ops *ops;
8512e074 381 const struct psb_offset *regmap;
6b7ce2c4 382
1fb28e9e
AC		 383 struct child_device_config *child_dev;
384 int child_dev_num;
5c49fd3a
AC		 385
386 struct psb_gtt gtt;
387
388 /* GTT Memory manager */
389 struct psb_gtt_mm *gtt_mm;
390 struct page *scratch_page;
eab37607 391 u32 __iomem *gtt_map;
5c49fd3a 392 uint32_t stolen_base;
37214ca0 393 u8 __iomem *vram_addr;
5c49fd3a 394 unsigned long vram_stolen_size;
5c49fd3a
AC		 395 u16 gmch_ctrl; /* Saved GTT setup */
396 u32 pge_ctl;
397
398 struct mutex gtt_mutex;
399 struct resource *gtt_mem; /* Our PCI resource */
400
737292a3
DV		 401 struct mutex mmap_mutex;
402
5c49fd3a
AC		 403 struct psb_mmu_driver *mmu;
404 struct psb_mmu_pd *pf_pd;
405
9083eb38 406 /* Register base */
846a6038
KS		 407 uint8_t __iomem *sgx_reg;
408 uint8_t __iomem *vdc_reg;
2657929d 409 uint8_t __iomem *aux_reg; /* Auxillary vdc pipe regs */
5a52b1f2 410 uint16_t lpc_gpio_base;
5c49fd3a
AC		 411 uint32_t gatt_free_offset;
412
9083eb38 413 /* Fencing / irq */
5c49fd3a
AC		 414 uint32_t vdc_irq_mask;
415 uint32_t pipestat[PSB_NUM_PIPE];
416
417 spinlock_t irqmask_lock;
da596080 418 bool irq_enabled;
5c49fd3a 419
9083eb38 420 /* Power */
672c4735 421 bool pm_initialized;
5c49fd3a 422
9083eb38 423 /* Modesetting */
5c49fd3a 424 struct psb_intel_mode_device mode_dev;
4ab2c7f1 425 bool modeset; /* true if we have done the mode_device setup */
5c49fd3a
AC		 426
427 struct drm_crtc *plane_to_crtc_mapping[PSB_NUM_PIPE];
428 struct drm_crtc *pipe_to_crtc_mapping[PSB_NUM_PIPE];
429 uint32_t num_pipe;
430
9083eb38 431 /* OSPM info (Power management base) (TODO: can go ?) */
5c49fd3a
AC		 432 uint32_t ospm_base;
433
9083eb38 434 /* Sizes info */
5c49fd3a
AC		 435 u32 fuse_reg_value;
436 u32 video_device_fuse;
437
438 /* PCI revision ID for B0:D2:F0 */
439 uint8_t platform_rev_id;
440
5c0c1d50
PJ		 441 /* gmbus */
442 struct intel_gmbus *gmbus;
2657929d 443 uint8_t __iomem *gmbus_reg;
5c0c1d50 444
5736995b
PJ		 445 /* Used by SDVO */
446 int crt_ddc_pin;
447 /* FIXME: The mappings should be parsed from bios but for now we can
448 pretend there are no mappings available */
449 struct sdvo_device_mapping sdvo_mappings[2];
450 u32 hotplug_supported_mask;
451 struct drm_property *broadcast_rgb_property;
452 struct drm_property *force_audio_property;
453
9083eb38 454 /* LVDS info */
5c49fd3a
AC		 455 int backlight_duty_cycle; /* restore backlight to this value */
456 bool panel_wants_dither;
457 struct drm_display_mode *panel_fixed_mode;
458 struct drm_display_mode *lfp_lvds_vbt_mode;
459 struct drm_display_mode *sdvo_lvds_vbt_mode;
460
461 struct bdb_lvds_backlight *lvds_bl; /* LVDS backlight info from VBT */
04477e5e 462 struct gma_i2c_chan *lvds_i2c_bus; /* FIXME: Remove this? */
5c49fd3a
AC		 463
464 /* Feature bits from the VBIOS */
465 unsigned int int_tv_support:1;
466 unsigned int lvds_dither:1;
467 unsigned int lvds_vbt:1;
468 unsigned int int_crt_support:1;
469 unsigned int lvds_use_ssc:1;
470 int lvds_ssc_freq;
471 bool is_lvds_on;
472 bool is_mipi_on;
7c420636 473 bool lvds_enabled_in_vbt;
5c49fd3a
AC		 474 u32 mipi_ctrl_display;
475
476 unsigned int core_freq;
477 uint32_t iLVDS_enable;
478
5c49fd3a 479 /* MID specific */
9b6a1657 480 bool use_msi;
4086b1e2 481 bool has_gct;
5c49fd3a
AC		 482 struct oaktrail_gct_data gct_data;
483
933315ac 484 /* Oaktrail HDMI state */
5c49fd3a 485 struct oaktrail_hdmi_dev *hdmi_priv;
6b7ce2c4 486
9083eb38 487 /* Register state */
c6265ff5
AC		 488 struct psb_save_area regs;
489
9083eb38 490 /* Hotplug handling */
ae0a246a 491 struct work_struct hotplug_work;
5c49fd3a 492
5c49fd3a 493 struct psb_intel_opregion opregion;
5c49fd3a 494
9083eb38 495 /* Watchdog */
5c49fd3a
AC		 496 uint32_t apm_reg;
497 uint16_t apm_base;
498
499 /*
500 * Used for modifying backlight from
501 * xrandr -- consider removing and using HAL instead
502 */
bfc838f8 503 struct intel_scu_ipc_dev *scu;
5c49fd3a
AC		 504 struct backlight_device *backlight_device;
505 struct drm_property *backlight_property;
d112a816
ZY		 506 bool backlight_enabled;
507 int backlight_level;
5c49fd3a
AC		 508 uint32_t blc_adj1;
509 uint32_t blc_adj2;
510
026abc33
KS		 511 bool dsr_enable;
512 u32 dsr_fb_update;
513 bool dpi_panel_on[3];
514 void *dsi_configs[2];
515 u32 bpp;
516 u32 bpp2;
517
518 u32 pipeconf[3];
519 u32 dspcntr[3];
520
642c52fc 521 bool dplla_96mhz; /* DPLL data from the VBT */
d112a816
ZY		 522
523 struct {
524 int rate;
525 int lanes;
526 int preemphasis;
527 int vswing;
528
529 bool initialized;
530 bool support;
531 int bpp;
532 struct edp_power_seq pps;
533 } edp;
534 uint8_t panel_type;
5c49fd3a
AC		 535};
536
f71635e8
TZ		 537static inline struct drm_psb_private *to_drm_psb_private(struct drm_device *dev)
538{
c2f17e60 539 return container_of(dev, struct drm_psb_private, dev);
f71635e8 540}
5c49fd3a 541
9083eb38 542/* Operations for each board type */
5c49fd3a
AC		 543struct psb_ops {
544 const char *name;
5c49fd3a
AC		 545 int pipes; /* Number of output pipes */
546 int crtcs; /* Number of CRTCs */
547 int sgx_offset; /* Base offset of SGX device */
d235e64a
AC		 548 int hdmi_mask; /* Mask of HDMI CRTCs */
549 int lvds_mask; /* Mask of LVDS CRTCs */
cf8efd3a 550 int sdvo_mask; /* Mask of SDVO CRTCs */
bc794829 551 int cursor_needs_phys; /* If cursor base reg need physical address */
5c49fd3a
AC		 552
553 /* Sub functions */
554 struct drm_crtc_helper_funcs const *crtc_helper;
5ea75e0f 555 const struct gma_clock_funcs *clock_funcs;
5c49fd3a
AC		 556
557 /* Setup hooks */
558 int (*chip_setup)(struct drm_device *dev);
559 void (*chip_teardown)(struct drm_device *dev);
d235e64a
AC		 560 /* Optional helper caller after modeset */
561 void (*errata)(struct drm_device *dev);
5c49fd3a
AC		 562
563 /* Display management hooks */
564 int (*output_init)(struct drm_device *dev);
68cb638f
AC		 565 int (*hotplug)(struct drm_device *dev);
566 void (*hotplug_enable)(struct drm_device *dev, bool on);
5c49fd3a
AC		 567 /* Power management hooks */
568 void (*init_pm)(struct drm_device *dev);
569 int (*save_regs)(struct drm_device *dev);
570 int (*restore_regs)(struct drm_device *dev);
d56f57ac
DV		 571 void (*save_crtc)(struct drm_crtc *crtc);
572 void (*restore_crtc)(struct drm_crtc *crtc);
5c49fd3a
AC		 573 int (*power_up)(struct drm_device *dev);
574 int (*power_down)(struct drm_device *dev);
28a8194c 575 void (*update_wm)(struct drm_device *dev, struct drm_crtc *crtc);
75346fe9 576 void (*disable_sr)(struct drm_device *dev);
5c49fd3a
AC		 577
578 void (*lvds_bl_power)(struct drm_device *dev, bool on);
1f90b123 579
5c49fd3a
AC		 580 /* Backlight */
581 int (*backlight_init)(struct drm_device *dev);
1f90b123
HG		 582 void (*backlight_set)(struct drm_device *dev, int level);
583 int (*backlight_get)(struct drm_device *dev);
584 const char *backlight_name;
585
5c49fd3a
AC		 586 int i2c_bus; /* I2C bus identifier for Moorestown */
587};
588
5c49fd3a
AC		 589/* modesetting */
590extern void psb_modeset_init(struct drm_device *dev);
591extern void psb_modeset_cleanup(struct drm_device *dev);
b8bbbea1
TZ		 592
593/* framebuffer */
594struct drm_framebuffer *psb_framebuffer_create(struct drm_device *dev,
595 const struct drm_mode_fb_cmd2 *mode_cmd,
596 struct drm_gem_object *obj);
597
598/* fbdev */
599#if defined(CONFIG_DRM_FBDEV_EMULATION)
8f1aaccb 600void psb_fbdev_setup(struct drm_psb_private *dev_priv);
b8bbbea1 601#else
8f1aaccb 602static inline void psb_fbdev_setup(struct drm_psb_private *dev_priv)
b8bbbea1
TZ		 603{ }
604#endif
5c49fd3a
AC		 605
606/* backlight.c */
607int gma_backlight_init(struct drm_device *dev);
608void gma_backlight_exit(struct drm_device *dev);
d112a816
ZY		 609void gma_backlight_disable(struct drm_device *dev);
610void gma_backlight_enable(struct drm_device *dev);
611void gma_backlight_set(struct drm_device *dev, int v);
5c49fd3a
AC		 612
613/* oaktrail_crtc.c */
614extern const struct drm_crtc_helper_funcs oaktrail_helper_funcs;
615
616/* oaktrail_lvds.c */
617extern void oaktrail_lvds_init(struct drm_device *dev,
618 struct psb_intel_mode_device *mode_dev);
619
620/* psb_intel_display.c */
621extern const struct drm_crtc_helper_funcs psb_intel_helper_funcs;
5c49fd3a
AC		 622
623/* psb_intel_lvds.c */
624extern const struct drm_connector_helper_funcs
625 psb_intel_lvds_connector_helper_funcs;
626extern const struct drm_connector_funcs psb_intel_lvds_connector_funcs;
627
628/* gem.c */
5c49fd3a
AC		 629extern int psb_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
630 struct drm_mode_create_dumb *args);
5c49fd3a
AC		 631
632/* psb_device.c */
633extern const struct psb_ops psb_chip_ops;
634
635/* oaktrail_device.c */
636extern const struct psb_ops oaktrail_chip_ops;
637
638/* cdv_device.c */
639extern const struct psb_ops cdv_chip_ops;
640
9083eb38 641/* Utilities */
5c49fd3a
AC		 642static inline uint32_t REGISTER_READ(struct drm_device *dev, uint32_t reg)
643{
f71635e8 644 struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
5c49fd3a
AC		 645 return ioread32(dev_priv->vdc_reg + reg);
646}
647
2657929d
PJ		 648static inline uint32_t REGISTER_READ_AUX(struct drm_device *dev, uint32_t reg)
649{
f71635e8 650 struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
2657929d
PJ		 651 return ioread32(dev_priv->aux_reg + reg);
652}
653
5c49fd3a 654#define REG_READ(reg) REGISTER_READ(dev, (reg))
2657929d 655#define REG_READ_AUX(reg) REGISTER_READ_AUX(dev, (reg))
5c49fd3a 656
b97b8287
PJ		 657/* Useful for post reads */
658static inline uint32_t REGISTER_READ_WITH_AUX(struct drm_device *dev,
659 uint32_t reg, int aux)
660{
661 uint32_t val;
662
663 if (aux)
664 val = REG_READ_AUX(reg);
665 else
666 val = REG_READ(reg);
667
668 return val;
669}
670
671#define REG_READ_WITH_AUX(reg, aux) REGISTER_READ_WITH_AUX(dev, (reg), (aux))
672
5c49fd3a 673static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg,
2657929d 674 uint32_t val)
5c49fd3a 675{
f71635e8 676 struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
5c49fd3a
AC		 677 iowrite32((val), dev_priv->vdc_reg + (reg));
678}
679
2657929d
PJ		 680static inline void REGISTER_WRITE_AUX(struct drm_device *dev, uint32_t reg,
681 uint32_t val)
682{
f71635e8 683 struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
2657929d
PJ		 684 iowrite32((val), dev_priv->aux_reg + (reg));
685}
686
5c49fd3a 687#define REG_WRITE(reg, val) REGISTER_WRITE(dev, (reg), (val))
2657929d 688#define REG_WRITE_AUX(reg, val) REGISTER_WRITE_AUX(dev, (reg), (val))
5c49fd3a 689
b97b8287
PJ		 690static inline void REGISTER_WRITE_WITH_AUX(struct drm_device *dev, uint32_t reg,
691 uint32_t val, int aux)
692{
693 if (aux)
694 REG_WRITE_AUX(reg, val);
695 else
696 REG_WRITE(reg, val);
697}
698
699#define REG_WRITE_WITH_AUX(reg, val, aux) REGISTER_WRITE_WITH_AUX(dev, (reg), (val), (aux))
700
5c49fd3a
AC		 701static inline void REGISTER_WRITE16(struct drm_device *dev,
702 uint32_t reg, uint32_t val)
703{
f71635e8 704 struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
5c49fd3a
AC		 705 iowrite16((val), dev_priv->vdc_reg + (reg));
706}
707
708#define REG_WRITE16(reg, val) REGISTER_WRITE16(dev, (reg), (val))
709
710static inline void REGISTER_WRITE8(struct drm_device *dev,
711 uint32_t reg, uint32_t val)
712{
f71635e8 713 struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
5c49fd3a
AC		 714 iowrite8((val), dev_priv->vdc_reg + (reg));
715}
716
717#define REG_WRITE8(reg, val) REGISTER_WRITE8(dev, (reg), (val))
718
719#define PSB_WVDC32(_val, _offs) iowrite32(_val, dev_priv->vdc_reg + (_offs))
720#define PSB_RVDC32(_offs) ioread32(dev_priv->vdc_reg + (_offs))
721
5c49fd3a 722#define PSB_RSGX32(_offs) ioread32(dev_priv->sgx_reg + (_offs))
5c49fd3a
AC		 723#define PSB_WSGX32(_val, _offs) iowrite32(_val, dev_priv->sgx_reg + (_offs))
724
5c49fd3a
AC		 725#define PSB_WMSVDX32(_val, _offs) iowrite32(_val, dev_priv->msvdx_reg + (_offs))
726#define PSB_RMSVDX32(_offs) ioread32(dev_priv->msvdx_reg + (_offs))
727
728#endif
Linux 6.x block layer and io_uring tree(s)