Commit | Line | Data |
---|---|---|
1b082ccf AC |
1 | /* |
2 | * Copyright © 2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Li Peng <peng.li@intel.com> | |
25 | */ | |
26 | ||
27 | #include <drm/drmP.h> | |
28 | #include <drm/drm.h> | |
29 | #include "psb_intel_drv.h" | |
30 | #include "psb_intel_reg.h" | |
31 | #include "psb_drv.h" | |
32 | ||
33 | #define HDMI_READ(reg) readl(hdmi_dev->regs + (reg)) | |
34 | #define HDMI_WRITE(reg, val) writel(val, hdmi_dev->regs + (reg)) | |
35 | ||
36 | #define HDMI_HCR 0x1000 | |
37 | #define HCR_ENABLE_HDCP (1 << 5) | |
38 | #define HCR_ENABLE_AUDIO (1 << 2) | |
39 | #define HCR_ENABLE_PIXEL (1 << 1) | |
40 | #define HCR_ENABLE_TMDS (1 << 0) | |
41 | ||
42 | #define HDMI_HICR 0x1004 | |
43 | #define HDMI_HSR 0x1008 | |
44 | #define HDMI_HISR 0x100C | |
45 | #define HDMI_DETECT_HDP (1 << 0) | |
46 | ||
47 | #define HDMI_VIDEO_REG 0x3000 | |
48 | #define HDMI_UNIT_EN (1 << 7) | |
49 | #define HDMI_MODE_OUTPUT (1 << 0) | |
50 | #define HDMI_HBLANK_A 0x3100 | |
51 | ||
52 | #define HDMI_AUDIO_CTRL 0x4000 | |
53 | #define HDMI_ENABLE_AUDIO (1 << 0) | |
54 | ||
55 | #define PCH_HTOTAL_B 0x3100 | |
56 | #define PCH_HBLANK_B 0x3104 | |
57 | #define PCH_HSYNC_B 0x3108 | |
58 | #define PCH_VTOTAL_B 0x310C | |
59 | #define PCH_VBLANK_B 0x3110 | |
60 | #define PCH_VSYNC_B 0x3114 | |
61 | #define PCH_PIPEBSRC 0x311C | |
62 | ||
63 | #define PCH_PIPEB_DSL 0x3800 | |
64 | #define PCH_PIPEB_SLC 0x3804 | |
65 | #define PCH_PIPEBCONF 0x3808 | |
66 | #define PCH_PIPEBSTAT 0x3824 | |
67 | ||
68 | #define CDVO_DFT 0x5000 | |
69 | #define CDVO_SLEWRATE 0x5004 | |
70 | #define CDVO_STRENGTH 0x5008 | |
71 | #define CDVO_RCOMP 0x500C | |
72 | ||
73 | #define DPLL_CTRL 0x6000 | |
74 | #define DPLL_PDIV_SHIFT 16 | |
75 | #define DPLL_PDIV_MASK (0xf << 16) | |
76 | #define DPLL_PWRDN (1 << 4) | |
77 | #define DPLL_RESET (1 << 3) | |
78 | #define DPLL_FASTEN (1 << 2) | |
79 | #define DPLL_ENSTAT (1 << 1) | |
80 | #define DPLL_DITHEN (1 << 0) | |
81 | ||
82 | #define DPLL_DIV_CTRL 0x6004 | |
83 | #define DPLL_CLKF_MASK 0xffffffc0 | |
84 | #define DPLL_CLKR_MASK (0x3f) | |
85 | ||
86 | #define DPLL_CLK_ENABLE 0x6008 | |
87 | #define DPLL_EN_DISP (1 << 31) | |
88 | #define DPLL_SEL_HDMI (1 << 8) | |
89 | #define DPLL_EN_HDMI (1 << 1) | |
90 | #define DPLL_EN_VGA (1 << 0) | |
91 | ||
92 | #define DPLL_ADJUST 0x600C | |
93 | #define DPLL_STATUS 0x6010 | |
94 | #define DPLL_UPDATE 0x6014 | |
95 | #define DPLL_DFT 0x6020 | |
96 | ||
97 | struct intel_range { | |
98 | int min, max; | |
99 | }; | |
100 | ||
101 | struct oaktrail_hdmi_limit { | |
102 | struct intel_range vco, np, nr, nf; | |
103 | }; | |
104 | ||
105 | struct oaktrail_hdmi_clock { | |
106 | int np; | |
107 | int nr; | |
108 | int nf; | |
109 | int dot; | |
110 | }; | |
111 | ||
112 | #define VCO_MIN 320000 | |
113 | #define VCO_MAX 1650000 | |
114 | #define NP_MIN 1 | |
115 | #define NP_MAX 15 | |
116 | #define NR_MIN 1 | |
117 | #define NR_MAX 64 | |
118 | #define NF_MIN 2 | |
119 | #define NF_MAX 4095 | |
120 | ||
121 | static const struct oaktrail_hdmi_limit oaktrail_hdmi_limit = { | |
122 | .vco = { .min = VCO_MIN, .max = VCO_MAX }, | |
123 | .np = { .min = NP_MIN, .max = NP_MAX }, | |
124 | .nr = { .min = NR_MIN, .max = NR_MAX }, | |
125 | .nf = { .min = NF_MIN, .max = NF_MAX }, | |
126 | }; | |
127 | ||
1b082ccf AC |
128 | static void oaktrail_hdmi_audio_enable(struct drm_device *dev) |
129 | { | |
130 | struct drm_psb_private *dev_priv = dev->dev_private; | |
131 | struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv; | |
132 | ||
133 | HDMI_WRITE(HDMI_HCR, 0x67); | |
134 | HDMI_READ(HDMI_HCR); | |
135 | ||
136 | HDMI_WRITE(0x51a8, 0x10); | |
137 | HDMI_READ(0x51a8); | |
138 | ||
139 | HDMI_WRITE(HDMI_AUDIO_CTRL, 0x1); | |
140 | HDMI_READ(HDMI_AUDIO_CTRL); | |
141 | } | |
142 | ||
143 | static void oaktrail_hdmi_audio_disable(struct drm_device *dev) | |
144 | { | |
145 | struct drm_psb_private *dev_priv = dev->dev_private; | |
146 | struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv; | |
147 | ||
148 | HDMI_WRITE(0x51a8, 0x0); | |
149 | HDMI_READ(0x51a8); | |
150 | ||
151 | HDMI_WRITE(HDMI_AUDIO_CTRL, 0x0); | |
152 | HDMI_READ(HDMI_AUDIO_CTRL); | |
153 | ||
154 | HDMI_WRITE(HDMI_HCR, 0x47); | |
155 | HDMI_READ(HDMI_HCR); | |
156 | } | |
157 | ||
39ec748f AC |
158 | static unsigned int htotal_calculate(struct drm_display_mode *mode) |
159 | { | |
160 | u32 htotal, new_crtc_htotal; | |
161 | ||
162 | htotal = (mode->crtc_hdisplay - 1) | ((mode->crtc_htotal - 1) << 16); | |
163 | ||
164 | /* | |
165 | * 1024 x 768 new_crtc_htotal = 0x1024; | |
166 | * 1280 x 1024 new_crtc_htotal = 0x0c34; | |
167 | */ | |
168 | new_crtc_htotal = (mode->crtc_htotal - 1) * 200 * 1000 / mode->clock; | |
169 | ||
170 | DRM_DEBUG_KMS("new crtc htotal 0x%4x\n", new_crtc_htotal); | |
171 | return (mode->crtc_hdisplay - 1) | (new_crtc_htotal << 16); | |
172 | } | |
173 | ||
174 | static void oaktrail_hdmi_find_dpll(struct drm_crtc *crtc, int target, | |
175 | int refclk, struct oaktrail_hdmi_clock *best_clock) | |
176 | { | |
177 | int np_min, np_max, nr_min, nr_max; | |
178 | int np, nr, nf; | |
179 | ||
180 | np_min = DIV_ROUND_UP(oaktrail_hdmi_limit.vco.min, target * 10); | |
181 | np_max = oaktrail_hdmi_limit.vco.max / (target * 10); | |
182 | if (np_min < oaktrail_hdmi_limit.np.min) | |
183 | np_min = oaktrail_hdmi_limit.np.min; | |
184 | if (np_max > oaktrail_hdmi_limit.np.max) | |
185 | np_max = oaktrail_hdmi_limit.np.max; | |
186 | ||
187 | nr_min = DIV_ROUND_UP((refclk * 1000), (target * 10 * np_max)); | |
188 | nr_max = DIV_ROUND_UP((refclk * 1000), (target * 10 * np_min)); | |
189 | if (nr_min < oaktrail_hdmi_limit.nr.min) | |
190 | nr_min = oaktrail_hdmi_limit.nr.min; | |
191 | if (nr_max > oaktrail_hdmi_limit.nr.max) | |
192 | nr_max = oaktrail_hdmi_limit.nr.max; | |
193 | ||
194 | np = DIV_ROUND_UP((refclk * 1000), (target * 10 * nr_max)); | |
195 | nr = DIV_ROUND_UP((refclk * 1000), (target * 10 * np)); | |
196 | nf = DIV_ROUND_CLOSEST((target * 10 * np * nr), refclk); | |
197 | DRM_DEBUG_KMS("np, nr, nf %d %d %d\n", np, nr, nf); | |
198 | ||
199 | /* | |
200 | * 1024 x 768 np = 1; nr = 0x26; nf = 0x0fd8000; | |
201 | * 1280 x 1024 np = 1; nr = 0x17; nf = 0x1034000; | |
202 | */ | |
203 | best_clock->np = np; | |
204 | best_clock->nr = nr - 1; | |
205 | best_clock->nf = (nf << 14); | |
206 | } | |
207 | ||
208 | static void scu_busy_loop(void __iomem *scu_base) | |
209 | { | |
210 | u32 status = 0; | |
211 | u32 loop_count = 0; | |
212 | ||
213 | status = readl(scu_base + 0x04); | |
214 | while (status & 1) { | |
215 | udelay(1); /* scu processing time is in few u secods */ | |
216 | status = readl(scu_base + 0x04); | |
217 | loop_count++; | |
218 | /* break if scu doesn't reset busy bit after huge retry */ | |
219 | if (loop_count > 1000) { | |
220 | DRM_DEBUG_KMS("SCU IPC timed out"); | |
221 | return; | |
222 | } | |
223 | } | |
224 | } | |
225 | ||
226 | /* | |
227 | * You don't want to know, you really really don't want to know.... | |
228 | * | |
229 | * This is magic. However it's safe magic because of the way the platform | |
230 | * works and it is necessary magic. | |
231 | */ | |
232 | static void oaktrail_hdmi_reset(struct drm_device *dev) | |
233 | { | |
234 | void __iomem *base; | |
235 | unsigned long scu_ipc_mmio = 0xff11c000UL; | |
236 | int scu_len = 1024; | |
237 | ||
238 | base = ioremap((resource_size_t)scu_ipc_mmio, scu_len); | |
239 | if (base == NULL) { | |
240 | DRM_ERROR("failed to map scu mmio\n"); | |
241 | return; | |
242 | } | |
243 | ||
244 | /* scu ipc: assert hdmi controller reset */ | |
245 | writel(0xff11d118, base + 0x0c); | |
246 | writel(0x7fffffdf, base + 0x80); | |
247 | writel(0x42005, base + 0x0); | |
248 | scu_busy_loop(base); | |
249 | ||
250 | /* scu ipc: de-assert hdmi controller reset */ | |
251 | writel(0xff11d118, base + 0x0c); | |
252 | writel(0x7fffffff, base + 0x80); | |
253 | writel(0x42005, base + 0x0); | |
254 | scu_busy_loop(base); | |
255 | ||
256 | iounmap(base); | |
257 | } | |
258 | ||
259 | int oaktrail_crtc_hdmi_mode_set(struct drm_crtc *crtc, | |
260 | struct drm_display_mode *mode, | |
261 | struct drm_display_mode *adjusted_mode, | |
262 | int x, int y, | |
263 | struct drm_framebuffer *old_fb) | |
264 | { | |
265 | struct drm_device *dev = crtc->dev; | |
266 | struct drm_psb_private *dev_priv = dev->dev_private; | |
267 | struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv; | |
268 | int pipe = 1; | |
269 | int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B; | |
270 | int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B; | |
271 | int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B; | |
272 | int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B; | |
273 | int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B; | |
274 | int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B; | |
275 | int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE; | |
276 | int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS; | |
277 | int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC; | |
278 | int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; | |
279 | int refclk; | |
280 | struct oaktrail_hdmi_clock clock; | |
281 | u32 dspcntr, pipeconf, dpll, temp; | |
282 | int dspcntr_reg = DSPBCNTR; | |
283 | ||
284 | if (!gma_power_begin(dev, true)) | |
285 | return 0; | |
286 | ||
287 | /* Disable the VGA plane that we never use */ | |
288 | REG_WRITE(VGACNTRL, VGA_DISP_DISABLE); | |
289 | ||
290 | /* Disable dpll if necessary */ | |
291 | dpll = REG_READ(DPLL_CTRL); | |
292 | if ((dpll & DPLL_PWRDN) == 0) { | |
293 | REG_WRITE(DPLL_CTRL, dpll | (DPLL_PWRDN | DPLL_RESET)); | |
294 | REG_WRITE(DPLL_DIV_CTRL, 0x00000000); | |
295 | REG_WRITE(DPLL_STATUS, 0x1); | |
296 | } | |
297 | udelay(150); | |
298 | ||
299 | /* Reset controller */ | |
300 | oaktrail_hdmi_reset(dev); | |
301 | ||
302 | /* program and enable dpll */ | |
303 | refclk = 25000; | |
304 | oaktrail_hdmi_find_dpll(crtc, adjusted_mode->clock, refclk, &clock); | |
305 | ||
306 | /* Set the DPLL */ | |
307 | dpll = REG_READ(DPLL_CTRL); | |
308 | dpll &= ~DPLL_PDIV_MASK; | |
309 | dpll &= ~(DPLL_PWRDN | DPLL_RESET); | |
310 | REG_WRITE(DPLL_CTRL, 0x00000008); | |
311 | REG_WRITE(DPLL_DIV_CTRL, ((clock.nf << 6) | clock.nr)); | |
312 | REG_WRITE(DPLL_ADJUST, ((clock.nf >> 14) - 1)); | |
313 | REG_WRITE(DPLL_CTRL, (dpll | (clock.np << DPLL_PDIV_SHIFT) | DPLL_ENSTAT | DPLL_DITHEN)); | |
314 | REG_WRITE(DPLL_UPDATE, 0x80000000); | |
315 | REG_WRITE(DPLL_CLK_ENABLE, 0x80050102); | |
316 | udelay(150); | |
317 | ||
318 | /* configure HDMI */ | |
319 | HDMI_WRITE(0x1004, 0x1fd); | |
320 | HDMI_WRITE(0x2000, 0x1); | |
321 | HDMI_WRITE(0x2008, 0x0); | |
322 | HDMI_WRITE(0x3130, 0x8); | |
323 | HDMI_WRITE(0x101c, 0x1800810); | |
324 | ||
325 | temp = htotal_calculate(adjusted_mode); | |
326 | REG_WRITE(htot_reg, temp); | |
327 | REG_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
328 | REG_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
329 | REG_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) | ((adjusted_mode->crtc_vtotal - 1) << 16)); | |
330 | REG_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) | ((adjusted_mode->crtc_vblank_end - 1) << 16)); | |
331 | REG_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
332 | REG_WRITE(pipesrc_reg, ((mode->crtc_hdisplay - 1) << 16) | (mode->crtc_vdisplay - 1)); | |
333 | ||
334 | REG_WRITE(PCH_HTOTAL_B, (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
335 | REG_WRITE(PCH_HBLANK_B, (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
336 | REG_WRITE(PCH_HSYNC_B, (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
337 | REG_WRITE(PCH_VTOTAL_B, (adjusted_mode->crtc_vdisplay - 1) | ((adjusted_mode->crtc_vtotal - 1) << 16)); | |
338 | REG_WRITE(PCH_VBLANK_B, (adjusted_mode->crtc_vblank_start - 1) | ((adjusted_mode->crtc_vblank_end - 1) << 16)); | |
339 | REG_WRITE(PCH_VSYNC_B, (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
340 | REG_WRITE(PCH_PIPEBSRC, ((mode->crtc_hdisplay - 1) << 16) | (mode->crtc_vdisplay - 1)); | |
341 | ||
342 | temp = adjusted_mode->crtc_hblank_end - adjusted_mode->crtc_hblank_start; | |
343 | HDMI_WRITE(HDMI_HBLANK_A, ((adjusted_mode->crtc_hdisplay - 1) << 16) | temp); | |
344 | ||
345 | REG_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1)); | |
346 | REG_WRITE(dsppos_reg, 0); | |
347 | ||
348 | /* Flush the plane changes */ | |
349 | { | |
350 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | |
351 | crtc_funcs->mode_set_base(crtc, x, y, old_fb); | |
352 | } | |
353 | ||
354 | /* Set up the display plane register */ | |
355 | dspcntr = REG_READ(dspcntr_reg); | |
356 | dspcntr |= DISPPLANE_GAMMA_ENABLE; | |
357 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
358 | dspcntr |= DISPLAY_PLANE_ENABLE; | |
359 | ||
360 | /* setup pipeconf */ | |
361 | pipeconf = REG_READ(pipeconf_reg); | |
362 | pipeconf |= PIPEACONF_ENABLE; | |
363 | ||
364 | REG_WRITE(pipeconf_reg, pipeconf); | |
365 | REG_READ(pipeconf_reg); | |
366 | ||
367 | REG_WRITE(PCH_PIPEBCONF, pipeconf); | |
368 | REG_READ(PCH_PIPEBCONF); | |
d1fa08f3 | 369 | gma_wait_for_vblank(dev); |
39ec748f AC |
370 | |
371 | REG_WRITE(dspcntr_reg, dspcntr); | |
d1fa08f3 | 372 | gma_wait_for_vblank(dev); |
39ec748f AC |
373 | |
374 | gma_power_end(dev); | |
375 | ||
376 | return 0; | |
377 | } | |
378 | ||
379 | void oaktrail_crtc_hdmi_dpms(struct drm_crtc *crtc, int mode) | |
380 | { | |
381 | struct drm_device *dev = crtc->dev; | |
382 | u32 temp; | |
383 | ||
384 | DRM_DEBUG_KMS("%s %d\n", __func__, mode); | |
385 | ||
386 | switch (mode) { | |
387 | case DRM_MODE_DPMS_OFF: | |
388 | REG_WRITE(VGACNTRL, 0x80000000); | |
389 | ||
390 | /* Disable plane */ | |
391 | temp = REG_READ(DSPBCNTR); | |
392 | if ((temp & DISPLAY_PLANE_ENABLE) != 0) { | |
393 | REG_WRITE(DSPBCNTR, temp & ~DISPLAY_PLANE_ENABLE); | |
394 | REG_READ(DSPBCNTR); | |
395 | /* Flush the plane changes */ | |
396 | REG_WRITE(DSPBSURF, REG_READ(DSPBSURF)); | |
397 | REG_READ(DSPBSURF); | |
398 | } | |
399 | ||
400 | /* Disable pipe B */ | |
401 | temp = REG_READ(PIPEBCONF); | |
402 | if ((temp & PIPEACONF_ENABLE) != 0) { | |
403 | REG_WRITE(PIPEBCONF, temp & ~PIPEACONF_ENABLE); | |
404 | REG_READ(PIPEBCONF); | |
405 | } | |
406 | ||
407 | /* Disable LNW Pipes, etc */ | |
408 | temp = REG_READ(PCH_PIPEBCONF); | |
409 | if ((temp & PIPEACONF_ENABLE) != 0) { | |
410 | REG_WRITE(PCH_PIPEBCONF, temp & ~PIPEACONF_ENABLE); | |
411 | REG_READ(PCH_PIPEBCONF); | |
412 | } | |
413 | ||
414 | /* wait for pipe off */ | |
415 | udelay(150); | |
416 | ||
417 | /* Disable dpll */ | |
418 | temp = REG_READ(DPLL_CTRL); | |
419 | if ((temp & DPLL_PWRDN) == 0) { | |
420 | REG_WRITE(DPLL_CTRL, temp | (DPLL_PWRDN | DPLL_RESET)); | |
421 | REG_WRITE(DPLL_STATUS, 0x1); | |
422 | } | |
423 | ||
424 | /* wait for dpll off */ | |
425 | udelay(150); | |
426 | ||
427 | break; | |
428 | case DRM_MODE_DPMS_ON: | |
429 | case DRM_MODE_DPMS_STANDBY: | |
430 | case DRM_MODE_DPMS_SUSPEND: | |
431 | /* Enable dpll */ | |
432 | temp = REG_READ(DPLL_CTRL); | |
433 | if ((temp & DPLL_PWRDN) != 0) { | |
434 | REG_WRITE(DPLL_CTRL, temp & ~(DPLL_PWRDN | DPLL_RESET)); | |
435 | temp = REG_READ(DPLL_CLK_ENABLE); | |
436 | REG_WRITE(DPLL_CLK_ENABLE, temp | DPLL_EN_DISP | DPLL_SEL_HDMI | DPLL_EN_HDMI); | |
437 | REG_READ(DPLL_CLK_ENABLE); | |
438 | } | |
439 | /* wait for dpll warm up */ | |
440 | udelay(150); | |
441 | ||
442 | /* Enable pipe B */ | |
443 | temp = REG_READ(PIPEBCONF); | |
444 | if ((temp & PIPEACONF_ENABLE) == 0) { | |
445 | REG_WRITE(PIPEBCONF, temp | PIPEACONF_ENABLE); | |
446 | REG_READ(PIPEBCONF); | |
447 | } | |
448 | ||
449 | /* Enable LNW Pipe B */ | |
450 | temp = REG_READ(PCH_PIPEBCONF); | |
451 | if ((temp & PIPEACONF_ENABLE) == 0) { | |
452 | REG_WRITE(PCH_PIPEBCONF, temp | PIPEACONF_ENABLE); | |
453 | REG_READ(PCH_PIPEBCONF); | |
454 | } | |
455 | ||
d1fa08f3 | 456 | gma_wait_for_vblank(dev); |
39ec748f AC |
457 | |
458 | /* Enable plane */ | |
459 | temp = REG_READ(DSPBCNTR); | |
460 | if ((temp & DISPLAY_PLANE_ENABLE) == 0) { | |
461 | REG_WRITE(DSPBCNTR, temp | DISPLAY_PLANE_ENABLE); | |
462 | /* Flush the plane changes */ | |
463 | REG_WRITE(DSPBSURF, REG_READ(DSPBSURF)); | |
464 | REG_READ(DSPBSURF); | |
465 | } | |
466 | ||
6443ea1a | 467 | gma_crtc_load_lut(crtc); |
39ec748f AC |
468 | } |
469 | ||
470 | /* DSPARB */ | |
471 | REG_WRITE(DSPARB, 0x00003fbf); | |
472 | ||
473 | /* FW1 */ | |
474 | REG_WRITE(0x70034, 0x3f880a0a); | |
475 | ||
476 | /* FW2 */ | |
477 | REG_WRITE(0x70038, 0x0b060808); | |
478 | ||
479 | /* FW4 */ | |
480 | REG_WRITE(0x70050, 0x08030404); | |
481 | ||
482 | /* FW5 */ | |
483 | REG_WRITE(0x70054, 0x04040404); | |
484 | ||
485 | /* LNC Chicken Bits - Squawk! */ | |
486 | REG_WRITE(0x70400, 0x4000); | |
487 | ||
488 | return; | |
489 | } | |
490 | ||
1b082ccf AC |
491 | static void oaktrail_hdmi_dpms(struct drm_encoder *encoder, int mode) |
492 | { | |
493 | static int dpms_mode = -1; | |
494 | ||
495 | struct drm_device *dev = encoder->dev; | |
496 | struct drm_psb_private *dev_priv = dev->dev_private; | |
497 | struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv; | |
498 | u32 temp; | |
499 | ||
500 | if (dpms_mode == mode) | |
501 | return; | |
502 | ||
503 | if (mode != DRM_MODE_DPMS_ON) | |
504 | temp = 0x0; | |
505 | else | |
506 | temp = 0x99; | |
507 | ||
508 | dpms_mode = mode; | |
509 | HDMI_WRITE(HDMI_VIDEO_REG, temp); | |
510 | } | |
511 | ||
1b082ccf AC |
512 | static int oaktrail_hdmi_mode_valid(struct drm_connector *connector, |
513 | struct drm_display_mode *mode) | |
514 | { | |
515 | if (mode->clock > 165000) | |
516 | return MODE_CLOCK_HIGH; | |
517 | if (mode->clock < 20000) | |
518 | return MODE_CLOCK_LOW; | |
519 | ||
520 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
521 | return MODE_NO_DBLESCAN; | |
522 | ||
523 | return MODE_OK; | |
524 | } | |
525 | ||
526 | static bool oaktrail_hdmi_mode_fixup(struct drm_encoder *encoder, | |
e811f5ae | 527 | const struct drm_display_mode *mode, |
1b082ccf AC |
528 | struct drm_display_mode *adjusted_mode) |
529 | { | |
530 | return true; | |
531 | } | |
532 | ||
533 | static enum drm_connector_status | |
534 | oaktrail_hdmi_detect(struct drm_connector *connector, bool force) | |
535 | { | |
536 | enum drm_connector_status status; | |
537 | struct drm_device *dev = connector->dev; | |
538 | struct drm_psb_private *dev_priv = dev->dev_private; | |
539 | struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv; | |
540 | u32 temp; | |
541 | ||
542 | temp = HDMI_READ(HDMI_HSR); | |
543 | DRM_DEBUG_KMS("HDMI_HSR %x\n", temp); | |
544 | ||
545 | if ((temp & HDMI_DETECT_HDP) != 0) | |
546 | status = connector_status_connected; | |
547 | else | |
548 | status = connector_status_disconnected; | |
549 | ||
550 | return status; | |
551 | } | |
552 | ||
553 | static const unsigned char raw_edid[] = { | |
554 | 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x10, 0xac, 0x2f, 0xa0, | |
555 | 0x53, 0x55, 0x33, 0x30, 0x16, 0x13, 0x01, 0x03, 0x0e, 0x3a, 0x24, 0x78, | |
556 | 0xea, 0xe9, 0xf5, 0xac, 0x51, 0x30, 0xb4, 0x25, 0x11, 0x50, 0x54, 0xa5, | |
557 | 0x4b, 0x00, 0x81, 0x80, 0xa9, 0x40, 0x71, 0x4f, 0xb3, 0x00, 0x01, 0x01, | |
558 | 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x28, 0x3c, 0x80, 0xa0, 0x70, 0xb0, | |
559 | 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x46, 0x6c, 0x21, 0x00, 0x00, 0x1a, | |
560 | 0x00, 0x00, 0x00, 0xff, 0x00, 0x47, 0x4e, 0x37, 0x32, 0x31, 0x39, 0x35, | |
561 | 0x52, 0x30, 0x33, 0x55, 0x53, 0x0a, 0x00, 0x00, 0x00, 0xfc, 0x00, 0x44, | |
562 | 0x45, 0x4c, 0x4c, 0x20, 0x32, 0x37, 0x30, 0x39, 0x57, 0x0a, 0x20, 0x20, | |
563 | 0x00, 0x00, 0x00, 0xfd, 0x00, 0x38, 0x4c, 0x1e, 0x53, 0x11, 0x00, 0x0a, | |
564 | 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x00, 0x8d | |
565 | }; | |
566 | ||
567 | static int oaktrail_hdmi_get_modes(struct drm_connector *connector) | |
568 | { | |
1b082ccf AC |
569 | struct i2c_adapter *i2c_adap; |
570 | struct edid *edid; | |
39ec748f | 571 | int ret = 0; |
1b082ccf | 572 | |
39ec748f AC |
573 | /* |
574 | * FIXME: We need to figure this lot out. In theory we can | |
575 | * read the EDID somehow but I've yet to find working reference | |
576 | * code. | |
577 | */ | |
1b082ccf AC |
578 | i2c_adap = i2c_get_adapter(3); |
579 | if (i2c_adap == NULL) { | |
580 | DRM_ERROR("No ddc adapter available!\n"); | |
581 | edid = (struct edid *)raw_edid; | |
582 | } else { | |
583 | edid = (struct edid *)raw_edid; | |
584 | /* FIXME ? edid = drm_get_edid(connector, i2c_adap); */ | |
585 | } | |
586 | ||
587 | if (edid) { | |
588 | drm_mode_connector_update_edid_property(connector, edid); | |
589 | ret = drm_add_edid_modes(connector, edid); | |
1b082ccf | 590 | } |
39ec748f | 591 | return ret; |
1b082ccf AC |
592 | } |
593 | ||
594 | static void oaktrail_hdmi_mode_set(struct drm_encoder *encoder, | |
595 | struct drm_display_mode *mode, | |
596 | struct drm_display_mode *adjusted_mode) | |
597 | { | |
598 | struct drm_device *dev = encoder->dev; | |
599 | ||
600 | oaktrail_hdmi_audio_enable(dev); | |
601 | return; | |
602 | } | |
603 | ||
604 | static void oaktrail_hdmi_destroy(struct drm_connector *connector) | |
605 | { | |
606 | return; | |
607 | } | |
608 | ||
609 | static const struct drm_encoder_helper_funcs oaktrail_hdmi_helper_funcs = { | |
610 | .dpms = oaktrail_hdmi_dpms, | |
611 | .mode_fixup = oaktrail_hdmi_mode_fixup, | |
c9d49590 | 612 | .prepare = gma_encoder_prepare, |
1b082ccf | 613 | .mode_set = oaktrail_hdmi_mode_set, |
c9d49590 | 614 | .commit = gma_encoder_commit, |
1b082ccf AC |
615 | }; |
616 | ||
617 | static const struct drm_connector_helper_funcs | |
618 | oaktrail_hdmi_connector_helper_funcs = { | |
619 | .get_modes = oaktrail_hdmi_get_modes, | |
620 | .mode_valid = oaktrail_hdmi_mode_valid, | |
c9d49590 | 621 | .best_encoder = gma_best_encoder, |
1b082ccf AC |
622 | }; |
623 | ||
624 | static const struct drm_connector_funcs oaktrail_hdmi_connector_funcs = { | |
625 | .dpms = drm_helper_connector_dpms, | |
626 | .detect = oaktrail_hdmi_detect, | |
627 | .fill_modes = drm_helper_probe_single_connector_modes, | |
628 | .destroy = oaktrail_hdmi_destroy, | |
629 | }; | |
630 | ||
631 | static void oaktrail_hdmi_enc_destroy(struct drm_encoder *encoder) | |
632 | { | |
633 | drm_encoder_cleanup(encoder); | |
634 | } | |
635 | ||
636 | static const struct drm_encoder_funcs oaktrail_hdmi_enc_funcs = { | |
637 | .destroy = oaktrail_hdmi_enc_destroy, | |
638 | }; | |
639 | ||
640 | void oaktrail_hdmi_init(struct drm_device *dev, | |
641 | struct psb_intel_mode_device *mode_dev) | |
642 | { | |
367e4408 | 643 | struct gma_encoder *gma_encoder; |
a3d5d75f | 644 | struct gma_connector *gma_connector; |
1b082ccf AC |
645 | struct drm_connector *connector; |
646 | struct drm_encoder *encoder; | |
647 | ||
367e4408 PJ |
648 | gma_encoder = kzalloc(sizeof(struct gma_encoder), GFP_KERNEL); |
649 | if (!gma_encoder) | |
1b082ccf AC |
650 | return; |
651 | ||
a3d5d75f PJ |
652 | gma_connector = kzalloc(sizeof(struct gma_connector), GFP_KERNEL); |
653 | if (!gma_connector) | |
9bd81acd PJ |
654 | goto failed_connector; |
655 | ||
a3d5d75f | 656 | connector = &gma_connector->base; |
367e4408 | 657 | encoder = &gma_encoder->base; |
9bd81acd | 658 | drm_connector_init(dev, connector, |
1b082ccf AC |
659 | &oaktrail_hdmi_connector_funcs, |
660 | DRM_MODE_CONNECTOR_DVID); | |
661 | ||
9bd81acd | 662 | drm_encoder_init(dev, encoder, |
1b082ccf AC |
663 | &oaktrail_hdmi_enc_funcs, |
664 | DRM_MODE_ENCODER_TMDS); | |
665 | ||
367e4408 | 666 | gma_connector_attach_encoder(gma_connector, gma_encoder); |
1b082ccf | 667 | |
367e4408 | 668 | gma_encoder->type = INTEL_OUTPUT_HDMI; |
1b082ccf AC |
669 | drm_encoder_helper_add(encoder, &oaktrail_hdmi_helper_funcs); |
670 | drm_connector_helper_add(connector, &oaktrail_hdmi_connector_helper_funcs); | |
671 | ||
672 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; | |
673 | connector->interlace_allowed = false; | |
674 | connector->doublescan_allowed = false; | |
675 | drm_sysfs_connector_add(connector); | |
39ec748f | 676 | dev_info(dev->dev, "HDMI initialised.\n"); |
1b082ccf AC |
677 | |
678 | return; | |
9bd81acd PJ |
679 | |
680 | failed_connector: | |
367e4408 | 681 | kfree(gma_encoder); |
1b082ccf AC |
682 | } |
683 | ||
684 | static DEFINE_PCI_DEVICE_TABLE(hdmi_ids) = { | |
685 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080d) }, | |
6e7f4573 | 686 | { 0 } |
1b082ccf AC |
687 | }; |
688 | ||
689 | void oaktrail_hdmi_setup(struct drm_device *dev) | |
690 | { | |
691 | struct drm_psb_private *dev_priv = dev->dev_private; | |
692 | struct pci_dev *pdev; | |
693 | struct oaktrail_hdmi_dev *hdmi_dev; | |
694 | int ret; | |
695 | ||
696 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x080d, NULL); | |
697 | if (!pdev) | |
698 | return; | |
699 | ||
700 | hdmi_dev = kzalloc(sizeof(struct oaktrail_hdmi_dev), GFP_KERNEL); | |
701 | if (!hdmi_dev) { | |
702 | dev_err(dev->dev, "failed to allocate memory\n"); | |
703 | goto out; | |
704 | } | |
705 | ||
706 | ||
707 | ret = pci_enable_device(pdev); | |
708 | if (ret) { | |
709 | dev_err(dev->dev, "failed to enable hdmi controller\n"); | |
710 | goto free; | |
711 | } | |
712 | ||
713 | hdmi_dev->mmio = pci_resource_start(pdev, 0); | |
714 | hdmi_dev->mmio_len = pci_resource_len(pdev, 0); | |
715 | hdmi_dev->regs = ioremap(hdmi_dev->mmio, hdmi_dev->mmio_len); | |
716 | if (!hdmi_dev->regs) { | |
717 | dev_err(dev->dev, "failed to map hdmi mmio\n"); | |
718 | goto free; | |
719 | } | |
720 | ||
721 | hdmi_dev->dev = pdev; | |
722 | pci_set_drvdata(pdev, hdmi_dev); | |
723 | ||
724 | /* Initialize i2c controller */ | |
725 | ret = oaktrail_hdmi_i2c_init(hdmi_dev->dev); | |
726 | if (ret) | |
727 | dev_err(dev->dev, "HDMI I2C initialization failed\n"); | |
728 | ||
729 | dev_priv->hdmi_priv = hdmi_dev; | |
730 | oaktrail_hdmi_audio_disable(dev); | |
39ec748f AC |
731 | |
732 | dev_info(dev->dev, "HDMI hardware present.\n"); | |
733 | ||
1b082ccf AC |
734 | return; |
735 | ||
736 | free: | |
737 | kfree(hdmi_dev); | |
738 | out: | |
739 | return; | |
740 | } | |
741 | ||
742 | void oaktrail_hdmi_teardown(struct drm_device *dev) | |
743 | { | |
744 | struct drm_psb_private *dev_priv = dev->dev_private; | |
745 | struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv; | |
746 | struct pci_dev *pdev; | |
747 | ||
748 | if (hdmi_dev) { | |
749 | pdev = hdmi_dev->dev; | |
750 | pci_set_drvdata(pdev, NULL); | |
751 | oaktrail_hdmi_i2c_exit(pdev); | |
752 | iounmap(hdmi_dev->regs); | |
753 | kfree(hdmi_dev); | |
754 | pci_dev_put(pdev); | |
755 | } | |
756 | } | |
757 | ||
758 | /* save HDMI register state */ | |
759 | void oaktrail_hdmi_save(struct drm_device *dev) | |
760 | { | |
761 | struct drm_psb_private *dev_priv = dev->dev_private; | |
762 | struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv; | |
c6265ff5 | 763 | struct psb_state *regs = &dev_priv->regs.psb; |
6256304b | 764 | struct psb_pipe *pipeb = &dev_priv->regs.pipe[1]; |
1b082ccf AC |
765 | int i; |
766 | ||
767 | /* dpll */ | |
768 | hdmi_dev->saveDPLL_CTRL = PSB_RVDC32(DPLL_CTRL); | |
769 | hdmi_dev->saveDPLL_DIV_CTRL = PSB_RVDC32(DPLL_DIV_CTRL); | |
770 | hdmi_dev->saveDPLL_ADJUST = PSB_RVDC32(DPLL_ADJUST); | |
771 | hdmi_dev->saveDPLL_UPDATE = PSB_RVDC32(DPLL_UPDATE); | |
772 | hdmi_dev->saveDPLL_CLK_ENABLE = PSB_RVDC32(DPLL_CLK_ENABLE); | |
773 | ||
774 | /* pipe B */ | |
6256304b AC |
775 | pipeb->conf = PSB_RVDC32(PIPEBCONF); |
776 | pipeb->src = PSB_RVDC32(PIPEBSRC); | |
777 | pipeb->htotal = PSB_RVDC32(HTOTAL_B); | |
778 | pipeb->hblank = PSB_RVDC32(HBLANK_B); | |
779 | pipeb->hsync = PSB_RVDC32(HSYNC_B); | |
780 | pipeb->vtotal = PSB_RVDC32(VTOTAL_B); | |
781 | pipeb->vblank = PSB_RVDC32(VBLANK_B); | |
782 | pipeb->vsync = PSB_RVDC32(VSYNC_B); | |
1b082ccf AC |
783 | |
784 | hdmi_dev->savePCH_PIPEBCONF = PSB_RVDC32(PCH_PIPEBCONF); | |
785 | hdmi_dev->savePCH_PIPEBSRC = PSB_RVDC32(PCH_PIPEBSRC); | |
786 | hdmi_dev->savePCH_HTOTAL_B = PSB_RVDC32(PCH_HTOTAL_B); | |
787 | hdmi_dev->savePCH_HBLANK_B = PSB_RVDC32(PCH_HBLANK_B); | |
788 | hdmi_dev->savePCH_HSYNC_B = PSB_RVDC32(PCH_HSYNC_B); | |
789 | hdmi_dev->savePCH_VTOTAL_B = PSB_RVDC32(PCH_VTOTAL_B); | |
790 | hdmi_dev->savePCH_VBLANK_B = PSB_RVDC32(PCH_VBLANK_B); | |
791 | hdmi_dev->savePCH_VSYNC_B = PSB_RVDC32(PCH_VSYNC_B); | |
792 | ||
793 | /* plane */ | |
6256304b AC |
794 | pipeb->cntr = PSB_RVDC32(DSPBCNTR); |
795 | pipeb->stride = PSB_RVDC32(DSPBSTRIDE); | |
796 | pipeb->addr = PSB_RVDC32(DSPBBASE); | |
797 | pipeb->surf = PSB_RVDC32(DSPBSURF); | |
798 | pipeb->linoff = PSB_RVDC32(DSPBLINOFF); | |
799 | pipeb->tileoff = PSB_RVDC32(DSPBTILEOFF); | |
1b082ccf AC |
800 | |
801 | /* cursor B */ | |
648a8e34 AC |
802 | regs->saveDSPBCURSOR_CTRL = PSB_RVDC32(CURBCNTR); |
803 | regs->saveDSPBCURSOR_BASE = PSB_RVDC32(CURBBASE); | |
804 | regs->saveDSPBCURSOR_POS = PSB_RVDC32(CURBPOS); | |
1b082ccf AC |
805 | |
806 | /* save palette */ | |
807 | for (i = 0; i < 256; i++) | |
6256304b | 808 | pipeb->palette[i] = PSB_RVDC32(PALETTE_B + (i << 2)); |
1b082ccf AC |
809 | } |
810 | ||
811 | /* restore HDMI register state */ | |
812 | void oaktrail_hdmi_restore(struct drm_device *dev) | |
813 | { | |
814 | struct drm_psb_private *dev_priv = dev->dev_private; | |
815 | struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv; | |
c6265ff5 | 816 | struct psb_state *regs = &dev_priv->regs.psb; |
6256304b | 817 | struct psb_pipe *pipeb = &dev_priv->regs.pipe[1]; |
1b082ccf AC |
818 | int i; |
819 | ||
820 | /* dpll */ | |
821 | PSB_WVDC32(hdmi_dev->saveDPLL_CTRL, DPLL_CTRL); | |
822 | PSB_WVDC32(hdmi_dev->saveDPLL_DIV_CTRL, DPLL_DIV_CTRL); | |
823 | PSB_WVDC32(hdmi_dev->saveDPLL_ADJUST, DPLL_ADJUST); | |
824 | PSB_WVDC32(hdmi_dev->saveDPLL_UPDATE, DPLL_UPDATE); | |
825 | PSB_WVDC32(hdmi_dev->saveDPLL_CLK_ENABLE, DPLL_CLK_ENABLE); | |
826 | DRM_UDELAY(150); | |
827 | ||
828 | /* pipe */ | |
6256304b AC |
829 | PSB_WVDC32(pipeb->src, PIPEBSRC); |
830 | PSB_WVDC32(pipeb->htotal, HTOTAL_B); | |
831 | PSB_WVDC32(pipeb->hblank, HBLANK_B); | |
832 | PSB_WVDC32(pipeb->hsync, HSYNC_B); | |
833 | PSB_WVDC32(pipeb->vtotal, VTOTAL_B); | |
834 | PSB_WVDC32(pipeb->vblank, VBLANK_B); | |
835 | PSB_WVDC32(pipeb->vsync, VSYNC_B); | |
1b082ccf AC |
836 | |
837 | PSB_WVDC32(hdmi_dev->savePCH_PIPEBSRC, PCH_PIPEBSRC); | |
838 | PSB_WVDC32(hdmi_dev->savePCH_HTOTAL_B, PCH_HTOTAL_B); | |
839 | PSB_WVDC32(hdmi_dev->savePCH_HBLANK_B, PCH_HBLANK_B); | |
840 | PSB_WVDC32(hdmi_dev->savePCH_HSYNC_B, PCH_HSYNC_B); | |
841 | PSB_WVDC32(hdmi_dev->savePCH_VTOTAL_B, PCH_VTOTAL_B); | |
842 | PSB_WVDC32(hdmi_dev->savePCH_VBLANK_B, PCH_VBLANK_B); | |
843 | PSB_WVDC32(hdmi_dev->savePCH_VSYNC_B, PCH_VSYNC_B); | |
844 | ||
6256304b | 845 | PSB_WVDC32(pipeb->conf, PIPEBCONF); |
1b082ccf AC |
846 | PSB_WVDC32(hdmi_dev->savePCH_PIPEBCONF, PCH_PIPEBCONF); |
847 | ||
848 | /* plane */ | |
6256304b AC |
849 | PSB_WVDC32(pipeb->linoff, DSPBLINOFF); |
850 | PSB_WVDC32(pipeb->stride, DSPBSTRIDE); | |
851 | PSB_WVDC32(pipeb->tileoff, DSPBTILEOFF); | |
852 | PSB_WVDC32(pipeb->cntr, DSPBCNTR); | |
853 | PSB_WVDC32(pipeb->surf, DSPBSURF); | |
1b082ccf AC |
854 | |
855 | /* cursor B */ | |
648a8e34 AC |
856 | PSB_WVDC32(regs->saveDSPBCURSOR_CTRL, CURBCNTR); |
857 | PSB_WVDC32(regs->saveDSPBCURSOR_POS, CURBPOS); | |
858 | PSB_WVDC32(regs->saveDSPBCURSOR_BASE, CURBBASE); | |
1b082ccf AC |
859 | |
860 | /* restore palette */ | |
861 | for (i = 0; i < 256; i++) | |
6256304b | 862 | PSB_WVDC32(pipeb->palette[i], PALETTE_B + (i << 2)); |
1b082ccf | 863 | } |