projects / linux-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/gma500: Add generic encoder functions
[linux-block.git] / drivers / gpu / drm / gma500 / cdv_intel_dp.c
CommitLineData
8695b612
AC		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
29#include <linux/slab.h>
16559ae4 30#include <linux/module.h>
612a9aab
LT		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
8695b612
AC		 34#include "psb_drv.h"
35#include "psb_intel_drv.h"
8695b612 36#include "psb_intel_reg.h"
d1fa08f3 37#include "gma_display.h"
612a9aab 38#include <drm/drm_dp_helper.h>
8695b612 39
d112a816
ZY		 40#define _wait_for(COND, MS, W) ({ \
41 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \
42 int ret__ = 0; \
43 while (! (COND)) { \
44 if (time_after(jiffies, timeout__)) { \
45 ret__ = -ETIMEDOUT; \
46 break; \
47 } \
48 if (W && !in_dbg_master()) msleep(W); \
49 } \
50 ret__; \
51})
52
53#define wait_for(COND, MS) _wait_for(COND, MS, 1)
8695b612
AC		 54
55#define DP_LINK_STATUS_SIZE 6
56#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
57
58#define DP_LINK_CONFIGURATION_SIZE 9
59
60#define CDV_FAST_LINK_TRAIN 1
61
37e7b184 62struct cdv_intel_dp {
8695b612
AC		 63 uint32_t output_reg;
64 uint32_t DP;
65 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
66 bool has_audio;
67 int force_audio;
68 uint32_t color_range;
69 uint8_t link_bw;
70 uint8_t lane_count;
71 uint8_t dpcd[4];
37e7b184 72 struct psb_intel_encoder *encoder;
8695b612
AC		 73 struct i2c_adapter adapter;
74 struct i2c_algo_dp_aux_data algo;
75 uint8_t train_set[4];
76 uint8_t link_status[DP_LINK_STATUS_SIZE];
d112a816
ZY		 77 int panel_power_up_delay;
78 int panel_power_down_delay;
79 int panel_power_cycle_delay;
80 int backlight_on_delay;
81 int backlight_off_delay;
82 struct drm_display_mode *panel_fixed_mode; /* for eDP */
83 bool panel_on;
8695b612
AC		 84};
85
86struct ddi_regoff {
87 uint32_t PreEmph1;
88 uint32_t PreEmph2;
89 uint32_t VSwing1;
90 uint32_t VSwing2;
91 uint32_t VSwing3;
92 uint32_t VSwing4;
93 uint32_t VSwing5;
94};
95
96static struct ddi_regoff ddi_DP_train_table[] = {
97 {.PreEmph1 = 0x812c, .PreEmph2 = 0x8124, .VSwing1 = 0x8154,
98 .VSwing2 = 0x8148, .VSwing3 = 0x814C, .VSwing4 = 0x8150,
99 .VSwing5 = 0x8158,},
100 {.PreEmph1 = 0x822c, .PreEmph2 = 0x8224, .VSwing1 = 0x8254,
101 .VSwing2 = 0x8248, .VSwing3 = 0x824C, .VSwing4 = 0x8250,
102 .VSwing5 = 0x8258,},
103};
104
105static uint32_t dp_vswing_premph_table[] = {
106 0x55338954, 0x4000,
107 0x554d8954, 0x2000,
108 0x55668954, 0,
109 0x559ac0d4, 0x6000,
110};
111/**
112 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
113 * @intel_dp: DP struct
114 *
115 * If a CPU or PCH DP output is attached to an eDP panel, this function
116 * will return true, and false otherwise.
117 */
37e7b184 118static bool is_edp(struct psb_intel_encoder *encoder)
8695b612 119{
37e7b184 120 return encoder->type == INTEL_OUTPUT_EDP;
8695b612
AC		 121}
122
123
37e7b184
AC		 124static void cdv_intel_dp_start_link_train(struct psb_intel_encoder *encoder);
125static void cdv_intel_dp_complete_link_train(struct psb_intel_encoder *encoder);
126static void cdv_intel_dp_link_down(struct psb_intel_encoder *encoder);
8695b612
AC		 127
128static int
37e7b184 129cdv_intel_dp_max_lane_count(struct psb_intel_encoder *encoder)
8695b612 130{
37e7b184 131 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
8695b612
AC		 132 int max_lane_count = 4;
133
134 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
135 max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
136 switch (max_lane_count) {
137 case 1: case 2: case 4:
138 break;
139 default:
140 max_lane_count = 4;
141 }
142 }
143 return max_lane_count;
144}
145
146static int
37e7b184 147cdv_intel_dp_max_link_bw(struct psb_intel_encoder *encoder)
8695b612 148{
37e7b184 149 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
8695b612
AC		 150 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
151
152 switch (max_link_bw) {
153 case DP_LINK_BW_1_62:
154 case DP_LINK_BW_2_7:
155 break;
156 default:
157 max_link_bw = DP_LINK_BW_1_62;
158 break;
159 }
160 return max_link_bw;
161}
162
163static int
37e7b184 164cdv_intel_dp_link_clock(uint8_t link_bw)
8695b612
AC		 165{
166 if (link_bw == DP_LINK_BW_2_7)
167 return 270000;
168 else
169 return 162000;
170}
171
172static int
37e7b184 173cdv_intel_dp_link_required(int pixel_clock, int bpp)
8695b612
AC		 174{
175 return (pixel_clock * bpp + 7) / 8;
176}
177
178static int
37e7b184 179cdv_intel_dp_max_data_rate(int max_link_clock, int max_lanes)
8695b612
AC		 180{
181 return (max_link_clock * max_lanes * 19) / 20;
182}
183
d112a816
ZY		 184static void cdv_intel_edp_panel_vdd_on(struct psb_intel_encoder *intel_encoder)
185{
186 struct drm_device *dev = intel_encoder->base.dev;
187 struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
188 u32 pp;
189
190 if (intel_dp->panel_on) {
191 DRM_DEBUG_KMS("Skip VDD on because of panel on\n");
192 return;
193 }
194 DRM_DEBUG_KMS("\n");
195
196 pp = REG_READ(PP_CONTROL);
197
198 pp |= EDP_FORCE_VDD;
199 REG_WRITE(PP_CONTROL, pp);
200 REG_READ(PP_CONTROL);
201 msleep(intel_dp->panel_power_up_delay);
202}
203
204static void cdv_intel_edp_panel_vdd_off(struct psb_intel_encoder *intel_encoder)
205{
206 struct drm_device *dev = intel_encoder->base.dev;
207 u32 pp;
208
209 DRM_DEBUG_KMS("\n");
210 pp = REG_READ(PP_CONTROL);
211
212 pp &= ~EDP_FORCE_VDD;
213 REG_WRITE(PP_CONTROL, pp);
214 REG_READ(PP_CONTROL);
215
216}
217
218/* Returns true if the panel was already on when called */
219static bool cdv_intel_edp_panel_on(struct psb_intel_encoder *intel_encoder)
220{
221 struct drm_device *dev = intel_encoder->base.dev;
222 struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
223 u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_NONE;
224
225 if (intel_dp->panel_on)
226 return true;
227
228 DRM_DEBUG_KMS("\n");
229 pp = REG_READ(PP_CONTROL);
230 pp &= ~PANEL_UNLOCK_MASK;
231
232 pp |= (PANEL_UNLOCK_REGS | POWER_TARGET_ON);
233 REG_WRITE(PP_CONTROL, pp);
234 REG_READ(PP_CONTROL);
235
236 if (wait_for(((REG_READ(PP_STATUS) & idle_on_mask) == idle_on_mask), 1000)) {
237 DRM_DEBUG_KMS("Error in Powering up eDP panel, status %x\n", REG_READ(PP_STATUS));
238 intel_dp->panel_on = false;
239 } else
240 intel_dp->panel_on = true;
241 msleep(intel_dp->panel_power_up_delay);
242
243 return false;
244}
245
246static void cdv_intel_edp_panel_off (struct psb_intel_encoder *intel_encoder)
247{
248 struct drm_device *dev = intel_encoder->base.dev;
249 u32 pp, idle_off_mask = PP_ON ;
250 struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
251
252 DRM_DEBUG_KMS("\n");
253
254 pp = REG_READ(PP_CONTROL);
255
256 if ((pp & POWER_TARGET_ON) == 0)
257 return;
258
259 intel_dp->panel_on = false;
260 pp &= ~PANEL_UNLOCK_MASK;
261 /* ILK workaround: disable reset around power sequence */
262
263 pp &= ~POWER_TARGET_ON;
264 pp &= ~EDP_FORCE_VDD;
265 pp &= ~EDP_BLC_ENABLE;
266 REG_WRITE(PP_CONTROL, pp);
267 REG_READ(PP_CONTROL);
268 DRM_DEBUG_KMS("PP_STATUS %x\n", REG_READ(PP_STATUS));
269
270 if (wait_for((REG_READ(PP_STATUS) & idle_off_mask) == 0, 1000)) {
271 DRM_DEBUG_KMS("Error in turning off Panel\n");
272 }
273
274 msleep(intel_dp->panel_power_cycle_delay);
275 DRM_DEBUG_KMS("Over\n");
276}
277
278static void cdv_intel_edp_backlight_on (struct psb_intel_encoder *intel_encoder)
279{
280 struct drm_device *dev = intel_encoder->base.dev;
281 u32 pp;
282
283 DRM_DEBUG_KMS("\n");
284 /*
285 * If we enable the backlight right away following a panel power
286 * on, we may see slight flicker as the panel syncs with the eDP
287 * link. So delay a bit to make sure the image is solid before
288 * allowing it to appear.
289 */
290 msleep(300);
291 pp = REG_READ(PP_CONTROL);
292
293 pp |= EDP_BLC_ENABLE;
294 REG_WRITE(PP_CONTROL, pp);
295 gma_backlight_enable(dev);
296}
297
298static void cdv_intel_edp_backlight_off (struct psb_intel_encoder *intel_encoder)
299{
300 struct drm_device *dev = intel_encoder->base.dev;
301 struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
302 u32 pp;
303
304 DRM_DEBUG_KMS("\n");
305 gma_backlight_disable(dev);
306 msleep(10);
307 pp = REG_READ(PP_CONTROL);
308
309 pp &= ~EDP_BLC_ENABLE;
310 REG_WRITE(PP_CONTROL, pp);
311 msleep(intel_dp->backlight_off_delay);
312}
313
8695b612 314static int
37e7b184 315cdv_intel_dp_mode_valid(struct drm_connector *connector,
8695b612
AC		 316 struct drm_display_mode *mode)
317{
37e7b184 318 struct psb_intel_encoder *encoder = psb_intel_attached_encoder(connector);
d112a816 319 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
37e7b184
AC		 320 int max_link_clock = cdv_intel_dp_link_clock(cdv_intel_dp_max_link_bw(encoder));
321 int max_lanes = cdv_intel_dp_max_lane_count(encoder);
d112a816 322 struct drm_psb_private *dev_priv = connector->dev->dev_private;
8695b612 323
d112a816
ZY		 324 if (is_edp(encoder) && intel_dp->panel_fixed_mode) {
325 if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
8695b612 326 return MODE_PANEL;
d112a816 327 if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
8695b612
AC		 328 return MODE_PANEL;
329 }
330
331 /* only refuse the mode on non eDP since we have seen some weird eDP panels
332 which are outside spec tolerances but somehow work by magic */
37e7b184 333 if (!is_edp(encoder) &&
d112a816 334 (cdv_intel_dp_link_required(mode->clock, dev_priv->edp.bpp)
37e7b184 335 > cdv_intel_dp_max_data_rate(max_link_clock, max_lanes)))
8695b612
AC		 336 return MODE_CLOCK_HIGH;
337
d112a816
ZY		 338 if (is_edp(encoder)) {
339 if (cdv_intel_dp_link_required(mode->clock, 24)
340 > cdv_intel_dp_max_data_rate(max_link_clock, max_lanes))
341 return MODE_CLOCK_HIGH;
342
343 }
8695b612
AC		 344 if (mode->clock < 10000)
345 return MODE_CLOCK_LOW;
346
347 return MODE_OK;
348}
349
350static uint32_t
351pack_aux(uint8_t *src, int src_bytes)
352{
353 int i;
354 uint32_t v = 0;
355
356 if (src_bytes > 4)
357 src_bytes = 4;
358 for (i = 0; i < src_bytes; i++)
359 v |= ((uint32_t) src[i]) << ((3-i) * 8);
360 return v;
361}
362
363static void
364unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
365{
366 int i;
367 if (dst_bytes > 4)
368 dst_bytes = 4;
369 for (i = 0; i < dst_bytes; i++)
370 dst[i] = src >> ((3-i) * 8);
371}
372
373static int
37e7b184 374cdv_intel_dp_aux_ch(struct psb_intel_encoder *encoder,
8695b612
AC		 375 uint8_t *send, int send_bytes,
376 uint8_t *recv, int recv_size)
377{
37e7b184 378 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
8695b612 379 uint32_t output_reg = intel_dp->output_reg;
37e7b184 380 struct drm_device *dev = encoder->base.dev;
8695b612
AC		 381 uint32_t ch_ctl = output_reg + 0x10;
382 uint32_t ch_data = ch_ctl + 4;
383 int i;
384 int recv_bytes;
385 uint32_t status;
386 uint32_t aux_clock_divider;
387 int try, precharge;
388
389 /* The clock divider is based off the hrawclk,
390 * and would like to run at 2MHz. So, take the
391 * hrawclk value and divide by 2 and use that
392 * On CDV platform it uses 200MHz as hrawclk.
393 *
394 */
395 aux_clock_divider = 200 / 2;
396
397 precharge = 4;
d112a816
ZY		 398 if (is_edp(encoder))
399 precharge = 10;
8695b612
AC		 400
401 if (REG_READ(ch_ctl) & DP_AUX_CH_CTL_SEND_BUSY) {
402 DRM_ERROR("dp_aux_ch not started status 0x%08x\n",
403 REG_READ(ch_ctl));
404 return -EBUSY;
405 }
406
407 /* Must try at least 3 times according to DP spec */
408 for (try = 0; try < 5; try++) {
409 /* Load the send data into the aux channel data registers */
410 for (i = 0; i < send_bytes; i += 4)
411 REG_WRITE(ch_data + i,
412 pack_aux(send + i, send_bytes - i));
413
414 /* Send the command and wait for it to complete */
415 REG_WRITE(ch_ctl,
416 DP_AUX_CH_CTL_SEND_BUSY |
417 DP_AUX_CH_CTL_TIME_OUT_400us |
418 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
419 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
420 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
421 DP_AUX_CH_CTL_DONE |
422 DP_AUX_CH_CTL_TIME_OUT_ERROR |
423 DP_AUX_CH_CTL_RECEIVE_ERROR);
424 for (;;) {
425 status = REG_READ(ch_ctl);
426 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
427 break;
428 udelay(100);
429 }
430
431 /* Clear done status and any errors */
432 REG_WRITE(ch_ctl,
433 status |
434 DP_AUX_CH_CTL_DONE |
435 DP_AUX_CH_CTL_TIME_OUT_ERROR |
436 DP_AUX_CH_CTL_RECEIVE_ERROR);
437 if (status & DP_AUX_CH_CTL_DONE)
438 break;
439 }
440
441 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
442 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
443 return -EBUSY;
444 }
445
446 /* Check for timeout or receive error.
447 * Timeouts occur when the sink is not connected
448 */
449 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
450 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
451 return -EIO;
452 }
453
454 /* Timeouts occur when the device isn't connected, so they're
455 * "normal" -- don't fill the kernel log with these */
456 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
457 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
458 return -ETIMEDOUT;
459 }
460
461 /* Unload any bytes sent back from the other side */
462 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
463 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
464 if (recv_bytes > recv_size)
465 recv_bytes = recv_size;
466
467 for (i = 0; i < recv_bytes; i += 4)
468 unpack_aux(REG_READ(ch_data + i),
469 recv + i, recv_bytes - i);
470
471 return recv_bytes;
472}
473
474/* Write data to the aux channel in native mode */
475static int
37e7b184 476cdv_intel_dp_aux_native_write(struct psb_intel_encoder *encoder,
8695b612
AC		 477 uint16_t address, uint8_t *send, int send_bytes)
478{
479 int ret;
480 uint8_t msg[20];
481 int msg_bytes;
482 uint8_t ack;
483
484 if (send_bytes > 16)
485 return -1;
486 msg[0] = AUX_NATIVE_WRITE << 4;
487 msg[1] = address >> 8;
488 msg[2] = address & 0xff;
489 msg[3] = send_bytes - 1;
490 memcpy(&msg[4], send, send_bytes);
491 msg_bytes = send_bytes + 4;
492 for (;;) {
37e7b184 493 ret = cdv_intel_dp_aux_ch(encoder, msg, msg_bytes, &ack, 1);
8695b612
AC		 494 if (ret < 0)
495 return ret;
496 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
497 break;
498 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
499 udelay(100);
500 else
501 return -EIO;
502 }
503 return send_bytes;
504}
505
506/* Write a single byte to the aux channel in native mode */
507static int
37e7b184 508cdv_intel_dp_aux_native_write_1(struct psb_intel_encoder *encoder,
8695b612
AC		 509 uint16_t address, uint8_t byte)
510{
37e7b184 511 return cdv_intel_dp_aux_native_write(encoder, address, &byte, 1);
8695b612
AC		 512}
513
514/* read bytes from a native aux channel */
515static int
37e7b184 516cdv_intel_dp_aux_native_read(struct psb_intel_encoder *encoder,
8695b612
AC		 517 uint16_t address, uint8_t *recv, int recv_bytes)
518{
519 uint8_t msg[4];
520 int msg_bytes;
521 uint8_t reply[20];
522 int reply_bytes;
523 uint8_t ack;
524 int ret;
525
526 msg[0] = AUX_NATIVE_READ << 4;
527 msg[1] = address >> 8;
528 msg[2] = address & 0xff;
529 msg[3] = recv_bytes - 1;
530
531 msg_bytes = 4;
532 reply_bytes = recv_bytes + 1;
533
534 for (;;) {
37e7b184 535 ret = cdv_intel_dp_aux_ch(encoder, msg, msg_bytes,
8695b612
AC		 536 reply, reply_bytes);
537 if (ret == 0)
538 return -EPROTO;
539 if (ret < 0)
540 return ret;
541 ack = reply[0];
542 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
543 memcpy(recv, reply + 1, ret - 1);
544 return ret - 1;
545 }
546 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
547 udelay(100);
548 else
549 return -EIO;
550 }
551}
552
553static int
37e7b184 554cdv_intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
8695b612
AC		 555 uint8_t write_byte, uint8_t *read_byte)
556{
557 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
37e7b184
AC		 558 struct cdv_intel_dp *intel_dp = container_of(adapter,
559 struct cdv_intel_dp,
8695b612 560 adapter);
37e7b184 561 struct psb_intel_encoder *encoder = intel_dp->encoder;
8695b612
AC		 562 uint16_t address = algo_data->address;
563 uint8_t msg[5];
564 uint8_t reply[2];
565 unsigned retry;
566 int msg_bytes;
567 int reply_bytes;
568 int ret;
569
570 /* Set up the command byte */
571 if (mode & MODE_I2C_READ)
572 msg[0] = AUX_I2C_READ << 4;
573 else
574 msg[0] = AUX_I2C_WRITE << 4;
575
576 if (!(mode & MODE_I2C_STOP))
577 msg[0] |= AUX_I2C_MOT << 4;
578
579 msg[1] = address >> 8;
580 msg[2] = address;
581
582 switch (mode) {
583 case MODE_I2C_WRITE:
584 msg[3] = 0;
585 msg[4] = write_byte;
586 msg_bytes = 5;
587 reply_bytes = 1;
588 break;
589 case MODE_I2C_READ:
590 msg[3] = 0;
591 msg_bytes = 4;
592 reply_bytes = 2;
593 break;
594 default:
595 msg_bytes = 3;
596 reply_bytes = 1;
597 break;
598 }
599
600 for (retry = 0; retry < 5; retry++) {
37e7b184 601 ret = cdv_intel_dp_aux_ch(encoder,
8695b612
AC		 602 msg, msg_bytes,
603 reply, reply_bytes);
604 if (ret < 0) {
605 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
606 return ret;
607 }
608
609 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
610 case AUX_NATIVE_REPLY_ACK:
611 /* I2C-over-AUX Reply field is only valid
612 * when paired with AUX ACK.
613 */
614 break;
615 case AUX_NATIVE_REPLY_NACK:
616 DRM_DEBUG_KMS("aux_ch native nack\n");
617 return -EREMOTEIO;
618 case AUX_NATIVE_REPLY_DEFER:
619 udelay(100);
620 continue;
621 default:
622 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
623 reply[0]);
624 return -EREMOTEIO;
625 }
626
627 switch (reply[0] & AUX_I2C_REPLY_MASK) {
628 case AUX_I2C_REPLY_ACK:
629 if (mode == MODE_I2C_READ) {
630 *read_byte = reply[1];
631 }
632 return reply_bytes - 1;
633 case AUX_I2C_REPLY_NACK:
634 DRM_DEBUG_KMS("aux_i2c nack\n");
635 return -EREMOTEIO;
636 case AUX_I2C_REPLY_DEFER:
637 DRM_DEBUG_KMS("aux_i2c defer\n");
638 udelay(100);
639 break;
640 default:
641 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
642 return -EREMOTEIO;
643 }
644 }
645
646 DRM_ERROR("too many retries, giving up\n");
647 return -EREMOTEIO;
648}
649
650static int
37e7b184 651cdv_intel_dp_i2c_init(struct psb_intel_connector *connector, struct psb_intel_encoder *encoder, const char *name)
8695b612 652{
37e7b184 653 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
d112a816
ZY		 654 int ret;
655
8695b612 656 DRM_DEBUG_KMS("i2c_init %s\n", name);
d112a816 657
8695b612
AC		 658 intel_dp->algo.running = false;
659 intel_dp->algo.address = 0;
37e7b184 660 intel_dp->algo.aux_ch = cdv_intel_dp_i2c_aux_ch;
8695b612
AC		 661
662 memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter));
663 intel_dp->adapter.owner = THIS_MODULE;
664 intel_dp->adapter.class = I2C_CLASS_DDC;
665 strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
666 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
667 intel_dp->adapter.algo_data = &intel_dp->algo;
37e7b184 668 intel_dp->adapter.dev.parent = &connector->base.kdev;
8695b612 669
d112a816
ZY		 670 if (is_edp(encoder))
671 cdv_intel_edp_panel_vdd_on(encoder);
672 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
673 if (is_edp(encoder))
674 cdv_intel_edp_panel_vdd_off(encoder);
675
676 return ret;
677}
678
679void cdv_intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
680 struct drm_display_mode *adjusted_mode)
681{
682 adjusted_mode->hdisplay = fixed_mode->hdisplay;
683 adjusted_mode->hsync_start = fixed_mode->hsync_start;
684 adjusted_mode->hsync_end = fixed_mode->hsync_end;
685 adjusted_mode->htotal = fixed_mode->htotal;
686
687 adjusted_mode->vdisplay = fixed_mode->vdisplay;
688 adjusted_mode->vsync_start = fixed_mode->vsync_start;
689 adjusted_mode->vsync_end = fixed_mode->vsync_end;
690 adjusted_mode->vtotal = fixed_mode->vtotal;
691
692 adjusted_mode->clock = fixed_mode->clock;
693
694 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
8695b612
AC		 695}
696
697static bool
37e7b184 698cdv_intel_dp_mode_fixup(struct drm_encoder *encoder, const struct drm_display_mode *mode,
8695b612
AC		 699 struct drm_display_mode *adjusted_mode)
700{
d112a816 701 struct drm_psb_private *dev_priv = encoder->dev->dev_private;
37e7b184
AC		 702 struct psb_intel_encoder *intel_encoder = to_psb_intel_encoder(encoder);
703 struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
8695b612 704 int lane_count, clock;
37e7b184
AC		 705 int max_lane_count = cdv_intel_dp_max_lane_count(intel_encoder);
706 int max_clock = cdv_intel_dp_max_link_bw(intel_encoder) == DP_LINK_BW_2_7 ? 1 : 0;
8695b612 707 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
d112a816
ZY		 708 int refclock = mode->clock;
709 int bpp = 24;
8695b612 710
d112a816
ZY		 711 if (is_edp(intel_encoder) && intel_dp->panel_fixed_mode) {
712 cdv_intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
713 refclock = intel_dp->panel_fixed_mode->clock;
714 bpp = dev_priv->edp.bpp;
715 }
8695b612
AC		 716
717 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
718 for (clock = max_clock; clock >= 0; clock--) {
37e7b184 719 int link_avail = cdv_intel_dp_max_data_rate(cdv_intel_dp_link_clock(bws[clock]), lane_count);
8695b612 720
d112a816 721 if (cdv_intel_dp_link_required(refclock, bpp) <= link_avail) {
8695b612
AC		 722 intel_dp->link_bw = bws[clock];
723 intel_dp->lane_count = lane_count;
37e7b184 724 adjusted_mode->clock = cdv_intel_dp_link_clock(intel_dp->link_bw);
8695b612
AC		 725 DRM_DEBUG_KMS("Display port link bw %02x lane "
726 "count %d clock %d\n",
727 intel_dp->link_bw, intel_dp->lane_count,
728 adjusted_mode->clock);
729 return true;
730 }
731 }
732 }
d112a816
ZY		 733 if (is_edp(intel_encoder)) {
734 /* okay we failed just pick the highest */
735 intel_dp->lane_count = max_lane_count;
736 intel_dp->link_bw = bws[max_clock];
737 adjusted_mode->clock = cdv_intel_dp_link_clock(intel_dp->link_bw);
738 DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
739 "count %d clock %d\n",
740 intel_dp->link_bw, intel_dp->lane_count,
741 adjusted_mode->clock);
742
743 return true;
744 }
8695b612
AC		 745 return false;
746}
747
37e7b184 748struct cdv_intel_dp_m_n {
8695b612
AC		 749 uint32_t tu;
750 uint32_t gmch_m;
751 uint32_t gmch_n;
752 uint32_t link_m;
753 uint32_t link_n;
754};
755
756static void
d112a816 757cdv_intel_reduce_ratio(uint32_t *num, uint32_t *den)
8695b612
AC		 758{
759 /*
760 while (*num > 0xffffff || *den > 0xffffff) {
761 *num >>= 1;
762 *den >>= 1;
763 }*/
764 uint64_t value, m;
765 m = *num;
766 value = m * (0x800000);
767 m = do_div(value, *den);
768 *num = value;
769 *den = 0x800000;
770}
771
772static void
37e7b184 773cdv_intel_dp_compute_m_n(int bpp,
8695b612
AC		 774 int nlanes,
775 int pixel_clock,
776 int link_clock,
37e7b184 777 struct cdv_intel_dp_m_n *m_n)
8695b612
AC		 778{
779 m_n->tu = 64;
780 m_n->gmch_m = (pixel_clock * bpp + 7) >> 3;
781 m_n->gmch_n = link_clock * nlanes;
d112a816 782 cdv_intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
8695b612
AC		 783 m_n->link_m = pixel_clock;
784 m_n->link_n = link_clock;
d112a816 785 cdv_intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
8695b612
AC		 786}
787
788void
37e7b184 789cdv_intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
8695b612
AC		 790 struct drm_display_mode *adjusted_mode)
791{
792 struct drm_device *dev = crtc->dev;
d112a816 793 struct drm_psb_private *dev_priv = dev->dev_private;
8695b612
AC		 794 struct drm_mode_config *mode_config = &dev->mode_config;
795 struct drm_encoder *encoder;
796 struct psb_intel_crtc *intel_crtc = to_psb_intel_crtc(crtc);
797 int lane_count = 4, bpp = 24;
37e7b184 798 struct cdv_intel_dp_m_n m_n;
8695b612
AC		 799 int pipe = intel_crtc->pipe;
800
801 /*
802 * Find the lane count in the intel_encoder private
803 */
804 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
37e7b184
AC		 805 struct psb_intel_encoder *intel_encoder;
806 struct cdv_intel_dp *intel_dp;
8695b612
AC		 807
808 if (encoder->crtc != crtc)
809 continue;
810
37e7b184
AC		 811 intel_encoder = to_psb_intel_encoder(encoder);
812 intel_dp = intel_encoder->dev_priv;
813 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
8695b612
AC		 814 lane_count = intel_dp->lane_count;
815 break;
37e7b184 816 } else if (is_edp(intel_encoder)) {
8695b612 817 lane_count = intel_dp->lane_count;
d112a816 818 bpp = dev_priv->edp.bpp;
8695b612
AC		 819 break;
820 }
821 }
822
823 /*
824 * Compute the GMCH and Link ratios. The '3' here is
825 * the number of bytes_per_pixel post-LUT, which we always
826 * set up for 8-bits of R/G/B, or 3 bytes total.
827 */
37e7b184 828 cdv_intel_dp_compute_m_n(bpp, lane_count,
8695b612
AC		 829 mode->clock, adjusted_mode->clock, &m_n);
830
831 {
832 REG_WRITE(PIPE_GMCH_DATA_M(pipe),
833 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
834 m_n.gmch_m);
835 REG_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
836 REG_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
837 REG_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
838 }
839}
840
841static void
37e7b184 842cdv_intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
8695b612
AC		 843 struct drm_display_mode *adjusted_mode)
844{
37e7b184 845 struct psb_intel_encoder *intel_encoder = to_psb_intel_encoder(encoder);
8695b612
AC		 846 struct drm_crtc *crtc = encoder->crtc;
847 struct psb_intel_crtc *intel_crtc = to_psb_intel_crtc(crtc);
37e7b184 848 struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
d112a816 849 struct drm_device *dev = encoder->dev;
8695b612
AC		 850
851 intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
852 intel_dp->DP |= intel_dp->color_range;
853
854 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
855 intel_dp->DP |= DP_SYNC_HS_HIGH;
856 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
857 intel_dp->DP |= DP_SYNC_VS_HIGH;
858
859 intel_dp->DP |= DP_LINK_TRAIN_OFF;
860
861 switch (intel_dp->lane_count) {
862 case 1:
863 intel_dp->DP |= DP_PORT_WIDTH_1;
864 break;
865 case 2:
866 intel_dp->DP |= DP_PORT_WIDTH_2;
867 break;
868 case 4:
869 intel_dp->DP |= DP_PORT_WIDTH_4;
870 break;
871 }
872 if (intel_dp->has_audio)
873 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
874
875 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
876 intel_dp->link_configuration[0] = intel_dp->link_bw;
877 intel_dp->link_configuration[1] = intel_dp->lane_count;
878
879 /*
880 * Check for DPCD version > 1.1 and enhanced framing support
881 */
882 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
883 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
884 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
885 intel_dp->DP |= DP_ENHANCED_FRAMING;
886 }
887
888 /* CPT DP's pipe select is decided in TRANS_DP_CTL */
889 if (intel_crtc->pipe == 1)
890 intel_dp->DP |= DP_PIPEB_SELECT;
891
d112a816 892 REG_WRITE(intel_dp->output_reg, (intel_dp->DP | DP_PORT_EN));
8695b612 893 DRM_DEBUG_KMS("DP expected reg is %x\n", intel_dp->DP);
d112a816
ZY		 894 if (is_edp(intel_encoder)) {
895 uint32_t pfit_control;
896 cdv_intel_edp_panel_on(intel_encoder);
897
898 if (mode->hdisplay != adjusted_mode->hdisplay ||
899 mode->vdisplay != adjusted_mode->vdisplay)
900 pfit_control = PFIT_ENABLE;
901 else
902 pfit_control = 0;
903
904 pfit_control |= intel_crtc->pipe << PFIT_PIPE_SHIFT;
905
906 REG_WRITE(PFIT_CONTROL, pfit_control);
907 }
8695b612
AC		 908}
909
910
911/* If the sink supports it, try to set the power state appropriately */
37e7b184 912static void cdv_intel_dp_sink_dpms(struct psb_intel_encoder *encoder, int mode)
8695b612 913{
37e7b184 914 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
8695b612
AC		 915 int ret, i;
916
917 /* Should have a valid DPCD by this point */
918 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
919 return;
920
921 if (mode != DRM_MODE_DPMS_ON) {
37e7b184 922 ret = cdv_intel_dp_aux_native_write_1(encoder, DP_SET_POWER,
8695b612
AC		 923 DP_SET_POWER_D3);
924 if (ret != 1)
925 DRM_DEBUG_DRIVER("failed to write sink power state\n");
926 } else {
927 /*
928 * When turning on, we need to retry for 1ms to give the sink
929 * time to wake up.
930 */
931 for (i = 0; i < 3; i++) {
37e7b184 932 ret = cdv_intel_dp_aux_native_write_1(encoder,
8695b612
AC		 933 DP_SET_POWER,
934 DP_SET_POWER_D0);
935 if (ret == 1)
936 break;
937 udelay(1000);
938 }
939 }
940}
941
37e7b184 942static void cdv_intel_dp_prepare(struct drm_encoder *encoder)
8695b612 943{
37e7b184 944 struct psb_intel_encoder *intel_encoder = to_psb_intel_encoder(encoder);
d112a816 945 int edp = is_edp(intel_encoder);
8695b612 946
d112a816
ZY		 947 if (edp) {
948 cdv_intel_edp_backlight_off(intel_encoder);
949 cdv_intel_edp_panel_off(intel_encoder);
950 cdv_intel_edp_panel_vdd_on(intel_encoder);
951 }
8695b612 952 /* Wake up the sink first */
37e7b184
AC		 953 cdv_intel_dp_sink_dpms(intel_encoder, DRM_MODE_DPMS_ON);
954 cdv_intel_dp_link_down(intel_encoder);
d112a816
ZY		 955 if (edp)
956 cdv_intel_edp_panel_vdd_off(intel_encoder);
8695b612
AC		 957}
958
37e7b184 959static void cdv_intel_dp_commit(struct drm_encoder *encoder)
8695b612 960{
37e7b184 961 struct psb_intel_encoder *intel_encoder = to_psb_intel_encoder(encoder);
d112a816 962 int edp = is_edp(intel_encoder);
8695b612 963
d112a816
ZY		 964 if (edp)
965 cdv_intel_edp_panel_on(intel_encoder);
37e7b184
AC		 966 cdv_intel_dp_start_link_train(intel_encoder);
967 cdv_intel_dp_complete_link_train(intel_encoder);
d112a816
ZY		 968 if (edp)
969 cdv_intel_edp_backlight_on(intel_encoder);
8695b612
AC		 970}
971
972static void
37e7b184 973cdv_intel_dp_dpms(struct drm_encoder *encoder, int mode)
8695b612 974{
37e7b184
AC		 975 struct psb_intel_encoder *intel_encoder = to_psb_intel_encoder(encoder);
976 struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
8695b612
AC		 977 struct drm_device *dev = encoder->dev;
978 uint32_t dp_reg = REG_READ(intel_dp->output_reg);
d112a816 979 int edp = is_edp(intel_encoder);
8695b612
AC		 980
981 if (mode != DRM_MODE_DPMS_ON) {
d112a816
ZY		 982 if (edp) {
983 cdv_intel_edp_backlight_off(intel_encoder);
984 cdv_intel_edp_panel_vdd_on(intel_encoder);
985 }
37e7b184
AC		 986 cdv_intel_dp_sink_dpms(intel_encoder, mode);
987 cdv_intel_dp_link_down(intel_encoder);
d112a816
ZY		 988 if (edp) {
989 cdv_intel_edp_panel_vdd_off(intel_encoder);
990 cdv_intel_edp_panel_off(intel_encoder);
991 }
8695b612 992 } else {
d112a816
ZY		 993 if (edp)
994 cdv_intel_edp_panel_on(intel_encoder);
37e7b184 995 cdv_intel_dp_sink_dpms(intel_encoder, mode);
8695b612 996 if (!(dp_reg & DP_PORT_EN)) {
37e7b184
AC		 997 cdv_intel_dp_start_link_train(intel_encoder);
998 cdv_intel_dp_complete_link_train(intel_encoder);
8695b612 999 }
d112a816
ZY		 1000 if (edp)
1001 cdv_intel_edp_backlight_on(intel_encoder);
8695b612
AC		 1002 }
1003}
1004
1005/*
1006 * Native read with retry for link status and receiver capability reads for
1007 * cases where the sink may still be asleep.
1008 */
1009static bool
37e7b184 1010cdv_intel_dp_aux_native_read_retry(struct psb_intel_encoder *encoder, uint16_t address,
8695b612
AC		 1011 uint8_t *recv, int recv_bytes)
1012{
1013 int ret, i;
1014
1015 /*
1016 * Sinks are *supposed* to come up within 1ms from an off state,
1017 * but we're also supposed to retry 3 times per the spec.
1018 */
1019 for (i = 0; i < 3; i++) {
37e7b184 1020 ret = cdv_intel_dp_aux_native_read(encoder, address, recv,
8695b612
AC		 1021 recv_bytes);
1022 if (ret == recv_bytes)
1023 return true;
1024 udelay(1000);
1025 }
1026
1027 return false;
1028}
1029
1030/*
1031 * Fetch AUX CH registers 0x202 - 0x207 which contain
1032 * link status information
1033 */
1034static bool
37e7b184 1035cdv_intel_dp_get_link_status(struct psb_intel_encoder *encoder)
8695b612 1036{
37e7b184
AC		 1037 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
1038 return cdv_intel_dp_aux_native_read_retry(encoder,
8695b612
AC		 1039 DP_LANE0_1_STATUS,
1040 intel_dp->link_status,
1041 DP_LINK_STATUS_SIZE);
1042}
1043
1044static uint8_t
37e7b184 1045cdv_intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
8695b612
AC		 1046 int r)
1047{
1048 return link_status[r - DP_LANE0_1_STATUS];
1049}
1050
1051static uint8_t
37e7b184 1052cdv_intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
8695b612
AC		 1053 int lane)
1054{
1055 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1056 int s = ((lane & 1) ?
1057 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1058 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
37e7b184 1059 uint8_t l = cdv_intel_dp_link_status(link_status, i);
8695b612
AC		 1060
1061 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1062}
1063
1064static uint8_t
37e7b184 1065cdv_intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
8695b612
AC		 1066 int lane)
1067{
1068 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1069 int s = ((lane & 1) ?
1070 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1071 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
37e7b184 1072 uint8_t l = cdv_intel_dp_link_status(link_status, i);
8695b612
AC		 1073
1074 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1075}
1076
1077
1078#if 0
1079static char *voltage_names[] = {
1080 "0.4V", "0.6V", "0.8V", "1.2V"
1081};
1082static char *pre_emph_names[] = {
1083 "0dB", "3.5dB", "6dB", "9.5dB"
1084};
1085static char *link_train_names[] = {
1086 "pattern 1", "pattern 2", "idle", "off"
1087};
1088#endif
1089
1090#define CDV_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200
1091/*
1092static uint8_t
37e7b184 1093cdv_intel_dp_pre_emphasis_max(uint8_t voltage_swing)
8695b612
AC		 1094{
1095 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1096 case DP_TRAIN_VOLTAGE_SWING_400:
1097 return DP_TRAIN_PRE_EMPHASIS_6;
1098 case DP_TRAIN_VOLTAGE_SWING_600:
1099 return DP_TRAIN_PRE_EMPHASIS_6;
1100 case DP_TRAIN_VOLTAGE_SWING_800:
1101 return DP_TRAIN_PRE_EMPHASIS_3_5;
1102 case DP_TRAIN_VOLTAGE_SWING_1200:
1103 default:
1104 return DP_TRAIN_PRE_EMPHASIS_0;
1105 }
1106}
1107*/
1108static void
37e7b184 1109cdv_intel_get_adjust_train(struct psb_intel_encoder *encoder)
8695b612 1110{
37e7b184 1111 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
8695b612
AC		 1112 uint8_t v = 0;
1113 uint8_t p = 0;
1114 int lane;
1115
1116 for (lane = 0; lane < intel_dp->lane_count; lane++) {
37e7b184
AC		 1117 uint8_t this_v = cdv_intel_get_adjust_request_voltage(intel_dp->link_status, lane);
1118 uint8_t this_p = cdv_intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane);
8695b612
AC		 1119
1120 if (this_v > v)
1121 v = this_v;
1122 if (this_p > p)
1123 p = this_p;
1124 }
1125
1126 if (v >= CDV_DP_VOLTAGE_MAX)
1127 v = CDV_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
1128
1129 if (p == DP_TRAIN_PRE_EMPHASIS_MASK)
1130 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1131
1132 for (lane = 0; lane < 4; lane++)
1133 intel_dp->train_set[lane] = v | p;
1134}
1135
1136
1137static uint8_t
37e7b184 1138cdv_intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
8695b612
AC		 1139 int lane)
1140{
1141 int i = DP_LANE0_1_STATUS + (lane >> 1);
1142 int s = (lane & 1) * 4;
37e7b184 1143 uint8_t l = cdv_intel_dp_link_status(link_status, i);
8695b612
AC		 1144
1145 return (l >> s) & 0xf;
1146}
1147
1148/* Check for clock recovery is done on all channels */
1149static bool
37e7b184 1150cdv_intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
8695b612
AC		 1151{
1152 int lane;
1153 uint8_t lane_status;
1154
1155 for (lane = 0; lane < lane_count; lane++) {
37e7b184 1156 lane_status = cdv_intel_get_lane_status(link_status, lane);
8695b612
AC		 1157 if ((lane_status & DP_LANE_CR_DONE) == 0)
1158 return false;
1159 }
1160 return true;
1161}
1162
1163/* Check to see if channel eq is done on all channels */
1164#define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1165 DP_LANE_CHANNEL_EQ_DONE|\
1166 DP_LANE_SYMBOL_LOCKED)
1167static bool
37e7b184 1168cdv_intel_channel_eq_ok(struct psb_intel_encoder *encoder)
8695b612 1169{
37e7b184 1170 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
8695b612
AC		 1171 uint8_t lane_align;
1172 uint8_t lane_status;
1173 int lane;
1174
37e7b184 1175 lane_align = cdv_intel_dp_link_status(intel_dp->link_status,
8695b612
AC		 1176 DP_LANE_ALIGN_STATUS_UPDATED);
1177 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1178 return false;
1179 for (lane = 0; lane < intel_dp->lane_count; lane++) {
37e7b184 1180 lane_status = cdv_intel_get_lane_status(intel_dp->link_status, lane);
8695b612
AC		 1181 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1182 return false;
1183 }
1184 return true;
1185}
1186
1187static bool
37e7b184 1188cdv_intel_dp_set_link_train(struct psb_intel_encoder *encoder,
8695b612
AC		 1189 uint32_t dp_reg_value,
1190 uint8_t dp_train_pat)
1191{
1192
37e7b184 1193 struct drm_device *dev = encoder->base.dev;
8695b612 1194 int ret;
37e7b184 1195 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
8695b612
AC		 1196
1197 REG_WRITE(intel_dp->output_reg, dp_reg_value);
1198 REG_READ(intel_dp->output_reg);
1199
37e7b184 1200 ret = cdv_intel_dp_aux_native_write_1(encoder,
8695b612
AC		 1201 DP_TRAINING_PATTERN_SET,
1202 dp_train_pat);
1203
1204 if (ret != 1) {
1205 DRM_DEBUG_KMS("Failure in setting link pattern %x\n",
1206 dp_train_pat);
1207 return false;
1208 }
1209
1210 return true;
1211}
1212
1213
1214static bool
37e7b184 1215cdv_intel_dplink_set_level(struct psb_intel_encoder *encoder,
8695b612
AC		 1216 uint8_t dp_train_pat)
1217{
1218
1219 int ret;
37e7b184 1220 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
8695b612 1221
37e7b184 1222 ret = cdv_intel_dp_aux_native_write(encoder,
8695b612
AC		 1223 DP_TRAINING_LANE0_SET,
1224 intel_dp->train_set,
1225 intel_dp->lane_count);
1226
1227 if (ret != intel_dp->lane_count) {
1228 DRM_DEBUG_KMS("Failure in setting level %d, lane_cnt= %d\n",
1229 intel_dp->train_set[0], intel_dp->lane_count);
1230 return false;
1231 }
1232 return true;
1233}
1234
1235static void
37e7b184 1236cdv_intel_dp_set_vswing_premph(struct psb_intel_encoder *encoder, uint8_t signal_level)
8695b612 1237{
37e7b184
AC		 1238 struct drm_device *dev = encoder->base.dev;
1239 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
8695b612
AC		 1240 struct ddi_regoff *ddi_reg;
1241 int vswing, premph, index;
1242
1243 if (intel_dp->output_reg == DP_B)
1244 ddi_reg = &ddi_DP_train_table[0];
1245 else
1246 ddi_reg = &ddi_DP_train_table[1];
1247
1248 vswing = (signal_level & DP_TRAIN_VOLTAGE_SWING_MASK);
1249 premph = ((signal_level & DP_TRAIN_PRE_EMPHASIS_MASK)) >>
1250 DP_TRAIN_PRE_EMPHASIS_SHIFT;
1251
1252 if (vswing + premph > 3)
1253 return;
1254#ifdef CDV_FAST_LINK_TRAIN
1255 return;
1256#endif
1257 DRM_DEBUG_KMS("Test2\n");
1258 //return ;
37e7b184 1259 cdv_sb_reset(dev);
8695b612
AC		 1260 /* ;Swing voltage programming
1261 ;gfx_dpio_set_reg(0xc058, 0x0505313A) */
37e7b184 1262 cdv_sb_write(dev, ddi_reg->VSwing5, 0x0505313A);
8695b612
AC		 1263
1264 /* ;gfx_dpio_set_reg(0x8154, 0x43406055) */
37e7b184 1265 cdv_sb_write(dev, ddi_reg->VSwing1, 0x43406055);
8695b612
AC		 1266
1267 /* ;gfx_dpio_set_reg(0x8148, 0x55338954)
1268 * The VSwing_PreEmph table is also considered based on the vswing/premp
1269 */
1270 index = (vswing + premph) * 2;
1271 if (premph == 1 && vswing == 1) {
37e7b184 1272 cdv_sb_write(dev, ddi_reg->VSwing2, 0x055738954);
8695b612 1273 } else
37e7b184 1274 cdv_sb_write(dev, ddi_reg->VSwing2, dp_vswing_premph_table[index]);
8695b612
AC		 1275
1276 /* ;gfx_dpio_set_reg(0x814c, 0x40802040) */
1277 if ((vswing + premph) == DP_TRAIN_VOLTAGE_SWING_1200)
37e7b184 1278 cdv_sb_write(dev, ddi_reg->VSwing3, 0x70802040);
8695b612 1279 else
37e7b184 1280 cdv_sb_write(dev, ddi_reg->VSwing3, 0x40802040);
8695b612
AC		 1281
1282 /* ;gfx_dpio_set_reg(0x8150, 0x2b405555) */
37e7b184 1283 /* cdv_sb_write(dev, ddi_reg->VSwing4, 0x2b405555); */
8695b612
AC		 1284
1285 /* ;gfx_dpio_set_reg(0x8154, 0xc3406055) */
37e7b184 1286 cdv_sb_write(dev, ddi_reg->VSwing1, 0xc3406055);
8695b612
AC		 1287
1288 /* ;Pre emphasis programming
1289 * ;gfx_dpio_set_reg(0xc02c, 0x1f030040)
1290 */
37e7b184 1291 cdv_sb_write(dev, ddi_reg->PreEmph1, 0x1f030040);
8695b612
AC		 1292
1293 /* ;gfx_dpio_set_reg(0x8124, 0x00004000) */
1294 index = 2 * premph + 1;
37e7b184 1295 cdv_sb_write(dev, ddi_reg->PreEmph2, dp_vswing_premph_table[index]);
8695b612
AC		 1296 return;
1297}
1298
1299
1300/* Enable corresponding port and start training pattern 1 */
1301static void
37e7b184 1302cdv_intel_dp_start_link_train(struct psb_intel_encoder *encoder)
8695b612 1303{
37e7b184
AC		 1304 struct drm_device *dev = encoder->base.dev;
1305 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
8695b612
AC		 1306 int i;
1307 uint8_t voltage;
1308 bool clock_recovery = false;
1309 int tries;
1310 u32 reg;
1311 uint32_t DP = intel_dp->DP;
1312
1313 DP |= DP_PORT_EN;
37e7b184 1314 DP &= ~DP_LINK_TRAIN_MASK;
8695b612 1315
37e7b184
AC		 1316 reg = DP;
1317 reg |= DP_LINK_TRAIN_PAT_1;
8695b612
AC		 1318 /* Enable output, wait for it to become active */
1319 REG_WRITE(intel_dp->output_reg, reg);
1320 REG_READ(intel_dp->output_reg);
d1fa08f3 1321 gma_wait_for_vblank(dev);
8695b612
AC		 1322
1323 DRM_DEBUG_KMS("Link config\n");
1324 /* Write the link configuration data */
37e7b184 1325 cdv_intel_dp_aux_native_write(encoder, DP_LINK_BW_SET,
8695b612
AC		 1326 intel_dp->link_configuration,
1327 2);
1328
1329 memset(intel_dp->train_set, 0, 4);
1330 voltage = 0;
1331 tries = 0;
1332 clock_recovery = false;
1333
1334 DRM_DEBUG_KMS("Start train\n");
1335 reg = DP | DP_LINK_TRAIN_PAT_1;
1336
1337
1338 for (;;) {
1339 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
d112a816
ZY		 1340 DRM_DEBUG_KMS("DP Link Train Set %x, Link_config %x, %x\n",
1341 intel_dp->train_set[0],
1342 intel_dp->link_configuration[0],
1343 intel_dp->link_configuration[1]);
8695b612 1344
37e7b184 1345 if (!cdv_intel_dp_set_link_train(encoder, reg, DP_TRAINING_PATTERN_1)) {
8695b612
AC		 1346 DRM_DEBUG_KMS("Failure in aux-transfer setting pattern 1\n");
1347 }
37e7b184 1348 cdv_intel_dp_set_vswing_premph(encoder, intel_dp->train_set[0]);
8695b612
AC		 1349 /* Set training pattern 1 */
1350
37e7b184 1351 cdv_intel_dplink_set_level(encoder, DP_TRAINING_PATTERN_1);
8695b612
AC		 1352
1353 udelay(200);
37e7b184 1354 if (!cdv_intel_dp_get_link_status(encoder))
8695b612
AC		 1355 break;
1356
d112a816
ZY		 1357 DRM_DEBUG_KMS("DP Link status %x, %x, %x, %x, %x, %x\n",
1358 intel_dp->link_status[0], intel_dp->link_status[1], intel_dp->link_status[2],
1359 intel_dp->link_status[3], intel_dp->link_status[4], intel_dp->link_status[5]);
1360
37e7b184 1361 if (cdv_intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
8695b612
AC		 1362 DRM_DEBUG_KMS("PT1 train is done\n");
1363 clock_recovery = true;
1364 break;
1365 }
1366
1367 /* Check to see if we've tried the max voltage */
1368 for (i = 0; i < intel_dp->lane_count; i++)
1369 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1370 break;
1371 if (i == intel_dp->lane_count)
1372 break;
1373
1374 /* Check to see if we've tried the same voltage 5 times */
1375 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1376 ++tries;
1377 if (tries == 5)
1378 break;
1379 } else
1380 tries = 0;
1381 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1382
1383 /* Compute new intel_dp->train_set as requested by target */
37e7b184 1384 cdv_intel_get_adjust_train(encoder);
8695b612
AC		 1385
1386 }
1387
1388 if (!clock_recovery) {
1389 DRM_DEBUG_KMS("failure in DP patter 1 training, train set %x\n", intel_dp->train_set[0]);
1390 }
1391
1392 intel_dp->DP = DP;
1393}
1394
1395static void
37e7b184 1396cdv_intel_dp_complete_link_train(struct psb_intel_encoder *encoder)
8695b612 1397{
37e7b184
AC		 1398 struct drm_device *dev = encoder->base.dev;
1399 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
8695b612
AC		 1400 bool channel_eq = false;
1401 int tries, cr_tries;
1402 u32 reg;
1403 uint32_t DP = intel_dp->DP;
1404
1405 /* channel equalization */
1406 tries = 0;
1407 cr_tries = 0;
1408 channel_eq = false;
1409
1410 DRM_DEBUG_KMS("\n");
1411 reg = DP | DP_LINK_TRAIN_PAT_2;
1412
1413 for (;;) {
d112a816
ZY		 1414
1415 DRM_DEBUG_KMS("DP Link Train Set %x, Link_config %x, %x\n",
1416 intel_dp->train_set[0],
1417 intel_dp->link_configuration[0],
1418 intel_dp->link_configuration[1]);
1419 /* channel eq pattern */
1420
37e7b184 1421 if (!cdv_intel_dp_set_link_train(encoder, reg,
8695b612
AC		 1422 DP_TRAINING_PATTERN_2)) {
1423 DRM_DEBUG_KMS("Failure in aux-transfer setting pattern 2\n");
1424 }
1425 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1426
1427 if (cr_tries > 5) {
1428 DRM_ERROR("failed to train DP, aborting\n");
37e7b184 1429 cdv_intel_dp_link_down(encoder);
8695b612
AC		 1430 break;
1431 }
1432
37e7b184 1433 cdv_intel_dp_set_vswing_premph(encoder, intel_dp->train_set[0]);
8695b612 1434
37e7b184 1435 cdv_intel_dplink_set_level(encoder, DP_TRAINING_PATTERN_2);
8695b612
AC		 1436
1437 udelay(1000);
37e7b184 1438 if (!cdv_intel_dp_get_link_status(encoder))
8695b612
AC		 1439 break;
1440
d112a816
ZY		 1441 DRM_DEBUG_KMS("DP Link status %x, %x, %x, %x, %x, %x\n",
1442 intel_dp->link_status[0], intel_dp->link_status[1], intel_dp->link_status[2],
1443 intel_dp->link_status[3], intel_dp->link_status[4], intel_dp->link_status[5]);
1444
8695b612 1445 /* Make sure clock is still ok */
37e7b184
AC		 1446 if (!cdv_intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1447 cdv_intel_dp_start_link_train(encoder);
8695b612
AC		 1448 cr_tries++;
1449 continue;
1450 }
1451
37e7b184 1452 if (cdv_intel_channel_eq_ok(encoder)) {
8695b612
AC		 1453 DRM_DEBUG_KMS("PT2 train is done\n");
1454 channel_eq = true;
1455 break;
1456 }
1457
1458 /* Try 5 times, then try clock recovery if that fails */
1459 if (tries > 5) {
37e7b184
AC		 1460 cdv_intel_dp_link_down(encoder);
1461 cdv_intel_dp_start_link_train(encoder);
8695b612
AC		 1462 tries = 0;
1463 cr_tries++;
1464 continue;
1465 }
1466
1467 /* Compute new intel_dp->train_set as requested by target */
37e7b184 1468 cdv_intel_get_adjust_train(encoder);
8695b612
AC		 1469 ++tries;
1470
1471 }
1472
1473 reg = DP | DP_LINK_TRAIN_OFF;
1474
1475 REG_WRITE(intel_dp->output_reg, reg);
1476 REG_READ(intel_dp->output_reg);
37e7b184 1477 cdv_intel_dp_aux_native_write_1(encoder,
8695b612
AC		 1478 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1479}
1480
1481static void
37e7b184 1482cdv_intel_dp_link_down(struct psb_intel_encoder *encoder)
8695b612 1483{
37e7b184
AC		 1484 struct drm_device *dev = encoder->base.dev;
1485 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
8695b612
AC		 1486 uint32_t DP = intel_dp->DP;
1487
1488 if ((REG_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
1489 return;
1490
1491 DRM_DEBUG_KMS("\n");
1492
1493
1494 {
1495 DP &= ~DP_LINK_TRAIN_MASK;
1496 REG_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1497 }
1498 REG_READ(intel_dp->output_reg);
1499
1500 msleep(17);
1501
1502 REG_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1503 REG_READ(intel_dp->output_reg);
1504}
1505
1506static enum drm_connector_status
37e7b184 1507cdv_dp_detect(struct psb_intel_encoder *encoder)
8695b612 1508{
37e7b184 1509 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
8695b612
AC		 1510 enum drm_connector_status status;
1511
1512 status = connector_status_disconnected;
37e7b184 1513 if (cdv_intel_dp_aux_native_read(encoder, 0x000, intel_dp->dpcd,
8695b612
AC		 1514 sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd))
1515 {
1516 if (intel_dp->dpcd[DP_DPCD_REV] != 0)
1517 status = connector_status_connected;
1518 }
1519 if (status == connector_status_connected)
1520 DRM_DEBUG_KMS("DPCD: Rev=%x LN_Rate=%x LN_CNT=%x LN_DOWNSP=%x\n",
1521 intel_dp->dpcd[0], intel_dp->dpcd[1],
1522 intel_dp->dpcd[2], intel_dp->dpcd[3]);
1523 return status;
1524}
1525
1526/**
1527 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1528 *
1529 * \return true if DP port is connected.
1530 * \return false if DP port is disconnected.
1531 */
1532static enum drm_connector_status
37e7b184 1533cdv_intel_dp_detect(struct drm_connector *connector, bool force)
8695b612 1534{
37e7b184
AC		 1535 struct psb_intel_encoder *encoder = psb_intel_attached_encoder(connector);
1536 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
8695b612
AC		 1537 enum drm_connector_status status;
1538 struct edid *edid = NULL;
d112a816 1539 int edp = is_edp(encoder);
8695b612
AC		 1540
1541 intel_dp->has_audio = false;
1542
d112a816
ZY		 1543 if (edp)
1544 cdv_intel_edp_panel_vdd_on(encoder);
37e7b184 1545 status = cdv_dp_detect(encoder);
d112a816
ZY		 1546 if (status != connector_status_connected) {
1547 if (edp)
1548 cdv_intel_edp_panel_vdd_off(encoder);
8695b612 1549 return status;
d112a816 1550 }
8695b612
AC		 1551
1552 if (intel_dp->force_audio) {
1553 intel_dp->has_audio = intel_dp->force_audio > 0;
1554 } else {
1555 edid = drm_get_edid(connector, &intel_dp->adapter);
1556 if (edid) {
1557 intel_dp->has_audio = drm_detect_monitor_audio(edid);
8695b612
AC		 1558 kfree(edid);
1559 }
1560 }
d112a816
ZY		 1561 if (edp)
1562 cdv_intel_edp_panel_vdd_off(encoder);
8695b612
AC		 1563
1564 return connector_status_connected;
1565}
1566
37e7b184 1567static int cdv_intel_dp_get_modes(struct drm_connector *connector)
8695b612 1568{
37e7b184
AC		 1569 struct psb_intel_encoder *intel_encoder = psb_intel_attached_encoder(connector);
1570 struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
8695b612
AC		 1571 struct edid *edid = NULL;
1572 int ret = 0;
d112a816 1573 int edp = is_edp(intel_encoder);
8695b612
AC		 1574
1575
37e7b184 1576 edid = drm_get_edid(connector, &intel_dp->adapter);
8695b612 1577 if (edid) {
37e7b184
AC		 1578 drm_mode_connector_update_edid_property(connector, edid);
1579 ret = drm_add_edid_modes(connector, edid);
8695b612
AC		 1580 kfree(edid);
1581 }
1582
d112a816
ZY		 1583 if (is_edp(intel_encoder)) {
1584 struct drm_device *dev = connector->dev;
1585 struct drm_psb_private *dev_priv = dev->dev_private;
1586
1587 cdv_intel_edp_panel_vdd_off(intel_encoder);
1588 if (ret) {
1589 if (edp && !intel_dp->panel_fixed_mode) {
1590 struct drm_display_mode *newmode;
1591 list_for_each_entry(newmode, &connector->probed_modes,
1592 head) {
1593 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1594 intel_dp->panel_fixed_mode =
1595 drm_mode_duplicate(dev, newmode);
1596 break;
1597 }
1598 }
1599 }
1600
1601 return ret;
1602 }
1603 if (!intel_dp->panel_fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
1604 intel_dp->panel_fixed_mode =
1605 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1606 if (intel_dp->panel_fixed_mode) {
1607 intel_dp->panel_fixed_mode->type |=
1608 DRM_MODE_TYPE_PREFERRED;
1609 }
1610 }
1611 if (intel_dp->panel_fixed_mode != NULL) {
1612 struct drm_display_mode *mode;
1613 mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
1614 drm_mode_probed_add(connector, mode);
1615 return 1;
1616 }
1617 }
1618
8695b612
AC		 1619 return ret;
1620}
1621
1622static bool
37e7b184 1623cdv_intel_dp_detect_audio(struct drm_connector *connector)
8695b612 1624{
37e7b184
AC		 1625 struct psb_intel_encoder *encoder = psb_intel_attached_encoder(connector);
1626 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
8695b612
AC		 1627 struct edid *edid;
1628 bool has_audio = false;
d112a816
ZY		 1629 int edp = is_edp(encoder);
1630
1631 if (edp)
1632 cdv_intel_edp_panel_vdd_on(encoder);
8695b612
AC		 1633
1634 edid = drm_get_edid(connector, &intel_dp->adapter);
1635 if (edid) {
1636 has_audio = drm_detect_monitor_audio(edid);
8695b612
AC		 1637 kfree(edid);
1638 }
d112a816
ZY		 1639 if (edp)
1640 cdv_intel_edp_panel_vdd_off(encoder);
8695b612
AC		 1641
1642 return has_audio;
1643}
1644
1645static int
37e7b184 1646cdv_intel_dp_set_property(struct drm_connector *connector,
8695b612
AC		 1647 struct drm_property *property,
1648 uint64_t val)
1649{
1650 struct drm_psb_private *dev_priv = connector->dev->dev_private;
37e7b184
AC		 1651 struct psb_intel_encoder *encoder = psb_intel_attached_encoder(connector);
1652 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
8695b612
AC		 1653 int ret;
1654
a69ac9ea 1655 ret = drm_object_property_set_value(&connector->base, property, val);
8695b612
AC		 1656 if (ret)
1657 return ret;
1658
1659 if (property == dev_priv->force_audio_property) {
1660 int i = val;
1661 bool has_audio;
1662
1663 if (i == intel_dp->force_audio)
1664 return 0;
1665
1666 intel_dp->force_audio = i;
1667
1668 if (i == 0)
37e7b184 1669 has_audio = cdv_intel_dp_detect_audio(connector);
8695b612
AC		 1670 else
1671 has_audio = i > 0;
1672
1673 if (has_audio == intel_dp->has_audio)
1674 return 0;
1675
1676 intel_dp->has_audio = has_audio;
1677 goto done;
1678 }
1679
1680 if (property == dev_priv->broadcast_rgb_property) {
1681 if (val == !!intel_dp->color_range)
1682 return 0;
1683
1684 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
1685 goto done;
1686 }
1687
1688 return -EINVAL;
1689
1690done:
37e7b184
AC		 1691 if (encoder->base.crtc) {
1692 struct drm_crtc *crtc = encoder->base.crtc;
8695b612
AC		 1693 drm_crtc_helper_set_mode(crtc, &crtc->mode,
1694 crtc->x, crtc->y,
1695 crtc->fb);
1696 }
1697
1698 return 0;
1699}
1700
1701static void
d112a816 1702cdv_intel_dp_destroy(struct drm_connector *connector)
8695b612 1703{
37e7b184
AC		 1704 struct psb_intel_encoder *psb_intel_encoder =
1705 psb_intel_attached_encoder(connector);
1706 struct cdv_intel_dp *intel_dp = psb_intel_encoder->dev_priv;
8695b612 1707
d112a816
ZY		 1708 if (is_edp(psb_intel_encoder)) {
1709 /* cdv_intel_panel_destroy_backlight(connector->dev); */
1710 if (intel_dp->panel_fixed_mode) {
1711 kfree(intel_dp->panel_fixed_mode);
1712 intel_dp->panel_fixed_mode = NULL;
1713 }
1714 }
8695b612
AC		 1715 i2c_del_adapter(&intel_dp->adapter);
1716 drm_sysfs_connector_remove(connector);
1717 drm_connector_cleanup(connector);
1718 kfree(connector);
1719}
1720
37e7b184 1721static void cdv_intel_dp_encoder_destroy(struct drm_encoder *encoder)
8695b612
AC		 1722{
1723 drm_encoder_cleanup(encoder);
1724}
1725
37e7b184
AC		 1726static const struct drm_encoder_helper_funcs cdv_intel_dp_helper_funcs = {
1727 .dpms = cdv_intel_dp_dpms,
1728 .mode_fixup = cdv_intel_dp_mode_fixup,
1729 .prepare = cdv_intel_dp_prepare,
1730 .mode_set = cdv_intel_dp_mode_set,
1731 .commit = cdv_intel_dp_commit,
8695b612
AC		 1732};
1733
37e7b184 1734static const struct drm_connector_funcs cdv_intel_dp_connector_funcs = {
8695b612 1735 .dpms = drm_helper_connector_dpms,
37e7b184 1736 .detect = cdv_intel_dp_detect,
8695b612 1737 .fill_modes = drm_helper_probe_single_connector_modes,
37e7b184
AC		 1738 .set_property = cdv_intel_dp_set_property,
1739 .destroy = cdv_intel_dp_destroy,
8695b612
AC		 1740};
1741
37e7b184
AC		 1742static const struct drm_connector_helper_funcs cdv_intel_dp_connector_helper_funcs = {
1743 .get_modes = cdv_intel_dp_get_modes,
1744 .mode_valid = cdv_intel_dp_mode_valid,
8695b612
AC		 1745 .best_encoder = psb_intel_best_encoder,
1746};
1747
37e7b184
AC		 1748static const struct drm_encoder_funcs cdv_intel_dp_enc_funcs = {
1749 .destroy = cdv_intel_dp_encoder_destroy,
8695b612
AC		 1750};
1751
1752
37e7b184 1753static void cdv_intel_dp_add_properties(struct drm_connector *connector)
8695b612 1754{
37e7b184
AC		 1755 cdv_intel_attach_force_audio_property(connector);
1756 cdv_intel_attach_broadcast_rgb_property(connector);
8695b612
AC		 1757}
1758
d112a816
ZY		 1759/* check the VBT to see whether the eDP is on DP-D port */
1760static bool cdv_intel_dpc_is_edp(struct drm_device *dev)
1761{
1762 struct drm_psb_private *dev_priv = dev->dev_private;
1763 struct child_device_config *p_child;
1764 int i;
1765
1766 if (!dev_priv->child_dev_num)
1767 return false;
1768
1769 for (i = 0; i < dev_priv->child_dev_num; i++) {
1770 p_child = dev_priv->child_dev + i;
1771
1772 if (p_child->dvo_port == PORT_IDPC &&
1773 p_child->device_type == DEVICE_TYPE_eDP)
1774 return true;
1775 }
1776 return false;
1777}
1778
9a9f5786
ZY		 1779/* Cedarview display clock gating
1780
1781 We need this disable dot get correct behaviour while enabling
1782 DP/eDP. TODO - investigate if we can turn it back to normality
1783 after enabling */
1784static void cdv_disable_intel_clock_gating(struct drm_device *dev)
1785{
1786 u32 reg_value;
1787 reg_value = REG_READ(DSPCLK_GATE_D);
1788
1789 reg_value |= (DPUNIT_PIPEB_GATE_DISABLE |
1790 DPUNIT_PIPEA_GATE_DISABLE |
1791 DPCUNIT_CLOCK_GATE_DISABLE |
1792 DPLSUNIT_CLOCK_GATE_DISABLE |
1793 DPOUNIT_CLOCK_GATE_DISABLE |
1794 DPIOUNIT_CLOCK_GATE_DISABLE);
1795
1796 REG_WRITE(DSPCLK_GATE_D, reg_value);
1797
1798 udelay(500);
1799}
1800
8695b612 1801void
37e7b184 1802cdv_intel_dp_init(struct drm_device *dev, struct psb_intel_mode_device *mode_dev, int output_reg)
8695b612 1803{
37e7b184
AC		 1804 struct psb_intel_encoder *psb_intel_encoder;
1805 struct psb_intel_connector *psb_intel_connector;
8695b612
AC		 1806 struct drm_connector *connector;
1807 struct drm_encoder *encoder;
37e7b184 1808 struct cdv_intel_dp *intel_dp;
8695b612 1809 const char *name = NULL;
d112a816 1810 int type = DRM_MODE_CONNECTOR_DisplayPort;
8695b612 1811
37e7b184
AC		 1812 psb_intel_encoder = kzalloc(sizeof(struct psb_intel_encoder), GFP_KERNEL);
1813 if (!psb_intel_encoder)
8695b612 1814 return;
37e7b184
AC		 1815 psb_intel_connector = kzalloc(sizeof(struct psb_intel_connector), GFP_KERNEL);
1816 if (!psb_intel_connector)
1817 goto err_connector;
1818 intel_dp = kzalloc(sizeof(struct cdv_intel_dp), GFP_KERNEL);
1819 if (!intel_dp)
1820 goto err_priv;
1821
d112a816
ZY		 1822 if ((output_reg == DP_C) && cdv_intel_dpc_is_edp(dev))
1823 type = DRM_MODE_CONNECTOR_eDP;
1824
37e7b184
AC		 1825 connector = &psb_intel_connector->base;
1826 encoder = &psb_intel_encoder->base;
8695b612 1827
d112a816 1828 drm_connector_init(dev, connector, &cdv_intel_dp_connector_funcs, type);
37e7b184 1829 drm_encoder_init(dev, encoder, &cdv_intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS);
8695b612 1830
37e7b184 1831 psb_intel_connector_attach_encoder(psb_intel_connector, psb_intel_encoder);
d112a816
ZY		 1832
1833 if (type == DRM_MODE_CONNECTOR_DisplayPort)
1834 psb_intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
1835 else
1836 psb_intel_encoder->type = INTEL_OUTPUT_EDP;
1837
37e7b184
AC		 1838
1839 psb_intel_encoder->dev_priv=intel_dp;
1840 intel_dp->encoder = psb_intel_encoder;
8695b612
AC		 1841 intel_dp->output_reg = output_reg;
1842
37e7b184
AC		 1843 drm_encoder_helper_add(encoder, &cdv_intel_dp_helper_funcs);
1844 drm_connector_helper_add(connector, &cdv_intel_dp_connector_helper_funcs);
8695b612
AC		 1845
1846 connector->polled = DRM_CONNECTOR_POLL_HPD;
37e7b184
AC		 1847 connector->interlace_allowed = false;
1848 connector->doublescan_allowed = false;
8695b612
AC		 1849
1850 drm_sysfs_connector_add(connector);
1851
1852 /* Set up the DDC bus. */
1853 switch (output_reg) {
1854 case DP_B:
1855 name = "DPDDC-B";
37e7b184 1856 psb_intel_encoder->ddi_select = (DP_MASK | DDI0_SELECT);
8695b612
AC		 1857 break;
1858 case DP_C:
1859 name = "DPDDC-C";
37e7b184 1860 psb_intel_encoder->ddi_select = (DP_MASK | DDI1_SELECT);
8695b612
AC		 1861 break;
1862 }
1863
9a9f5786
ZY		 1864 cdv_disable_intel_clock_gating(dev);
1865
37e7b184
AC		 1866 cdv_intel_dp_i2c_init(psb_intel_connector, psb_intel_encoder, name);
1867 /* FIXME:fail check */
1868 cdv_intel_dp_add_properties(connector);
d112a816
ZY		 1869
1870 if (is_edp(psb_intel_encoder)) {
1871 int ret;
1872 struct edp_power_seq cur;
1873 u32 pp_on, pp_off, pp_div;
1874 u32 pwm_ctrl;
1875
1876 pp_on = REG_READ(PP_CONTROL);
1877 pp_on &= ~PANEL_UNLOCK_MASK;
1878 pp_on |= PANEL_UNLOCK_REGS;
1879
1880 REG_WRITE(PP_CONTROL, pp_on);
1881
1882 pwm_ctrl = REG_READ(BLC_PWM_CTL2);
1883 pwm_ctrl |= PWM_PIPE_B;
1884 REG_WRITE(BLC_PWM_CTL2, pwm_ctrl);
1885
1886 pp_on = REG_READ(PP_ON_DELAYS);
1887 pp_off = REG_READ(PP_OFF_DELAYS);
1888 pp_div = REG_READ(PP_DIVISOR);
1889
1890 /* Pull timing values out of registers */
1891 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
1892 PANEL_POWER_UP_DELAY_SHIFT;
1893
1894 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
1895 PANEL_LIGHT_ON_DELAY_SHIFT;
1896
1897 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
1898 PANEL_LIGHT_OFF_DELAY_SHIFT;
1899
1900 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
1901 PANEL_POWER_DOWN_DELAY_SHIFT;
1902
1903 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
1904 PANEL_POWER_CYCLE_DELAY_SHIFT);
1905
1906 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
1907 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
1908
1909
1910 intel_dp->panel_power_up_delay = cur.t1_t3 / 10;
1911 intel_dp->backlight_on_delay = cur.t8 / 10;
1912 intel_dp->backlight_off_delay = cur.t9 / 10;
1913 intel_dp->panel_power_down_delay = cur.t10 / 10;
1914 intel_dp->panel_power_cycle_delay = (cur.t11_t12 - 1) * 100;
1915
1916 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
1917 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
1918 intel_dp->panel_power_cycle_delay);
1919
1920 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
1921 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
1922
1923
1924 cdv_intel_edp_panel_vdd_on(psb_intel_encoder);
1925 ret = cdv_intel_dp_aux_native_read(psb_intel_encoder, DP_DPCD_REV,
1926 intel_dp->dpcd,
1927 sizeof(intel_dp->dpcd));
1928 cdv_intel_edp_panel_vdd_off(psb_intel_encoder);
1929 if (ret == 0) {
1930 /* if this fails, presume the device is a ghost */
1931 DRM_INFO("failed to retrieve link info, disabling eDP\n");
1932 cdv_intel_dp_encoder_destroy(encoder);
1933 cdv_intel_dp_destroy(connector);
1934 goto err_priv;
1935 } else {
1936 DRM_DEBUG_KMS("DPCD: Rev=%x LN_Rate=%x LN_CNT=%x LN_DOWNSP=%x\n",
1937 intel_dp->dpcd[0], intel_dp->dpcd[1],
1938 intel_dp->dpcd[2], intel_dp->dpcd[3]);
1939
1940 }
1941 /* The CDV reference driver moves pnale backlight setup into the displays that
1942 have a backlight: this is a good idea and one we should probably adopt, however
1943 we need to migrate all the drivers before we can do that */
1944 /*cdv_intel_panel_setup_backlight(dev); */
1945 }
37e7b184 1946 return;
8695b612 1947
37e7b184
AC		 1948err_priv:
1949 kfree(psb_intel_connector);
1950err_connector:
1951 kfree(psb_intel_encoder);
8695b612 1952}
Linux 6.x block layer and io_uring tree(s)