[linux-2.6-block.git] / drivers / gpu / drm / fsl-dcu / fsl_dcu_drm_drv.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright 2015 Freescale Semiconductor, Inc.
 *
 * Freescale DCU drm device driver
 */

#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/console.h>
#include <linux/io.h>
#include <linux/mfd/syscon.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>

#include <drm/drmP.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_fb_cma_helper.h>
#include <drm/drm_fb_helper.h>
#include <drm/drm_gem_cma_helper.h>
#include <drm/drm_modeset_helper.h>
#include <drm/drm_probe_helper.h>

#include "fsl_dcu_drm_crtc.h"
#include "fsl_dcu_drm_drv.h"
#include "fsl_tcon.h"

static int legacyfb_depth = 24;
module_param(legacyfb_depth, int, 0444);

static bool fsl_dcu_drm_is_volatile_reg(struct device *dev, unsigned int reg)
{
	if (reg == DCU_INT_STATUS || reg == DCU_UPDATE_MODE)
		return true;

	return false;
}

static const struct regmap_config fsl_dcu_regmap_config = {
	.reg_bits = 32,
	.reg_stride = 4,
	.val_bits = 32,

	.volatile_reg = fsl_dcu_drm_is_volatile_reg,
};

static void fsl_dcu_irq_uninstall(struct drm_device *dev)
{
	struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;

	regmap_write(fsl_dev->regmap, DCU_INT_STATUS, ~0);
	regmap_write(fsl_dev->regmap, DCU_INT_MASK, ~0);
}

static int fsl_dcu_load(struct drm_device *dev, unsigned long flags)
{
	struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
	int ret;

	ret = fsl_dcu_drm_modeset_init(fsl_dev);
	if (ret < 0) {
		dev_err(dev->dev, "failed to initialize mode setting\n");
		return ret;
	}

	ret = drm_vblank_init(dev, dev->mode_config.num_crtc);
	if (ret < 0) {
		dev_err(dev->dev, "failed to initialize vblank\n");
		goto done;
	}

	ret = drm_irq_install(dev, fsl_dev->irq);
	if (ret < 0) {
		dev_err(dev->dev, "failed to install IRQ handler\n");
		goto done;
	}

	if (legacyfb_depth != 16 && legacyfb_depth != 24 &&
	    legacyfb_depth != 32) {
		dev_warn(dev->dev,
			"Invalid legacyfb_depth.  Defaulting to 24bpp\n");
		legacyfb_depth = 24;
	}

	return 0;
done:
	drm_kms_helper_poll_fini(dev);

	drm_mode_config_cleanup(dev);
	drm_irq_uninstall(dev);
	dev->dev_private = NULL;

	return ret;
}

static void fsl_dcu_unload(struct drm_device *dev)
{
	drm_atomic_helper_shutdown(dev);
	drm_kms_helper_poll_fini(dev);

	drm_mode_config_cleanup(dev);
	drm_irq_uninstall(dev);

	dev->dev_private = NULL;
}

static irqreturn_t fsl_dcu_drm_irq(int irq, void *arg)
{
	struct drm_device *dev = arg;
	struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
	unsigned int int_status;
	int ret;

	ret = regmap_read(fsl_dev->regmap, DCU_INT_STATUS, &int_status);
	if (ret) {
		dev_err(dev->dev, "read DCU_INT_STATUS failed\n");
		return IRQ_NONE;
	}

	if (int_status & DCU_INT_STATUS_VBLANK)
		drm_handle_vblank(dev, 0);

	regmap_write(fsl_dev->regmap, DCU_INT_STATUS, int_status);

	return IRQ_HANDLED;
}

DEFINE_DRM_GEM_CMA_FOPS(fsl_dcu_drm_fops);

static struct drm_driver fsl_dcu_drm_driver = {
	.driver_features	= DRIVER_GEM | DRIVER_MODESET
				| DRIVER_PRIME | DRIVER_ATOMIC,
	.load			= fsl_dcu_load,
	.unload			= fsl_dcu_unload,
	.irq_handler		= fsl_dcu_drm_irq,
	.irq_preinstall		= fsl_dcu_irq_uninstall,
	.irq_uninstall		= fsl_dcu_irq_uninstall,
	.gem_free_object_unlocked = drm_gem_cma_free_object,
	.gem_vm_ops		= &drm_gem_cma_vm_ops,
	.prime_handle_to_fd	= drm_gem_prime_handle_to_fd,
	.prime_fd_to_handle	= drm_gem_prime_fd_to_handle,
	.gem_prime_import	= drm_gem_prime_import,
	.gem_prime_export	= drm_gem_prime_export,
	.gem_prime_get_sg_table	= drm_gem_cma_prime_get_sg_table,
	.gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
	.gem_prime_vmap		= drm_gem_cma_prime_vmap,
	.gem_prime_vunmap	= drm_gem_cma_prime_vunmap,
	.gem_prime_mmap		= drm_gem_cma_prime_mmap,
	.dumb_create		= drm_gem_cma_dumb_create,
	.fops			= &fsl_dcu_drm_fops,
	.name			= "fsl-dcu-drm",
	.desc			= "Freescale DCU DRM",
	.date			= "20160425",
	.major			= 1,
	.minor			= 1,
};

#ifdef CONFIG_PM_SLEEP
static int fsl_dcu_drm_pm_suspend(struct device *dev)
{
	struct fsl_dcu_drm_device *fsl_dev = dev_get_drvdata(dev);
	int ret;

	if (!fsl_dev)
		return 0;

	disable_irq(fsl_dev->irq);

	ret = drm_mode_config_helper_suspend(fsl_dev->drm);
	if (ret) {
		enable_irq(fsl_dev->irq);
		return ret;
	}

	clk_disable_unprepare(fsl_dev->clk);

	return 0;
}

static int fsl_dcu_drm_pm_resume(struct device *dev)
{
	struct fsl_dcu_drm_device *fsl_dev = dev_get_drvdata(dev);
	int ret;

	if (!fsl_dev)
		return 0;

	ret = clk_prepare_enable(fsl_dev->clk);
	if (ret < 0) {
		dev_err(dev, "failed to enable dcu clk\n");
		return ret;
	}

	if (fsl_dev->tcon)
		fsl_tcon_bypass_enable(fsl_dev->tcon);
	fsl_dcu_drm_init_planes(fsl_dev->drm);
	enable_irq(fsl_dev->irq);

	drm_mode_config_helper_resume(fsl_dev->drm);

	return 0;
}
#endif

static const struct dev_pm_ops fsl_dcu_drm_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(fsl_dcu_drm_pm_suspend, fsl_dcu_drm_pm_resume)
};

static const struct fsl_dcu_soc_data fsl_dcu_ls1021a_data = {
	.name = "ls1021a",
	.total_layer = 16,
	.max_layer = 4,
	.layer_regs = LS1021A_LAYER_REG_NUM,
};

static const struct fsl_dcu_soc_data fsl_dcu_vf610_data = {
	.name = "vf610",
	.total_layer = 64,
	.max_layer = 6,
	.layer_regs = VF610_LAYER_REG_NUM,
};

static const struct of_device_id fsl_dcu_of_match[] = {
	{
		.compatible = "fsl,ls1021a-dcu",
		.data = &fsl_dcu_ls1021a_data,
	}, {
		.compatible = "fsl,vf610-dcu",
		.data = &fsl_dcu_vf610_data,
	}, {
	},
};
MODULE_DEVICE_TABLE(of, fsl_dcu_of_match);

static int fsl_dcu_drm_probe(struct platform_device *pdev)
{
	struct fsl_dcu_drm_device *fsl_dev;
	struct drm_device *drm;
	struct device *dev = &pdev->dev;
	struct resource *res;
	void __iomem *base;
	struct drm_driver *driver = &fsl_dcu_drm_driver;
	struct clk *pix_clk_in;
	char pix_clk_name[32];
	const char *pix_clk_in_name;
	const struct of_device_id *id;
	int ret;
	u8 div_ratio_shift = 0;

	fsl_dev = devm_kzalloc(dev, sizeof(*fsl_dev), GFP_KERNEL);
	if (!fsl_dev)
		return -ENOMEM;

	id = of_match_node(fsl_dcu_of_match, pdev->dev.of_node);
	if (!id)
		return -ENODEV;
	fsl_dev->soc = id->data;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	base = devm_ioremap_resource(dev, res);
	if (IS_ERR(base)) {
		ret = PTR_ERR(base);
		return ret;
	}

	fsl_dev->irq = platform_get_irq(pdev, 0);
	if (fsl_dev->irq < 0) {
		dev_err(dev, "failed to get irq\n");
		return fsl_dev->irq;
	}

	fsl_dev->regmap = devm_regmap_init_mmio(dev, base,
			&fsl_dcu_regmap_config);
	if (IS_ERR(fsl_dev->regmap)) {
		dev_err(dev, "regmap init failed\n");
		return PTR_ERR(fsl_dev->regmap);
	}

	fsl_dev->clk = devm_clk_get(dev, "dcu");
	if (IS_ERR(fsl_dev->clk)) {
		dev_err(dev, "failed to get dcu clock\n");
		return PTR_ERR(fsl_dev->clk);
	}
	ret = clk_prepare_enable(fsl_dev->clk);
	if (ret < 0) {
		dev_err(dev, "failed to enable dcu clk\n");
		return ret;
	}

	pix_clk_in = devm_clk_get(dev, "pix");
	if (IS_ERR(pix_clk_in)) {
		/* legancy binding, use dcu clock as pixel clock input */
		pix_clk_in = fsl_dev->clk;
	}

	if (of_property_read_bool(dev->of_node, "big-endian"))
		div_ratio_shift = 24;

	pix_clk_in_name = __clk_get_name(pix_clk_in);
	snprintf(pix_clk_name, sizeof(pix_clk_name), "%s_pix", pix_clk_in_name);
	fsl_dev->pix_clk = clk_register_divider(dev, pix_clk_name,
			pix_clk_in_name, 0, base + DCU_DIV_RATIO,
			div_ratio_shift, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL);
	if (IS_ERR(fsl_dev->pix_clk)) {
		dev_err(dev, "failed to register pix clk\n");
		ret = PTR_ERR(fsl_dev->pix_clk);
		goto disable_clk;
	}

	fsl_dev->tcon = fsl_tcon_init(dev);

	drm = drm_dev_alloc(driver, dev);
	if (IS_ERR(drm)) {
		ret = PTR_ERR(drm);
		goto unregister_pix_clk;
	}

	fsl_dev->dev = dev;
	fsl_dev->drm = drm;
	fsl_dev->np = dev->of_node;
	drm->dev_private = fsl_dev;
	dev_set_drvdata(dev, fsl_dev);

	ret = drm_dev_register(drm, 0);
	if (ret < 0)
		goto put;

	drm_fbdev_generic_setup(drm, legacyfb_depth);

	return 0;

put:
	drm_dev_put(drm);
unregister_pix_clk:
	clk_unregister(fsl_dev->pix_clk);
disable_clk:
	clk_disable_unprepare(fsl_dev->clk);
	return ret;
}

static int fsl_dcu_drm_remove(struct platform_device *pdev)
{
	struct fsl_dcu_drm_device *fsl_dev = platform_get_drvdata(pdev);

	drm_dev_unregister(fsl_dev->drm);
	drm_dev_put(fsl_dev->drm);
	clk_disable_unprepare(fsl_dev->clk);
	clk_unregister(fsl_dev->pix_clk);

	return 0;
}

static struct platform_driver fsl_dcu_drm_platform_driver = {
	.probe		= fsl_dcu_drm_probe,
	.remove		= fsl_dcu_drm_remove,
	.driver		= {
		.name	= "fsl-dcu",
		.pm	= &fsl_dcu_drm_pm_ops,
		.of_match_table = fsl_dcu_of_match,
	},
};

module_platform_driver(fsl_dcu_drm_platform_driver);

MODULE_DESCRIPTION("Freescale DCU DRM Driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
109eee2f JW	2	/*
	3	* Copyright 2015 Freescale Semiconductor, Inc.
	4	*
	5	* Freescale DCU drm device driver
109eee2f JW	6	*/
	7
	8	#include <linux/clk.h>
	9	#include <linux/clk-provider.h>
a8db4324	10	#include <linux/console.h>
109eee2f JW	11	#include <linux/io.h>
	12	#include <linux/mfd/syscon.h>
	13	#include <linux/mm.h>
	14	#include <linux/module.h>
	15	#include <linux/of_platform.h>
	16	#include <linux/platform_device.h>
	17	#include <linux/pm.h>
	18	#include <linux/pm_runtime.h>
	19	#include <linux/regmap.h>
	20
	21	#include <drm/drmP.h>
a8db4324	22	#include <drm/drm_atomic_helper.h>
afb49e4d	23	#include <drm/drm_fb_cma_helper.h>
f4d26fa9	24	#include <drm/drm_fb_helper.h>
109eee2f	25	#include <drm/drm_gem_cma_helper.h>
3b712391	26	#include <drm/drm_modeset_helper.h>
fcd70cd3	27	#include <drm/drm_probe_helper.h>
109eee2f JW	28
	29	#include "fsl_dcu_drm_crtc.h"
	30	#include "fsl_dcu_drm_drv.h"
fb127b79	31	#include "fsl_tcon.h"
109eee2f	32
73fe26a4 SA	33	static int legacyfb_depth = 24;
	34	module_param(legacyfb_depth, int, 0444);
	35
efb8b491 SA	36	static bool fsl_dcu_drm_is_volatile_reg(struct device *dev, unsigned int reg)
	37	{
	38	if (reg == DCU_INT_STATUS \|\| reg == DCU_UPDATE_MODE)
	39	return true;
	40
	41	return false;
	42	}
	43
109eee2f JW	44	static const struct regmap_config fsl_dcu_regmap_config = {
	45	.reg_bits = 32,
	46	.reg_stride = 4,
	47	.val_bits = 32,
efb8b491 SA	48
efb8b491 SA	49	.volatile_reg = fsl_dcu_drm_is_volatile_reg,
109eee2f JW	50	};
109eee2f JW	51
685ec6eb	52	static void fsl_dcu_irq_uninstall(struct drm_device *dev)
109eee2f JW	53	{
109eee2f JW	54	struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
109eee2f	55
685ec6eb	56	regmap_write(fsl_dev->regmap, DCU_INT_STATUS, ~0);
638c93f6	57	regmap_write(fsl_dev->regmap, DCU_INT_MASK, ~0);
109eee2f JW	58	}
109eee2f JW	59
b617966c	60	static int fsl_dcu_load(struct drm_device *dev, unsigned long flags)
109eee2f	61	{
b617966c	62	struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
109eee2f JW	63	int ret;
	64
	65	ret = fsl_dcu_drm_modeset_init(fsl_dev);
	66	if (ret < 0) {
b617966c	67	dev_err(dev->dev, "failed to initialize mode setting\n");
109eee2f JW	68	return ret;
	69	}
	70
b617966c	71	ret = drm_vblank_init(dev, dev->mode_config.num_crtc);
109eee2f	72	if (ret < 0) {
b617966c	73	dev_err(dev->dev, "failed to initialize vblank\n");
109eee2f JW	74	goto done;
109eee2f JW	75	}
109eee2f	76
685ec6eb SA	77	ret = drm_irq_install(dev, fsl_dev->irq);
	78	if (ret < 0) {
	79	dev_err(dev->dev, "failed to install IRQ handler\n");
109eee2f	80	goto done;
685ec6eb	81	}
109eee2f	82
73fe26a4 SA	83	if (legacyfb_depth != 16 && legacyfb_depth != 24 &&
	84	legacyfb_depth != 32) {
	85	dev_warn(dev->dev,
	86	"Invalid legacyfb_depth. Defaulting to 24bpp\n");
	87	legacyfb_depth = 24;
	88	}
109eee2f JW	89
	90	return 0;
	91	done:
7d17a626 SA	92	drm_kms_helper_poll_fini(dev);
7d17a626 SA	93
b617966c	94	drm_mode_config_cleanup(dev);
b617966c SA	95	drm_irq_uninstall(dev);
b617966c SA	96	dev->dev_private = NULL;
109eee2f JW	97
	98	return ret;
	99	}
	100
11b3c20b	101	static void fsl_dcu_unload(struct drm_device *dev)
109eee2f	102	{
09cedcb6	103	drm_atomic_helper_shutdown(dev);
7d17a626 SA	104	drm_kms_helper_poll_fini(dev);
7d17a626 SA	105
109eee2f	106	drm_mode_config_cleanup(dev);
109eee2f JW	107	drm_irq_uninstall(dev);
	108
	109	dev->dev_private = NULL;
109eee2f JW	110	}
109eee2f JW	111
109eee2f JW	112	static irqreturn_t fsl_dcu_drm_irq(int irq, void *arg)
	113	{
	114	struct drm_device *dev = arg;
	115	struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
	116	unsigned int int_status;
	117	int ret;
	118
	119	ret = regmap_read(fsl_dev->regmap, DCU_INT_STATUS, &int_status);
e291d298 SA	120	if (ret) {
	121	dev_err(dev->dev, "read DCU_INT_STATUS failed\n");
	122	return IRQ_NONE;
	123	}
	124
109eee2f JW	125	if (int_status & DCU_INT_STATUS_VBLANK)
	126	drm_handle_vblank(dev, 0);
	127
e291d298	128	regmap_write(fsl_dev->regmap, DCU_INT_STATUS, int_status);
109eee2f JW	129
	130	return IRQ_HANDLED;
	131	}
	132
d55f7e5d	133	DEFINE_DRM_GEM_CMA_FOPS(fsl_dcu_drm_fops);
109eee2f JW	134
109eee2f JW	135	static struct drm_driver fsl_dcu_drm_driver = {
5b38e747	136	.driver_features = DRIVER_GEM \| DRIVER_MODESET
109eee2f JW	137	\| DRIVER_PRIME \| DRIVER_ATOMIC,
	138	.load = fsl_dcu_load,
	139	.unload = fsl_dcu_unload,
109eee2f	140	.irq_handler = fsl_dcu_drm_irq,
685ec6eb SA	141	.irq_preinstall = fsl_dcu_irq_uninstall,
685ec6eb SA	142	.irq_uninstall = fsl_dcu_irq_uninstall,
7c089285	143	.gem_free_object_unlocked = drm_gem_cma_free_object,
109eee2f JW	144	.gem_vm_ops = &drm_gem_cma_vm_ops,
	145	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
	146	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
	147	.gem_prime_import = drm_gem_prime_import,
	148	.gem_prime_export = drm_gem_prime_export,
	149	.gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
	150	.gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
	151	.gem_prime_vmap = drm_gem_cma_prime_vmap,
	152	.gem_prime_vunmap = drm_gem_cma_prime_vunmap,
	153	.gem_prime_mmap = drm_gem_cma_prime_mmap,
	154	.dumb_create = drm_gem_cma_dumb_create,
109eee2f JW	155	.fops = &fsl_dcu_drm_fops,
	156	.name = "fsl-dcu-drm",
	157	.desc = "Freescale DCU DRM",
0449eefe	158	.date = "20160425",
109eee2f	159	.major = 1,
0449eefe	160	.minor = 1,
109eee2f JW	161	};
	162
	163	#ifdef CONFIG_PM_SLEEP
	164	static int fsl_dcu_drm_pm_suspend(struct device *dev)
	165	{
	166	struct fsl_dcu_drm_device *fsl_dev = dev_get_drvdata(dev);
3b712391	167	int ret;
109eee2f JW	168
	169	if (!fsl_dev)
	170	return 0;
	171
a8db4324	172	disable_irq(fsl_dev->irq);
a8db4324	173
3b712391 NT	174	ret = drm_mode_config_helper_suspend(fsl_dev->drm);
3b712391 NT	175	if (ret) {
a8db4324	176	enable_irq(fsl_dev->irq);
3b712391	177	return ret;
a8db4324 SA	178	}
a8db4324 SA	179
ff09b41f	180	clk_disable_unprepare(fsl_dev->clk);
109eee2f JW	181
	182	return 0;
	183	}
	184
	185	static int fsl_dcu_drm_pm_resume(struct device *dev)
	186	{
	187	struct fsl_dcu_drm_device *fsl_dev = dev_get_drvdata(dev);
	188	int ret;
	189
	190	if (!fsl_dev)
	191	return 0;
	192
ff09b41f	193	ret = clk_prepare_enable(fsl_dev->clk);
109eee2f JW	194	if (ret < 0) {
109eee2f JW	195	dev_err(dev, "failed to enable dcu clk\n");
109eee2f JW	196	return ret;
109eee2f JW	197	}
109eee2f	198
8dedefbc SA	199	if (fsl_dev->tcon)
8dedefbc SA	200	fsl_tcon_bypass_enable(fsl_dev->tcon);
a8db4324	201	fsl_dcu_drm_init_planes(fsl_dev->drm);
9fd99f4f	202	enable_irq(fsl_dev->irq);
a8db4324	203
3b712391	204	drm_mode_config_helper_resume(fsl_dev->drm);
109eee2f JW	205
	206	return 0;
	207	}
	208	#endif
	209
	210	static const struct dev_pm_ops fsl_dcu_drm_pm_ops = {
	211	SET_SYSTEM_SLEEP_PM_OPS(fsl_dcu_drm_pm_suspend, fsl_dcu_drm_pm_resume)
	212	};
	213
	214	static const struct fsl_dcu_soc_data fsl_dcu_ls1021a_data = {
	215	.name = "ls1021a",
	216	.total_layer = 16,
	217	.max_layer = 4,
6aaf5a49	218	.layer_regs = LS1021A_LAYER_REG_NUM,
109eee2f JW	219	};
	220
	221	static const struct fsl_dcu_soc_data fsl_dcu_vf610_data = {
	222	.name = "vf610",
	223	.total_layer = 64,
	224	.max_layer = 6,
6aaf5a49	225	.layer_regs = VF610_LAYER_REG_NUM,
109eee2f JW	226	};
	227
	228	static const struct of_device_id fsl_dcu_of_match[] = {
	229	{
	230	.compatible = "fsl,ls1021a-dcu",
	231	.data = &fsl_dcu_ls1021a_data,
	232	}, {
	233	.compatible = "fsl,vf610-dcu",
	234	.data = &fsl_dcu_vf610_data,
	235	}, {
	236	},
	237	};
	238	MODULE_DEVICE_TABLE(of, fsl_dcu_of_match);
	239
	240	static int fsl_dcu_drm_probe(struct platform_device *pdev)
	241	{
	242	struct fsl_dcu_drm_device *fsl_dev;
	243	struct drm_device *drm;
	244	struct device *dev = &pdev->dev;
	245	struct resource *res;
	246	void __iomem *base;
	247	struct drm_driver *driver = &fsl_dcu_drm_driver;
2d701449 SA	248	struct clk *pix_clk_in;
	249	char pix_clk_name[32];
	250	const char *pix_clk_in_name;
109eee2f JW	251	const struct of_device_id *id;
109eee2f JW	252	int ret;
6cc4758a	253	u8 div_ratio_shift = 0;
109eee2f JW	254
	255	fsl_dev = devm_kzalloc(dev, sizeof(*fsl_dev), GFP_KERNEL);
	256	if (!fsl_dev)
	257	return -ENOMEM;
	258
73fa3033 SA	259	id = of_match_node(fsl_dcu_of_match, pdev->dev.of_node);
	260	if (!id)
	261	return -ENODEV;
	262	fsl_dev->soc = id->data;
	263
109eee2f	264	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
109eee2f JW	265	base = devm_ioremap_resource(dev, res);
	266	if (IS_ERR(base)) {
	267	ret = PTR_ERR(base);
	268	return ret;
	269	}
	270
	271	fsl_dev->irq = platform_get_irq(pdev, 0);
	272	if (fsl_dev->irq < 0) {
	273	dev_err(dev, "failed to get irq\n");
238e4f44	274	return fsl_dev->irq;
109eee2f JW	275	}
109eee2f JW	276
73fa3033 SA	277	fsl_dev->regmap = devm_regmap_init_mmio(dev, base,
	278	&fsl_dcu_regmap_config);
	279	if (IS_ERR(fsl_dev->regmap)) {
	280	dev_err(dev, "regmap init failed\n");
	281	return PTR_ERR(fsl_dev->regmap);
	282	}
	283
109eee2f JW	284	fsl_dev->clk = devm_clk_get(dev, "dcu");
109eee2f JW	285	if (IS_ERR(fsl_dev->clk)) {
109eee2f	286	dev_err(dev, "failed to get dcu clock\n");
73fa3033	287	return PTR_ERR(fsl_dev->clk);
109eee2f	288	}
73fa3033	289	ret = clk_prepare_enable(fsl_dev->clk);
109eee2f JW	290	if (ret < 0) {
109eee2f JW	291	dev_err(dev, "failed to enable dcu clk\n");
109eee2f JW	292	return ret;
	293	}
	294
2d701449 SA	295	pix_clk_in = devm_clk_get(dev, "pix");
	296	if (IS_ERR(pix_clk_in)) {
	297	/* legancy binding, use dcu clock as pixel clock input */
	298	pix_clk_in = fsl_dev->clk;
	299	}
	300
6cc4758a SA	301	if (of_property_read_bool(dev->of_node, "big-endian"))
	302	div_ratio_shift = 24;
	303
2d701449 SA	304	pix_clk_in_name = __clk_get_name(pix_clk_in);
	305	snprintf(pix_clk_name, sizeof(pix_clk_name), "%s_pix", pix_clk_in_name);
	306	fsl_dev->pix_clk = clk_register_divider(dev, pix_clk_name,
	307	pix_clk_in_name, 0, base + DCU_DIV_RATIO,
6cc4758a	308	div_ratio_shift, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL);
f93500f4	309	if (IS_ERR(fsl_dev->pix_clk)) {
2d701449 SA	310	dev_err(dev, "failed to register pix clk\n");
	311	ret = PTR_ERR(fsl_dev->pix_clk);
	312	goto disable_clk;
f93500f4	313	}
2d701449	314
fb127b79 SA	315	fsl_dev->tcon = fsl_tcon_init(dev);
fb127b79 SA	316
109eee2f	317	drm = drm_dev_alloc(driver, dev);
0f288605 TG	318	if (IS_ERR(drm)) {
0f288605 TG	319	ret = PTR_ERR(drm);
0a70c998	320	goto unregister_pix_clk;
73fa3033	321	}
109eee2f JW	322
	323	fsl_dev->dev = dev;
	324	fsl_dev->drm = drm;
	325	fsl_dev->np = dev->of_node;
	326	drm->dev_private = fsl_dev;
	327	dev_set_drvdata(dev, fsl_dev);
109eee2f JW	328
	329	ret = drm_dev_register(drm, 0);
	330	if (ret < 0)
a74c0aa5	331	goto put;
109eee2f	332
f4d26fa9 NT	333	drm_fbdev_generic_setup(drm, legacyfb_depth);
f4d26fa9 NT	334
109eee2f JW	335	return 0;
109eee2f JW	336
a74c0aa5 TZ	337	put:
a74c0aa5 TZ	338	drm_dev_put(drm);
2d701449 SA	339	unregister_pix_clk:
2d701449 SA	340	clk_unregister(fsl_dev->pix_clk);
73fa3033 SA	341	disable_clk:
73fa3033 SA	342	clk_disable_unprepare(fsl_dev->clk);
109eee2f JW	343	return ret;
	344	}
	345
	346	static int fsl_dcu_drm_remove(struct platform_device *pdev)
	347	{
	348	struct fsl_dcu_drm_device *fsl_dev = platform_get_drvdata(pdev);
	349
c4085743	350	drm_dev_unregister(fsl_dev->drm);
a74c0aa5	351	drm_dev_put(fsl_dev->drm);
73fa3033	352	clk_disable_unprepare(fsl_dev->clk);
2d701449	353	clk_unregister(fsl_dev->pix_clk);
109eee2f JW	354
	355	return 0;
	356	}
	357
	358	static struct platform_driver fsl_dcu_drm_platform_driver = {
	359	.probe = fsl_dcu_drm_probe,
	360	.remove = fsl_dcu_drm_remove,
	361	.driver = {
	362	.name = "fsl-dcu",
	363	.pm = &fsl_dcu_drm_pm_ops,
	364	.of_match_table = fsl_dcu_of_match,
	365	},
	366	};
	367
	368	module_platform_driver(fsl_dcu_drm_platform_driver);
	369
	370	MODULE_DESCRIPTION("Freescale DCU DRM Driver");
	371	MODULE_LICENSE("GPL");