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d2912cb1 | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
d8408326 SWK |
2 | /* |
3 | * | |
4 | * Cloned from drivers/media/video/s5p-tv/regs-mixer.h | |
5 | * | |
6 | * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. | |
7 | * http://www.samsung.com/ | |
8 | * | |
9 | * Mixer register header file for Samsung Mixer driver | |
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10 | */ |
11 | #ifndef SAMSUNG_REGS_MIXER_H | |
12 | #define SAMSUNG_REGS_MIXER_H | |
13 | ||
14 | /* | |
15 | * Register part | |
16 | */ | |
17 | #define MXR_STATUS 0x0000 | |
18 | #define MXR_CFG 0x0004 | |
19 | #define MXR_INT_EN 0x0008 | |
20 | #define MXR_INT_STATUS 0x000C | |
21 | #define MXR_LAYER_CFG 0x0010 | |
22 | #define MXR_VIDEO_CFG 0x0014 | |
23 | #define MXR_GRAPHIC0_CFG 0x0020 | |
24 | #define MXR_GRAPHIC0_BASE 0x0024 | |
25 | #define MXR_GRAPHIC0_SPAN 0x0028 | |
26 | #define MXR_GRAPHIC0_SXY 0x002C | |
27 | #define MXR_GRAPHIC0_WH 0x0030 | |
28 | #define MXR_GRAPHIC0_DXY 0x0034 | |
29 | #define MXR_GRAPHIC0_BLANK 0x0038 | |
30 | #define MXR_GRAPHIC1_CFG 0x0040 | |
31 | #define MXR_GRAPHIC1_BASE 0x0044 | |
32 | #define MXR_GRAPHIC1_SPAN 0x0048 | |
33 | #define MXR_GRAPHIC1_SXY 0x004C | |
34 | #define MXR_GRAPHIC1_WH 0x0050 | |
35 | #define MXR_GRAPHIC1_DXY 0x0054 | |
36 | #define MXR_GRAPHIC1_BLANK 0x0058 | |
37 | #define MXR_BG_CFG 0x0060 | |
38 | #define MXR_BG_COLOR0 0x0064 | |
39 | #define MXR_BG_COLOR1 0x0068 | |
40 | #define MXR_BG_COLOR2 0x006C | |
41 | #define MXR_CM_COEFF_Y 0x0080 | |
42 | #define MXR_CM_COEFF_CB 0x0084 | |
43 | #define MXR_CM_COEFF_CR 0x0088 | |
def5e095 RS |
44 | #define MXR_MO 0x0304 |
45 | #define MXR_RESOLUTION 0x0310 | |
46 | ||
2eced8e9 | 47 | #define MXR_CFG_S 0x2004 |
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48 | #define MXR_GRAPHIC0_BASE_S 0x2024 |
49 | #define MXR_GRAPHIC1_BASE_S 0x2044 | |
50 | ||
51 | /* for parametrized access to layer registers */ | |
52 | #define MXR_GRAPHIC_CFG(i) (0x0020 + (i) * 0x20) | |
53 | #define MXR_GRAPHIC_BASE(i) (0x0024 + (i) * 0x20) | |
54 | #define MXR_GRAPHIC_SPAN(i) (0x0028 + (i) * 0x20) | |
55 | #define MXR_GRAPHIC_SXY(i) (0x002C + (i) * 0x20) | |
56 | #define MXR_GRAPHIC_WH(i) (0x0030 + (i) * 0x20) | |
57 | #define MXR_GRAPHIC_DXY(i) (0x0034 + (i) * 0x20) | |
58 | #define MXR_GRAPHIC_BLANK(i) (0x0038 + (i) * 0x20) | |
59 | #define MXR_GRAPHIC_BASE_S(i) (0x2024 + (i) * 0x20) | |
60 | ||
61 | /* | |
62 | * Bit definition part | |
63 | */ | |
64 | ||
65 | /* generates mask for range of bits */ | |
66 | #define MXR_MASK(high_bit, low_bit) \ | |
67 | (((2 << ((high_bit) - (low_bit))) - 1) << (low_bit)) | |
68 | ||
69 | #define MXR_MASK_VAL(val, high_bit, low_bit) \ | |
70 | (((val) << (low_bit)) & MXR_MASK(high_bit, low_bit)) | |
71 | ||
72 | /* bits for MXR_STATUS */ | |
aaf8b49e | 73 | #define MXR_STATUS_SOFT_RESET (1 << 8) |
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74 | #define MXR_STATUS_16_BURST (1 << 7) |
75 | #define MXR_STATUS_BURST_MASK (1 << 7) | |
76 | #define MXR_STATUS_BIG_ENDIAN (1 << 3) | |
77 | #define MXR_STATUS_ENDIAN_MASK (1 << 3) | |
78 | #define MXR_STATUS_SYNC_ENABLE (1 << 2) | |
381be025 | 79 | #define MXR_STATUS_REG_IDLE (1 << 1) |
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80 | #define MXR_STATUS_REG_RUN (1 << 0) |
81 | ||
82 | /* bits for MXR_CFG */ | |
aaf8b49e RS |
83 | #define MXR_CFG_LAYER_UPDATE (1 << 31) |
84 | #define MXR_CFG_LAYER_UPDATE_COUNT_MASK (3 << 29) | |
13e810f1 CM |
85 | #define MXR_CFG_QUANT_RANGE_FULL (0 << 9) |
86 | #define MXR_CFG_QUANT_RANGE_LIMITED (1 << 9) | |
87 | #define MXR_CFG_RGB601 (0 << 10) | |
88 | #define MXR_CFG_RGB709 (1 << 10) | |
89 | ||
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90 | #define MXR_CFG_RGB_FMT_MASK 0x600 |
91 | #define MXR_CFG_OUT_YUV444 (0 << 8) | |
92 | #define MXR_CFG_OUT_RGB888 (1 << 8) | |
93 | #define MXR_CFG_OUT_MASK (1 << 8) | |
94 | #define MXR_CFG_DST_SDO (0 << 7) | |
95 | #define MXR_CFG_DST_HDMI (1 << 7) | |
96 | #define MXR_CFG_DST_MASK (1 << 7) | |
97 | #define MXR_CFG_SCAN_HD_720 (0 << 6) | |
98 | #define MXR_CFG_SCAN_HD_1080 (1 << 6) | |
99 | #define MXR_CFG_GRP1_ENABLE (1 << 5) | |
100 | #define MXR_CFG_GRP0_ENABLE (1 << 4) | |
101 | #define MXR_CFG_VP_ENABLE (1 << 3) | |
102 | #define MXR_CFG_SCAN_INTERLACE (0 << 2) | |
1e6d459d | 103 | #define MXR_CFG_SCAN_PROGRESSIVE (1 << 2) |
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104 | #define MXR_CFG_SCAN_NTSC (0 << 1) |
105 | #define MXR_CFG_SCAN_PAL (1 << 1) | |
106 | #define MXR_CFG_SCAN_SD (0 << 0) | |
107 | #define MXR_CFG_SCAN_HD (1 << 0) | |
108 | #define MXR_CFG_SCAN_MASK 0x47 | |
109 | ||
6ac99a32 CM |
110 | /* bits for MXR_VIDEO_CFG */ |
111 | #define MXR_VID_CFG_BLEND_EN (1 << 16) | |
112 | ||
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113 | /* bits for MXR_GRAPHICn_CFG */ |
114 | #define MXR_GRP_CFG_COLOR_KEY_DISABLE (1 << 21) | |
115 | #define MXR_GRP_CFG_BLEND_PRE_MUL (1 << 20) | |
116 | #define MXR_GRP_CFG_WIN_BLEND_EN (1 << 17) | |
117 | #define MXR_GRP_CFG_PIXEL_BLEND_EN (1 << 16) | |
6ac99a32 | 118 | #define MXR_GRP_CFG_MISC_MASK ((3 << 16) | (3 << 20) | 0xff) |
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119 | #define MXR_GRP_CFG_FORMAT_VAL(x) MXR_MASK_VAL(x, 11, 8) |
120 | #define MXR_GRP_CFG_FORMAT_MASK MXR_GRP_CFG_FORMAT_VAL(~0) | |
121 | #define MXR_GRP_CFG_ALPHA_VAL(x) MXR_MASK_VAL(x, 7, 0) | |
122 | ||
123 | /* bits for MXR_GRAPHICn_WH */ | |
124 | #define MXR_GRP_WH_H_SCALE(x) MXR_MASK_VAL(x, 28, 28) | |
125 | #define MXR_GRP_WH_V_SCALE(x) MXR_MASK_VAL(x, 12, 12) | |
126 | #define MXR_GRP_WH_WIDTH(x) MXR_MASK_VAL(x, 26, 16) | |
127 | #define MXR_GRP_WH_HEIGHT(x) MXR_MASK_VAL(x, 10, 0) | |
128 | ||
def5e095 RS |
129 | /* bits for MXR_RESOLUTION */ |
130 | #define MXR_MXR_RES_HEIGHT(x) MXR_MASK_VAL(x, 26, 16) | |
131 | #define MXR_MXR_RES_WIDTH(x) MXR_MASK_VAL(x, 10, 0) | |
132 | ||
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133 | /* bits for MXR_GRAPHICn_SXY */ |
134 | #define MXR_GRP_SXY_SX(x) MXR_MASK_VAL(x, 26, 16) | |
135 | #define MXR_GRP_SXY_SY(x) MXR_MASK_VAL(x, 10, 0) | |
136 | ||
137 | /* bits for MXR_GRAPHICn_DXY */ | |
138 | #define MXR_GRP_DXY_DX(x) MXR_MASK_VAL(x, 26, 16) | |
139 | #define MXR_GRP_DXY_DY(x) MXR_MASK_VAL(x, 10, 0) | |
140 | ||
141 | /* bits for MXR_INT_EN */ | |
142 | #define MXR_INT_EN_VSYNC (1 << 11) | |
143 | #define MXR_INT_EN_ALL (0x0f << 8) | |
144 | ||
2a6e4cd5 | 145 | /* bits for MXR_INT_STATUS */ |
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146 | #define MXR_INT_CLEAR_VSYNC (1 << 11) |
147 | #define MXR_INT_STATUS_VSYNC (1 << 0) | |
148 | ||
2a6e4cd5 | 149 | /* bits for MXR_LAYER_CFG */ |
d8408326 | 150 | #define MXR_LAYER_CFG_GRP1_VAL(x) MXR_MASK_VAL(x, 11, 8) |
a2cb911e | 151 | #define MXR_LAYER_CFG_GRP1_MASK MXR_LAYER_CFG_GRP1_VAL(~0) |
d8408326 | 152 | #define MXR_LAYER_CFG_GRP0_VAL(x) MXR_MASK_VAL(x, 7, 4) |
a2cb911e | 153 | #define MXR_LAYER_CFG_GRP0_MASK MXR_LAYER_CFG_GRP0_VAL(~0) |
d8408326 | 154 | #define MXR_LAYER_CFG_VP_VAL(x) MXR_MASK_VAL(x, 3, 0) |
a2cb911e | 155 | #define MXR_LAYER_CFG_VP_MASK MXR_LAYER_CFG_VP_VAL(~0) |
d8408326 | 156 | |
2a6e4cd5 TJ |
157 | /* bits for MXR_CM_COEFF_Y */ |
158 | #define MXR_CM_COEFF_RGB_FULL (1 << 30) | |
159 | ||
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160 | #endif /* SAMSUNG_REGS_MIXER_H */ |
161 |