Commit | Line | Data |
---|---|---|
d7f1642c JS |
1 | /* |
2 | * Copyright (C) 2012 Samsung Electronics Co.Ltd | |
3 | * Authors: Joonyoung Shim <jy0922.shim@samsung.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundationr | |
8 | */ | |
9 | ||
10 | #include <linux/kernel.h> | |
d7f1642c JS |
11 | #include <linux/clk.h> |
12 | #include <linux/err.h> | |
13 | #include <linux/interrupt.h> | |
14 | #include <linux/io.h> | |
15 | #include <linux/platform_device.h> | |
16 | #include <linux/pm_runtime.h> | |
17 | #include <linux/slab.h> | |
18 | #include <linux/workqueue.h> | |
d87342c1 ID |
19 | #include <linux/dma-mapping.h> |
20 | #include <linux/dma-attrs.h> | |
95fc6337 | 21 | #include <linux/of.h> |
d7f1642c | 22 | |
760285e7 DH |
23 | #include <drm/drmP.h> |
24 | #include <drm/exynos_drm.h> | |
d7f1642c | 25 | #include "exynos_drm_drv.h" |
e30655d0 | 26 | #include "exynos_drm_g2d.h" |
d7f1642c | 27 | #include "exynos_drm_gem.h" |
d87342c1 | 28 | #include "exynos_drm_iommu.h" |
d7f1642c JS |
29 | |
30 | #define G2D_HW_MAJOR_VER 4 | |
31 | #define G2D_HW_MINOR_VER 1 | |
32 | ||
33 | /* vaild register range set from user: 0x0104 ~ 0x0880 */ | |
34 | #define G2D_VALID_START 0x0104 | |
35 | #define G2D_VALID_END 0x0880 | |
36 | ||
37 | /* general registers */ | |
38 | #define G2D_SOFT_RESET 0x0000 | |
39 | #define G2D_INTEN 0x0004 | |
40 | #define G2D_INTC_PEND 0x000C | |
41 | #define G2D_DMA_SFR_BASE_ADDR 0x0080 | |
42 | #define G2D_DMA_COMMAND 0x0084 | |
43 | #define G2D_DMA_STATUS 0x008C | |
44 | #define G2D_DMA_HOLD_CMD 0x0090 | |
45 | ||
46 | /* command registers */ | |
47 | #define G2D_BITBLT_START 0x0100 | |
48 | ||
49 | /* registers for base address */ | |
50 | #define G2D_SRC_BASE_ADDR 0x0304 | |
179239a7 | 51 | #define G2D_SRC_STRIDE_REG 0x0308 |
2dec17c7 YC |
52 | #define G2D_SRC_COLOR_MODE 0x030C |
53 | #define G2D_SRC_LEFT_TOP 0x0310 | |
54 | #define G2D_SRC_RIGHT_BOTTOM 0x0314 | |
d7f1642c JS |
55 | #define G2D_SRC_PLANE2_BASE_ADDR 0x0318 |
56 | #define G2D_DST_BASE_ADDR 0x0404 | |
179239a7 | 57 | #define G2D_DST_STRIDE_REG 0x0408 |
2dec17c7 YC |
58 | #define G2D_DST_COLOR_MODE 0x040C |
59 | #define G2D_DST_LEFT_TOP 0x0410 | |
60 | #define G2D_DST_RIGHT_BOTTOM 0x0414 | |
d7f1642c JS |
61 | #define G2D_DST_PLANE2_BASE_ADDR 0x0418 |
62 | #define G2D_PAT_BASE_ADDR 0x0500 | |
63 | #define G2D_MSK_BASE_ADDR 0x0520 | |
64 | ||
65 | /* G2D_SOFT_RESET */ | |
66 | #define G2D_SFRCLEAR (1 << 1) | |
67 | #define G2D_R (1 << 0) | |
68 | ||
69 | /* G2D_INTEN */ | |
70 | #define G2D_INTEN_ACF (1 << 3) | |
71 | #define G2D_INTEN_UCF (1 << 2) | |
72 | #define G2D_INTEN_GCF (1 << 1) | |
73 | #define G2D_INTEN_SCF (1 << 0) | |
74 | ||
75 | /* G2D_INTC_PEND */ | |
76 | #define G2D_INTP_ACMD_FIN (1 << 3) | |
77 | #define G2D_INTP_UCMD_FIN (1 << 2) | |
78 | #define G2D_INTP_GCMD_FIN (1 << 1) | |
79 | #define G2D_INTP_SCMD_FIN (1 << 0) | |
80 | ||
81 | /* G2D_DMA_COMMAND */ | |
82 | #define G2D_DMA_HALT (1 << 2) | |
83 | #define G2D_DMA_CONTINUE (1 << 1) | |
84 | #define G2D_DMA_START (1 << 0) | |
85 | ||
86 | /* G2D_DMA_STATUS */ | |
87 | #define G2D_DMA_LIST_DONE_COUNT (0xFF << 17) | |
88 | #define G2D_DMA_BITBLT_DONE_COUNT (0xFFFF << 1) | |
89 | #define G2D_DMA_DONE (1 << 0) | |
90 | #define G2D_DMA_LIST_DONE_COUNT_OFFSET 17 | |
91 | ||
92 | /* G2D_DMA_HOLD_CMD */ | |
7ad01814 | 93 | #define G2D_USER_HOLD (1 << 2) |
d7f1642c JS |
94 | #define G2D_LIST_HOLD (1 << 1) |
95 | #define G2D_BITBLT_HOLD (1 << 0) | |
96 | ||
97 | /* G2D_BITBLT_START */ | |
98 | #define G2D_START_CASESEL (1 << 2) | |
99 | #define G2D_START_NHOLT (1 << 1) | |
100 | #define G2D_START_BITBLT (1 << 0) | |
101 | ||
2dec17c7 YC |
102 | /* buffer color format */ |
103 | #define G2D_FMT_XRGB8888 0 | |
104 | #define G2D_FMT_ARGB8888 1 | |
105 | #define G2D_FMT_RGB565 2 | |
106 | #define G2D_FMT_XRGB1555 3 | |
107 | #define G2D_FMT_ARGB1555 4 | |
108 | #define G2D_FMT_XRGB4444 5 | |
109 | #define G2D_FMT_ARGB4444 6 | |
110 | #define G2D_FMT_PACKED_RGB888 7 | |
111 | #define G2D_FMT_A8 11 | |
112 | #define G2D_FMT_L8 12 | |
113 | ||
114 | /* buffer valid length */ | |
115 | #define G2D_LEN_MIN 1 | |
116 | #define G2D_LEN_MAX 8000 | |
117 | ||
d7f1642c JS |
118 | #define G2D_CMDLIST_SIZE (PAGE_SIZE / 4) |
119 | #define G2D_CMDLIST_NUM 64 | |
120 | #define G2D_CMDLIST_POOL_SIZE (G2D_CMDLIST_SIZE * G2D_CMDLIST_NUM) | |
121 | #define G2D_CMDLIST_DATA_NUM (G2D_CMDLIST_SIZE / sizeof(u32) - 2) | |
122 | ||
2a3098ff ID |
123 | /* maximum buffer pool size of userptr is 64MB as default */ |
124 | #define MAX_POOL (64 * 1024 * 1024) | |
125 | ||
126 | enum { | |
127 | BUF_TYPE_GEM = 1, | |
128 | BUF_TYPE_USERPTR, | |
129 | }; | |
130 | ||
9963cb6e YC |
131 | enum g2d_reg_type { |
132 | REG_TYPE_NONE = -1, | |
133 | REG_TYPE_SRC, | |
134 | REG_TYPE_SRC_PLANE2, | |
135 | REG_TYPE_DST, | |
136 | REG_TYPE_DST_PLANE2, | |
137 | REG_TYPE_PAT, | |
138 | REG_TYPE_MSK, | |
139 | MAX_REG_TYPE_NR | |
140 | }; | |
141 | ||
d7f1642c JS |
142 | /* cmdlist data structure */ |
143 | struct g2d_cmdlist { | |
2a3098ff ID |
144 | u32 head; |
145 | unsigned long data[G2D_CMDLIST_DATA_NUM]; | |
146 | u32 last; /* last data offset */ | |
d7f1642c JS |
147 | }; |
148 | ||
2dec17c7 YC |
149 | /* |
150 | * A structure of buffer description | |
151 | * | |
152 | * @format: color format | |
179239a7 | 153 | * @stride: buffer stride/pitch in bytes |
2dec17c7 YC |
154 | * @left_x: the x coordinates of left top corner |
155 | * @top_y: the y coordinates of left top corner | |
156 | * @right_x: the x coordinates of right bottom corner | |
157 | * @bottom_y: the y coordinates of right bottom corner | |
158 | * | |
159 | */ | |
160 | struct g2d_buf_desc { | |
161 | unsigned int format; | |
179239a7 | 162 | unsigned int stride; |
2dec17c7 YC |
163 | unsigned int left_x; |
164 | unsigned int top_y; | |
165 | unsigned int right_x; | |
166 | unsigned int bottom_y; | |
167 | }; | |
168 | ||
9963cb6e YC |
169 | /* |
170 | * A structure of buffer information | |
171 | * | |
172 | * @map_nr: manages the number of mapped buffers | |
173 | * @reg_types: stores regitster type in the order of requested command | |
174 | * @handles: stores buffer handle in its reg_type position | |
175 | * @types: stores buffer type in its reg_type position | |
2dec17c7 | 176 | * @descs: stores buffer description in its reg_type position |
9963cb6e YC |
177 | * |
178 | */ | |
179 | struct g2d_buf_info { | |
180 | unsigned int map_nr; | |
181 | enum g2d_reg_type reg_types[MAX_REG_TYPE_NR]; | |
182 | unsigned long handles[MAX_REG_TYPE_NR]; | |
183 | unsigned int types[MAX_REG_TYPE_NR]; | |
2dec17c7 | 184 | struct g2d_buf_desc descs[MAX_REG_TYPE_NR]; |
9963cb6e YC |
185 | }; |
186 | ||
d7f1642c JS |
187 | struct drm_exynos_pending_g2d_event { |
188 | struct drm_pending_event base; | |
189 | struct drm_exynos_g2d_event event; | |
190 | }; | |
191 | ||
2a3098ff ID |
192 | struct g2d_cmdlist_userptr { |
193 | struct list_head list; | |
194 | dma_addr_t dma_addr; | |
195 | unsigned long userptr; | |
196 | unsigned long size; | |
63540f01 | 197 | struct frame_vector *vec; |
2a3098ff | 198 | struct sg_table *sgt; |
2a3098ff ID |
199 | atomic_t refcount; |
200 | bool in_pool; | |
201 | bool out_of_list; | |
202 | }; | |
d7f1642c JS |
203 | struct g2d_cmdlist_node { |
204 | struct list_head list; | |
205 | struct g2d_cmdlist *cmdlist; | |
d7f1642c | 206 | dma_addr_t dma_addr; |
9963cb6e | 207 | struct g2d_buf_info buf_info; |
d7f1642c JS |
208 | |
209 | struct drm_exynos_pending_g2d_event *event; | |
210 | }; | |
211 | ||
212 | struct g2d_runqueue_node { | |
213 | struct list_head list; | |
214 | struct list_head run_cmdlist; | |
215 | struct list_head event_list; | |
d87342c1 | 216 | struct drm_file *filp; |
6b6bae24 | 217 | pid_t pid; |
d7f1642c JS |
218 | struct completion complete; |
219 | int async; | |
220 | }; | |
221 | ||
222 | struct g2d_data { | |
223 | struct device *dev; | |
224 | struct clk *gate_clk; | |
d7f1642c JS |
225 | void __iomem *regs; |
226 | int irq; | |
227 | struct workqueue_struct *g2d_workq; | |
228 | struct work_struct runqueue_work; | |
229 | struct exynos_drm_subdrv subdrv; | |
230 | bool suspended; | |
231 | ||
232 | /* cmdlist */ | |
233 | struct g2d_cmdlist_node *cmdlist_node; | |
234 | struct list_head free_cmdlist; | |
235 | struct mutex cmdlist_mutex; | |
236 | dma_addr_t cmdlist_pool; | |
237 | void *cmdlist_pool_virt; | |
d87342c1 | 238 | struct dma_attrs cmdlist_dma_attrs; |
d7f1642c JS |
239 | |
240 | /* runqueue*/ | |
241 | struct g2d_runqueue_node *runqueue_node; | |
242 | struct list_head runqueue; | |
243 | struct mutex runqueue_mutex; | |
244 | struct kmem_cache *runqueue_slab; | |
2a3098ff ID |
245 | |
246 | unsigned long current_pool; | |
247 | unsigned long max_pool; | |
d7f1642c JS |
248 | }; |
249 | ||
250 | static int g2d_init_cmdlist(struct g2d_data *g2d) | |
251 | { | |
252 | struct device *dev = g2d->dev; | |
253 | struct g2d_cmdlist_node *node = g2d->cmdlist_node; | |
d87342c1 | 254 | struct exynos_drm_subdrv *subdrv = &g2d->subdrv; |
d7f1642c JS |
255 | int nr; |
256 | int ret; | |
9963cb6e | 257 | struct g2d_buf_info *buf_info; |
d7f1642c | 258 | |
d87342c1 ID |
259 | init_dma_attrs(&g2d->cmdlist_dma_attrs); |
260 | dma_set_attr(DMA_ATTR_WRITE_COMBINE, &g2d->cmdlist_dma_attrs); | |
261 | ||
262 | g2d->cmdlist_pool_virt = dma_alloc_attrs(subdrv->drm_dev->dev, | |
263 | G2D_CMDLIST_POOL_SIZE, | |
264 | &g2d->cmdlist_pool, GFP_KERNEL, | |
265 | &g2d->cmdlist_dma_attrs); | |
d7f1642c JS |
266 | if (!g2d->cmdlist_pool_virt) { |
267 | dev_err(dev, "failed to allocate dma memory\n"); | |
268 | return -ENOMEM; | |
269 | } | |
270 | ||
fab9f8d0 | 271 | node = kcalloc(G2D_CMDLIST_NUM, sizeof(*node), GFP_KERNEL); |
d7f1642c JS |
272 | if (!node) { |
273 | dev_err(dev, "failed to allocate memory\n"); | |
274 | ret = -ENOMEM; | |
275 | goto err; | |
276 | } | |
277 | ||
278 | for (nr = 0; nr < G2D_CMDLIST_NUM; nr++) { | |
9963cb6e YC |
279 | unsigned int i; |
280 | ||
d7f1642c JS |
281 | node[nr].cmdlist = |
282 | g2d->cmdlist_pool_virt + nr * G2D_CMDLIST_SIZE; | |
283 | node[nr].dma_addr = | |
284 | g2d->cmdlist_pool + nr * G2D_CMDLIST_SIZE; | |
285 | ||
9963cb6e YC |
286 | buf_info = &node[nr].buf_info; |
287 | for (i = 0; i < MAX_REG_TYPE_NR; i++) | |
288 | buf_info->reg_types[i] = REG_TYPE_NONE; | |
289 | ||
d7f1642c JS |
290 | list_add_tail(&node[nr].list, &g2d->free_cmdlist); |
291 | } | |
292 | ||
293 | return 0; | |
294 | ||
295 | err: | |
d87342c1 ID |
296 | dma_free_attrs(subdrv->drm_dev->dev, G2D_CMDLIST_POOL_SIZE, |
297 | g2d->cmdlist_pool_virt, | |
298 | g2d->cmdlist_pool, &g2d->cmdlist_dma_attrs); | |
d7f1642c JS |
299 | return ret; |
300 | } | |
301 | ||
302 | static void g2d_fini_cmdlist(struct g2d_data *g2d) | |
303 | { | |
d87342c1 | 304 | struct exynos_drm_subdrv *subdrv = &g2d->subdrv; |
d7f1642c JS |
305 | |
306 | kfree(g2d->cmdlist_node); | |
9ad703e9 ID |
307 | |
308 | if (g2d->cmdlist_pool_virt && g2d->cmdlist_pool) { | |
309 | dma_free_attrs(subdrv->drm_dev->dev, G2D_CMDLIST_POOL_SIZE, | |
310 | g2d->cmdlist_pool_virt, | |
311 | g2d->cmdlist_pool, &g2d->cmdlist_dma_attrs); | |
312 | } | |
d7f1642c JS |
313 | } |
314 | ||
315 | static struct g2d_cmdlist_node *g2d_get_cmdlist(struct g2d_data *g2d) | |
316 | { | |
317 | struct device *dev = g2d->dev; | |
318 | struct g2d_cmdlist_node *node; | |
319 | ||
320 | mutex_lock(&g2d->cmdlist_mutex); | |
321 | if (list_empty(&g2d->free_cmdlist)) { | |
322 | dev_err(dev, "there is no free cmdlist\n"); | |
323 | mutex_unlock(&g2d->cmdlist_mutex); | |
324 | return NULL; | |
325 | } | |
326 | ||
327 | node = list_first_entry(&g2d->free_cmdlist, struct g2d_cmdlist_node, | |
328 | list); | |
329 | list_del_init(&node->list); | |
330 | mutex_unlock(&g2d->cmdlist_mutex); | |
331 | ||
332 | return node; | |
333 | } | |
334 | ||
335 | static void g2d_put_cmdlist(struct g2d_data *g2d, struct g2d_cmdlist_node *node) | |
336 | { | |
337 | mutex_lock(&g2d->cmdlist_mutex); | |
338 | list_move_tail(&node->list, &g2d->free_cmdlist); | |
339 | mutex_unlock(&g2d->cmdlist_mutex); | |
340 | } | |
341 | ||
342 | static void g2d_add_cmdlist_to_inuse(struct exynos_drm_g2d_private *g2d_priv, | |
343 | struct g2d_cmdlist_node *node) | |
344 | { | |
345 | struct g2d_cmdlist_node *lnode; | |
346 | ||
347 | if (list_empty(&g2d_priv->inuse_cmdlist)) | |
348 | goto add_to_list; | |
349 | ||
350 | /* this links to base address of new cmdlist */ | |
351 | lnode = list_entry(g2d_priv->inuse_cmdlist.prev, | |
352 | struct g2d_cmdlist_node, list); | |
353 | lnode->cmdlist->data[lnode->cmdlist->last] = node->dma_addr; | |
354 | ||
355 | add_to_list: | |
356 | list_add_tail(&node->list, &g2d_priv->inuse_cmdlist); | |
357 | ||
358 | if (node->event) | |
359 | list_add_tail(&node->event->base.link, &g2d_priv->event_list); | |
360 | } | |
361 | ||
2a3098ff ID |
362 | static void g2d_userptr_put_dma_addr(struct drm_device *drm_dev, |
363 | unsigned long obj, | |
364 | bool force) | |
365 | { | |
366 | struct g2d_cmdlist_userptr *g2d_userptr = | |
367 | (struct g2d_cmdlist_userptr *)obj; | |
63540f01 | 368 | struct page **pages; |
2a3098ff ID |
369 | |
370 | if (!obj) | |
371 | return; | |
372 | ||
373 | if (force) | |
374 | goto out; | |
375 | ||
376 | atomic_dec(&g2d_userptr->refcount); | |
377 | ||
378 | if (atomic_read(&g2d_userptr->refcount) > 0) | |
379 | return; | |
380 | ||
381 | if (g2d_userptr->in_pool) | |
382 | return; | |
383 | ||
384 | out: | |
385 | exynos_gem_unmap_sgt_from_dma(drm_dev, g2d_userptr->sgt, | |
386 | DMA_BIDIRECTIONAL); | |
387 | ||
63540f01 JK |
388 | pages = frame_vector_pages(g2d_userptr->vec); |
389 | if (!IS_ERR(pages)) { | |
390 | int i; | |
2a3098ff | 391 | |
63540f01 JK |
392 | for (i = 0; i < frame_vector_count(g2d_userptr->vec); i++) |
393 | set_page_dirty_lock(pages[i]); | |
394 | } | |
395 | put_vaddr_frames(g2d_userptr->vec); | |
396 | frame_vector_destroy(g2d_userptr->vec); | |
c3bddbda | 397 | |
2a3098ff ID |
398 | if (!g2d_userptr->out_of_list) |
399 | list_del_init(&g2d_userptr->list); | |
400 | ||
401 | sg_free_table(g2d_userptr->sgt); | |
402 | kfree(g2d_userptr->sgt); | |
df3d90e5 | 403 | kfree(g2d_userptr); |
2a3098ff ID |
404 | } |
405 | ||
b7848c7a | 406 | static dma_addr_t *g2d_userptr_get_dma_addr(struct drm_device *drm_dev, |
2a3098ff ID |
407 | unsigned long userptr, |
408 | unsigned long size, | |
409 | struct drm_file *filp, | |
410 | unsigned long *obj) | |
411 | { | |
412 | struct drm_exynos_file_private *file_priv = filp->driver_priv; | |
413 | struct exynos_drm_g2d_private *g2d_priv = file_priv->g2d_priv; | |
414 | struct g2d_cmdlist_userptr *g2d_userptr; | |
415 | struct g2d_data *g2d; | |
2a3098ff | 416 | struct sg_table *sgt; |
2a3098ff ID |
417 | unsigned long start, end; |
418 | unsigned int npages, offset; | |
419 | int ret; | |
420 | ||
421 | if (!size) { | |
422 | DRM_ERROR("invalid userptr size.\n"); | |
423 | return ERR_PTR(-EINVAL); | |
424 | } | |
425 | ||
426 | g2d = dev_get_drvdata(g2d_priv->dev); | |
427 | ||
428 | /* check if userptr already exists in userptr_list. */ | |
429 | list_for_each_entry(g2d_userptr, &g2d_priv->userptr_list, list) { | |
430 | if (g2d_userptr->userptr == userptr) { | |
431 | /* | |
432 | * also check size because there could be same address | |
433 | * and different size. | |
434 | */ | |
435 | if (g2d_userptr->size == size) { | |
436 | atomic_inc(&g2d_userptr->refcount); | |
437 | *obj = (unsigned long)g2d_userptr; | |
438 | ||
439 | return &g2d_userptr->dma_addr; | |
440 | } | |
441 | ||
442 | /* | |
443 | * at this moment, maybe g2d dma is accessing this | |
444 | * g2d_userptr memory region so just remove this | |
445 | * g2d_userptr object from userptr_list not to be | |
446 | * referred again and also except it the userptr | |
447 | * pool to be released after the dma access completion. | |
448 | */ | |
449 | g2d_userptr->out_of_list = true; | |
450 | g2d_userptr->in_pool = false; | |
451 | list_del_init(&g2d_userptr->list); | |
452 | ||
453 | break; | |
454 | } | |
455 | } | |
456 | ||
457 | g2d_userptr = kzalloc(sizeof(*g2d_userptr), GFP_KERNEL); | |
38bb5253 | 458 | if (!g2d_userptr) |
2a3098ff | 459 | return ERR_PTR(-ENOMEM); |
2a3098ff ID |
460 | |
461 | atomic_set(&g2d_userptr->refcount, 1); | |
63540f01 | 462 | g2d_userptr->size = size; |
2a3098ff ID |
463 | |
464 | start = userptr & PAGE_MASK; | |
465 | offset = userptr & ~PAGE_MASK; | |
466 | end = PAGE_ALIGN(userptr + size); | |
467 | npages = (end - start) >> PAGE_SHIFT; | |
63540f01 JK |
468 | g2d_userptr->vec = frame_vector_create(npages); |
469 | if (!g2d_userptr->vec) { | |
4bb615c5 SWK |
470 | ret = -ENOMEM; |
471 | goto err_free; | |
2a3098ff ID |
472 | } |
473 | ||
63540f01 JK |
474 | ret = get_vaddr_frames(start, npages, true, true, g2d_userptr->vec); |
475 | if (ret != npages) { | |
476 | DRM_ERROR("failed to get user pages from userptr.\n"); | |
477 | if (ret < 0) | |
478 | goto err_destroy_framevec; | |
2a3098ff | 479 | ret = -EFAULT; |
63540f01 | 480 | goto err_put_framevec; |
2a3098ff | 481 | } |
63540f01 | 482 | if (frame_vector_to_pages(g2d_userptr->vec) < 0) { |
2a3098ff | 483 | ret = -EFAULT; |
63540f01 | 484 | goto err_put_framevec; |
2a3098ff ID |
485 | } |
486 | ||
e44a5c00 | 487 | sgt = kzalloc(sizeof(*sgt), GFP_KERNEL); |
2a3098ff | 488 | if (!sgt) { |
2a3098ff | 489 | ret = -ENOMEM; |
63540f01 | 490 | goto err_put_framevec; |
2a3098ff ID |
491 | } |
492 | ||
63540f01 JK |
493 | ret = sg_alloc_table_from_pages(sgt, |
494 | frame_vector_pages(g2d_userptr->vec), | |
495 | npages, offset, size, GFP_KERNEL); | |
2a3098ff ID |
496 | if (ret < 0) { |
497 | DRM_ERROR("failed to get sgt from pages.\n"); | |
498 | goto err_free_sgt; | |
499 | } | |
500 | ||
501 | g2d_userptr->sgt = sgt; | |
502 | ||
503 | ret = exynos_gem_map_sgt_with_dma(drm_dev, g2d_userptr->sgt, | |
504 | DMA_BIDIRECTIONAL); | |
505 | if (ret < 0) { | |
506 | DRM_ERROR("failed to map sgt with dma region.\n"); | |
067ed331 | 507 | goto err_sg_free_table; |
2a3098ff ID |
508 | } |
509 | ||
510 | g2d_userptr->dma_addr = sgt->sgl[0].dma_address; | |
511 | g2d_userptr->userptr = userptr; | |
512 | ||
513 | list_add_tail(&g2d_userptr->list, &g2d_priv->userptr_list); | |
514 | ||
515 | if (g2d->current_pool + (npages << PAGE_SHIFT) < g2d->max_pool) { | |
516 | g2d->current_pool += npages << PAGE_SHIFT; | |
517 | g2d_userptr->in_pool = true; | |
518 | } | |
519 | ||
520 | *obj = (unsigned long)g2d_userptr; | |
521 | ||
522 | return &g2d_userptr->dma_addr; | |
523 | ||
067ed331 | 524 | err_sg_free_table: |
2a3098ff | 525 | sg_free_table(sgt); |
067ed331 YC |
526 | |
527 | err_free_sgt: | |
2a3098ff | 528 | kfree(sgt); |
2a3098ff | 529 | |
63540f01 JK |
530 | err_put_framevec: |
531 | put_vaddr_frames(g2d_userptr->vec); | |
2a3098ff | 532 | |
63540f01 JK |
533 | err_destroy_framevec: |
534 | frame_vector_destroy(g2d_userptr->vec); | |
4bb615c5 SWK |
535 | |
536 | err_free: | |
2a3098ff | 537 | kfree(g2d_userptr); |
2a3098ff ID |
538 | |
539 | return ERR_PTR(ret); | |
540 | } | |
541 | ||
542 | static void g2d_userptr_free_all(struct drm_device *drm_dev, | |
543 | struct g2d_data *g2d, | |
544 | struct drm_file *filp) | |
545 | { | |
546 | struct drm_exynos_file_private *file_priv = filp->driver_priv; | |
547 | struct exynos_drm_g2d_private *g2d_priv = file_priv->g2d_priv; | |
548 | struct g2d_cmdlist_userptr *g2d_userptr, *n; | |
549 | ||
550 | list_for_each_entry_safe(g2d_userptr, n, &g2d_priv->userptr_list, list) | |
551 | if (g2d_userptr->in_pool) | |
552 | g2d_userptr_put_dma_addr(drm_dev, | |
553 | (unsigned long)g2d_userptr, | |
554 | true); | |
555 | ||
556 | g2d->current_pool = 0; | |
557 | } | |
558 | ||
9963cb6e YC |
559 | static enum g2d_reg_type g2d_get_reg_type(int reg_offset) |
560 | { | |
561 | enum g2d_reg_type reg_type; | |
562 | ||
563 | switch (reg_offset) { | |
564 | case G2D_SRC_BASE_ADDR: | |
179239a7 | 565 | case G2D_SRC_STRIDE_REG: |
2dec17c7 YC |
566 | case G2D_SRC_COLOR_MODE: |
567 | case G2D_SRC_LEFT_TOP: | |
568 | case G2D_SRC_RIGHT_BOTTOM: | |
9963cb6e YC |
569 | reg_type = REG_TYPE_SRC; |
570 | break; | |
571 | case G2D_SRC_PLANE2_BASE_ADDR: | |
572 | reg_type = REG_TYPE_SRC_PLANE2; | |
573 | break; | |
574 | case G2D_DST_BASE_ADDR: | |
179239a7 | 575 | case G2D_DST_STRIDE_REG: |
2dec17c7 YC |
576 | case G2D_DST_COLOR_MODE: |
577 | case G2D_DST_LEFT_TOP: | |
578 | case G2D_DST_RIGHT_BOTTOM: | |
9963cb6e YC |
579 | reg_type = REG_TYPE_DST; |
580 | break; | |
581 | case G2D_DST_PLANE2_BASE_ADDR: | |
582 | reg_type = REG_TYPE_DST_PLANE2; | |
583 | break; | |
584 | case G2D_PAT_BASE_ADDR: | |
585 | reg_type = REG_TYPE_PAT; | |
586 | break; | |
587 | case G2D_MSK_BASE_ADDR: | |
588 | reg_type = REG_TYPE_MSK; | |
589 | break; | |
590 | default: | |
591 | reg_type = REG_TYPE_NONE; | |
592 | DRM_ERROR("Unknown register offset![%d]\n", reg_offset); | |
593 | break; | |
5cdbc8d9 | 594 | } |
9963cb6e YC |
595 | |
596 | return reg_type; | |
597 | } | |
598 | ||
2dec17c7 YC |
599 | static unsigned long g2d_get_buf_bpp(unsigned int format) |
600 | { | |
601 | unsigned long bpp; | |
602 | ||
603 | switch (format) { | |
604 | case G2D_FMT_XRGB8888: | |
605 | case G2D_FMT_ARGB8888: | |
606 | bpp = 4; | |
607 | break; | |
608 | case G2D_FMT_RGB565: | |
609 | case G2D_FMT_XRGB1555: | |
610 | case G2D_FMT_ARGB1555: | |
611 | case G2D_FMT_XRGB4444: | |
612 | case G2D_FMT_ARGB4444: | |
613 | bpp = 2; | |
614 | break; | |
615 | case G2D_FMT_PACKED_RGB888: | |
616 | bpp = 3; | |
617 | break; | |
618 | default: | |
619 | bpp = 1; | |
620 | break; | |
621 | } | |
622 | ||
623 | return bpp; | |
624 | } | |
625 | ||
626 | static bool g2d_check_buf_desc_is_valid(struct g2d_buf_desc *buf_desc, | |
627 | enum g2d_reg_type reg_type, | |
628 | unsigned long size) | |
629 | { | |
179239a7 TJ |
630 | int width, height; |
631 | unsigned long bpp, last_pos; | |
2dec17c7 YC |
632 | |
633 | /* | |
634 | * check source and destination buffers only. | |
635 | * so the others are always valid. | |
636 | */ | |
637 | if (reg_type != REG_TYPE_SRC && reg_type != REG_TYPE_DST) | |
638 | return true; | |
639 | ||
179239a7 TJ |
640 | /* This check also makes sure that right_x > left_x. */ |
641 | width = (int)buf_desc->right_x - (int)buf_desc->left_x; | |
2dec17c7 | 642 | if (width < G2D_LEN_MIN || width > G2D_LEN_MAX) { |
179239a7 | 643 | DRM_ERROR("width[%d] is out of range!\n", width); |
2dec17c7 YC |
644 | return false; |
645 | } | |
646 | ||
179239a7 TJ |
647 | /* This check also makes sure that bottom_y > top_y. */ |
648 | height = (int)buf_desc->bottom_y - (int)buf_desc->top_y; | |
2dec17c7 | 649 | if (height < G2D_LEN_MIN || height > G2D_LEN_MAX) { |
179239a7 | 650 | DRM_ERROR("height[%d] is out of range!\n", height); |
2dec17c7 YC |
651 | return false; |
652 | } | |
653 | ||
179239a7 TJ |
654 | bpp = g2d_get_buf_bpp(buf_desc->format); |
655 | ||
656 | /* Compute the position of the last byte that the engine accesses. */ | |
657 | last_pos = ((unsigned long)buf_desc->bottom_y - 1) * | |
658 | (unsigned long)buf_desc->stride + | |
659 | (unsigned long)buf_desc->right_x * bpp - 1; | |
660 | ||
661 | /* | |
662 | * Since right_x > left_x and bottom_y > top_y we already know | |
663 | * that the first_pos < last_pos (first_pos being the position | |
664 | * of the first byte the engine accesses), it just remains to | |
665 | * check if last_pos is smaller then the buffer size. | |
666 | */ | |
667 | ||
668 | if (last_pos >= size) { | |
669 | DRM_ERROR("last engine access position [%lu] " | |
670 | "is out of range [%lu]!\n", last_pos, size); | |
2dec17c7 YC |
671 | return false; |
672 | } | |
673 | ||
674 | return true; | |
675 | } | |
676 | ||
d87342c1 ID |
677 | static int g2d_map_cmdlist_gem(struct g2d_data *g2d, |
678 | struct g2d_cmdlist_node *node, | |
679 | struct drm_device *drm_dev, | |
680 | struct drm_file *file) | |
d7f1642c | 681 | { |
d7f1642c | 682 | struct g2d_cmdlist *cmdlist = node->cmdlist; |
9963cb6e | 683 | struct g2d_buf_info *buf_info = &node->buf_info; |
d7f1642c | 684 | int offset; |
9963cb6e | 685 | int ret; |
d7f1642c JS |
686 | int i; |
687 | ||
9963cb6e | 688 | for (i = 0; i < buf_info->map_nr; i++) { |
2dec17c7 | 689 | struct g2d_buf_desc *buf_desc; |
9963cb6e YC |
690 | enum g2d_reg_type reg_type; |
691 | int reg_pos; | |
d87342c1 ID |
692 | unsigned long handle; |
693 | dma_addr_t *addr; | |
d7f1642c | 694 | |
9963cb6e YC |
695 | reg_pos = cmdlist->last - 2 * (i + 1); |
696 | ||
697 | offset = cmdlist->data[reg_pos]; | |
698 | handle = cmdlist->data[reg_pos + 1]; | |
699 | ||
700 | reg_type = g2d_get_reg_type(offset); | |
701 | if (reg_type == REG_TYPE_NONE) { | |
702 | ret = -EFAULT; | |
703 | goto err; | |
704 | } | |
d7f1642c | 705 | |
2dec17c7 YC |
706 | buf_desc = &buf_info->descs[reg_type]; |
707 | ||
9963cb6e | 708 | if (buf_info->types[reg_type] == BUF_TYPE_GEM) { |
2dec17c7 YC |
709 | unsigned long size; |
710 | ||
711 | size = exynos_drm_gem_get_size(drm_dev, handle, file); | |
712 | if (!size) { | |
713 | ret = -EFAULT; | |
714 | goto err; | |
715 | } | |
716 | ||
717 | if (!g2d_check_buf_desc_is_valid(buf_desc, reg_type, | |
718 | size)) { | |
719 | ret = -EFAULT; | |
720 | goto err; | |
721 | } | |
722 | ||
2a3098ff ID |
723 | addr = exynos_drm_gem_get_dma_addr(drm_dev, handle, |
724 | file); | |
725 | if (IS_ERR(addr)) { | |
9963cb6e YC |
726 | ret = -EFAULT; |
727 | goto err; | |
2a3098ff ID |
728 | } |
729 | } else { | |
730 | struct drm_exynos_g2d_userptr g2d_userptr; | |
731 | ||
732 | if (copy_from_user(&g2d_userptr, (void __user *)handle, | |
733 | sizeof(struct drm_exynos_g2d_userptr))) { | |
9963cb6e YC |
734 | ret = -EFAULT; |
735 | goto err; | |
2a3098ff ID |
736 | } |
737 | ||
2dec17c7 YC |
738 | if (!g2d_check_buf_desc_is_valid(buf_desc, reg_type, |
739 | g2d_userptr.size)) { | |
740 | ret = -EFAULT; | |
741 | goto err; | |
742 | } | |
743 | ||
2a3098ff ID |
744 | addr = g2d_userptr_get_dma_addr(drm_dev, |
745 | g2d_userptr.userptr, | |
746 | g2d_userptr.size, | |
747 | file, | |
748 | &handle); | |
749 | if (IS_ERR(addr)) { | |
9963cb6e YC |
750 | ret = -EFAULT; |
751 | goto err; | |
2a3098ff | 752 | } |
d7f1642c JS |
753 | } |
754 | ||
9963cb6e YC |
755 | cmdlist->data[reg_pos + 1] = *addr; |
756 | buf_info->reg_types[i] = reg_type; | |
757 | buf_info->handles[reg_type] = handle; | |
d7f1642c JS |
758 | } |
759 | ||
760 | return 0; | |
9963cb6e YC |
761 | |
762 | err: | |
763 | buf_info->map_nr = i; | |
764 | return ret; | |
d7f1642c JS |
765 | } |
766 | ||
d87342c1 ID |
767 | static void g2d_unmap_cmdlist_gem(struct g2d_data *g2d, |
768 | struct g2d_cmdlist_node *node, | |
769 | struct drm_file *filp) | |
d7f1642c | 770 | { |
d87342c1 | 771 | struct exynos_drm_subdrv *subdrv = &g2d->subdrv; |
9963cb6e | 772 | struct g2d_buf_info *buf_info = &node->buf_info; |
d87342c1 | 773 | int i; |
d7f1642c | 774 | |
9963cb6e | 775 | for (i = 0; i < buf_info->map_nr; i++) { |
2dec17c7 | 776 | struct g2d_buf_desc *buf_desc; |
9963cb6e YC |
777 | enum g2d_reg_type reg_type; |
778 | unsigned long handle; | |
779 | ||
780 | reg_type = buf_info->reg_types[i]; | |
d87342c1 | 781 | |
2dec17c7 | 782 | buf_desc = &buf_info->descs[reg_type]; |
9963cb6e YC |
783 | handle = buf_info->handles[reg_type]; |
784 | ||
785 | if (buf_info->types[reg_type] == BUF_TYPE_GEM) | |
2a3098ff ID |
786 | exynos_drm_gem_put_dma_addr(subdrv->drm_dev, handle, |
787 | filp); | |
788 | else | |
789 | g2d_userptr_put_dma_addr(subdrv->drm_dev, handle, | |
790 | false); | |
d7f1642c | 791 | |
9963cb6e YC |
792 | buf_info->reg_types[i] = REG_TYPE_NONE; |
793 | buf_info->handles[reg_type] = 0; | |
794 | buf_info->types[reg_type] = 0; | |
2dec17c7 | 795 | memset(buf_desc, 0x00, sizeof(*buf_desc)); |
d7f1642c | 796 | } |
d87342c1 | 797 | |
9963cb6e | 798 | buf_info->map_nr = 0; |
d7f1642c JS |
799 | } |
800 | ||
801 | static void g2d_dma_start(struct g2d_data *g2d, | |
802 | struct g2d_runqueue_node *runqueue_node) | |
803 | { | |
804 | struct g2d_cmdlist_node *node = | |
805 | list_first_entry(&runqueue_node->run_cmdlist, | |
806 | struct g2d_cmdlist_node, list); | |
89f8b85e ID |
807 | int ret; |
808 | ||
809 | ret = pm_runtime_get_sync(g2d->dev); | |
b10d6350 | 810 | if (ret < 0) |
89f8b85e | 811 | return; |
d7f1642c | 812 | |
d7f1642c JS |
813 | writel_relaxed(node->dma_addr, g2d->regs + G2D_DMA_SFR_BASE_ADDR); |
814 | writel_relaxed(G2D_DMA_START, g2d->regs + G2D_DMA_COMMAND); | |
815 | } | |
816 | ||
817 | static struct g2d_runqueue_node *g2d_get_runqueue_node(struct g2d_data *g2d) | |
818 | { | |
819 | struct g2d_runqueue_node *runqueue_node; | |
820 | ||
821 | if (list_empty(&g2d->runqueue)) | |
822 | return NULL; | |
823 | ||
824 | runqueue_node = list_first_entry(&g2d->runqueue, | |
825 | struct g2d_runqueue_node, list); | |
826 | list_del_init(&runqueue_node->list); | |
827 | return runqueue_node; | |
828 | } | |
829 | ||
830 | static void g2d_free_runqueue_node(struct g2d_data *g2d, | |
831 | struct g2d_runqueue_node *runqueue_node) | |
832 | { | |
d87342c1 ID |
833 | struct g2d_cmdlist_node *node; |
834 | ||
d7f1642c JS |
835 | if (!runqueue_node) |
836 | return; | |
837 | ||
838 | mutex_lock(&g2d->cmdlist_mutex); | |
d87342c1 ID |
839 | /* |
840 | * commands in run_cmdlist have been completed so unmap all gem | |
841 | * objects in each command node so that they are unreferenced. | |
842 | */ | |
843 | list_for_each_entry(node, &runqueue_node->run_cmdlist, list) | |
844 | g2d_unmap_cmdlist_gem(g2d, node, runqueue_node->filp); | |
d7f1642c JS |
845 | list_splice_tail_init(&runqueue_node->run_cmdlist, &g2d->free_cmdlist); |
846 | mutex_unlock(&g2d->cmdlist_mutex); | |
847 | ||
848 | kmem_cache_free(g2d->runqueue_slab, runqueue_node); | |
849 | } | |
850 | ||
851 | static void g2d_exec_runqueue(struct g2d_data *g2d) | |
852 | { | |
853 | g2d->runqueue_node = g2d_get_runqueue_node(g2d); | |
854 | if (g2d->runqueue_node) | |
855 | g2d_dma_start(g2d, g2d->runqueue_node); | |
856 | } | |
857 | ||
858 | static void g2d_runqueue_worker(struct work_struct *work) | |
859 | { | |
860 | struct g2d_data *g2d = container_of(work, struct g2d_data, | |
861 | runqueue_work); | |
862 | ||
d7f1642c | 863 | mutex_lock(&g2d->runqueue_mutex); |
d7f1642c JS |
864 | pm_runtime_put_sync(g2d->dev); |
865 | ||
866 | complete(&g2d->runqueue_node->complete); | |
867 | if (g2d->runqueue_node->async) | |
868 | g2d_free_runqueue_node(g2d, g2d->runqueue_node); | |
869 | ||
870 | if (g2d->suspended) | |
871 | g2d->runqueue_node = NULL; | |
872 | else | |
873 | g2d_exec_runqueue(g2d); | |
874 | mutex_unlock(&g2d->runqueue_mutex); | |
875 | } | |
876 | ||
877 | static void g2d_finish_event(struct g2d_data *g2d, u32 cmdlist_no) | |
878 | { | |
879 | struct drm_device *drm_dev = g2d->subdrv.drm_dev; | |
880 | struct g2d_runqueue_node *runqueue_node = g2d->runqueue_node; | |
881 | struct drm_exynos_pending_g2d_event *e; | |
882 | struct timeval now; | |
d7f1642c JS |
883 | |
884 | if (list_empty(&runqueue_node->event_list)) | |
885 | return; | |
886 | ||
887 | e = list_first_entry(&runqueue_node->event_list, | |
888 | struct drm_exynos_pending_g2d_event, base.link); | |
889 | ||
890 | do_gettimeofday(&now); | |
891 | e->event.tv_sec = now.tv_sec; | |
892 | e->event.tv_usec = now.tv_usec; | |
893 | e->event.cmdlist_no = cmdlist_no; | |
894 | ||
fb740cf2 | 895 | drm_send_event(drm_dev, &e->base); |
d7f1642c JS |
896 | } |
897 | ||
898 | static irqreturn_t g2d_irq_handler(int irq, void *dev_id) | |
899 | { | |
900 | struct g2d_data *g2d = dev_id; | |
901 | u32 pending; | |
902 | ||
903 | pending = readl_relaxed(g2d->regs + G2D_INTC_PEND); | |
904 | if (pending) | |
905 | writel_relaxed(pending, g2d->regs + G2D_INTC_PEND); | |
906 | ||
907 | if (pending & G2D_INTP_GCMD_FIN) { | |
908 | u32 cmdlist_no = readl_relaxed(g2d->regs + G2D_DMA_STATUS); | |
909 | ||
910 | cmdlist_no = (cmdlist_no & G2D_DMA_LIST_DONE_COUNT) >> | |
911 | G2D_DMA_LIST_DONE_COUNT_OFFSET; | |
912 | ||
913 | g2d_finish_event(g2d, cmdlist_no); | |
914 | ||
915 | writel_relaxed(0, g2d->regs + G2D_DMA_HOLD_CMD); | |
916 | if (!(pending & G2D_INTP_ACMD_FIN)) { | |
917 | writel_relaxed(G2D_DMA_CONTINUE, | |
918 | g2d->regs + G2D_DMA_COMMAND); | |
919 | } | |
920 | } | |
921 | ||
922 | if (pending & G2D_INTP_ACMD_FIN) | |
923 | queue_work(g2d->g2d_workq, &g2d->runqueue_work); | |
924 | ||
925 | return IRQ_HANDLED; | |
926 | } | |
927 | ||
2a3098ff ID |
928 | static int g2d_check_reg_offset(struct device *dev, |
929 | struct g2d_cmdlist_node *node, | |
d7f1642c JS |
930 | int nr, bool for_addr) |
931 | { | |
2a3098ff | 932 | struct g2d_cmdlist *cmdlist = node->cmdlist; |
d7f1642c JS |
933 | int reg_offset; |
934 | int index; | |
935 | int i; | |
936 | ||
937 | for (i = 0; i < nr; i++) { | |
9963cb6e | 938 | struct g2d_buf_info *buf_info = &node->buf_info; |
2dec17c7 | 939 | struct g2d_buf_desc *buf_desc; |
9963cb6e | 940 | enum g2d_reg_type reg_type; |
2dec17c7 | 941 | unsigned long value; |
2a3098ff | 942 | |
9963cb6e | 943 | index = cmdlist->last - 2 * (i + 1); |
2a3098ff | 944 | |
d7f1642c | 945 | reg_offset = cmdlist->data[index] & ~0xfffff000; |
d7f1642c JS |
946 | if (reg_offset < G2D_VALID_START || reg_offset > G2D_VALID_END) |
947 | goto err; | |
948 | if (reg_offset % 4) | |
949 | goto err; | |
950 | ||
951 | switch (reg_offset) { | |
952 | case G2D_SRC_BASE_ADDR: | |
953 | case G2D_SRC_PLANE2_BASE_ADDR: | |
954 | case G2D_DST_BASE_ADDR: | |
955 | case G2D_DST_PLANE2_BASE_ADDR: | |
956 | case G2D_PAT_BASE_ADDR: | |
957 | case G2D_MSK_BASE_ADDR: | |
958 | if (!for_addr) | |
959 | goto err; | |
2a3098ff | 960 | |
9963cb6e | 961 | reg_type = g2d_get_reg_type(reg_offset); |
9963cb6e YC |
962 | |
963 | /* check userptr buffer type. */ | |
964 | if ((cmdlist->data[index] & ~0x7fffffff) >> 31) { | |
965 | buf_info->types[reg_type] = BUF_TYPE_USERPTR; | |
966 | cmdlist->data[index] &= ~G2D_BUF_USERPTR; | |
967 | } else | |
968 | buf_info->types[reg_type] = BUF_TYPE_GEM; | |
d7f1642c | 969 | break; |
179239a7 TJ |
970 | case G2D_SRC_STRIDE_REG: |
971 | case G2D_DST_STRIDE_REG: | |
972 | if (for_addr) | |
973 | goto err; | |
974 | ||
975 | reg_type = g2d_get_reg_type(reg_offset); | |
976 | ||
977 | buf_desc = &buf_info->descs[reg_type]; | |
978 | buf_desc->stride = cmdlist->data[index + 1]; | |
979 | break; | |
2dec17c7 YC |
980 | case G2D_SRC_COLOR_MODE: |
981 | case G2D_DST_COLOR_MODE: | |
982 | if (for_addr) | |
983 | goto err; | |
984 | ||
985 | reg_type = g2d_get_reg_type(reg_offset); | |
2dec17c7 YC |
986 | |
987 | buf_desc = &buf_info->descs[reg_type]; | |
988 | value = cmdlist->data[index + 1]; | |
989 | ||
990 | buf_desc->format = value & 0xf; | |
991 | break; | |
992 | case G2D_SRC_LEFT_TOP: | |
993 | case G2D_DST_LEFT_TOP: | |
994 | if (for_addr) | |
995 | goto err; | |
996 | ||
997 | reg_type = g2d_get_reg_type(reg_offset); | |
2dec17c7 YC |
998 | |
999 | buf_desc = &buf_info->descs[reg_type]; | |
1000 | value = cmdlist->data[index + 1]; | |
1001 | ||
1002 | buf_desc->left_x = value & 0x1fff; | |
1003 | buf_desc->top_y = (value & 0x1fff0000) >> 16; | |
1004 | break; | |
1005 | case G2D_SRC_RIGHT_BOTTOM: | |
1006 | case G2D_DST_RIGHT_BOTTOM: | |
1007 | if (for_addr) | |
1008 | goto err; | |
1009 | ||
1010 | reg_type = g2d_get_reg_type(reg_offset); | |
2dec17c7 YC |
1011 | |
1012 | buf_desc = &buf_info->descs[reg_type]; | |
1013 | value = cmdlist->data[index + 1]; | |
1014 | ||
1015 | buf_desc->right_x = value & 0x1fff; | |
1016 | buf_desc->bottom_y = (value & 0x1fff0000) >> 16; | |
1017 | break; | |
d7f1642c JS |
1018 | default: |
1019 | if (for_addr) | |
1020 | goto err; | |
1021 | break; | |
1022 | } | |
1023 | } | |
1024 | ||
1025 | return 0; | |
1026 | ||
1027 | err: | |
2a3098ff | 1028 | dev_err(dev, "Bad register offset: 0x%lx\n", cmdlist->data[index]); |
d7f1642c JS |
1029 | return -EINVAL; |
1030 | } | |
1031 | ||
1032 | /* ioctl functions */ | |
1033 | int exynos_g2d_get_ver_ioctl(struct drm_device *drm_dev, void *data, | |
1034 | struct drm_file *file) | |
1035 | { | |
ef7ce055 TJ |
1036 | struct drm_exynos_file_private *file_priv = file->driver_priv; |
1037 | struct exynos_drm_g2d_private *g2d_priv = file_priv->g2d_priv; | |
1038 | struct device *dev; | |
1039 | struct g2d_data *g2d; | |
d7f1642c JS |
1040 | struct drm_exynos_g2d_get_ver *ver = data; |
1041 | ||
ef7ce055 TJ |
1042 | if (!g2d_priv) |
1043 | return -ENODEV; | |
1044 | ||
1045 | dev = g2d_priv->dev; | |
1046 | if (!dev) | |
1047 | return -ENODEV; | |
1048 | ||
1049 | g2d = dev_get_drvdata(dev); | |
1050 | if (!g2d) | |
1051 | return -EFAULT; | |
1052 | ||
d7f1642c JS |
1053 | ver->major = G2D_HW_MAJOR_VER; |
1054 | ver->minor = G2D_HW_MINOR_VER; | |
1055 | ||
1056 | return 0; | |
1057 | } | |
d7f1642c JS |
1058 | |
1059 | int exynos_g2d_set_cmdlist_ioctl(struct drm_device *drm_dev, void *data, | |
1060 | struct drm_file *file) | |
1061 | { | |
1062 | struct drm_exynos_file_private *file_priv = file->driver_priv; | |
1063 | struct exynos_drm_g2d_private *g2d_priv = file_priv->g2d_priv; | |
1cd1ea56 | 1064 | struct device *dev; |
d7f1642c JS |
1065 | struct g2d_data *g2d; |
1066 | struct drm_exynos_g2d_set_cmdlist *req = data; | |
1067 | struct drm_exynos_g2d_cmd *cmd; | |
1068 | struct drm_exynos_pending_g2d_event *e; | |
1069 | struct g2d_cmdlist_node *node; | |
1070 | struct g2d_cmdlist *cmdlist; | |
d7f1642c JS |
1071 | int size; |
1072 | int ret; | |
1073 | ||
1cd1ea56 TJ |
1074 | if (!g2d_priv) |
1075 | return -ENODEV; | |
1076 | ||
1077 | dev = g2d_priv->dev; | |
d7f1642c JS |
1078 | if (!dev) |
1079 | return -ENODEV; | |
1080 | ||
1081 | g2d = dev_get_drvdata(dev); | |
1082 | if (!g2d) | |
1083 | return -EFAULT; | |
1084 | ||
1085 | node = g2d_get_cmdlist(g2d); | |
1086 | if (!node) | |
1087 | return -ENOMEM; | |
1088 | ||
1089 | node->event = NULL; | |
1090 | ||
1091 | if (req->event_type != G2D_EVENT_NOT) { | |
d7f1642c JS |
1092 | e = kzalloc(sizeof(*node->event), GFP_KERNEL); |
1093 | if (!e) { | |
d7f1642c JS |
1094 | ret = -ENOMEM; |
1095 | goto err; | |
1096 | } | |
1097 | ||
1098 | e->event.base.type = DRM_EXYNOS_G2D_EVENT; | |
1099 | e->event.base.length = sizeof(e->event); | |
1100 | e->event.user_data = req->user_data; | |
7142a348 DV |
1101 | |
1102 | ret = drm_event_reserve_init(drm_dev, file, &e->base, &e->event.base); | |
1103 | if (ret) { | |
1104 | kfree(e); | |
1105 | goto err; | |
1106 | } | |
d7f1642c JS |
1107 | |
1108 | node->event = e; | |
1109 | } | |
1110 | ||
1111 | cmdlist = node->cmdlist; | |
1112 | ||
1113 | cmdlist->last = 0; | |
1114 | ||
1115 | /* | |
1116 | * If don't clear SFR registers, the cmdlist is affected by register | |
1117 | * values of previous cmdlist. G2D hw executes SFR clear command and | |
1118 | * a next command at the same time then the next command is ignored and | |
1119 | * is executed rightly from next next command, so needs a dummy command | |
1120 | * to next command of SFR clear command. | |
1121 | */ | |
1122 | cmdlist->data[cmdlist->last++] = G2D_SOFT_RESET; | |
1123 | cmdlist->data[cmdlist->last++] = G2D_SFRCLEAR; | |
1124 | cmdlist->data[cmdlist->last++] = G2D_SRC_BASE_ADDR; | |
1125 | cmdlist->data[cmdlist->last++] = 0; | |
1126 | ||
7ad01814 YC |
1127 | /* |
1128 | * 'LIST_HOLD' command should be set to the DMA_HOLD_CMD_REG | |
1129 | * and GCF bit should be set to INTEN register if user wants | |
1130 | * G2D interrupt event once current command list execution is | |
1131 | * finished. | |
1132 | * Otherwise only ACF bit should be set to INTEN register so | |
c6b78bc8 | 1133 | * that one interrupt is occurred after all command lists |
7ad01814 YC |
1134 | * have been completed. |
1135 | */ | |
d7f1642c | 1136 | if (node->event) { |
7ad01814 YC |
1137 | cmdlist->data[cmdlist->last++] = G2D_INTEN; |
1138 | cmdlist->data[cmdlist->last++] = G2D_INTEN_ACF | G2D_INTEN_GCF; | |
d7f1642c JS |
1139 | cmdlist->data[cmdlist->last++] = G2D_DMA_HOLD_CMD; |
1140 | cmdlist->data[cmdlist->last++] = G2D_LIST_HOLD; | |
7ad01814 YC |
1141 | } else { |
1142 | cmdlist->data[cmdlist->last++] = G2D_INTEN; | |
1143 | cmdlist->data[cmdlist->last++] = G2D_INTEN_ACF; | |
d7f1642c JS |
1144 | } |
1145 | ||
1146 | /* Check size of cmdlist: last 2 is about G2D_BITBLT_START */ | |
2a3098ff | 1147 | size = cmdlist->last + req->cmd_nr * 2 + req->cmd_buf_nr * 2 + 2; |
d7f1642c JS |
1148 | if (size > G2D_CMDLIST_DATA_NUM) { |
1149 | dev_err(dev, "cmdlist size is too big\n"); | |
1150 | ret = -EINVAL; | |
1151 | goto err_free_event; | |
1152 | } | |
1153 | ||
c5f2f0c4 | 1154 | cmd = (struct drm_exynos_g2d_cmd *)(unsigned long)req->cmd; |
d7f1642c JS |
1155 | |
1156 | if (copy_from_user(cmdlist->data + cmdlist->last, | |
1157 | (void __user *)cmd, | |
1158 | sizeof(*cmd) * req->cmd_nr)) { | |
1159 | ret = -EFAULT; | |
1160 | goto err_free_event; | |
1161 | } | |
1162 | cmdlist->last += req->cmd_nr * 2; | |
1163 | ||
2a3098ff | 1164 | ret = g2d_check_reg_offset(dev, node, req->cmd_nr, false); |
d7f1642c JS |
1165 | if (ret < 0) |
1166 | goto err_free_event; | |
1167 | ||
9963cb6e | 1168 | node->buf_info.map_nr = req->cmd_buf_nr; |
2a3098ff ID |
1169 | if (req->cmd_buf_nr) { |
1170 | struct drm_exynos_g2d_cmd *cmd_buf; | |
d7f1642c | 1171 | |
c5f2f0c4 MS |
1172 | cmd_buf = (struct drm_exynos_g2d_cmd *) |
1173 | (unsigned long)req->cmd_buf; | |
d7f1642c JS |
1174 | |
1175 | if (copy_from_user(cmdlist->data + cmdlist->last, | |
2a3098ff ID |
1176 | (void __user *)cmd_buf, |
1177 | sizeof(*cmd_buf) * req->cmd_buf_nr)) { | |
d7f1642c JS |
1178 | ret = -EFAULT; |
1179 | goto err_free_event; | |
1180 | } | |
2a3098ff | 1181 | cmdlist->last += req->cmd_buf_nr * 2; |
d7f1642c | 1182 | |
2a3098ff | 1183 | ret = g2d_check_reg_offset(dev, node, req->cmd_buf_nr, true); |
d7f1642c JS |
1184 | if (ret < 0) |
1185 | goto err_free_event; | |
1186 | ||
d87342c1 | 1187 | ret = g2d_map_cmdlist_gem(g2d, node, drm_dev, file); |
d7f1642c JS |
1188 | if (ret < 0) |
1189 | goto err_unmap; | |
1190 | } | |
1191 | ||
1192 | cmdlist->data[cmdlist->last++] = G2D_BITBLT_START; | |
1193 | cmdlist->data[cmdlist->last++] = G2D_START_BITBLT; | |
1194 | ||
1195 | /* head */ | |
1196 | cmdlist->head = cmdlist->last / 2; | |
1197 | ||
1198 | /* tail */ | |
1199 | cmdlist->data[cmdlist->last] = 0; | |
1200 | ||
1201 | g2d_add_cmdlist_to_inuse(g2d_priv, node); | |
1202 | ||
1203 | return 0; | |
1204 | ||
1205 | err_unmap: | |
d87342c1 | 1206 | g2d_unmap_cmdlist_gem(g2d, node, file); |
d7f1642c | 1207 | err_free_event: |
7142a348 DV |
1208 | if (node->event) |
1209 | drm_event_cancel_free(drm_dev, &node->event->base); | |
d7f1642c JS |
1210 | err: |
1211 | g2d_put_cmdlist(g2d, node); | |
1212 | return ret; | |
1213 | } | |
d7f1642c JS |
1214 | |
1215 | int exynos_g2d_exec_ioctl(struct drm_device *drm_dev, void *data, | |
1216 | struct drm_file *file) | |
1217 | { | |
1218 | struct drm_exynos_file_private *file_priv = file->driver_priv; | |
1219 | struct exynos_drm_g2d_private *g2d_priv = file_priv->g2d_priv; | |
1cd1ea56 | 1220 | struct device *dev; |
d7f1642c JS |
1221 | struct g2d_data *g2d; |
1222 | struct drm_exynos_g2d_exec *req = data; | |
1223 | struct g2d_runqueue_node *runqueue_node; | |
1224 | struct list_head *run_cmdlist; | |
1225 | struct list_head *event_list; | |
1226 | ||
1cd1ea56 TJ |
1227 | if (!g2d_priv) |
1228 | return -ENODEV; | |
1229 | ||
1230 | dev = g2d_priv->dev; | |
d7f1642c JS |
1231 | if (!dev) |
1232 | return -ENODEV; | |
1233 | ||
1234 | g2d = dev_get_drvdata(dev); | |
1235 | if (!g2d) | |
1236 | return -EFAULT; | |
1237 | ||
1238 | runqueue_node = kmem_cache_alloc(g2d->runqueue_slab, GFP_KERNEL); | |
1239 | if (!runqueue_node) { | |
1240 | dev_err(dev, "failed to allocate memory\n"); | |
1241 | return -ENOMEM; | |
1242 | } | |
1243 | run_cmdlist = &runqueue_node->run_cmdlist; | |
1244 | event_list = &runqueue_node->event_list; | |
1245 | INIT_LIST_HEAD(run_cmdlist); | |
1246 | INIT_LIST_HEAD(event_list); | |
1247 | init_completion(&runqueue_node->complete); | |
1248 | runqueue_node->async = req->async; | |
1249 | ||
1250 | list_splice_init(&g2d_priv->inuse_cmdlist, run_cmdlist); | |
1251 | list_splice_init(&g2d_priv->event_list, event_list); | |
1252 | ||
1253 | if (list_empty(run_cmdlist)) { | |
1254 | dev_err(dev, "there is no inuse cmdlist\n"); | |
1255 | kmem_cache_free(g2d->runqueue_slab, runqueue_node); | |
1256 | return -EPERM; | |
1257 | } | |
1258 | ||
1259 | mutex_lock(&g2d->runqueue_mutex); | |
6b6bae24 | 1260 | runqueue_node->pid = current->pid; |
d87342c1 | 1261 | runqueue_node->filp = file; |
d7f1642c JS |
1262 | list_add_tail(&runqueue_node->list, &g2d->runqueue); |
1263 | if (!g2d->runqueue_node) | |
1264 | g2d_exec_runqueue(g2d); | |
1265 | mutex_unlock(&g2d->runqueue_mutex); | |
1266 | ||
1267 | if (runqueue_node->async) | |
1268 | goto out; | |
1269 | ||
1270 | wait_for_completion(&runqueue_node->complete); | |
1271 | g2d_free_runqueue_node(g2d, runqueue_node); | |
1272 | ||
1273 | out: | |
1274 | return 0; | |
1275 | } | |
d7f1642c | 1276 | |
d87342c1 ID |
1277 | static int g2d_subdrv_probe(struct drm_device *drm_dev, struct device *dev) |
1278 | { | |
1279 | struct g2d_data *g2d; | |
1280 | int ret; | |
1281 | ||
1282 | g2d = dev_get_drvdata(dev); | |
1283 | if (!g2d) | |
1284 | return -EFAULT; | |
1285 | ||
1286 | /* allocate dma-aware cmdlist buffer. */ | |
1287 | ret = g2d_init_cmdlist(g2d); | |
1288 | if (ret < 0) { | |
1289 | dev_err(dev, "cmdlist init failed\n"); | |
1290 | return ret; | |
1291 | } | |
1292 | ||
d87342c1 ID |
1293 | ret = drm_iommu_attach_device(drm_dev, dev); |
1294 | if (ret < 0) { | |
1295 | dev_err(dev, "failed to enable iommu.\n"); | |
1296 | g2d_fini_cmdlist(g2d); | |
1297 | } | |
1298 | ||
1299 | return ret; | |
1300 | ||
1301 | } | |
1302 | ||
1303 | static void g2d_subdrv_remove(struct drm_device *drm_dev, struct device *dev) | |
1304 | { | |
d87342c1 ID |
1305 | drm_iommu_detach_device(drm_dev, dev); |
1306 | } | |
1307 | ||
d7f1642c JS |
1308 | static int g2d_open(struct drm_device *drm_dev, struct device *dev, |
1309 | struct drm_file *file) | |
1310 | { | |
1311 | struct drm_exynos_file_private *file_priv = file->driver_priv; | |
1312 | struct exynos_drm_g2d_private *g2d_priv; | |
1313 | ||
1314 | g2d_priv = kzalloc(sizeof(*g2d_priv), GFP_KERNEL); | |
38bb5253 | 1315 | if (!g2d_priv) |
d7f1642c | 1316 | return -ENOMEM; |
d7f1642c JS |
1317 | |
1318 | g2d_priv->dev = dev; | |
1319 | file_priv->g2d_priv = g2d_priv; | |
1320 | ||
1321 | INIT_LIST_HEAD(&g2d_priv->inuse_cmdlist); | |
1322 | INIT_LIST_HEAD(&g2d_priv->event_list); | |
2a3098ff | 1323 | INIT_LIST_HEAD(&g2d_priv->userptr_list); |
d7f1642c JS |
1324 | |
1325 | return 0; | |
1326 | } | |
1327 | ||
1328 | static void g2d_close(struct drm_device *drm_dev, struct device *dev, | |
1329 | struct drm_file *file) | |
1330 | { | |
1331 | struct drm_exynos_file_private *file_priv = file->driver_priv; | |
1332 | struct exynos_drm_g2d_private *g2d_priv = file_priv->g2d_priv; | |
1333 | struct g2d_data *g2d; | |
1334 | struct g2d_cmdlist_node *node, *n; | |
1335 | ||
1336 | if (!dev) | |
1337 | return; | |
1338 | ||
1339 | g2d = dev_get_drvdata(dev); | |
1340 | if (!g2d) | |
1341 | return; | |
1342 | ||
1343 | mutex_lock(&g2d->cmdlist_mutex); | |
d87342c1 ID |
1344 | list_for_each_entry_safe(node, n, &g2d_priv->inuse_cmdlist, list) { |
1345 | /* | |
1346 | * unmap all gem objects not completed. | |
1347 | * | |
1348 | * P.S. if current process was terminated forcely then | |
1349 | * there may be some commands in inuse_cmdlist so unmap | |
1350 | * them. | |
1351 | */ | |
1352 | g2d_unmap_cmdlist_gem(g2d, node, file); | |
d7f1642c | 1353 | list_move_tail(&node->list, &g2d->free_cmdlist); |
d87342c1 | 1354 | } |
d7f1642c JS |
1355 | mutex_unlock(&g2d->cmdlist_mutex); |
1356 | ||
2a3098ff ID |
1357 | /* release all g2d_userptr in pool. */ |
1358 | g2d_userptr_free_all(drm_dev, g2d, file); | |
1359 | ||
d7f1642c JS |
1360 | kfree(file_priv->g2d_priv); |
1361 | } | |
1362 | ||
56550d94 | 1363 | static int g2d_probe(struct platform_device *pdev) |
d7f1642c JS |
1364 | { |
1365 | struct device *dev = &pdev->dev; | |
1366 | struct resource *res; | |
1367 | struct g2d_data *g2d; | |
1368 | struct exynos_drm_subdrv *subdrv; | |
1369 | int ret; | |
1370 | ||
d873ab99 | 1371 | g2d = devm_kzalloc(dev, sizeof(*g2d), GFP_KERNEL); |
38bb5253 | 1372 | if (!g2d) |
d7f1642c | 1373 | return -ENOMEM; |
d7f1642c JS |
1374 | |
1375 | g2d->runqueue_slab = kmem_cache_create("g2d_runqueue_slab", | |
1376 | sizeof(struct g2d_runqueue_node), 0, 0, NULL); | |
b7675933 SK |
1377 | if (!g2d->runqueue_slab) |
1378 | return -ENOMEM; | |
d7f1642c JS |
1379 | |
1380 | g2d->dev = dev; | |
1381 | ||
1382 | g2d->g2d_workq = create_singlethread_workqueue("g2d"); | |
1383 | if (!g2d->g2d_workq) { | |
1384 | dev_err(dev, "failed to create workqueue\n"); | |
1385 | ret = -EINVAL; | |
1386 | goto err_destroy_slab; | |
1387 | } | |
1388 | ||
1389 | INIT_WORK(&g2d->runqueue_work, g2d_runqueue_worker); | |
1390 | INIT_LIST_HEAD(&g2d->free_cmdlist); | |
1391 | INIT_LIST_HEAD(&g2d->runqueue); | |
1392 | ||
1393 | mutex_init(&g2d->cmdlist_mutex); | |
1394 | mutex_init(&g2d->runqueue_mutex); | |
1395 | ||
dc625537 | 1396 | g2d->gate_clk = devm_clk_get(dev, "fimg2d"); |
d7f1642c JS |
1397 | if (IS_ERR(g2d->gate_clk)) { |
1398 | dev_err(dev, "failed to get gate clock\n"); | |
1399 | ret = PTR_ERR(g2d->gate_clk); | |
d87342c1 | 1400 | goto err_destroy_workqueue; |
d7f1642c JS |
1401 | } |
1402 | ||
1403 | pm_runtime_enable(dev); | |
1404 | ||
1405 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
d7f1642c | 1406 | |
d873ab99 | 1407 | g2d->regs = devm_ioremap_resource(dev, res); |
d4ed6025 TR |
1408 | if (IS_ERR(g2d->regs)) { |
1409 | ret = PTR_ERR(g2d->regs); | |
b7675933 | 1410 | goto err_put_clk; |
d7f1642c JS |
1411 | } |
1412 | ||
1413 | g2d->irq = platform_get_irq(pdev, 0); | |
1414 | if (g2d->irq < 0) { | |
1415 | dev_err(dev, "failed to get irq\n"); | |
1416 | ret = g2d->irq; | |
b7675933 | 1417 | goto err_put_clk; |
d7f1642c JS |
1418 | } |
1419 | ||
d873ab99 | 1420 | ret = devm_request_irq(dev, g2d->irq, g2d_irq_handler, 0, |
b7675933 | 1421 | "drm_g2d", g2d); |
d7f1642c JS |
1422 | if (ret < 0) { |
1423 | dev_err(dev, "irq request failed\n"); | |
b7675933 | 1424 | goto err_put_clk; |
d7f1642c JS |
1425 | } |
1426 | ||
2a3098ff ID |
1427 | g2d->max_pool = MAX_POOL; |
1428 | ||
d7f1642c JS |
1429 | platform_set_drvdata(pdev, g2d); |
1430 | ||
1431 | subdrv = &g2d->subdrv; | |
1432 | subdrv->dev = dev; | |
d87342c1 ID |
1433 | subdrv->probe = g2d_subdrv_probe; |
1434 | subdrv->remove = g2d_subdrv_remove; | |
d7f1642c JS |
1435 | subdrv->open = g2d_open; |
1436 | subdrv->close = g2d_close; | |
1437 | ||
1438 | ret = exynos_drm_subdrv_register(subdrv); | |
1439 | if (ret < 0) { | |
1440 | dev_err(dev, "failed to register drm g2d device\n"); | |
b7675933 | 1441 | goto err_put_clk; |
d7f1642c JS |
1442 | } |
1443 | ||
1444 | dev_info(dev, "The exynos g2d(ver %d.%d) successfully probed\n", | |
1445 | G2D_HW_MAJOR_VER, G2D_HW_MINOR_VER); | |
1446 | ||
1447 | return 0; | |
1448 | ||
d7f1642c JS |
1449 | err_put_clk: |
1450 | pm_runtime_disable(dev); | |
d7f1642c JS |
1451 | err_destroy_workqueue: |
1452 | destroy_workqueue(g2d->g2d_workq); | |
1453 | err_destroy_slab: | |
1454 | kmem_cache_destroy(g2d->runqueue_slab); | |
d7f1642c JS |
1455 | return ret; |
1456 | } | |
1457 | ||
56550d94 | 1458 | static int g2d_remove(struct platform_device *pdev) |
d7f1642c JS |
1459 | { |
1460 | struct g2d_data *g2d = platform_get_drvdata(pdev); | |
1461 | ||
1462 | cancel_work_sync(&g2d->runqueue_work); | |
1463 | exynos_drm_subdrv_unregister(&g2d->subdrv); | |
d7f1642c JS |
1464 | |
1465 | while (g2d->runqueue_node) { | |
1466 | g2d_free_runqueue_node(g2d, g2d->runqueue_node); | |
1467 | g2d->runqueue_node = g2d_get_runqueue_node(g2d); | |
1468 | } | |
1469 | ||
d7f1642c | 1470 | pm_runtime_disable(&pdev->dev); |
d7f1642c JS |
1471 | |
1472 | g2d_fini_cmdlist(g2d); | |
1473 | destroy_workqueue(g2d->g2d_workq); | |
1474 | kmem_cache_destroy(g2d->runqueue_slab); | |
d7f1642c JS |
1475 | |
1476 | return 0; | |
1477 | } | |
1478 | ||
1479 | #ifdef CONFIG_PM_SLEEP | |
1480 | static int g2d_suspend(struct device *dev) | |
1481 | { | |
1482 | struct g2d_data *g2d = dev_get_drvdata(dev); | |
1483 | ||
1484 | mutex_lock(&g2d->runqueue_mutex); | |
1485 | g2d->suspended = true; | |
1486 | mutex_unlock(&g2d->runqueue_mutex); | |
1487 | ||
1488 | while (g2d->runqueue_node) | |
1489 | /* FIXME: good range? */ | |
1490 | usleep_range(500, 1000); | |
1491 | ||
43829731 | 1492 | flush_work(&g2d->runqueue_work); |
d7f1642c JS |
1493 | |
1494 | return 0; | |
1495 | } | |
1496 | ||
1497 | static int g2d_resume(struct device *dev) | |
1498 | { | |
1499 | struct g2d_data *g2d = dev_get_drvdata(dev); | |
1500 | ||
1501 | g2d->suspended = false; | |
1502 | g2d_exec_runqueue(g2d); | |
1503 | ||
1504 | return 0; | |
1505 | } | |
1506 | #endif | |
1507 | ||
06453edb | 1508 | #ifdef CONFIG_PM |
b10d6350 ID |
1509 | static int g2d_runtime_suspend(struct device *dev) |
1510 | { | |
1511 | struct g2d_data *g2d = dev_get_drvdata(dev); | |
1512 | ||
1513 | clk_disable_unprepare(g2d->gate_clk); | |
1514 | ||
1515 | return 0; | |
1516 | } | |
1517 | ||
1518 | static int g2d_runtime_resume(struct device *dev) | |
1519 | { | |
1520 | struct g2d_data *g2d = dev_get_drvdata(dev); | |
1521 | int ret; | |
1522 | ||
1523 | ret = clk_prepare_enable(g2d->gate_clk); | |
1524 | if (ret < 0) | |
1525 | dev_warn(dev, "failed to enable clock.\n"); | |
1526 | ||
1527 | return ret; | |
1528 | } | |
1529 | #endif | |
1530 | ||
1531 | static const struct dev_pm_ops g2d_pm_ops = { | |
1532 | SET_SYSTEM_SLEEP_PM_OPS(g2d_suspend, g2d_resume) | |
1533 | SET_RUNTIME_PM_OPS(g2d_runtime_suspend, g2d_runtime_resume, NULL) | |
1534 | }; | |
d7f1642c | 1535 | |
95fc6337 AK |
1536 | static const struct of_device_id exynos_g2d_match[] = { |
1537 | { .compatible = "samsung,exynos5250-g2d" }, | |
6411fe3c | 1538 | { .compatible = "samsung,exynos4212-g2d" }, |
95fc6337 AK |
1539 | {}, |
1540 | }; | |
0262ceeb | 1541 | MODULE_DEVICE_TABLE(of, exynos_g2d_match); |
95fc6337 | 1542 | |
d7f1642c JS |
1543 | struct platform_driver g2d_driver = { |
1544 | .probe = g2d_probe, | |
56550d94 | 1545 | .remove = g2d_remove, |
d7f1642c JS |
1546 | .driver = { |
1547 | .name = "s5p-g2d", | |
1548 | .owner = THIS_MODULE, | |
1549 | .pm = &g2d_pm_ops, | |
61c48fbf | 1550 | .of_match_table = exynos_g2d_match, |
d7f1642c JS |
1551 | }, |
1552 | }; |