Commit | Line | Data |
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d7f1642c JS |
1 | /* |
2 | * Copyright (C) 2012 Samsung Electronics Co.Ltd | |
3 | * Authors: Joonyoung Shim <jy0922.shim@samsung.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundationr | |
8 | */ | |
9 | ||
10 | #include <linux/kernel.h> | |
11 | #include <linux/module.h> | |
12 | #include <linux/clk.h> | |
13 | #include <linux/err.h> | |
14 | #include <linux/interrupt.h> | |
15 | #include <linux/io.h> | |
16 | #include <linux/platform_device.h> | |
17 | #include <linux/pm_runtime.h> | |
18 | #include <linux/slab.h> | |
19 | #include <linux/workqueue.h> | |
d87342c1 ID |
20 | #include <linux/dma-mapping.h> |
21 | #include <linux/dma-attrs.h> | |
d7f1642c | 22 | |
760285e7 DH |
23 | #include <drm/drmP.h> |
24 | #include <drm/exynos_drm.h> | |
d7f1642c JS |
25 | #include "exynos_drm_drv.h" |
26 | #include "exynos_drm_gem.h" | |
d87342c1 | 27 | #include "exynos_drm_iommu.h" |
d7f1642c JS |
28 | |
29 | #define G2D_HW_MAJOR_VER 4 | |
30 | #define G2D_HW_MINOR_VER 1 | |
31 | ||
32 | /* vaild register range set from user: 0x0104 ~ 0x0880 */ | |
33 | #define G2D_VALID_START 0x0104 | |
34 | #define G2D_VALID_END 0x0880 | |
35 | ||
36 | /* general registers */ | |
37 | #define G2D_SOFT_RESET 0x0000 | |
38 | #define G2D_INTEN 0x0004 | |
39 | #define G2D_INTC_PEND 0x000C | |
40 | #define G2D_DMA_SFR_BASE_ADDR 0x0080 | |
41 | #define G2D_DMA_COMMAND 0x0084 | |
42 | #define G2D_DMA_STATUS 0x008C | |
43 | #define G2D_DMA_HOLD_CMD 0x0090 | |
44 | ||
45 | /* command registers */ | |
46 | #define G2D_BITBLT_START 0x0100 | |
47 | ||
48 | /* registers for base address */ | |
49 | #define G2D_SRC_BASE_ADDR 0x0304 | |
50 | #define G2D_SRC_PLANE2_BASE_ADDR 0x0318 | |
51 | #define G2D_DST_BASE_ADDR 0x0404 | |
52 | #define G2D_DST_PLANE2_BASE_ADDR 0x0418 | |
53 | #define G2D_PAT_BASE_ADDR 0x0500 | |
54 | #define G2D_MSK_BASE_ADDR 0x0520 | |
55 | ||
56 | /* G2D_SOFT_RESET */ | |
57 | #define G2D_SFRCLEAR (1 << 1) | |
58 | #define G2D_R (1 << 0) | |
59 | ||
60 | /* G2D_INTEN */ | |
61 | #define G2D_INTEN_ACF (1 << 3) | |
62 | #define G2D_INTEN_UCF (1 << 2) | |
63 | #define G2D_INTEN_GCF (1 << 1) | |
64 | #define G2D_INTEN_SCF (1 << 0) | |
65 | ||
66 | /* G2D_INTC_PEND */ | |
67 | #define G2D_INTP_ACMD_FIN (1 << 3) | |
68 | #define G2D_INTP_UCMD_FIN (1 << 2) | |
69 | #define G2D_INTP_GCMD_FIN (1 << 1) | |
70 | #define G2D_INTP_SCMD_FIN (1 << 0) | |
71 | ||
72 | /* G2D_DMA_COMMAND */ | |
73 | #define G2D_DMA_HALT (1 << 2) | |
74 | #define G2D_DMA_CONTINUE (1 << 1) | |
75 | #define G2D_DMA_START (1 << 0) | |
76 | ||
77 | /* G2D_DMA_STATUS */ | |
78 | #define G2D_DMA_LIST_DONE_COUNT (0xFF << 17) | |
79 | #define G2D_DMA_BITBLT_DONE_COUNT (0xFFFF << 1) | |
80 | #define G2D_DMA_DONE (1 << 0) | |
81 | #define G2D_DMA_LIST_DONE_COUNT_OFFSET 17 | |
82 | ||
83 | /* G2D_DMA_HOLD_CMD */ | |
84 | #define G2D_USET_HOLD (1 << 2) | |
85 | #define G2D_LIST_HOLD (1 << 1) | |
86 | #define G2D_BITBLT_HOLD (1 << 0) | |
87 | ||
88 | /* G2D_BITBLT_START */ | |
89 | #define G2D_START_CASESEL (1 << 2) | |
90 | #define G2D_START_NHOLT (1 << 1) | |
91 | #define G2D_START_BITBLT (1 << 0) | |
92 | ||
93 | #define G2D_CMDLIST_SIZE (PAGE_SIZE / 4) | |
94 | #define G2D_CMDLIST_NUM 64 | |
95 | #define G2D_CMDLIST_POOL_SIZE (G2D_CMDLIST_SIZE * G2D_CMDLIST_NUM) | |
96 | #define G2D_CMDLIST_DATA_NUM (G2D_CMDLIST_SIZE / sizeof(u32) - 2) | |
97 | ||
d87342c1 ID |
98 | #define MAX_BUF_ADDR_NR 6 |
99 | ||
d7f1642c JS |
100 | /* cmdlist data structure */ |
101 | struct g2d_cmdlist { | |
102 | u32 head; | |
103 | u32 data[G2D_CMDLIST_DATA_NUM]; | |
104 | u32 last; /* last data offset */ | |
105 | }; | |
106 | ||
107 | struct drm_exynos_pending_g2d_event { | |
108 | struct drm_pending_event base; | |
109 | struct drm_exynos_g2d_event event; | |
110 | }; | |
111 | ||
d7f1642c JS |
112 | struct g2d_cmdlist_node { |
113 | struct list_head list; | |
114 | struct g2d_cmdlist *cmdlist; | |
d87342c1 ID |
115 | unsigned int map_nr; |
116 | unsigned int handles[MAX_BUF_ADDR_NR]; | |
d7f1642c JS |
117 | dma_addr_t dma_addr; |
118 | ||
119 | struct drm_exynos_pending_g2d_event *event; | |
120 | }; | |
121 | ||
122 | struct g2d_runqueue_node { | |
123 | struct list_head list; | |
124 | struct list_head run_cmdlist; | |
125 | struct list_head event_list; | |
d87342c1 | 126 | struct drm_file *filp; |
6b6bae24 | 127 | pid_t pid; |
d7f1642c JS |
128 | struct completion complete; |
129 | int async; | |
130 | }; | |
131 | ||
132 | struct g2d_data { | |
133 | struct device *dev; | |
134 | struct clk *gate_clk; | |
d7f1642c JS |
135 | void __iomem *regs; |
136 | int irq; | |
137 | struct workqueue_struct *g2d_workq; | |
138 | struct work_struct runqueue_work; | |
139 | struct exynos_drm_subdrv subdrv; | |
140 | bool suspended; | |
141 | ||
142 | /* cmdlist */ | |
143 | struct g2d_cmdlist_node *cmdlist_node; | |
144 | struct list_head free_cmdlist; | |
145 | struct mutex cmdlist_mutex; | |
146 | dma_addr_t cmdlist_pool; | |
147 | void *cmdlist_pool_virt; | |
d87342c1 | 148 | struct dma_attrs cmdlist_dma_attrs; |
d7f1642c JS |
149 | |
150 | /* runqueue*/ | |
151 | struct g2d_runqueue_node *runqueue_node; | |
152 | struct list_head runqueue; | |
153 | struct mutex runqueue_mutex; | |
154 | struct kmem_cache *runqueue_slab; | |
155 | }; | |
156 | ||
157 | static int g2d_init_cmdlist(struct g2d_data *g2d) | |
158 | { | |
159 | struct device *dev = g2d->dev; | |
160 | struct g2d_cmdlist_node *node = g2d->cmdlist_node; | |
d87342c1 | 161 | struct exynos_drm_subdrv *subdrv = &g2d->subdrv; |
d7f1642c JS |
162 | int nr; |
163 | int ret; | |
164 | ||
d87342c1 ID |
165 | init_dma_attrs(&g2d->cmdlist_dma_attrs); |
166 | dma_set_attr(DMA_ATTR_WRITE_COMBINE, &g2d->cmdlist_dma_attrs); | |
167 | ||
168 | g2d->cmdlist_pool_virt = dma_alloc_attrs(subdrv->drm_dev->dev, | |
169 | G2D_CMDLIST_POOL_SIZE, | |
170 | &g2d->cmdlist_pool, GFP_KERNEL, | |
171 | &g2d->cmdlist_dma_attrs); | |
d7f1642c JS |
172 | if (!g2d->cmdlist_pool_virt) { |
173 | dev_err(dev, "failed to allocate dma memory\n"); | |
174 | return -ENOMEM; | |
175 | } | |
176 | ||
fab9f8d0 | 177 | node = kcalloc(G2D_CMDLIST_NUM, sizeof(*node), GFP_KERNEL); |
d7f1642c JS |
178 | if (!node) { |
179 | dev_err(dev, "failed to allocate memory\n"); | |
180 | ret = -ENOMEM; | |
181 | goto err; | |
182 | } | |
183 | ||
184 | for (nr = 0; nr < G2D_CMDLIST_NUM; nr++) { | |
185 | node[nr].cmdlist = | |
186 | g2d->cmdlist_pool_virt + nr * G2D_CMDLIST_SIZE; | |
187 | node[nr].dma_addr = | |
188 | g2d->cmdlist_pool + nr * G2D_CMDLIST_SIZE; | |
189 | ||
190 | list_add_tail(&node[nr].list, &g2d->free_cmdlist); | |
191 | } | |
192 | ||
193 | return 0; | |
194 | ||
195 | err: | |
d87342c1 ID |
196 | dma_free_attrs(subdrv->drm_dev->dev, G2D_CMDLIST_POOL_SIZE, |
197 | g2d->cmdlist_pool_virt, | |
198 | g2d->cmdlist_pool, &g2d->cmdlist_dma_attrs); | |
d7f1642c JS |
199 | return ret; |
200 | } | |
201 | ||
202 | static void g2d_fini_cmdlist(struct g2d_data *g2d) | |
203 | { | |
d87342c1 | 204 | struct exynos_drm_subdrv *subdrv = &g2d->subdrv; |
d7f1642c JS |
205 | |
206 | kfree(g2d->cmdlist_node); | |
d87342c1 ID |
207 | dma_free_attrs(subdrv->drm_dev->dev, G2D_CMDLIST_POOL_SIZE, |
208 | g2d->cmdlist_pool_virt, | |
209 | g2d->cmdlist_pool, &g2d->cmdlist_dma_attrs); | |
d7f1642c JS |
210 | } |
211 | ||
212 | static struct g2d_cmdlist_node *g2d_get_cmdlist(struct g2d_data *g2d) | |
213 | { | |
214 | struct device *dev = g2d->dev; | |
215 | struct g2d_cmdlist_node *node; | |
216 | ||
217 | mutex_lock(&g2d->cmdlist_mutex); | |
218 | if (list_empty(&g2d->free_cmdlist)) { | |
219 | dev_err(dev, "there is no free cmdlist\n"); | |
220 | mutex_unlock(&g2d->cmdlist_mutex); | |
221 | return NULL; | |
222 | } | |
223 | ||
224 | node = list_first_entry(&g2d->free_cmdlist, struct g2d_cmdlist_node, | |
225 | list); | |
226 | list_del_init(&node->list); | |
227 | mutex_unlock(&g2d->cmdlist_mutex); | |
228 | ||
229 | return node; | |
230 | } | |
231 | ||
232 | static void g2d_put_cmdlist(struct g2d_data *g2d, struct g2d_cmdlist_node *node) | |
233 | { | |
234 | mutex_lock(&g2d->cmdlist_mutex); | |
235 | list_move_tail(&node->list, &g2d->free_cmdlist); | |
236 | mutex_unlock(&g2d->cmdlist_mutex); | |
237 | } | |
238 | ||
239 | static void g2d_add_cmdlist_to_inuse(struct exynos_drm_g2d_private *g2d_priv, | |
240 | struct g2d_cmdlist_node *node) | |
241 | { | |
242 | struct g2d_cmdlist_node *lnode; | |
243 | ||
244 | if (list_empty(&g2d_priv->inuse_cmdlist)) | |
245 | goto add_to_list; | |
246 | ||
247 | /* this links to base address of new cmdlist */ | |
248 | lnode = list_entry(g2d_priv->inuse_cmdlist.prev, | |
249 | struct g2d_cmdlist_node, list); | |
250 | lnode->cmdlist->data[lnode->cmdlist->last] = node->dma_addr; | |
251 | ||
252 | add_to_list: | |
253 | list_add_tail(&node->list, &g2d_priv->inuse_cmdlist); | |
254 | ||
255 | if (node->event) | |
256 | list_add_tail(&node->event->base.link, &g2d_priv->event_list); | |
257 | } | |
258 | ||
d87342c1 ID |
259 | static int g2d_map_cmdlist_gem(struct g2d_data *g2d, |
260 | struct g2d_cmdlist_node *node, | |
261 | struct drm_device *drm_dev, | |
262 | struct drm_file *file) | |
d7f1642c | 263 | { |
d7f1642c | 264 | struct g2d_cmdlist *cmdlist = node->cmdlist; |
d7f1642c JS |
265 | int offset; |
266 | int i; | |
267 | ||
d87342c1 ID |
268 | for (i = 0; i < node->map_nr; i++) { |
269 | unsigned long handle; | |
270 | dma_addr_t *addr; | |
d7f1642c JS |
271 | |
272 | offset = cmdlist->last - (i * 2 + 1); | |
d87342c1 | 273 | handle = cmdlist->data[offset]; |
d7f1642c | 274 | |
d87342c1 | 275 | addr = exynos_drm_gem_get_dma_addr(drm_dev, handle, file); |
d7f1642c | 276 | if (IS_ERR(addr)) { |
d87342c1 ID |
277 | node->map_nr = i; |
278 | return -EFAULT; | |
d7f1642c JS |
279 | } |
280 | ||
281 | cmdlist->data[offset] = *addr; | |
d87342c1 | 282 | node->handles[i] = handle; |
d7f1642c JS |
283 | } |
284 | ||
285 | return 0; | |
286 | } | |
287 | ||
d87342c1 ID |
288 | static void g2d_unmap_cmdlist_gem(struct g2d_data *g2d, |
289 | struct g2d_cmdlist_node *node, | |
290 | struct drm_file *filp) | |
d7f1642c | 291 | { |
d87342c1 ID |
292 | struct exynos_drm_subdrv *subdrv = &g2d->subdrv; |
293 | int i; | |
d7f1642c | 294 | |
d87342c1 ID |
295 | for (i = 0; i < node->map_nr; i++) { |
296 | unsigned int handle = node->handles[i]; | |
297 | ||
298 | exynos_drm_gem_put_dma_addr(subdrv->drm_dev, handle, filp); | |
d7f1642c | 299 | |
d87342c1 | 300 | node->handles[i] = 0; |
d7f1642c | 301 | } |
d87342c1 ID |
302 | |
303 | node->map_nr = 0; | |
d7f1642c JS |
304 | } |
305 | ||
306 | static void g2d_dma_start(struct g2d_data *g2d, | |
307 | struct g2d_runqueue_node *runqueue_node) | |
308 | { | |
309 | struct g2d_cmdlist_node *node = | |
310 | list_first_entry(&runqueue_node->run_cmdlist, | |
311 | struct g2d_cmdlist_node, list); | |
312 | ||
313 | pm_runtime_get_sync(g2d->dev); | |
314 | clk_enable(g2d->gate_clk); | |
315 | ||
316 | /* interrupt enable */ | |
317 | writel_relaxed(G2D_INTEN_ACF | G2D_INTEN_UCF | G2D_INTEN_GCF, | |
318 | g2d->regs + G2D_INTEN); | |
319 | ||
320 | writel_relaxed(node->dma_addr, g2d->regs + G2D_DMA_SFR_BASE_ADDR); | |
321 | writel_relaxed(G2D_DMA_START, g2d->regs + G2D_DMA_COMMAND); | |
322 | } | |
323 | ||
324 | static struct g2d_runqueue_node *g2d_get_runqueue_node(struct g2d_data *g2d) | |
325 | { | |
326 | struct g2d_runqueue_node *runqueue_node; | |
327 | ||
328 | if (list_empty(&g2d->runqueue)) | |
329 | return NULL; | |
330 | ||
331 | runqueue_node = list_first_entry(&g2d->runqueue, | |
332 | struct g2d_runqueue_node, list); | |
333 | list_del_init(&runqueue_node->list); | |
334 | return runqueue_node; | |
335 | } | |
336 | ||
337 | static void g2d_free_runqueue_node(struct g2d_data *g2d, | |
338 | struct g2d_runqueue_node *runqueue_node) | |
339 | { | |
d87342c1 ID |
340 | struct g2d_cmdlist_node *node; |
341 | ||
d7f1642c JS |
342 | if (!runqueue_node) |
343 | return; | |
344 | ||
345 | mutex_lock(&g2d->cmdlist_mutex); | |
d87342c1 ID |
346 | /* |
347 | * commands in run_cmdlist have been completed so unmap all gem | |
348 | * objects in each command node so that they are unreferenced. | |
349 | */ | |
350 | list_for_each_entry(node, &runqueue_node->run_cmdlist, list) | |
351 | g2d_unmap_cmdlist_gem(g2d, node, runqueue_node->filp); | |
d7f1642c JS |
352 | list_splice_tail_init(&runqueue_node->run_cmdlist, &g2d->free_cmdlist); |
353 | mutex_unlock(&g2d->cmdlist_mutex); | |
354 | ||
355 | kmem_cache_free(g2d->runqueue_slab, runqueue_node); | |
356 | } | |
357 | ||
358 | static void g2d_exec_runqueue(struct g2d_data *g2d) | |
359 | { | |
360 | g2d->runqueue_node = g2d_get_runqueue_node(g2d); | |
361 | if (g2d->runqueue_node) | |
362 | g2d_dma_start(g2d, g2d->runqueue_node); | |
363 | } | |
364 | ||
365 | static void g2d_runqueue_worker(struct work_struct *work) | |
366 | { | |
367 | struct g2d_data *g2d = container_of(work, struct g2d_data, | |
368 | runqueue_work); | |
369 | ||
370 | ||
371 | mutex_lock(&g2d->runqueue_mutex); | |
372 | clk_disable(g2d->gate_clk); | |
373 | pm_runtime_put_sync(g2d->dev); | |
374 | ||
375 | complete(&g2d->runqueue_node->complete); | |
376 | if (g2d->runqueue_node->async) | |
377 | g2d_free_runqueue_node(g2d, g2d->runqueue_node); | |
378 | ||
379 | if (g2d->suspended) | |
380 | g2d->runqueue_node = NULL; | |
381 | else | |
382 | g2d_exec_runqueue(g2d); | |
383 | mutex_unlock(&g2d->runqueue_mutex); | |
384 | } | |
385 | ||
386 | static void g2d_finish_event(struct g2d_data *g2d, u32 cmdlist_no) | |
387 | { | |
388 | struct drm_device *drm_dev = g2d->subdrv.drm_dev; | |
389 | struct g2d_runqueue_node *runqueue_node = g2d->runqueue_node; | |
390 | struct drm_exynos_pending_g2d_event *e; | |
391 | struct timeval now; | |
392 | unsigned long flags; | |
393 | ||
394 | if (list_empty(&runqueue_node->event_list)) | |
395 | return; | |
396 | ||
397 | e = list_first_entry(&runqueue_node->event_list, | |
398 | struct drm_exynos_pending_g2d_event, base.link); | |
399 | ||
400 | do_gettimeofday(&now); | |
401 | e->event.tv_sec = now.tv_sec; | |
402 | e->event.tv_usec = now.tv_usec; | |
403 | e->event.cmdlist_no = cmdlist_no; | |
404 | ||
405 | spin_lock_irqsave(&drm_dev->event_lock, flags); | |
406 | list_move_tail(&e->base.link, &e->base.file_priv->event_list); | |
407 | wake_up_interruptible(&e->base.file_priv->event_wait); | |
408 | spin_unlock_irqrestore(&drm_dev->event_lock, flags); | |
409 | } | |
410 | ||
411 | static irqreturn_t g2d_irq_handler(int irq, void *dev_id) | |
412 | { | |
413 | struct g2d_data *g2d = dev_id; | |
414 | u32 pending; | |
415 | ||
416 | pending = readl_relaxed(g2d->regs + G2D_INTC_PEND); | |
417 | if (pending) | |
418 | writel_relaxed(pending, g2d->regs + G2D_INTC_PEND); | |
419 | ||
420 | if (pending & G2D_INTP_GCMD_FIN) { | |
421 | u32 cmdlist_no = readl_relaxed(g2d->regs + G2D_DMA_STATUS); | |
422 | ||
423 | cmdlist_no = (cmdlist_no & G2D_DMA_LIST_DONE_COUNT) >> | |
424 | G2D_DMA_LIST_DONE_COUNT_OFFSET; | |
425 | ||
426 | g2d_finish_event(g2d, cmdlist_no); | |
427 | ||
428 | writel_relaxed(0, g2d->regs + G2D_DMA_HOLD_CMD); | |
429 | if (!(pending & G2D_INTP_ACMD_FIN)) { | |
430 | writel_relaxed(G2D_DMA_CONTINUE, | |
431 | g2d->regs + G2D_DMA_COMMAND); | |
432 | } | |
433 | } | |
434 | ||
435 | if (pending & G2D_INTP_ACMD_FIN) | |
436 | queue_work(g2d->g2d_workq, &g2d->runqueue_work); | |
437 | ||
438 | return IRQ_HANDLED; | |
439 | } | |
440 | ||
441 | static int g2d_check_reg_offset(struct device *dev, struct g2d_cmdlist *cmdlist, | |
442 | int nr, bool for_addr) | |
443 | { | |
444 | int reg_offset; | |
445 | int index; | |
446 | int i; | |
447 | ||
448 | for (i = 0; i < nr; i++) { | |
449 | index = cmdlist->last - 2 * (i + 1); | |
450 | reg_offset = cmdlist->data[index] & ~0xfffff000; | |
451 | ||
452 | if (reg_offset < G2D_VALID_START || reg_offset > G2D_VALID_END) | |
453 | goto err; | |
454 | if (reg_offset % 4) | |
455 | goto err; | |
456 | ||
457 | switch (reg_offset) { | |
458 | case G2D_SRC_BASE_ADDR: | |
459 | case G2D_SRC_PLANE2_BASE_ADDR: | |
460 | case G2D_DST_BASE_ADDR: | |
461 | case G2D_DST_PLANE2_BASE_ADDR: | |
462 | case G2D_PAT_BASE_ADDR: | |
463 | case G2D_MSK_BASE_ADDR: | |
464 | if (!for_addr) | |
465 | goto err; | |
466 | break; | |
467 | default: | |
468 | if (for_addr) | |
469 | goto err; | |
470 | break; | |
471 | } | |
472 | } | |
473 | ||
474 | return 0; | |
475 | ||
476 | err: | |
477 | dev_err(dev, "Bad register offset: 0x%x\n", cmdlist->data[index]); | |
478 | return -EINVAL; | |
479 | } | |
480 | ||
481 | /* ioctl functions */ | |
482 | int exynos_g2d_get_ver_ioctl(struct drm_device *drm_dev, void *data, | |
483 | struct drm_file *file) | |
484 | { | |
485 | struct drm_exynos_g2d_get_ver *ver = data; | |
486 | ||
487 | ver->major = G2D_HW_MAJOR_VER; | |
488 | ver->minor = G2D_HW_MINOR_VER; | |
489 | ||
490 | return 0; | |
491 | } | |
492 | EXPORT_SYMBOL_GPL(exynos_g2d_get_ver_ioctl); | |
493 | ||
494 | int exynos_g2d_set_cmdlist_ioctl(struct drm_device *drm_dev, void *data, | |
495 | struct drm_file *file) | |
496 | { | |
497 | struct drm_exynos_file_private *file_priv = file->driver_priv; | |
498 | struct exynos_drm_g2d_private *g2d_priv = file_priv->g2d_priv; | |
499 | struct device *dev = g2d_priv->dev; | |
500 | struct g2d_data *g2d; | |
501 | struct drm_exynos_g2d_set_cmdlist *req = data; | |
502 | struct drm_exynos_g2d_cmd *cmd; | |
503 | struct drm_exynos_pending_g2d_event *e; | |
504 | struct g2d_cmdlist_node *node; | |
505 | struct g2d_cmdlist *cmdlist; | |
506 | unsigned long flags; | |
507 | int size; | |
508 | int ret; | |
509 | ||
510 | if (!dev) | |
511 | return -ENODEV; | |
512 | ||
513 | g2d = dev_get_drvdata(dev); | |
514 | if (!g2d) | |
515 | return -EFAULT; | |
516 | ||
517 | node = g2d_get_cmdlist(g2d); | |
518 | if (!node) | |
519 | return -ENOMEM; | |
520 | ||
521 | node->event = NULL; | |
522 | ||
523 | if (req->event_type != G2D_EVENT_NOT) { | |
524 | spin_lock_irqsave(&drm_dev->event_lock, flags); | |
525 | if (file->event_space < sizeof(e->event)) { | |
526 | spin_unlock_irqrestore(&drm_dev->event_lock, flags); | |
527 | ret = -ENOMEM; | |
528 | goto err; | |
529 | } | |
530 | file->event_space -= sizeof(e->event); | |
531 | spin_unlock_irqrestore(&drm_dev->event_lock, flags); | |
532 | ||
533 | e = kzalloc(sizeof(*node->event), GFP_KERNEL); | |
534 | if (!e) { | |
535 | dev_err(dev, "failed to allocate event\n"); | |
536 | ||
537 | spin_lock_irqsave(&drm_dev->event_lock, flags); | |
538 | file->event_space += sizeof(e->event); | |
539 | spin_unlock_irqrestore(&drm_dev->event_lock, flags); | |
540 | ||
541 | ret = -ENOMEM; | |
542 | goto err; | |
543 | } | |
544 | ||
545 | e->event.base.type = DRM_EXYNOS_G2D_EVENT; | |
546 | e->event.base.length = sizeof(e->event); | |
547 | e->event.user_data = req->user_data; | |
548 | e->base.event = &e->event.base; | |
549 | e->base.file_priv = file; | |
550 | e->base.destroy = (void (*) (struct drm_pending_event *)) kfree; | |
551 | ||
552 | node->event = e; | |
553 | } | |
554 | ||
555 | cmdlist = node->cmdlist; | |
556 | ||
557 | cmdlist->last = 0; | |
558 | ||
559 | /* | |
560 | * If don't clear SFR registers, the cmdlist is affected by register | |
561 | * values of previous cmdlist. G2D hw executes SFR clear command and | |
562 | * a next command at the same time then the next command is ignored and | |
563 | * is executed rightly from next next command, so needs a dummy command | |
564 | * to next command of SFR clear command. | |
565 | */ | |
566 | cmdlist->data[cmdlist->last++] = G2D_SOFT_RESET; | |
567 | cmdlist->data[cmdlist->last++] = G2D_SFRCLEAR; | |
568 | cmdlist->data[cmdlist->last++] = G2D_SRC_BASE_ADDR; | |
569 | cmdlist->data[cmdlist->last++] = 0; | |
570 | ||
571 | if (node->event) { | |
572 | cmdlist->data[cmdlist->last++] = G2D_DMA_HOLD_CMD; | |
573 | cmdlist->data[cmdlist->last++] = G2D_LIST_HOLD; | |
574 | } | |
575 | ||
576 | /* Check size of cmdlist: last 2 is about G2D_BITBLT_START */ | |
577 | size = cmdlist->last + req->cmd_nr * 2 + req->cmd_gem_nr * 2 + 2; | |
578 | if (size > G2D_CMDLIST_DATA_NUM) { | |
579 | dev_err(dev, "cmdlist size is too big\n"); | |
580 | ret = -EINVAL; | |
581 | goto err_free_event; | |
582 | } | |
583 | ||
584 | cmd = (struct drm_exynos_g2d_cmd *)(uint32_t)req->cmd; | |
585 | ||
586 | if (copy_from_user(cmdlist->data + cmdlist->last, | |
587 | (void __user *)cmd, | |
588 | sizeof(*cmd) * req->cmd_nr)) { | |
589 | ret = -EFAULT; | |
590 | goto err_free_event; | |
591 | } | |
592 | cmdlist->last += req->cmd_nr * 2; | |
593 | ||
594 | ret = g2d_check_reg_offset(dev, cmdlist, req->cmd_nr, false); | |
595 | if (ret < 0) | |
596 | goto err_free_event; | |
597 | ||
d87342c1 | 598 | node->map_nr = req->cmd_gem_nr; |
d7f1642c JS |
599 | if (req->cmd_gem_nr) { |
600 | struct drm_exynos_g2d_cmd *cmd_gem; | |
601 | ||
602 | cmd_gem = (struct drm_exynos_g2d_cmd *)(uint32_t)req->cmd_gem; | |
603 | ||
604 | if (copy_from_user(cmdlist->data + cmdlist->last, | |
605 | (void __user *)cmd_gem, | |
606 | sizeof(*cmd_gem) * req->cmd_gem_nr)) { | |
607 | ret = -EFAULT; | |
608 | goto err_free_event; | |
609 | } | |
610 | cmdlist->last += req->cmd_gem_nr * 2; | |
611 | ||
612 | ret = g2d_check_reg_offset(dev, cmdlist, req->cmd_gem_nr, true); | |
613 | if (ret < 0) | |
614 | goto err_free_event; | |
615 | ||
d87342c1 | 616 | ret = g2d_map_cmdlist_gem(g2d, node, drm_dev, file); |
d7f1642c JS |
617 | if (ret < 0) |
618 | goto err_unmap; | |
619 | } | |
620 | ||
621 | cmdlist->data[cmdlist->last++] = G2D_BITBLT_START; | |
622 | cmdlist->data[cmdlist->last++] = G2D_START_BITBLT; | |
623 | ||
624 | /* head */ | |
625 | cmdlist->head = cmdlist->last / 2; | |
626 | ||
627 | /* tail */ | |
628 | cmdlist->data[cmdlist->last] = 0; | |
629 | ||
630 | g2d_add_cmdlist_to_inuse(g2d_priv, node); | |
631 | ||
632 | return 0; | |
633 | ||
634 | err_unmap: | |
d87342c1 | 635 | g2d_unmap_cmdlist_gem(g2d, node, file); |
d7f1642c JS |
636 | err_free_event: |
637 | if (node->event) { | |
638 | spin_lock_irqsave(&drm_dev->event_lock, flags); | |
639 | file->event_space += sizeof(e->event); | |
640 | spin_unlock_irqrestore(&drm_dev->event_lock, flags); | |
641 | kfree(node->event); | |
642 | } | |
643 | err: | |
644 | g2d_put_cmdlist(g2d, node); | |
645 | return ret; | |
646 | } | |
647 | EXPORT_SYMBOL_GPL(exynos_g2d_set_cmdlist_ioctl); | |
648 | ||
649 | int exynos_g2d_exec_ioctl(struct drm_device *drm_dev, void *data, | |
650 | struct drm_file *file) | |
651 | { | |
652 | struct drm_exynos_file_private *file_priv = file->driver_priv; | |
653 | struct exynos_drm_g2d_private *g2d_priv = file_priv->g2d_priv; | |
654 | struct device *dev = g2d_priv->dev; | |
655 | struct g2d_data *g2d; | |
656 | struct drm_exynos_g2d_exec *req = data; | |
657 | struct g2d_runqueue_node *runqueue_node; | |
658 | struct list_head *run_cmdlist; | |
659 | struct list_head *event_list; | |
660 | ||
661 | if (!dev) | |
662 | return -ENODEV; | |
663 | ||
664 | g2d = dev_get_drvdata(dev); | |
665 | if (!g2d) | |
666 | return -EFAULT; | |
667 | ||
668 | runqueue_node = kmem_cache_alloc(g2d->runqueue_slab, GFP_KERNEL); | |
669 | if (!runqueue_node) { | |
670 | dev_err(dev, "failed to allocate memory\n"); | |
671 | return -ENOMEM; | |
672 | } | |
673 | run_cmdlist = &runqueue_node->run_cmdlist; | |
674 | event_list = &runqueue_node->event_list; | |
675 | INIT_LIST_HEAD(run_cmdlist); | |
676 | INIT_LIST_HEAD(event_list); | |
677 | init_completion(&runqueue_node->complete); | |
678 | runqueue_node->async = req->async; | |
679 | ||
680 | list_splice_init(&g2d_priv->inuse_cmdlist, run_cmdlist); | |
681 | list_splice_init(&g2d_priv->event_list, event_list); | |
682 | ||
683 | if (list_empty(run_cmdlist)) { | |
684 | dev_err(dev, "there is no inuse cmdlist\n"); | |
685 | kmem_cache_free(g2d->runqueue_slab, runqueue_node); | |
686 | return -EPERM; | |
687 | } | |
688 | ||
689 | mutex_lock(&g2d->runqueue_mutex); | |
6b6bae24 | 690 | runqueue_node->pid = current->pid; |
d87342c1 | 691 | runqueue_node->filp = file; |
d7f1642c JS |
692 | list_add_tail(&runqueue_node->list, &g2d->runqueue); |
693 | if (!g2d->runqueue_node) | |
694 | g2d_exec_runqueue(g2d); | |
695 | mutex_unlock(&g2d->runqueue_mutex); | |
696 | ||
697 | if (runqueue_node->async) | |
698 | goto out; | |
699 | ||
700 | wait_for_completion(&runqueue_node->complete); | |
701 | g2d_free_runqueue_node(g2d, runqueue_node); | |
702 | ||
703 | out: | |
704 | return 0; | |
705 | } | |
706 | EXPORT_SYMBOL_GPL(exynos_g2d_exec_ioctl); | |
707 | ||
d87342c1 ID |
708 | static int g2d_subdrv_probe(struct drm_device *drm_dev, struct device *dev) |
709 | { | |
710 | struct g2d_data *g2d; | |
711 | int ret; | |
712 | ||
713 | g2d = dev_get_drvdata(dev); | |
714 | if (!g2d) | |
715 | return -EFAULT; | |
716 | ||
717 | /* allocate dma-aware cmdlist buffer. */ | |
718 | ret = g2d_init_cmdlist(g2d); | |
719 | if (ret < 0) { | |
720 | dev_err(dev, "cmdlist init failed\n"); | |
721 | return ret; | |
722 | } | |
723 | ||
724 | if (!is_drm_iommu_supported(drm_dev)) | |
725 | return 0; | |
726 | ||
727 | ret = drm_iommu_attach_device(drm_dev, dev); | |
728 | if (ret < 0) { | |
729 | dev_err(dev, "failed to enable iommu.\n"); | |
730 | g2d_fini_cmdlist(g2d); | |
731 | } | |
732 | ||
733 | return ret; | |
734 | ||
735 | } | |
736 | ||
737 | static void g2d_subdrv_remove(struct drm_device *drm_dev, struct device *dev) | |
738 | { | |
739 | if (!is_drm_iommu_supported(drm_dev)) | |
740 | return; | |
741 | ||
742 | drm_iommu_detach_device(drm_dev, dev); | |
743 | } | |
744 | ||
d7f1642c JS |
745 | static int g2d_open(struct drm_device *drm_dev, struct device *dev, |
746 | struct drm_file *file) | |
747 | { | |
748 | struct drm_exynos_file_private *file_priv = file->driver_priv; | |
749 | struct exynos_drm_g2d_private *g2d_priv; | |
750 | ||
751 | g2d_priv = kzalloc(sizeof(*g2d_priv), GFP_KERNEL); | |
752 | if (!g2d_priv) { | |
753 | dev_err(dev, "failed to allocate g2d private data\n"); | |
754 | return -ENOMEM; | |
755 | } | |
756 | ||
757 | g2d_priv->dev = dev; | |
758 | file_priv->g2d_priv = g2d_priv; | |
759 | ||
760 | INIT_LIST_HEAD(&g2d_priv->inuse_cmdlist); | |
761 | INIT_LIST_HEAD(&g2d_priv->event_list); | |
762 | INIT_LIST_HEAD(&g2d_priv->gem_list); | |
763 | ||
764 | return 0; | |
765 | } | |
766 | ||
767 | static void g2d_close(struct drm_device *drm_dev, struct device *dev, | |
768 | struct drm_file *file) | |
769 | { | |
770 | struct drm_exynos_file_private *file_priv = file->driver_priv; | |
771 | struct exynos_drm_g2d_private *g2d_priv = file_priv->g2d_priv; | |
772 | struct g2d_data *g2d; | |
773 | struct g2d_cmdlist_node *node, *n; | |
774 | ||
775 | if (!dev) | |
776 | return; | |
777 | ||
778 | g2d = dev_get_drvdata(dev); | |
779 | if (!g2d) | |
780 | return; | |
781 | ||
782 | mutex_lock(&g2d->cmdlist_mutex); | |
d87342c1 ID |
783 | list_for_each_entry_safe(node, n, &g2d_priv->inuse_cmdlist, list) { |
784 | /* | |
785 | * unmap all gem objects not completed. | |
786 | * | |
787 | * P.S. if current process was terminated forcely then | |
788 | * there may be some commands in inuse_cmdlist so unmap | |
789 | * them. | |
790 | */ | |
791 | g2d_unmap_cmdlist_gem(g2d, node, file); | |
d7f1642c | 792 | list_move_tail(&node->list, &g2d->free_cmdlist); |
d87342c1 | 793 | } |
d7f1642c JS |
794 | mutex_unlock(&g2d->cmdlist_mutex); |
795 | ||
d7f1642c JS |
796 | kfree(file_priv->g2d_priv); |
797 | } | |
798 | ||
799 | static int __devinit g2d_probe(struct platform_device *pdev) | |
800 | { | |
801 | struct device *dev = &pdev->dev; | |
802 | struct resource *res; | |
803 | struct g2d_data *g2d; | |
804 | struct exynos_drm_subdrv *subdrv; | |
805 | int ret; | |
806 | ||
b7675933 | 807 | g2d = devm_kzalloc(&pdev->dev, sizeof(*g2d), GFP_KERNEL); |
d7f1642c JS |
808 | if (!g2d) { |
809 | dev_err(dev, "failed to allocate driver data\n"); | |
810 | return -ENOMEM; | |
811 | } | |
812 | ||
813 | g2d->runqueue_slab = kmem_cache_create("g2d_runqueue_slab", | |
814 | sizeof(struct g2d_runqueue_node), 0, 0, NULL); | |
b7675933 SK |
815 | if (!g2d->runqueue_slab) |
816 | return -ENOMEM; | |
d7f1642c JS |
817 | |
818 | g2d->dev = dev; | |
819 | ||
820 | g2d->g2d_workq = create_singlethread_workqueue("g2d"); | |
821 | if (!g2d->g2d_workq) { | |
822 | dev_err(dev, "failed to create workqueue\n"); | |
823 | ret = -EINVAL; | |
824 | goto err_destroy_slab; | |
825 | } | |
826 | ||
827 | INIT_WORK(&g2d->runqueue_work, g2d_runqueue_worker); | |
828 | INIT_LIST_HEAD(&g2d->free_cmdlist); | |
829 | INIT_LIST_HEAD(&g2d->runqueue); | |
830 | ||
831 | mutex_init(&g2d->cmdlist_mutex); | |
832 | mutex_init(&g2d->runqueue_mutex); | |
833 | ||
d7f1642c JS |
834 | g2d->gate_clk = clk_get(dev, "fimg2d"); |
835 | if (IS_ERR(g2d->gate_clk)) { | |
836 | dev_err(dev, "failed to get gate clock\n"); | |
837 | ret = PTR_ERR(g2d->gate_clk); | |
d87342c1 | 838 | goto err_destroy_workqueue; |
d7f1642c JS |
839 | } |
840 | ||
841 | pm_runtime_enable(dev); | |
842 | ||
843 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
d7f1642c | 844 | |
b7675933 | 845 | g2d->regs = devm_request_and_ioremap(&pdev->dev, res); |
d7f1642c JS |
846 | if (!g2d->regs) { |
847 | dev_err(dev, "failed to remap I/O memory\n"); | |
848 | ret = -ENXIO; | |
b7675933 | 849 | goto err_put_clk; |
d7f1642c JS |
850 | } |
851 | ||
852 | g2d->irq = platform_get_irq(pdev, 0); | |
853 | if (g2d->irq < 0) { | |
854 | dev_err(dev, "failed to get irq\n"); | |
855 | ret = g2d->irq; | |
b7675933 | 856 | goto err_put_clk; |
d7f1642c JS |
857 | } |
858 | ||
b7675933 SK |
859 | ret = devm_request_irq(&pdev->dev, g2d->irq, g2d_irq_handler, 0, |
860 | "drm_g2d", g2d); | |
d7f1642c JS |
861 | if (ret < 0) { |
862 | dev_err(dev, "irq request failed\n"); | |
b7675933 | 863 | goto err_put_clk; |
d7f1642c JS |
864 | } |
865 | ||
866 | platform_set_drvdata(pdev, g2d); | |
867 | ||
868 | subdrv = &g2d->subdrv; | |
869 | subdrv->dev = dev; | |
d87342c1 ID |
870 | subdrv->probe = g2d_subdrv_probe; |
871 | subdrv->remove = g2d_subdrv_remove; | |
d7f1642c JS |
872 | subdrv->open = g2d_open; |
873 | subdrv->close = g2d_close; | |
874 | ||
875 | ret = exynos_drm_subdrv_register(subdrv); | |
876 | if (ret < 0) { | |
877 | dev_err(dev, "failed to register drm g2d device\n"); | |
b7675933 | 878 | goto err_put_clk; |
d7f1642c JS |
879 | } |
880 | ||
881 | dev_info(dev, "The exynos g2d(ver %d.%d) successfully probed\n", | |
882 | G2D_HW_MAJOR_VER, G2D_HW_MINOR_VER); | |
883 | ||
884 | return 0; | |
885 | ||
d7f1642c JS |
886 | err_put_clk: |
887 | pm_runtime_disable(dev); | |
888 | clk_put(g2d->gate_clk); | |
d7f1642c JS |
889 | err_destroy_workqueue: |
890 | destroy_workqueue(g2d->g2d_workq); | |
891 | err_destroy_slab: | |
892 | kmem_cache_destroy(g2d->runqueue_slab); | |
d7f1642c JS |
893 | return ret; |
894 | } | |
895 | ||
896 | static int __devexit g2d_remove(struct platform_device *pdev) | |
897 | { | |
898 | struct g2d_data *g2d = platform_get_drvdata(pdev); | |
899 | ||
900 | cancel_work_sync(&g2d->runqueue_work); | |
901 | exynos_drm_subdrv_unregister(&g2d->subdrv); | |
d7f1642c JS |
902 | |
903 | while (g2d->runqueue_node) { | |
904 | g2d_free_runqueue_node(g2d, g2d->runqueue_node); | |
905 | g2d->runqueue_node = g2d_get_runqueue_node(g2d); | |
906 | } | |
907 | ||
d7f1642c JS |
908 | pm_runtime_disable(&pdev->dev); |
909 | clk_put(g2d->gate_clk); | |
910 | ||
911 | g2d_fini_cmdlist(g2d); | |
912 | destroy_workqueue(g2d->g2d_workq); | |
913 | kmem_cache_destroy(g2d->runqueue_slab); | |
d7f1642c JS |
914 | |
915 | return 0; | |
916 | } | |
917 | ||
918 | #ifdef CONFIG_PM_SLEEP | |
919 | static int g2d_suspend(struct device *dev) | |
920 | { | |
921 | struct g2d_data *g2d = dev_get_drvdata(dev); | |
922 | ||
923 | mutex_lock(&g2d->runqueue_mutex); | |
924 | g2d->suspended = true; | |
925 | mutex_unlock(&g2d->runqueue_mutex); | |
926 | ||
927 | while (g2d->runqueue_node) | |
928 | /* FIXME: good range? */ | |
929 | usleep_range(500, 1000); | |
930 | ||
43829731 | 931 | flush_work(&g2d->runqueue_work); |
d7f1642c JS |
932 | |
933 | return 0; | |
934 | } | |
935 | ||
936 | static int g2d_resume(struct device *dev) | |
937 | { | |
938 | struct g2d_data *g2d = dev_get_drvdata(dev); | |
939 | ||
940 | g2d->suspended = false; | |
941 | g2d_exec_runqueue(g2d); | |
942 | ||
943 | return 0; | |
944 | } | |
945 | #endif | |
946 | ||
9e1355e7 | 947 | static SIMPLE_DEV_PM_OPS(g2d_pm_ops, g2d_suspend, g2d_resume); |
d7f1642c JS |
948 | |
949 | struct platform_driver g2d_driver = { | |
950 | .probe = g2d_probe, | |
951 | .remove = __devexit_p(g2d_remove), | |
952 | .driver = { | |
953 | .name = "s5p-g2d", | |
954 | .owner = THIS_MODULE, | |
955 | .pm = &g2d_pm_ops, | |
956 | }, | |
957 | }; |