Commit | Line | Data |
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9f06080f | 1 | // SPDX-License-Identifier: GPL-2.0-only |
d7f1642c JS |
2 | /* |
3 | * Copyright (C) 2012 Samsung Electronics Co.Ltd | |
4 | * Authors: Joonyoung Shim <jy0922.shim@samsung.com> | |
d7f1642c JS |
5 | */ |
6 | ||
d7f1642c | 7 | #include <linux/clk.h> |
eb4d9796 | 8 | #include <linux/component.h> |
2bda34d7 SR |
9 | #include <linux/delay.h> |
10 | #include <linux/dma-mapping.h> | |
d7f1642c JS |
11 | #include <linux/err.h> |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/io.h> | |
2bda34d7 SR |
14 | #include <linux/kernel.h> |
15 | #include <linux/of.h> | |
d7f1642c JS |
16 | #include <linux/platform_device.h> |
17 | #include <linux/pm_runtime.h> | |
18 | #include <linux/slab.h> | |
2bda34d7 | 19 | #include <linux/uaccess.h> |
d7f1642c JS |
20 | #include <linux/workqueue.h> |
21 | ||
2bda34d7 | 22 | #include <drm/drm_file.h> |
760285e7 | 23 | #include <drm/exynos_drm.h> |
2bda34d7 | 24 | |
d7f1642c | 25 | #include "exynos_drm_drv.h" |
e30655d0 | 26 | #include "exynos_drm_g2d.h" |
d7f1642c JS |
27 | #include "exynos_drm_gem.h" |
28 | ||
29 | #define G2D_HW_MAJOR_VER 4 | |
30 | #define G2D_HW_MINOR_VER 1 | |
31 | ||
32 | /* vaild register range set from user: 0x0104 ~ 0x0880 */ | |
33 | #define G2D_VALID_START 0x0104 | |
34 | #define G2D_VALID_END 0x0880 | |
35 | ||
36 | /* general registers */ | |
37 | #define G2D_SOFT_RESET 0x0000 | |
38 | #define G2D_INTEN 0x0004 | |
39 | #define G2D_INTC_PEND 0x000C | |
40 | #define G2D_DMA_SFR_BASE_ADDR 0x0080 | |
41 | #define G2D_DMA_COMMAND 0x0084 | |
42 | #define G2D_DMA_STATUS 0x008C | |
43 | #define G2D_DMA_HOLD_CMD 0x0090 | |
44 | ||
45 | /* command registers */ | |
46 | #define G2D_BITBLT_START 0x0100 | |
47 | ||
48 | /* registers for base address */ | |
49 | #define G2D_SRC_BASE_ADDR 0x0304 | |
ed4dc271 | 50 | #define G2D_SRC_STRIDE 0x0308 |
2dec17c7 YC |
51 | #define G2D_SRC_COLOR_MODE 0x030C |
52 | #define G2D_SRC_LEFT_TOP 0x0310 | |
53 | #define G2D_SRC_RIGHT_BOTTOM 0x0314 | |
d7f1642c JS |
54 | #define G2D_SRC_PLANE2_BASE_ADDR 0x0318 |
55 | #define G2D_DST_BASE_ADDR 0x0404 | |
ed4dc271 | 56 | #define G2D_DST_STRIDE 0x0408 |
2dec17c7 YC |
57 | #define G2D_DST_COLOR_MODE 0x040C |
58 | #define G2D_DST_LEFT_TOP 0x0410 | |
59 | #define G2D_DST_RIGHT_BOTTOM 0x0414 | |
d7f1642c JS |
60 | #define G2D_DST_PLANE2_BASE_ADDR 0x0418 |
61 | #define G2D_PAT_BASE_ADDR 0x0500 | |
62 | #define G2D_MSK_BASE_ADDR 0x0520 | |
63 | ||
64 | /* G2D_SOFT_RESET */ | |
65 | #define G2D_SFRCLEAR (1 << 1) | |
66 | #define G2D_R (1 << 0) | |
67 | ||
68 | /* G2D_INTEN */ | |
69 | #define G2D_INTEN_ACF (1 << 3) | |
70 | #define G2D_INTEN_UCF (1 << 2) | |
71 | #define G2D_INTEN_GCF (1 << 1) | |
72 | #define G2D_INTEN_SCF (1 << 0) | |
73 | ||
74 | /* G2D_INTC_PEND */ | |
75 | #define G2D_INTP_ACMD_FIN (1 << 3) | |
76 | #define G2D_INTP_UCMD_FIN (1 << 2) | |
77 | #define G2D_INTP_GCMD_FIN (1 << 1) | |
78 | #define G2D_INTP_SCMD_FIN (1 << 0) | |
79 | ||
80 | /* G2D_DMA_COMMAND */ | |
81 | #define G2D_DMA_HALT (1 << 2) | |
82 | #define G2D_DMA_CONTINUE (1 << 1) | |
83 | #define G2D_DMA_START (1 << 0) | |
84 | ||
85 | /* G2D_DMA_STATUS */ | |
86 | #define G2D_DMA_LIST_DONE_COUNT (0xFF << 17) | |
87 | #define G2D_DMA_BITBLT_DONE_COUNT (0xFFFF << 1) | |
88 | #define G2D_DMA_DONE (1 << 0) | |
89 | #define G2D_DMA_LIST_DONE_COUNT_OFFSET 17 | |
90 | ||
91 | /* G2D_DMA_HOLD_CMD */ | |
7ad01814 | 92 | #define G2D_USER_HOLD (1 << 2) |
d7f1642c JS |
93 | #define G2D_LIST_HOLD (1 << 1) |
94 | #define G2D_BITBLT_HOLD (1 << 0) | |
95 | ||
96 | /* G2D_BITBLT_START */ | |
97 | #define G2D_START_CASESEL (1 << 2) | |
98 | #define G2D_START_NHOLT (1 << 1) | |
99 | #define G2D_START_BITBLT (1 << 0) | |
100 | ||
2dec17c7 YC |
101 | /* buffer color format */ |
102 | #define G2D_FMT_XRGB8888 0 | |
103 | #define G2D_FMT_ARGB8888 1 | |
104 | #define G2D_FMT_RGB565 2 | |
105 | #define G2D_FMT_XRGB1555 3 | |
106 | #define G2D_FMT_ARGB1555 4 | |
107 | #define G2D_FMT_XRGB4444 5 | |
108 | #define G2D_FMT_ARGB4444 6 | |
109 | #define G2D_FMT_PACKED_RGB888 7 | |
110 | #define G2D_FMT_A8 11 | |
111 | #define G2D_FMT_L8 12 | |
112 | ||
113 | /* buffer valid length */ | |
114 | #define G2D_LEN_MIN 1 | |
115 | #define G2D_LEN_MAX 8000 | |
116 | ||
d7f1642c JS |
117 | #define G2D_CMDLIST_SIZE (PAGE_SIZE / 4) |
118 | #define G2D_CMDLIST_NUM 64 | |
119 | #define G2D_CMDLIST_POOL_SIZE (G2D_CMDLIST_SIZE * G2D_CMDLIST_NUM) | |
120 | #define G2D_CMDLIST_DATA_NUM (G2D_CMDLIST_SIZE / sizeof(u32) - 2) | |
121 | ||
2a3098ff ID |
122 | /* maximum buffer pool size of userptr is 64MB as default */ |
123 | #define MAX_POOL (64 * 1024 * 1024) | |
124 | ||
125 | enum { | |
126 | BUF_TYPE_GEM = 1, | |
127 | BUF_TYPE_USERPTR, | |
128 | }; | |
129 | ||
9963cb6e YC |
130 | enum g2d_reg_type { |
131 | REG_TYPE_NONE = -1, | |
132 | REG_TYPE_SRC, | |
133 | REG_TYPE_SRC_PLANE2, | |
134 | REG_TYPE_DST, | |
135 | REG_TYPE_DST_PLANE2, | |
136 | REG_TYPE_PAT, | |
137 | REG_TYPE_MSK, | |
138 | MAX_REG_TYPE_NR | |
139 | }; | |
140 | ||
22d6704d TJ |
141 | enum g2d_flag_bits { |
142 | /* | |
143 | * If set, suspends the runqueue worker after the currently | |
144 | * processed node is finished. | |
145 | */ | |
146 | G2D_BIT_SUSPEND_RUNQUEUE, | |
147 | /* | |
148 | * If set, indicates that the engine is currently busy. | |
149 | */ | |
150 | G2D_BIT_ENGINE_BUSY, | |
151 | }; | |
152 | ||
d7f1642c JS |
153 | /* cmdlist data structure */ |
154 | struct g2d_cmdlist { | |
2a3098ff ID |
155 | u32 head; |
156 | unsigned long data[G2D_CMDLIST_DATA_NUM]; | |
157 | u32 last; /* last data offset */ | |
d7f1642c JS |
158 | }; |
159 | ||
2dec17c7 YC |
160 | /* |
161 | * A structure of buffer description | |
162 | * | |
163 | * @format: color format | |
179239a7 | 164 | * @stride: buffer stride/pitch in bytes |
2dec17c7 YC |
165 | * @left_x: the x coordinates of left top corner |
166 | * @top_y: the y coordinates of left top corner | |
167 | * @right_x: the x coordinates of right bottom corner | |
168 | * @bottom_y: the y coordinates of right bottom corner | |
169 | * | |
170 | */ | |
171 | struct g2d_buf_desc { | |
172 | unsigned int format; | |
179239a7 | 173 | unsigned int stride; |
2dec17c7 YC |
174 | unsigned int left_x; |
175 | unsigned int top_y; | |
176 | unsigned int right_x; | |
177 | unsigned int bottom_y; | |
178 | }; | |
179 | ||
9963cb6e YC |
180 | /* |
181 | * A structure of buffer information | |
182 | * | |
183 | * @map_nr: manages the number of mapped buffers | |
184 | * @reg_types: stores regitster type in the order of requested command | |
185 | * @handles: stores buffer handle in its reg_type position | |
186 | * @types: stores buffer type in its reg_type position | |
2dec17c7 | 187 | * @descs: stores buffer description in its reg_type position |
9963cb6e YC |
188 | * |
189 | */ | |
190 | struct g2d_buf_info { | |
191 | unsigned int map_nr; | |
192 | enum g2d_reg_type reg_types[MAX_REG_TYPE_NR]; | |
3aa2a5c1 | 193 | void *obj[MAX_REG_TYPE_NR]; |
9963cb6e | 194 | unsigned int types[MAX_REG_TYPE_NR]; |
2dec17c7 | 195 | struct g2d_buf_desc descs[MAX_REG_TYPE_NR]; |
9963cb6e YC |
196 | }; |
197 | ||
d7f1642c JS |
198 | struct drm_exynos_pending_g2d_event { |
199 | struct drm_pending_event base; | |
200 | struct drm_exynos_g2d_event event; | |
201 | }; | |
202 | ||
2a3098ff ID |
203 | struct g2d_cmdlist_userptr { |
204 | struct list_head list; | |
205 | dma_addr_t dma_addr; | |
206 | unsigned long userptr; | |
207 | unsigned long size; | |
63540f01 | 208 | struct frame_vector *vec; |
2a3098ff | 209 | struct sg_table *sgt; |
2a3098ff ID |
210 | atomic_t refcount; |
211 | bool in_pool; | |
212 | bool out_of_list; | |
213 | }; | |
d7f1642c JS |
214 | struct g2d_cmdlist_node { |
215 | struct list_head list; | |
216 | struct g2d_cmdlist *cmdlist; | |
d7f1642c | 217 | dma_addr_t dma_addr; |
9963cb6e | 218 | struct g2d_buf_info buf_info; |
d7f1642c JS |
219 | |
220 | struct drm_exynos_pending_g2d_event *event; | |
221 | }; | |
222 | ||
223 | struct g2d_runqueue_node { | |
224 | struct list_head list; | |
225 | struct list_head run_cmdlist; | |
226 | struct list_head event_list; | |
d87342c1 | 227 | struct drm_file *filp; |
6b6bae24 | 228 | pid_t pid; |
d7f1642c JS |
229 | struct completion complete; |
230 | int async; | |
231 | }; | |
232 | ||
233 | struct g2d_data { | |
234 | struct device *dev; | |
07dc3678 | 235 | void *dma_priv; |
d7f1642c | 236 | struct clk *gate_clk; |
d7f1642c JS |
237 | void __iomem *regs; |
238 | int irq; | |
239 | struct workqueue_struct *g2d_workq; | |
240 | struct work_struct runqueue_work; | |
eb4d9796 | 241 | struct drm_device *drm_dev; |
22d6704d | 242 | unsigned long flags; |
d7f1642c JS |
243 | |
244 | /* cmdlist */ | |
245 | struct g2d_cmdlist_node *cmdlist_node; | |
246 | struct list_head free_cmdlist; | |
247 | struct mutex cmdlist_mutex; | |
248 | dma_addr_t cmdlist_pool; | |
249 | void *cmdlist_pool_virt; | |
00085f1e | 250 | unsigned long cmdlist_dma_attrs; |
d7f1642c JS |
251 | |
252 | /* runqueue*/ | |
253 | struct g2d_runqueue_node *runqueue_node; | |
254 | struct list_head runqueue; | |
255 | struct mutex runqueue_mutex; | |
256 | struct kmem_cache *runqueue_slab; | |
2a3098ff ID |
257 | |
258 | unsigned long current_pool; | |
259 | unsigned long max_pool; | |
d7f1642c JS |
260 | }; |
261 | ||
134a0fe9 TJ |
262 | static inline void g2d_hw_reset(struct g2d_data *g2d) |
263 | { | |
264 | writel(G2D_R | G2D_SFRCLEAR, g2d->regs + G2D_SOFT_RESET); | |
265 | clear_bit(G2D_BIT_ENGINE_BUSY, &g2d->flags); | |
266 | } | |
267 | ||
d7f1642c JS |
268 | static int g2d_init_cmdlist(struct g2d_data *g2d) |
269 | { | |
270 | struct device *dev = g2d->dev; | |
59d43174 | 271 | struct g2d_cmdlist_node *node; |
d7f1642c JS |
272 | int nr; |
273 | int ret; | |
9963cb6e | 274 | struct g2d_buf_info *buf_info; |
d7f1642c | 275 | |
00085f1e | 276 | g2d->cmdlist_dma_attrs = DMA_ATTR_WRITE_COMBINE; |
d87342c1 | 277 | |
eb4d9796 | 278 | g2d->cmdlist_pool_virt = dma_alloc_attrs(to_dma_dev(g2d->drm_dev), |
d87342c1 ID |
279 | G2D_CMDLIST_POOL_SIZE, |
280 | &g2d->cmdlist_pool, GFP_KERNEL, | |
00085f1e | 281 | g2d->cmdlist_dma_attrs); |
d7f1642c JS |
282 | if (!g2d->cmdlist_pool_virt) { |
283 | dev_err(dev, "failed to allocate dma memory\n"); | |
284 | return -ENOMEM; | |
285 | } | |
286 | ||
fab9f8d0 | 287 | node = kcalloc(G2D_CMDLIST_NUM, sizeof(*node), GFP_KERNEL); |
d7f1642c | 288 | if (!node) { |
d7f1642c JS |
289 | ret = -ENOMEM; |
290 | goto err; | |
291 | } | |
292 | ||
293 | for (nr = 0; nr < G2D_CMDLIST_NUM; nr++) { | |
9963cb6e YC |
294 | unsigned int i; |
295 | ||
d7f1642c JS |
296 | node[nr].cmdlist = |
297 | g2d->cmdlist_pool_virt + nr * G2D_CMDLIST_SIZE; | |
298 | node[nr].dma_addr = | |
299 | g2d->cmdlist_pool + nr * G2D_CMDLIST_SIZE; | |
300 | ||
9963cb6e YC |
301 | buf_info = &node[nr].buf_info; |
302 | for (i = 0; i < MAX_REG_TYPE_NR; i++) | |
303 | buf_info->reg_types[i] = REG_TYPE_NONE; | |
304 | ||
d7f1642c JS |
305 | list_add_tail(&node[nr].list, &g2d->free_cmdlist); |
306 | } | |
307 | ||
308 | return 0; | |
309 | ||
310 | err: | |
eb4d9796 | 311 | dma_free_attrs(to_dma_dev(g2d->drm_dev), G2D_CMDLIST_POOL_SIZE, |
d87342c1 | 312 | g2d->cmdlist_pool_virt, |
00085f1e | 313 | g2d->cmdlist_pool, g2d->cmdlist_dma_attrs); |
d7f1642c JS |
314 | return ret; |
315 | } | |
316 | ||
317 | static void g2d_fini_cmdlist(struct g2d_data *g2d) | |
318 | { | |
d7f1642c | 319 | kfree(g2d->cmdlist_node); |
9ad703e9 ID |
320 | |
321 | if (g2d->cmdlist_pool_virt && g2d->cmdlist_pool) { | |
eb4d9796 | 322 | dma_free_attrs(to_dma_dev(g2d->drm_dev), |
f43c3596 | 323 | G2D_CMDLIST_POOL_SIZE, |
9ad703e9 | 324 | g2d->cmdlist_pool_virt, |
00085f1e | 325 | g2d->cmdlist_pool, g2d->cmdlist_dma_attrs); |
9ad703e9 | 326 | } |
d7f1642c JS |
327 | } |
328 | ||
329 | static struct g2d_cmdlist_node *g2d_get_cmdlist(struct g2d_data *g2d) | |
330 | { | |
331 | struct device *dev = g2d->dev; | |
332 | struct g2d_cmdlist_node *node; | |
333 | ||
334 | mutex_lock(&g2d->cmdlist_mutex); | |
335 | if (list_empty(&g2d->free_cmdlist)) { | |
336 | dev_err(dev, "there is no free cmdlist\n"); | |
337 | mutex_unlock(&g2d->cmdlist_mutex); | |
338 | return NULL; | |
339 | } | |
340 | ||
341 | node = list_first_entry(&g2d->free_cmdlist, struct g2d_cmdlist_node, | |
342 | list); | |
343 | list_del_init(&node->list); | |
344 | mutex_unlock(&g2d->cmdlist_mutex); | |
345 | ||
346 | return node; | |
347 | } | |
348 | ||
349 | static void g2d_put_cmdlist(struct g2d_data *g2d, struct g2d_cmdlist_node *node) | |
350 | { | |
351 | mutex_lock(&g2d->cmdlist_mutex); | |
352 | list_move_tail(&node->list, &g2d->free_cmdlist); | |
353 | mutex_unlock(&g2d->cmdlist_mutex); | |
354 | } | |
355 | ||
eb4d9796 | 356 | static void g2d_add_cmdlist_to_inuse(struct drm_exynos_file_private *file_priv, |
d7f1642c JS |
357 | struct g2d_cmdlist_node *node) |
358 | { | |
359 | struct g2d_cmdlist_node *lnode; | |
360 | ||
eb4d9796 | 361 | if (list_empty(&file_priv->inuse_cmdlist)) |
d7f1642c JS |
362 | goto add_to_list; |
363 | ||
364 | /* this links to base address of new cmdlist */ | |
eb4d9796 | 365 | lnode = list_entry(file_priv->inuse_cmdlist.prev, |
d7f1642c JS |
366 | struct g2d_cmdlist_node, list); |
367 | lnode->cmdlist->data[lnode->cmdlist->last] = node->dma_addr; | |
368 | ||
369 | add_to_list: | |
eb4d9796 | 370 | list_add_tail(&node->list, &file_priv->inuse_cmdlist); |
d7f1642c JS |
371 | |
372 | if (node->event) | |
eb4d9796 | 373 | list_add_tail(&node->event->base.link, &file_priv->event_list); |
d7f1642c JS |
374 | } |
375 | ||
eb4d9796 | 376 | static void g2d_userptr_put_dma_addr(struct g2d_data *g2d, |
3aa2a5c1 | 377 | void *obj, |
2a3098ff ID |
378 | bool force) |
379 | { | |
3aa2a5c1 | 380 | struct g2d_cmdlist_userptr *g2d_userptr = obj; |
63540f01 | 381 | struct page **pages; |
2a3098ff ID |
382 | |
383 | if (!obj) | |
384 | return; | |
385 | ||
386 | if (force) | |
387 | goto out; | |
388 | ||
389 | atomic_dec(&g2d_userptr->refcount); | |
390 | ||
391 | if (atomic_read(&g2d_userptr->refcount) > 0) | |
392 | return; | |
393 | ||
394 | if (g2d_userptr->in_pool) | |
395 | return; | |
396 | ||
397 | out: | |
eb4d9796 | 398 | dma_unmap_sg(to_dma_dev(g2d->drm_dev), g2d_userptr->sgt->sgl, |
6aa5e85d | 399 | g2d_userptr->sgt->nents, DMA_BIDIRECTIONAL); |
2a3098ff | 400 | |
63540f01 JK |
401 | pages = frame_vector_pages(g2d_userptr->vec); |
402 | if (!IS_ERR(pages)) { | |
403 | int i; | |
2a3098ff | 404 | |
63540f01 JK |
405 | for (i = 0; i < frame_vector_count(g2d_userptr->vec); i++) |
406 | set_page_dirty_lock(pages[i]); | |
407 | } | |
408 | put_vaddr_frames(g2d_userptr->vec); | |
409 | frame_vector_destroy(g2d_userptr->vec); | |
c3bddbda | 410 | |
2a3098ff ID |
411 | if (!g2d_userptr->out_of_list) |
412 | list_del_init(&g2d_userptr->list); | |
413 | ||
414 | sg_free_table(g2d_userptr->sgt); | |
415 | kfree(g2d_userptr->sgt); | |
df3d90e5 | 416 | kfree(g2d_userptr); |
2a3098ff ID |
417 | } |
418 | ||
eb4d9796 | 419 | static dma_addr_t *g2d_userptr_get_dma_addr(struct g2d_data *g2d, |
2a3098ff ID |
420 | unsigned long userptr, |
421 | unsigned long size, | |
422 | struct drm_file *filp, | |
3aa2a5c1 | 423 | void **obj) |
2a3098ff ID |
424 | { |
425 | struct drm_exynos_file_private *file_priv = filp->driver_priv; | |
2a3098ff | 426 | struct g2d_cmdlist_userptr *g2d_userptr; |
2a3098ff | 427 | struct sg_table *sgt; |
2a3098ff ID |
428 | unsigned long start, end; |
429 | unsigned int npages, offset; | |
430 | int ret; | |
431 | ||
432 | if (!size) { | |
6f83d208 | 433 | DRM_DEV_ERROR(g2d->dev, "invalid userptr size.\n"); |
2a3098ff ID |
434 | return ERR_PTR(-EINVAL); |
435 | } | |
436 | ||
2a3098ff | 437 | /* check if userptr already exists in userptr_list. */ |
eb4d9796 | 438 | list_for_each_entry(g2d_userptr, &file_priv->userptr_list, list) { |
2a3098ff ID |
439 | if (g2d_userptr->userptr == userptr) { |
440 | /* | |
441 | * also check size because there could be same address | |
442 | * and different size. | |
443 | */ | |
444 | if (g2d_userptr->size == size) { | |
445 | atomic_inc(&g2d_userptr->refcount); | |
3aa2a5c1 | 446 | *obj = g2d_userptr; |
2a3098ff ID |
447 | |
448 | return &g2d_userptr->dma_addr; | |
449 | } | |
450 | ||
451 | /* | |
452 | * at this moment, maybe g2d dma is accessing this | |
453 | * g2d_userptr memory region so just remove this | |
454 | * g2d_userptr object from userptr_list not to be | |
455 | * referred again and also except it the userptr | |
456 | * pool to be released after the dma access completion. | |
457 | */ | |
458 | g2d_userptr->out_of_list = true; | |
459 | g2d_userptr->in_pool = false; | |
460 | list_del_init(&g2d_userptr->list); | |
461 | ||
462 | break; | |
463 | } | |
464 | } | |
465 | ||
466 | g2d_userptr = kzalloc(sizeof(*g2d_userptr), GFP_KERNEL); | |
38bb5253 | 467 | if (!g2d_userptr) |
2a3098ff | 468 | return ERR_PTR(-ENOMEM); |
2a3098ff ID |
469 | |
470 | atomic_set(&g2d_userptr->refcount, 1); | |
63540f01 | 471 | g2d_userptr->size = size; |
2a3098ff ID |
472 | |
473 | start = userptr & PAGE_MASK; | |
474 | offset = userptr & ~PAGE_MASK; | |
475 | end = PAGE_ALIGN(userptr + size); | |
476 | npages = (end - start) >> PAGE_SHIFT; | |
63540f01 JK |
477 | g2d_userptr->vec = frame_vector_create(npages); |
478 | if (!g2d_userptr->vec) { | |
4bb615c5 SWK |
479 | ret = -ENOMEM; |
480 | goto err_free; | |
2a3098ff ID |
481 | } |
482 | ||
7f23b350 LS |
483 | ret = get_vaddr_frames(start, npages, FOLL_FORCE | FOLL_WRITE, |
484 | g2d_userptr->vec); | |
63540f01 | 485 | if (ret != npages) { |
6f83d208 ID |
486 | DRM_DEV_ERROR(g2d->dev, |
487 | "failed to get user pages from userptr.\n"); | |
63540f01 JK |
488 | if (ret < 0) |
489 | goto err_destroy_framevec; | |
2a3098ff | 490 | ret = -EFAULT; |
63540f01 | 491 | goto err_put_framevec; |
2a3098ff | 492 | } |
63540f01 | 493 | if (frame_vector_to_pages(g2d_userptr->vec) < 0) { |
2a3098ff | 494 | ret = -EFAULT; |
63540f01 | 495 | goto err_put_framevec; |
2a3098ff ID |
496 | } |
497 | ||
e44a5c00 | 498 | sgt = kzalloc(sizeof(*sgt), GFP_KERNEL); |
2a3098ff | 499 | if (!sgt) { |
2a3098ff | 500 | ret = -ENOMEM; |
63540f01 | 501 | goto err_put_framevec; |
2a3098ff ID |
502 | } |
503 | ||
63540f01 JK |
504 | ret = sg_alloc_table_from_pages(sgt, |
505 | frame_vector_pages(g2d_userptr->vec), | |
506 | npages, offset, size, GFP_KERNEL); | |
2a3098ff | 507 | if (ret < 0) { |
6f83d208 | 508 | DRM_DEV_ERROR(g2d->dev, "failed to get sgt from pages.\n"); |
2a3098ff ID |
509 | goto err_free_sgt; |
510 | } | |
511 | ||
512 | g2d_userptr->sgt = sgt; | |
513 | ||
eb4d9796 | 514 | if (!dma_map_sg(to_dma_dev(g2d->drm_dev), sgt->sgl, sgt->nents, |
6aa5e85d | 515 | DMA_BIDIRECTIONAL)) { |
6f83d208 | 516 | DRM_DEV_ERROR(g2d->dev, "failed to map sgt with dma region.\n"); |
6aa5e85d | 517 | ret = -ENOMEM; |
067ed331 | 518 | goto err_sg_free_table; |
2a3098ff ID |
519 | } |
520 | ||
521 | g2d_userptr->dma_addr = sgt->sgl[0].dma_address; | |
522 | g2d_userptr->userptr = userptr; | |
523 | ||
eb4d9796 | 524 | list_add_tail(&g2d_userptr->list, &file_priv->userptr_list); |
2a3098ff ID |
525 | |
526 | if (g2d->current_pool + (npages << PAGE_SHIFT) < g2d->max_pool) { | |
527 | g2d->current_pool += npages << PAGE_SHIFT; | |
528 | g2d_userptr->in_pool = true; | |
529 | } | |
530 | ||
3aa2a5c1 | 531 | *obj = g2d_userptr; |
2a3098ff ID |
532 | |
533 | return &g2d_userptr->dma_addr; | |
534 | ||
067ed331 | 535 | err_sg_free_table: |
2a3098ff | 536 | sg_free_table(sgt); |
067ed331 YC |
537 | |
538 | err_free_sgt: | |
2a3098ff | 539 | kfree(sgt); |
2a3098ff | 540 | |
63540f01 JK |
541 | err_put_framevec: |
542 | put_vaddr_frames(g2d_userptr->vec); | |
2a3098ff | 543 | |
63540f01 JK |
544 | err_destroy_framevec: |
545 | frame_vector_destroy(g2d_userptr->vec); | |
4bb615c5 SWK |
546 | |
547 | err_free: | |
2a3098ff | 548 | kfree(g2d_userptr); |
2a3098ff ID |
549 | |
550 | return ERR_PTR(ret); | |
551 | } | |
552 | ||
eb4d9796 | 553 | static void g2d_userptr_free_all(struct g2d_data *g2d, struct drm_file *filp) |
2a3098ff ID |
554 | { |
555 | struct drm_exynos_file_private *file_priv = filp->driver_priv; | |
2a3098ff ID |
556 | struct g2d_cmdlist_userptr *g2d_userptr, *n; |
557 | ||
eb4d9796 | 558 | list_for_each_entry_safe(g2d_userptr, n, &file_priv->userptr_list, list) |
2a3098ff | 559 | if (g2d_userptr->in_pool) |
3aa2a5c1 | 560 | g2d_userptr_put_dma_addr(g2d, g2d_userptr, true); |
2a3098ff ID |
561 | |
562 | g2d->current_pool = 0; | |
563 | } | |
564 | ||
6f83d208 | 565 | static enum g2d_reg_type g2d_get_reg_type(struct g2d_data *g2d, int reg_offset) |
9963cb6e YC |
566 | { |
567 | enum g2d_reg_type reg_type; | |
568 | ||
569 | switch (reg_offset) { | |
570 | case G2D_SRC_BASE_ADDR: | |
ed4dc271 | 571 | case G2D_SRC_STRIDE: |
2dec17c7 YC |
572 | case G2D_SRC_COLOR_MODE: |
573 | case G2D_SRC_LEFT_TOP: | |
574 | case G2D_SRC_RIGHT_BOTTOM: | |
9963cb6e YC |
575 | reg_type = REG_TYPE_SRC; |
576 | break; | |
577 | case G2D_SRC_PLANE2_BASE_ADDR: | |
578 | reg_type = REG_TYPE_SRC_PLANE2; | |
579 | break; | |
580 | case G2D_DST_BASE_ADDR: | |
ed4dc271 | 581 | case G2D_DST_STRIDE: |
2dec17c7 YC |
582 | case G2D_DST_COLOR_MODE: |
583 | case G2D_DST_LEFT_TOP: | |
584 | case G2D_DST_RIGHT_BOTTOM: | |
9963cb6e YC |
585 | reg_type = REG_TYPE_DST; |
586 | break; | |
587 | case G2D_DST_PLANE2_BASE_ADDR: | |
588 | reg_type = REG_TYPE_DST_PLANE2; | |
589 | break; | |
590 | case G2D_PAT_BASE_ADDR: | |
591 | reg_type = REG_TYPE_PAT; | |
592 | break; | |
593 | case G2D_MSK_BASE_ADDR: | |
594 | reg_type = REG_TYPE_MSK; | |
595 | break; | |
596 | default: | |
597 | reg_type = REG_TYPE_NONE; | |
6f83d208 ID |
598 | DRM_DEV_ERROR(g2d->dev, "Unknown register offset![%d]\n", |
599 | reg_offset); | |
9963cb6e | 600 | break; |
5cdbc8d9 | 601 | } |
9963cb6e YC |
602 | |
603 | return reg_type; | |
604 | } | |
605 | ||
2dec17c7 YC |
606 | static unsigned long g2d_get_buf_bpp(unsigned int format) |
607 | { | |
608 | unsigned long bpp; | |
609 | ||
610 | switch (format) { | |
611 | case G2D_FMT_XRGB8888: | |
612 | case G2D_FMT_ARGB8888: | |
613 | bpp = 4; | |
614 | break; | |
615 | case G2D_FMT_RGB565: | |
616 | case G2D_FMT_XRGB1555: | |
617 | case G2D_FMT_ARGB1555: | |
618 | case G2D_FMT_XRGB4444: | |
619 | case G2D_FMT_ARGB4444: | |
620 | bpp = 2; | |
621 | break; | |
622 | case G2D_FMT_PACKED_RGB888: | |
623 | bpp = 3; | |
624 | break; | |
625 | default: | |
626 | bpp = 1; | |
627 | break; | |
628 | } | |
629 | ||
630 | return bpp; | |
631 | } | |
632 | ||
6f83d208 ID |
633 | static bool g2d_check_buf_desc_is_valid(struct g2d_data *g2d, |
634 | struct g2d_buf_desc *buf_desc, | |
635 | enum g2d_reg_type reg_type, | |
636 | unsigned long size) | |
2dec17c7 | 637 | { |
179239a7 TJ |
638 | int width, height; |
639 | unsigned long bpp, last_pos; | |
2dec17c7 YC |
640 | |
641 | /* | |
642 | * check source and destination buffers only. | |
643 | * so the others are always valid. | |
644 | */ | |
645 | if (reg_type != REG_TYPE_SRC && reg_type != REG_TYPE_DST) | |
646 | return true; | |
647 | ||
179239a7 TJ |
648 | /* This check also makes sure that right_x > left_x. */ |
649 | width = (int)buf_desc->right_x - (int)buf_desc->left_x; | |
2dec17c7 | 650 | if (width < G2D_LEN_MIN || width > G2D_LEN_MAX) { |
6f83d208 | 651 | DRM_DEV_ERROR(g2d->dev, "width[%d] is out of range!\n", width); |
2dec17c7 YC |
652 | return false; |
653 | } | |
654 | ||
179239a7 TJ |
655 | /* This check also makes sure that bottom_y > top_y. */ |
656 | height = (int)buf_desc->bottom_y - (int)buf_desc->top_y; | |
2dec17c7 | 657 | if (height < G2D_LEN_MIN || height > G2D_LEN_MAX) { |
6f83d208 ID |
658 | DRM_DEV_ERROR(g2d->dev, |
659 | "height[%d] is out of range!\n", height); | |
2dec17c7 YC |
660 | return false; |
661 | } | |
662 | ||
179239a7 TJ |
663 | bpp = g2d_get_buf_bpp(buf_desc->format); |
664 | ||
665 | /* Compute the position of the last byte that the engine accesses. */ | |
666 | last_pos = ((unsigned long)buf_desc->bottom_y - 1) * | |
667 | (unsigned long)buf_desc->stride + | |
668 | (unsigned long)buf_desc->right_x * bpp - 1; | |
669 | ||
670 | /* | |
671 | * Since right_x > left_x and bottom_y > top_y we already know | |
672 | * that the first_pos < last_pos (first_pos being the position | |
673 | * of the first byte the engine accesses), it just remains to | |
674 | * check if last_pos is smaller then the buffer size. | |
675 | */ | |
676 | ||
677 | if (last_pos >= size) { | |
6f83d208 ID |
678 | DRM_DEV_ERROR(g2d->dev, "last engine access position [%lu] " |
679 | "is out of range [%lu]!\n", last_pos, size); | |
2dec17c7 YC |
680 | return false; |
681 | } | |
682 | ||
683 | return true; | |
684 | } | |
685 | ||
d87342c1 ID |
686 | static int g2d_map_cmdlist_gem(struct g2d_data *g2d, |
687 | struct g2d_cmdlist_node *node, | |
688 | struct drm_device *drm_dev, | |
689 | struct drm_file *file) | |
d7f1642c | 690 | { |
d7f1642c | 691 | struct g2d_cmdlist *cmdlist = node->cmdlist; |
9963cb6e | 692 | struct g2d_buf_info *buf_info = &node->buf_info; |
d7f1642c | 693 | int offset; |
9963cb6e | 694 | int ret; |
d7f1642c JS |
695 | int i; |
696 | ||
9963cb6e | 697 | for (i = 0; i < buf_info->map_nr; i++) { |
2dec17c7 | 698 | struct g2d_buf_desc *buf_desc; |
9963cb6e YC |
699 | enum g2d_reg_type reg_type; |
700 | int reg_pos; | |
d87342c1 ID |
701 | unsigned long handle; |
702 | dma_addr_t *addr; | |
d7f1642c | 703 | |
9963cb6e YC |
704 | reg_pos = cmdlist->last - 2 * (i + 1); |
705 | ||
706 | offset = cmdlist->data[reg_pos]; | |
707 | handle = cmdlist->data[reg_pos + 1]; | |
708 | ||
6f83d208 | 709 | reg_type = g2d_get_reg_type(g2d, offset); |
9963cb6e YC |
710 | if (reg_type == REG_TYPE_NONE) { |
711 | ret = -EFAULT; | |
712 | goto err; | |
713 | } | |
d7f1642c | 714 | |
2dec17c7 YC |
715 | buf_desc = &buf_info->descs[reg_type]; |
716 | ||
9963cb6e | 717 | if (buf_info->types[reg_type] == BUF_TYPE_GEM) { |
3aa2a5c1 | 718 | struct exynos_drm_gem *exynos_gem; |
2dec17c7 | 719 | |
3aa2a5c1 MS |
720 | exynos_gem = exynos_drm_gem_get(file, handle); |
721 | if (!exynos_gem) { | |
2dec17c7 YC |
722 | ret = -EFAULT; |
723 | goto err; | |
724 | } | |
725 | ||
6f83d208 | 726 | if (!g2d_check_buf_desc_is_valid(g2d, buf_desc, |
3aa2a5c1 MS |
727 | reg_type, exynos_gem->size)) { |
728 | exynos_drm_gem_put(exynos_gem); | |
2dec17c7 YC |
729 | ret = -EFAULT; |
730 | goto err; | |
731 | } | |
732 | ||
3aa2a5c1 MS |
733 | addr = &exynos_gem->dma_addr; |
734 | buf_info->obj[reg_type] = exynos_gem; | |
2a3098ff ID |
735 | } else { |
736 | struct drm_exynos_g2d_userptr g2d_userptr; | |
737 | ||
738 | if (copy_from_user(&g2d_userptr, (void __user *)handle, | |
739 | sizeof(struct drm_exynos_g2d_userptr))) { | |
9963cb6e YC |
740 | ret = -EFAULT; |
741 | goto err; | |
2a3098ff ID |
742 | } |
743 | ||
6f83d208 ID |
744 | if (!g2d_check_buf_desc_is_valid(g2d, buf_desc, |
745 | reg_type, | |
746 | g2d_userptr.size)) { | |
2dec17c7 YC |
747 | ret = -EFAULT; |
748 | goto err; | |
749 | } | |
750 | ||
eb4d9796 | 751 | addr = g2d_userptr_get_dma_addr(g2d, |
2a3098ff ID |
752 | g2d_userptr.userptr, |
753 | g2d_userptr.size, | |
754 | file, | |
3aa2a5c1 | 755 | &buf_info->obj[reg_type]); |
2a3098ff | 756 | if (IS_ERR(addr)) { |
9963cb6e YC |
757 | ret = -EFAULT; |
758 | goto err; | |
2a3098ff | 759 | } |
d7f1642c JS |
760 | } |
761 | ||
9963cb6e YC |
762 | cmdlist->data[reg_pos + 1] = *addr; |
763 | buf_info->reg_types[i] = reg_type; | |
d7f1642c JS |
764 | } |
765 | ||
766 | return 0; | |
9963cb6e YC |
767 | |
768 | err: | |
769 | buf_info->map_nr = i; | |
770 | return ret; | |
d7f1642c JS |
771 | } |
772 | ||
d87342c1 ID |
773 | static void g2d_unmap_cmdlist_gem(struct g2d_data *g2d, |
774 | struct g2d_cmdlist_node *node, | |
775 | struct drm_file *filp) | |
d7f1642c | 776 | { |
9963cb6e | 777 | struct g2d_buf_info *buf_info = &node->buf_info; |
d87342c1 | 778 | int i; |
d7f1642c | 779 | |
9963cb6e | 780 | for (i = 0; i < buf_info->map_nr; i++) { |
2dec17c7 | 781 | struct g2d_buf_desc *buf_desc; |
9963cb6e | 782 | enum g2d_reg_type reg_type; |
3aa2a5c1 | 783 | void *obj; |
9963cb6e YC |
784 | |
785 | reg_type = buf_info->reg_types[i]; | |
d87342c1 | 786 | |
2dec17c7 | 787 | buf_desc = &buf_info->descs[reg_type]; |
3aa2a5c1 | 788 | obj = buf_info->obj[reg_type]; |
9963cb6e YC |
789 | |
790 | if (buf_info->types[reg_type] == BUF_TYPE_GEM) | |
3aa2a5c1 | 791 | exynos_drm_gem_put(obj); |
2a3098ff | 792 | else |
3aa2a5c1 | 793 | g2d_userptr_put_dma_addr(g2d, obj, false); |
d7f1642c | 794 | |
9963cb6e | 795 | buf_info->reg_types[i] = REG_TYPE_NONE; |
3aa2a5c1 | 796 | buf_info->obj[reg_type] = NULL; |
9963cb6e | 797 | buf_info->types[reg_type] = 0; |
2dec17c7 | 798 | memset(buf_desc, 0x00, sizeof(*buf_desc)); |
d7f1642c | 799 | } |
d87342c1 | 800 | |
9963cb6e | 801 | buf_info->map_nr = 0; |
d7f1642c JS |
802 | } |
803 | ||
804 | static void g2d_dma_start(struct g2d_data *g2d, | |
805 | struct g2d_runqueue_node *runqueue_node) | |
806 | { | |
807 | struct g2d_cmdlist_node *node = | |
808 | list_first_entry(&runqueue_node->run_cmdlist, | |
809 | struct g2d_cmdlist_node, list); | |
d7f1642c | 810 | |
22d6704d | 811 | set_bit(G2D_BIT_ENGINE_BUSY, &g2d->flags); |
d7f1642c JS |
812 | writel_relaxed(node->dma_addr, g2d->regs + G2D_DMA_SFR_BASE_ADDR); |
813 | writel_relaxed(G2D_DMA_START, g2d->regs + G2D_DMA_COMMAND); | |
814 | } | |
815 | ||
816 | static struct g2d_runqueue_node *g2d_get_runqueue_node(struct g2d_data *g2d) | |
817 | { | |
818 | struct g2d_runqueue_node *runqueue_node; | |
819 | ||
820 | if (list_empty(&g2d->runqueue)) | |
821 | return NULL; | |
822 | ||
823 | runqueue_node = list_first_entry(&g2d->runqueue, | |
824 | struct g2d_runqueue_node, list); | |
825 | list_del_init(&runqueue_node->list); | |
826 | return runqueue_node; | |
827 | } | |
828 | ||
829 | static void g2d_free_runqueue_node(struct g2d_data *g2d, | |
830 | struct g2d_runqueue_node *runqueue_node) | |
831 | { | |
d87342c1 ID |
832 | struct g2d_cmdlist_node *node; |
833 | ||
d7f1642c | 834 | mutex_lock(&g2d->cmdlist_mutex); |
d87342c1 ID |
835 | /* |
836 | * commands in run_cmdlist have been completed so unmap all gem | |
837 | * objects in each command node so that they are unreferenced. | |
838 | */ | |
839 | list_for_each_entry(node, &runqueue_node->run_cmdlist, list) | |
840 | g2d_unmap_cmdlist_gem(g2d, node, runqueue_node->filp); | |
d7f1642c JS |
841 | list_splice_tail_init(&runqueue_node->run_cmdlist, &g2d->free_cmdlist); |
842 | mutex_unlock(&g2d->cmdlist_mutex); | |
843 | ||
844 | kmem_cache_free(g2d->runqueue_slab, runqueue_node); | |
845 | } | |
846 | ||
53327374 TJ |
847 | /** |
848 | * g2d_remove_runqueue_nodes - remove items from the list of runqueue nodes | |
849 | * @g2d: G2D state object | |
850 | * @file: if not zero, only remove items with this DRM file | |
851 | * | |
852 | * Has to be called under runqueue lock. | |
853 | */ | |
f9af3f84 | 854 | static void g2d_remove_runqueue_nodes(struct g2d_data *g2d, struct drm_file *file) |
d7f1642c | 855 | { |
53327374 TJ |
856 | struct g2d_runqueue_node *node, *n; |
857 | ||
858 | if (list_empty(&g2d->runqueue)) | |
859 | return; | |
860 | ||
861 | list_for_each_entry_safe(node, n, &g2d->runqueue, list) { | |
862 | if (file && node->filp != file) | |
863 | continue; | |
864 | ||
865 | list_del_init(&node->list); | |
866 | g2d_free_runqueue_node(g2d, node); | |
867 | } | |
d7f1642c JS |
868 | } |
869 | ||
870 | static void g2d_runqueue_worker(struct work_struct *work) | |
871 | { | |
872 | struct g2d_data *g2d = container_of(work, struct g2d_data, | |
873 | runqueue_work); | |
22d6704d TJ |
874 | struct g2d_runqueue_node *runqueue_node; |
875 | ||
876 | /* | |
877 | * The engine is busy and the completion of the current node is going | |
878 | * to poke the runqueue worker, so nothing to do here. | |
879 | */ | |
880 | if (test_bit(G2D_BIT_ENGINE_BUSY, &g2d->flags)) | |
881 | return; | |
d7f1642c | 882 | |
d7f1642c | 883 | mutex_lock(&g2d->runqueue_mutex); |
d7f1642c | 884 | |
22d6704d TJ |
885 | runqueue_node = g2d->runqueue_node; |
886 | g2d->runqueue_node = NULL; | |
887 | ||
888 | if (runqueue_node) { | |
7c3fc2b5 TJ |
889 | pm_runtime_mark_last_busy(g2d->dev); |
890 | pm_runtime_put_autosuspend(g2d->dev); | |
22d6704d TJ |
891 | |
892 | complete(&runqueue_node->complete); | |
893 | if (runqueue_node->async) | |
894 | g2d_free_runqueue_node(g2d, runqueue_node); | |
895 | } | |
896 | ||
897 | if (!test_bit(G2D_BIT_SUSPEND_RUNQUEUE, &g2d->flags)) { | |
898 | g2d->runqueue_node = g2d_get_runqueue_node(g2d); | |
899 | ||
900 | if (g2d->runqueue_node) { | |
901 | pm_runtime_get_sync(g2d->dev); | |
902 | g2d_dma_start(g2d, g2d->runqueue_node); | |
903 | } | |
904 | } | |
d7f1642c | 905 | |
d7f1642c JS |
906 | mutex_unlock(&g2d->runqueue_mutex); |
907 | } | |
908 | ||
909 | static void g2d_finish_event(struct g2d_data *g2d, u32 cmdlist_no) | |
910 | { | |
eb4d9796 | 911 | struct drm_device *drm_dev = g2d->drm_dev; |
d7f1642c JS |
912 | struct g2d_runqueue_node *runqueue_node = g2d->runqueue_node; |
913 | struct drm_exynos_pending_g2d_event *e; | |
a588a8bb | 914 | struct timespec64 now; |
d7f1642c JS |
915 | |
916 | if (list_empty(&runqueue_node->event_list)) | |
917 | return; | |
918 | ||
919 | e = list_first_entry(&runqueue_node->event_list, | |
920 | struct drm_exynos_pending_g2d_event, base.link); | |
921 | ||
a588a8bb | 922 | ktime_get_ts64(&now); |
d7f1642c | 923 | e->event.tv_sec = now.tv_sec; |
a588a8bb | 924 | e->event.tv_usec = now.tv_nsec / NSEC_PER_USEC; |
d7f1642c JS |
925 | e->event.cmdlist_no = cmdlist_no; |
926 | ||
fb740cf2 | 927 | drm_send_event(drm_dev, &e->base); |
d7f1642c JS |
928 | } |
929 | ||
930 | static irqreturn_t g2d_irq_handler(int irq, void *dev_id) | |
931 | { | |
932 | struct g2d_data *g2d = dev_id; | |
933 | u32 pending; | |
934 | ||
935 | pending = readl_relaxed(g2d->regs + G2D_INTC_PEND); | |
936 | if (pending) | |
937 | writel_relaxed(pending, g2d->regs + G2D_INTC_PEND); | |
938 | ||
939 | if (pending & G2D_INTP_GCMD_FIN) { | |
940 | u32 cmdlist_no = readl_relaxed(g2d->regs + G2D_DMA_STATUS); | |
941 | ||
942 | cmdlist_no = (cmdlist_no & G2D_DMA_LIST_DONE_COUNT) >> | |
943 | G2D_DMA_LIST_DONE_COUNT_OFFSET; | |
944 | ||
945 | g2d_finish_event(g2d, cmdlist_no); | |
946 | ||
947 | writel_relaxed(0, g2d->regs + G2D_DMA_HOLD_CMD); | |
948 | if (!(pending & G2D_INTP_ACMD_FIN)) { | |
949 | writel_relaxed(G2D_DMA_CONTINUE, | |
950 | g2d->regs + G2D_DMA_COMMAND); | |
951 | } | |
952 | } | |
953 | ||
22d6704d TJ |
954 | if (pending & G2D_INTP_ACMD_FIN) { |
955 | clear_bit(G2D_BIT_ENGINE_BUSY, &g2d->flags); | |
d7f1642c | 956 | queue_work(g2d->g2d_workq, &g2d->runqueue_work); |
22d6704d | 957 | } |
d7f1642c JS |
958 | |
959 | return IRQ_HANDLED; | |
960 | } | |
961 | ||
134a0fe9 TJ |
962 | /** |
963 | * g2d_wait_finish - wait for the G2D engine to finish the current runqueue node | |
964 | * @g2d: G2D state object | |
965 | * @file: if not zero, only wait if the current runqueue node belongs | |
966 | * to the DRM file | |
967 | * | |
968 | * Should the engine not become idle after a 100ms timeout, a hardware | |
969 | * reset is issued. | |
970 | */ | |
971 | static void g2d_wait_finish(struct g2d_data *g2d, struct drm_file *file) | |
972 | { | |
973 | struct device *dev = g2d->dev; | |
974 | ||
975 | struct g2d_runqueue_node *runqueue_node = NULL; | |
976 | unsigned int tries = 10; | |
977 | ||
978 | mutex_lock(&g2d->runqueue_mutex); | |
979 | ||
980 | /* If no node is currently processed, we have nothing to do. */ | |
981 | if (!g2d->runqueue_node) | |
982 | goto out; | |
983 | ||
984 | runqueue_node = g2d->runqueue_node; | |
985 | ||
986 | /* Check if the currently processed item belongs to us. */ | |
987 | if (file && runqueue_node->filp != file) | |
988 | goto out; | |
989 | ||
990 | mutex_unlock(&g2d->runqueue_mutex); | |
991 | ||
992 | /* Wait for the G2D engine to finish. */ | |
993 | while (tries-- && (g2d->runqueue_node == runqueue_node)) | |
994 | mdelay(10); | |
995 | ||
996 | mutex_lock(&g2d->runqueue_mutex); | |
997 | ||
998 | if (g2d->runqueue_node != runqueue_node) | |
999 | goto out; | |
1000 | ||
1001 | dev_err(dev, "wait timed out, resetting engine...\n"); | |
1002 | g2d_hw_reset(g2d); | |
1003 | ||
1004 | /* | |
1005 | * After the hardware reset of the engine we are going to loose | |
1006 | * the IRQ which triggers the PM runtime put(). | |
1007 | * So do this manually here. | |
1008 | */ | |
7c3fc2b5 TJ |
1009 | pm_runtime_mark_last_busy(dev); |
1010 | pm_runtime_put_autosuspend(dev); | |
134a0fe9 TJ |
1011 | |
1012 | complete(&runqueue_node->complete); | |
1013 | if (runqueue_node->async) | |
1014 | g2d_free_runqueue_node(g2d, runqueue_node); | |
1015 | ||
1016 | out: | |
1017 | mutex_unlock(&g2d->runqueue_mutex); | |
1018 | } | |
1019 | ||
eb4d9796 | 1020 | static int g2d_check_reg_offset(struct g2d_data *g2d, |
2a3098ff | 1021 | struct g2d_cmdlist_node *node, |
d7f1642c JS |
1022 | int nr, bool for_addr) |
1023 | { | |
2a3098ff | 1024 | struct g2d_cmdlist *cmdlist = node->cmdlist; |
d7f1642c JS |
1025 | int reg_offset; |
1026 | int index; | |
1027 | int i; | |
1028 | ||
1029 | for (i = 0; i < nr; i++) { | |
9963cb6e | 1030 | struct g2d_buf_info *buf_info = &node->buf_info; |
2dec17c7 | 1031 | struct g2d_buf_desc *buf_desc; |
9963cb6e | 1032 | enum g2d_reg_type reg_type; |
2dec17c7 | 1033 | unsigned long value; |
2a3098ff | 1034 | |
9963cb6e | 1035 | index = cmdlist->last - 2 * (i + 1); |
2a3098ff | 1036 | |
d7f1642c | 1037 | reg_offset = cmdlist->data[index] & ~0xfffff000; |
d7f1642c JS |
1038 | if (reg_offset < G2D_VALID_START || reg_offset > G2D_VALID_END) |
1039 | goto err; | |
1040 | if (reg_offset % 4) | |
1041 | goto err; | |
1042 | ||
1043 | switch (reg_offset) { | |
1044 | case G2D_SRC_BASE_ADDR: | |
1045 | case G2D_SRC_PLANE2_BASE_ADDR: | |
1046 | case G2D_DST_BASE_ADDR: | |
1047 | case G2D_DST_PLANE2_BASE_ADDR: | |
1048 | case G2D_PAT_BASE_ADDR: | |
1049 | case G2D_MSK_BASE_ADDR: | |
1050 | if (!for_addr) | |
1051 | goto err; | |
2a3098ff | 1052 | |
6f83d208 | 1053 | reg_type = g2d_get_reg_type(g2d, reg_offset); |
9963cb6e YC |
1054 | |
1055 | /* check userptr buffer type. */ | |
1056 | if ((cmdlist->data[index] & ~0x7fffffff) >> 31) { | |
1057 | buf_info->types[reg_type] = BUF_TYPE_USERPTR; | |
1058 | cmdlist->data[index] &= ~G2D_BUF_USERPTR; | |
1059 | } else | |
1060 | buf_info->types[reg_type] = BUF_TYPE_GEM; | |
d7f1642c | 1061 | break; |
ed4dc271 TJ |
1062 | case G2D_SRC_STRIDE: |
1063 | case G2D_DST_STRIDE: | |
179239a7 TJ |
1064 | if (for_addr) |
1065 | goto err; | |
1066 | ||
6f83d208 | 1067 | reg_type = g2d_get_reg_type(g2d, reg_offset); |
179239a7 TJ |
1068 | |
1069 | buf_desc = &buf_info->descs[reg_type]; | |
1070 | buf_desc->stride = cmdlist->data[index + 1]; | |
1071 | break; | |
2dec17c7 YC |
1072 | case G2D_SRC_COLOR_MODE: |
1073 | case G2D_DST_COLOR_MODE: | |
1074 | if (for_addr) | |
1075 | goto err; | |
1076 | ||
6f83d208 | 1077 | reg_type = g2d_get_reg_type(g2d, reg_offset); |
2dec17c7 YC |
1078 | |
1079 | buf_desc = &buf_info->descs[reg_type]; | |
1080 | value = cmdlist->data[index + 1]; | |
1081 | ||
1082 | buf_desc->format = value & 0xf; | |
1083 | break; | |
1084 | case G2D_SRC_LEFT_TOP: | |
1085 | case G2D_DST_LEFT_TOP: | |
1086 | if (for_addr) | |
1087 | goto err; | |
1088 | ||
6f83d208 | 1089 | reg_type = g2d_get_reg_type(g2d, reg_offset); |
2dec17c7 YC |
1090 | |
1091 | buf_desc = &buf_info->descs[reg_type]; | |
1092 | value = cmdlist->data[index + 1]; | |
1093 | ||
1094 | buf_desc->left_x = value & 0x1fff; | |
1095 | buf_desc->top_y = (value & 0x1fff0000) >> 16; | |
1096 | break; | |
1097 | case G2D_SRC_RIGHT_BOTTOM: | |
1098 | case G2D_DST_RIGHT_BOTTOM: | |
1099 | if (for_addr) | |
1100 | goto err; | |
1101 | ||
6f83d208 | 1102 | reg_type = g2d_get_reg_type(g2d, reg_offset); |
2dec17c7 YC |
1103 | |
1104 | buf_desc = &buf_info->descs[reg_type]; | |
1105 | value = cmdlist->data[index + 1]; | |
1106 | ||
1107 | buf_desc->right_x = value & 0x1fff; | |
1108 | buf_desc->bottom_y = (value & 0x1fff0000) >> 16; | |
1109 | break; | |
d7f1642c JS |
1110 | default: |
1111 | if (for_addr) | |
1112 | goto err; | |
1113 | break; | |
1114 | } | |
1115 | } | |
1116 | ||
1117 | return 0; | |
1118 | ||
1119 | err: | |
eb4d9796 | 1120 | dev_err(g2d->dev, "Bad register offset: 0x%lx\n", cmdlist->data[index]); |
d7f1642c JS |
1121 | return -EINVAL; |
1122 | } | |
1123 | ||
1124 | /* ioctl functions */ | |
1125 | int exynos_g2d_get_ver_ioctl(struct drm_device *drm_dev, void *data, | |
1126 | struct drm_file *file) | |
1127 | { | |
1128 | struct drm_exynos_g2d_get_ver *ver = data; | |
1129 | ||
1130 | ver->major = G2D_HW_MAJOR_VER; | |
1131 | ver->minor = G2D_HW_MINOR_VER; | |
1132 | ||
1133 | return 0; | |
1134 | } | |
d7f1642c JS |
1135 | |
1136 | int exynos_g2d_set_cmdlist_ioctl(struct drm_device *drm_dev, void *data, | |
1137 | struct drm_file *file) | |
1138 | { | |
1139 | struct drm_exynos_file_private *file_priv = file->driver_priv; | |
eb4d9796 MS |
1140 | struct exynos_drm_private *priv = drm_dev->dev_private; |
1141 | struct g2d_data *g2d = dev_get_drvdata(priv->g2d_dev); | |
d7f1642c JS |
1142 | struct drm_exynos_g2d_set_cmdlist *req = data; |
1143 | struct drm_exynos_g2d_cmd *cmd; | |
1144 | struct drm_exynos_pending_g2d_event *e; | |
1145 | struct g2d_cmdlist_node *node; | |
1146 | struct g2d_cmdlist *cmdlist; | |
d7f1642c JS |
1147 | int size; |
1148 | int ret; | |
1149 | ||
d7f1642c JS |
1150 | node = g2d_get_cmdlist(g2d); |
1151 | if (!node) | |
1152 | return -ENOMEM; | |
1153 | ||
e41456bf JS |
1154 | /* |
1155 | * To avoid an integer overflow for the later size computations, we | |
1156 | * enforce a maximum number of submitted commands here. This limit is | |
1157 | * sufficient for all conceivable usage cases of the G2D. | |
1158 | */ | |
1159 | if (req->cmd_nr > G2D_CMDLIST_DATA_NUM || | |
1160 | req->cmd_buf_nr > G2D_CMDLIST_DATA_NUM) { | |
eb4d9796 | 1161 | dev_err(g2d->dev, "number of submitted G2D commands exceeds limit\n"); |
e41456bf JS |
1162 | return -EINVAL; |
1163 | } | |
1164 | ||
d7f1642c JS |
1165 | node->event = NULL; |
1166 | ||
1167 | if (req->event_type != G2D_EVENT_NOT) { | |
d7f1642c JS |
1168 | e = kzalloc(sizeof(*node->event), GFP_KERNEL); |
1169 | if (!e) { | |
d7f1642c JS |
1170 | ret = -ENOMEM; |
1171 | goto err; | |
1172 | } | |
1173 | ||
1174 | e->event.base.type = DRM_EXYNOS_G2D_EVENT; | |
1175 | e->event.base.length = sizeof(e->event); | |
1176 | e->event.user_data = req->user_data; | |
7142a348 DV |
1177 | |
1178 | ret = drm_event_reserve_init(drm_dev, file, &e->base, &e->event.base); | |
1179 | if (ret) { | |
1180 | kfree(e); | |
1181 | goto err; | |
1182 | } | |
d7f1642c JS |
1183 | |
1184 | node->event = e; | |
1185 | } | |
1186 | ||
1187 | cmdlist = node->cmdlist; | |
1188 | ||
1189 | cmdlist->last = 0; | |
1190 | ||
1191 | /* | |
1192 | * If don't clear SFR registers, the cmdlist is affected by register | |
1193 | * values of previous cmdlist. G2D hw executes SFR clear command and | |
1194 | * a next command at the same time then the next command is ignored and | |
1195 | * is executed rightly from next next command, so needs a dummy command | |
1196 | * to next command of SFR clear command. | |
1197 | */ | |
1198 | cmdlist->data[cmdlist->last++] = G2D_SOFT_RESET; | |
1199 | cmdlist->data[cmdlist->last++] = G2D_SFRCLEAR; | |
1200 | cmdlist->data[cmdlist->last++] = G2D_SRC_BASE_ADDR; | |
1201 | cmdlist->data[cmdlist->last++] = 0; | |
1202 | ||
7ad01814 YC |
1203 | /* |
1204 | * 'LIST_HOLD' command should be set to the DMA_HOLD_CMD_REG | |
1205 | * and GCF bit should be set to INTEN register if user wants | |
1206 | * G2D interrupt event once current command list execution is | |
1207 | * finished. | |
1208 | * Otherwise only ACF bit should be set to INTEN register so | |
c6b78bc8 | 1209 | * that one interrupt is occurred after all command lists |
7ad01814 YC |
1210 | * have been completed. |
1211 | */ | |
d7f1642c | 1212 | if (node->event) { |
7ad01814 YC |
1213 | cmdlist->data[cmdlist->last++] = G2D_INTEN; |
1214 | cmdlist->data[cmdlist->last++] = G2D_INTEN_ACF | G2D_INTEN_GCF; | |
d7f1642c JS |
1215 | cmdlist->data[cmdlist->last++] = G2D_DMA_HOLD_CMD; |
1216 | cmdlist->data[cmdlist->last++] = G2D_LIST_HOLD; | |
7ad01814 YC |
1217 | } else { |
1218 | cmdlist->data[cmdlist->last++] = G2D_INTEN; | |
1219 | cmdlist->data[cmdlist->last++] = G2D_INTEN_ACF; | |
d7f1642c JS |
1220 | } |
1221 | ||
e41456bf JS |
1222 | /* |
1223 | * Check the size of cmdlist. The 2 that is added last comes from | |
1224 | * the implicit G2D_BITBLT_START that is appended once we have | |
1225 | * checked all the submitted commands. | |
1226 | */ | |
2a3098ff | 1227 | size = cmdlist->last + req->cmd_nr * 2 + req->cmd_buf_nr * 2 + 2; |
d7f1642c | 1228 | if (size > G2D_CMDLIST_DATA_NUM) { |
eb4d9796 | 1229 | dev_err(g2d->dev, "cmdlist size is too big\n"); |
d7f1642c JS |
1230 | ret = -EINVAL; |
1231 | goto err_free_event; | |
1232 | } | |
1233 | ||
c5f2f0c4 | 1234 | cmd = (struct drm_exynos_g2d_cmd *)(unsigned long)req->cmd; |
d7f1642c JS |
1235 | |
1236 | if (copy_from_user(cmdlist->data + cmdlist->last, | |
1237 | (void __user *)cmd, | |
1238 | sizeof(*cmd) * req->cmd_nr)) { | |
1239 | ret = -EFAULT; | |
1240 | goto err_free_event; | |
1241 | } | |
1242 | cmdlist->last += req->cmd_nr * 2; | |
1243 | ||
eb4d9796 | 1244 | ret = g2d_check_reg_offset(g2d, node, req->cmd_nr, false); |
d7f1642c JS |
1245 | if (ret < 0) |
1246 | goto err_free_event; | |
1247 | ||
9963cb6e | 1248 | node->buf_info.map_nr = req->cmd_buf_nr; |
2a3098ff ID |
1249 | if (req->cmd_buf_nr) { |
1250 | struct drm_exynos_g2d_cmd *cmd_buf; | |
d7f1642c | 1251 | |
c5f2f0c4 MS |
1252 | cmd_buf = (struct drm_exynos_g2d_cmd *) |
1253 | (unsigned long)req->cmd_buf; | |
d7f1642c JS |
1254 | |
1255 | if (copy_from_user(cmdlist->data + cmdlist->last, | |
2a3098ff ID |
1256 | (void __user *)cmd_buf, |
1257 | sizeof(*cmd_buf) * req->cmd_buf_nr)) { | |
d7f1642c JS |
1258 | ret = -EFAULT; |
1259 | goto err_free_event; | |
1260 | } | |
2a3098ff | 1261 | cmdlist->last += req->cmd_buf_nr * 2; |
d7f1642c | 1262 | |
eb4d9796 | 1263 | ret = g2d_check_reg_offset(g2d, node, req->cmd_buf_nr, true); |
d7f1642c JS |
1264 | if (ret < 0) |
1265 | goto err_free_event; | |
1266 | ||
d87342c1 | 1267 | ret = g2d_map_cmdlist_gem(g2d, node, drm_dev, file); |
d7f1642c JS |
1268 | if (ret < 0) |
1269 | goto err_unmap; | |
1270 | } | |
1271 | ||
1272 | cmdlist->data[cmdlist->last++] = G2D_BITBLT_START; | |
1273 | cmdlist->data[cmdlist->last++] = G2D_START_BITBLT; | |
1274 | ||
1275 | /* head */ | |
1276 | cmdlist->head = cmdlist->last / 2; | |
1277 | ||
1278 | /* tail */ | |
1279 | cmdlist->data[cmdlist->last] = 0; | |
1280 | ||
eb4d9796 | 1281 | g2d_add_cmdlist_to_inuse(file_priv, node); |
d7f1642c JS |
1282 | |
1283 | return 0; | |
1284 | ||
1285 | err_unmap: | |
d87342c1 | 1286 | g2d_unmap_cmdlist_gem(g2d, node, file); |
d7f1642c | 1287 | err_free_event: |
7142a348 DV |
1288 | if (node->event) |
1289 | drm_event_cancel_free(drm_dev, &node->event->base); | |
d7f1642c JS |
1290 | err: |
1291 | g2d_put_cmdlist(g2d, node); | |
1292 | return ret; | |
1293 | } | |
d7f1642c JS |
1294 | |
1295 | int exynos_g2d_exec_ioctl(struct drm_device *drm_dev, void *data, | |
1296 | struct drm_file *file) | |
1297 | { | |
1298 | struct drm_exynos_file_private *file_priv = file->driver_priv; | |
eb4d9796 MS |
1299 | struct exynos_drm_private *priv = drm_dev->dev_private; |
1300 | struct g2d_data *g2d = dev_get_drvdata(priv->g2d_dev); | |
d7f1642c JS |
1301 | struct drm_exynos_g2d_exec *req = data; |
1302 | struct g2d_runqueue_node *runqueue_node; | |
1303 | struct list_head *run_cmdlist; | |
1304 | struct list_head *event_list; | |
1305 | ||
d7f1642c | 1306 | runqueue_node = kmem_cache_alloc(g2d->runqueue_slab, GFP_KERNEL); |
6f0a6029 | 1307 | if (!runqueue_node) |
d7f1642c | 1308 | return -ENOMEM; |
6f0a6029 | 1309 | |
d7f1642c JS |
1310 | run_cmdlist = &runqueue_node->run_cmdlist; |
1311 | event_list = &runqueue_node->event_list; | |
1312 | INIT_LIST_HEAD(run_cmdlist); | |
1313 | INIT_LIST_HEAD(event_list); | |
1314 | init_completion(&runqueue_node->complete); | |
1315 | runqueue_node->async = req->async; | |
1316 | ||
eb4d9796 MS |
1317 | list_splice_init(&file_priv->inuse_cmdlist, run_cmdlist); |
1318 | list_splice_init(&file_priv->event_list, event_list); | |
d7f1642c JS |
1319 | |
1320 | if (list_empty(run_cmdlist)) { | |
eb4d9796 | 1321 | dev_err(g2d->dev, "there is no inuse cmdlist\n"); |
d7f1642c JS |
1322 | kmem_cache_free(g2d->runqueue_slab, runqueue_node); |
1323 | return -EPERM; | |
1324 | } | |
1325 | ||
1326 | mutex_lock(&g2d->runqueue_mutex); | |
6b6bae24 | 1327 | runqueue_node->pid = current->pid; |
d87342c1 | 1328 | runqueue_node->filp = file; |
d7f1642c | 1329 | list_add_tail(&runqueue_node->list, &g2d->runqueue); |
d7f1642c JS |
1330 | mutex_unlock(&g2d->runqueue_mutex); |
1331 | ||
22d6704d TJ |
1332 | /* Let the runqueue know that there is work to do. */ |
1333 | queue_work(g2d->g2d_workq, &g2d->runqueue_work); | |
1334 | ||
d7f1642c JS |
1335 | if (runqueue_node->async) |
1336 | goto out; | |
1337 | ||
1338 | wait_for_completion(&runqueue_node->complete); | |
1339 | g2d_free_runqueue_node(g2d, runqueue_node); | |
1340 | ||
1341 | out: | |
1342 | return 0; | |
1343 | } | |
d7f1642c | 1344 | |
eb4d9796 | 1345 | int g2d_open(struct drm_device *drm_dev, struct drm_file *file) |
d7f1642c JS |
1346 | { |
1347 | struct drm_exynos_file_private *file_priv = file->driver_priv; | |
d7f1642c | 1348 | |
eb4d9796 MS |
1349 | INIT_LIST_HEAD(&file_priv->inuse_cmdlist); |
1350 | INIT_LIST_HEAD(&file_priv->event_list); | |
1351 | INIT_LIST_HEAD(&file_priv->userptr_list); | |
d7f1642c JS |
1352 | |
1353 | return 0; | |
1354 | } | |
1355 | ||
eb4d9796 | 1356 | void g2d_close(struct drm_device *drm_dev, struct drm_file *file) |
d7f1642c JS |
1357 | { |
1358 | struct drm_exynos_file_private *file_priv = file->driver_priv; | |
eb4d9796 | 1359 | struct exynos_drm_private *priv = drm_dev->dev_private; |
d7f1642c JS |
1360 | struct g2d_data *g2d; |
1361 | struct g2d_cmdlist_node *node, *n; | |
1362 | ||
eb4d9796 | 1363 | if (!priv->g2d_dev) |
d7f1642c JS |
1364 | return; |
1365 | ||
eb4d9796 | 1366 | g2d = dev_get_drvdata(priv->g2d_dev); |
d7f1642c | 1367 | |
53327374 TJ |
1368 | /* Remove the runqueue nodes that belong to us. */ |
1369 | mutex_lock(&g2d->runqueue_mutex); | |
1370 | g2d_remove_runqueue_nodes(g2d, file); | |
1371 | mutex_unlock(&g2d->runqueue_mutex); | |
1372 | ||
134a0fe9 TJ |
1373 | /* |
1374 | * Wait for the runqueue worker to finish its current node. | |
1375 | * After this the engine should no longer be accessing any | |
1376 | * memory belonging to us. | |
1377 | */ | |
1378 | g2d_wait_finish(g2d, file); | |
1379 | ||
53327374 TJ |
1380 | /* |
1381 | * Even after the engine is idle, there might still be stale cmdlists | |
1382 | * (i.e. cmdlisst which we submitted but never executed) around, with | |
1383 | * their corresponding GEM/userptr buffers. | |
1384 | * Properly unmap these buffers here. | |
1385 | */ | |
d7f1642c | 1386 | mutex_lock(&g2d->cmdlist_mutex); |
eb4d9796 | 1387 | list_for_each_entry_safe(node, n, &file_priv->inuse_cmdlist, list) { |
d87342c1 | 1388 | g2d_unmap_cmdlist_gem(g2d, node, file); |
d7f1642c | 1389 | list_move_tail(&node->list, &g2d->free_cmdlist); |
d87342c1 | 1390 | } |
d7f1642c JS |
1391 | mutex_unlock(&g2d->cmdlist_mutex); |
1392 | ||
2a3098ff | 1393 | /* release all g2d_userptr in pool. */ |
eb4d9796 MS |
1394 | g2d_userptr_free_all(g2d, file); |
1395 | } | |
1396 | ||
1397 | static int g2d_bind(struct device *dev, struct device *master, void *data) | |
1398 | { | |
1399 | struct g2d_data *g2d = dev_get_drvdata(dev); | |
1400 | struct drm_device *drm_dev = data; | |
1401 | struct exynos_drm_private *priv = drm_dev->dev_private; | |
1402 | int ret; | |
1403 | ||
1404 | g2d->drm_dev = drm_dev; | |
1405 | ||
1406 | /* allocate dma-aware cmdlist buffer. */ | |
1407 | ret = g2d_init_cmdlist(g2d); | |
1408 | if (ret < 0) { | |
1409 | dev_err(dev, "cmdlist init failed\n"); | |
1410 | return ret; | |
1411 | } | |
1412 | ||
07dc3678 | 1413 | ret = exynos_drm_register_dma(drm_dev, dev, &g2d->dma_priv); |
eb4d9796 MS |
1414 | if (ret < 0) { |
1415 | dev_err(dev, "failed to enable iommu.\n"); | |
1416 | g2d_fini_cmdlist(g2d); | |
1417 | return ret; | |
1418 | } | |
1419 | priv->g2d_dev = dev; | |
2a3098ff | 1420 | |
eb4d9796 MS |
1421 | dev_info(dev, "The Exynos G2D (ver %d.%d) successfully registered.\n", |
1422 | G2D_HW_MAJOR_VER, G2D_HW_MINOR_VER); | |
1423 | return 0; | |
d7f1642c JS |
1424 | } |
1425 | ||
eb4d9796 MS |
1426 | static void g2d_unbind(struct device *dev, struct device *master, void *data) |
1427 | { | |
1428 | struct g2d_data *g2d = dev_get_drvdata(dev); | |
1429 | struct drm_device *drm_dev = data; | |
1430 | struct exynos_drm_private *priv = drm_dev->dev_private; | |
1431 | ||
1432 | /* Suspend operation and wait for engine idle. */ | |
1433 | set_bit(G2D_BIT_SUSPEND_RUNQUEUE, &g2d->flags); | |
1434 | g2d_wait_finish(g2d, NULL); | |
1435 | priv->g2d_dev = NULL; | |
1436 | ||
1437 | cancel_work_sync(&g2d->runqueue_work); | |
07dc3678 | 1438 | exynos_drm_unregister_dma(g2d->drm_dev, dev, &g2d->dma_priv); |
eb4d9796 MS |
1439 | } |
1440 | ||
1441 | static const struct component_ops g2d_component_ops = { | |
1442 | .bind = g2d_bind, | |
1443 | .unbind = g2d_unbind, | |
1444 | }; | |
1445 | ||
56550d94 | 1446 | static int g2d_probe(struct platform_device *pdev) |
d7f1642c JS |
1447 | { |
1448 | struct device *dev = &pdev->dev; | |
1449 | struct resource *res; | |
1450 | struct g2d_data *g2d; | |
d7f1642c JS |
1451 | int ret; |
1452 | ||
d873ab99 | 1453 | g2d = devm_kzalloc(dev, sizeof(*g2d), GFP_KERNEL); |
38bb5253 | 1454 | if (!g2d) |
d7f1642c | 1455 | return -ENOMEM; |
d7f1642c JS |
1456 | |
1457 | g2d->runqueue_slab = kmem_cache_create("g2d_runqueue_slab", | |
1458 | sizeof(struct g2d_runqueue_node), 0, 0, NULL); | |
b7675933 SK |
1459 | if (!g2d->runqueue_slab) |
1460 | return -ENOMEM; | |
d7f1642c JS |
1461 | |
1462 | g2d->dev = dev; | |
1463 | ||
1464 | g2d->g2d_workq = create_singlethread_workqueue("g2d"); | |
1465 | if (!g2d->g2d_workq) { | |
1466 | dev_err(dev, "failed to create workqueue\n"); | |
1467 | ret = -EINVAL; | |
1468 | goto err_destroy_slab; | |
1469 | } | |
1470 | ||
1471 | INIT_WORK(&g2d->runqueue_work, g2d_runqueue_worker); | |
1472 | INIT_LIST_HEAD(&g2d->free_cmdlist); | |
1473 | INIT_LIST_HEAD(&g2d->runqueue); | |
1474 | ||
1475 | mutex_init(&g2d->cmdlist_mutex); | |
1476 | mutex_init(&g2d->runqueue_mutex); | |
1477 | ||
dc625537 | 1478 | g2d->gate_clk = devm_clk_get(dev, "fimg2d"); |
d7f1642c JS |
1479 | if (IS_ERR(g2d->gate_clk)) { |
1480 | dev_err(dev, "failed to get gate clock\n"); | |
1481 | ret = PTR_ERR(g2d->gate_clk); | |
d87342c1 | 1482 | goto err_destroy_workqueue; |
d7f1642c JS |
1483 | } |
1484 | ||
7c3fc2b5 TJ |
1485 | pm_runtime_use_autosuspend(dev); |
1486 | pm_runtime_set_autosuspend_delay(dev, 2000); | |
d7f1642c | 1487 | pm_runtime_enable(dev); |
22d6704d TJ |
1488 | clear_bit(G2D_BIT_SUSPEND_RUNQUEUE, &g2d->flags); |
1489 | clear_bit(G2D_BIT_ENGINE_BUSY, &g2d->flags); | |
d7f1642c JS |
1490 | |
1491 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
d7f1642c | 1492 | |
d873ab99 | 1493 | g2d->regs = devm_ioremap_resource(dev, res); |
d4ed6025 TR |
1494 | if (IS_ERR(g2d->regs)) { |
1495 | ret = PTR_ERR(g2d->regs); | |
b7675933 | 1496 | goto err_put_clk; |
d7f1642c JS |
1497 | } |
1498 | ||
1499 | g2d->irq = platform_get_irq(pdev, 0); | |
1500 | if (g2d->irq < 0) { | |
d7f1642c | 1501 | ret = g2d->irq; |
b7675933 | 1502 | goto err_put_clk; |
d7f1642c JS |
1503 | } |
1504 | ||
d873ab99 | 1505 | ret = devm_request_irq(dev, g2d->irq, g2d_irq_handler, 0, |
b7675933 | 1506 | "drm_g2d", g2d); |
d7f1642c JS |
1507 | if (ret < 0) { |
1508 | dev_err(dev, "irq request failed\n"); | |
b7675933 | 1509 | goto err_put_clk; |
d7f1642c JS |
1510 | } |
1511 | ||
2a3098ff ID |
1512 | g2d->max_pool = MAX_POOL; |
1513 | ||
d7f1642c JS |
1514 | platform_set_drvdata(pdev, g2d); |
1515 | ||
eb4d9796 | 1516 | ret = component_add(dev, &g2d_component_ops); |
d7f1642c JS |
1517 | if (ret < 0) { |
1518 | dev_err(dev, "failed to register drm g2d device\n"); | |
b7675933 | 1519 | goto err_put_clk; |
d7f1642c JS |
1520 | } |
1521 | ||
d7f1642c JS |
1522 | return 0; |
1523 | ||
d7f1642c JS |
1524 | err_put_clk: |
1525 | pm_runtime_disable(dev); | |
d7f1642c JS |
1526 | err_destroy_workqueue: |
1527 | destroy_workqueue(g2d->g2d_workq); | |
1528 | err_destroy_slab: | |
1529 | kmem_cache_destroy(g2d->runqueue_slab); | |
d7f1642c JS |
1530 | return ret; |
1531 | } | |
1532 | ||
56550d94 | 1533 | static int g2d_remove(struct platform_device *pdev) |
d7f1642c JS |
1534 | { |
1535 | struct g2d_data *g2d = platform_get_drvdata(pdev); | |
1536 | ||
eb4d9796 | 1537 | component_del(&pdev->dev, &g2d_component_ops); |
d7f1642c | 1538 | |
53327374 TJ |
1539 | /* There should be no locking needed here. */ |
1540 | g2d_remove_runqueue_nodes(g2d, NULL); | |
d7f1642c | 1541 | |
7c3fc2b5 | 1542 | pm_runtime_dont_use_autosuspend(&pdev->dev); |
d7f1642c | 1543 | pm_runtime_disable(&pdev->dev); |
d7f1642c JS |
1544 | |
1545 | g2d_fini_cmdlist(g2d); | |
1546 | destroy_workqueue(g2d->g2d_workq); | |
1547 | kmem_cache_destroy(g2d->runqueue_slab); | |
d7f1642c JS |
1548 | |
1549 | return 0; | |
1550 | } | |
1551 | ||
05e2e466 TJ |
1552 | #ifdef CONFIG_PM_SLEEP |
1553 | static int g2d_suspend(struct device *dev) | |
d7f1642c JS |
1554 | { |
1555 | struct g2d_data *g2d = dev_get_drvdata(dev); | |
1556 | ||
134a0fe9 TJ |
1557 | /* |
1558 | * Suspend the runqueue worker operation and wait until the G2D | |
1559 | * engine is idle. | |
1560 | */ | |
22d6704d | 1561 | set_bit(G2D_BIT_SUSPEND_RUNQUEUE, &g2d->flags); |
134a0fe9 | 1562 | g2d_wait_finish(g2d, NULL); |
43829731 | 1563 | flush_work(&g2d->runqueue_work); |
d7f1642c | 1564 | |
05e2e466 TJ |
1565 | return 0; |
1566 | } | |
1567 | ||
1568 | static int g2d_resume(struct device *dev) | |
1569 | { | |
1570 | struct g2d_data *g2d = dev_get_drvdata(dev); | |
1571 | ||
22d6704d TJ |
1572 | clear_bit(G2D_BIT_SUSPEND_RUNQUEUE, &g2d->flags); |
1573 | queue_work(g2d->g2d_workq, &g2d->runqueue_work); | |
05e2e466 TJ |
1574 | |
1575 | return 0; | |
1576 | } | |
1577 | #endif | |
1578 | ||
1579 | #ifdef CONFIG_PM | |
1580 | static int g2d_runtime_suspend(struct device *dev) | |
1581 | { | |
1582 | struct g2d_data *g2d = dev_get_drvdata(dev); | |
1583 | ||
b10d6350 ID |
1584 | clk_disable_unprepare(g2d->gate_clk); |
1585 | ||
1586 | return 0; | |
1587 | } | |
1588 | ||
1589 | static int g2d_runtime_resume(struct device *dev) | |
1590 | { | |
1591 | struct g2d_data *g2d = dev_get_drvdata(dev); | |
1592 | int ret; | |
1593 | ||
1594 | ret = clk_prepare_enable(g2d->gate_clk); | |
1595 | if (ret < 0) | |
1596 | dev_warn(dev, "failed to enable clock.\n"); | |
1597 | ||
1598 | return ret; | |
1599 | } | |
1600 | #endif | |
1601 | ||
1602 | static const struct dev_pm_ops g2d_pm_ops = { | |
05e2e466 | 1603 | SET_SYSTEM_SLEEP_PM_OPS(g2d_suspend, g2d_resume) |
b10d6350 ID |
1604 | SET_RUNTIME_PM_OPS(g2d_runtime_suspend, g2d_runtime_resume, NULL) |
1605 | }; | |
d7f1642c | 1606 | |
95fc6337 AK |
1607 | static const struct of_device_id exynos_g2d_match[] = { |
1608 | { .compatible = "samsung,exynos5250-g2d" }, | |
6411fe3c | 1609 | { .compatible = "samsung,exynos4212-g2d" }, |
95fc6337 AK |
1610 | {}, |
1611 | }; | |
0262ceeb | 1612 | MODULE_DEVICE_TABLE(of, exynos_g2d_match); |
95fc6337 | 1613 | |
d7f1642c JS |
1614 | struct platform_driver g2d_driver = { |
1615 | .probe = g2d_probe, | |
56550d94 | 1616 | .remove = g2d_remove, |
d7f1642c | 1617 | .driver = { |
d796ddc9 | 1618 | .name = "exynos-drm-g2d", |
d7f1642c JS |
1619 | .owner = THIS_MODULE, |
1620 | .pm = &g2d_pm_ops, | |
61c48fbf | 1621 | .of_match_table = exynos_g2d_match, |
d7f1642c JS |
1622 | }, |
1623 | }; |