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drm/exynos: fimd: add fimd_enable_video_output() to cleanup
[linux-2.6-block.git] / drivers / gpu / drm / exynos / exynos_drm_fimd.c
CommitLineData
1c248b7d
ID		 1/* exynos_drm_fimd.c
2 *
3 * Copyright (C) 2011 Samsung Electronics Co.Ltd
4 * Authors:
5 * Joonyoung Shim <jy0922.shim@samsung.com>
6 * Inki Dae <inki.dae@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
760285e7 14#include <drm/drmP.h>
1c248b7d
ID		 15
16#include <linux/kernel.h>
1c248b7d
ID		 17#include <linux/platform_device.h>
18#include <linux/clk.h>
3f1c781d 19#include <linux/of.h>
d636ead8 20#include <linux/of_device.h>
cb91f6a0 21#include <linux/pm_runtime.h>
f37cd5e8 22#include <linux/component.h>
3854fab2
YC		 23#include <linux/mfd/syscon.h>
24#include <linux/regmap.h>
1c248b7d 25
7f4596f4 26#include <video/of_display_timing.h>
111e6055 27#include <video/of_videomode.h>
5a213a55 28#include <video/samsung_fimd.h>
1c248b7d 29#include <drm/exynos_drm.h>
1c248b7d
ID		 30
31#include "exynos_drm_drv.h"
32#include "exynos_drm_fbdev.h"
33#include "exynos_drm_crtc.h"
bcc5cd1c 34#include "exynos_drm_iommu.h"
1c248b7d
ID		 35
36/*
b8654b37 37 * FIMD stands for Fully Interactive Mobile Display and
1c248b7d
ID		 38 * as a display controller, it transfers contents drawn on memory
39 * to a LCD Panel through Display Interfaces such as RGB or
40 * CPU Interface.
41 */
42
111e6055 43#define FIMD_DEFAULT_FRAMERATE 60
66367461 44#define MIN_FB_WIDTH_FOR_16WORD_BURST 128
111e6055 45
1c248b7d
ID		 46/* position control register for hardware window 0, 2 ~ 4.*/
47#define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16)
48#define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16)
0f10cf14
LKA		 49/*
50 * size control register for hardware windows 0 and alpha control register
51 * for hardware windows 1 ~ 4
52 */
53#define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16)
54/* size control register for hardware windows 1 ~ 2. */
1c248b7d
ID		 55#define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16)
56
57#define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8)
58#define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8)
59#define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4)
60
61/* color key control register for hardware window 1 ~ 4. */
0f10cf14 62#define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8))
1c248b7d 63/* color key value register for hardware window 1 ~ 4. */
0f10cf14 64#define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8))
1c248b7d 65
3854fab2
YC		 66/* I80 / RGB trigger control register */
67#define TRIGCON 0x1A4
68#define TRGMODE_I80_RGB_ENABLE_I80 (1 << 0)
69#define SWTRGCMD_I80_RGB_ENABLE (1 << 1)
70
71/* display mode change control register except exynos4 */
72#define VIDOUT_CON 0x000
73#define VIDOUT_CON_F_I80_LDI0 (0x2 << 8)
74
75/* I80 interface control for main LDI register */
76#define I80IFCONFAx(x) (0x1B0 + (x) * 4)
77#define I80IFCONFBx(x) (0x1B8 + (x) * 4)
78#define LCD_CS_SETUP(x) ((x) << 16)
79#define LCD_WR_SETUP(x) ((x) << 12)
80#define LCD_WR_ACTIVE(x) ((x) << 8)
81#define LCD_WR_HOLD(x) ((x) << 4)
82#define I80IFEN_ENABLE (1 << 0)
83
1c248b7d
ID		 84/* FIMD has totally five hardware windows. */
85#define WINDOWS_NR 5
86
bb7704d6 87#define get_fimd_manager(mgr) platform_get_drvdata(to_platform_device(dev))
1c248b7d 88
e2e13389
LKA		 89struct fimd_driver_data {
90 unsigned int timing_base;
3854fab2
YC		 91 unsigned int lcdblk_offset;
92 unsigned int lcdblk_vt_shift;
93 unsigned int lcdblk_bypass_shift;
de7af100
TF		 94
95 unsigned int has_shadowcon:1;
411d9ed4 96 unsigned int has_clksel:1;
5cc4621a 97 unsigned int has_limited_fmt:1;
3854fab2 98 unsigned int has_vidoutcon:1;
3c3c9c1d 99 unsigned int has_vtsel:1;
e2e13389
LKA		 100};
101
725ddead
TF		 102static struct fimd_driver_data s3c64xx_fimd_driver_data = {
103 .timing_base = 0x0,
104 .has_clksel = 1,
5cc4621a 105 .has_limited_fmt = 1,
725ddead
TF		 106};
107
d6ce7b58
ID		 108static struct fimd_driver_data exynos3_fimd_driver_data = {
109 .timing_base = 0x20000,
110 .lcdblk_offset = 0x210,
111 .lcdblk_bypass_shift = 1,
112 .has_shadowcon = 1,
113 .has_vidoutcon = 1,
114};
115
6ecf18f9 116static struct fimd_driver_data exynos4_fimd_driver_data = {
e2e13389 117 .timing_base = 0x0,
3854fab2
YC		 118 .lcdblk_offset = 0x210,
119 .lcdblk_vt_shift = 10,
120 .lcdblk_bypass_shift = 1,
de7af100 121 .has_shadowcon = 1,
3c3c9c1d 122 .has_vtsel = 1,
e2e13389
LKA		 123};
124
dcb622aa
YC		 125static struct fimd_driver_data exynos4415_fimd_driver_data = {
126 .timing_base = 0x20000,
127 .lcdblk_offset = 0x210,
128 .lcdblk_vt_shift = 10,
129 .lcdblk_bypass_shift = 1,
130 .has_shadowcon = 1,
131 .has_vidoutcon = 1,
3c3c9c1d 132 .has_vtsel = 1,
dcb622aa
YC		 133};
134
6ecf18f9 135static struct fimd_driver_data exynos5_fimd_driver_data = {
e2e13389 136 .timing_base = 0x20000,
3854fab2
YC		 137 .lcdblk_offset = 0x214,
138 .lcdblk_vt_shift = 24,
139 .lcdblk_bypass_shift = 15,
de7af100 140 .has_shadowcon = 1,
3854fab2 141 .has_vidoutcon = 1,
3c3c9c1d 142 .has_vtsel = 1,
e2e13389
LKA		 143};
144
1c248b7d
ID		 145struct fimd_win_data {
146 unsigned int offset_x;
147 unsigned int offset_y;
19c8b834
ID		 148 unsigned int ovl_width;
149 unsigned int ovl_height;
150 unsigned int fb_width;
151 unsigned int fb_height;
1c248b7d 152 unsigned int bpp;
a4f38a80 153 unsigned int pixel_format;
2c871127 154 dma_addr_t dma_addr;
1c248b7d
ID		 155 unsigned int buf_offsize;
156 unsigned int line_size; /* bytes */
ec05da95 157 bool enabled;
db7e55ae 158 bool resume;
1c248b7d
ID		 159};
160
161struct fimd_context {
bb7704d6 162 struct device *dev;
40c8ab4b 163 struct drm_device *drm_dev;
1c248b7d
ID		 164 struct clk *bus_clk;
165 struct clk *lcd_clk;
1c248b7d 166 void __iomem *regs;
3854fab2 167 struct regmap *sysreg;
a968e727 168 struct drm_display_mode mode;
1c248b7d 169 struct fimd_win_data win_data[WINDOWS_NR];
1c248b7d
ID		 170 unsigned int default_win;
171 unsigned long irq_flags;
3854fab2 172 u32 vidcon0;
1c248b7d 173 u32 vidcon1;
3854fab2
YC		 174 u32 vidout_con;
175 u32 i80ifcon;
176 bool i80_if;
cb91f6a0 177 bool suspended;
080be03d 178 int pipe;
01ce113c
P		 179 wait_queue_head_t wait_vsync_queue;
180 atomic_t wait_vsync_event;
3854fab2
YC		 181 atomic_t win_updated;
182 atomic_t triggering;
1c248b7d 183
562ad9f4 184 struct exynos_drm_panel_info panel;
18873465 185 struct fimd_driver_data *driver_data;
000cc920 186 struct exynos_drm_display *display;
1c248b7d
ID		 187};
188
d636ead8 189static const struct of_device_id fimd_driver_dt_match[] = {
725ddead
TF		 190 { .compatible = "samsung,s3c6400-fimd",
191 .data = &s3c64xx_fimd_driver_data },
d6ce7b58
ID		 192 { .compatible = "samsung,exynos3250-fimd",
193 .data = &exynos3_fimd_driver_data },
5830daf8 194 { .compatible = "samsung,exynos4210-fimd",
d636ead8 195 .data = &exynos4_fimd_driver_data },
dcb622aa
YC		 196 { .compatible = "samsung,exynos4415-fimd",
197 .data = &exynos4415_fimd_driver_data },
5830daf8 198 { .compatible = "samsung,exynos5250-fimd",
d636ead8
JS		 199 .data = &exynos5_fimd_driver_data },
200 {},
201};
0262ceeb 202MODULE_DEVICE_TABLE(of, fimd_driver_dt_match);
d636ead8 203
e2e13389
LKA		 204static inline struct fimd_driver_data *drm_fimd_get_driver_data(
205 struct platform_device *pdev)
206{
d636ead8
JS		 207 const struct of_device_id *of_id =
208 of_match_device(fimd_driver_dt_match, &pdev->dev);
209
2d3f173c 210 return (struct fimd_driver_data *)of_id->data;
e2e13389
LKA		 211}
212
f13bdbd1
AA		 213static void fimd_wait_for_vblank(struct exynos_drm_manager *mgr)
214{
215 struct fimd_context *ctx = mgr->ctx;
216
217 if (ctx->suspended)
218 return;
219
220 atomic_set(&ctx->wait_vsync_event, 1);
221
222 /*
223 * wait for FIMD to signal VSYNC interrupt or return after
224 * timeout which is set to 50ms (refresh rate of 20).
225 */
226 if (!wait_event_timeout(ctx->wait_vsync_queue,
227 !atomic_read(&ctx->wait_vsync_event),
228 HZ/20))
229 DRM_DEBUG_KMS("vblank wait timed out.\n");
230}
231
f181a543
YC		 232static void fimd_enable_video_output(struct fimd_context *ctx, int win,
233 bool enable)
234{
235 u32 val = readl(ctx->regs + WINCON(win));
236
237 if (enable)
238 val |= WINCONx_ENWIN;
239 else
240 val &= ~WINCONx_ENWIN;
241
242 writel(val, ctx->regs + WINCON(win));
243}
244
f13bdbd1
AA		 245static void fimd_clear_channel(struct exynos_drm_manager *mgr)
246{
247 struct fimd_context *ctx = mgr->ctx;
248 int win, ch_enabled = 0;
249
250 DRM_DEBUG_KMS("%s\n", __FILE__);
251
252 /* Check if any channel is enabled. */
253 for (win = 0; win < WINDOWS_NR; win++) {
eb8a3bf7
MS		 254 u32 val = readl(ctx->regs + WINCON(win));
255
256 if (val & WINCONx_ENWIN) {
f181a543 257 fimd_enable_video_output(ctx, win, false);
eb8a3bf7
MS		 258
259 /* unprotect windows */
260 if (ctx->driver_data->has_shadowcon) {
261 val = readl(ctx->regs + SHADOWCON);
262 val &= ~SHADOWCON_CHx_ENABLE(win);
263 writel(val, ctx->regs + SHADOWCON);
264 }
f13bdbd1
AA		 265 ch_enabled = 1;
266 }
267 }
268
269 /* Wait for vsync, as disable channel takes effect at next vsync */
eb8a3bf7
MS		 270 if (ch_enabled) {
271 unsigned int state = ctx->suspended;
272
273 ctx->suspended = 0;
f13bdbd1 274 fimd_wait_for_vblank(mgr);
eb8a3bf7
MS		 275 ctx->suspended = state;
276 }
f13bdbd1
AA		 277}
278
bb7704d6 279static int fimd_mgr_initialize(struct exynos_drm_manager *mgr,
f37cd5e8 280 struct drm_device *drm_dev)
40c8ab4b 281{
bb7704d6 282 struct fimd_context *ctx = mgr->ctx;
f37cd5e8
ID		 283 struct exynos_drm_private *priv;
284 priv = drm_dev->dev_private;
40c8ab4b 285
f37cd5e8
ID		 286 mgr->drm_dev = ctx->drm_dev = drm_dev;
287 mgr->pipe = ctx->pipe = priv->pipe++;
40c8ab4b 288
080be03d 289 /* attach this sub driver to iommu mapping if supported. */
f13bdbd1
AA		 290 if (is_drm_iommu_supported(ctx->drm_dev)) {
291 /*
292 * If any channel is already active, iommu will throw
293 * a PAGE FAULT when enabled. So clear any channel if enabled.
294 */
295 fimd_clear_channel(mgr);
080be03d 296 drm_iommu_attach_device(ctx->drm_dev, ctx->dev);
f13bdbd1 297 }
c32b06ef 298
080be03d 299 return 0;
ec05da95
ID		 300}
301
080be03d 302static void fimd_mgr_remove(struct exynos_drm_manager *mgr)
ec05da95 303{
bb7704d6 304 struct fimd_context *ctx = mgr->ctx;
ec05da95 305
080be03d
SP		 306 /* detach this sub driver from iommu mapping if supported. */
307 if (is_drm_iommu_supported(ctx->drm_dev))
308 drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
ec05da95
ID		 309}
310
a968e727
SP		 311static u32 fimd_calc_clkdiv(struct fimd_context *ctx,
312 const struct drm_display_mode *mode)
313{
314 unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh;
315 u32 clkdiv;
316
3854fab2
YC		 317 if (ctx->i80_if) {
318 /*
319 * The frame done interrupt should be occurred prior to the
320 * next TE signal.
321 */
322 ideal_clk *= 2;
323 }
324
a968e727
SP		 325 /* Find the clock divider value that gets us closest to ideal_clk */
326 clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->lcd_clk), ideal_clk);
327
328 return (clkdiv < 0x100) ? clkdiv : 0xff;
329}
330
331static bool fimd_mode_fixup(struct exynos_drm_manager *mgr,
332 const struct drm_display_mode *mode,
333 struct drm_display_mode *adjusted_mode)
334{
335 if (adjusted_mode->vrefresh == 0)
336 adjusted_mode->vrefresh = FIMD_DEFAULT_FRAMERATE;
337
338 return true;
339}
340
341static void fimd_mode_set(struct exynos_drm_manager *mgr,
342 const struct drm_display_mode *in_mode)
343{
344 struct fimd_context *ctx = mgr->ctx;
345
346 drm_mode_copy(&ctx->mode, in_mode);
347}
348
bb7704d6 349static void fimd_commit(struct exynos_drm_manager *mgr)
1c248b7d 350{
bb7704d6 351 struct fimd_context *ctx = mgr->ctx;
a968e727 352 struct drm_display_mode *mode = &ctx->mode;
3854fab2
YC		 353 struct fimd_driver_data *driver_data = ctx->driver_data;
354 void *timing_base = ctx->regs + driver_data->timing_base;
355 u32 val, clkdiv;
1c248b7d 356
e30d4bcf
ID		 357 if (ctx->suspended)
358 return;
359
a968e727
SP		 360 /* nothing to do if we haven't set the mode yet */
361 if (mode->htotal == 0 || mode->vtotal == 0)
362 return;
363
3854fab2
YC		 364 if (ctx->i80_if) {
365 val = ctx->i80ifcon | I80IFEN_ENABLE;
366 writel(val, timing_base + I80IFCONFAx(0));
367
368 /* disable auto frame rate */
369 writel(0, timing_base + I80IFCONFBx(0));
370
371 /* set video type selection to I80 interface */
3c3c9c1d
JS		 372 if (driver_data->has_vtsel && ctx->sysreg &&
373 regmap_update_bits(ctx->sysreg,
3854fab2
YC		 374 driver_data->lcdblk_offset,
375 0x3 << driver_data->lcdblk_vt_shift,
376 0x1 << driver_data->lcdblk_vt_shift)) {
377 DRM_ERROR("Failed to update sysreg for I80 i/f.\n");
378 return;
379 }
380 } else {
381 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
382 u32 vidcon1;
383
384 /* setup polarity values */
385 vidcon1 = ctx->vidcon1;
386 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
387 vidcon1 |= VIDCON1_INV_VSYNC;
388 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
389 vidcon1 |= VIDCON1_INV_HSYNC;
390 writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1);
391
392 /* setup vertical timing values. */
393 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
394 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
395 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;
396
397 val = VIDTCON0_VBPD(vbpd - 1) |
398 VIDTCON0_VFPD(vfpd - 1) |
399 VIDTCON0_VSPW(vsync_len - 1);
400 writel(val, ctx->regs + driver_data->timing_base + VIDTCON0);
401
402 /* setup horizontal timing values. */
403 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
404 hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
405 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;
406
407 val = VIDTCON1_HBPD(hbpd - 1) |
408 VIDTCON1_HFPD(hfpd - 1) |
409 VIDTCON1_HSPW(hsync_len - 1);
410 writel(val, ctx->regs + driver_data->timing_base + VIDTCON1);
411 }
412
413 if (driver_data->has_vidoutcon)
414 writel(ctx->vidout_con, timing_base + VIDOUT_CON);
415
416 /* set bypass selection */
417 if (ctx->sysreg && regmap_update_bits(ctx->sysreg,
418 driver_data->lcdblk_offset,
419 0x1 << driver_data->lcdblk_bypass_shift,
420 0x1 << driver_data->lcdblk_bypass_shift)) {
421 DRM_ERROR("Failed to update sysreg for bypass setting.\n");
422 return;
423 }
1c248b7d
ID		 424
425 /* setup horizontal and vertical display size. */
a968e727
SP		 426 val = VIDTCON2_LINEVAL(mode->vdisplay - 1) |
427 VIDTCON2_HOZVAL(mode->hdisplay - 1) |
428 VIDTCON2_LINEVAL_E(mode->vdisplay - 1) |
429 VIDTCON2_HOZVAL_E(mode->hdisplay - 1);
e2e13389 430 writel(val, ctx->regs + driver_data->timing_base + VIDTCON2);
1c248b7d 431
1d531062
AH		 432 /*
433 * fields of register with prefix '_F' would be updated
434 * at vsync(same as dma start)
435 */
3854fab2
YC		 436 val = ctx->vidcon0;
437 val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
1c248b7d 438
1d531062 439 if (ctx->driver_data->has_clksel)
411d9ed4 440 val |= VIDCON0_CLKSEL_LCD;
411d9ed4 441
a968e727
SP		 442 clkdiv = fimd_calc_clkdiv(ctx, mode);
443 if (clkdiv > 1)
444 val |= VIDCON0_CLKVAL_F(clkdiv - 1) | VIDCON0_CLKDIR;
1c248b7d 445
1c248b7d
ID		 446 writel(val, ctx->regs + VIDCON0);
447}
448
bb7704d6 449static int fimd_enable_vblank(struct exynos_drm_manager *mgr)
1c248b7d 450{
bb7704d6 451 struct fimd_context *ctx = mgr->ctx;
1c248b7d
ID		 452 u32 val;
453
cb91f6a0
JS		 454 if (ctx->suspended)
455 return -EPERM;
456
1c248b7d
ID		 457 if (!test_and_set_bit(0, &ctx->irq_flags)) {
458 val = readl(ctx->regs + VIDINTCON0);
459
460 val |= VIDINTCON0_INT_ENABLE;
461 val |= VIDINTCON0_INT_FRAME;
462
463 val &= ~VIDINTCON0_FRAMESEL0_MASK;
464 val |= VIDINTCON0_FRAMESEL0_VSYNC;
465 val &= ~VIDINTCON0_FRAMESEL1_MASK;
466 val |= VIDINTCON0_FRAMESEL1_NONE;
467
468 writel(val, ctx->regs + VIDINTCON0);
469 }
470
471 return 0;
472}
473
bb7704d6 474static void fimd_disable_vblank(struct exynos_drm_manager *mgr)
1c248b7d 475{
bb7704d6 476 struct fimd_context *ctx = mgr->ctx;
1c248b7d
ID		 477 u32 val;
478
cb91f6a0
JS		 479 if (ctx->suspended)
480 return;
481
1c248b7d
ID		 482 if (test_and_clear_bit(0, &ctx->irq_flags)) {
483 val = readl(ctx->regs + VIDINTCON0);
484
485 val &= ~VIDINTCON0_INT_FRAME;
486 val &= ~VIDINTCON0_INT_ENABLE;
487
488 writel(val, ctx->regs + VIDINTCON0);
489 }
490}
491
bb7704d6
SP		 492static void fimd_win_mode_set(struct exynos_drm_manager *mgr,
493 struct exynos_drm_overlay *overlay)
1c248b7d 494{
bb7704d6 495 struct fimd_context *ctx = mgr->ctx;
1c248b7d 496 struct fimd_win_data *win_data;
864ee9e6 497 int win;
19c8b834 498 unsigned long offset;
1c248b7d 499
1c248b7d 500 if (!overlay) {
bb7704d6 501 DRM_ERROR("overlay is NULL\n");
1c248b7d
ID		 502 return;
503 }
504
864ee9e6
JS		 505 win = overlay->zpos;
506 if (win == DEFAULT_ZPOS)
507 win = ctx->default_win;
508
37b006e8 509 if (win < 0 || win >= WINDOWS_NR)
864ee9e6
JS		 510 return;
511
19c8b834
ID		 512 offset = overlay->fb_x * (overlay->bpp >> 3);
513 offset += overlay->fb_y * overlay->pitch;
514
515 DRM_DEBUG_KMS("offset = 0x%lx, pitch = %x\n", offset, overlay->pitch);
516
864ee9e6 517 win_data = &ctx->win_data[win];
1c248b7d 518
19c8b834
ID		 519 win_data->offset_x = overlay->crtc_x;
520 win_data->offset_y = overlay->crtc_y;
521 win_data->ovl_width = overlay->crtc_width;
522 win_data->ovl_height = overlay->crtc_height;
523 win_data->fb_width = overlay->fb_width;
524 win_data->fb_height = overlay->fb_height;
229d3534 525 win_data->dma_addr = overlay->dma_addr[0] + offset;
1c248b7d 526 win_data->bpp = overlay->bpp;
a4f38a80 527 win_data->pixel_format = overlay->pixel_format;
19c8b834
ID		 528 win_data->buf_offsize = (overlay->fb_width - overlay->crtc_width) *
529 (overlay->bpp >> 3);
530 win_data->line_size = overlay->crtc_width * (overlay->bpp >> 3);
531
532 DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n",
533 win_data->offset_x, win_data->offset_y);
534 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
535 win_data->ovl_width, win_data->ovl_height);
ddd8e959 536 DRM_DEBUG_KMS("paddr = 0x%lx\n", (unsigned long)win_data->dma_addr);
19c8b834
ID		 537 DRM_DEBUG_KMS("fb_width = %d, crtc_width = %d\n",
538 overlay->fb_width, overlay->crtc_width);
1c248b7d
ID		 539}
540
bb7704d6 541static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win)
1c248b7d 542{
1c248b7d
ID		 543 struct fimd_win_data *win_data = &ctx->win_data[win];
544 unsigned long val;
545
1c248b7d
ID		 546 val = WINCONx_ENWIN;
547
5cc4621a
ID		 548 /*
549 * In case of s3c64xx, window 0 doesn't support alpha channel.
550 * So the request format is ARGB8888 then change it to XRGB8888.
551 */
552 if (ctx->driver_data->has_limited_fmt && !win) {
553 if (win_data->pixel_format == DRM_FORMAT_ARGB8888)
554 win_data->pixel_format = DRM_FORMAT_XRGB8888;
555 }
556
a4f38a80
ID		 557 switch (win_data->pixel_format) {
558 case DRM_FORMAT_C8:
1c248b7d
ID		 559 val |= WINCON0_BPPMODE_8BPP_PALETTE;
560 val |= WINCONx_BURSTLEN_8WORD;
561 val |= WINCONx_BYTSWP;
562 break;
a4f38a80
ID		 563 case DRM_FORMAT_XRGB1555:
564 val |= WINCON0_BPPMODE_16BPP_1555;
565 val |= WINCONx_HAWSWP;
566 val |= WINCONx_BURSTLEN_16WORD;
567 break;
568 case DRM_FORMAT_RGB565:
1c248b7d
ID		 569 val |= WINCON0_BPPMODE_16BPP_565;
570 val |= WINCONx_HAWSWP;
571 val |= WINCONx_BURSTLEN_16WORD;
572 break;
a4f38a80 573 case DRM_FORMAT_XRGB8888:
1c248b7d
ID		 574 val |= WINCON0_BPPMODE_24BPP_888;
575 val |= WINCONx_WSWP;
576 val |= WINCONx_BURSTLEN_16WORD;
577 break;
a4f38a80
ID		 578 case DRM_FORMAT_ARGB8888:
579 val |= WINCON1_BPPMODE_25BPP_A1888
1c248b7d
ID		 580 | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
581 val |= WINCONx_WSWP;
582 val |= WINCONx_BURSTLEN_16WORD;
583 break;
584 default:
585 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
586
587 val |= WINCON0_BPPMODE_24BPP_888;
588 val |= WINCONx_WSWP;
589 val |= WINCONx_BURSTLEN_16WORD;
590 break;
591 }
592
593 DRM_DEBUG_KMS("bpp = %d\n", win_data->bpp);
594
66367461
RS		 595 /*
596 * In case of exynos, setting dma-burst to 16Word causes permanent
597 * tearing for very small buffers, e.g. cursor buffer. Burst Mode
598 * switching which is based on overlay size is not recommended as
599 * overlay size varies alot towards the end of the screen and rapid
600 * movement causes unstable DMA which results into iommu crash/tear.
601 */
602
603 if (win_data->fb_width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
604 val &= ~WINCONx_BURSTLEN_MASK;
605 val |= WINCONx_BURSTLEN_4WORD;
606 }
607
1c248b7d
ID		 608 writel(val, ctx->regs + WINCON(win));
609}
610
bb7704d6 611static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win)
1c248b7d 612{
1c248b7d
ID		 613 unsigned int keycon0 = 0, keycon1 = 0;
614
1c248b7d
ID		 615 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
616 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
617
618 keycon1 = WxKEYCON1_COLVAL(0xffffffff);
619
620 writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
621 writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
622}
623
de7af100
TF		 624/**
625 * shadow_protect_win() - disable updating values from shadow registers at vsync
626 *
627 * @win: window to protect registers for
628 * @protect: 1 to protect (disable updates)
629 */
630static void fimd_shadow_protect_win(struct fimd_context *ctx,
631 int win, bool protect)
632{
633 u32 reg, bits, val;
634
635 if (ctx->driver_data->has_shadowcon) {
636 reg = SHADOWCON;
637 bits = SHADOWCON_WINx_PROTECT(win);
638 } else {
639 reg = PRTCON;
640 bits = PRTCON_PROTECT;
641 }
642
643 val = readl(ctx->regs + reg);
644 if (protect)
645 val |= bits;
646 else
647 val &= ~bits;
648 writel(val, ctx->regs + reg);
649}
650
bb7704d6 651static void fimd_win_commit(struct exynos_drm_manager *mgr, int zpos)
1c248b7d 652{
bb7704d6 653 struct fimd_context *ctx = mgr->ctx;
1c248b7d 654 struct fimd_win_data *win_data;
864ee9e6 655 int win = zpos;
1c248b7d 656 unsigned long val, alpha, size;
f56aad3a
JS		 657 unsigned int last_x;
658 unsigned int last_y;
1c248b7d 659
e30d4bcf
ID		 660 if (ctx->suspended)
661 return;
662
864ee9e6
JS		 663 if (win == DEFAULT_ZPOS)
664 win = ctx->default_win;
665
37b006e8 666 if (win < 0 || win >= WINDOWS_NR)
1c248b7d
ID		 667 return;
668
669 win_data = &ctx->win_data[win];
670
a43b933b
SP		 671 /* If suspended, enable this on resume */
672 if (ctx->suspended) {
673 win_data->resume = true;
674 return;
675 }
676
1c248b7d 677 /*
de7af100 678 * SHADOWCON/PRTCON register is used for enabling timing.
1c248b7d
ID		 679 *
680 * for example, once only width value of a register is set,
681 * if the dma is started then fimd hardware could malfunction so
682 * with protect window setting, the register fields with prefix '_F'
683 * wouldn't be updated at vsync also but updated once unprotect window
684 * is set.
685 */
686
687 /* protect windows */
de7af100 688 fimd_shadow_protect_win(ctx, win, true);
1c248b7d
ID		 689
690 /* buffer start address */
2c871127 691 val = (unsigned long)win_data->dma_addr;
1c248b7d
ID		 692 writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
693
694 /* buffer end address */
19c8b834 695 size = win_data->fb_width * win_data->ovl_height * (win_data->bpp >> 3);
2c871127 696 val = (unsigned long)(win_data->dma_addr + size);
1c248b7d
ID		 697 writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
698
699 DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
2c871127 700 (unsigned long)win_data->dma_addr, val, size);
19c8b834
ID		 701 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
702 win_data->ovl_width, win_data->ovl_height);
1c248b7d
ID		 703
704 /* buffer size */
705 val = VIDW_BUF_SIZE_OFFSET(win_data->buf_offsize) |
ca555e5a
JS		 706 VIDW_BUF_SIZE_PAGEWIDTH(win_data->line_size) |
707 VIDW_BUF_SIZE_OFFSET_E(win_data->buf_offsize) |
708 VIDW_BUF_SIZE_PAGEWIDTH_E(win_data->line_size);
1c248b7d
ID		 709 writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
710
711 /* OSD position */
712 val = VIDOSDxA_TOPLEFT_X(win_data->offset_x) |
ca555e5a
JS		 713 VIDOSDxA_TOPLEFT_Y(win_data->offset_y) |
714 VIDOSDxA_TOPLEFT_X_E(win_data->offset_x) |
715 VIDOSDxA_TOPLEFT_Y_E(win_data->offset_y);
1c248b7d
ID		 716 writel(val, ctx->regs + VIDOSD_A(win));
717
f56aad3a
JS		 718 last_x = win_data->offset_x + win_data->ovl_width;
719 if (last_x)
720 last_x--;
721 last_y = win_data->offset_y + win_data->ovl_height;
722 if (last_y)
723 last_y--;
724
ca555e5a
JS		 725 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) |
726 VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y);
727
1c248b7d
ID		 728 writel(val, ctx->regs + VIDOSD_B(win));
729
19c8b834 730 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
f56aad3a 731 win_data->offset_x, win_data->offset_y, last_x, last_y);
1c248b7d
ID		 732
733 /* hardware window 0 doesn't support alpha channel. */
734 if (win != 0) {
735 /* OSD alpha */
736 alpha = VIDISD14C_ALPHA1_R(0xf) |
737 VIDISD14C_ALPHA1_G(0xf) |
738 VIDISD14C_ALPHA1_B(0xf);
739
740 writel(alpha, ctx->regs + VIDOSD_C(win));
741 }
742
743 /* OSD size */
744 if (win != 3 && win != 4) {
745 u32 offset = VIDOSD_D(win);
746 if (win == 0)
0f10cf14 747 offset = VIDOSD_C(win);
19c8b834 748 val = win_data->ovl_width * win_data->ovl_height;
1c248b7d
ID		 749 writel(val, ctx->regs + offset);
750
751 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val);
752 }
753
bb7704d6 754 fimd_win_set_pixfmt(ctx, win);
1c248b7d
ID		 755
756 /* hardware window 0 doesn't support color key. */
757 if (win != 0)
bb7704d6 758 fimd_win_set_colkey(ctx, win);
1c248b7d 759
f181a543 760 fimd_enable_video_output(ctx, win, true);
ec05da95 761
de7af100
TF		 762 if (ctx->driver_data->has_shadowcon) {
763 val = readl(ctx->regs + SHADOWCON);
764 val |= SHADOWCON_CHx_ENABLE(win);
765 writel(val, ctx->regs + SHADOWCON);
766 }
ec05da95 767
74944a58
YC		 768 /* Enable DMA channel and unprotect windows */
769 fimd_shadow_protect_win(ctx, win, false);
770
ec05da95 771 win_data->enabled = true;
3854fab2
YC		 772
773 if (ctx->i80_if)
774 atomic_set(&ctx->win_updated, 1);
1c248b7d
ID		 775}
776
bb7704d6 777static void fimd_win_disable(struct exynos_drm_manager *mgr, int zpos)
1c248b7d 778{
bb7704d6 779 struct fimd_context *ctx = mgr->ctx;
ec05da95 780 struct fimd_win_data *win_data;
864ee9e6 781 int win = zpos;
1c248b7d
ID		 782 u32 val;
783
864ee9e6
JS		 784 if (win == DEFAULT_ZPOS)
785 win = ctx->default_win;
786
37b006e8 787 if (win < 0 || win >= WINDOWS_NR)
1c248b7d
ID		 788 return;
789
ec05da95
ID		 790 win_data = &ctx->win_data[win];
791
db7e55ae
P		 792 if (ctx->suspended) {
793 /* do not resume this window*/
794 win_data->resume = false;
795 return;
796 }
797
1c248b7d 798 /* protect windows */
de7af100 799 fimd_shadow_protect_win(ctx, win, true);
1c248b7d 800
f181a543 801 fimd_enable_video_output(ctx, win, false);
1c248b7d
ID		 802
803 /* unprotect windows */
de7af100
TF		 804 if (ctx->driver_data->has_shadowcon) {
805 val = readl(ctx->regs + SHADOWCON);
806 val &= ~SHADOWCON_CHx_ENABLE(win);
807 writel(val, ctx->regs + SHADOWCON);
808 }
809
810 fimd_shadow_protect_win(ctx, win, false);
ec05da95
ID		 811
812 win_data->enabled = false;
1c248b7d
ID		 813}
814
a43b933b
SP		 815static void fimd_window_suspend(struct exynos_drm_manager *mgr)
816{
817 struct fimd_context *ctx = mgr->ctx;
818 struct fimd_win_data *win_data;
819 int i;
820
821 for (i = 0; i < WINDOWS_NR; i++) {
822 win_data = &ctx->win_data[i];
823 win_data->resume = win_data->enabled;
824 if (win_data->enabled)
825 fimd_win_disable(mgr, i);
826 }
a43b933b
SP		 827}
828
829static void fimd_window_resume(struct exynos_drm_manager *mgr)
830{
831 struct fimd_context *ctx = mgr->ctx;
832 struct fimd_win_data *win_data;
833 int i;
834
835 for (i = 0; i < WINDOWS_NR; i++) {
836 win_data = &ctx->win_data[i];
837 win_data->enabled = win_data->resume;
838 win_data->resume = false;
839 }
840}
841
842static void fimd_apply(struct exynos_drm_manager *mgr)
843{
844 struct fimd_context *ctx = mgr->ctx;
845 struct fimd_win_data *win_data;
846 int i;
847
848 for (i = 0; i < WINDOWS_NR; i++) {
849 win_data = &ctx->win_data[i];
850 if (win_data->enabled)
851 fimd_win_commit(mgr, i);
d9b68d89
AH		 852 else
853 fimd_win_disable(mgr, i);
a43b933b
SP		 854 }
855
856 fimd_commit(mgr);
857}
858
859static int fimd_poweron(struct exynos_drm_manager *mgr)
860{
861 struct fimd_context *ctx = mgr->ctx;
862 int ret;
863
864 if (!ctx->suspended)
865 return 0;
866
867 ctx->suspended = false;
868
af65c804
SP		 869 pm_runtime_get_sync(ctx->dev);
870
a43b933b
SP		 871 ret = clk_prepare_enable(ctx->bus_clk);
872 if (ret < 0) {
873 DRM_ERROR("Failed to prepare_enable the bus clk [%d]\n", ret);
874 goto bus_clk_err;
875 }
876
877 ret = clk_prepare_enable(ctx->lcd_clk);
878 if (ret < 0) {
879 DRM_ERROR("Failed to prepare_enable the lcd clk [%d]\n", ret);
880 goto lcd_clk_err;
881 }
882
883 /* if vblank was enabled status, enable it again. */
884 if (test_and_clear_bit(0, &ctx->irq_flags)) {
885 ret = fimd_enable_vblank(mgr);
886 if (ret) {
887 DRM_ERROR("Failed to re-enable vblank [%d]\n", ret);
888 goto enable_vblank_err;
889 }
890 }
891
892 fimd_window_resume(mgr);
893
894 fimd_apply(mgr);
895
896 return 0;
897
898enable_vblank_err:
899 clk_disable_unprepare(ctx->lcd_clk);
900lcd_clk_err:
901 clk_disable_unprepare(ctx->bus_clk);
902bus_clk_err:
903 ctx->suspended = true;
904 return ret;
905}
906
907static int fimd_poweroff(struct exynos_drm_manager *mgr)
908{
909 struct fimd_context *ctx = mgr->ctx;
910
911 if (ctx->suspended)
912 return 0;
913
914 /*
915 * We need to make sure that all windows are disabled before we
916 * suspend that connector. Otherwise we might try to scan from
917 * a destroyed buffer later.
918 */
919 fimd_window_suspend(mgr);
920
921 clk_disable_unprepare(ctx->lcd_clk);
922 clk_disable_unprepare(ctx->bus_clk);
923
af65c804
SP		 924 pm_runtime_put_sync(ctx->dev);
925
a43b933b
SP		 926 ctx->suspended = true;
927 return 0;
928}
929
080be03d
SP		 930static void fimd_dpms(struct exynos_drm_manager *mgr, int mode)
931{
af65c804 932 DRM_DEBUG_KMS("%s, %d\n", __FILE__, mode);
080be03d 933
080be03d
SP		 934 switch (mode) {
935 case DRM_MODE_DPMS_ON:
af65c804 936 fimd_poweron(mgr);
080be03d
SP		 937 break;
938 case DRM_MODE_DPMS_STANDBY:
939 case DRM_MODE_DPMS_SUSPEND:
940 case DRM_MODE_DPMS_OFF:
af65c804 941 fimd_poweroff(mgr);
080be03d
SP		 942 break;
943 default:
944 DRM_DEBUG_KMS("unspecified mode %d\n", mode);
945 break;
946 }
080be03d
SP		 947}
948
3854fab2
YC		 949static void fimd_trigger(struct device *dev)
950{
951 struct exynos_drm_manager *mgr = get_fimd_manager(dev);
952 struct fimd_context *ctx = mgr->ctx;
953 struct fimd_driver_data *driver_data = ctx->driver_data;
954 void *timing_base = ctx->regs + driver_data->timing_base;
955 u32 reg;
956
9b67eb73
JS		 957 /*
958 * Skips to trigger if in triggering state, because multiple triggering
959 * requests can cause panel reset.
960 */
961 if (atomic_read(&ctx->triggering))
962 return;
963
3854fab2
YC		 964 atomic_set(&ctx->triggering, 1);
965
966 reg = readl(ctx->regs + VIDINTCON0);
967 reg |= (VIDINTCON0_INT_ENABLE | VIDINTCON0_INT_I80IFDONE |
968 VIDINTCON0_INT_SYSMAINCON);
969 writel(reg, ctx->regs + VIDINTCON0);
970
971 reg = readl(timing_base + TRIGCON);
972 reg |= (TRGMODE_I80_RGB_ENABLE_I80 | SWTRGCMD_I80_RGB_ENABLE);
973 writel(reg, timing_base + TRIGCON);
974}
975
976static void fimd_te_handler(struct exynos_drm_manager *mgr)
977{
978 struct fimd_context *ctx = mgr->ctx;
979
980 /* Checks the crtc is detached already from encoder */
981 if (ctx->pipe < 0 || !ctx->drm_dev)
982 return;
983
3854fab2
YC		 984 /*
985 * If there is a page flip request, triggers and handles the page flip
986 * event so that current fb can be updated into panel GRAM.
987 */
988 if (atomic_add_unless(&ctx->win_updated, -1, 0))
989 fimd_trigger(ctx->dev);
990
991 /* Wakes up vsync event queue */
992 if (atomic_read(&ctx->wait_vsync_event)) {
993 atomic_set(&ctx->wait_vsync_event, 0);
994 wake_up(&ctx->wait_vsync_queue);
3854fab2 995 }
b301ae24
YC		 996
997 if (!atomic_read(&ctx->triggering))
998 drm_handle_vblank(ctx->drm_dev, ctx->pipe);
3854fab2
YC		 999}
1000
1c6244c3
SP		 1001static struct exynos_drm_manager_ops fimd_manager_ops = {
1002 .dpms = fimd_dpms,
a968e727
SP		 1003 .mode_fixup = fimd_mode_fixup,
1004 .mode_set = fimd_mode_set,
1c6244c3
SP		 1005 .commit = fimd_commit,
1006 .enable_vblank = fimd_enable_vblank,
1007 .disable_vblank = fimd_disable_vblank,
1008 .wait_for_vblank = fimd_wait_for_vblank,
1009 .win_mode_set = fimd_win_mode_set,
1010 .win_commit = fimd_win_commit,
1011 .win_disable = fimd_win_disable,
3854fab2 1012 .te_handler = fimd_te_handler,
1c248b7d
ID		 1013};
1014
677e84c1 1015static struct exynos_drm_manager fimd_manager = {
080be03d
SP		 1016 .type = EXYNOS_DISPLAY_TYPE_LCD,
1017 .ops = &fimd_manager_ops,
677e84c1
JS		 1018};
1019
1c248b7d
ID		 1020static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
1021{
1022 struct fimd_context *ctx = (struct fimd_context *)dev_id;
3854fab2 1023 u32 val, clear_bit;
1c248b7d
ID		 1024
1025 val = readl(ctx->regs + VIDINTCON1);
1026
3854fab2
YC		 1027 clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME;
1028 if (val & clear_bit)
1029 writel(clear_bit, ctx->regs + VIDINTCON1);
1c248b7d 1030
ec05da95 1031 /* check the crtc is detached already from encoder */
080be03d 1032 if (ctx->pipe < 0 || !ctx->drm_dev)
ec05da95 1033 goto out;
483b88f8 1034
3854fab2
YC		 1035 if (ctx->i80_if) {
1036 /* unset I80 frame done interrupt */
1037 val = readl(ctx->regs + VIDINTCON0);
1038 val &= ~(VIDINTCON0_INT_I80IFDONE | VIDINTCON0_INT_SYSMAINCON);
1039 writel(val, ctx->regs + VIDINTCON0);
1c248b7d 1040
3854fab2
YC		 1041 /* exit triggering mode */
1042 atomic_set(&ctx->triggering, 0);
1043
1044 drm_handle_vblank(ctx->drm_dev, ctx->pipe);
1045 exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe);
1046 } else {
1047 drm_handle_vblank(ctx->drm_dev, ctx->pipe);
1048 exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe);
1049
1050 /* set wait vsync event to zero and wake up queue. */
1051 if (atomic_read(&ctx->wait_vsync_event)) {
1052 atomic_set(&ctx->wait_vsync_event, 0);
1053 wake_up(&ctx->wait_vsync_queue);
1054 }
01ce113c 1055 }
3854fab2 1056
ec05da95 1057out:
1c248b7d
ID		 1058 return IRQ_HANDLED;
1059}
1060
f37cd5e8 1061static int fimd_bind(struct device *dev, struct device *master, void *data)
562ad9f4 1062{
000cc920 1063 struct fimd_context *ctx = fimd_manager.ctx;
f37cd5e8 1064 struct drm_device *drm_dev = data;
000cc920
AH		 1065
1066 fimd_mgr_initialize(&fimd_manager, drm_dev);
1067 exynos_drm_crtc_create(&fimd_manager);
1068 if (ctx->display)
1069 exynos_drm_create_enc_conn(drm_dev, ctx->display);
1070
000cc920
AH		 1071 return 0;
1072
1073}
1074
1075static void fimd_unbind(struct device *dev, struct device *master,
1076 void *data)
1077{
1078 struct exynos_drm_manager *mgr = dev_get_drvdata(dev);
1079 struct fimd_context *ctx = fimd_manager.ctx;
000cc920
AH		 1080
1081 fimd_dpms(mgr, DRM_MODE_DPMS_OFF);
1082
1083 if (ctx->display)
1084 exynos_dpi_remove(dev);
1085
1086 fimd_mgr_remove(mgr);
000cc920
AH		 1087}
1088
1089static const struct component_ops fimd_component_ops = {
1090 .bind = fimd_bind,
1091 .unbind = fimd_unbind,
1092};
1093
1094static int fimd_probe(struct platform_device *pdev)
1095{
1096 struct device *dev = &pdev->dev;
562ad9f4 1097 struct fimd_context *ctx;
3854fab2 1098 struct device_node *i80_if_timings;
562ad9f4 1099 struct resource *res;
562ad9f4 1100 int ret = -EINVAL;
1c248b7d 1101
df5225bc
ID		 1102 ret = exynos_drm_component_add(&pdev->dev, EXYNOS_DEVICE_TYPE_CRTC,
1103 fimd_manager.type);
1104 if (ret)
1105 return ret;
1106
1107 if (!dev->of_node) {
1108 ret = -ENODEV;
1109 goto err_del_component;
1110 }
2d3f173c 1111
d873ab99 1112 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
df5225bc
ID		 1113 if (!ctx) {
1114 ret = -ENOMEM;
1115 goto err_del_component;
1116 }
1c248b7d 1117
bb7704d6 1118 ctx->dev = dev;
a43b933b 1119 ctx->suspended = true;
3854fab2 1120 ctx->driver_data = drm_fimd_get_driver_data(pdev);
bb7704d6 1121
1417f109
SP		 1122 if (of_property_read_bool(dev->of_node, "samsung,invert-vden"))
1123 ctx->vidcon1 |= VIDCON1_INV_VDEN;
1124 if (of_property_read_bool(dev->of_node, "samsung,invert-vclk"))
1125 ctx->vidcon1 |= VIDCON1_INV_VCLK;
562ad9f4 1126
3854fab2
YC		 1127 i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");
1128 if (i80_if_timings) {
1129 u32 val;
1130
1131 ctx->i80_if = true;
1132
1133 if (ctx->driver_data->has_vidoutcon)
1134 ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0;
1135 else
1136 ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0;
1137 /*
1138 * The user manual describes that this "DSI_EN" bit is required
1139 * to enable I80 24-bit data interface.
1140 */
1141 ctx->vidcon0 |= VIDCON0_DSI_EN;
1142
1143 if (of_property_read_u32(i80_if_timings, "cs-setup", &val))
1144 val = 0;
1145 ctx->i80ifcon = LCD_CS_SETUP(val);
1146 if (of_property_read_u32(i80_if_timings, "wr-setup", &val))
1147 val = 0;
1148 ctx->i80ifcon |= LCD_WR_SETUP(val);
1149 if (of_property_read_u32(i80_if_timings, "wr-active", &val))
1150 val = 1;
1151 ctx->i80ifcon |= LCD_WR_ACTIVE(val);
1152 if (of_property_read_u32(i80_if_timings, "wr-hold", &val))
1153 val = 0;
1154 ctx->i80ifcon |= LCD_WR_HOLD(val);
1155 }
1156 of_node_put(i80_if_timings);
1157
1158 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
1159 "samsung,sysreg");
1160 if (IS_ERR(ctx->sysreg)) {
1161 dev_warn(dev, "failed to get system register.\n");
1162 ctx->sysreg = NULL;
1163 }
1164
a968e727
SP		 1165 ctx->bus_clk = devm_clk_get(dev, "fimd");
1166 if (IS_ERR(ctx->bus_clk)) {
1167 dev_err(dev, "failed to get bus clock\n");
df5225bc
ID		 1168 ret = PTR_ERR(ctx->bus_clk);
1169 goto err_del_component;
a968e727
SP		 1170 }
1171
1172 ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd");
1173 if (IS_ERR(ctx->lcd_clk)) {
1174 dev_err(dev, "failed to get lcd clock\n");
df5225bc
ID		 1175 ret = PTR_ERR(ctx->lcd_clk);
1176 goto err_del_component;
a968e727 1177 }
1c248b7d 1178
1c248b7d 1179 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1c248b7d 1180
d873ab99 1181 ctx->regs = devm_ioremap_resource(dev, res);
df5225bc
ID		 1182 if (IS_ERR(ctx->regs)) {
1183 ret = PTR_ERR(ctx->regs);
1184 goto err_del_component;
1185 }
1c248b7d 1186
3854fab2
YC		 1187 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1188 ctx->i80_if ? "lcd_sys" : "vsync");
1c248b7d
ID		 1189 if (!res) {
1190 dev_err(dev, "irq request failed.\n");
df5225bc
ID		 1191 ret = -ENXIO;
1192 goto err_del_component;
1c248b7d
ID		 1193 }
1194
055e0c06 1195 ret = devm_request_irq(dev, res->start, fimd_irq_handler,
edc57266
SK		 1196 0, "drm_fimd", ctx);
1197 if (ret) {
1c248b7d 1198 dev_err(dev, "irq request failed.\n");
df5225bc 1199 goto err_del_component;
1c248b7d
ID		 1200 }
1201
57ed0f7b 1202 init_waitqueue_head(&ctx->wait_vsync_queue);
01ce113c 1203 atomic_set(&ctx->wait_vsync_event, 0);
1c248b7d 1204
bb7704d6 1205 platform_set_drvdata(pdev, &fimd_manager);
c32b06ef 1206
080be03d 1207 fimd_manager.ctx = ctx;
14b6873a 1208
000cc920
AH		 1209 ctx->display = exynos_dpi_probe(dev);
1210 if (IS_ERR(ctx->display))
1211 return PTR_ERR(ctx->display);
f37cd5e8
ID		 1212
1213 pm_runtime_enable(&pdev->dev);
1214
df5225bc
ID		 1215 ret = component_add(&pdev->dev, &fimd_component_ops);
1216 if (ret)
1217 goto err_disable_pm_runtime;
1218
1219 return ret;
1220
1221err_disable_pm_runtime:
1222 pm_runtime_disable(&pdev->dev);
1223
1224err_del_component:
1225 exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CRTC);
1226 return ret;
f37cd5e8 1227}
cb91f6a0 1228
f37cd5e8
ID		 1229static int fimd_remove(struct platform_device *pdev)
1230{
af65c804 1231 pm_runtime_disable(&pdev->dev);
5d55393a 1232
df5225bc
ID		 1233 component_del(&pdev->dev, &fimd_component_ops);
1234 exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CRTC);
1235
5d55393a 1236 return 0;
e30d4bcf
ID		 1237}
1238
132a5b91 1239struct platform_driver fimd_driver = {
1c248b7d 1240 .probe = fimd_probe,
56550d94 1241 .remove = fimd_remove,
1c248b7d
ID		 1242 .driver = {
1243 .name = "exynos4-fb",
1244 .owner = THIS_MODULE,
2d3f173c 1245 .of_match_table = fimd_driver_dt_match,
1c248b7d
ID		 1246 },
1247};
Linux 6.x block layer and io_uring tree(s)