Commit | Line | Data |
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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
1c248b7d ID |
2 | /* exynos_drm_fimd.c |
3 | * | |
4 | * Copyright (C) 2011 Samsung Electronics Co.Ltd | |
5 | * Authors: | |
6 | * Joonyoung Shim <jy0922.shim@samsung.com> | |
7 | * Inki Dae <inki.dae@samsung.com> | |
1c248b7d | 8 | */ |
1c248b7d | 9 | |
1c248b7d | 10 | #include <linux/clk.h> |
2bda34d7 SR |
11 | #include <linux/component.h> |
12 | #include <linux/kernel.h> | |
13 | #include <linux/mfd/syscon.h> | |
3f1c781d | 14 | #include <linux/of.h> |
2bda34d7 | 15 | #include <linux/platform_device.h> |
cb91f6a0 | 16 | #include <linux/pm_runtime.h> |
3854fab2 | 17 | #include <linux/regmap.h> |
1c248b7d | 18 | |
7f4596f4 | 19 | #include <video/of_display_timing.h> |
111e6055 | 20 | #include <video/of_videomode.h> |
5a213a55 | 21 | #include <video/samsung_fimd.h> |
2bda34d7 | 22 | |
90bb087f | 23 | #include <drm/drm_blend.h> |
2bda34d7 | 24 | #include <drm/drm_fourcc.h> |
720cf96d | 25 | #include <drm/drm_framebuffer.h> |
2bda34d7 | 26 | #include <drm/drm_vblank.h> |
1c248b7d | 27 | #include <drm/exynos_drm.h> |
1c248b7d | 28 | |
2bda34d7 | 29 | #include "exynos_drm_crtc.h" |
1c248b7d | 30 | #include "exynos_drm_drv.h" |
0488f50e | 31 | #include "exynos_drm_fb.h" |
7ee14cdc | 32 | #include "exynos_drm_plane.h" |
1c248b7d ID |
33 | |
34 | /* | |
b8654b37 | 35 | * FIMD stands for Fully Interactive Mobile Display and |
1c248b7d ID |
36 | * as a display controller, it transfers contents drawn on memory |
37 | * to a LCD Panel through Display Interfaces such as RGB or | |
38 | * CPU Interface. | |
39 | */ | |
40 | ||
66367461 | 41 | #define MIN_FB_WIDTH_FOR_16WORD_BURST 128 |
111e6055 | 42 | |
1c248b7d ID |
43 | /* position control register for hardware window 0, 2 ~ 4.*/ |
44 | #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16) | |
45 | #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16) | |
0f10cf14 LKA |
46 | /* |
47 | * size control register for hardware windows 0 and alpha control register | |
48 | * for hardware windows 1 ~ 4 | |
49 | */ | |
50 | #define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16) | |
51 | /* size control register for hardware windows 1 ~ 2. */ | |
1c248b7d ID |
52 | #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16) |
53 | ||
453b44a3 GP |
54 | #define VIDWnALPHA0(win) (VIDW_ALPHA + 0x00 + (win) * 8) |
55 | #define VIDWnALPHA1(win) (VIDW_ALPHA + 0x04 + (win) * 8) | |
56 | ||
1c248b7d | 57 | #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8) |
cb11b3f1 | 58 | #define VIDWx_BUF_START_S(win, buf) (VIDW_BUF_START_S(buf) + (win) * 8) |
1c248b7d ID |
59 | #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8) |
60 | #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4) | |
61 | ||
62 | /* color key control register for hardware window 1 ~ 4. */ | |
0f10cf14 | 63 | #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8)) |
1c248b7d | 64 | /* color key value register for hardware window 1 ~ 4. */ |
0f10cf14 | 65 | #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8)) |
1c248b7d | 66 | |
b5bf0f1e | 67 | /* I80 trigger control register */ |
3854fab2 | 68 | #define TRIGCON 0x1A4 |
b5bf0f1e ID |
69 | #define TRGMODE_ENABLE (1 << 0) |
70 | #define SWTRGCMD_ENABLE (1 << 1) | |
6bdc92ee | 71 | /* Exynos3250, 3472, 5260 5410, 5420 and 5422 only supported. */ |
b5bf0f1e ID |
72 | #define HWTRGEN_ENABLE (1 << 3) |
73 | #define HWTRGMASK_ENABLE (1 << 4) | |
6bdc92ee | 74 | /* Exynos3250, 3472, 5260, 5420 and 5422 only supported. */ |
b5bf0f1e | 75 | #define HWTRIGEN_PER_ENABLE (1 << 31) |
3854fab2 YC |
76 | |
77 | /* display mode change control register except exynos4 */ | |
78 | #define VIDOUT_CON 0x000 | |
79 | #define VIDOUT_CON_F_I80_LDI0 (0x2 << 8) | |
80 | ||
81 | /* I80 interface control for main LDI register */ | |
82 | #define I80IFCONFAx(x) (0x1B0 + (x) * 4) | |
83 | #define I80IFCONFBx(x) (0x1B8 + (x) * 4) | |
84 | #define LCD_CS_SETUP(x) ((x) << 16) | |
85 | #define LCD_WR_SETUP(x) ((x) << 12) | |
86 | #define LCD_WR_ACTIVE(x) ((x) << 8) | |
87 | #define LCD_WR_HOLD(x) ((x) << 4) | |
88 | #define I80IFEN_ENABLE (1 << 0) | |
89 | ||
1c248b7d ID |
90 | /* FIMD has totally five hardware windows. */ |
91 | #define WINDOWS_NR 5 | |
92 | ||
a6f75aa1 ID |
93 | /* HW trigger flag on i80 panel. */ |
94 | #define I80_HW_TRG (1 << 1) | |
95 | ||
e2e13389 LKA |
96 | struct fimd_driver_data { |
97 | unsigned int timing_base; | |
3854fab2 YC |
98 | unsigned int lcdblk_offset; |
99 | unsigned int lcdblk_vt_shift; | |
100 | unsigned int lcdblk_bypass_shift; | |
1feafd3a | 101 | unsigned int lcdblk_mic_bypass_shift; |
a6f75aa1 | 102 | unsigned int trg_type; |
de7af100 TF |
103 | |
104 | unsigned int has_shadowcon:1; | |
411d9ed4 | 105 | unsigned int has_clksel:1; |
5cc4621a | 106 | unsigned int has_limited_fmt:1; |
3854fab2 | 107 | unsigned int has_vidoutcon:1; |
3c3c9c1d | 108 | unsigned int has_vtsel:1; |
1feafd3a | 109 | unsigned int has_mic_bypass:1; |
196e059a | 110 | unsigned int has_dp_clk:1; |
a6f75aa1 ID |
111 | unsigned int has_hw_trigger:1; |
112 | unsigned int has_trigger_per_te:1; | |
2d684f4e | 113 | unsigned int has_bgr_support:1; |
e2e13389 LKA |
114 | }; |
115 | ||
725ddead TF |
116 | static struct fimd_driver_data s3c64xx_fimd_driver_data = { |
117 | .timing_base = 0x0, | |
118 | .has_clksel = 1, | |
5cc4621a | 119 | .has_limited_fmt = 1, |
725ddead TF |
120 | }; |
121 | ||
fa50b7b4 TF |
122 | static struct fimd_driver_data s5pv210_fimd_driver_data = { |
123 | .timing_base = 0x0, | |
124 | .has_shadowcon = 1, | |
125 | .has_clksel = 1, | |
126 | }; | |
127 | ||
d6ce7b58 ID |
128 | static struct fimd_driver_data exynos3_fimd_driver_data = { |
129 | .timing_base = 0x20000, | |
130 | .lcdblk_offset = 0x210, | |
131 | .lcdblk_bypass_shift = 1, | |
132 | .has_shadowcon = 1, | |
133 | .has_vidoutcon = 1, | |
134 | }; | |
135 | ||
6ecf18f9 | 136 | static struct fimd_driver_data exynos4_fimd_driver_data = { |
e2e13389 | 137 | .timing_base = 0x0, |
3854fab2 YC |
138 | .lcdblk_offset = 0x210, |
139 | .lcdblk_vt_shift = 10, | |
140 | .lcdblk_bypass_shift = 1, | |
de7af100 | 141 | .has_shadowcon = 1, |
3c3c9c1d | 142 | .has_vtsel = 1, |
2d684f4e | 143 | .has_bgr_support = 1, |
e2e13389 LKA |
144 | }; |
145 | ||
6ecf18f9 | 146 | static struct fimd_driver_data exynos5_fimd_driver_data = { |
e2e13389 | 147 | .timing_base = 0x20000, |
3854fab2 YC |
148 | .lcdblk_offset = 0x214, |
149 | .lcdblk_vt_shift = 24, | |
150 | .lcdblk_bypass_shift = 15, | |
de7af100 | 151 | .has_shadowcon = 1, |
3854fab2 | 152 | .has_vidoutcon = 1, |
3c3c9c1d | 153 | .has_vtsel = 1, |
196e059a | 154 | .has_dp_clk = 1, |
2d684f4e | 155 | .has_bgr_support = 1, |
e2e13389 LKA |
156 | }; |
157 | ||
1feafd3a CP |
158 | static struct fimd_driver_data exynos5420_fimd_driver_data = { |
159 | .timing_base = 0x20000, | |
160 | .lcdblk_offset = 0x214, | |
161 | .lcdblk_vt_shift = 24, | |
162 | .lcdblk_bypass_shift = 15, | |
163 | .lcdblk_mic_bypass_shift = 11, | |
164 | .has_shadowcon = 1, | |
165 | .has_vidoutcon = 1, | |
166 | .has_vtsel = 1, | |
167 | .has_mic_bypass = 1, | |
196e059a | 168 | .has_dp_clk = 1, |
2d684f4e | 169 | .has_bgr_support = 1, |
1feafd3a CP |
170 | }; |
171 | ||
1c248b7d | 172 | struct fimd_context { |
bb7704d6 | 173 | struct device *dev; |
40c8ab4b | 174 | struct drm_device *drm_dev; |
07dc3678 | 175 | void *dma_priv; |
93bca243 | 176 | struct exynos_drm_crtc *crtc; |
7ee14cdc | 177 | struct exynos_drm_plane planes[WINDOWS_NR]; |
fd2d2fc2 | 178 | struct exynos_drm_plane_config configs[WINDOWS_NR]; |
1c248b7d ID |
179 | struct clk *bus_clk; |
180 | struct clk *lcd_clk; | |
1c248b7d | 181 | void __iomem *regs; |
3854fab2 | 182 | struct regmap *sysreg; |
1c248b7d | 183 | unsigned long irq_flags; |
3854fab2 | 184 | u32 vidcon0; |
1c248b7d | 185 | u32 vidcon1; |
3854fab2 YC |
186 | u32 vidout_con; |
187 | u32 i80ifcon; | |
188 | bool i80_if; | |
cb91f6a0 | 189 | bool suspended; |
01ce113c P |
190 | wait_queue_head_t wait_vsync_queue; |
191 | atomic_t wait_vsync_event; | |
3854fab2 YC |
192 | atomic_t win_updated; |
193 | atomic_t triggering; | |
c96fdfde | 194 | u32 clkdiv; |
1c248b7d | 195 | |
e1a7b9b4 | 196 | const struct fimd_driver_data *driver_data; |
2b8376c8 | 197 | struct drm_encoder *encoder; |
196e059a | 198 | struct exynos_drm_clk dp_clk; |
1c248b7d ID |
199 | }; |
200 | ||
d636ead8 | 201 | static const struct of_device_id fimd_driver_dt_match[] = { |
725ddead TF |
202 | { .compatible = "samsung,s3c6400-fimd", |
203 | .data = &s3c64xx_fimd_driver_data }, | |
fa50b7b4 TF |
204 | { .compatible = "samsung,s5pv210-fimd", |
205 | .data = &s5pv210_fimd_driver_data }, | |
d6ce7b58 ID |
206 | { .compatible = "samsung,exynos3250-fimd", |
207 | .data = &exynos3_fimd_driver_data }, | |
5830daf8 | 208 | { .compatible = "samsung,exynos4210-fimd", |
d636ead8 | 209 | .data = &exynos4_fimd_driver_data }, |
5830daf8 | 210 | { .compatible = "samsung,exynos5250-fimd", |
d636ead8 | 211 | .data = &exynos5_fimd_driver_data }, |
1feafd3a CP |
212 | { .compatible = "samsung,exynos5420-fimd", |
213 | .data = &exynos5420_fimd_driver_data }, | |
d636ead8 JS |
214 | {}, |
215 | }; | |
0262ceeb | 216 | MODULE_DEVICE_TABLE(of, fimd_driver_dt_match); |
d636ead8 | 217 | |
fd2d2fc2 MS |
218 | static const enum drm_plane_type fimd_win_types[WINDOWS_NR] = { |
219 | DRM_PLANE_TYPE_PRIMARY, | |
220 | DRM_PLANE_TYPE_OVERLAY, | |
221 | DRM_PLANE_TYPE_OVERLAY, | |
222 | DRM_PLANE_TYPE_OVERLAY, | |
223 | DRM_PLANE_TYPE_CURSOR, | |
224 | }; | |
225 | ||
fbbb1e1a MS |
226 | static const uint32_t fimd_formats[] = { |
227 | DRM_FORMAT_C8, | |
228 | DRM_FORMAT_XRGB1555, | |
229 | DRM_FORMAT_RGB565, | |
230 | DRM_FORMAT_XRGB8888, | |
231 | DRM_FORMAT_ARGB8888, | |
232 | }; | |
233 | ||
2d684f4e MJ |
234 | static const uint32_t fimd_extended_formats[] = { |
235 | DRM_FORMAT_C8, | |
236 | DRM_FORMAT_XRGB1555, | |
237 | DRM_FORMAT_XBGR1555, | |
238 | DRM_FORMAT_RGB565, | |
239 | DRM_FORMAT_BGR565, | |
240 | DRM_FORMAT_XRGB8888, | |
241 | DRM_FORMAT_XBGR8888, | |
242 | DRM_FORMAT_ARGB8888, | |
243 | DRM_FORMAT_ABGR8888, | |
244 | }; | |
245 | ||
6f8ee5c2 CM |
246 | static const unsigned int capabilities[WINDOWS_NR] = { |
247 | 0, | |
3b5129b3 CM |
248 | EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND, |
249 | EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND, | |
250 | EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND, | |
251 | EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND, | |
6f8ee5c2 CM |
252 | }; |
253 | ||
254 | static inline void fimd_set_bits(struct fimd_context *ctx, u32 reg, u32 mask, | |
255 | u32 val) | |
256 | { | |
257 | val = (val & mask) | (readl(ctx->regs + reg) & ~mask); | |
258 | writel(val, ctx->regs + reg); | |
259 | } | |
260 | ||
fb88e214 MS |
261 | static int fimd_enable_vblank(struct exynos_drm_crtc *crtc) |
262 | { | |
263 | struct fimd_context *ctx = crtc->ctx; | |
264 | u32 val; | |
265 | ||
266 | if (ctx->suspended) | |
267 | return -EPERM; | |
268 | ||
269 | if (!test_and_set_bit(0, &ctx->irq_flags)) { | |
270 | val = readl(ctx->regs + VIDINTCON0); | |
271 | ||
272 | val |= VIDINTCON0_INT_ENABLE; | |
273 | ||
274 | if (ctx->i80_if) { | |
275 | val |= VIDINTCON0_INT_I80IFDONE; | |
276 | val |= VIDINTCON0_INT_SYSMAINCON; | |
277 | val &= ~VIDINTCON0_INT_SYSSUBCON; | |
278 | } else { | |
279 | val |= VIDINTCON0_INT_FRAME; | |
280 | ||
281 | val &= ~VIDINTCON0_FRAMESEL0_MASK; | |
82a01783 | 282 | val |= VIDINTCON0_FRAMESEL0_FRONTPORCH; |
fb88e214 MS |
283 | val &= ~VIDINTCON0_FRAMESEL1_MASK; |
284 | val |= VIDINTCON0_FRAMESEL1_NONE; | |
285 | } | |
286 | ||
287 | writel(val, ctx->regs + VIDINTCON0); | |
288 | } | |
289 | ||
290 | return 0; | |
291 | } | |
292 | ||
293 | static void fimd_disable_vblank(struct exynos_drm_crtc *crtc) | |
294 | { | |
295 | struct fimd_context *ctx = crtc->ctx; | |
296 | u32 val; | |
297 | ||
298 | if (ctx->suspended) | |
299 | return; | |
300 | ||
301 | if (test_and_clear_bit(0, &ctx->irq_flags)) { | |
302 | val = readl(ctx->regs + VIDINTCON0); | |
303 | ||
304 | val &= ~VIDINTCON0_INT_ENABLE; | |
305 | ||
306 | if (ctx->i80_if) { | |
307 | val &= ~VIDINTCON0_INT_I80IFDONE; | |
308 | val &= ~VIDINTCON0_INT_SYSMAINCON; | |
309 | val &= ~VIDINTCON0_INT_SYSSUBCON; | |
310 | } else | |
311 | val &= ~VIDINTCON0_INT_FRAME; | |
312 | ||
313 | writel(val, ctx->regs + VIDINTCON0); | |
314 | } | |
315 | } | |
316 | ||
93bca243 | 317 | static void fimd_wait_for_vblank(struct exynos_drm_crtc *crtc) |
f13bdbd1 | 318 | { |
93bca243 | 319 | struct fimd_context *ctx = crtc->ctx; |
f13bdbd1 AA |
320 | |
321 | if (ctx->suspended) | |
322 | return; | |
323 | ||
324 | atomic_set(&ctx->wait_vsync_event, 1); | |
325 | ||
326 | /* | |
327 | * wait for FIMD to signal VSYNC interrupt or return after | |
328 | * timeout which is set to 50ms (refresh rate of 20). | |
329 | */ | |
330 | if (!wait_event_timeout(ctx->wait_vsync_queue, | |
331 | !atomic_read(&ctx->wait_vsync_event), | |
332 | HZ/20)) | |
6be90056 | 333 | DRM_DEV_DEBUG_KMS(ctx->dev, "vblank wait timed out.\n"); |
f13bdbd1 AA |
334 | } |
335 | ||
5b1d5bc6 | 336 | static void fimd_enable_video_output(struct fimd_context *ctx, unsigned int win, |
f181a543 YC |
337 | bool enable) |
338 | { | |
339 | u32 val = readl(ctx->regs + WINCON(win)); | |
340 | ||
341 | if (enable) | |
342 | val |= WINCONx_ENWIN; | |
343 | else | |
344 | val &= ~WINCONx_ENWIN; | |
345 | ||
346 | writel(val, ctx->regs + WINCON(win)); | |
347 | } | |
348 | ||
5b1d5bc6 TJ |
349 | static void fimd_enable_shadow_channel_path(struct fimd_context *ctx, |
350 | unsigned int win, | |
999d8b31 YC |
351 | bool enable) |
352 | { | |
353 | u32 val = readl(ctx->regs + SHADOWCON); | |
354 | ||
355 | if (enable) | |
356 | val |= SHADOWCON_CHx_ENABLE(win); | |
357 | else | |
358 | val &= ~SHADOWCON_CHx_ENABLE(win); | |
359 | ||
360 | writel(val, ctx->regs + SHADOWCON); | |
361 | } | |
362 | ||
445d3bed | 363 | static int fimd_clear_channels(struct exynos_drm_crtc *crtc) |
f13bdbd1 | 364 | { |
fc2e013f | 365 | struct fimd_context *ctx = crtc->ctx; |
5b1d5bc6 | 366 | unsigned int win, ch_enabled = 0; |
445d3bed | 367 | int ret; |
f13bdbd1 | 368 | |
fb88e214 | 369 | /* Hardware is in unknown state, so ensure it gets enabled properly */ |
445d3bed ID |
370 | ret = pm_runtime_resume_and_get(ctx->dev); |
371 | if (ret < 0) { | |
372 | dev_err(ctx->dev, "failed to enable FIMD device.\n"); | |
373 | return ret; | |
374 | } | |
fb88e214 MS |
375 | |
376 | clk_prepare_enable(ctx->bus_clk); | |
377 | clk_prepare_enable(ctx->lcd_clk); | |
378 | ||
f13bdbd1 AA |
379 | /* Check if any channel is enabled. */ |
380 | for (win = 0; win < WINDOWS_NR; win++) { | |
eb8a3bf7 MS |
381 | u32 val = readl(ctx->regs + WINCON(win)); |
382 | ||
383 | if (val & WINCONx_ENWIN) { | |
f181a543 | 384 | fimd_enable_video_output(ctx, win, false); |
eb8a3bf7 | 385 | |
999d8b31 YC |
386 | if (ctx->driver_data->has_shadowcon) |
387 | fimd_enable_shadow_channel_path(ctx, win, | |
388 | false); | |
389 | ||
f13bdbd1 AA |
390 | ch_enabled = 1; |
391 | } | |
392 | } | |
393 | ||
394 | /* Wait for vsync, as disable channel takes effect at next vsync */ | |
eb8a3bf7 | 395 | if (ch_enabled) { |
fb88e214 | 396 | ctx->suspended = false; |
eb8a3bf7 | 397 | |
fb88e214 | 398 | fimd_enable_vblank(ctx->crtc); |
92dc7a04 | 399 | fimd_wait_for_vblank(ctx->crtc); |
fb88e214 MS |
400 | fimd_disable_vblank(ctx->crtc); |
401 | ||
402 | ctx->suspended = true; | |
eb8a3bf7 | 403 | } |
fb88e214 MS |
404 | |
405 | clk_disable_unprepare(ctx->lcd_clk); | |
406 | clk_disable_unprepare(ctx->bus_clk); | |
407 | ||
408 | pm_runtime_put(ctx->dev); | |
445d3bed ID |
409 | |
410 | return 0; | |
f13bdbd1 AA |
411 | } |
412 | ||
c96fdfde AH |
413 | |
414 | static int fimd_atomic_check(struct exynos_drm_crtc *crtc, | |
415 | struct drm_crtc_state *state) | |
a968e727 | 416 | { |
c96fdfde AH |
417 | struct drm_display_mode *mode = &state->adjusted_mode; |
418 | struct fimd_context *ctx = crtc->ctx; | |
419 | unsigned long ideal_clk, lcd_rate; | |
a968e727 SP |
420 | u32 clkdiv; |
421 | ||
fa9971d6 | 422 | if (mode->clock == 0) { |
6f83d208 | 423 | DRM_DEV_ERROR(ctx->dev, "Mode has zero clock value.\n"); |
c96fdfde | 424 | return -EINVAL; |
fa9971d6 TJ |
425 | } |
426 | ||
427 | ideal_clk = mode->clock * 1000; | |
428 | ||
3854fab2 YC |
429 | if (ctx->i80_if) { |
430 | /* | |
431 | * The frame done interrupt should be occurred prior to the | |
432 | * next TE signal. | |
433 | */ | |
434 | ideal_clk *= 2; | |
435 | } | |
436 | ||
c96fdfde AH |
437 | lcd_rate = clk_get_rate(ctx->lcd_clk); |
438 | if (2 * lcd_rate < ideal_clk) { | |
6f83d208 ID |
439 | DRM_DEV_ERROR(ctx->dev, |
440 | "sclk_fimd clock too low(%lu) for requested pixel clock(%lu)\n", | |
441 | lcd_rate, ideal_clk); | |
c96fdfde AH |
442 | return -EINVAL; |
443 | } | |
444 | ||
a968e727 | 445 | /* Find the clock divider value that gets us closest to ideal_clk */ |
c96fdfde AH |
446 | clkdiv = DIV_ROUND_CLOSEST(lcd_rate, ideal_clk); |
447 | if (clkdiv >= 0x200) { | |
6f83d208 ID |
448 | DRM_DEV_ERROR(ctx->dev, "requested pixel clock(%lu) too low\n", |
449 | ideal_clk); | |
c96fdfde AH |
450 | return -EINVAL; |
451 | } | |
452 | ||
453 | ctx->clkdiv = (clkdiv < 0x100) ? clkdiv : 0xff; | |
a968e727 | 454 | |
c96fdfde | 455 | return 0; |
a968e727 SP |
456 | } |
457 | ||
a6f75aa1 ID |
458 | static void fimd_setup_trigger(struct fimd_context *ctx) |
459 | { | |
460 | void __iomem *timing_base = ctx->regs + ctx->driver_data->timing_base; | |
461 | u32 trg_type = ctx->driver_data->trg_type; | |
462 | u32 val = readl(timing_base + TRIGCON); | |
463 | ||
b5bf0f1e | 464 | val &= ~(TRGMODE_ENABLE); |
a6f75aa1 ID |
465 | |
466 | if (trg_type == I80_HW_TRG) { | |
467 | if (ctx->driver_data->has_hw_trigger) | |
b5bf0f1e | 468 | val |= HWTRGEN_ENABLE | HWTRGMASK_ENABLE; |
a6f75aa1 | 469 | if (ctx->driver_data->has_trigger_per_te) |
b5bf0f1e | 470 | val |= HWTRIGEN_PER_ENABLE; |
a6f75aa1 | 471 | } else { |
b5bf0f1e | 472 | val |= TRGMODE_ENABLE; |
a6f75aa1 ID |
473 | } |
474 | ||
475 | writel(val, timing_base + TRIGCON); | |
476 | } | |
477 | ||
93bca243 | 478 | static void fimd_commit(struct exynos_drm_crtc *crtc) |
1c248b7d | 479 | { |
93bca243 | 480 | struct fimd_context *ctx = crtc->ctx; |
020e79de | 481 | struct drm_display_mode *mode = &crtc->base.state->adjusted_mode; |
e1a7b9b4 | 482 | const struct fimd_driver_data *driver_data = ctx->driver_data; |
477552e1 | 483 | void __iomem *timing_base = ctx->regs + driver_data->timing_base; |
c96fdfde | 484 | u32 val; |
1c248b7d | 485 | |
e30d4bcf ID |
486 | if (ctx->suspended) |
487 | return; | |
488 | ||
a968e727 SP |
489 | /* nothing to do if we haven't set the mode yet */ |
490 | if (mode->htotal == 0 || mode->vtotal == 0) | |
491 | return; | |
492 | ||
3854fab2 YC |
493 | if (ctx->i80_if) { |
494 | val = ctx->i80ifcon | I80IFEN_ENABLE; | |
495 | writel(val, timing_base + I80IFCONFAx(0)); | |
496 | ||
497 | /* disable auto frame rate */ | |
498 | writel(0, timing_base + I80IFCONFBx(0)); | |
499 | ||
500 | /* set video type selection to I80 interface */ | |
3c3c9c1d JS |
501 | if (driver_data->has_vtsel && ctx->sysreg && |
502 | regmap_update_bits(ctx->sysreg, | |
3854fab2 YC |
503 | driver_data->lcdblk_offset, |
504 | 0x3 << driver_data->lcdblk_vt_shift, | |
505 | 0x1 << driver_data->lcdblk_vt_shift)) { | |
6f83d208 ID |
506 | DRM_DEV_ERROR(ctx->dev, |
507 | "Failed to update sysreg for I80 i/f.\n"); | |
3854fab2 YC |
508 | return; |
509 | } | |
510 | } else { | |
511 | int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd; | |
512 | u32 vidcon1; | |
513 | ||
514 | /* setup polarity values */ | |
515 | vidcon1 = ctx->vidcon1; | |
516 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
517 | vidcon1 |= VIDCON1_INV_VSYNC; | |
518 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
519 | vidcon1 |= VIDCON1_INV_HSYNC; | |
520 | writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1); | |
521 | ||
522 | /* setup vertical timing values. */ | |
523 | vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; | |
524 | vbpd = mode->crtc_vtotal - mode->crtc_vsync_end; | |
525 | vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay; | |
526 | ||
527 | val = VIDTCON0_VBPD(vbpd - 1) | | |
528 | VIDTCON0_VFPD(vfpd - 1) | | |
529 | VIDTCON0_VSPW(vsync_len - 1); | |
530 | writel(val, ctx->regs + driver_data->timing_base + VIDTCON0); | |
531 | ||
532 | /* setup horizontal timing values. */ | |
533 | hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; | |
534 | hbpd = mode->crtc_htotal - mode->crtc_hsync_end; | |
535 | hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay; | |
536 | ||
537 | val = VIDTCON1_HBPD(hbpd - 1) | | |
538 | VIDTCON1_HFPD(hfpd - 1) | | |
539 | VIDTCON1_HSPW(hsync_len - 1); | |
540 | writel(val, ctx->regs + driver_data->timing_base + VIDTCON1); | |
541 | } | |
542 | ||
543 | if (driver_data->has_vidoutcon) | |
544 | writel(ctx->vidout_con, timing_base + VIDOUT_CON); | |
545 | ||
546 | /* set bypass selection */ | |
547 | if (ctx->sysreg && regmap_update_bits(ctx->sysreg, | |
548 | driver_data->lcdblk_offset, | |
549 | 0x1 << driver_data->lcdblk_bypass_shift, | |
550 | 0x1 << driver_data->lcdblk_bypass_shift)) { | |
6f83d208 ID |
551 | DRM_DEV_ERROR(ctx->dev, |
552 | "Failed to update sysreg for bypass setting.\n"); | |
3854fab2 YC |
553 | return; |
554 | } | |
1c248b7d | 555 | |
1feafd3a CP |
556 | /* TODO: When MIC is enabled for display path, the lcdblk_mic_bypass |
557 | * bit should be cleared. | |
558 | */ | |
559 | if (driver_data->has_mic_bypass && ctx->sysreg && | |
560 | regmap_update_bits(ctx->sysreg, | |
561 | driver_data->lcdblk_offset, | |
562 | 0x1 << driver_data->lcdblk_mic_bypass_shift, | |
563 | 0x1 << driver_data->lcdblk_mic_bypass_shift)) { | |
6f83d208 ID |
564 | DRM_DEV_ERROR(ctx->dev, |
565 | "Failed to update sysreg for bypass mic.\n"); | |
1feafd3a CP |
566 | return; |
567 | } | |
568 | ||
1c248b7d | 569 | /* setup horizontal and vertical display size. */ |
a968e727 SP |
570 | val = VIDTCON2_LINEVAL(mode->vdisplay - 1) | |
571 | VIDTCON2_HOZVAL(mode->hdisplay - 1) | | |
572 | VIDTCON2_LINEVAL_E(mode->vdisplay - 1) | | |
573 | VIDTCON2_HOZVAL_E(mode->hdisplay - 1); | |
e2e13389 | 574 | writel(val, ctx->regs + driver_data->timing_base + VIDTCON2); |
1c248b7d | 575 | |
a6f75aa1 ID |
576 | fimd_setup_trigger(ctx); |
577 | ||
1d531062 AH |
578 | /* |
579 | * fields of register with prefix '_F' would be updated | |
580 | * at vsync(same as dma start) | |
581 | */ | |
3854fab2 YC |
582 | val = ctx->vidcon0; |
583 | val |= VIDCON0_ENVID | VIDCON0_ENVID_F; | |
1c248b7d | 584 | |
1d531062 | 585 | if (ctx->driver_data->has_clksel) |
411d9ed4 | 586 | val |= VIDCON0_CLKSEL_LCD; |
411d9ed4 | 587 | |
c96fdfde AH |
588 | if (ctx->clkdiv > 1) |
589 | val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR; | |
1c248b7d | 590 | |
1c248b7d ID |
591 | writel(val, ctx->regs + VIDCON0); |
592 | } | |
593 | ||
3b5129b3 CM |
594 | static void fimd_win_set_bldeq(struct fimd_context *ctx, unsigned int win, |
595 | unsigned int alpha, unsigned int pixel_alpha) | |
596 | { | |
597 | u32 mask = BLENDEQ_A_FUNC_F(0xf) | BLENDEQ_B_FUNC_F(0xf); | |
598 | u32 val = 0; | |
599 | ||
600 | switch (pixel_alpha) { | |
601 | case DRM_MODE_BLEND_PIXEL_NONE: | |
602 | case DRM_MODE_BLEND_COVERAGE: | |
603 | val |= BLENDEQ_A_FUNC_F(BLENDEQ_ALPHA_A); | |
604 | val |= BLENDEQ_B_FUNC_F(BLENDEQ_ONE_MINUS_ALPHA_A); | |
605 | break; | |
606 | case DRM_MODE_BLEND_PREMULTI: | |
607 | default: | |
608 | if (alpha != DRM_BLEND_ALPHA_OPAQUE) { | |
609 | val |= BLENDEQ_A_FUNC_F(BLENDEQ_ALPHA0); | |
610 | val |= BLENDEQ_B_FUNC_F(BLENDEQ_ONE_MINUS_ALPHA_A); | |
611 | } else { | |
612 | val |= BLENDEQ_A_FUNC_F(BLENDEQ_ONE); | |
613 | val |= BLENDEQ_B_FUNC_F(BLENDEQ_ONE_MINUS_ALPHA_A); | |
614 | } | |
615 | break; | |
616 | } | |
617 | fimd_set_bits(ctx, BLENDEQx(win), mask, val); | |
618 | } | |
619 | ||
6f8ee5c2 | 620 | static void fimd_win_set_bldmod(struct fimd_context *ctx, unsigned int win, |
3b5129b3 | 621 | unsigned int alpha, unsigned int pixel_alpha) |
6f8ee5c2 CM |
622 | { |
623 | u32 win_alpha_l = (alpha >> 8) & 0xf; | |
624 | u32 win_alpha_h = alpha >> 12; | |
625 | u32 val = 0; | |
626 | ||
3b5129b3 CM |
627 | switch (pixel_alpha) { |
628 | case DRM_MODE_BLEND_PIXEL_NONE: | |
629 | break; | |
630 | case DRM_MODE_BLEND_COVERAGE: | |
631 | case DRM_MODE_BLEND_PREMULTI: | |
632 | default: | |
633 | val |= WINCON1_ALPHA_SEL; | |
634 | val |= WINCON1_BLD_PIX; | |
635 | val |= WINCON1_ALPHA_MUL; | |
636 | break; | |
637 | } | |
638 | fimd_set_bits(ctx, WINCON(win), WINCONx_BLEND_MODE_MASK, val); | |
639 | ||
6f8ee5c2 CM |
640 | /* OSD alpha */ |
641 | val = VIDISD14C_ALPHA0_R(win_alpha_h) | | |
642 | VIDISD14C_ALPHA0_G(win_alpha_h) | | |
643 | VIDISD14C_ALPHA0_B(win_alpha_h) | | |
644 | VIDISD14C_ALPHA1_R(0x0) | | |
645 | VIDISD14C_ALPHA1_G(0x0) | | |
646 | VIDISD14C_ALPHA1_B(0x0); | |
647 | writel(val, ctx->regs + VIDOSD_C(win)); | |
648 | ||
649 | val = VIDW_ALPHA_R(win_alpha_l) | VIDW_ALPHA_G(win_alpha_l) | | |
650 | VIDW_ALPHA_B(win_alpha_l); | |
651 | writel(val, ctx->regs + VIDWnALPHA0(win)); | |
652 | ||
653 | val = VIDW_ALPHA_R(0x0) | VIDW_ALPHA_G(0x0) | | |
654 | VIDW_ALPHA_B(0x0); | |
655 | writel(val, ctx->regs + VIDWnALPHA1(win)); | |
656 | ||
657 | fimd_set_bits(ctx, BLENDCON, BLENDCON_NEW_MASK, | |
658 | BLENDCON_NEW_8BIT_ALPHA_VALUE); | |
659 | } | |
1c248b7d | 660 | |
2eeb2e5e | 661 | static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win, |
6f8ee5c2 | 662 | struct drm_framebuffer *fb, int width) |
1c248b7d | 663 | { |
960b537e | 664 | struct exynos_drm_plane *plane = &ctx->planes[win]; |
6f8ee5c2 | 665 | struct exynos_drm_plane_state *state = |
960b537e | 666 | to_exynos_plane_state(plane->base.state); |
6f8ee5c2 CM |
667 | uint32_t pixel_format = fb->format->format; |
668 | unsigned int alpha = state->base.alpha; | |
669 | u32 val = WINCONx_ENWIN; | |
3b5129b3 CM |
670 | unsigned int pixel_alpha; |
671 | ||
672 | if (fb->format->has_alpha) | |
673 | pixel_alpha = state->base.pixel_blend_mode; | |
674 | else | |
675 | pixel_alpha = DRM_MODE_BLEND_PIXEL_NONE; | |
1c248b7d | 676 | |
5cc4621a ID |
677 | /* |
678 | * In case of s3c64xx, window 0 doesn't support alpha channel. | |
679 | * So the request format is ARGB8888 then change it to XRGB8888. | |
680 | */ | |
681 | if (ctx->driver_data->has_limited_fmt && !win) { | |
8b704d8a MS |
682 | if (pixel_format == DRM_FORMAT_ARGB8888) |
683 | pixel_format = DRM_FORMAT_XRGB8888; | |
5cc4621a ID |
684 | } |
685 | ||
8b704d8a | 686 | switch (pixel_format) { |
a4f38a80 | 687 | case DRM_FORMAT_C8: |
1c248b7d ID |
688 | val |= WINCON0_BPPMODE_8BPP_PALETTE; |
689 | val |= WINCONx_BURSTLEN_8WORD; | |
690 | val |= WINCONx_BYTSWP; | |
691 | break; | |
a4f38a80 | 692 | case DRM_FORMAT_XRGB1555: |
2d684f4e | 693 | case DRM_FORMAT_XBGR1555: |
a4f38a80 ID |
694 | val |= WINCON0_BPPMODE_16BPP_1555; |
695 | val |= WINCONx_HAWSWP; | |
696 | val |= WINCONx_BURSTLEN_16WORD; | |
697 | break; | |
698 | case DRM_FORMAT_RGB565: | |
2d684f4e | 699 | case DRM_FORMAT_BGR565: |
1c248b7d ID |
700 | val |= WINCON0_BPPMODE_16BPP_565; |
701 | val |= WINCONx_HAWSWP; | |
702 | val |= WINCONx_BURSTLEN_16WORD; | |
703 | break; | |
a4f38a80 | 704 | case DRM_FORMAT_XRGB8888: |
2d684f4e | 705 | case DRM_FORMAT_XBGR8888: |
1c248b7d ID |
706 | val |= WINCON0_BPPMODE_24BPP_888; |
707 | val |= WINCONx_WSWP; | |
708 | val |= WINCONx_BURSTLEN_16WORD; | |
709 | break; | |
a4f38a80 | 710 | case DRM_FORMAT_ARGB8888: |
2d684f4e | 711 | case DRM_FORMAT_ABGR8888: |
5b7b1b7f | 712 | default: |
3b5129b3 | 713 | val |= WINCON1_BPPMODE_25BPP_A1888; |
1c248b7d ID |
714 | val |= WINCONx_WSWP; |
715 | val |= WINCONx_BURSTLEN_16WORD; | |
716 | break; | |
1c248b7d ID |
717 | } |
718 | ||
2d684f4e MJ |
719 | switch (pixel_format) { |
720 | case DRM_FORMAT_XBGR1555: | |
721 | case DRM_FORMAT_XBGR8888: | |
722 | case DRM_FORMAT_ABGR8888: | |
723 | case DRM_FORMAT_BGR565: | |
724 | writel(WIN_RGB_ORDER_REVERSE, ctx->regs + WIN_RGB_ORDER(win)); | |
725 | break; | |
726 | default: | |
727 | writel(WIN_RGB_ORDER_FORWARD, ctx->regs + WIN_RGB_ORDER(win)); | |
728 | break; | |
729 | } | |
730 | ||
66367461 | 731 | /* |
8b704d8a MS |
732 | * Setting dma-burst to 16Word causes permanent tearing for very small |
733 | * buffers, e.g. cursor buffer. Burst Mode switching which based on | |
734 | * plane size is not recommended as plane size varies alot towards the | |
735 | * end of the screen and rapid movement causes unstable DMA, but it is | |
736 | * still better to change dma-burst than displaying garbage. | |
66367461 RS |
737 | */ |
738 | ||
8b704d8a | 739 | if (width < MIN_FB_WIDTH_FOR_16WORD_BURST) { |
66367461 RS |
740 | val &= ~WINCONx_BURSTLEN_MASK; |
741 | val |= WINCONx_BURSTLEN_4WORD; | |
742 | } | |
3b5129b3 | 743 | fimd_set_bits(ctx, WINCON(win), ~WINCONx_BLEND_MODE_MASK, val); |
453b44a3 GP |
744 | |
745 | /* hardware window 0 doesn't support alpha channel. */ | |
3b5129b3 CM |
746 | if (win != 0) { |
747 | fimd_win_set_bldmod(ctx, win, alpha, pixel_alpha); | |
748 | fimd_win_set_bldeq(ctx, win, alpha, pixel_alpha); | |
749 | } | |
1c248b7d ID |
750 | } |
751 | ||
bb7704d6 | 752 | static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win) |
1c248b7d | 753 | { |
1c248b7d ID |
754 | unsigned int keycon0 = 0, keycon1 = 0; |
755 | ||
1c248b7d ID |
756 | keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F | |
757 | WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0); | |
758 | ||
759 | keycon1 = WxKEYCON1_COLVAL(0xffffffff); | |
760 | ||
761 | writel(keycon0, ctx->regs + WKEYCON0_BASE(win)); | |
762 | writel(keycon1, ctx->regs + WKEYCON1_BASE(win)); | |
763 | } | |
764 | ||
de7af100 | 765 | /** |
b80bfc59 | 766 | * fimd_shadow_protect_win() - disable updating values from shadow registers at vsync |
de7af100 | 767 | * |
cc40c475 | 768 | * @ctx: local driver data |
de7af100 TF |
769 | * @win: window to protect registers for |
770 | * @protect: 1 to protect (disable updates) | |
771 | */ | |
772 | static void fimd_shadow_protect_win(struct fimd_context *ctx, | |
6e2a3b66 | 773 | unsigned int win, bool protect) |
de7af100 TF |
774 | { |
775 | u32 reg, bits, val; | |
776 | ||
ce3ff36b GP |
777 | /* |
778 | * SHADOWCON/PRTCON register is used for enabling timing. | |
779 | * | |
780 | * for example, once only width value of a register is set, | |
781 | * if the dma is started then fimd hardware could malfunction so | |
782 | * with protect window setting, the register fields with prefix '_F' | |
783 | * wouldn't be updated at vsync also but updated once unprotect window | |
784 | * is set. | |
785 | */ | |
786 | ||
de7af100 TF |
787 | if (ctx->driver_data->has_shadowcon) { |
788 | reg = SHADOWCON; | |
789 | bits = SHADOWCON_WINx_PROTECT(win); | |
790 | } else { | |
791 | reg = PRTCON; | |
792 | bits = PRTCON_PROTECT; | |
793 | } | |
794 | ||
795 | val = readl(ctx->regs + reg); | |
796 | if (protect) | |
797 | val |= bits; | |
798 | else | |
799 | val &= ~bits; | |
800 | writel(val, ctx->regs + reg); | |
801 | } | |
802 | ||
d29c2c14 | 803 | static void fimd_atomic_begin(struct exynos_drm_crtc *crtc) |
ce3ff36b GP |
804 | { |
805 | struct fimd_context *ctx = crtc->ctx; | |
d29c2c14 | 806 | int i; |
ce3ff36b GP |
807 | |
808 | if (ctx->suspended) | |
809 | return; | |
810 | ||
d29c2c14 MS |
811 | for (i = 0; i < WINDOWS_NR; i++) |
812 | fimd_shadow_protect_win(ctx, i, true); | |
ce3ff36b GP |
813 | } |
814 | ||
d29c2c14 | 815 | static void fimd_atomic_flush(struct exynos_drm_crtc *crtc) |
ce3ff36b GP |
816 | { |
817 | struct fimd_context *ctx = crtc->ctx; | |
d29c2c14 | 818 | int i; |
ce3ff36b GP |
819 | |
820 | if (ctx->suspended) | |
821 | return; | |
822 | ||
d29c2c14 MS |
823 | for (i = 0; i < WINDOWS_NR; i++) |
824 | fimd_shadow_protect_win(ctx, i, false); | |
a392276d AH |
825 | |
826 | exynos_crtc_handle_event(crtc); | |
ce3ff36b GP |
827 | } |
828 | ||
1e1d1393 GP |
829 | static void fimd_update_plane(struct exynos_drm_crtc *crtc, |
830 | struct exynos_drm_plane *plane) | |
1c248b7d | 831 | { |
0114f404 MS |
832 | struct exynos_drm_plane_state *state = |
833 | to_exynos_plane_state(plane->base.state); | |
93bca243 | 834 | struct fimd_context *ctx = crtc->ctx; |
0114f404 | 835 | struct drm_framebuffer *fb = state->base.fb; |
7ee14cdc GP |
836 | dma_addr_t dma_addr; |
837 | unsigned long val, size, offset; | |
838 | unsigned int last_x, last_y, buf_offsize, line_size; | |
40bdfb0a | 839 | unsigned int win = plane->index; |
ac60944c | 840 | unsigned int cpp = fb->format->cpp[0]; |
0488f50e | 841 | unsigned int pitch = fb->pitches[0]; |
1c248b7d | 842 | |
e30d4bcf ID |
843 | if (ctx->suspended) |
844 | return; | |
845 | ||
ac60944c | 846 | offset = state->src.x * cpp; |
0114f404 | 847 | offset += state->src.y * pitch; |
7ee14cdc | 848 | |
1c248b7d | 849 | /* buffer start address */ |
0488f50e | 850 | dma_addr = exynos_drm_fb_dma_addr(fb, 0) + offset; |
7ee14cdc | 851 | val = (unsigned long)dma_addr; |
1c248b7d ID |
852 | writel(val, ctx->regs + VIDWx_BUF_START(win, 0)); |
853 | ||
854 | /* buffer end address */ | |
0114f404 | 855 | size = pitch * state->crtc.h; |
7ee14cdc | 856 | val = (unsigned long)(dma_addr + size); |
1c248b7d ID |
857 | writel(val, ctx->regs + VIDWx_BUF_END(win, 0)); |
858 | ||
6be90056 ID |
859 | DRM_DEV_DEBUG_KMS(ctx->dev, |
860 | "start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n", | |
861 | (unsigned long)dma_addr, val, size); | |
862 | DRM_DEV_DEBUG_KMS(ctx->dev, "ovl_width = %d, ovl_height = %d\n", | |
863 | state->crtc.w, state->crtc.h); | |
1c248b7d ID |
864 | |
865 | /* buffer size */ | |
ac60944c TJ |
866 | buf_offsize = pitch - (state->crtc.w * cpp); |
867 | line_size = state->crtc.w * cpp; | |
7ee14cdc GP |
868 | val = VIDW_BUF_SIZE_OFFSET(buf_offsize) | |
869 | VIDW_BUF_SIZE_PAGEWIDTH(line_size) | | |
870 | VIDW_BUF_SIZE_OFFSET_E(buf_offsize) | | |
871 | VIDW_BUF_SIZE_PAGEWIDTH_E(line_size); | |
1c248b7d ID |
872 | writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0)); |
873 | ||
874 | /* OSD position */ | |
0114f404 MS |
875 | val = VIDOSDxA_TOPLEFT_X(state->crtc.x) | |
876 | VIDOSDxA_TOPLEFT_Y(state->crtc.y) | | |
877 | VIDOSDxA_TOPLEFT_X_E(state->crtc.x) | | |
878 | VIDOSDxA_TOPLEFT_Y_E(state->crtc.y); | |
1c248b7d ID |
879 | writel(val, ctx->regs + VIDOSD_A(win)); |
880 | ||
0114f404 | 881 | last_x = state->crtc.x + state->crtc.w; |
f56aad3a JS |
882 | if (last_x) |
883 | last_x--; | |
0114f404 | 884 | last_y = state->crtc.y + state->crtc.h; |
f56aad3a JS |
885 | if (last_y) |
886 | last_y--; | |
887 | ||
ca555e5a JS |
888 | val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) | |
889 | VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y); | |
890 | ||
1c248b7d ID |
891 | writel(val, ctx->regs + VIDOSD_B(win)); |
892 | ||
6be90056 ID |
893 | DRM_DEV_DEBUG_KMS(ctx->dev, |
894 | "osd pos: tx = %d, ty = %d, bx = %d, by = %d\n", | |
895 | state->crtc.x, state->crtc.y, last_x, last_y); | |
1c248b7d | 896 | |
1c248b7d ID |
897 | /* OSD size */ |
898 | if (win != 3 && win != 4) { | |
899 | u32 offset = VIDOSD_D(win); | |
900 | if (win == 0) | |
0f10cf14 | 901 | offset = VIDOSD_C(win); |
0114f404 | 902 | val = state->crtc.w * state->crtc.h; |
1c248b7d ID |
903 | writel(val, ctx->regs + offset); |
904 | ||
6be90056 ID |
905 | DRM_DEV_DEBUG_KMS(ctx->dev, "osd size = 0x%x\n", |
906 | (unsigned int)val); | |
1c248b7d ID |
907 | } |
908 | ||
6f8ee5c2 | 909 | fimd_win_set_pixfmt(ctx, win, fb, state->src.w); |
1c248b7d ID |
910 | |
911 | /* hardware window 0 doesn't support color key. */ | |
912 | if (win != 0) | |
bb7704d6 | 913 | fimd_win_set_colkey(ctx, win); |
1c248b7d | 914 | |
f181a543 | 915 | fimd_enable_video_output(ctx, win, true); |
ec05da95 | 916 | |
999d8b31 YC |
917 | if (ctx->driver_data->has_shadowcon) |
918 | fimd_enable_shadow_channel_path(ctx, win, true); | |
ec05da95 | 919 | |
3854fab2 YC |
920 | if (ctx->i80_if) |
921 | atomic_set(&ctx->win_updated, 1); | |
1c248b7d ID |
922 | } |
923 | ||
1e1d1393 GP |
924 | static void fimd_disable_plane(struct exynos_drm_crtc *crtc, |
925 | struct exynos_drm_plane *plane) | |
1c248b7d | 926 | { |
93bca243 | 927 | struct fimd_context *ctx = crtc->ctx; |
40bdfb0a | 928 | unsigned int win = plane->index; |
ec05da95 | 929 | |
c329f667 | 930 | if (ctx->suspended) |
db7e55ae | 931 | return; |
db7e55ae | 932 | |
f181a543 | 933 | fimd_enable_video_output(ctx, win, false); |
1c248b7d | 934 | |
999d8b31 YC |
935 | if (ctx->driver_data->has_shadowcon) |
936 | fimd_enable_shadow_channel_path(ctx, win, false); | |
a43b933b SP |
937 | } |
938 | ||
11f95489 | 939 | static void fimd_atomic_enable(struct exynos_drm_crtc *crtc) |
a43b933b | 940 | { |
3cecda03 | 941 | struct fimd_context *ctx = crtc->ctx; |
a43b933b SP |
942 | |
943 | if (!ctx->suspended) | |
3cecda03 | 944 | return; |
a43b933b SP |
945 | |
946 | ctx->suspended = false; | |
947 | ||
445d3bed ID |
948 | if (pm_runtime_resume_and_get(ctx->dev) < 0) { |
949 | dev_warn(ctx->dev, "failed to enable FIMD device.\n"); | |
950 | return; | |
951 | } | |
af65c804 | 952 | |
a43b933b | 953 | /* if vblank was enabled status, enable it again. */ |
3cecda03 GP |
954 | if (test_and_clear_bit(0, &ctx->irq_flags)) |
955 | fimd_enable_vblank(ctx->crtc); | |
a43b933b | 956 | |
c329f667 | 957 | fimd_commit(ctx->crtc); |
a43b933b SP |
958 | } |
959 | ||
11f95489 | 960 | static void fimd_atomic_disable(struct exynos_drm_crtc *crtc) |
a43b933b | 961 | { |
3cecda03 | 962 | struct fimd_context *ctx = crtc->ctx; |
c329f667 | 963 | int i; |
3cecda03 | 964 | |
a43b933b | 965 | if (ctx->suspended) |
3cecda03 | 966 | return; |
a43b933b SP |
967 | |
968 | /* | |
969 | * We need to make sure that all windows are disabled before we | |
970 | * suspend that connector. Otherwise we might try to scan from | |
971 | * a destroyed buffer later. | |
972 | */ | |
c329f667 | 973 | for (i = 0; i < WINDOWS_NR; i++) |
1e1d1393 | 974 | fimd_disable_plane(crtc, &ctx->planes[i]); |
a43b933b | 975 | |
94ab95a9 ID |
976 | fimd_enable_vblank(crtc); |
977 | fimd_wait_for_vblank(crtc); | |
978 | fimd_disable_vblank(crtc); | |
979 | ||
b74f14fd JS |
980 | writel(0, ctx->regs + VIDCON0); |
981 | ||
af65c804 | 982 | pm_runtime_put_sync(ctx->dev); |
a43b933b | 983 | ctx->suspended = true; |
080be03d SP |
984 | } |
985 | ||
3854fab2 YC |
986 | static void fimd_trigger(struct device *dev) |
987 | { | |
e152dbd7 | 988 | struct fimd_context *ctx = dev_get_drvdata(dev); |
e1a7b9b4 | 989 | const struct fimd_driver_data *driver_data = ctx->driver_data; |
3854fab2 YC |
990 | void *timing_base = ctx->regs + driver_data->timing_base; |
991 | u32 reg; | |
992 | ||
9b67eb73 | 993 | /* |
1c905d95 YC |
994 | * Skips triggering if in triggering state, because multiple triggering |
995 | * requests can cause panel reset. | |
996 | */ | |
9b67eb73 JS |
997 | if (atomic_read(&ctx->triggering)) |
998 | return; | |
999 | ||
1c905d95 | 1000 | /* Enters triggering mode */ |
3854fab2 YC |
1001 | atomic_set(&ctx->triggering, 1); |
1002 | ||
3854fab2 | 1003 | reg = readl(timing_base + TRIGCON); |
b5bf0f1e | 1004 | reg |= (TRGMODE_ENABLE | SWTRGCMD_ENABLE); |
3854fab2 | 1005 | writel(reg, timing_base + TRIGCON); |
87ab85b3 YC |
1006 | |
1007 | /* | |
1008 | * Exits triggering mode if vblank is not enabled yet, because when the | |
1009 | * VIDINTCON0 register is not set, it can not exit from triggering mode. | |
1010 | */ | |
1011 | if (!test_bit(0, &ctx->irq_flags)) | |
1012 | atomic_set(&ctx->triggering, 0); | |
3854fab2 YC |
1013 | } |
1014 | ||
93bca243 | 1015 | static void fimd_te_handler(struct exynos_drm_crtc *crtc) |
3854fab2 | 1016 | { |
93bca243 | 1017 | struct fimd_context *ctx = crtc->ctx; |
a6f75aa1 | 1018 | u32 trg_type = ctx->driver_data->trg_type; |
3854fab2 YC |
1019 | |
1020 | /* Checks the crtc is detached already from encoder */ | |
2949390e | 1021 | if (!ctx->drm_dev) |
3854fab2 YC |
1022 | return; |
1023 | ||
a6f75aa1 ID |
1024 | if (trg_type == I80_HW_TRG) |
1025 | goto out; | |
1026 | ||
3854fab2 YC |
1027 | /* |
1028 | * If there is a page flip request, triggers and handles the page flip | |
1029 | * event so that current fb can be updated into panel GRAM. | |
1030 | */ | |
1031 | if (atomic_add_unless(&ctx->win_updated, -1, 0)) | |
1032 | fimd_trigger(ctx->dev); | |
1033 | ||
a6f75aa1 | 1034 | out: |
3854fab2 YC |
1035 | /* Wakes up vsync event queue */ |
1036 | if (atomic_read(&ctx->wait_vsync_event)) { | |
1037 | atomic_set(&ctx->wait_vsync_event, 0); | |
1038 | wake_up(&ctx->wait_vsync_queue); | |
3854fab2 | 1039 | } |
b301ae24 | 1040 | |
adf67abf | 1041 | if (test_bit(0, &ctx->irq_flags)) |
eafd540a | 1042 | drm_crtc_handle_vblank(&ctx->crtc->base); |
3854fab2 YC |
1043 | } |
1044 | ||
196e059a | 1045 | static void fimd_dp_clock_enable(struct exynos_drm_clk *clk, bool enable) |
48107d7b | 1046 | { |
196e059a AH |
1047 | struct fimd_context *ctx = container_of(clk, struct fimd_context, |
1048 | dp_clk); | |
1049 | u32 val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE; | |
3c79fb8c | 1050 | writel(val, ctx->regs + DP_MIE_CLKCON); |
48107d7b KK |
1051 | } |
1052 | ||
f3aaf762 | 1053 | static const struct exynos_drm_crtc_ops fimd_crtc_ops = { |
11f95489 ID |
1054 | .atomic_enable = fimd_atomic_enable, |
1055 | .atomic_disable = fimd_atomic_disable, | |
1c6244c3 SP |
1056 | .enable_vblank = fimd_enable_vblank, |
1057 | .disable_vblank = fimd_disable_vblank, | |
ce3ff36b | 1058 | .atomic_begin = fimd_atomic_begin, |
9cc7610a GP |
1059 | .update_plane = fimd_update_plane, |
1060 | .disable_plane = fimd_disable_plane, | |
ce3ff36b | 1061 | .atomic_flush = fimd_atomic_flush, |
c96fdfde | 1062 | .atomic_check = fimd_atomic_check, |
3854fab2 | 1063 | .te_handler = fimd_te_handler, |
1c248b7d ID |
1064 | }; |
1065 | ||
1c248b7d ID |
1066 | static irqreturn_t fimd_irq_handler(int irq, void *dev_id) |
1067 | { | |
1068 | struct fimd_context *ctx = (struct fimd_context *)dev_id; | |
9276dff7 | 1069 | u32 val, clear_bit; |
1c248b7d ID |
1070 | |
1071 | val = readl(ctx->regs + VIDINTCON1); | |
1072 | ||
3854fab2 YC |
1073 | clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME; |
1074 | if (val & clear_bit) | |
1075 | writel(clear_bit, ctx->regs + VIDINTCON1); | |
1c248b7d | 1076 | |
ec05da95 | 1077 | /* check the crtc is detached already from encoder */ |
2949390e | 1078 | if (!ctx->drm_dev) |
ec05da95 | 1079 | goto out; |
483b88f8 | 1080 | |
fc75f710 GP |
1081 | if (!ctx->i80_if) |
1082 | drm_crtc_handle_vblank(&ctx->crtc->base); | |
1083 | ||
fc75f710 | 1084 | if (ctx->i80_if) { |
1c905d95 | 1085 | /* Exits triggering mode */ |
3854fab2 | 1086 | atomic_set(&ctx->triggering, 0); |
3854fab2 | 1087 | } else { |
3854fab2 YC |
1088 | /* set wait vsync event to zero and wake up queue. */ |
1089 | if (atomic_read(&ctx->wait_vsync_event)) { | |
1090 | atomic_set(&ctx->wait_vsync_event, 0); | |
1091 | wake_up(&ctx->wait_vsync_queue); | |
1092 | } | |
01ce113c | 1093 | } |
3854fab2 | 1094 | |
ec05da95 | 1095 | out: |
1c248b7d ID |
1096 | return IRQ_HANDLED; |
1097 | } | |
1098 | ||
f37cd5e8 | 1099 | static int fimd_bind(struct device *dev, struct device *master, void *data) |
562ad9f4 | 1100 | { |
e152dbd7 | 1101 | struct fimd_context *ctx = dev_get_drvdata(dev); |
f37cd5e8 | 1102 | struct drm_device *drm_dev = data; |
7ee14cdc | 1103 | struct exynos_drm_plane *exynos_plane; |
fd2d2fc2 | 1104 | unsigned int i; |
6e2a3b66 | 1105 | int ret; |
000cc920 | 1106 | |
cdbfca89 | 1107 | ctx->drm_dev = drm_dev; |
efa75bcd | 1108 | |
fd2d2fc2 | 1109 | for (i = 0; i < WINDOWS_NR; i++) { |
2d684f4e MJ |
1110 | if (ctx->driver_data->has_bgr_support) { |
1111 | ctx->configs[i].pixel_formats = fimd_extended_formats; | |
1112 | ctx->configs[i].num_pixel_formats = ARRAY_SIZE(fimd_extended_formats); | |
1113 | } else { | |
1114 | ctx->configs[i].pixel_formats = fimd_formats; | |
1115 | ctx->configs[i].num_pixel_formats = ARRAY_SIZE(fimd_formats); | |
1116 | } | |
1117 | ||
fd2d2fc2 MS |
1118 | ctx->configs[i].zpos = i; |
1119 | ctx->configs[i].type = fimd_win_types[i]; | |
6f8ee5c2 | 1120 | ctx->configs[i].capabilities = capabilities[i]; |
40bdfb0a | 1121 | ret = exynos_plane_init(drm_dev, &ctx->planes[i], i, |
2c82607b | 1122 | &ctx->configs[i]); |
7ee14cdc GP |
1123 | if (ret) |
1124 | return ret; | |
1125 | } | |
1126 | ||
5d3d0995 | 1127 | exynos_plane = &ctx->planes[DEFAULT_WIN]; |
7ee14cdc | 1128 | ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, |
d644951c | 1129 | EXYNOS_DISPLAY_TYPE_LCD, &fimd_crtc_ops, ctx); |
d1222842 HH |
1130 | if (IS_ERR(ctx->crtc)) |
1131 | return PTR_ERR(ctx->crtc); | |
93bca243 | 1132 | |
196e059a AH |
1133 | if (ctx->driver_data->has_dp_clk) { |
1134 | ctx->dp_clk.enable = fimd_dp_clock_enable; | |
1135 | ctx->crtc->pipe_clk = &ctx->dp_clk; | |
1136 | } | |
1137 | ||
cf67cc9a | 1138 | if (ctx->encoder) |
a2986e80 | 1139 | exynos_dpi_bind(drm_dev, ctx->encoder); |
000cc920 | 1140 | |
445d3bed ID |
1141 | if (is_drm_iommu_supported(drm_dev)) { |
1142 | int ret; | |
1143 | ||
1144 | ret = fimd_clear_channels(ctx->crtc); | |
1145 | if (ret < 0) | |
1146 | return ret; | |
1147 | } | |
eb7a3fc7 | 1148 | |
07dc3678 | 1149 | return exynos_drm_register_dma(drm_dev, dev, &ctx->dma_priv); |
000cc920 AH |
1150 | } |
1151 | ||
1152 | static void fimd_unbind(struct device *dev, struct device *master, | |
1153 | void *data) | |
1154 | { | |
e152dbd7 | 1155 | struct fimd_context *ctx = dev_get_drvdata(dev); |
000cc920 | 1156 | |
11f95489 | 1157 | fimd_atomic_disable(ctx->crtc); |
000cc920 | 1158 | |
07dc3678 | 1159 | exynos_drm_unregister_dma(ctx->drm_dev, ctx->dev, &ctx->dma_priv); |
cdbfca89 | 1160 | |
cf67cc9a GP |
1161 | if (ctx->encoder) |
1162 | exynos_dpi_remove(ctx->encoder); | |
000cc920 AH |
1163 | } |
1164 | ||
1165 | static const struct component_ops fimd_component_ops = { | |
1166 | .bind = fimd_bind, | |
1167 | .unbind = fimd_unbind, | |
1168 | }; | |
1169 | ||
1170 | static int fimd_probe(struct platform_device *pdev) | |
1171 | { | |
1172 | struct device *dev = &pdev->dev; | |
562ad9f4 | 1173 | struct fimd_context *ctx; |
3854fab2 | 1174 | struct device_node *i80_if_timings; |
fe42cfb4 | 1175 | int ret; |
1c248b7d | 1176 | |
e152dbd7 AH |
1177 | if (!dev->of_node) |
1178 | return -ENODEV; | |
2d3f173c | 1179 | |
d873ab99 | 1180 | ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); |
e152dbd7 AH |
1181 | if (!ctx) |
1182 | return -ENOMEM; | |
1183 | ||
bb7704d6 | 1184 | ctx->dev = dev; |
a43b933b | 1185 | ctx->suspended = true; |
e1a7b9b4 | 1186 | ctx->driver_data = of_device_get_match_data(dev); |
bb7704d6 | 1187 | |
1417f109 SP |
1188 | if (of_property_read_bool(dev->of_node, "samsung,invert-vden")) |
1189 | ctx->vidcon1 |= VIDCON1_INV_VDEN; | |
1190 | if (of_property_read_bool(dev->of_node, "samsung,invert-vclk")) | |
1191 | ctx->vidcon1 |= VIDCON1_INV_VCLK; | |
562ad9f4 | 1192 | |
3854fab2 YC |
1193 | i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings"); |
1194 | if (i80_if_timings) { | |
1195 | u32 val; | |
1196 | ||
1197 | ctx->i80_if = true; | |
1198 | ||
1199 | if (ctx->driver_data->has_vidoutcon) | |
1200 | ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0; | |
1201 | else | |
1202 | ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0; | |
1203 | /* | |
1204 | * The user manual describes that this "DSI_EN" bit is required | |
1205 | * to enable I80 24-bit data interface. | |
1206 | */ | |
1207 | ctx->vidcon0 |= VIDCON0_DSI_EN; | |
1208 | ||
1209 | if (of_property_read_u32(i80_if_timings, "cs-setup", &val)) | |
1210 | val = 0; | |
1211 | ctx->i80ifcon = LCD_CS_SETUP(val); | |
1212 | if (of_property_read_u32(i80_if_timings, "wr-setup", &val)) | |
1213 | val = 0; | |
1214 | ctx->i80ifcon |= LCD_WR_SETUP(val); | |
1215 | if (of_property_read_u32(i80_if_timings, "wr-active", &val)) | |
1216 | val = 1; | |
1217 | ctx->i80ifcon |= LCD_WR_ACTIVE(val); | |
1218 | if (of_property_read_u32(i80_if_timings, "wr-hold", &val)) | |
1219 | val = 0; | |
1220 | ctx->i80ifcon |= LCD_WR_HOLD(val); | |
1221 | } | |
1222 | of_node_put(i80_if_timings); | |
1223 | ||
1224 | ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node, | |
1225 | "samsung,sysreg"); | |
1226 | if (IS_ERR(ctx->sysreg)) { | |
1227 | dev_warn(dev, "failed to get system register.\n"); | |
1228 | ctx->sysreg = NULL; | |
1229 | } | |
1230 | ||
a968e727 SP |
1231 | ctx->bus_clk = devm_clk_get(dev, "fimd"); |
1232 | if (IS_ERR(ctx->bus_clk)) { | |
1233 | dev_err(dev, "failed to get bus clock\n"); | |
86650408 | 1234 | return PTR_ERR(ctx->bus_clk); |
a968e727 SP |
1235 | } |
1236 | ||
1237 | ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd"); | |
1238 | if (IS_ERR(ctx->lcd_clk)) { | |
1239 | dev_err(dev, "failed to get lcd clock\n"); | |
86650408 | 1240 | return PTR_ERR(ctx->lcd_clk); |
a968e727 | 1241 | } |
1c248b7d | 1242 | |
17ac76e0 | 1243 | ctx->regs = devm_platform_ioremap_resource(pdev, 0); |
86650408 AH |
1244 | if (IS_ERR(ctx->regs)) |
1245 | return PTR_ERR(ctx->regs); | |
1c248b7d | 1246 | |
9df3f43a LP |
1247 | ret = platform_get_irq_byname(pdev, ctx->i80_if ? "lcd_sys" : "vsync"); |
1248 | if (ret < 0) | |
1249 | return ret; | |
1c248b7d | 1250 | |
9df3f43a | 1251 | ret = devm_request_irq(dev, ret, fimd_irq_handler, 0, "drm_fimd", ctx); |
edc57266 | 1252 | if (ret) { |
1c248b7d | 1253 | dev_err(dev, "irq request failed.\n"); |
86650408 | 1254 | return ret; |
1c248b7d ID |
1255 | } |
1256 | ||
57ed0f7b | 1257 | init_waitqueue_head(&ctx->wait_vsync_queue); |
01ce113c | 1258 | atomic_set(&ctx->wait_vsync_event, 0); |
1c248b7d | 1259 | |
e152dbd7 | 1260 | platform_set_drvdata(pdev, ctx); |
14b6873a | 1261 | |
cf67cc9a GP |
1262 | ctx->encoder = exynos_dpi_probe(dev); |
1263 | if (IS_ERR(ctx->encoder)) | |
1264 | return PTR_ERR(ctx->encoder); | |
f37cd5e8 | 1265 | |
e152dbd7 | 1266 | pm_runtime_enable(dev); |
f37cd5e8 | 1267 | |
e152dbd7 | 1268 | ret = component_add(dev, &fimd_component_ops); |
df5225bc ID |
1269 | if (ret) |
1270 | goto err_disable_pm_runtime; | |
1271 | ||
1272 | return ret; | |
1273 | ||
1274 | err_disable_pm_runtime: | |
e152dbd7 | 1275 | pm_runtime_disable(dev); |
df5225bc | 1276 | |
df5225bc | 1277 | return ret; |
f37cd5e8 | 1278 | } |
cb91f6a0 | 1279 | |
4fe7a1ec | 1280 | static void fimd_remove(struct platform_device *pdev) |
f37cd5e8 | 1281 | { |
af65c804 | 1282 | pm_runtime_disable(&pdev->dev); |
5d55393a | 1283 | |
df5225bc | 1284 | component_del(&pdev->dev, &fimd_component_ops); |
e30d4bcf ID |
1285 | } |
1286 | ||
41571976 GP |
1287 | static int exynos_fimd_suspend(struct device *dev) |
1288 | { | |
1289 | struct fimd_context *ctx = dev_get_drvdata(dev); | |
1290 | ||
1291 | clk_disable_unprepare(ctx->lcd_clk); | |
1292 | clk_disable_unprepare(ctx->bus_clk); | |
1293 | ||
1294 | return 0; | |
1295 | } | |
1296 | ||
1297 | static int exynos_fimd_resume(struct device *dev) | |
1298 | { | |
1299 | struct fimd_context *ctx = dev_get_drvdata(dev); | |
1300 | int ret; | |
1301 | ||
1302 | ret = clk_prepare_enable(ctx->bus_clk); | |
1303 | if (ret < 0) { | |
6f83d208 ID |
1304 | DRM_DEV_ERROR(dev, |
1305 | "Failed to prepare_enable the bus clk [%d]\n", | |
1306 | ret); | |
41571976 GP |
1307 | return ret; |
1308 | } | |
1309 | ||
1310 | ret = clk_prepare_enable(ctx->lcd_clk); | |
1311 | if (ret < 0) { | |
6f83d208 ID |
1312 | DRM_DEV_ERROR(dev, |
1313 | "Failed to prepare_enable the lcd clk [%d]\n", | |
1314 | ret); | |
41571976 GP |
1315 | return ret; |
1316 | } | |
1317 | ||
1318 | return 0; | |
1319 | } | |
41571976 | 1320 | |
1d9e6664 PC |
1321 | static DEFINE_RUNTIME_DEV_PM_OPS(exynos_fimd_pm_ops, exynos_fimd_suspend, |
1322 | exynos_fimd_resume, NULL); | |
41571976 | 1323 | |
132a5b91 | 1324 | struct platform_driver fimd_driver = { |
1c248b7d | 1325 | .probe = fimd_probe, |
4fe7a1ec | 1326 | .remove_new = fimd_remove, |
1c248b7d ID |
1327 | .driver = { |
1328 | .name = "exynos4-fb", | |
1329 | .owner = THIS_MODULE, | |
1d9e6664 | 1330 | .pm = pm_ptr(&exynos_fimd_pm_ops), |
2d3f173c | 1331 | .of_match_table = fimd_driver_dt_match, |
1c248b7d ID |
1332 | }, |
1333 | }; |