Commit | Line | Data |
---|---|---|
2874c5fd | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
1c248b7d ID |
2 | /* exynos_drm_drv.h |
3 | * | |
4 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | |
5 | * Authors: | |
6 | * Inki Dae <inki.dae@samsung.com> | |
7 | * Joonyoung Shim <jy0922.shim@samsung.com> | |
8 | * Seung-Woo Kim <sw0312.kim@samsung.com> | |
1c248b7d ID |
9 | */ |
10 | ||
11 | #ifndef _EXYNOS_DRM_DRV_H_ | |
12 | #define _EXYNOS_DRM_DRV_H_ | |
13 | ||
4f9eb94f | 14 | #include <linux/module.h> |
1c248b7d | 15 | |
2bda34d7 SR |
16 | #include <drm/drm_crtc.h> |
17 | #include <drm/drm_device.h> | |
18 | #include <drm/drm_plane.h> | |
19 | ||
b73d1230 | 20 | #define MAX_CRTC 3 |
864ee9e6 | 21 | #define MAX_PLANE 5 |
b73d1230 | 22 | #define MAX_FB_BUFFER 4 |
1c248b7d | 23 | |
5d3d0995 GP |
24 | #define DEFAULT_WIN 0 |
25 | ||
2bda34d7 SR |
26 | struct drm_crtc_state; |
27 | struct drm_display_mode; | |
28 | ||
357193cd | 29 | #define to_exynos_crtc(x) container_of(x, struct exynos_drm_crtc, base) |
8837deea | 30 | #define to_exynos_plane(x) container_of(x, struct exynos_drm_plane, base) |
ffceaed6 | 31 | |
1c248b7d ID |
32 | /* this enumerates display type. */ |
33 | enum exynos_drm_output_type { | |
34 | EXYNOS_DISPLAY_TYPE_NONE, | |
35 | /* RGB or CPU Interface. */ | |
36 | EXYNOS_DISPLAY_TYPE_LCD, | |
37 | /* HDMI Interface. */ | |
38 | EXYNOS_DISPLAY_TYPE_HDMI, | |
b73d1230 ID |
39 | /* Virtual Display Interface. */ |
40 | EXYNOS_DISPLAY_TYPE_VIDI, | |
1c248b7d ID |
41 | }; |
42 | ||
0114f404 MS |
43 | struct exynos_drm_rect { |
44 | unsigned int x, y; | |
45 | unsigned int w, h; | |
46 | }; | |
47 | ||
1c248b7d | 48 | /* |
0114f404 | 49 | * Exynos drm plane state structure. |
1c248b7d | 50 | * |
0114f404 MS |
51 | * @base: plane_state object (contains drm_framebuffer pointer) |
52 | * @src: rectangle of the source image data to be displayed (clipped to | |
53 | * visible part). | |
54 | * @crtc: rectangle of the target image position on hardware screen | |
55 | * (clipped to visible part). | |
3cabaf7e JS |
56 | * @h_ratio: horizontal scaling ratio, 16.16 fixed point |
57 | * @v_ratio: vertical scaling ratio, 16.16 fixed point | |
0114f404 MS |
58 | * |
59 | * this structure consists plane state data that will be applied to hardware | |
60 | * specific overlay info. | |
61 | */ | |
62 | ||
63 | struct exynos_drm_plane_state { | |
64 | struct drm_plane_state base; | |
65 | struct exynos_drm_rect crtc; | |
66 | struct exynos_drm_rect src; | |
67 | unsigned int h_ratio; | |
68 | unsigned int v_ratio; | |
69 | }; | |
70 | ||
71 | static inline struct exynos_drm_plane_state * | |
72 | to_exynos_plane_state(struct drm_plane_state *state) | |
73 | { | |
74 | return container_of(state, struct exynos_drm_plane_state, base); | |
75 | } | |
76 | ||
77 | /* | |
78 | * Exynos drm common overlay structure. | |
79 | * | |
80 | * @base: plane object | |
40bdfb0a | 81 | * @index: hardware index of the overlay layer |
1c248b7d ID |
82 | * |
83 | * this structure is common to exynos SoC and its contents would be copied | |
84 | * to hardware specific overlay info. | |
85 | */ | |
8837deea GP |
86 | |
87 | struct exynos_drm_plane { | |
88 | struct drm_plane base; | |
fd2d2fc2 | 89 | const struct exynos_drm_plane_config *config; |
40bdfb0a | 90 | unsigned int index; |
1c248b7d ID |
91 | }; |
92 | ||
6178d3d1 MS |
93 | #define EXYNOS_DRM_PLANE_CAP_DOUBLE (1 << 0) |
94 | #define EXYNOS_DRM_PLANE_CAP_SCALE (1 << 1) | |
0ea72405 | 95 | #define EXYNOS_DRM_PLANE_CAP_ZPOS (1 << 2) |
f40031c2 | 96 | #define EXYNOS_DRM_PLANE_CAP_TILE (1 << 3) |
482582c0 | 97 | #define EXYNOS_DRM_PLANE_CAP_PIX_BLEND (1 << 4) |
6ac99a32 | 98 | #define EXYNOS_DRM_PLANE_CAP_WIN_BLEND (1 << 5) |
6178d3d1 | 99 | |
fd2d2fc2 MS |
100 | /* |
101 | * Exynos DRM plane configuration structure. | |
102 | * | |
0ea72405 | 103 | * @zpos: initial z-position of the plane. |
fd2d2fc2 MS |
104 | * @type: type of the plane (primary, cursor or overlay). |
105 | * @pixel_formats: supported pixel formats. | |
106 | * @num_pixel_formats: number of elements in 'pixel_formats'. | |
107 | * @capabilities: supported features (see EXYNOS_DRM_PLANE_CAP_*) | |
108 | */ | |
109 | ||
110 | struct exynos_drm_plane_config { | |
111 | unsigned int zpos; | |
112 | enum drm_plane_type type; | |
113 | const uint32_t *pixel_formats; | |
114 | unsigned int num_pixel_formats; | |
115 | unsigned int capabilities; | |
116 | }; | |
117 | ||
1c248b7d | 118 | /* |
93bca243 | 119 | * Exynos drm crtc ops |
1c248b7d | 120 | * |
11f95489 ID |
121 | * @atomic_enable: enable the device |
122 | * @atomic_disable: disable the device | |
1c248b7d ID |
123 | * @enable_vblank: specific driver callback for enabling vblank interrupt. |
124 | * @disable_vblank: specific driver callback for disabling vblank interrupt. | |
c3653fed | 125 | * @mode_valid: specific driver callback for mode validation |
5625b341 | 126 | * @atomic_check: validate state |
d29c2c14 MS |
127 | * @atomic_begin: prepare device to receive an update |
128 | * @atomic_flush: mark the end of device update | |
9cc7610a GP |
129 | * @update_plane: apply hardware specific overlay data to registers. |
130 | * @disable_plane: disable hardware specific overlay. | |
5595d4d8 YC |
131 | * @te_handler: trigger to transfer video image at the tearing effect |
132 | * synchronization signal if there is a page flip request. | |
1c248b7d | 133 | */ |
93bca243 GP |
134 | struct exynos_drm_crtc; |
135 | struct exynos_drm_crtc_ops { | |
11f95489 ID |
136 | void (*atomic_enable)(struct exynos_drm_crtc *crtc); |
137 | void (*atomic_disable)(struct exynos_drm_crtc *crtc); | |
93bca243 GP |
138 | int (*enable_vblank)(struct exynos_drm_crtc *crtc); |
139 | void (*disable_vblank)(struct exynos_drm_crtc *crtc); | |
c3653fed AH |
140 | enum drm_mode_status (*mode_valid)(struct exynos_drm_crtc *crtc, |
141 | const struct drm_display_mode *mode); | |
2466db97 AH |
142 | bool (*mode_fixup)(struct exynos_drm_crtc *crtc, |
143 | const struct drm_display_mode *mode, | |
144 | struct drm_display_mode *adjusted_mode); | |
5625b341 AH |
145 | int (*atomic_check)(struct exynos_drm_crtc *crtc, |
146 | struct drm_crtc_state *state); | |
d29c2c14 | 147 | void (*atomic_begin)(struct exynos_drm_crtc *crtc); |
1e1d1393 GP |
148 | void (*update_plane)(struct exynos_drm_crtc *crtc, |
149 | struct exynos_drm_plane *plane); | |
150 | void (*disable_plane)(struct exynos_drm_crtc *crtc, | |
151 | struct exynos_drm_plane *plane); | |
d29c2c14 | 152 | void (*atomic_flush)(struct exynos_drm_crtc *crtc); |
93bca243 | 153 | void (*te_handler)(struct exynos_drm_crtc *crtc); |
1c248b7d ID |
154 | }; |
155 | ||
f26b9343 AH |
156 | struct exynos_drm_clk { |
157 | void (*enable)(struct exynos_drm_clk *clk, bool enable); | |
158 | }; | |
159 | ||
2bf053eb GP |
160 | /* |
161 | * Exynos specific crtc structure. | |
162 | * | |
357193cd | 163 | * @base: crtc object. |
5d1741ad | 164 | * @type: one of EXYNOS_DISPLAY_TYPE_LCD and HDMI. |
93bca243 GP |
165 | * @ops: pointer to callbacks for exynos drm specific functionality |
166 | * @ctx: A pointer to the crtc's implementation specific context | |
e379cbee | 167 | * @pipe_clk: A pointer to the crtc's pipeline clock. |
2bf053eb GP |
168 | */ |
169 | struct exynos_drm_crtc { | |
357193cd | 170 | struct drm_crtc base; |
5d1741ad | 171 | enum exynos_drm_output_type type; |
f3aaf762 | 172 | const struct exynos_drm_crtc_ops *ops; |
93bca243 | 173 | void *ctx; |
f26b9343 | 174 | struct exynos_drm_clk *pipe_clk; |
c038f538 | 175 | bool i80_mode : 1; |
2bf053eb GP |
176 | }; |
177 | ||
f26b9343 AH |
178 | static inline void exynos_drm_pipe_clk_enable(struct exynos_drm_crtc *crtc, |
179 | bool enable) | |
180 | { | |
181 | if (crtc->pipe_clk) | |
182 | crtc->pipe_clk->enable(crtc->pipe_clk, enable); | |
183 | } | |
184 | ||
eb4d9796 MS |
185 | struct drm_exynos_file_private { |
186 | /* for g2d api */ | |
d7f1642c JS |
187 | struct list_head inuse_cmdlist; |
188 | struct list_head event_list; | |
2a3098ff | 189 | struct list_head userptr_list; |
d7f1642c JS |
190 | }; |
191 | ||
1c248b7d ID |
192 | /* |
193 | * Exynos drm private structure. | |
0519f9a1 | 194 | * |
a379df19 GP |
195 | * @pending: the crtcs that have pending updates to finish |
196 | * @lock: protect access to @pending | |
197 | * @wait: wait an atomic commit to finish | |
1c248b7d ID |
198 | */ |
199 | struct exynos_drm_private { | |
200 | struct drm_fb_helper *fb_helper; | |
201 | ||
eb4d9796 | 202 | struct device *g2d_dev; |
f43c3596 | 203 | struct device *dma_dev; |
f43c3596 | 204 | void *mapping; |
f37cd5e8 | 205 | |
a379df19 GP |
206 | /* for atomic commit */ |
207 | u32 pending; | |
208 | spinlock_t lock; | |
209 | wait_queue_head_t wait; | |
1c248b7d ID |
210 | }; |
211 | ||
f43c3596 MS |
212 | static inline struct device *to_dma_dev(struct drm_device *dev) |
213 | { | |
214 | struct exynos_drm_private *priv = dev->dev_private; | |
215 | ||
216 | return priv->dma_dev; | |
217 | } | |
218 | ||
23755696 AH |
219 | static inline bool is_drm_iommu_supported(struct drm_device *drm_dev) |
220 | { | |
221 | struct exynos_drm_private *priv = drm_dev->dev_private; | |
222 | ||
223 | return priv->mapping ? true : false; | |
224 | } | |
225 | ||
07dc3678 MS |
226 | int exynos_drm_register_dma(struct drm_device *drm, struct device *dev, |
227 | void **dma_priv); | |
228 | void exynos_drm_unregister_dma(struct drm_device *drm, struct device *dev, | |
229 | void **dma_priv); | |
23755696 | 230 | void exynos_drm_cleanup_dma(struct drm_device *drm); |
29cbf24a | 231 | |
14b6873a | 232 | #ifdef CONFIG_DRM_EXYNOS_DPI |
2b8376c8 GP |
233 | struct drm_encoder *exynos_dpi_probe(struct device *dev); |
234 | int exynos_dpi_remove(struct drm_encoder *encoder); | |
235 | int exynos_dpi_bind(struct drm_device *dev, struct drm_encoder *encoder); | |
14b6873a | 236 | #else |
2b8376c8 | 237 | static inline struct drm_encoder * |
dcdffeda | 238 | exynos_dpi_probe(struct device *dev) { return NULL; } |
2b8376c8 | 239 | static inline int exynos_dpi_remove(struct drm_encoder *encoder) |
1c9ff4ab GP |
240 | { |
241 | return 0; | |
242 | } | |
a2986e80 | 243 | static inline int exynos_dpi_bind(struct drm_device *dev, |
2b8376c8 | 244 | struct drm_encoder *encoder) |
a2986e80 GP |
245 | { |
246 | return 0; | |
247 | } | |
14b6873a AH |
248 | #endif |
249 | ||
7a2d5c77 MS |
250 | #ifdef CONFIG_DRM_EXYNOS_FIMC |
251 | int exynos_drm_check_fimc_device(struct device *dev); | |
252 | #else | |
253 | static inline int exynos_drm_check_fimc_device(struct device *dev) | |
254 | { | |
255 | return 0; | |
256 | } | |
257 | #endif | |
258 | ||
a379df19 | 259 | int exynos_atomic_commit(struct drm_device *dev, struct drm_atomic_state *state, |
1b3f09d8 | 260 | bool nonblock); |
a379df19 | 261 | |
f37cd5e8 | 262 | |
f37cd5e8 | 263 | extern struct platform_driver fimd_driver; |
c8466a91 | 264 | extern struct platform_driver exynos5433_decon_driver; |
96976c3d | 265 | extern struct platform_driver decon_driver; |
1417f109 | 266 | extern struct platform_driver dp_driver; |
7eb8f069 | 267 | extern struct platform_driver dsi_driver; |
132a5b91 | 268 | extern struct platform_driver mixer_driver; |
f37cd5e8 | 269 | extern struct platform_driver hdmi_driver; |
b73d1230 | 270 | extern struct platform_driver vidi_driver; |
d7f1642c | 271 | extern struct platform_driver g2d_driver; |
16102edb | 272 | extern struct platform_driver fimc_driver; |
bea8a429 | 273 | extern struct platform_driver rotator_driver; |
01fb9185 | 274 | extern struct platform_driver scaler_driver; |
f2646380 | 275 | extern struct platform_driver gsc_driver; |
77bbd891 | 276 | extern struct platform_driver mic_driver; |
1c248b7d | 277 | #endif |