Commit | Line | Data |
---|---|---|
1c248b7d ID |
1 | /* exynos_drm_crtc.c |
2 | * | |
3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | |
4 | * Authors: | |
5 | * Inki Dae <inki.dae@samsung.com> | |
6 | * Joonyoung Shim <jy0922.shim@samsung.com> | |
7 | * Seung-Woo Kim <sw0312.kim@samsung.com> | |
8 | * | |
d81aecb5 ID |
9 | * This program is free software; you can redistribute it and/or modify it |
10 | * under the terms of the GNU General Public License as published by the | |
11 | * Free Software Foundation; either version 2 of the License, or (at your | |
12 | * option) any later version. | |
1c248b7d ID |
13 | */ |
14 | ||
760285e7 DH |
15 | #include <drm/drmP.h> |
16 | #include <drm/drm_crtc_helper.h> | |
1c248b7d | 17 | |
e30655d0 | 18 | #include "exynos_drm_crtc.h" |
1c248b7d | 19 | #include "exynos_drm_drv.h" |
1c248b7d | 20 | #include "exynos_drm_encoder.h" |
b5d2eb3b | 21 | #include "exynos_drm_plane.h" |
1c248b7d | 22 | |
1c248b7d ID |
23 | static void exynos_drm_crtc_dpms(struct drm_crtc *crtc, int mode) |
24 | { | |
d2716c89 | 25 | struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(crtc); |
080be03d | 26 | struct exynos_drm_manager *manager = exynos_crtc->manager; |
1c248b7d | 27 | |
d2716c89 JS |
28 | DRM_DEBUG_KMS("crtc[%d] mode[%d]\n", crtc->base.id, mode); |
29 | ||
ec05da95 ID |
30 | if (exynos_crtc->dpms == mode) { |
31 | DRM_DEBUG_KMS("desired dpms mode is same as previous one.\n"); | |
32 | return; | |
33 | } | |
34 | ||
20cd2640 ID |
35 | if (mode > DRM_MODE_DPMS_ON) { |
36 | /* wait for the completion of page flip. */ | |
e35d7223 YC |
37 | if (!wait_event_timeout(exynos_crtc->pending_flip_queue, |
38 | !atomic_read(&exynos_crtc->pending_flip), | |
39 | HZ/20)) | |
40 | atomic_set(&exynos_crtc->pending_flip, 0); | |
d6948b2f | 41 | drm_crtc_vblank_off(crtc); |
20cd2640 ID |
42 | } |
43 | ||
080be03d SP |
44 | if (manager->ops->dpms) |
45 | manager->ops->dpms(manager, mode); | |
46 | ||
cf5188ac | 47 | exynos_crtc->dpms = mode; |
d6948b2f AH |
48 | |
49 | if (mode == DRM_MODE_DPMS_ON) | |
50 | drm_crtc_vblank_on(crtc); | |
1c248b7d ID |
51 | } |
52 | ||
53 | static void exynos_drm_crtc_prepare(struct drm_crtc *crtc) | |
54 | { | |
1c248b7d ID |
55 | /* drm framework doesn't check NULL. */ |
56 | } | |
57 | ||
58 | static void exynos_drm_crtc_commit(struct drm_crtc *crtc) | |
59 | { | |
d2716c89 | 60 | struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(crtc); |
080be03d | 61 | struct exynos_drm_manager *manager = exynos_crtc->manager; |
9d5310c0 | 62 | struct exynos_drm_plane *exynos_plane = to_exynos_plane(crtc->primary); |
d2716c89 | 63 | |
50caf25c | 64 | exynos_drm_crtc_dpms(crtc, DRM_MODE_DPMS_ON); |
080be03d | 65 | |
9d5310c0 GP |
66 | if (manager->ops->win_commit) |
67 | manager->ops->win_commit(manager, exynos_plane->zpos); | |
080be03d SP |
68 | |
69 | if (manager->ops->commit) | |
70 | manager->ops->commit(manager); | |
71 | ||
72ed6ccd | 72 | exynos_plane_dpms(crtc->primary, DRM_MODE_DPMS_ON); |
1c248b7d ID |
73 | } |
74 | ||
75 | static bool | |
76 | exynos_drm_crtc_mode_fixup(struct drm_crtc *crtc, | |
e811f5ae | 77 | const struct drm_display_mode *mode, |
1c248b7d ID |
78 | struct drm_display_mode *adjusted_mode) |
79 | { | |
4b405269 SP |
80 | struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(crtc); |
81 | struct exynos_drm_manager *manager = exynos_crtc->manager; | |
82 | ||
83 | if (manager->ops->mode_fixup) | |
84 | return manager->ops->mode_fixup(manager, mode, adjusted_mode); | |
85 | ||
1c248b7d ID |
86 | return true; |
87 | } | |
88 | ||
89 | static int | |
90 | exynos_drm_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode, | |
91 | struct drm_display_mode *adjusted_mode, int x, int y, | |
92 | struct drm_framebuffer *old_fb) | |
93 | { | |
aeb29224 | 94 | struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(crtc); |
cd706aa8 | 95 | struct exynos_drm_manager *manager = exynos_crtc->manager; |
72ed6ccd | 96 | struct drm_framebuffer *fb = crtc->primary->fb; |
4070d212 JS |
97 | unsigned int crtc_w; |
98 | unsigned int crtc_h; | |
aeb29224 | 99 | |
1de425b0 ID |
100 | /* |
101 | * copy the mode data adjusted by mode_fixup() into crtc->mode | |
102 | * so that hardware can be seet to proper mode. | |
103 | */ | |
104 | memcpy(&crtc->mode, adjusted_mode, sizeof(*adjusted_mode)); | |
1c248b7d | 105 | |
72ed6ccd AH |
106 | crtc_w = fb->width - x; |
107 | crtc_h = fb->height - y; | |
4070d212 | 108 | |
cd706aa8 SP |
109 | if (manager->ops->mode_set) |
110 | manager->ops->mode_set(manager, &crtc->mode); | |
111 | ||
72ed6ccd AH |
112 | return exynos_plane_mode_set(crtc->primary, crtc, fb, 0, 0, |
113 | crtc_w, crtc_h, x, y, crtc_w, crtc_h); | |
1c248b7d ID |
114 | } |
115 | ||
fd092d7a | 116 | static int exynos_drm_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, |
1c248b7d ID |
117 | struct drm_framebuffer *old_fb) |
118 | { | |
4070d212 | 119 | struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(crtc); |
72ed6ccd | 120 | struct drm_framebuffer *fb = crtc->primary->fb; |
4070d212 JS |
121 | unsigned int crtc_w; |
122 | unsigned int crtc_h; | |
1c248b7d | 123 | |
32aeab17 ID |
124 | /* when framebuffer changing is requested, crtc's dpms should be on */ |
125 | if (exynos_crtc->dpms > DRM_MODE_DPMS_ON) { | |
126 | DRM_ERROR("failed framebuffer changing request.\n"); | |
127 | return -EPERM; | |
128 | } | |
129 | ||
72ed6ccd AH |
130 | crtc_w = fb->width - x; |
131 | crtc_h = fb->height - y; | |
4070d212 | 132 | |
0e0a649f GP |
133 | return exynos_update_plane(crtc->primary, crtc, fb, 0, 0, |
134 | crtc_w, crtc_h, x, y, crtc_w, crtc_h); | |
1c248b7d ID |
135 | } |
136 | ||
a365d9eb JS |
137 | static void exynos_drm_crtc_disable(struct drm_crtc *crtc) |
138 | { | |
a9c4cd21 SP |
139 | struct drm_plane *plane; |
140 | int ret; | |
a365d9eb | 141 | |
a365d9eb | 142 | exynos_drm_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); |
a9c4cd21 | 143 | |
0886327a | 144 | drm_for_each_legacy_plane(plane, &crtc->dev->mode_config.plane_list) { |
a9c4cd21 SP |
145 | if (plane->crtc != crtc) |
146 | continue; | |
147 | ||
148 | ret = plane->funcs->disable_plane(plane); | |
149 | if (ret) | |
150 | DRM_ERROR("Failed to disable plane %d\n", ret); | |
151 | } | |
a365d9eb JS |
152 | } |
153 | ||
1c248b7d ID |
154 | static struct drm_crtc_helper_funcs exynos_crtc_helper_funcs = { |
155 | .dpms = exynos_drm_crtc_dpms, | |
156 | .prepare = exynos_drm_crtc_prepare, | |
157 | .commit = exynos_drm_crtc_commit, | |
158 | .mode_fixup = exynos_drm_crtc_mode_fixup, | |
159 | .mode_set = exynos_drm_crtc_mode_set, | |
160 | .mode_set_base = exynos_drm_crtc_mode_set_base, | |
a365d9eb | 161 | .disable = exynos_drm_crtc_disable, |
1c248b7d ID |
162 | }; |
163 | ||
164 | static int exynos_drm_crtc_page_flip(struct drm_crtc *crtc, | |
ed8d1975 KP |
165 | struct drm_framebuffer *fb, |
166 | struct drm_pending_vblank_event *event, | |
167 | uint32_t page_flip_flags) | |
1c248b7d ID |
168 | { |
169 | struct drm_device *dev = crtc->dev; | |
170 | struct exynos_drm_private *dev_priv = dev->dev_private; | |
171 | struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(crtc); | |
f4510a27 | 172 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
8b9c4505 | 173 | unsigned int crtc_w, crtc_h; |
1c248b7d ID |
174 | int ret = -EINVAL; |
175 | ||
ef6223dc ID |
176 | /* when the page flip is requested, crtc's dpms should be on */ |
177 | if (exynos_crtc->dpms > DRM_MODE_DPMS_ON) { | |
178 | DRM_ERROR("failed page flip request.\n"); | |
179 | return -EINVAL; | |
180 | } | |
181 | ||
1c248b7d ID |
182 | mutex_lock(&dev->struct_mutex); |
183 | ||
ccf4d883 ID |
184 | if (event) { |
185 | /* | |
186 | * the pipe from user always is 0 so we can set pipe number | |
187 | * of current owner to event. | |
188 | */ | |
189 | event->pipe = exynos_crtc->pipe; | |
190 | ||
1c248b7d ID |
191 | ret = drm_vblank_get(dev, exynos_crtc->pipe); |
192 | if (ret) { | |
193 | DRM_DEBUG("failed to acquire vblank counter\n"); | |
ccf4d883 | 194 | |
1c248b7d ID |
195 | goto out; |
196 | } | |
197 | ||
85473328 | 198 | spin_lock_irq(&dev->event_lock); |
c5614ae3 ID |
199 | list_add_tail(&event->base.link, |
200 | &dev_priv->pageflip_event_list); | |
20cd2640 | 201 | atomic_set(&exynos_crtc->pending_flip, 1); |
85473328 | 202 | spin_unlock_irq(&dev->event_lock); |
c5614ae3 | 203 | |
f4510a27 | 204 | crtc->primary->fb = fb; |
8b9c4505 GP |
205 | crtc_w = fb->width - crtc->x; |
206 | crtc_h = fb->height - crtc->y; | |
207 | ret = exynos_update_plane(crtc->primary, crtc, fb, 0, 0, | |
208 | crtc_w, crtc_h, crtc->x, crtc->y, | |
209 | crtc_w, crtc_h); | |
1c248b7d | 210 | if (ret) { |
f4510a27 | 211 | crtc->primary->fb = old_fb; |
85473328 ID |
212 | |
213 | spin_lock_irq(&dev->event_lock); | |
1c248b7d | 214 | drm_vblank_put(dev, exynos_crtc->pipe); |
ccf4d883 | 215 | list_del(&event->base.link); |
e35d7223 | 216 | atomic_set(&exynos_crtc->pending_flip, 0); |
85473328 | 217 | spin_unlock_irq(&dev->event_lock); |
1c248b7d ID |
218 | |
219 | goto out; | |
220 | } | |
1c248b7d ID |
221 | } |
222 | out: | |
223 | mutex_unlock(&dev->struct_mutex); | |
224 | return ret; | |
225 | } | |
226 | ||
227 | static void exynos_drm_crtc_destroy(struct drm_crtc *crtc) | |
228 | { | |
229 | struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(crtc); | |
230 | struct exynos_drm_private *private = crtc->dev->dev_private; | |
231 | ||
1c248b7d ID |
232 | private->crtc[exynos_crtc->pipe] = NULL; |
233 | ||
234 | drm_crtc_cleanup(crtc); | |
235 | kfree(exynos_crtc); | |
236 | } | |
237 | ||
3b8d1cf8 JS |
238 | static int exynos_drm_crtc_set_property(struct drm_crtc *crtc, |
239 | struct drm_property *property, | |
240 | uint64_t val) | |
241 | { | |
242 | struct drm_device *dev = crtc->dev; | |
243 | struct exynos_drm_private *dev_priv = dev->dev_private; | |
244 | struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(crtc); | |
245 | ||
3b8d1cf8 JS |
246 | if (property == dev_priv->crtc_mode_property) { |
247 | enum exynos_crtc_mode mode = val; | |
248 | ||
249 | if (mode == exynos_crtc->mode) | |
250 | return 0; | |
251 | ||
252 | exynos_crtc->mode = mode; | |
253 | ||
254 | switch (mode) { | |
255 | case CRTC_MODE_NORMAL: | |
256 | exynos_drm_crtc_commit(crtc); | |
257 | break; | |
258 | case CRTC_MODE_BLANK: | |
72ed6ccd | 259 | exynos_plane_dpms(crtc->primary, DRM_MODE_DPMS_OFF); |
3b8d1cf8 JS |
260 | break; |
261 | default: | |
262 | break; | |
263 | } | |
264 | ||
265 | return 0; | |
266 | } | |
267 | ||
268 | return -EINVAL; | |
269 | } | |
270 | ||
1c248b7d ID |
271 | static struct drm_crtc_funcs exynos_crtc_funcs = { |
272 | .set_config = drm_crtc_helper_set_config, | |
273 | .page_flip = exynos_drm_crtc_page_flip, | |
274 | .destroy = exynos_drm_crtc_destroy, | |
3b8d1cf8 JS |
275 | .set_property = exynos_drm_crtc_set_property, |
276 | }; | |
277 | ||
278 | static const struct drm_prop_enum_list mode_names[] = { | |
279 | { CRTC_MODE_NORMAL, "normal" }, | |
280 | { CRTC_MODE_BLANK, "blank" }, | |
1c248b7d ID |
281 | }; |
282 | ||
3b8d1cf8 JS |
283 | static void exynos_drm_crtc_attach_mode_property(struct drm_crtc *crtc) |
284 | { | |
285 | struct drm_device *dev = crtc->dev; | |
286 | struct exynos_drm_private *dev_priv = dev->dev_private; | |
287 | struct drm_property *prop; | |
288 | ||
3b8d1cf8 JS |
289 | prop = dev_priv->crtc_mode_property; |
290 | if (!prop) { | |
291 | prop = drm_property_create_enum(dev, 0, "mode", mode_names, | |
292 | ARRAY_SIZE(mode_names)); | |
293 | if (!prop) | |
294 | return; | |
295 | ||
296 | dev_priv->crtc_mode_property = prop; | |
297 | } | |
298 | ||
299 | drm_object_attach_property(&crtc->base, prop, 0); | |
300 | } | |
301 | ||
080be03d | 302 | int exynos_drm_crtc_create(struct exynos_drm_manager *manager) |
1c248b7d ID |
303 | { |
304 | struct exynos_drm_crtc *exynos_crtc; | |
72ed6ccd | 305 | struct drm_plane *plane; |
080be03d | 306 | struct exynos_drm_private *private = manager->drm_dev->dev_private; |
1c248b7d | 307 | struct drm_crtc *crtc; |
72ed6ccd | 308 | int ret; |
1c248b7d | 309 | |
1c248b7d | 310 | exynos_crtc = kzalloc(sizeof(*exynos_crtc), GFP_KERNEL); |
38bb5253 | 311 | if (!exynos_crtc) |
1c248b7d | 312 | return -ENOMEM; |
1c248b7d | 313 | |
20cd2640 ID |
314 | init_waitqueue_head(&exynos_crtc->pending_flip_queue); |
315 | atomic_set(&exynos_crtc->pending_flip, 0); | |
080be03d SP |
316 | |
317 | exynos_crtc->dpms = DRM_MODE_DPMS_OFF; | |
318 | exynos_crtc->manager = manager; | |
319 | exynos_crtc->pipe = manager->pipe; | |
72ed6ccd AH |
320 | plane = exynos_plane_init(manager->drm_dev, 1 << manager->pipe, |
321 | DRM_PLANE_TYPE_PRIMARY); | |
322 | if (IS_ERR(plane)) { | |
323 | ret = PTR_ERR(plane); | |
324 | goto err_plane; | |
b5d2eb3b JS |
325 | } |
326 | ||
f37cd5e8 | 327 | manager->crtc = &exynos_crtc->drm_crtc; |
1c248b7d ID |
328 | crtc = &exynos_crtc->drm_crtc; |
329 | ||
080be03d | 330 | private->crtc[manager->pipe] = crtc; |
1c248b7d | 331 | |
72ed6ccd AH |
332 | ret = drm_crtc_init_with_planes(manager->drm_dev, crtc, plane, NULL, |
333 | &exynos_crtc_funcs); | |
334 | if (ret < 0) | |
335 | goto err_crtc; | |
336 | ||
1c248b7d ID |
337 | drm_crtc_helper_add(crtc, &exynos_crtc_helper_funcs); |
338 | ||
3b8d1cf8 JS |
339 | exynos_drm_crtc_attach_mode_property(crtc); |
340 | ||
1c248b7d | 341 | return 0; |
72ed6ccd AH |
342 | |
343 | err_crtc: | |
344 | plane->funcs->destroy(plane); | |
345 | err_plane: | |
346 | kfree(exynos_crtc); | |
347 | return ret; | |
1c248b7d ID |
348 | } |
349 | ||
080be03d | 350 | int exynos_drm_crtc_enable_vblank(struct drm_device *dev, int pipe) |
1c248b7d ID |
351 | { |
352 | struct exynos_drm_private *private = dev->dev_private; | |
ec05da95 | 353 | struct exynos_drm_crtc *exynos_crtc = |
080be03d SP |
354 | to_exynos_crtc(private->crtc[pipe]); |
355 | struct exynos_drm_manager *manager = exynos_crtc->manager; | |
1c248b7d | 356 | |
ec05da95 ID |
357 | if (exynos_crtc->dpms != DRM_MODE_DPMS_ON) |
358 | return -EPERM; | |
359 | ||
080be03d SP |
360 | if (manager->ops->enable_vblank) |
361 | manager->ops->enable_vblank(manager); | |
1c248b7d ID |
362 | |
363 | return 0; | |
364 | } | |
365 | ||
080be03d | 366 | void exynos_drm_crtc_disable_vblank(struct drm_device *dev, int pipe) |
1c248b7d ID |
367 | { |
368 | struct exynos_drm_private *private = dev->dev_private; | |
ec05da95 | 369 | struct exynos_drm_crtc *exynos_crtc = |
080be03d SP |
370 | to_exynos_crtc(private->crtc[pipe]); |
371 | struct exynos_drm_manager *manager = exynos_crtc->manager; | |
1c248b7d | 372 | |
ec05da95 ID |
373 | if (exynos_crtc->dpms != DRM_MODE_DPMS_ON) |
374 | return; | |
375 | ||
080be03d SP |
376 | if (manager->ops->disable_vblank) |
377 | manager->ops->disable_vblank(manager); | |
1c248b7d | 378 | } |
663d8766 | 379 | |
080be03d | 380 | void exynos_drm_crtc_finish_pageflip(struct drm_device *dev, int pipe) |
663d8766 RS |
381 | { |
382 | struct exynos_drm_private *dev_priv = dev->dev_private; | |
383 | struct drm_pending_vblank_event *e, *t; | |
080be03d | 384 | struct drm_crtc *drm_crtc = dev_priv->crtc[pipe]; |
20cd2640 | 385 | struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(drm_crtc); |
663d8766 RS |
386 | unsigned long flags; |
387 | ||
663d8766 RS |
388 | spin_lock_irqsave(&dev->event_lock, flags); |
389 | ||
390 | list_for_each_entry_safe(e, t, &dev_priv->pageflip_event_list, | |
391 | base.link) { | |
392 | /* if event's pipe isn't same as crtc then ignore it. */ | |
080be03d | 393 | if (pipe != e->pipe) |
663d8766 RS |
394 | continue; |
395 | ||
c5cca97f RC |
396 | list_del(&e->base.link); |
397 | drm_send_vblank_event(dev, -1, e); | |
080be03d | 398 | drm_vblank_put(dev, pipe); |
20cd2640 ID |
399 | atomic_set(&exynos_crtc->pending_flip, 0); |
400 | wake_up(&exynos_crtc->pending_flip_queue); | |
663d8766 RS |
401 | } |
402 | ||
403 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
404 | } | |
080be03d | 405 | |
080be03d SP |
406 | void exynos_drm_crtc_complete_scanout(struct drm_framebuffer *fb) |
407 | { | |
408 | struct exynos_drm_manager *manager; | |
409 | struct drm_device *dev = fb->dev; | |
410 | struct drm_crtc *crtc; | |
411 | ||
412 | /* | |
413 | * make sure that overlay data are updated to real hardware | |
414 | * for all encoders. | |
415 | */ | |
416 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
417 | manager = to_exynos_crtc(crtc)->manager; | |
418 | ||
419 | /* | |
420 | * wait for vblank interrupt | |
421 | * - this makes sure that overlay data are updated to | |
422 | * real hardware. | |
423 | */ | |
424 | if (manager->ops->wait_for_vblank) | |
425 | manager->ops->wait_for_vblank(manager); | |
426 | } | |
427 | } | |
f37cd5e8 ID |
428 | |
429 | int exynos_drm_crtc_get_pipe_from_type(struct drm_device *drm_dev, | |
430 | unsigned int out_type) | |
431 | { | |
432 | struct drm_crtc *crtc; | |
433 | ||
434 | list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { | |
435 | struct exynos_drm_crtc *exynos_crtc; | |
436 | ||
437 | exynos_crtc = to_exynos_crtc(crtc); | |
438 | if (exynos_crtc->manager->type == out_type) | |
439 | return exynos_crtc->manager->pipe; | |
440 | } | |
441 | ||
442 | return -EPERM; | |
443 | } | |
5595d4d8 YC |
444 | |
445 | void exynos_drm_crtc_te_handler(struct drm_crtc *crtc) | |
446 | { | |
447 | struct exynos_drm_manager *manager = to_exynos_crtc(crtc)->manager; | |
448 | ||
449 | if (manager->ops->te_handler) | |
450 | manager->ops->te_handler(manager); | |
451 | } |