Commit | Line | Data |
---|---|---|
e9474be4 JH |
1 | /* |
2 | * Samsung SoC DP (Display Port) interface driver. | |
3 | * | |
4 | * Copyright (C) 2012 Samsung Electronics Co., Ltd. | |
5 | * Author: Jingoo Han <jg1.han@samsung.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License as published by the | |
9 | * Free Software Foundation; either version 2 of the License, or (at your | |
10 | * option) any later version. | |
11 | */ | |
12 | ||
13 | #include <linux/module.h> | |
14 | #include <linux/platform_device.h> | |
e9474be4 JH |
15 | #include <linux/err.h> |
16 | #include <linux/clk.h> | |
17 | #include <linux/io.h> | |
18 | #include <linux/interrupt.h> | |
c4e235c2 | 19 | #include <linux/of.h> |
b8b52471 | 20 | #include <linux/of_gpio.h> |
80185567 | 21 | #include <linux/of_graph.h> |
b8b52471 | 22 | #include <linux/gpio.h> |
f37cd5e8 | 23 | #include <linux/component.h> |
8114fabc | 24 | #include <linux/phy/phy.h> |
1417f109 SP |
25 | #include <video/of_display_timing.h> |
26 | #include <video/of_videomode.h> | |
e9474be4 | 27 | |
1417f109 | 28 | #include <drm/drmP.h> |
caa5d1e5 SP |
29 | #include <drm/drm_crtc.h> |
30 | #include <drm/drm_crtc_helper.h> | |
4ea9526b | 31 | #include <drm/drm_atomic_helper.h> |
5f1dcd8b | 32 | #include <drm/drm_panel.h> |
1417f109 | 33 | |
e9474be4 JH |
34 | #include "exynos_dp_core.h" |
35 | ||
caa5d1e5 SP |
36 | #define ctx_from_connector(c) container_of(c, struct exynos_dp_device, \ |
37 | connector) | |
38 | ||
1c363c7c KK |
39 | static inline struct exynos_drm_crtc *dp_to_crtc(struct exynos_dp_device *dp) |
40 | { | |
cf67cc9a | 41 | return to_exynos_crtc(dp->encoder.base.crtc); |
1c363c7c KK |
42 | } |
43 | ||
cf67cc9a GP |
44 | static inline struct exynos_dp_device *encoder_to_dp( |
45 | struct exynos_drm_encoder *e) | |
63b3be32 | 46 | { |
cf67cc9a | 47 | return container_of(e, struct exynos_dp_device, encoder); |
63b3be32 AH |
48 | } |
49 | ||
1634ba25 SP |
50 | struct bridge_init { |
51 | struct i2c_client *client; | |
52 | struct device_node *node; | |
53 | }; | |
54 | ||
5f1dcd8b | 55 | static void exynos_dp_init_dp(struct exynos_dp_device *dp) |
e9474be4 JH |
56 | { |
57 | exynos_dp_reset(dp); | |
58 | ||
24db03a8 JH |
59 | exynos_dp_swreset(dp); |
60 | ||
75435c74 JH |
61 | exynos_dp_init_analog_param(dp); |
62 | exynos_dp_init_interrupt(dp); | |
63 | ||
e9474be4 JH |
64 | /* SW defined function Normal operation */ |
65 | exynos_dp_enable_sw_function(dp); | |
66 | ||
67 | exynos_dp_config_interrupt(dp); | |
68 | exynos_dp_init_analog_func(dp); | |
69 | ||
70 | exynos_dp_init_hpd(dp); | |
71 | exynos_dp_init_aux(dp); | |
e9474be4 JH |
72 | } |
73 | ||
74 | static int exynos_dp_detect_hpd(struct exynos_dp_device *dp) | |
75 | { | |
76 | int timeout_loop = 0; | |
77 | ||
e9474be4 JH |
78 | while (exynos_dp_get_plug_in_status(dp) != 0) { |
79 | timeout_loop++; | |
80 | if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) { | |
81 | dev_err(dp->dev, "failed to get hpd plug status\n"); | |
82 | return -ETIMEDOUT; | |
83 | } | |
a2c81bc1 | 84 | usleep_range(10, 11); |
e9474be4 JH |
85 | } |
86 | ||
87 | return 0; | |
88 | } | |
89 | ||
90 | static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data) | |
91 | { | |
92 | int i; | |
93 | unsigned char sum = 0; | |
94 | ||
95 | for (i = 0; i < EDID_BLOCK_LENGTH; i++) | |
96 | sum = sum + edid_data[i]; | |
97 | ||
98 | return sum; | |
99 | } | |
100 | ||
101 | static int exynos_dp_read_edid(struct exynos_dp_device *dp) | |
102 | { | |
103 | unsigned char edid[EDID_BLOCK_LENGTH * 2]; | |
104 | unsigned int extend_block = 0; | |
105 | unsigned char sum; | |
106 | unsigned char test_vector; | |
107 | int retval; | |
108 | ||
109 | /* | |
110 | * EDID device address is 0x50. | |
111 | * However, if necessary, you must have set upper address | |
112 | * into E-EDID in I2C device, 0x30. | |
113 | */ | |
114 | ||
115 | /* Read Extension Flag, Number of 128-byte EDID extension blocks */ | |
99f54152 | 116 | retval = exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR, |
e9474be4 JH |
117 | EDID_EXTENSION_FLAG, |
118 | &extend_block); | |
99f54152 SP |
119 | if (retval) |
120 | return retval; | |
e9474be4 JH |
121 | |
122 | if (extend_block > 0) { | |
123 | dev_dbg(dp->dev, "EDID data includes a single extension!\n"); | |
124 | ||
125 | /* Read EDID data */ | |
126 | retval = exynos_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR, | |
127 | EDID_HEADER_PATTERN, | |
128 | EDID_BLOCK_LENGTH, | |
129 | &edid[EDID_HEADER_PATTERN]); | |
130 | if (retval != 0) { | |
131 | dev_err(dp->dev, "EDID Read failed!\n"); | |
132 | return -EIO; | |
133 | } | |
134 | sum = exynos_dp_calc_edid_check_sum(edid); | |
135 | if (sum != 0) { | |
136 | dev_err(dp->dev, "EDID bad checksum!\n"); | |
137 | return -EIO; | |
138 | } | |
139 | ||
140 | /* Read additional EDID data */ | |
141 | retval = exynos_dp_read_bytes_from_i2c(dp, | |
142 | I2C_EDID_DEVICE_ADDR, | |
143 | EDID_BLOCK_LENGTH, | |
144 | EDID_BLOCK_LENGTH, | |
145 | &edid[EDID_BLOCK_LENGTH]); | |
146 | if (retval != 0) { | |
147 | dev_err(dp->dev, "EDID Read failed!\n"); | |
148 | return -EIO; | |
149 | } | |
150 | sum = exynos_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]); | |
151 | if (sum != 0) { | |
152 | dev_err(dp->dev, "EDID bad checksum!\n"); | |
153 | return -EIO; | |
154 | } | |
155 | ||
073ea2ae | 156 | exynos_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST, |
e9474be4 | 157 | &test_vector); |
073ea2ae | 158 | if (test_vector & DP_TEST_LINK_EDID_READ) { |
e9474be4 | 159 | exynos_dp_write_byte_to_dpcd(dp, |
073ea2ae | 160 | DP_TEST_EDID_CHECKSUM, |
e9474be4 JH |
161 | edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]); |
162 | exynos_dp_write_byte_to_dpcd(dp, | |
073ea2ae JH |
163 | DP_TEST_RESPONSE, |
164 | DP_TEST_EDID_CHECKSUM_WRITE); | |
e9474be4 JH |
165 | } |
166 | } else { | |
167 | dev_info(dp->dev, "EDID data does not include any extensions.\n"); | |
168 | ||
169 | /* Read EDID data */ | |
170 | retval = exynos_dp_read_bytes_from_i2c(dp, | |
171 | I2C_EDID_DEVICE_ADDR, | |
172 | EDID_HEADER_PATTERN, | |
173 | EDID_BLOCK_LENGTH, | |
174 | &edid[EDID_HEADER_PATTERN]); | |
175 | if (retval != 0) { | |
176 | dev_err(dp->dev, "EDID Read failed!\n"); | |
177 | return -EIO; | |
178 | } | |
179 | sum = exynos_dp_calc_edid_check_sum(edid); | |
180 | if (sum != 0) { | |
181 | dev_err(dp->dev, "EDID bad checksum!\n"); | |
182 | return -EIO; | |
183 | } | |
184 | ||
185 | exynos_dp_read_byte_from_dpcd(dp, | |
073ea2ae | 186 | DP_TEST_REQUEST, |
e9474be4 | 187 | &test_vector); |
073ea2ae | 188 | if (test_vector & DP_TEST_LINK_EDID_READ) { |
e9474be4 | 189 | exynos_dp_write_byte_to_dpcd(dp, |
073ea2ae | 190 | DP_TEST_EDID_CHECKSUM, |
e9474be4 JH |
191 | edid[EDID_CHECKSUM]); |
192 | exynos_dp_write_byte_to_dpcd(dp, | |
073ea2ae JH |
193 | DP_TEST_RESPONSE, |
194 | DP_TEST_EDID_CHECKSUM_WRITE); | |
e9474be4 JH |
195 | } |
196 | } | |
197 | ||
b0f155ad | 198 | dev_dbg(dp->dev, "EDID Read success!\n"); |
e9474be4 JH |
199 | return 0; |
200 | } | |
201 | ||
202 | static int exynos_dp_handle_edid(struct exynos_dp_device *dp) | |
203 | { | |
204 | u8 buf[12]; | |
205 | int i; | |
206 | int retval; | |
207 | ||
073ea2ae JH |
208 | /* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */ |
209 | retval = exynos_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV, | |
99f54152 SP |
210 | 12, buf); |
211 | if (retval) | |
212 | return retval; | |
e9474be4 JH |
213 | |
214 | /* Read EDID */ | |
215 | for (i = 0; i < 3; i++) { | |
216 | retval = exynos_dp_read_edid(dp); | |
99f54152 | 217 | if (!retval) |
e9474be4 JH |
218 | break; |
219 | } | |
220 | ||
221 | return retval; | |
222 | } | |
223 | ||
224 | static void exynos_dp_enable_rx_to_enhanced_mode(struct exynos_dp_device *dp, | |
225 | bool enable) | |
226 | { | |
227 | u8 data; | |
228 | ||
073ea2ae | 229 | exynos_dp_read_byte_from_dpcd(dp, DP_LANE_COUNT_SET, &data); |
e9474be4 JH |
230 | |
231 | if (enable) | |
073ea2ae JH |
232 | exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET, |
233 | DP_LANE_COUNT_ENHANCED_FRAME_EN | | |
e9474be4 JH |
234 | DPCD_LANE_COUNT_SET(data)); |
235 | else | |
073ea2ae | 236 | exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET, |
e9474be4 JH |
237 | DPCD_LANE_COUNT_SET(data)); |
238 | } | |
239 | ||
240 | static int exynos_dp_is_enhanced_mode_available(struct exynos_dp_device *dp) | |
241 | { | |
242 | u8 data; | |
243 | int retval; | |
244 | ||
073ea2ae | 245 | exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data); |
e9474be4 JH |
246 | retval = DPCD_ENHANCED_FRAME_CAP(data); |
247 | ||
248 | return retval; | |
249 | } | |
250 | ||
251 | static void exynos_dp_set_enhanced_mode(struct exynos_dp_device *dp) | |
252 | { | |
253 | u8 data; | |
254 | ||
255 | data = exynos_dp_is_enhanced_mode_available(dp); | |
256 | exynos_dp_enable_rx_to_enhanced_mode(dp, data); | |
257 | exynos_dp_enable_enhanced_mode(dp, data); | |
258 | } | |
259 | ||
260 | static void exynos_dp_training_pattern_dis(struct exynos_dp_device *dp) | |
261 | { | |
262 | exynos_dp_set_training_pattern(dp, DP_NONE); | |
263 | ||
264 | exynos_dp_write_byte_to_dpcd(dp, | |
073ea2ae JH |
265 | DP_TRAINING_PATTERN_SET, |
266 | DP_TRAINING_PATTERN_DISABLE); | |
e9474be4 JH |
267 | } |
268 | ||
269 | static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp, | |
270 | int pre_emphasis, int lane) | |
271 | { | |
272 | switch (lane) { | |
273 | case 0: | |
274 | exynos_dp_set_lane0_pre_emphasis(dp, pre_emphasis); | |
275 | break; | |
276 | case 1: | |
277 | exynos_dp_set_lane1_pre_emphasis(dp, pre_emphasis); | |
278 | break; | |
279 | ||
280 | case 2: | |
281 | exynos_dp_set_lane2_pre_emphasis(dp, pre_emphasis); | |
282 | break; | |
283 | ||
284 | case 3: | |
285 | exynos_dp_set_lane3_pre_emphasis(dp, pre_emphasis); | |
286 | break; | |
287 | } | |
288 | } | |
289 | ||
ace2d7f2 | 290 | static int exynos_dp_link_start(struct exynos_dp_device *dp) |
e9474be4 | 291 | { |
d5c0eed0 | 292 | u8 buf[4]; |
49ce41f3 | 293 | int lane, lane_count, pll_tries, retval; |
e9474be4 JH |
294 | |
295 | lane_count = dp->link_train.lane_count; | |
296 | ||
297 | dp->link_train.lt_state = CLOCK_RECOVERY; | |
298 | dp->link_train.eq_loop = 0; | |
299 | ||
300 | for (lane = 0; lane < lane_count; lane++) | |
301 | dp->link_train.cr_loop[lane] = 0; | |
302 | ||
e9474be4 JH |
303 | /* Set link rate and count as you want to establish*/ |
304 | exynos_dp_set_link_bandwidth(dp, dp->link_train.link_rate); | |
305 | exynos_dp_set_lane_count(dp, dp->link_train.lane_count); | |
306 | ||
307 | /* Setup RX configuration */ | |
308 | buf[0] = dp->link_train.link_rate; | |
309 | buf[1] = dp->link_train.lane_count; | |
073ea2ae | 310 | retval = exynos_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET, |
e9474be4 | 311 | 2, buf); |
ace2d7f2 SP |
312 | if (retval) |
313 | return retval; | |
e9474be4 JH |
314 | |
315 | /* Set TX pre-emphasis to minimum */ | |
316 | for (lane = 0; lane < lane_count; lane++) | |
317 | exynos_dp_set_lane_lane_pre_emphasis(dp, | |
318 | PRE_EMPHASIS_LEVEL_0, lane); | |
319 | ||
49ce41f3 SP |
320 | /* Wait for PLL lock */ |
321 | pll_tries = 0; | |
322 | while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { | |
323 | if (pll_tries == DP_TIMEOUT_LOOP_COUNT) { | |
324 | dev_err(dp->dev, "Wait for PLL lock timed out\n"); | |
325 | return -ETIMEDOUT; | |
326 | } | |
327 | ||
328 | pll_tries++; | |
329 | usleep_range(90, 120); | |
330 | } | |
331 | ||
e9474be4 JH |
332 | /* Set training pattern 1 */ |
333 | exynos_dp_set_training_pattern(dp, TRAINING_PTN1); | |
334 | ||
335 | /* Set RX training pattern */ | |
fadec4b7 | 336 | retval = exynos_dp_write_byte_to_dpcd(dp, |
073ea2ae JH |
337 | DP_TRAINING_PATTERN_SET, |
338 | DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1); | |
fadec4b7 SP |
339 | if (retval) |
340 | return retval; | |
e9474be4 JH |
341 | |
342 | for (lane = 0; lane < lane_count; lane++) | |
0ded9254 SJ |
343 | buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 | |
344 | DP_TRAIN_VOLTAGE_SWING_LEVEL_0; | |
fadec4b7 | 345 | |
073ea2ae | 346 | retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET, |
fadec4b7 | 347 | lane_count, buf); |
ace2d7f2 SP |
348 | |
349 | return retval; | |
e9474be4 JH |
350 | } |
351 | ||
d5c0eed0 | 352 | static unsigned char exynos_dp_get_lane_status(u8 link_status[2], int lane) |
e9474be4 JH |
353 | { |
354 | int shift = (lane & 1) * 4; | |
355 | u8 link_value = link_status[lane>>1]; | |
356 | ||
357 | return (link_value >> shift) & 0xf; | |
358 | } | |
359 | ||
d5c0eed0 | 360 | static int exynos_dp_clock_recovery_ok(u8 link_status[2], int lane_count) |
e9474be4 JH |
361 | { |
362 | int lane; | |
363 | u8 lane_status; | |
364 | ||
365 | for (lane = 0; lane < lane_count; lane++) { | |
366 | lane_status = exynos_dp_get_lane_status(link_status, lane); | |
073ea2ae | 367 | if ((lane_status & DP_LANE_CR_DONE) == 0) |
e9474be4 JH |
368 | return -EINVAL; |
369 | } | |
370 | return 0; | |
371 | } | |
372 | ||
fadec4b7 SP |
373 | static int exynos_dp_channel_eq_ok(u8 link_status[2], u8 link_align, |
374 | int lane_count) | |
e9474be4 JH |
375 | { |
376 | int lane; | |
e9474be4 JH |
377 | u8 lane_status; |
378 | ||
073ea2ae | 379 | if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0) |
e9474be4 JH |
380 | return -EINVAL; |
381 | ||
382 | for (lane = 0; lane < lane_count; lane++) { | |
fadec4b7 | 383 | lane_status = exynos_dp_get_lane_status(link_status, lane); |
073ea2ae JH |
384 | lane_status &= DP_CHANNEL_EQ_BITS; |
385 | if (lane_status != DP_CHANNEL_EQ_BITS) | |
e9474be4 JH |
386 | return -EINVAL; |
387 | } | |
d5c0eed0 | 388 | |
e9474be4 JH |
389 | return 0; |
390 | } | |
391 | ||
392 | static unsigned char exynos_dp_get_adjust_request_voltage(u8 adjust_request[2], | |
393 | int lane) | |
394 | { | |
395 | int shift = (lane & 1) * 4; | |
396 | u8 link_value = adjust_request[lane>>1]; | |
397 | ||
398 | return (link_value >> shift) & 0x3; | |
399 | } | |
400 | ||
401 | static unsigned char exynos_dp_get_adjust_request_pre_emphasis( | |
402 | u8 adjust_request[2], | |
403 | int lane) | |
404 | { | |
405 | int shift = (lane & 1) * 4; | |
406 | u8 link_value = adjust_request[lane>>1]; | |
407 | ||
408 | return ((link_value >> shift) & 0xc) >> 2; | |
409 | } | |
410 | ||
411 | static void exynos_dp_set_lane_link_training(struct exynos_dp_device *dp, | |
412 | u8 training_lane_set, int lane) | |
413 | { | |
414 | switch (lane) { | |
415 | case 0: | |
416 | exynos_dp_set_lane0_link_training(dp, training_lane_set); | |
417 | break; | |
418 | case 1: | |
419 | exynos_dp_set_lane1_link_training(dp, training_lane_set); | |
420 | break; | |
421 | ||
422 | case 2: | |
423 | exynos_dp_set_lane2_link_training(dp, training_lane_set); | |
424 | break; | |
425 | ||
426 | case 3: | |
427 | exynos_dp_set_lane3_link_training(dp, training_lane_set); | |
428 | break; | |
429 | } | |
430 | } | |
431 | ||
432 | static unsigned int exynos_dp_get_lane_link_training( | |
433 | struct exynos_dp_device *dp, | |
434 | int lane) | |
435 | { | |
436 | u32 reg; | |
437 | ||
438 | switch (lane) { | |
439 | case 0: | |
440 | reg = exynos_dp_get_lane0_link_training(dp); | |
441 | break; | |
442 | case 1: | |
443 | reg = exynos_dp_get_lane1_link_training(dp); | |
444 | break; | |
445 | case 2: | |
446 | reg = exynos_dp_get_lane2_link_training(dp); | |
447 | break; | |
448 | case 3: | |
449 | reg = exynos_dp_get_lane3_link_training(dp); | |
450 | break; | |
64c43dfa JH |
451 | default: |
452 | WARN_ON(1); | |
453 | return 0; | |
e9474be4 JH |
454 | } |
455 | ||
456 | return reg; | |
457 | } | |
458 | ||
459 | static void exynos_dp_reduce_link_rate(struct exynos_dp_device *dp) | |
460 | { | |
d5c0eed0 JH |
461 | exynos_dp_training_pattern_dis(dp); |
462 | exynos_dp_set_enhanced_mode(dp); | |
e9474be4 | 463 | |
d5c0eed0 | 464 | dp->link_train.lt_state = FAILED; |
e9474be4 JH |
465 | } |
466 | ||
fadec4b7 SP |
467 | static void exynos_dp_get_adjust_training_lane(struct exynos_dp_device *dp, |
468 | u8 adjust_request[2]) | |
469 | { | |
470 | int lane, lane_count; | |
471 | u8 voltage_swing, pre_emphasis, training_lane; | |
472 | ||
473 | lane_count = dp->link_train.lane_count; | |
474 | for (lane = 0; lane < lane_count; lane++) { | |
475 | voltage_swing = exynos_dp_get_adjust_request_voltage( | |
476 | adjust_request, lane); | |
477 | pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis( | |
478 | adjust_request, lane); | |
479 | training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) | | |
480 | DPCD_PRE_EMPHASIS_SET(pre_emphasis); | |
481 | ||
482 | if (voltage_swing == VOLTAGE_LEVEL_3) | |
073ea2ae | 483 | training_lane |= DP_TRAIN_MAX_SWING_REACHED; |
fadec4b7 | 484 | if (pre_emphasis == PRE_EMPHASIS_LEVEL_3) |
073ea2ae | 485 | training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; |
fadec4b7 SP |
486 | |
487 | dp->link_train.training_lane[lane] = training_lane; | |
488 | } | |
489 | } | |
490 | ||
e9474be4 JH |
491 | static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp) |
492 | { | |
ace2d7f2 | 493 | int lane, lane_count, retval; |
fadec4b7 SP |
494 | u8 voltage_swing, pre_emphasis, training_lane; |
495 | u8 link_status[2], adjust_request[2]; | |
e9474be4 | 496 | |
a2c81bc1 | 497 | usleep_range(100, 101); |
e9474be4 | 498 | |
e9474be4 JH |
499 | lane_count = dp->link_train.lane_count; |
500 | ||
fadec4b7 | 501 | retval = exynos_dp_read_bytes_from_dpcd(dp, |
073ea2ae | 502 | DP_LANE0_1_STATUS, 2, link_status); |
fadec4b7 SP |
503 | if (retval) |
504 | return retval; | |
505 | ||
506 | retval = exynos_dp_read_bytes_from_dpcd(dp, | |
073ea2ae | 507 | DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request); |
ace2d7f2 SP |
508 | if (retval) |
509 | return retval; | |
d5c0eed0 | 510 | |
e9474be4 JH |
511 | if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) { |
512 | /* set training pattern 2 for EQ */ | |
513 | exynos_dp_set_training_pattern(dp, TRAINING_PTN2); | |
514 | ||
ace2d7f2 | 515 | retval = exynos_dp_write_byte_to_dpcd(dp, |
073ea2ae JH |
516 | DP_TRAINING_PATTERN_SET, |
517 | DP_LINK_SCRAMBLING_DISABLE | | |
518 | DP_TRAINING_PATTERN_2); | |
ace2d7f2 SP |
519 | if (retval) |
520 | return retval; | |
d5c0eed0 JH |
521 | |
522 | dev_info(dp->dev, "Link Training Clock Recovery success\n"); | |
523 | dp->link_train.lt_state = EQUALIZER_TRAINING; | |
524 | } else { | |
e9474be4 JH |
525 | for (lane = 0; lane < lane_count; lane++) { |
526 | training_lane = exynos_dp_get_lane_link_training( | |
527 | dp, lane); | |
528 | voltage_swing = exynos_dp_get_adjust_request_voltage( | |
529 | adjust_request, lane); | |
530 | pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis( | |
531 | adjust_request, lane); | |
e9474be4 | 532 | |
fadec4b7 SP |
533 | if (DPCD_VOLTAGE_SWING_GET(training_lane) == |
534 | voltage_swing && | |
535 | DPCD_PRE_EMPHASIS_GET(training_lane) == | |
536 | pre_emphasis) | |
d5c0eed0 | 537 | dp->link_train.cr_loop[lane]++; |
d5c0eed0 | 538 | |
fadec4b7 SP |
539 | if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP || |
540 | voltage_swing == VOLTAGE_LEVEL_3 || | |
541 | pre_emphasis == PRE_EMPHASIS_LEVEL_3) { | |
542 | dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n", | |
543 | dp->link_train.cr_loop[lane], | |
544 | voltage_swing, pre_emphasis); | |
545 | exynos_dp_reduce_link_rate(dp); | |
546 | return -EIO; | |
547 | } | |
548 | } | |
549 | } | |
d5c0eed0 | 550 | |
fadec4b7 | 551 | exynos_dp_get_adjust_training_lane(dp, adjust_request); |
d5c0eed0 | 552 | |
fadec4b7 SP |
553 | for (lane = 0; lane < lane_count; lane++) |
554 | exynos_dp_set_lane_link_training(dp, | |
555 | dp->link_train.training_lane[lane], lane); | |
d5c0eed0 | 556 | |
fadec4b7 | 557 | retval = exynos_dp_write_bytes_to_dpcd(dp, |
073ea2ae | 558 | DP_TRAINING_LANE0_SET, lane_count, |
fadec4b7 SP |
559 | dp->link_train.training_lane); |
560 | if (retval) | |
561 | return retval; | |
e9474be4 | 562 | |
ace2d7f2 | 563 | return retval; |
e9474be4 JH |
564 | } |
565 | ||
566 | static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp) | |
567 | { | |
ace2d7f2 | 568 | int lane, lane_count, retval; |
e9474be4 | 569 | u32 reg; |
fadec4b7 | 570 | u8 link_align, link_status[2], adjust_request[2]; |
e9474be4 | 571 | |
a2c81bc1 | 572 | usleep_range(400, 401); |
e9474be4 | 573 | |
e9474be4 JH |
574 | lane_count = dp->link_train.lane_count; |
575 | ||
fadec4b7 | 576 | retval = exynos_dp_read_bytes_from_dpcd(dp, |
073ea2ae | 577 | DP_LANE0_1_STATUS, 2, link_status); |
ace2d7f2 SP |
578 | if (retval) |
579 | return retval; | |
d5c0eed0 | 580 | |
fadec4b7 SP |
581 | if (exynos_dp_clock_recovery_ok(link_status, lane_count)) { |
582 | exynos_dp_reduce_link_rate(dp); | |
583 | return -EIO; | |
584 | } | |
d5c0eed0 | 585 | |
fadec4b7 | 586 | retval = exynos_dp_read_bytes_from_dpcd(dp, |
073ea2ae | 587 | DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request); |
fadec4b7 SP |
588 | if (retval) |
589 | return retval; | |
ace2d7f2 | 590 | |
fadec4b7 | 591 | retval = exynos_dp_read_byte_from_dpcd(dp, |
073ea2ae | 592 | DP_LANE_ALIGN_STATUS_UPDATED, &link_align); |
fadec4b7 SP |
593 | if (retval) |
594 | return retval; | |
d5c0eed0 | 595 | |
fadec4b7 | 596 | exynos_dp_get_adjust_training_lane(dp, adjust_request); |
d5c0eed0 | 597 | |
fadec4b7 SP |
598 | if (!exynos_dp_channel_eq_ok(link_status, link_align, lane_count)) { |
599 | /* traing pattern Set to Normal */ | |
600 | exynos_dp_training_pattern_dis(dp); | |
e9474be4 | 601 | |
fadec4b7 | 602 | dev_info(dp->dev, "Link Training success!\n"); |
e9474be4 | 603 | |
fadec4b7 SP |
604 | exynos_dp_get_link_bandwidth(dp, ®); |
605 | dp->link_train.link_rate = reg; | |
606 | dev_dbg(dp->dev, "final bandwidth = %.2x\n", | |
607 | dp->link_train.link_rate); | |
e9474be4 | 608 | |
fadec4b7 SP |
609 | exynos_dp_get_lane_count(dp, ®); |
610 | dp->link_train.lane_count = reg; | |
611 | dev_dbg(dp->dev, "final lane count = %.2x\n", | |
612 | dp->link_train.lane_count); | |
e9474be4 | 613 | |
fadec4b7 SP |
614 | /* set enhanced mode if available */ |
615 | exynos_dp_set_enhanced_mode(dp); | |
616 | dp->link_train.lt_state = FINISHED; | |
d5c0eed0 | 617 | |
fadec4b7 SP |
618 | return 0; |
619 | } | |
e9474be4 | 620 | |
fadec4b7 SP |
621 | /* not all locked */ |
622 | dp->link_train.eq_loop++; | |
d5c0eed0 | 623 | |
fadec4b7 SP |
624 | if (dp->link_train.eq_loop > MAX_EQ_LOOP) { |
625 | dev_err(dp->dev, "EQ Max loop\n"); | |
626 | exynos_dp_reduce_link_rate(dp); | |
627 | return -EIO; | |
e9474be4 JH |
628 | } |
629 | ||
fadec4b7 SP |
630 | for (lane = 0; lane < lane_count; lane++) |
631 | exynos_dp_set_lane_link_training(dp, | |
632 | dp->link_train.training_lane[lane], lane); | |
d5c0eed0 | 633 | |
073ea2ae | 634 | retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET, |
fadec4b7 SP |
635 | lane_count, dp->link_train.training_lane); |
636 | ||
637 | return retval; | |
e9474be4 JH |
638 | } |
639 | ||
640 | static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp, | |
d5c0eed0 | 641 | u8 *bandwidth) |
e9474be4 JH |
642 | { |
643 | u8 data; | |
644 | ||
645 | /* | |
646 | * For DP rev.1.1, Maximum link rate of Main Link lanes | |
647 | * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps | |
648 | */ | |
073ea2ae | 649 | exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data); |
e9474be4 JH |
650 | *bandwidth = data; |
651 | } | |
652 | ||
653 | static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp, | |
d5c0eed0 | 654 | u8 *lane_count) |
e9474be4 JH |
655 | { |
656 | u8 data; | |
657 | ||
658 | /* | |
659 | * For DP rev.1.1, Maximum number of Main Link lanes | |
660 | * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes | |
661 | */ | |
073ea2ae | 662 | exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data); |
e9474be4 JH |
663 | *lane_count = DPCD_MAX_LANE_COUNT(data); |
664 | } | |
665 | ||
666 | static void exynos_dp_init_training(struct exynos_dp_device *dp, | |
667 | enum link_lane_count_type max_lane, | |
668 | enum link_rate_type max_rate) | |
669 | { | |
670 | /* | |
671 | * MACRO_RST must be applied after the PLL_LOCK to avoid | |
672 | * the DP inter pair skew issue for at least 10 us | |
673 | */ | |
674 | exynos_dp_reset_macro(dp); | |
675 | ||
676 | /* Initialize by reading RX's DPCD */ | |
677 | exynos_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate); | |
678 | exynos_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count); | |
679 | ||
680 | if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) && | |
681 | (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) { | |
682 | dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n", | |
683 | dp->link_train.link_rate); | |
684 | dp->link_train.link_rate = LINK_RATE_1_62GBPS; | |
685 | } | |
686 | ||
687 | if (dp->link_train.lane_count == 0) { | |
688 | dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n", | |
689 | dp->link_train.lane_count); | |
690 | dp->link_train.lane_count = (u8)LANE_COUNT1; | |
691 | } | |
692 | ||
693 | /* Setup TX lane count & rate */ | |
694 | if (dp->link_train.lane_count > max_lane) | |
695 | dp->link_train.lane_count = max_lane; | |
696 | if (dp->link_train.link_rate > max_rate) | |
697 | dp->link_train.link_rate = max_rate; | |
698 | ||
699 | /* All DP analog module power up */ | |
700 | exynos_dp_set_analog_power_down(dp, POWER_ALL, 0); | |
701 | } | |
702 | ||
703 | static int exynos_dp_sw_link_training(struct exynos_dp_device *dp) | |
704 | { | |
ace2d7f2 | 705 | int retval = 0, training_finished = 0; |
e9474be4 JH |
706 | |
707 | dp->link_train.lt_state = START; | |
708 | ||
709 | /* Process here */ | |
ace2d7f2 | 710 | while (!retval && !training_finished) { |
e9474be4 JH |
711 | switch (dp->link_train.lt_state) { |
712 | case START: | |
ace2d7f2 SP |
713 | retval = exynos_dp_link_start(dp); |
714 | if (retval) | |
715 | dev_err(dp->dev, "LT link start failed!\n"); | |
e9474be4 JH |
716 | break; |
717 | case CLOCK_RECOVERY: | |
d5c0eed0 JH |
718 | retval = exynos_dp_process_clock_recovery(dp); |
719 | if (retval) | |
720 | dev_err(dp->dev, "LT CR failed!\n"); | |
e9474be4 JH |
721 | break; |
722 | case EQUALIZER_TRAINING: | |
d5c0eed0 JH |
723 | retval = exynos_dp_process_equalizer_training(dp); |
724 | if (retval) | |
725 | dev_err(dp->dev, "LT EQ failed!\n"); | |
e9474be4 JH |
726 | break; |
727 | case FINISHED: | |
728 | training_finished = 1; | |
729 | break; | |
730 | case FAILED: | |
731 | return -EREMOTEIO; | |
732 | } | |
733 | } | |
ace2d7f2 SP |
734 | if (retval) |
735 | dev_err(dp->dev, "eDP link training failed (%d)\n", retval); | |
e9474be4 JH |
736 | |
737 | return retval; | |
738 | } | |
739 | ||
740 | static int exynos_dp_set_link_train(struct exynos_dp_device *dp, | |
741 | u32 count, | |
742 | u32 bwtype) | |
743 | { | |
744 | int i; | |
745 | int retval; | |
746 | ||
747 | for (i = 0; i < DP_TIMEOUT_LOOP_COUNT; i++) { | |
748 | exynos_dp_init_training(dp, count, bwtype); | |
749 | retval = exynos_dp_sw_link_training(dp); | |
750 | if (retval == 0) | |
751 | break; | |
752 | ||
a2c81bc1 | 753 | usleep_range(100, 110); |
e9474be4 JH |
754 | } |
755 | ||
756 | return retval; | |
757 | } | |
758 | ||
3fcb6eb4 | 759 | static int exynos_dp_config_video(struct exynos_dp_device *dp) |
e9474be4 JH |
760 | { |
761 | int retval = 0; | |
762 | int timeout_loop = 0; | |
763 | int done_count = 0; | |
764 | ||
3fcb6eb4 | 765 | exynos_dp_config_video_slave_mode(dp); |
e9474be4 | 766 | |
3fcb6eb4 | 767 | exynos_dp_set_video_color_format(dp); |
e9474be4 JH |
768 | |
769 | if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { | |
770 | dev_err(dp->dev, "PLL is not locked yet.\n"); | |
771 | return -EINVAL; | |
772 | } | |
773 | ||
774 | for (;;) { | |
775 | timeout_loop++; | |
776 | if (exynos_dp_is_slave_video_stream_clock_on(dp) == 0) | |
777 | break; | |
778 | if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) { | |
779 | dev_err(dp->dev, "Timeout of video streamclk ok\n"); | |
780 | return -ETIMEDOUT; | |
781 | } | |
782 | ||
a2c81bc1 | 783 | usleep_range(1, 2); |
e9474be4 JH |
784 | } |
785 | ||
786 | /* Set to use the register calculated M/N video */ | |
787 | exynos_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0); | |
788 | ||
789 | /* For video bist, Video timing must be generated by register */ | |
790 | exynos_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE); | |
791 | ||
792 | /* Disable video mute */ | |
793 | exynos_dp_enable_video_mute(dp, 0); | |
794 | ||
795 | /* Configure video slave mode */ | |
796 | exynos_dp_enable_video_master(dp, 0); | |
797 | ||
798 | /* Enable video */ | |
799 | exynos_dp_start_video(dp); | |
800 | ||
801 | timeout_loop = 0; | |
802 | ||
803 | for (;;) { | |
804 | timeout_loop++; | |
805 | if (exynos_dp_is_video_stream_on(dp) == 0) { | |
806 | done_count++; | |
807 | if (done_count > 10) | |
808 | break; | |
809 | } else if (done_count) { | |
810 | done_count = 0; | |
811 | } | |
812 | if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) { | |
813 | dev_err(dp->dev, "Timeout of video streamclk ok\n"); | |
814 | return -ETIMEDOUT; | |
815 | } | |
816 | ||
a2c81bc1 | 817 | usleep_range(1000, 1001); |
e9474be4 JH |
818 | } |
819 | ||
820 | if (retval != 0) | |
821 | dev_err(dp->dev, "Video stream is not detected!\n"); | |
822 | ||
823 | return retval; | |
824 | } | |
825 | ||
826 | static void exynos_dp_enable_scramble(struct exynos_dp_device *dp, bool enable) | |
827 | { | |
828 | u8 data; | |
829 | ||
830 | if (enable) { | |
831 | exynos_dp_enable_scrambling(dp); | |
832 | ||
833 | exynos_dp_read_byte_from_dpcd(dp, | |
073ea2ae | 834 | DP_TRAINING_PATTERN_SET, |
e9474be4 JH |
835 | &data); |
836 | exynos_dp_write_byte_to_dpcd(dp, | |
073ea2ae JH |
837 | DP_TRAINING_PATTERN_SET, |
838 | (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE)); | |
e9474be4 JH |
839 | } else { |
840 | exynos_dp_disable_scrambling(dp); | |
841 | ||
842 | exynos_dp_read_byte_from_dpcd(dp, | |
073ea2ae | 843 | DP_TRAINING_PATTERN_SET, |
e9474be4 JH |
844 | &data); |
845 | exynos_dp_write_byte_to_dpcd(dp, | |
073ea2ae JH |
846 | DP_TRAINING_PATTERN_SET, |
847 | (u8)(data | DP_LINK_SCRAMBLING_DISABLE)); | |
e9474be4 JH |
848 | } |
849 | } | |
850 | ||
851 | static irqreturn_t exynos_dp_irq_handler(int irq, void *arg) | |
852 | { | |
853 | struct exynos_dp_device *dp = arg; | |
854 | ||
c30ffb90 SP |
855 | enum dp_irq_type irq_type; |
856 | ||
857 | irq_type = exynos_dp_get_irq_type(dp); | |
858 | switch (irq_type) { | |
859 | case DP_IRQ_TYPE_HP_CABLE_IN: | |
860 | dev_dbg(dp->dev, "Received irq - cable in\n"); | |
861 | schedule_work(&dp->hotplug_work); | |
862 | exynos_dp_clear_hotplug_interrupts(dp); | |
863 | break; | |
864 | case DP_IRQ_TYPE_HP_CABLE_OUT: | |
865 | dev_dbg(dp->dev, "Received irq - cable out\n"); | |
866 | exynos_dp_clear_hotplug_interrupts(dp); | |
867 | break; | |
868 | case DP_IRQ_TYPE_HP_CHANGE: | |
869 | /* | |
870 | * We get these change notifications once in a while, but there | |
871 | * is nothing we can do with them. Just ignore it for now and | |
872 | * only handle cable changes. | |
873 | */ | |
874 | dev_dbg(dp->dev, "Received irq - hotplug change; ignoring.\n"); | |
875 | exynos_dp_clear_hotplug_interrupts(dp); | |
876 | break; | |
877 | default: | |
878 | dev_err(dp->dev, "Received irq - unknown type!\n"); | |
879 | break; | |
880 | } | |
e9474be4 JH |
881 | return IRQ_HANDLED; |
882 | } | |
883 | ||
784fa9a1 SP |
884 | static void exynos_dp_hotplug(struct work_struct *work) |
885 | { | |
886 | struct exynos_dp_device *dp; | |
784fa9a1 SP |
887 | |
888 | dp = container_of(work, struct exynos_dp_device, hotplug_work); | |
889 | ||
4deabfa0 AK |
890 | if (dp->drm_dev) |
891 | drm_helper_hpd_irq_event(dp->drm_dev); | |
892 | } | |
893 | ||
cf67cc9a | 894 | static void exynos_dp_commit(struct exynos_drm_encoder *encoder) |
4deabfa0 | 895 | { |
cf67cc9a | 896 | struct exynos_dp_device *dp = encoder_to_dp(encoder); |
4deabfa0 AK |
897 | int ret; |
898 | ||
5f1dcd8b AK |
899 | /* Keep the panel disabled while we configure video */ |
900 | if (dp->panel) { | |
901 | if (drm_panel_disable(dp->panel)) | |
902 | DRM_ERROR("failed to disable the panel\n"); | |
903 | } | |
904 | ||
784fa9a1 SP |
905 | ret = exynos_dp_detect_hpd(dp); |
906 | if (ret) { | |
c30ffb90 | 907 | /* Cable has been disconnected, we're done */ |
784fa9a1 SP |
908 | return; |
909 | } | |
910 | ||
911 | ret = exynos_dp_handle_edid(dp); | |
912 | if (ret) { | |
913 | dev_err(dp->dev, "unable to handle edid\n"); | |
914 | return; | |
915 | } | |
916 | ||
917 | ret = exynos_dp_set_link_train(dp, dp->video_info->lane_count, | |
918 | dp->video_info->link_rate); | |
919 | if (ret) { | |
920 | dev_err(dp->dev, "unable to do link train\n"); | |
921 | return; | |
922 | } | |
923 | ||
924 | exynos_dp_enable_scramble(dp, 1); | |
925 | exynos_dp_enable_rx_to_enhanced_mode(dp, 1); | |
926 | exynos_dp_enable_enhanced_mode(dp, 1); | |
927 | ||
928 | exynos_dp_set_lane_count(dp, dp->video_info->lane_count); | |
929 | exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate); | |
930 | ||
931 | exynos_dp_init_video(dp); | |
3fcb6eb4 | 932 | ret = exynos_dp_config_video(dp); |
784fa9a1 SP |
933 | if (ret) |
934 | dev_err(dp->dev, "unable to config video\n"); | |
5f1dcd8b AK |
935 | |
936 | /* Safe to enable the panel now */ | |
937 | if (dp->panel) { | |
938 | if (drm_panel_enable(dp->panel)) | |
939 | DRM_ERROR("failed to enable the panel\n"); | |
940 | } | |
784fa9a1 SP |
941 | } |
942 | ||
caa5d1e5 SP |
943 | static enum drm_connector_status exynos_dp_detect( |
944 | struct drm_connector *connector, bool force) | |
1417f109 | 945 | { |
caa5d1e5 | 946 | return connector_status_connected; |
1417f109 SP |
947 | } |
948 | ||
caa5d1e5 | 949 | static void exynos_dp_connector_destroy(struct drm_connector *connector) |
1417f109 | 950 | { |
7c61b1ec AH |
951 | drm_connector_unregister(connector); |
952 | drm_connector_cleanup(connector); | |
caa5d1e5 SP |
953 | } |
954 | ||
955 | static struct drm_connector_funcs exynos_dp_connector_funcs = { | |
63498e30 | 956 | .dpms = drm_atomic_helper_connector_dpms, |
caa5d1e5 SP |
957 | .fill_modes = drm_helper_probe_single_connector_modes, |
958 | .detect = exynos_dp_detect, | |
959 | .destroy = exynos_dp_connector_destroy, | |
4ea9526b GP |
960 | .reset = drm_atomic_helper_connector_reset, |
961 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, | |
962 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, | |
caa5d1e5 SP |
963 | }; |
964 | ||
965 | static int exynos_dp_get_modes(struct drm_connector *connector) | |
966 | { | |
967 | struct exynos_dp_device *dp = ctx_from_connector(connector); | |
968 | struct drm_display_mode *mode; | |
969 | ||
5f1dcd8b AK |
970 | if (dp->panel) |
971 | return drm_panel_get_modes(dp->panel); | |
972 | ||
caa5d1e5 SP |
973 | mode = drm_mode_create(connector->dev); |
974 | if (!mode) { | |
975 | DRM_ERROR("failed to create a new display mode.\n"); | |
976 | return 0; | |
977 | } | |
978 | ||
5f1dcd8b AK |
979 | drm_display_mode_from_videomode(&dp->priv.vm, mode); |
980 | mode->width_mm = dp->priv.width_mm; | |
981 | mode->height_mm = dp->priv.height_mm; | |
caa5d1e5 SP |
982 | connector->display_info.width_mm = mode->width_mm; |
983 | connector->display_info.height_mm = mode->height_mm; | |
984 | ||
985 | mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; | |
986 | drm_mode_set_name(mode); | |
987 | drm_mode_probed_add(connector, mode); | |
1417f109 | 988 | |
caa5d1e5 | 989 | return 1; |
1417f109 SP |
990 | } |
991 | ||
caa5d1e5 SP |
992 | static struct drm_encoder *exynos_dp_best_encoder( |
993 | struct drm_connector *connector) | |
994 | { | |
995 | struct exynos_dp_device *dp = ctx_from_connector(connector); | |
996 | ||
cf67cc9a | 997 | return &dp->encoder.base; |
caa5d1e5 SP |
998 | } |
999 | ||
1000 | static struct drm_connector_helper_funcs exynos_dp_connector_helper_funcs = { | |
1001 | .get_modes = exynos_dp_get_modes, | |
caa5d1e5 SP |
1002 | .best_encoder = exynos_dp_best_encoder, |
1003 | }; | |
1004 | ||
1634ba25 | 1005 | /* returns the number of bridges attached */ |
80185567 | 1006 | static int exynos_drm_attach_lcd_bridge(struct exynos_dp_device *dp, |
1634ba25 SP |
1007 | struct drm_encoder *encoder) |
1008 | { | |
80185567 AK |
1009 | int ret; |
1010 | ||
1011 | encoder->bridge = dp->bridge; | |
1012 | dp->bridge->encoder = encoder; | |
1013 | ret = drm_bridge_attach(encoder->dev, dp->bridge); | |
1014 | if (ret) { | |
1015 | DRM_ERROR("Failed to attach bridge to drm\n"); | |
1016 | return ret; | |
1017 | } | |
1018 | ||
1634ba25 SP |
1019 | return 0; |
1020 | } | |
1021 | ||
cf67cc9a | 1022 | static int exynos_dp_create_connector(struct exynos_drm_encoder *exynos_encoder) |
caa5d1e5 | 1023 | { |
cf67cc9a GP |
1024 | struct exynos_dp_device *dp = encoder_to_dp(exynos_encoder); |
1025 | struct drm_encoder *encoder = &exynos_encoder->base; | |
caa5d1e5 SP |
1026 | struct drm_connector *connector = &dp->connector; |
1027 | int ret; | |
1028 | ||
1634ba25 | 1029 | /* Pre-empt DP connector creation if there's a bridge */ |
80185567 AK |
1030 | if (dp->bridge) { |
1031 | ret = exynos_drm_attach_lcd_bridge(dp, encoder); | |
1032 | if (!ret) | |
1033 | return 0; | |
1034 | } | |
1634ba25 | 1035 | |
caa5d1e5 SP |
1036 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
1037 | ||
1038 | ret = drm_connector_init(dp->drm_dev, connector, | |
1039 | &exynos_dp_connector_funcs, DRM_MODE_CONNECTOR_eDP); | |
1040 | if (ret) { | |
1041 | DRM_ERROR("Failed to initialize connector with drm\n"); | |
1042 | return ret; | |
1043 | } | |
1044 | ||
1045 | drm_connector_helper_add(connector, &exynos_dp_connector_helper_funcs); | |
34ea3d38 | 1046 | drm_connector_register(connector); |
caa5d1e5 SP |
1047 | drm_mode_connector_attach_encoder(connector, encoder); |
1048 | ||
5f1dcd8b AK |
1049 | if (dp->panel) |
1050 | ret = drm_panel_attach(dp->panel, &dp->connector); | |
1051 | ||
1052 | return ret; | |
1417f109 SP |
1053 | } |
1054 | ||
cf67cc9a | 1055 | static void exynos_dp_enable(struct exynos_drm_encoder *encoder) |
12f5ad6c | 1056 | { |
cf67cc9a | 1057 | struct exynos_dp_device *dp = encoder_to_dp(encoder); |
48107d7b KK |
1058 | struct exynos_drm_crtc *crtc = dp_to_crtc(dp); |
1059 | ||
12f5ad6c SP |
1060 | if (dp->dpms_mode == DRM_MODE_DPMS_ON) |
1061 | return; | |
1062 | ||
5f1dcd8b AK |
1063 | if (dp->panel) { |
1064 | if (drm_panel_prepare(dp->panel)) { | |
1065 | DRM_ERROR("failed to setup the panel\n"); | |
1066 | return; | |
1067 | } | |
1068 | } | |
1069 | ||
48107d7b KK |
1070 | if (crtc->ops->clock_enable) |
1071 | crtc->ops->clock_enable(dp_to_crtc(dp), true); | |
1c363c7c | 1072 | |
12f5ad6c | 1073 | clk_prepare_enable(dp->clock); |
b6f3c361 | 1074 | phy_power_on(dp->phy); |
12f5ad6c SP |
1075 | exynos_dp_init_dp(dp); |
1076 | enable_irq(dp->irq); | |
cf67cc9a | 1077 | exynos_dp_commit(&dp->encoder); |
b6595dc7 GP |
1078 | |
1079 | dp->dpms_mode = DRM_MODE_DPMS_ON; | |
12f5ad6c SP |
1080 | } |
1081 | ||
cf67cc9a | 1082 | static void exynos_dp_disable(struct exynos_drm_encoder *encoder) |
12f5ad6c | 1083 | { |
cf67cc9a | 1084 | struct exynos_dp_device *dp = encoder_to_dp(encoder); |
48107d7b KK |
1085 | struct exynos_drm_crtc *crtc = dp_to_crtc(dp); |
1086 | ||
12f5ad6c SP |
1087 | if (dp->dpms_mode != DRM_MODE_DPMS_ON) |
1088 | return; | |
1089 | ||
5f1dcd8b AK |
1090 | if (dp->panel) { |
1091 | if (drm_panel_disable(dp->panel)) { | |
1092 | DRM_ERROR("failed to disable the panel\n"); | |
1093 | return; | |
1094 | } | |
1095 | } | |
1096 | ||
12f5ad6c SP |
1097 | disable_irq(dp->irq); |
1098 | flush_work(&dp->hotplug_work); | |
b6f3c361 | 1099 | phy_power_off(dp->phy); |
12f5ad6c | 1100 | clk_disable_unprepare(dp->clock); |
5f1dcd8b | 1101 | |
48107d7b KK |
1102 | if (crtc->ops->clock_enable) |
1103 | crtc->ops->clock_enable(dp_to_crtc(dp), false); | |
1c363c7c | 1104 | |
5f1dcd8b AK |
1105 | if (dp->panel) { |
1106 | if (drm_panel_unprepare(dp->panel)) | |
1107 | DRM_ERROR("failed to turnoff the panel\n"); | |
1108 | } | |
12f5ad6c | 1109 | |
b6595dc7 | 1110 | dp->dpms_mode = DRM_MODE_DPMS_OFF; |
12f5ad6c SP |
1111 | } |
1112 | ||
cf67cc9a | 1113 | static struct exynos_drm_encoder_ops exynos_dp_encoder_ops = { |
caa5d1e5 | 1114 | .create_connector = exynos_dp_create_connector, |
b6595dc7 GP |
1115 | .enable = exynos_dp_enable, |
1116 | .disable = exynos_dp_disable, | |
4deabfa0 | 1117 | .commit = exynos_dp_commit, |
1417f109 SP |
1118 | }; |
1119 | ||
f9b1e013 | 1120 | static struct video_info *exynos_dp_dt_parse_pdata(struct device *dev) |
c4e235c2 AK |
1121 | { |
1122 | struct device_node *dp_node = dev->of_node; | |
c4e235c2 AK |
1123 | struct video_info *dp_video_config; |
1124 | ||
c4e235c2 AK |
1125 | dp_video_config = devm_kzalloc(dev, |
1126 | sizeof(*dp_video_config), GFP_KERNEL); | |
7a5b6827 | 1127 | if (!dp_video_config) |
c4e235c2 | 1128 | return ERR_PTR(-ENOMEM); |
c4e235c2 AK |
1129 | |
1130 | dp_video_config->h_sync_polarity = | |
1131 | of_property_read_bool(dp_node, "hsync-active-high"); | |
1132 | ||
1133 | dp_video_config->v_sync_polarity = | |
1134 | of_property_read_bool(dp_node, "vsync-active-high"); | |
1135 | ||
1136 | dp_video_config->interlaced = | |
1137 | of_property_read_bool(dp_node, "interlaced"); | |
1138 | ||
1139 | if (of_property_read_u32(dp_node, "samsung,color-space", | |
1140 | &dp_video_config->color_space)) { | |
1141 | dev_err(dev, "failed to get color-space\n"); | |
1142 | return ERR_PTR(-EINVAL); | |
1143 | } | |
1144 | ||
1145 | if (of_property_read_u32(dp_node, "samsung,dynamic-range", | |
1146 | &dp_video_config->dynamic_range)) { | |
1147 | dev_err(dev, "failed to get dynamic-range\n"); | |
1148 | return ERR_PTR(-EINVAL); | |
1149 | } | |
1150 | ||
1151 | if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff", | |
1152 | &dp_video_config->ycbcr_coeff)) { | |
1153 | dev_err(dev, "failed to get ycbcr-coeff\n"); | |
1154 | return ERR_PTR(-EINVAL); | |
1155 | } | |
1156 | ||
1157 | if (of_property_read_u32(dp_node, "samsung,color-depth", | |
1158 | &dp_video_config->color_depth)) { | |
1159 | dev_err(dev, "failed to get color-depth\n"); | |
1160 | return ERR_PTR(-EINVAL); | |
1161 | } | |
1162 | ||
1163 | if (of_property_read_u32(dp_node, "samsung,link-rate", | |
1164 | &dp_video_config->link_rate)) { | |
1165 | dev_err(dev, "failed to get link-rate\n"); | |
1166 | return ERR_PTR(-EINVAL); | |
1167 | } | |
1168 | ||
1169 | if (of_property_read_u32(dp_node, "samsung,lane-count", | |
1170 | &dp_video_config->lane_count)) { | |
1171 | dev_err(dev, "failed to get lane-count\n"); | |
1172 | return ERR_PTR(-EINVAL); | |
1173 | } | |
1174 | ||
f9b1e013 | 1175 | return dp_video_config; |
c4e235c2 AK |
1176 | } |
1177 | ||
1417f109 SP |
1178 | static int exynos_dp_dt_parse_panel(struct exynos_dp_device *dp) |
1179 | { | |
1180 | int ret; | |
1181 | ||
5f1dcd8b | 1182 | ret = of_get_videomode(dp->dev->of_node, &dp->priv.vm, |
1417f109 SP |
1183 | OF_USE_NATIVE_MODE); |
1184 | if (ret) { | |
1185 | DRM_ERROR("failed: of_get_videomode() : %d\n", ret); | |
1186 | return ret; | |
1187 | } | |
1188 | return 0; | |
1189 | } | |
1190 | ||
f37cd5e8 | 1191 | static int exynos_dp_bind(struct device *dev, struct device *master, void *data) |
e9474be4 | 1192 | { |
1df6e5fb | 1193 | struct exynos_dp_device *dp = dev_get_drvdata(dev); |
f37cd5e8 ID |
1194 | struct platform_device *pdev = to_platform_device(dev); |
1195 | struct drm_device *drm_dev = data; | |
e9474be4 | 1196 | struct resource *res; |
b8b52471 | 1197 | unsigned int irq_flags; |
e9474be4 JH |
1198 | int ret = 0; |
1199 | ||
e9474be4 | 1200 | dp->dev = &pdev->dev; |
12f5ad6c | 1201 | dp->dpms_mode = DRM_MODE_DPMS_OFF; |
e9474be4 | 1202 | |
f9b1e013 JH |
1203 | dp->video_info = exynos_dp_dt_parse_pdata(&pdev->dev); |
1204 | if (IS_ERR(dp->video_info)) | |
1205 | return PTR_ERR(dp->video_info); | |
c4e235c2 | 1206 | |
b128aefe VG |
1207 | dp->phy = devm_phy_get(dp->dev, "dp"); |
1208 | if (IS_ERR(dp->phy)) { | |
1209 | dev_err(dp->dev, "no DP phy configured\n"); | |
1210 | ret = PTR_ERR(dp->phy); | |
1211 | if (ret) { | |
1212 | /* | |
1213 | * phy itself is not enabled, so we can move forward | |
1214 | * assigning NULL to phy pointer. | |
1215 | */ | |
1216 | if (ret == -ENOSYS || ret == -ENODEV) | |
1217 | dp->phy = NULL; | |
1218 | else | |
1219 | return ret; | |
1220 | } | |
1221 | } | |
c4e235c2 | 1222 | |
80185567 | 1223 | if (!dp->panel && !dp->bridge) { |
5f1dcd8b AK |
1224 | ret = exynos_dp_dt_parse_panel(dp); |
1225 | if (ret) | |
1226 | return ret; | |
1227 | } | |
1417f109 | 1228 | |
d913f36e | 1229 | dp->clock = devm_clk_get(&pdev->dev, "dp"); |
e9474be4 JH |
1230 | if (IS_ERR(dp->clock)) { |
1231 | dev_err(&pdev->dev, "failed to get clock\n"); | |
4d10ecf8 | 1232 | return PTR_ERR(dp->clock); |
e9474be4 JH |
1233 | } |
1234 | ||
37414fbe | 1235 | clk_prepare_enable(dp->clock); |
e9474be4 JH |
1236 | |
1237 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
e9474be4 | 1238 | |
bc3bad16 TR |
1239 | dp->reg_base = devm_ioremap_resource(&pdev->dev, res); |
1240 | if (IS_ERR(dp->reg_base)) | |
1241 | return PTR_ERR(dp->reg_base); | |
e9474be4 | 1242 | |
b8b52471 AB |
1243 | dp->hpd_gpio = of_get_named_gpio(dev->of_node, "samsung,hpd-gpio", 0); |
1244 | ||
1245 | if (gpio_is_valid(dp->hpd_gpio)) { | |
1246 | /* | |
1247 | * Set up the hotplug GPIO from the device tree as an interrupt. | |
1248 | * Simply specifying a different interrupt in the device tree | |
1249 | * doesn't work since we handle hotplug rather differently when | |
1250 | * using a GPIO. We also need the actual GPIO specifier so | |
1251 | * that we can get the current state of the GPIO. | |
1252 | */ | |
1253 | ret = devm_gpio_request_one(&pdev->dev, dp->hpd_gpio, GPIOF_IN, | |
1254 | "hpd_gpio"); | |
1255 | if (ret) { | |
1256 | dev_err(&pdev->dev, "failed to get hpd gpio\n"); | |
1257 | return ret; | |
1258 | } | |
1259 | dp->irq = gpio_to_irq(dp->hpd_gpio); | |
1260 | irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING; | |
1261 | } else { | |
1262 | dp->hpd_gpio = -ENODEV; | |
1263 | dp->irq = platform_get_irq(pdev, 0); | |
1264 | irq_flags = 0; | |
1265 | } | |
1266 | ||
1cefc1d6 | 1267 | if (dp->irq == -ENXIO) { |
e9474be4 | 1268 | dev_err(&pdev->dev, "failed to get irq\n"); |
d913f36e | 1269 | return -ENODEV; |
e9474be4 JH |
1270 | } |
1271 | ||
784fa9a1 SP |
1272 | INIT_WORK(&dp->hotplug_work, exynos_dp_hotplug); |
1273 | ||
b6f3c361 | 1274 | phy_power_on(dp->phy); |
e9474be4 JH |
1275 | |
1276 | exynos_dp_init_dp(dp); | |
1277 | ||
b8b52471 AB |
1278 | ret = devm_request_irq(&pdev->dev, dp->irq, exynos_dp_irq_handler, |
1279 | irq_flags, "exynos-dp", dp); | |
22ce19cb AK |
1280 | if (ret) { |
1281 | dev_err(&pdev->dev, "failed to request irq\n"); | |
1282 | return ret; | |
1283 | } | |
12f5ad6c | 1284 | disable_irq(dp->irq); |
e9474be4 | 1285 | |
f37cd5e8 | 1286 | dp->drm_dev = drm_dev; |
12f5ad6c | 1287 | |
cf67cc9a GP |
1288 | return exynos_drm_create_enc_conn(drm_dev, &dp->encoder, |
1289 | EXYNOS_DISPLAY_TYPE_LCD); | |
e9474be4 JH |
1290 | } |
1291 | ||
f37cd5e8 ID |
1292 | static void exynos_dp_unbind(struct device *dev, struct device *master, |
1293 | void *data) | |
e9474be4 | 1294 | { |
1df6e5fb | 1295 | struct exynos_dp_device *dp = dev_get_drvdata(dev); |
e9474be4 | 1296 | |
cf67cc9a | 1297 | exynos_dp_disable(&dp->encoder); |
f37cd5e8 ID |
1298 | } |
1299 | ||
1300 | static const struct component_ops exynos_dp_ops = { | |
1301 | .bind = exynos_dp_bind, | |
1302 | .unbind = exynos_dp_unbind, | |
1303 | }; | |
1304 | ||
1305 | static int exynos_dp_probe(struct platform_device *pdev) | |
1306 | { | |
5f1dcd8b | 1307 | struct device *dev = &pdev->dev; |
80185567 | 1308 | struct device_node *panel_node, *bridge_node, *endpoint; |
5f1dcd8b | 1309 | struct exynos_dp_device *dp; |
df5225bc | 1310 | |
5f1dcd8b AK |
1311 | dp = devm_kzalloc(&pdev->dev, sizeof(struct exynos_dp_device), |
1312 | GFP_KERNEL); | |
1313 | if (!dp) | |
1314 | return -ENOMEM; | |
1315 | ||
cf67cc9a | 1316 | dp->encoder.ops = &exynos_dp_encoder_ops; |
1df6e5fb AH |
1317 | platform_set_drvdata(pdev, dp); |
1318 | ||
5f1dcd8b AK |
1319 | panel_node = of_parse_phandle(dev->of_node, "panel", 0); |
1320 | if (panel_node) { | |
1321 | dp->panel = of_drm_find_panel(panel_node); | |
1322 | of_node_put(panel_node); | |
1323 | if (!dp->panel) | |
1324 | return -EPROBE_DEFER; | |
1325 | } | |
1326 | ||
80185567 AK |
1327 | endpoint = of_graph_get_next_endpoint(dev->of_node, NULL); |
1328 | if (endpoint) { | |
1329 | bridge_node = of_graph_get_remote_port_parent(endpoint); | |
1330 | if (bridge_node) { | |
1331 | dp->bridge = of_drm_find_bridge(bridge_node); | |
1332 | of_node_put(bridge_node); | |
1333 | if (!dp->bridge) | |
1334 | return -EPROBE_DEFER; | |
1335 | } else | |
1336 | return -EPROBE_DEFER; | |
1337 | } | |
1338 | ||
86650408 | 1339 | return component_add(&pdev->dev, &exynos_dp_ops); |
f37cd5e8 ID |
1340 | } |
1341 | ||
1342 | static int exynos_dp_remove(struct platform_device *pdev) | |
1343 | { | |
df5225bc | 1344 | component_del(&pdev->dev, &exynos_dp_ops); |
df5225bc | 1345 | |
e9474be4 JH |
1346 | return 0; |
1347 | } | |
1348 | ||
1349 | #ifdef CONFIG_PM_SLEEP | |
1350 | static int exynos_dp_suspend(struct device *dev) | |
1351 | { | |
1df6e5fb | 1352 | struct exynos_dp_device *dp = dev_get_drvdata(dev); |
e9474be4 | 1353 | |
cf67cc9a | 1354 | exynos_dp_disable(&dp->encoder); |
e9474be4 JH |
1355 | return 0; |
1356 | } | |
1357 | ||
1358 | static int exynos_dp_resume(struct device *dev) | |
1359 | { | |
1df6e5fb | 1360 | struct exynos_dp_device *dp = dev_get_drvdata(dev); |
e9474be4 | 1361 | |
cf67cc9a | 1362 | exynos_dp_enable(&dp->encoder); |
e9474be4 JH |
1363 | return 0; |
1364 | } | |
1365 | #endif | |
1366 | ||
1367 | static const struct dev_pm_ops exynos_dp_pm_ops = { | |
1368 | SET_SYSTEM_SLEEP_PM_OPS(exynos_dp_suspend, exynos_dp_resume) | |
1369 | }; | |
1370 | ||
c4e235c2 AK |
1371 | static const struct of_device_id exynos_dp_match[] = { |
1372 | { .compatible = "samsung,exynos5-dp" }, | |
1373 | {}, | |
1374 | }; | |
bd024b86 | 1375 | MODULE_DEVICE_TABLE(of, exynos_dp_match); |
c4e235c2 | 1376 | |
1417f109 | 1377 | struct platform_driver dp_driver = { |
e9474be4 | 1378 | .probe = exynos_dp_probe, |
48c68c4f | 1379 | .remove = exynos_dp_remove, |
e9474be4 JH |
1380 | .driver = { |
1381 | .name = "exynos-dp", | |
1382 | .owner = THIS_MODULE, | |
1383 | .pm = &exynos_dp_pm_ops, | |
f9b1e013 | 1384 | .of_match_table = exynos_dp_match, |
e9474be4 JH |
1385 | }, |
1386 | }; | |
1387 | ||
e9474be4 JH |
1388 | MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>"); |
1389 | MODULE_DESCRIPTION("Samsung SoC DP Driver"); | |
8f589bba | 1390 | MODULE_LICENSE("GPL v2"); |