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c8466a91 JS |
1 | /* drivers/gpu/drm/exynos5433_drm_decon.c |
2 | * | |
3 | * Copyright (C) 2015 Samsung Electronics Co.Ltd | |
4 | * Authors: | |
5 | * Joonyoung Shim <jy0922.shim@samsung.com> | |
6 | * Hyungwon Hwang <human.hwang@samsung.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundationr | |
11 | */ | |
12 | ||
13 | #include <linux/platform_device.h> | |
14 | #include <linux/clk.h> | |
15 | #include <linux/component.h> | |
b8182832 | 16 | #include <linux/of_device.h> |
c8466a91 JS |
17 | #include <linux/of_gpio.h> |
18 | #include <linux/pm_runtime.h> | |
19 | ||
20 | #include <video/exynos5433_decon.h> | |
21 | ||
22 | #include "exynos_drm_drv.h" | |
23 | #include "exynos_drm_crtc.h" | |
0488f50e | 24 | #include "exynos_drm_fb.h" |
c8466a91 JS |
25 | #include "exynos_drm_plane.h" |
26 | #include "exynos_drm_iommu.h" | |
27 | ||
28 | #define WINDOWS_NR 3 | |
29 | #define MIN_FB_WIDTH_FOR_16WORD_BURST 128 | |
30 | ||
4f54f21c AH |
31 | static const char * const decon_clks_name[] = { |
32 | "pclk", | |
33 | "aclk_decon", | |
34 | "aclk_smmu_decon0x", | |
35 | "aclk_xiu_decon0x", | |
36 | "pclk_smmu_decon0x", | |
37 | "sclk_decon_vclk", | |
38 | "sclk_decon_eclk", | |
39 | }; | |
40 | ||
b8182832 AH |
41 | enum decon_iftype { |
42 | IFTYPE_RGB, | |
43 | IFTYPE_I80, | |
44 | IFTYPE_HDMI | |
45 | }; | |
46 | ||
7b6bb6ed AH |
47 | enum decon_flag_bits { |
48 | BIT_CLKS_ENABLED, | |
49 | BIT_IRQS_ENABLED, | |
50 | BIT_WIN_UPDATED, | |
51 | BIT_SUSPENDED | |
52 | }; | |
53 | ||
c8466a91 JS |
54 | struct decon_context { |
55 | struct device *dev; | |
56 | struct drm_device *drm_dev; | |
57 | struct exynos_drm_crtc *crtc; | |
58 | struct exynos_drm_plane planes[WINDOWS_NR]; | |
fd2d2fc2 | 59 | struct exynos_drm_plane_config configs[WINDOWS_NR]; |
c8466a91 | 60 | void __iomem *addr; |
4f54f21c | 61 | struct clk *clks[ARRAY_SIZE(decon_clks_name)]; |
c8466a91 | 62 | int pipe; |
7b6bb6ed | 63 | unsigned long flags; |
b8182832 AH |
64 | enum decon_iftype out_type; |
65 | int first_win; | |
c8466a91 JS |
66 | }; |
67 | ||
fbbb1e1a MS |
68 | static const uint32_t decon_formats[] = { |
69 | DRM_FORMAT_XRGB1555, | |
70 | DRM_FORMAT_RGB565, | |
71 | DRM_FORMAT_XRGB8888, | |
72 | DRM_FORMAT_ARGB8888, | |
73 | }; | |
74 | ||
fd2d2fc2 MS |
75 | static const enum drm_plane_type decon_win_types[WINDOWS_NR] = { |
76 | DRM_PLANE_TYPE_PRIMARY, | |
77 | DRM_PLANE_TYPE_OVERLAY, | |
78 | DRM_PLANE_TYPE_CURSOR, | |
79 | }; | |
80 | ||
b2192073 AH |
81 | static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask, |
82 | u32 val) | |
83 | { | |
84 | val = (val & mask) | (readl(ctx->addr + reg) & ~mask); | |
85 | writel(val, ctx->addr + reg); | |
86 | } | |
87 | ||
c8466a91 JS |
88 | static int decon_enable_vblank(struct exynos_drm_crtc *crtc) |
89 | { | |
90 | struct decon_context *ctx = crtc->ctx; | |
91 | u32 val; | |
92 | ||
7b6bb6ed | 93 | if (test_bit(BIT_SUSPENDED, &ctx->flags)) |
c8466a91 JS |
94 | return -EPERM; |
95 | ||
74ebc706 | 96 | if (!test_and_set_bit(BIT_IRQS_ENABLED, &ctx->flags)) { |
c8466a91 | 97 | val = VIDINTCON0_INTEN; |
b8182832 | 98 | if (ctx->out_type == IFTYPE_I80) |
c8466a91 JS |
99 | val |= VIDINTCON0_FRAMEDONE; |
100 | else | |
101 | val |= VIDINTCON0_INTFRMEN; | |
102 | ||
103 | writel(val, ctx->addr + DECON_VIDINTCON0); | |
104 | } | |
105 | ||
106 | return 0; | |
107 | } | |
108 | ||
109 | static void decon_disable_vblank(struct exynos_drm_crtc *crtc) | |
110 | { | |
111 | struct decon_context *ctx = crtc->ctx; | |
112 | ||
7b6bb6ed | 113 | if (test_bit(BIT_SUSPENDED, &ctx->flags)) |
c8466a91 JS |
114 | return; |
115 | ||
7b6bb6ed | 116 | if (test_and_clear_bit(BIT_IRQS_ENABLED, &ctx->flags)) |
c8466a91 JS |
117 | writel(0, ctx->addr + DECON_VIDINTCON0); |
118 | } | |
119 | ||
120 | static void decon_setup_trigger(struct decon_context *ctx) | |
121 | { | |
b8182832 AH |
122 | u32 val = (ctx->out_type != IFTYPE_HDMI) |
123 | ? TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F | | |
124 | TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN | |
125 | : TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F | | |
126 | TRIGCON_HWTRIGMASK_I80_RGB | TRIGCON_HWTRIGEN_I80_RGB; | |
c8466a91 JS |
127 | writel(val, ctx->addr + DECON_TRIGCON); |
128 | } | |
129 | ||
130 | static void decon_commit(struct exynos_drm_crtc *crtc) | |
131 | { | |
132 | struct decon_context *ctx = crtc->ctx; | |
85de275a | 133 | struct drm_display_mode *m = &crtc->base.mode; |
c8466a91 JS |
134 | u32 val; |
135 | ||
7b6bb6ed | 136 | if (test_bit(BIT_SUSPENDED, &ctx->flags)) |
c8466a91 JS |
137 | return; |
138 | ||
b8182832 AH |
139 | if (ctx->out_type == IFTYPE_HDMI) { |
140 | m->crtc_hsync_start = m->crtc_hdisplay + 10; | |
141 | m->crtc_hsync_end = m->crtc_htotal - 92; | |
142 | m->crtc_vsync_start = m->crtc_vdisplay + 1; | |
143 | m->crtc_vsync_end = m->crtc_vsync_start + 1; | |
144 | } | |
145 | ||
146 | decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID, 0); | |
147 | ||
c8466a91 JS |
148 | /* enable clock gate */ |
149 | val = CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F; | |
150 | writel(val, ctx->addr + DECON_CMU); | |
151 | ||
152 | /* lcd on and use command if */ | |
153 | val = VIDOUT_LCD_ON; | |
b8182832 | 154 | if (ctx->out_type == IFTYPE_I80) |
c8466a91 JS |
155 | val |= VIDOUT_COMMAND_IF; |
156 | else | |
157 | val |= VIDOUT_RGB_IF; | |
158 | writel(val, ctx->addr + DECON_VIDOUTCON0); | |
159 | ||
85de275a AH |
160 | val = VIDTCON2_LINEVAL(m->vdisplay - 1) | |
161 | VIDTCON2_HOZVAL(m->hdisplay - 1); | |
c8466a91 JS |
162 | writel(val, ctx->addr + DECON_VIDTCON2); |
163 | ||
b8182832 | 164 | if (ctx->out_type != IFTYPE_I80) { |
c8466a91 | 165 | val = VIDTCON00_VBPD_F( |
85de275a | 166 | m->crtc_vtotal - m->crtc_vsync_end - 1) | |
c8466a91 | 167 | VIDTCON00_VFPD_F( |
85de275a | 168 | m->crtc_vsync_start - m->crtc_vdisplay - 1); |
c8466a91 JS |
169 | writel(val, ctx->addr + DECON_VIDTCON00); |
170 | ||
171 | val = VIDTCON01_VSPW_F( | |
85de275a | 172 | m->crtc_vsync_end - m->crtc_vsync_start - 1); |
c8466a91 JS |
173 | writel(val, ctx->addr + DECON_VIDTCON01); |
174 | ||
175 | val = VIDTCON10_HBPD_F( | |
85de275a | 176 | m->crtc_htotal - m->crtc_hsync_end - 1) | |
c8466a91 | 177 | VIDTCON10_HFPD_F( |
85de275a | 178 | m->crtc_hsync_start - m->crtc_hdisplay - 1); |
c8466a91 JS |
179 | writel(val, ctx->addr + DECON_VIDTCON10); |
180 | ||
181 | val = VIDTCON11_HSPW_F( | |
85de275a | 182 | m->crtc_hsync_end - m->crtc_hsync_start - 1); |
c8466a91 JS |
183 | writel(val, ctx->addr + DECON_VIDTCON11); |
184 | } | |
185 | ||
186 | decon_setup_trigger(ctx); | |
187 | ||
188 | /* enable output and display signal */ | |
b8182832 | 189 | decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID | VIDCON0_ENVID_F, ~0); |
c8466a91 JS |
190 | } |
191 | ||
2eeb2e5e GP |
192 | static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win, |
193 | struct drm_framebuffer *fb) | |
c8466a91 | 194 | { |
c8466a91 JS |
195 | unsigned long val; |
196 | ||
197 | val = readl(ctx->addr + DECON_WINCONx(win)); | |
198 | val &= ~WINCONx_BPPMODE_MASK; | |
199 | ||
2eeb2e5e | 200 | switch (fb->pixel_format) { |
c8466a91 JS |
201 | case DRM_FORMAT_XRGB1555: |
202 | val |= WINCONx_BPPMODE_16BPP_I1555; | |
203 | val |= WINCONx_HAWSWP_F; | |
204 | val |= WINCONx_BURSTLEN_16WORD; | |
205 | break; | |
206 | case DRM_FORMAT_RGB565: | |
207 | val |= WINCONx_BPPMODE_16BPP_565; | |
208 | val |= WINCONx_HAWSWP_F; | |
209 | val |= WINCONx_BURSTLEN_16WORD; | |
210 | break; | |
211 | case DRM_FORMAT_XRGB8888: | |
212 | val |= WINCONx_BPPMODE_24BPP_888; | |
213 | val |= WINCONx_WSWP_F; | |
214 | val |= WINCONx_BURSTLEN_16WORD; | |
215 | break; | |
216 | case DRM_FORMAT_ARGB8888: | |
217 | val |= WINCONx_BPPMODE_32BPP_A8888; | |
218 | val |= WINCONx_WSWP_F | WINCONx_BLD_PIX_F | WINCONx_ALPHA_SEL_F; | |
219 | val |= WINCONx_BURSTLEN_16WORD; | |
220 | break; | |
221 | default: | |
222 | DRM_ERROR("Proper pixel format is not set\n"); | |
223 | return; | |
224 | } | |
225 | ||
2eeb2e5e | 226 | DRM_DEBUG_KMS("bpp = %u\n", fb->bits_per_pixel); |
c8466a91 JS |
227 | |
228 | /* | |
229 | * In case of exynos, setting dma-burst to 16Word causes permanent | |
230 | * tearing for very small buffers, e.g. cursor buffer. Burst Mode | |
231 | * switching which is based on plane size is not recommended as | |
232 | * plane size varies a lot towards the end of the screen and rapid | |
233 | * movement causes unstable DMA which results into iommu crash/tear. | |
234 | */ | |
235 | ||
2eeb2e5e | 236 | if (fb->width < MIN_FB_WIDTH_FOR_16WORD_BURST) { |
c8466a91 JS |
237 | val &= ~WINCONx_BURSTLEN_MASK; |
238 | val |= WINCONx_BURSTLEN_8WORD; | |
239 | } | |
240 | ||
241 | writel(val, ctx->addr + DECON_WINCONx(win)); | |
242 | } | |
243 | ||
244 | static void decon_shadow_protect_win(struct decon_context *ctx, int win, | |
245 | bool protect) | |
246 | { | |
b2192073 AH |
247 | decon_set_bits(ctx, DECON_SHADOWCON, SHADOWCON_Wx_PROTECT(win), |
248 | protect ? ~0 : 0); | |
c8466a91 JS |
249 | } |
250 | ||
d29c2c14 | 251 | static void decon_atomic_begin(struct exynos_drm_crtc *crtc) |
cc5a7b35 HH |
252 | { |
253 | struct decon_context *ctx = crtc->ctx; | |
d29c2c14 | 254 | int i; |
cc5a7b35 | 255 | |
7b6bb6ed | 256 | if (test_bit(BIT_SUSPENDED, &ctx->flags)) |
cc5a7b35 HH |
257 | return; |
258 | ||
d29c2c14 MS |
259 | for (i = ctx->first_win; i < WINDOWS_NR; i++) |
260 | decon_shadow_protect_win(ctx, i, true); | |
cc5a7b35 HH |
261 | } |
262 | ||
b8182832 AH |
263 | #define BIT_VAL(x, e, s) (((x) & ((1 << ((e) - (s) + 1)) - 1)) << (s)) |
264 | #define COORDINATE_X(x) BIT_VAL((x), 23, 12) | |
265 | #define COORDINATE_Y(x) BIT_VAL((x), 11, 0) | |
266 | ||
1e1d1393 GP |
267 | static void decon_update_plane(struct exynos_drm_crtc *crtc, |
268 | struct exynos_drm_plane *plane) | |
c8466a91 | 269 | { |
0114f404 MS |
270 | struct exynos_drm_plane_state *state = |
271 | to_exynos_plane_state(plane->base.state); | |
c8466a91 | 272 | struct decon_context *ctx = crtc->ctx; |
0114f404 | 273 | struct drm_framebuffer *fb = state->base.fb; |
40bdfb0a | 274 | unsigned int win = plane->index; |
0488f50e MS |
275 | unsigned int bpp = fb->bits_per_pixel >> 3; |
276 | unsigned int pitch = fb->pitches[0]; | |
277 | dma_addr_t dma_addr = exynos_drm_fb_dma_addr(fb, 0); | |
c8466a91 JS |
278 | u32 val; |
279 | ||
7b6bb6ed | 280 | if (test_bit(BIT_SUSPENDED, &ctx->flags)) |
c8466a91 JS |
281 | return; |
282 | ||
0114f404 | 283 | val = COORDINATE_X(state->crtc.x) | COORDINATE_Y(state->crtc.y); |
c8466a91 JS |
284 | writel(val, ctx->addr + DECON_VIDOSDxA(win)); |
285 | ||
0114f404 MS |
286 | val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) | |
287 | COORDINATE_Y(state->crtc.y + state->crtc.h - 1); | |
c8466a91 JS |
288 | writel(val, ctx->addr + DECON_VIDOSDxB(win)); |
289 | ||
290 | val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) | | |
291 | VIDOSD_Wx_ALPHA_B_F(0x0); | |
292 | writel(val, ctx->addr + DECON_VIDOSDxC(win)); | |
293 | ||
294 | val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) | | |
295 | VIDOSD_Wx_ALPHA_B_F(0x0); | |
296 | writel(val, ctx->addr + DECON_VIDOSDxD(win)); | |
297 | ||
0488f50e | 298 | writel(dma_addr, ctx->addr + DECON_VIDW0xADD0B0(win)); |
c8466a91 | 299 | |
0114f404 | 300 | val = dma_addr + pitch * state->src.h; |
c8466a91 JS |
301 | writel(val, ctx->addr + DECON_VIDW0xADD1B0(win)); |
302 | ||
b8182832 | 303 | if (ctx->out_type != IFTYPE_HDMI) |
0114f404 MS |
304 | val = BIT_VAL(pitch - state->crtc.w * bpp, 27, 14) |
305 | | BIT_VAL(state->crtc.w * bpp, 13, 0); | |
b8182832 | 306 | else |
0114f404 MS |
307 | val = BIT_VAL(pitch - state->crtc.w * bpp, 29, 15) |
308 | | BIT_VAL(state->crtc.w * bpp, 14, 0); | |
c8466a91 JS |
309 | writel(val, ctx->addr + DECON_VIDW0xADD2(win)); |
310 | ||
0488f50e | 311 | decon_win_set_pixfmt(ctx, win, fb); |
c8466a91 JS |
312 | |
313 | /* window enable */ | |
b2192073 | 314 | decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, ~0); |
c8466a91 | 315 | |
c8466a91 | 316 | /* standalone update */ |
b2192073 | 317 | decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0); |
c8466a91 JS |
318 | } |
319 | ||
1e1d1393 GP |
320 | static void decon_disable_plane(struct exynos_drm_crtc *crtc, |
321 | struct exynos_drm_plane *plane) | |
c8466a91 JS |
322 | { |
323 | struct decon_context *ctx = crtc->ctx; | |
40bdfb0a | 324 | unsigned int win = plane->index; |
c8466a91 | 325 | |
7b6bb6ed | 326 | if (test_bit(BIT_SUSPENDED, &ctx->flags)) |
c8466a91 JS |
327 | return; |
328 | ||
329 | decon_shadow_protect_win(ctx, win, true); | |
330 | ||
331 | /* window disable */ | |
b2192073 | 332 | decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0); |
c8466a91 JS |
333 | |
334 | decon_shadow_protect_win(ctx, win, false); | |
335 | ||
336 | /* standalone update */ | |
b2192073 | 337 | decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0); |
c8466a91 JS |
338 | } |
339 | ||
d29c2c14 | 340 | static void decon_atomic_flush(struct exynos_drm_crtc *crtc) |
cc5a7b35 HH |
341 | { |
342 | struct decon_context *ctx = crtc->ctx; | |
d29c2c14 | 343 | int i; |
cc5a7b35 | 344 | |
7b6bb6ed | 345 | if (test_bit(BIT_SUSPENDED, &ctx->flags)) |
cc5a7b35 HH |
346 | return; |
347 | ||
d29c2c14 MS |
348 | for (i = ctx->first_win; i < WINDOWS_NR; i++) |
349 | decon_shadow_protect_win(ctx, i, false); | |
cc5a7b35 | 350 | |
b8182832 | 351 | if (ctx->out_type == IFTYPE_I80) |
7b6bb6ed | 352 | set_bit(BIT_WIN_UPDATED, &ctx->flags); |
cc5a7b35 HH |
353 | } |
354 | ||
c8466a91 JS |
355 | static void decon_swreset(struct decon_context *ctx) |
356 | { | |
357 | unsigned int tries; | |
358 | ||
359 | writel(0, ctx->addr + DECON_VIDCON0); | |
360 | for (tries = 2000; tries; --tries) { | |
361 | if (~readl(ctx->addr + DECON_VIDCON0) & VIDCON0_STOP_STATUS) | |
362 | break; | |
363 | udelay(10); | |
364 | } | |
365 | ||
366 | WARN(tries == 0, "failed to disable DECON\n"); | |
367 | ||
368 | writel(VIDCON0_SWRESET, ctx->addr + DECON_VIDCON0); | |
369 | for (tries = 2000; tries; --tries) { | |
370 | if (~readl(ctx->addr + DECON_VIDCON0) & VIDCON0_SWRESET) | |
371 | break; | |
372 | udelay(10); | |
373 | } | |
374 | ||
375 | WARN(tries == 0, "failed to software reset DECON\n"); | |
b8182832 AH |
376 | |
377 | if (ctx->out_type != IFTYPE_HDMI) | |
378 | return; | |
379 | ||
380 | writel(VIDCON0_CLKVALUP | VIDCON0_VLCKFREE, ctx->addr + DECON_VIDCON0); | |
381 | decon_set_bits(ctx, DECON_CMU, | |
382 | CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F, ~0); | |
383 | writel(VIDCON1_VCLK_RUN_VDEN_DISABLE, ctx->addr + DECON_VIDCON1); | |
384 | writel(CRCCTRL_CRCEN | CRCCTRL_CRCSTART_F | CRCCTRL_CRCCLKEN, | |
385 | ctx->addr + DECON_CRCCTRL); | |
386 | decon_setup_trigger(ctx); | |
c8466a91 JS |
387 | } |
388 | ||
389 | static void decon_enable(struct exynos_drm_crtc *crtc) | |
390 | { | |
391 | struct decon_context *ctx = crtc->ctx; | |
c8466a91 | 392 | |
7b6bb6ed | 393 | if (!test_and_clear_bit(BIT_SUSPENDED, &ctx->flags)) |
c8466a91 JS |
394 | return; |
395 | ||
c8466a91 JS |
396 | pm_runtime_get_sync(ctx->dev); |
397 | ||
7b6bb6ed | 398 | set_bit(BIT_CLKS_ENABLED, &ctx->flags); |
c8466a91 JS |
399 | |
400 | /* if vblank was enabled status, enable it again. */ | |
7b6bb6ed | 401 | if (test_and_clear_bit(BIT_IRQS_ENABLED, &ctx->flags)) |
c8466a91 JS |
402 | decon_enable_vblank(ctx->crtc); |
403 | ||
404 | decon_commit(ctx->crtc); | |
c8466a91 JS |
405 | } |
406 | ||
407 | static void decon_disable(struct exynos_drm_crtc *crtc) | |
408 | { | |
409 | struct decon_context *ctx = crtc->ctx; | |
410 | int i; | |
411 | ||
7b6bb6ed | 412 | if (test_bit(BIT_SUSPENDED, &ctx->flags)) |
c8466a91 JS |
413 | return; |
414 | ||
415 | /* | |
416 | * We need to make sure that all windows are disabled before we | |
417 | * suspend that connector. Otherwise we might try to scan from | |
418 | * a destroyed buffer later. | |
419 | */ | |
b8182832 | 420 | for (i = ctx->first_win; i < WINDOWS_NR; i++) |
1e1d1393 | 421 | decon_disable_plane(crtc, &ctx->planes[i]); |
c8466a91 JS |
422 | |
423 | decon_swreset(ctx); | |
424 | ||
7b6bb6ed | 425 | clear_bit(BIT_CLKS_ENABLED, &ctx->flags); |
c8466a91 JS |
426 | |
427 | pm_runtime_put_sync(ctx->dev); | |
428 | ||
7b6bb6ed | 429 | set_bit(BIT_SUSPENDED, &ctx->flags); |
c8466a91 JS |
430 | } |
431 | ||
432 | void decon_te_irq_handler(struct exynos_drm_crtc *crtc) | |
433 | { | |
434 | struct decon_context *ctx = crtc->ctx; | |
c8466a91 | 435 | |
7b6bb6ed | 436 | if (!test_bit(BIT_CLKS_ENABLED, &ctx->flags)) |
c8466a91 JS |
437 | return; |
438 | ||
7b6bb6ed | 439 | if (test_and_clear_bit(BIT_WIN_UPDATED, &ctx->flags)) |
b2192073 | 440 | decon_set_bits(ctx, DECON_TRIGCON, TRIGCON_SWTRIGCMD, ~0); |
c8466a91 | 441 | |
eafd540a | 442 | drm_crtc_handle_vblank(&ctx->crtc->base); |
c8466a91 JS |
443 | } |
444 | ||
445 | static void decon_clear_channels(struct exynos_drm_crtc *crtc) | |
446 | { | |
447 | struct decon_context *ctx = crtc->ctx; | |
448 | int win, i, ret; | |
c8466a91 JS |
449 | |
450 | DRM_DEBUG_KMS("%s\n", __FILE__); | |
451 | ||
452 | for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) { | |
453 | ret = clk_prepare_enable(ctx->clks[i]); | |
454 | if (ret < 0) | |
455 | goto err; | |
456 | } | |
457 | ||
458 | for (win = 0; win < WINDOWS_NR; win++) { | |
b2192073 AH |
459 | decon_shadow_protect_win(ctx, win, true); |
460 | decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0); | |
461 | decon_shadow_protect_win(ctx, win, false); | |
462 | decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0); | |
c8466a91 JS |
463 | } |
464 | /* TODO: wait for possible vsync */ | |
465 | msleep(50); | |
466 | ||
467 | err: | |
468 | while (--i >= 0) | |
469 | clk_disable_unprepare(ctx->clks[i]); | |
470 | } | |
471 | ||
472 | static struct exynos_drm_crtc_ops decon_crtc_ops = { | |
473 | .enable = decon_enable, | |
474 | .disable = decon_disable, | |
c8466a91 JS |
475 | .enable_vblank = decon_enable_vblank, |
476 | .disable_vblank = decon_disable_vblank, | |
cc5a7b35 | 477 | .atomic_begin = decon_atomic_begin, |
9cc7610a GP |
478 | .update_plane = decon_update_plane, |
479 | .disable_plane = decon_disable_plane, | |
cc5a7b35 | 480 | .atomic_flush = decon_atomic_flush, |
c8466a91 | 481 | .te_handler = decon_te_irq_handler, |
c8466a91 JS |
482 | }; |
483 | ||
484 | static int decon_bind(struct device *dev, struct device *master, void *data) | |
485 | { | |
486 | struct decon_context *ctx = dev_get_drvdata(dev); | |
487 | struct drm_device *drm_dev = data; | |
488 | struct exynos_drm_private *priv = drm_dev->dev_private; | |
489 | struct exynos_drm_plane *exynos_plane; | |
b8182832 | 490 | enum exynos_drm_output_type out_type; |
b8182832 | 491 | unsigned int win; |
c8466a91 JS |
492 | int ret; |
493 | ||
494 | ctx->drm_dev = drm_dev; | |
495 | ctx->pipe = priv->pipe++; | |
496 | ||
b8182832 AH |
497 | for (win = ctx->first_win; win < WINDOWS_NR; win++) { |
498 | int tmp = (win == ctx->first_win) ? 0 : win; | |
499 | ||
fd2d2fc2 MS |
500 | ctx->configs[win].pixel_formats = decon_formats; |
501 | ctx->configs[win].num_pixel_formats = ARRAY_SIZE(decon_formats); | |
502 | ctx->configs[win].zpos = win; | |
503 | ctx->configs[win].type = decon_win_types[tmp]; | |
504 | ||
40bdfb0a | 505 | ret = exynos_plane_init(drm_dev, &ctx->planes[win], win, |
fd2d2fc2 | 506 | 1 << ctx->pipe, &ctx->configs[win]); |
c8466a91 JS |
507 | if (ret) |
508 | return ret; | |
509 | } | |
510 | ||
b8182832 AH |
511 | exynos_plane = &ctx->planes[ctx->first_win]; |
512 | out_type = (ctx->out_type == IFTYPE_HDMI) ? EXYNOS_DISPLAY_TYPE_HDMI | |
513 | : EXYNOS_DISPLAY_TYPE_LCD; | |
c8466a91 | 514 | ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, |
b8182832 | 515 | ctx->pipe, out_type, |
c8466a91 JS |
516 | &decon_crtc_ops, ctx); |
517 | if (IS_ERR(ctx->crtc)) { | |
518 | ret = PTR_ERR(ctx->crtc); | |
519 | goto err; | |
520 | } | |
521 | ||
eb7a3fc7 JS |
522 | decon_clear_channels(ctx->crtc); |
523 | ||
524 | ret = drm_iommu_attach_device(drm_dev, dev); | |
c8466a91 JS |
525 | if (ret) |
526 | goto err; | |
527 | ||
528 | return ret; | |
529 | err: | |
530 | priv->pipe--; | |
531 | return ret; | |
532 | } | |
533 | ||
534 | static void decon_unbind(struct device *dev, struct device *master, void *data) | |
535 | { | |
536 | struct decon_context *ctx = dev_get_drvdata(dev); | |
537 | ||
538 | decon_disable(ctx->crtc); | |
539 | ||
540 | /* detach this sub driver from iommu mapping if supported. */ | |
bf56608a | 541 | drm_iommu_detach_device(ctx->drm_dev, ctx->dev); |
c8466a91 JS |
542 | } |
543 | ||
544 | static const struct component_ops decon_component_ops = { | |
545 | .bind = decon_bind, | |
546 | .unbind = decon_unbind, | |
547 | }; | |
548 | ||
b8182832 | 549 | static irqreturn_t decon_irq_handler(int irq, void *dev_id) |
c8466a91 JS |
550 | { |
551 | struct decon_context *ctx = dev_id; | |
552 | u32 val; | |
822f6dfd | 553 | int win; |
c8466a91 | 554 | |
7b6bb6ed | 555 | if (!test_bit(BIT_CLKS_ENABLED, &ctx->flags)) |
c8466a91 JS |
556 | goto out; |
557 | ||
558 | val = readl(ctx->addr + DECON_VIDINTCON1); | |
b8182832 AH |
559 | val &= VIDINTCON1_INTFRMDONEPEND | VIDINTCON1_INTFRMPEND; |
560 | ||
561 | if (val) { | |
562 | for (win = ctx->first_win; win < WINDOWS_NR ; win++) { | |
822f6dfd GP |
563 | struct exynos_drm_plane *plane = &ctx->planes[win]; |
564 | ||
565 | if (!plane->pending_fb) | |
566 | continue; | |
567 | ||
568 | exynos_drm_crtc_finish_update(ctx->crtc, plane); | |
569 | } | |
c8466a91 JS |
570 | |
571 | /* clear */ | |
b8182832 | 572 | writel(val, ctx->addr + DECON_VIDINTCON1); |
c8466a91 JS |
573 | } |
574 | ||
575 | out: | |
576 | return IRQ_HANDLED; | |
577 | } | |
578 | ||
ebf3fd40 GP |
579 | #ifdef CONFIG_PM |
580 | static int exynos5433_decon_suspend(struct device *dev) | |
581 | { | |
582 | struct decon_context *ctx = dev_get_drvdata(dev); | |
00780f3b | 583 | int i = ARRAY_SIZE(decon_clks_name); |
ebf3fd40 | 584 | |
00780f3b | 585 | while (--i >= 0) |
ebf3fd40 GP |
586 | clk_disable_unprepare(ctx->clks[i]); |
587 | ||
588 | return 0; | |
589 | } | |
590 | ||
591 | static int exynos5433_decon_resume(struct device *dev) | |
592 | { | |
593 | struct decon_context *ctx = dev_get_drvdata(dev); | |
594 | int i, ret; | |
595 | ||
596 | for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) { | |
597 | ret = clk_prepare_enable(ctx->clks[i]); | |
598 | if (ret < 0) | |
599 | goto err; | |
600 | } | |
601 | ||
602 | return 0; | |
603 | ||
604 | err: | |
605 | while (--i >= 0) | |
606 | clk_disable_unprepare(ctx->clks[i]); | |
607 | ||
608 | return ret; | |
609 | } | |
610 | #endif | |
611 | ||
612 | static const struct dev_pm_ops exynos5433_decon_pm_ops = { | |
613 | SET_RUNTIME_PM_OPS(exynos5433_decon_suspend, exynos5433_decon_resume, | |
614 | NULL) | |
615 | }; | |
616 | ||
b8182832 AH |
617 | static const struct of_device_id exynos5433_decon_driver_dt_match[] = { |
618 | { | |
619 | .compatible = "samsung,exynos5433-decon", | |
620 | .data = (void *)IFTYPE_RGB | |
621 | }, | |
622 | { | |
623 | .compatible = "samsung,exynos5433-decon-tv", | |
624 | .data = (void *)IFTYPE_HDMI | |
625 | }, | |
626 | {}, | |
627 | }; | |
628 | MODULE_DEVICE_TABLE(of, exynos5433_decon_driver_dt_match); | |
629 | ||
c8466a91 JS |
630 | static int exynos5433_decon_probe(struct platform_device *pdev) |
631 | { | |
b8182832 | 632 | const struct of_device_id *of_id; |
c8466a91 JS |
633 | struct device *dev = &pdev->dev; |
634 | struct decon_context *ctx; | |
635 | struct resource *res; | |
636 | int ret; | |
637 | int i; | |
638 | ||
639 | ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); | |
640 | if (!ctx) | |
641 | return -ENOMEM; | |
642 | ||
7b6bb6ed | 643 | __set_bit(BIT_SUSPENDED, &ctx->flags); |
c8466a91 | 644 | ctx->dev = dev; |
b8182832 AH |
645 | |
646 | of_id = of_match_device(exynos5433_decon_driver_dt_match, &pdev->dev); | |
647 | ctx->out_type = (enum decon_iftype)of_id->data; | |
648 | ||
649 | if (ctx->out_type == IFTYPE_HDMI) | |
650 | ctx->first_win = 1; | |
651 | else if (of_get_child_by_name(dev->of_node, "i80-if-timings")) | |
652 | ctx->out_type = IFTYPE_I80; | |
c8466a91 JS |
653 | |
654 | for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) { | |
655 | struct clk *clk; | |
656 | ||
657 | clk = devm_clk_get(ctx->dev, decon_clks_name[i]); | |
658 | if (IS_ERR(clk)) | |
659 | return PTR_ERR(clk); | |
660 | ||
661 | ctx->clks[i] = clk; | |
662 | } | |
663 | ||
664 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
665 | if (!res) { | |
666 | dev_err(dev, "cannot find IO resource\n"); | |
667 | return -ENXIO; | |
668 | } | |
669 | ||
670 | ctx->addr = devm_ioremap_resource(dev, res); | |
671 | if (IS_ERR(ctx->addr)) { | |
672 | dev_err(dev, "ioremap failed\n"); | |
673 | return PTR_ERR(ctx->addr); | |
674 | } | |
675 | ||
676 | res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, | |
b8182832 | 677 | (ctx->out_type == IFTYPE_I80) ? "lcd_sys" : "vsync"); |
c8466a91 JS |
678 | if (!res) { |
679 | dev_err(dev, "cannot find IRQ resource\n"); | |
680 | return -ENXIO; | |
681 | } | |
682 | ||
b8182832 AH |
683 | ret = devm_request_irq(dev, res->start, decon_irq_handler, 0, |
684 | "drm_decon", ctx); | |
c8466a91 JS |
685 | if (ret < 0) { |
686 | dev_err(dev, "lcd_sys irq request failed\n"); | |
687 | return ret; | |
688 | } | |
689 | ||
690 | platform_set_drvdata(pdev, ctx); | |
691 | ||
692 | pm_runtime_enable(dev); | |
693 | ||
694 | ret = component_add(dev, &decon_component_ops); | |
695 | if (ret) | |
696 | goto err_disable_pm_runtime; | |
697 | ||
698 | return 0; | |
699 | ||
700 | err_disable_pm_runtime: | |
701 | pm_runtime_disable(dev); | |
702 | ||
703 | return ret; | |
704 | } | |
705 | ||
706 | static int exynos5433_decon_remove(struct platform_device *pdev) | |
707 | { | |
708 | pm_runtime_disable(&pdev->dev); | |
709 | ||
710 | component_del(&pdev->dev, &decon_component_ops); | |
711 | ||
712 | return 0; | |
713 | } | |
714 | ||
c8466a91 JS |
715 | struct platform_driver exynos5433_decon_driver = { |
716 | .probe = exynos5433_decon_probe, | |
717 | .remove = exynos5433_decon_remove, | |
718 | .driver = { | |
719 | .name = "exynos5433-decon", | |
ebf3fd40 | 720 | .pm = &exynos5433_decon_pm_ops, |
c8466a91 JS |
721 | .of_match_table = exynos5433_decon_driver_dt_match, |
722 | }, | |
723 | }; |