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a8c21a54 T |
1 | /* |
2 | * Copyright (C) 2015 Etnaviv Project | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms of the GNU General Public License version 2 as published by | |
6 | * the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License along with | |
14 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
15 | */ | |
16 | ||
17 | #include <linux/component.h> | |
18 | #include <linux/fence.h> | |
19 | #include <linux/moduleparam.h> | |
20 | #include <linux/of_device.h> | |
21 | #include "etnaviv_dump.h" | |
22 | #include "etnaviv_gpu.h" | |
23 | #include "etnaviv_gem.h" | |
24 | #include "etnaviv_mmu.h" | |
25 | #include "etnaviv_iommu.h" | |
26 | #include "etnaviv_iommu_v2.h" | |
27 | #include "common.xml.h" | |
28 | #include "state.xml.h" | |
29 | #include "state_hi.xml.h" | |
30 | #include "cmdstream.xml.h" | |
31 | ||
32 | static const struct platform_device_id gpu_ids[] = { | |
33 | { .name = "etnaviv-gpu,2d" }, | |
34 | { }, | |
35 | }; | |
36 | ||
37 | static bool etnaviv_dump_core = true; | |
38 | module_param_named(dump_core, etnaviv_dump_core, bool, 0600); | |
39 | ||
40 | /* | |
41 | * Driver functions: | |
42 | */ | |
43 | ||
44 | int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value) | |
45 | { | |
46 | switch (param) { | |
47 | case ETNAVIV_PARAM_GPU_MODEL: | |
48 | *value = gpu->identity.model; | |
49 | break; | |
50 | ||
51 | case ETNAVIV_PARAM_GPU_REVISION: | |
52 | *value = gpu->identity.revision; | |
53 | break; | |
54 | ||
55 | case ETNAVIV_PARAM_GPU_FEATURES_0: | |
56 | *value = gpu->identity.features; | |
57 | break; | |
58 | ||
59 | case ETNAVIV_PARAM_GPU_FEATURES_1: | |
60 | *value = gpu->identity.minor_features0; | |
61 | break; | |
62 | ||
63 | case ETNAVIV_PARAM_GPU_FEATURES_2: | |
64 | *value = gpu->identity.minor_features1; | |
65 | break; | |
66 | ||
67 | case ETNAVIV_PARAM_GPU_FEATURES_3: | |
68 | *value = gpu->identity.minor_features2; | |
69 | break; | |
70 | ||
71 | case ETNAVIV_PARAM_GPU_FEATURES_4: | |
72 | *value = gpu->identity.minor_features3; | |
73 | break; | |
74 | ||
602eb489 RK |
75 | case ETNAVIV_PARAM_GPU_FEATURES_5: |
76 | *value = gpu->identity.minor_features4; | |
77 | break; | |
78 | ||
79 | case ETNAVIV_PARAM_GPU_FEATURES_6: | |
80 | *value = gpu->identity.minor_features5; | |
81 | break; | |
82 | ||
a8c21a54 T |
83 | case ETNAVIV_PARAM_GPU_STREAM_COUNT: |
84 | *value = gpu->identity.stream_count; | |
85 | break; | |
86 | ||
87 | case ETNAVIV_PARAM_GPU_REGISTER_MAX: | |
88 | *value = gpu->identity.register_max; | |
89 | break; | |
90 | ||
91 | case ETNAVIV_PARAM_GPU_THREAD_COUNT: | |
92 | *value = gpu->identity.thread_count; | |
93 | break; | |
94 | ||
95 | case ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE: | |
96 | *value = gpu->identity.vertex_cache_size; | |
97 | break; | |
98 | ||
99 | case ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT: | |
100 | *value = gpu->identity.shader_core_count; | |
101 | break; | |
102 | ||
103 | case ETNAVIV_PARAM_GPU_PIXEL_PIPES: | |
104 | *value = gpu->identity.pixel_pipes; | |
105 | break; | |
106 | ||
107 | case ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE: | |
108 | *value = gpu->identity.vertex_output_buffer_size; | |
109 | break; | |
110 | ||
111 | case ETNAVIV_PARAM_GPU_BUFFER_SIZE: | |
112 | *value = gpu->identity.buffer_size; | |
113 | break; | |
114 | ||
115 | case ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT: | |
116 | *value = gpu->identity.instruction_count; | |
117 | break; | |
118 | ||
119 | case ETNAVIV_PARAM_GPU_NUM_CONSTANTS: | |
120 | *value = gpu->identity.num_constants; | |
121 | break; | |
122 | ||
602eb489 RK |
123 | case ETNAVIV_PARAM_GPU_NUM_VARYINGS: |
124 | *value = gpu->identity.varyings_count; | |
125 | break; | |
126 | ||
a8c21a54 T |
127 | default: |
128 | DBG("%s: invalid param: %u", dev_name(gpu->dev), param); | |
129 | return -EINVAL; | |
130 | } | |
131 | ||
132 | return 0; | |
133 | } | |
134 | ||
472f79dc RK |
135 | |
136 | #define etnaviv_is_model_rev(gpu, mod, rev) \ | |
137 | ((gpu)->identity.model == chipModel_##mod && \ | |
138 | (gpu)->identity.revision == rev) | |
52f36ba1 RK |
139 | #define etnaviv_field(val, field) \ |
140 | (((val) & field##__MASK) >> field##__SHIFT) | |
141 | ||
a8c21a54 T |
142 | static void etnaviv_hw_specs(struct etnaviv_gpu *gpu) |
143 | { | |
144 | if (gpu->identity.minor_features0 & | |
145 | chipMinorFeatures0_MORE_MINOR_FEATURES) { | |
602eb489 RK |
146 | u32 specs[4]; |
147 | unsigned int streams; | |
a8c21a54 T |
148 | |
149 | specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS); | |
150 | specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2); | |
602eb489 RK |
151 | specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3); |
152 | specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4); | |
a8c21a54 | 153 | |
52f36ba1 RK |
154 | gpu->identity.stream_count = etnaviv_field(specs[0], |
155 | VIVS_HI_CHIP_SPECS_STREAM_COUNT); | |
156 | gpu->identity.register_max = etnaviv_field(specs[0], | |
157 | VIVS_HI_CHIP_SPECS_REGISTER_MAX); | |
158 | gpu->identity.thread_count = etnaviv_field(specs[0], | |
159 | VIVS_HI_CHIP_SPECS_THREAD_COUNT); | |
160 | gpu->identity.vertex_cache_size = etnaviv_field(specs[0], | |
161 | VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE); | |
162 | gpu->identity.shader_core_count = etnaviv_field(specs[0], | |
163 | VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT); | |
164 | gpu->identity.pixel_pipes = etnaviv_field(specs[0], | |
165 | VIVS_HI_CHIP_SPECS_PIXEL_PIPES); | |
a8c21a54 | 166 | gpu->identity.vertex_output_buffer_size = |
52f36ba1 RK |
167 | etnaviv_field(specs[0], |
168 | VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE); | |
169 | ||
170 | gpu->identity.buffer_size = etnaviv_field(specs[1], | |
171 | VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE); | |
172 | gpu->identity.instruction_count = etnaviv_field(specs[1], | |
173 | VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT); | |
174 | gpu->identity.num_constants = etnaviv_field(specs[1], | |
175 | VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS); | |
602eb489 RK |
176 | |
177 | gpu->identity.varyings_count = etnaviv_field(specs[2], | |
178 | VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT); | |
179 | ||
180 | /* This overrides the value from older register if non-zero */ | |
181 | streams = etnaviv_field(specs[3], | |
182 | VIVS_HI_CHIP_SPECS_4_STREAM_COUNT); | |
183 | if (streams) | |
184 | gpu->identity.stream_count = streams; | |
a8c21a54 T |
185 | } |
186 | ||
187 | /* Fill in the stream count if not specified */ | |
188 | if (gpu->identity.stream_count == 0) { | |
189 | if (gpu->identity.model >= 0x1000) | |
190 | gpu->identity.stream_count = 4; | |
191 | else | |
192 | gpu->identity.stream_count = 1; | |
193 | } | |
194 | ||
195 | /* Convert the register max value */ | |
196 | if (gpu->identity.register_max) | |
197 | gpu->identity.register_max = 1 << gpu->identity.register_max; | |
507f8991 | 198 | else if (gpu->identity.model == chipModel_GC400) |
a8c21a54 T |
199 | gpu->identity.register_max = 32; |
200 | else | |
201 | gpu->identity.register_max = 64; | |
202 | ||
203 | /* Convert thread count */ | |
204 | if (gpu->identity.thread_count) | |
205 | gpu->identity.thread_count = 1 << gpu->identity.thread_count; | |
507f8991 | 206 | else if (gpu->identity.model == chipModel_GC400) |
a8c21a54 | 207 | gpu->identity.thread_count = 64; |
507f8991 RK |
208 | else if (gpu->identity.model == chipModel_GC500 || |
209 | gpu->identity.model == chipModel_GC530) | |
a8c21a54 T |
210 | gpu->identity.thread_count = 128; |
211 | else | |
212 | gpu->identity.thread_count = 256; | |
213 | ||
214 | if (gpu->identity.vertex_cache_size == 0) | |
215 | gpu->identity.vertex_cache_size = 8; | |
216 | ||
217 | if (gpu->identity.shader_core_count == 0) { | |
218 | if (gpu->identity.model >= 0x1000) | |
219 | gpu->identity.shader_core_count = 2; | |
220 | else | |
221 | gpu->identity.shader_core_count = 1; | |
222 | } | |
223 | ||
224 | if (gpu->identity.pixel_pipes == 0) | |
225 | gpu->identity.pixel_pipes = 1; | |
226 | ||
227 | /* Convert virtex buffer size */ | |
228 | if (gpu->identity.vertex_output_buffer_size) { | |
229 | gpu->identity.vertex_output_buffer_size = | |
230 | 1 << gpu->identity.vertex_output_buffer_size; | |
507f8991 | 231 | } else if (gpu->identity.model == chipModel_GC400) { |
a8c21a54 T |
232 | if (gpu->identity.revision < 0x4000) |
233 | gpu->identity.vertex_output_buffer_size = 512; | |
234 | else if (gpu->identity.revision < 0x4200) | |
235 | gpu->identity.vertex_output_buffer_size = 256; | |
236 | else | |
237 | gpu->identity.vertex_output_buffer_size = 128; | |
238 | } else { | |
239 | gpu->identity.vertex_output_buffer_size = 512; | |
240 | } | |
241 | ||
242 | switch (gpu->identity.instruction_count) { | |
243 | case 0: | |
472f79dc | 244 | if (etnaviv_is_model_rev(gpu, GC2000, 0x5108) || |
507f8991 | 245 | gpu->identity.model == chipModel_GC880) |
a8c21a54 T |
246 | gpu->identity.instruction_count = 512; |
247 | else | |
248 | gpu->identity.instruction_count = 256; | |
249 | break; | |
250 | ||
251 | case 1: | |
252 | gpu->identity.instruction_count = 1024; | |
253 | break; | |
254 | ||
255 | case 2: | |
256 | gpu->identity.instruction_count = 2048; | |
257 | break; | |
258 | ||
259 | default: | |
260 | gpu->identity.instruction_count = 256; | |
261 | break; | |
262 | } | |
263 | ||
264 | if (gpu->identity.num_constants == 0) | |
265 | gpu->identity.num_constants = 168; | |
602eb489 RK |
266 | |
267 | if (gpu->identity.varyings_count == 0) { | |
268 | if (gpu->identity.minor_features1 & chipMinorFeatures1_HALTI0) | |
269 | gpu->identity.varyings_count = 12; | |
270 | else | |
271 | gpu->identity.varyings_count = 8; | |
272 | } | |
273 | ||
274 | /* | |
275 | * For some cores, two varyings are consumed for position, so the | |
276 | * maximum varying count needs to be reduced by one. | |
277 | */ | |
278 | if (etnaviv_is_model_rev(gpu, GC5000, 0x5434) || | |
279 | etnaviv_is_model_rev(gpu, GC4000, 0x5222) || | |
280 | etnaviv_is_model_rev(gpu, GC4000, 0x5245) || | |
281 | etnaviv_is_model_rev(gpu, GC4000, 0x5208) || | |
282 | etnaviv_is_model_rev(gpu, GC3000, 0x5435) || | |
283 | etnaviv_is_model_rev(gpu, GC2200, 0x5244) || | |
284 | etnaviv_is_model_rev(gpu, GC2100, 0x5108) || | |
285 | etnaviv_is_model_rev(gpu, GC2000, 0x5108) || | |
286 | etnaviv_is_model_rev(gpu, GC1500, 0x5246) || | |
287 | etnaviv_is_model_rev(gpu, GC880, 0x5107) || | |
288 | etnaviv_is_model_rev(gpu, GC880, 0x5106)) | |
289 | gpu->identity.varyings_count -= 1; | |
a8c21a54 T |
290 | } |
291 | ||
292 | static void etnaviv_hw_identify(struct etnaviv_gpu *gpu) | |
293 | { | |
294 | u32 chipIdentity; | |
295 | ||
296 | chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY); | |
297 | ||
298 | /* Special case for older graphic cores. */ | |
52f36ba1 | 299 | if (etnaviv_field(chipIdentity, VIVS_HI_CHIP_IDENTITY_FAMILY) == 0x01) { |
507f8991 | 300 | gpu->identity.model = chipModel_GC500; |
52f36ba1 RK |
301 | gpu->identity.revision = etnaviv_field(chipIdentity, |
302 | VIVS_HI_CHIP_IDENTITY_REVISION); | |
a8c21a54 T |
303 | } else { |
304 | ||
305 | gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL); | |
306 | gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV); | |
307 | ||
308 | /* | |
309 | * !!!! HACK ALERT !!!! | |
310 | * Because people change device IDs without letting software | |
311 | * know about it - here is the hack to make it all look the | |
312 | * same. Only for GC400 family. | |
313 | */ | |
314 | if ((gpu->identity.model & 0xff00) == 0x0400 && | |
507f8991 | 315 | gpu->identity.model != chipModel_GC420) { |
a8c21a54 T |
316 | gpu->identity.model = gpu->identity.model & 0x0400; |
317 | } | |
318 | ||
319 | /* Another special case */ | |
472f79dc | 320 | if (etnaviv_is_model_rev(gpu, GC300, 0x2201)) { |
a8c21a54 T |
321 | u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE); |
322 | u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME); | |
323 | ||
324 | if (chipDate == 0x20080814 && chipTime == 0x12051100) { | |
325 | /* | |
326 | * This IP has an ECO; put the correct | |
327 | * revision in it. | |
328 | */ | |
329 | gpu->identity.revision = 0x1051; | |
330 | } | |
331 | } | |
332 | } | |
333 | ||
334 | dev_info(gpu->dev, "model: GC%x, revision: %x\n", | |
335 | gpu->identity.model, gpu->identity.revision); | |
336 | ||
337 | gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE); | |
338 | ||
339 | /* Disable fast clear on GC700. */ | |
507f8991 | 340 | if (gpu->identity.model == chipModel_GC700) |
a8c21a54 T |
341 | gpu->identity.features &= ~chipFeatures_FAST_CLEAR; |
342 | ||
507f8991 RK |
343 | if ((gpu->identity.model == chipModel_GC500 && |
344 | gpu->identity.revision < 2) || | |
345 | (gpu->identity.model == chipModel_GC300 && | |
346 | gpu->identity.revision < 0x2000)) { | |
a8c21a54 T |
347 | |
348 | /* | |
349 | * GC500 rev 1.x and GC300 rev < 2.0 doesn't have these | |
350 | * registers. | |
351 | */ | |
352 | gpu->identity.minor_features0 = 0; | |
353 | gpu->identity.minor_features1 = 0; | |
354 | gpu->identity.minor_features2 = 0; | |
355 | gpu->identity.minor_features3 = 0; | |
602eb489 RK |
356 | gpu->identity.minor_features4 = 0; |
357 | gpu->identity.minor_features5 = 0; | |
a8c21a54 T |
358 | } else |
359 | gpu->identity.minor_features0 = | |
360 | gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0); | |
361 | ||
362 | if (gpu->identity.minor_features0 & | |
363 | chipMinorFeatures0_MORE_MINOR_FEATURES) { | |
364 | gpu->identity.minor_features1 = | |
365 | gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1); | |
366 | gpu->identity.minor_features2 = | |
367 | gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2); | |
368 | gpu->identity.minor_features3 = | |
369 | gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3); | |
602eb489 RK |
370 | gpu->identity.minor_features4 = |
371 | gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4); | |
372 | gpu->identity.minor_features5 = | |
373 | gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5); | |
a8c21a54 T |
374 | } |
375 | ||
376 | /* GC600 idle register reports zero bits where modules aren't present */ | |
377 | if (gpu->identity.model == chipModel_GC600) { | |
378 | gpu->idle_mask = VIVS_HI_IDLE_STATE_TX | | |
379 | VIVS_HI_IDLE_STATE_RA | | |
380 | VIVS_HI_IDLE_STATE_SE | | |
381 | VIVS_HI_IDLE_STATE_PA | | |
382 | VIVS_HI_IDLE_STATE_SH | | |
383 | VIVS_HI_IDLE_STATE_PE | | |
384 | VIVS_HI_IDLE_STATE_DE | | |
385 | VIVS_HI_IDLE_STATE_FE; | |
386 | } else { | |
387 | gpu->idle_mask = ~VIVS_HI_IDLE_STATE_AXI_LP; | |
388 | } | |
389 | ||
390 | etnaviv_hw_specs(gpu); | |
391 | } | |
392 | ||
393 | static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock) | |
394 | { | |
395 | gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock | | |
396 | VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD); | |
397 | gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); | |
398 | } | |
399 | ||
400 | static int etnaviv_hw_reset(struct etnaviv_gpu *gpu) | |
401 | { | |
402 | u32 control, idle; | |
403 | unsigned long timeout; | |
404 | bool failed = true; | |
405 | ||
406 | /* TODO | |
407 | * | |
408 | * - clock gating | |
409 | * - puls eater | |
410 | * - what about VG? | |
411 | */ | |
412 | ||
413 | /* We hope that the GPU resets in under one second */ | |
414 | timeout = jiffies + msecs_to_jiffies(1000); | |
415 | ||
416 | while (time_is_after_jiffies(timeout)) { | |
417 | control = VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS | | |
418 | VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(0x40); | |
419 | ||
420 | /* enable clock */ | |
421 | etnaviv_gpu_load_clock(gpu, control); | |
422 | ||
423 | /* Wait for stable clock. Vivante's code waited for 1ms */ | |
424 | usleep_range(1000, 10000); | |
425 | ||
426 | /* isolate the GPU. */ | |
427 | control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU; | |
428 | gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); | |
429 | ||
430 | /* set soft reset. */ | |
431 | control |= VIVS_HI_CLOCK_CONTROL_SOFT_RESET; | |
432 | gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); | |
433 | ||
434 | /* wait for reset. */ | |
435 | msleep(1); | |
436 | ||
437 | /* reset soft reset bit. */ | |
438 | control &= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET; | |
439 | gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); | |
440 | ||
441 | /* reset GPU isolation. */ | |
442 | control &= ~VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU; | |
443 | gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); | |
444 | ||
445 | /* read idle register. */ | |
446 | idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); | |
447 | ||
448 | /* try reseting again if FE it not idle */ | |
449 | if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) { | |
450 | dev_dbg(gpu->dev, "FE is not idle\n"); | |
451 | continue; | |
452 | } | |
453 | ||
454 | /* read reset register. */ | |
455 | control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); | |
456 | ||
457 | /* is the GPU idle? */ | |
458 | if (((control & VIVS_HI_CLOCK_CONTROL_IDLE_3D) == 0) || | |
459 | ((control & VIVS_HI_CLOCK_CONTROL_IDLE_2D) == 0)) { | |
460 | dev_dbg(gpu->dev, "GPU is not idle\n"); | |
461 | continue; | |
462 | } | |
463 | ||
464 | failed = false; | |
465 | break; | |
466 | } | |
467 | ||
468 | if (failed) { | |
469 | idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); | |
470 | control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); | |
471 | ||
472 | dev_err(gpu->dev, "GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidle\n", | |
473 | idle & VIVS_HI_IDLE_STATE_FE ? "" : "not ", | |
474 | control & VIVS_HI_CLOCK_CONTROL_IDLE_3D ? "" : "not ", | |
475 | control & VIVS_HI_CLOCK_CONTROL_IDLE_2D ? "" : "not "); | |
476 | ||
477 | return -EBUSY; | |
478 | } | |
479 | ||
480 | /* We rely on the GPU running, so program the clock */ | |
481 | control = VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS | | |
482 | VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(0x40); | |
483 | ||
484 | /* enable clock */ | |
485 | etnaviv_gpu_load_clock(gpu, control); | |
486 | ||
487 | return 0; | |
488 | } | |
489 | ||
7d0c6e71 RK |
490 | static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu) |
491 | { | |
492 | u32 pmc, ppc; | |
493 | ||
494 | /* enable clock gating */ | |
495 | ppc = gpu_read(gpu, VIVS_PM_POWER_CONTROLS); | |
496 | ppc |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING; | |
497 | ||
498 | /* Disable stall module clock gating for 4.3.0.1 and 4.3.0.2 revs */ | |
499 | if (gpu->identity.revision == 0x4301 || | |
500 | gpu->identity.revision == 0x4302) | |
501 | ppc |= VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING; | |
502 | ||
503 | gpu_write(gpu, VIVS_PM_POWER_CONTROLS, ppc); | |
504 | ||
505 | pmc = gpu_read(gpu, VIVS_PM_MODULE_CONTROLS); | |
506 | ||
507 | /* Disable PA clock gating for GC400+ except for GC420 */ | |
508 | if (gpu->identity.model >= chipModel_GC400 && | |
509 | gpu->identity.model != chipModel_GC420) | |
510 | pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA; | |
511 | ||
512 | /* | |
513 | * Disable PE clock gating on revs < 5.0.0.0 when HZ is | |
514 | * present without a bug fix. | |
515 | */ | |
516 | if (gpu->identity.revision < 0x5000 && | |
517 | gpu->identity.minor_features0 & chipMinorFeatures0_HZ && | |
518 | !(gpu->identity.minor_features1 & | |
519 | chipMinorFeatures1_DISABLE_PE_GATING)) | |
520 | pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE; | |
521 | ||
522 | if (gpu->identity.revision < 0x5422) | |
523 | pmc |= BIT(15); /* Unknown bit */ | |
524 | ||
525 | pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ; | |
526 | pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ; | |
527 | ||
528 | gpu_write(gpu, VIVS_PM_MODULE_CONTROLS, pmc); | |
529 | } | |
530 | ||
a8c21a54 T |
531 | static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu) |
532 | { | |
533 | u16 prefetch; | |
534 | ||
472f79dc RK |
535 | if ((etnaviv_is_model_rev(gpu, GC320, 0x5007) || |
536 | etnaviv_is_model_rev(gpu, GC320, 0x5220)) && | |
537 | gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) { | |
a8c21a54 T |
538 | u32 mc_memory_debug; |
539 | ||
540 | mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff; | |
541 | ||
542 | if (gpu->identity.revision == 0x5007) | |
543 | mc_memory_debug |= 0x0c; | |
544 | else | |
545 | mc_memory_debug |= 0x08; | |
546 | ||
547 | gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug); | |
548 | } | |
549 | ||
7d0c6e71 RK |
550 | /* enable module-level clock gating */ |
551 | etnaviv_gpu_enable_mlcg(gpu); | |
552 | ||
a8c21a54 T |
553 | /* |
554 | * Update GPU AXI cache atttribute to "cacheable, no allocate". | |
555 | * This is necessary to prevent the iMX6 SoC locking up. | |
556 | */ | |
557 | gpu_write(gpu, VIVS_HI_AXI_CONFIG, | |
558 | VIVS_HI_AXI_CONFIG_AWCACHE(2) | | |
559 | VIVS_HI_AXI_CONFIG_ARCACHE(2)); | |
560 | ||
561 | /* GC2000 rev 5108 needs a special bus config */ | |
472f79dc | 562 | if (etnaviv_is_model_rev(gpu, GC2000, 0x5108)) { |
a8c21a54 T |
563 | u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG); |
564 | bus_config &= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK | | |
565 | VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK); | |
566 | bus_config |= VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(1) | | |
567 | VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(0); | |
568 | gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config); | |
569 | } | |
570 | ||
571 | /* set base addresses */ | |
572 | gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_RA, gpu->memory_base); | |
573 | gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_FE, gpu->memory_base); | |
574 | gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_TX, gpu->memory_base); | |
575 | gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PEZ, gpu->memory_base); | |
576 | gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PE, gpu->memory_base); | |
577 | ||
578 | /* setup the MMU page table pointers */ | |
579 | etnaviv_iommu_domain_restore(gpu, gpu->mmu->domain); | |
580 | ||
581 | /* Start command processor */ | |
582 | prefetch = etnaviv_buffer_init(gpu); | |
583 | ||
584 | gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U); | |
585 | gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS, | |
586 | gpu->buffer->paddr - gpu->memory_base); | |
587 | gpu_write(gpu, VIVS_FE_COMMAND_CONTROL, | |
588 | VIVS_FE_COMMAND_CONTROL_ENABLE | | |
589 | VIVS_FE_COMMAND_CONTROL_PREFETCH(prefetch)); | |
590 | } | |
591 | ||
592 | int etnaviv_gpu_init(struct etnaviv_gpu *gpu) | |
593 | { | |
594 | int ret, i; | |
595 | struct iommu_domain *iommu; | |
596 | enum etnaviv_iommu_version version; | |
597 | bool mmuv2; | |
598 | ||
599 | ret = pm_runtime_get_sync(gpu->dev); | |
600 | if (ret < 0) | |
601 | return ret; | |
602 | ||
603 | etnaviv_hw_identify(gpu); | |
604 | ||
605 | if (gpu->identity.model == 0) { | |
606 | dev_err(gpu->dev, "Unknown GPU model\n"); | |
f6427760 RK |
607 | ret = -ENXIO; |
608 | goto fail; | |
a8c21a54 T |
609 | } |
610 | ||
b98c6688 RK |
611 | /* Exclude VG cores with FE2.0 */ |
612 | if (gpu->identity.features & chipFeatures_PIPE_VG && | |
613 | gpu->identity.features & chipFeatures_FE20) { | |
614 | dev_info(gpu->dev, "Ignoring GPU with VG and FE2.0\n"); | |
615 | ret = -ENXIO; | |
616 | goto fail; | |
617 | } | |
618 | ||
2144fff7 LS |
619 | /* |
620 | * Set the GPU linear window to be at the end of the DMA window, where | |
621 | * the CMA area is likely to reside. This ensures that we are able to | |
622 | * map the command buffers while having the linear window overlap as | |
623 | * much RAM as possible, so we can optimize mappings for other buffers. | |
624 | * | |
625 | * For 3D cores only do this if MC2.0 is present, as with MC1.0 it leads | |
626 | * to different views of the memory on the individual engines. | |
627 | */ | |
628 | if (!(gpu->identity.features & chipFeatures_PIPE_3D) || | |
629 | (gpu->identity.minor_features0 & chipMinorFeatures0_MC20)) { | |
630 | u32 dma_mask = (u32)dma_get_required_mask(gpu->dev); | |
631 | if (dma_mask < PHYS_OFFSET + SZ_2G) | |
632 | gpu->memory_base = PHYS_OFFSET; | |
633 | else | |
634 | gpu->memory_base = dma_mask - SZ_2G + 1; | |
635 | } | |
636 | ||
a8c21a54 T |
637 | ret = etnaviv_hw_reset(gpu); |
638 | if (ret) | |
639 | goto fail; | |
640 | ||
641 | /* Setup IOMMU.. eventually we will (I think) do this once per context | |
642 | * and have separate page tables per context. For now, to keep things | |
643 | * simple and to get something working, just use a single address space: | |
644 | */ | |
645 | mmuv2 = gpu->identity.minor_features1 & chipMinorFeatures1_MMU_VERSION; | |
646 | dev_dbg(gpu->dev, "mmuv2: %d\n", mmuv2); | |
647 | ||
648 | if (!mmuv2) { | |
649 | iommu = etnaviv_iommu_domain_alloc(gpu); | |
650 | version = ETNAVIV_IOMMU_V1; | |
651 | } else { | |
652 | iommu = etnaviv_iommu_v2_domain_alloc(gpu); | |
653 | version = ETNAVIV_IOMMU_V2; | |
654 | } | |
655 | ||
656 | if (!iommu) { | |
657 | ret = -ENOMEM; | |
658 | goto fail; | |
659 | } | |
660 | ||
a8c21a54 T |
661 | gpu->mmu = etnaviv_iommu_new(gpu, iommu, version); |
662 | if (!gpu->mmu) { | |
45d16a6d | 663 | iommu_domain_free(iommu); |
a8c21a54 T |
664 | ret = -ENOMEM; |
665 | goto fail; | |
666 | } | |
667 | ||
668 | /* Create buffer: */ | |
669 | gpu->buffer = etnaviv_gpu_cmdbuf_new(gpu, PAGE_SIZE, 0); | |
670 | if (!gpu->buffer) { | |
671 | ret = -ENOMEM; | |
672 | dev_err(gpu->dev, "could not create command buffer\n"); | |
45d16a6d | 673 | goto destroy_iommu; |
a8c21a54 T |
674 | } |
675 | if (gpu->buffer->paddr - gpu->memory_base > 0x80000000) { | |
676 | ret = -EINVAL; | |
677 | dev_err(gpu->dev, | |
678 | "command buffer outside valid memory window\n"); | |
679 | goto free_buffer; | |
680 | } | |
681 | ||
682 | /* Setup event management */ | |
683 | spin_lock_init(&gpu->event_spinlock); | |
684 | init_completion(&gpu->event_free); | |
685 | for (i = 0; i < ARRAY_SIZE(gpu->event); i++) { | |
686 | gpu->event[i].used = false; | |
687 | complete(&gpu->event_free); | |
688 | } | |
689 | ||
690 | /* Now program the hardware */ | |
691 | mutex_lock(&gpu->lock); | |
692 | etnaviv_gpu_hw_init(gpu); | |
f6086311 | 693 | gpu->exec_state = -1; |
a8c21a54 T |
694 | mutex_unlock(&gpu->lock); |
695 | ||
696 | pm_runtime_mark_last_busy(gpu->dev); | |
697 | pm_runtime_put_autosuspend(gpu->dev); | |
698 | ||
699 | return 0; | |
700 | ||
701 | free_buffer: | |
702 | etnaviv_gpu_cmdbuf_free(gpu->buffer); | |
703 | gpu->buffer = NULL; | |
45d16a6d LS |
704 | destroy_iommu: |
705 | etnaviv_iommu_destroy(gpu->mmu); | |
706 | gpu->mmu = NULL; | |
a8c21a54 T |
707 | fail: |
708 | pm_runtime_mark_last_busy(gpu->dev); | |
709 | pm_runtime_put_autosuspend(gpu->dev); | |
710 | ||
711 | return ret; | |
712 | } | |
713 | ||
714 | #ifdef CONFIG_DEBUG_FS | |
715 | struct dma_debug { | |
716 | u32 address[2]; | |
717 | u32 state[2]; | |
718 | }; | |
719 | ||
720 | static void verify_dma(struct etnaviv_gpu *gpu, struct dma_debug *debug) | |
721 | { | |
722 | u32 i; | |
723 | ||
724 | debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); | |
725 | debug->state[0] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE); | |
726 | ||
727 | for (i = 0; i < 500; i++) { | |
728 | debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); | |
729 | debug->state[1] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE); | |
730 | ||
731 | if (debug->address[0] != debug->address[1]) | |
732 | break; | |
733 | ||
734 | if (debug->state[0] != debug->state[1]) | |
735 | break; | |
736 | } | |
737 | } | |
738 | ||
739 | int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m) | |
740 | { | |
741 | struct dma_debug debug; | |
742 | u32 dma_lo, dma_hi, axi, idle; | |
743 | int ret; | |
744 | ||
745 | seq_printf(m, "%s Status:\n", dev_name(gpu->dev)); | |
746 | ||
747 | ret = pm_runtime_get_sync(gpu->dev); | |
748 | if (ret < 0) | |
749 | return ret; | |
750 | ||
751 | dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW); | |
752 | dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH); | |
753 | axi = gpu_read(gpu, VIVS_HI_AXI_STATUS); | |
754 | idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); | |
755 | ||
756 | verify_dma(gpu, &debug); | |
757 | ||
758 | seq_puts(m, "\tfeatures\n"); | |
759 | seq_printf(m, "\t minor_features0: 0x%08x\n", | |
760 | gpu->identity.minor_features0); | |
761 | seq_printf(m, "\t minor_features1: 0x%08x\n", | |
762 | gpu->identity.minor_features1); | |
763 | seq_printf(m, "\t minor_features2: 0x%08x\n", | |
764 | gpu->identity.minor_features2); | |
765 | seq_printf(m, "\t minor_features3: 0x%08x\n", | |
766 | gpu->identity.minor_features3); | |
602eb489 RK |
767 | seq_printf(m, "\t minor_features4: 0x%08x\n", |
768 | gpu->identity.minor_features4); | |
769 | seq_printf(m, "\t minor_features5: 0x%08x\n", | |
770 | gpu->identity.minor_features5); | |
a8c21a54 T |
771 | |
772 | seq_puts(m, "\tspecs\n"); | |
773 | seq_printf(m, "\t stream_count: %d\n", | |
774 | gpu->identity.stream_count); | |
775 | seq_printf(m, "\t register_max: %d\n", | |
776 | gpu->identity.register_max); | |
777 | seq_printf(m, "\t thread_count: %d\n", | |
778 | gpu->identity.thread_count); | |
779 | seq_printf(m, "\t vertex_cache_size: %d\n", | |
780 | gpu->identity.vertex_cache_size); | |
781 | seq_printf(m, "\t shader_core_count: %d\n", | |
782 | gpu->identity.shader_core_count); | |
783 | seq_printf(m, "\t pixel_pipes: %d\n", | |
784 | gpu->identity.pixel_pipes); | |
785 | seq_printf(m, "\t vertex_output_buffer_size: %d\n", | |
786 | gpu->identity.vertex_output_buffer_size); | |
787 | seq_printf(m, "\t buffer_size: %d\n", | |
788 | gpu->identity.buffer_size); | |
789 | seq_printf(m, "\t instruction_count: %d\n", | |
790 | gpu->identity.instruction_count); | |
791 | seq_printf(m, "\t num_constants: %d\n", | |
792 | gpu->identity.num_constants); | |
602eb489 RK |
793 | seq_printf(m, "\t varyings_count: %d\n", |
794 | gpu->identity.varyings_count); | |
a8c21a54 T |
795 | |
796 | seq_printf(m, "\taxi: 0x%08x\n", axi); | |
797 | seq_printf(m, "\tidle: 0x%08x\n", idle); | |
798 | idle |= ~gpu->idle_mask & ~VIVS_HI_IDLE_STATE_AXI_LP; | |
799 | if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) | |
800 | seq_puts(m, "\t FE is not idle\n"); | |
801 | if ((idle & VIVS_HI_IDLE_STATE_DE) == 0) | |
802 | seq_puts(m, "\t DE is not idle\n"); | |
803 | if ((idle & VIVS_HI_IDLE_STATE_PE) == 0) | |
804 | seq_puts(m, "\t PE is not idle\n"); | |
805 | if ((idle & VIVS_HI_IDLE_STATE_SH) == 0) | |
806 | seq_puts(m, "\t SH is not idle\n"); | |
807 | if ((idle & VIVS_HI_IDLE_STATE_PA) == 0) | |
808 | seq_puts(m, "\t PA is not idle\n"); | |
809 | if ((idle & VIVS_HI_IDLE_STATE_SE) == 0) | |
810 | seq_puts(m, "\t SE is not idle\n"); | |
811 | if ((idle & VIVS_HI_IDLE_STATE_RA) == 0) | |
812 | seq_puts(m, "\t RA is not idle\n"); | |
813 | if ((idle & VIVS_HI_IDLE_STATE_TX) == 0) | |
814 | seq_puts(m, "\t TX is not idle\n"); | |
815 | if ((idle & VIVS_HI_IDLE_STATE_VG) == 0) | |
816 | seq_puts(m, "\t VG is not idle\n"); | |
817 | if ((idle & VIVS_HI_IDLE_STATE_IM) == 0) | |
818 | seq_puts(m, "\t IM is not idle\n"); | |
819 | if ((idle & VIVS_HI_IDLE_STATE_FP) == 0) | |
820 | seq_puts(m, "\t FP is not idle\n"); | |
821 | if ((idle & VIVS_HI_IDLE_STATE_TS) == 0) | |
822 | seq_puts(m, "\t TS is not idle\n"); | |
823 | if (idle & VIVS_HI_IDLE_STATE_AXI_LP) | |
824 | seq_puts(m, "\t AXI low power mode\n"); | |
825 | ||
826 | if (gpu->identity.features & chipFeatures_DEBUG_MODE) { | |
827 | u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0); | |
828 | u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1); | |
829 | u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE); | |
830 | ||
831 | seq_puts(m, "\tMC\n"); | |
832 | seq_printf(m, "\t read0: 0x%08x\n", read0); | |
833 | seq_printf(m, "\t read1: 0x%08x\n", read1); | |
834 | seq_printf(m, "\t write: 0x%08x\n", write); | |
835 | } | |
836 | ||
837 | seq_puts(m, "\tDMA "); | |
838 | ||
839 | if (debug.address[0] == debug.address[1] && | |
840 | debug.state[0] == debug.state[1]) { | |
841 | seq_puts(m, "seems to be stuck\n"); | |
842 | } else if (debug.address[0] == debug.address[1]) { | |
c01e0159 | 843 | seq_puts(m, "address is constant\n"); |
a8c21a54 | 844 | } else { |
c01e0159 | 845 | seq_puts(m, "is running\n"); |
a8c21a54 T |
846 | } |
847 | ||
848 | seq_printf(m, "\t address 0: 0x%08x\n", debug.address[0]); | |
849 | seq_printf(m, "\t address 1: 0x%08x\n", debug.address[1]); | |
850 | seq_printf(m, "\t state 0: 0x%08x\n", debug.state[0]); | |
851 | seq_printf(m, "\t state 1: 0x%08x\n", debug.state[1]); | |
852 | seq_printf(m, "\t last fetch 64 bit word: 0x%08x 0x%08x\n", | |
853 | dma_lo, dma_hi); | |
854 | ||
855 | ret = 0; | |
856 | ||
857 | pm_runtime_mark_last_busy(gpu->dev); | |
858 | pm_runtime_put_autosuspend(gpu->dev); | |
859 | ||
860 | return ret; | |
861 | } | |
862 | #endif | |
863 | ||
864 | /* | |
865 | * Power Management: | |
866 | */ | |
867 | static int enable_clk(struct etnaviv_gpu *gpu) | |
868 | { | |
869 | if (gpu->clk_core) | |
870 | clk_prepare_enable(gpu->clk_core); | |
871 | if (gpu->clk_shader) | |
872 | clk_prepare_enable(gpu->clk_shader); | |
873 | ||
874 | return 0; | |
875 | } | |
876 | ||
877 | static int disable_clk(struct etnaviv_gpu *gpu) | |
878 | { | |
879 | if (gpu->clk_core) | |
880 | clk_disable_unprepare(gpu->clk_core); | |
881 | if (gpu->clk_shader) | |
882 | clk_disable_unprepare(gpu->clk_shader); | |
883 | ||
884 | return 0; | |
885 | } | |
886 | ||
887 | static int enable_axi(struct etnaviv_gpu *gpu) | |
888 | { | |
889 | if (gpu->clk_bus) | |
890 | clk_prepare_enable(gpu->clk_bus); | |
891 | ||
892 | return 0; | |
893 | } | |
894 | ||
895 | static int disable_axi(struct etnaviv_gpu *gpu) | |
896 | { | |
897 | if (gpu->clk_bus) | |
898 | clk_disable_unprepare(gpu->clk_bus); | |
899 | ||
900 | return 0; | |
901 | } | |
902 | ||
903 | /* | |
904 | * Hangcheck detection for locked gpu: | |
905 | */ | |
906 | static void recover_worker(struct work_struct *work) | |
907 | { | |
908 | struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu, | |
909 | recover_work); | |
910 | unsigned long flags; | |
911 | unsigned int i; | |
912 | ||
913 | dev_err(gpu->dev, "hangcheck recover!\n"); | |
914 | ||
915 | if (pm_runtime_get_sync(gpu->dev) < 0) | |
916 | return; | |
917 | ||
918 | mutex_lock(&gpu->lock); | |
919 | ||
920 | /* Only catch the first event, or when manually re-armed */ | |
921 | if (etnaviv_dump_core) { | |
922 | etnaviv_core_dump(gpu); | |
923 | etnaviv_dump_core = false; | |
924 | } | |
925 | ||
926 | etnaviv_hw_reset(gpu); | |
927 | ||
928 | /* complete all events, the GPU won't do it after the reset */ | |
929 | spin_lock_irqsave(&gpu->event_spinlock, flags); | |
930 | for (i = 0; i < ARRAY_SIZE(gpu->event); i++) { | |
931 | if (!gpu->event[i].used) | |
932 | continue; | |
933 | fence_signal(gpu->event[i].fence); | |
934 | gpu->event[i].fence = NULL; | |
935 | gpu->event[i].used = false; | |
936 | complete(&gpu->event_free); | |
a8c21a54 T |
937 | } |
938 | spin_unlock_irqrestore(&gpu->event_spinlock, flags); | |
939 | gpu->completed_fence = gpu->active_fence; | |
940 | ||
941 | etnaviv_gpu_hw_init(gpu); | |
942 | gpu->switch_context = true; | |
f6086311 | 943 | gpu->exec_state = -1; |
a8c21a54 T |
944 | |
945 | mutex_unlock(&gpu->lock); | |
946 | pm_runtime_mark_last_busy(gpu->dev); | |
947 | pm_runtime_put_autosuspend(gpu->dev); | |
948 | ||
949 | /* Retire the buffer objects in a work */ | |
950 | etnaviv_queue_work(gpu->drm, &gpu->retire_work); | |
951 | } | |
952 | ||
953 | static void hangcheck_timer_reset(struct etnaviv_gpu *gpu) | |
954 | { | |
955 | DBG("%s", dev_name(gpu->dev)); | |
956 | mod_timer(&gpu->hangcheck_timer, | |
957 | round_jiffies_up(jiffies + DRM_ETNAVIV_HANGCHECK_JIFFIES)); | |
958 | } | |
959 | ||
960 | static void hangcheck_handler(unsigned long data) | |
961 | { | |
962 | struct etnaviv_gpu *gpu = (struct etnaviv_gpu *)data; | |
963 | u32 fence = gpu->completed_fence; | |
964 | bool progress = false; | |
965 | ||
966 | if (fence != gpu->hangcheck_fence) { | |
967 | gpu->hangcheck_fence = fence; | |
968 | progress = true; | |
969 | } | |
970 | ||
971 | if (!progress) { | |
972 | u32 dma_addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); | |
973 | int change = dma_addr - gpu->hangcheck_dma_addr; | |
974 | ||
975 | if (change < 0 || change > 16) { | |
976 | gpu->hangcheck_dma_addr = dma_addr; | |
977 | progress = true; | |
978 | } | |
979 | } | |
980 | ||
981 | if (!progress && fence_after(gpu->active_fence, fence)) { | |
982 | dev_err(gpu->dev, "hangcheck detected gpu lockup!\n"); | |
983 | dev_err(gpu->dev, " completed fence: %u\n", fence); | |
984 | dev_err(gpu->dev, " active fence: %u\n", | |
985 | gpu->active_fence); | |
986 | etnaviv_queue_work(gpu->drm, &gpu->recover_work); | |
987 | } | |
988 | ||
989 | /* if still more pending work, reset the hangcheck timer: */ | |
990 | if (fence_after(gpu->active_fence, gpu->hangcheck_fence)) | |
991 | hangcheck_timer_reset(gpu); | |
992 | } | |
993 | ||
994 | static void hangcheck_disable(struct etnaviv_gpu *gpu) | |
995 | { | |
996 | del_timer_sync(&gpu->hangcheck_timer); | |
997 | cancel_work_sync(&gpu->recover_work); | |
998 | } | |
999 | ||
1000 | /* fence object management */ | |
1001 | struct etnaviv_fence { | |
1002 | struct etnaviv_gpu *gpu; | |
1003 | struct fence base; | |
1004 | }; | |
1005 | ||
1006 | static inline struct etnaviv_fence *to_etnaviv_fence(struct fence *fence) | |
1007 | { | |
1008 | return container_of(fence, struct etnaviv_fence, base); | |
1009 | } | |
1010 | ||
1011 | static const char *etnaviv_fence_get_driver_name(struct fence *fence) | |
1012 | { | |
1013 | return "etnaviv"; | |
1014 | } | |
1015 | ||
1016 | static const char *etnaviv_fence_get_timeline_name(struct fence *fence) | |
1017 | { | |
1018 | struct etnaviv_fence *f = to_etnaviv_fence(fence); | |
1019 | ||
1020 | return dev_name(f->gpu->dev); | |
1021 | } | |
1022 | ||
1023 | static bool etnaviv_fence_enable_signaling(struct fence *fence) | |
1024 | { | |
1025 | return true; | |
1026 | } | |
1027 | ||
1028 | static bool etnaviv_fence_signaled(struct fence *fence) | |
1029 | { | |
1030 | struct etnaviv_fence *f = to_etnaviv_fence(fence); | |
1031 | ||
1032 | return fence_completed(f->gpu, f->base.seqno); | |
1033 | } | |
1034 | ||
1035 | static void etnaviv_fence_release(struct fence *fence) | |
1036 | { | |
1037 | struct etnaviv_fence *f = to_etnaviv_fence(fence); | |
1038 | ||
1039 | kfree_rcu(f, base.rcu); | |
1040 | } | |
1041 | ||
1042 | static const struct fence_ops etnaviv_fence_ops = { | |
1043 | .get_driver_name = etnaviv_fence_get_driver_name, | |
1044 | .get_timeline_name = etnaviv_fence_get_timeline_name, | |
1045 | .enable_signaling = etnaviv_fence_enable_signaling, | |
1046 | .signaled = etnaviv_fence_signaled, | |
1047 | .wait = fence_default_wait, | |
1048 | .release = etnaviv_fence_release, | |
1049 | }; | |
1050 | ||
1051 | static struct fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu) | |
1052 | { | |
1053 | struct etnaviv_fence *f; | |
1054 | ||
1055 | f = kzalloc(sizeof(*f), GFP_KERNEL); | |
1056 | if (!f) | |
1057 | return NULL; | |
1058 | ||
1059 | f->gpu = gpu; | |
1060 | ||
1061 | fence_init(&f->base, &etnaviv_fence_ops, &gpu->fence_spinlock, | |
1062 | gpu->fence_context, ++gpu->next_fence); | |
1063 | ||
1064 | return &f->base; | |
1065 | } | |
1066 | ||
1067 | int etnaviv_gpu_fence_sync_obj(struct etnaviv_gem_object *etnaviv_obj, | |
1068 | unsigned int context, bool exclusive) | |
1069 | { | |
1070 | struct reservation_object *robj = etnaviv_obj->resv; | |
1071 | struct reservation_object_list *fobj; | |
1072 | struct fence *fence; | |
1073 | int i, ret; | |
1074 | ||
1075 | if (!exclusive) { | |
1076 | ret = reservation_object_reserve_shared(robj); | |
1077 | if (ret) | |
1078 | return ret; | |
1079 | } | |
1080 | ||
1081 | /* | |
1082 | * If we have any shared fences, then the exclusive fence | |
1083 | * should be ignored as it will already have been signalled. | |
1084 | */ | |
1085 | fobj = reservation_object_get_list(robj); | |
1086 | if (!fobj || fobj->shared_count == 0) { | |
1087 | /* Wait on any existing exclusive fence which isn't our own */ | |
1088 | fence = reservation_object_get_excl(robj); | |
1089 | if (fence && fence->context != context) { | |
1090 | ret = fence_wait(fence, true); | |
1091 | if (ret) | |
1092 | return ret; | |
1093 | } | |
1094 | } | |
1095 | ||
1096 | if (!exclusive || !fobj) | |
1097 | return 0; | |
1098 | ||
1099 | for (i = 0; i < fobj->shared_count; i++) { | |
1100 | fence = rcu_dereference_protected(fobj->shared[i], | |
1101 | reservation_object_held(robj)); | |
1102 | if (fence->context != context) { | |
1103 | ret = fence_wait(fence, true); | |
1104 | if (ret) | |
1105 | return ret; | |
1106 | } | |
1107 | } | |
1108 | ||
1109 | return 0; | |
1110 | } | |
1111 | ||
1112 | /* | |
1113 | * event management: | |
1114 | */ | |
1115 | ||
1116 | static unsigned int event_alloc(struct etnaviv_gpu *gpu) | |
1117 | { | |
1118 | unsigned long ret, flags; | |
1119 | unsigned int i, event = ~0U; | |
1120 | ||
1121 | ret = wait_for_completion_timeout(&gpu->event_free, | |
1122 | msecs_to_jiffies(10 * 10000)); | |
1123 | if (!ret) | |
1124 | dev_err(gpu->dev, "wait_for_completion_timeout failed"); | |
1125 | ||
1126 | spin_lock_irqsave(&gpu->event_spinlock, flags); | |
1127 | ||
1128 | /* find first free event */ | |
1129 | for (i = 0; i < ARRAY_SIZE(gpu->event); i++) { | |
1130 | if (gpu->event[i].used == false) { | |
1131 | gpu->event[i].used = true; | |
1132 | event = i; | |
1133 | break; | |
1134 | } | |
1135 | } | |
1136 | ||
1137 | spin_unlock_irqrestore(&gpu->event_spinlock, flags); | |
1138 | ||
1139 | return event; | |
1140 | } | |
1141 | ||
1142 | static void event_free(struct etnaviv_gpu *gpu, unsigned int event) | |
1143 | { | |
1144 | unsigned long flags; | |
1145 | ||
1146 | spin_lock_irqsave(&gpu->event_spinlock, flags); | |
1147 | ||
1148 | if (gpu->event[event].used == false) { | |
1149 | dev_warn(gpu->dev, "event %u is already marked as free", | |
1150 | event); | |
1151 | spin_unlock_irqrestore(&gpu->event_spinlock, flags); | |
1152 | } else { | |
1153 | gpu->event[event].used = false; | |
1154 | spin_unlock_irqrestore(&gpu->event_spinlock, flags); | |
1155 | ||
1156 | complete(&gpu->event_free); | |
1157 | } | |
1158 | } | |
1159 | ||
1160 | /* | |
1161 | * Cmdstream submission/retirement: | |
1162 | */ | |
1163 | ||
1164 | struct etnaviv_cmdbuf *etnaviv_gpu_cmdbuf_new(struct etnaviv_gpu *gpu, u32 size, | |
1165 | size_t nr_bos) | |
1166 | { | |
1167 | struct etnaviv_cmdbuf *cmdbuf; | |
b6325f40 | 1168 | size_t sz = size_vstruct(nr_bos, sizeof(cmdbuf->bo_map[0]), |
a8c21a54 T |
1169 | sizeof(*cmdbuf)); |
1170 | ||
1171 | cmdbuf = kzalloc(sz, GFP_KERNEL); | |
1172 | if (!cmdbuf) | |
1173 | return NULL; | |
1174 | ||
f6e45661 LR |
1175 | cmdbuf->vaddr = dma_alloc_wc(gpu->dev, size, &cmdbuf->paddr, |
1176 | GFP_KERNEL); | |
a8c21a54 T |
1177 | if (!cmdbuf->vaddr) { |
1178 | kfree(cmdbuf); | |
1179 | return NULL; | |
1180 | } | |
1181 | ||
1182 | cmdbuf->gpu = gpu; | |
1183 | cmdbuf->size = size; | |
1184 | ||
1185 | return cmdbuf; | |
1186 | } | |
1187 | ||
1188 | void etnaviv_gpu_cmdbuf_free(struct etnaviv_cmdbuf *cmdbuf) | |
1189 | { | |
f6e45661 LR |
1190 | dma_free_wc(cmdbuf->gpu->dev, cmdbuf->size, cmdbuf->vaddr, |
1191 | cmdbuf->paddr); | |
a8c21a54 T |
1192 | kfree(cmdbuf); |
1193 | } | |
1194 | ||
1195 | static void retire_worker(struct work_struct *work) | |
1196 | { | |
1197 | struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu, | |
1198 | retire_work); | |
1199 | u32 fence = gpu->completed_fence; | |
1200 | struct etnaviv_cmdbuf *cmdbuf, *tmp; | |
1201 | unsigned int i; | |
1202 | ||
1203 | mutex_lock(&gpu->lock); | |
1204 | list_for_each_entry_safe(cmdbuf, tmp, &gpu->active_cmd_list, node) { | |
1205 | if (!fence_is_signaled(cmdbuf->fence)) | |
1206 | break; | |
1207 | ||
1208 | list_del(&cmdbuf->node); | |
1209 | fence_put(cmdbuf->fence); | |
1210 | ||
1211 | for (i = 0; i < cmdbuf->nr_bos; i++) { | |
b6325f40 RK |
1212 | struct etnaviv_vram_mapping *mapping = cmdbuf->bo_map[i]; |
1213 | struct etnaviv_gem_object *etnaviv_obj = mapping->object; | |
a8c21a54 T |
1214 | |
1215 | atomic_dec(&etnaviv_obj->gpu_active); | |
1216 | /* drop the refcount taken in etnaviv_gpu_submit */ | |
b6325f40 | 1217 | etnaviv_gem_mapping_unreference(mapping); |
a8c21a54 T |
1218 | } |
1219 | ||
1220 | etnaviv_gpu_cmdbuf_free(cmdbuf); | |
d9fd0c7d LS |
1221 | /* |
1222 | * We need to balance the runtime PM count caused by | |
1223 | * each submission. Upon submission, we increment | |
1224 | * the runtime PM counter, and allocate one event. | |
1225 | * So here, we put the runtime PM count for each | |
1226 | * completed event. | |
1227 | */ | |
1228 | pm_runtime_put_autosuspend(gpu->dev); | |
a8c21a54 T |
1229 | } |
1230 | ||
1231 | gpu->retired_fence = fence; | |
1232 | ||
1233 | mutex_unlock(&gpu->lock); | |
1234 | ||
1235 | wake_up_all(&gpu->fence_event); | |
1236 | } | |
1237 | ||
1238 | int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu, | |
1239 | u32 fence, struct timespec *timeout) | |
1240 | { | |
1241 | int ret; | |
1242 | ||
1243 | if (fence_after(fence, gpu->next_fence)) { | |
1244 | DRM_ERROR("waiting on invalid fence: %u (of %u)\n", | |
1245 | fence, gpu->next_fence); | |
1246 | return -EINVAL; | |
1247 | } | |
1248 | ||
1249 | if (!timeout) { | |
1250 | /* No timeout was requested: just test for completion */ | |
1251 | ret = fence_completed(gpu, fence) ? 0 : -EBUSY; | |
1252 | } else { | |
1253 | unsigned long remaining = etnaviv_timeout_to_jiffies(timeout); | |
1254 | ||
1255 | ret = wait_event_interruptible_timeout(gpu->fence_event, | |
1256 | fence_completed(gpu, fence), | |
1257 | remaining); | |
1258 | if (ret == 0) { | |
1259 | DBG("timeout waiting for fence: %u (retired: %u completed: %u)", | |
1260 | fence, gpu->retired_fence, | |
1261 | gpu->completed_fence); | |
1262 | ret = -ETIMEDOUT; | |
1263 | } else if (ret != -ERESTARTSYS) { | |
1264 | ret = 0; | |
1265 | } | |
1266 | } | |
1267 | ||
1268 | return ret; | |
1269 | } | |
1270 | ||
1271 | /* | |
1272 | * Wait for an object to become inactive. This, on it's own, is not race | |
1273 | * free: the object is moved by the retire worker off the active list, and | |
1274 | * then the iova is put. Moreover, the object could be re-submitted just | |
1275 | * after we notice that it's become inactive. | |
1276 | * | |
1277 | * Although the retirement happens under the gpu lock, we don't want to hold | |
1278 | * that lock in this function while waiting. | |
1279 | */ | |
1280 | int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu, | |
1281 | struct etnaviv_gem_object *etnaviv_obj, struct timespec *timeout) | |
1282 | { | |
1283 | unsigned long remaining; | |
1284 | long ret; | |
1285 | ||
1286 | if (!timeout) | |
1287 | return !is_active(etnaviv_obj) ? 0 : -EBUSY; | |
1288 | ||
1289 | remaining = etnaviv_timeout_to_jiffies(timeout); | |
1290 | ||
1291 | ret = wait_event_interruptible_timeout(gpu->fence_event, | |
1292 | !is_active(etnaviv_obj), | |
1293 | remaining); | |
1294 | if (ret > 0) { | |
1295 | struct etnaviv_drm_private *priv = gpu->drm->dev_private; | |
1296 | ||
1297 | /* Synchronise with the retire worker */ | |
1298 | flush_workqueue(priv->wq); | |
1299 | return 0; | |
1300 | } else if (ret == -ERESTARTSYS) { | |
1301 | return -ERESTARTSYS; | |
1302 | } else { | |
1303 | return -ETIMEDOUT; | |
1304 | } | |
1305 | } | |
1306 | ||
1307 | int etnaviv_gpu_pm_get_sync(struct etnaviv_gpu *gpu) | |
1308 | { | |
1309 | return pm_runtime_get_sync(gpu->dev); | |
1310 | } | |
1311 | ||
1312 | void etnaviv_gpu_pm_put(struct etnaviv_gpu *gpu) | |
1313 | { | |
1314 | pm_runtime_mark_last_busy(gpu->dev); | |
1315 | pm_runtime_put_autosuspend(gpu->dev); | |
1316 | } | |
1317 | ||
1318 | /* add bo's to gpu's ring, and kick gpu: */ | |
1319 | int etnaviv_gpu_submit(struct etnaviv_gpu *gpu, | |
1320 | struct etnaviv_gem_submit *submit, struct etnaviv_cmdbuf *cmdbuf) | |
1321 | { | |
1322 | struct fence *fence; | |
1323 | unsigned int event, i; | |
1324 | int ret; | |
1325 | ||
1326 | ret = etnaviv_gpu_pm_get_sync(gpu); | |
1327 | if (ret < 0) | |
1328 | return ret; | |
1329 | ||
1330 | mutex_lock(&gpu->lock); | |
1331 | ||
1332 | /* | |
1333 | * TODO | |
1334 | * | |
1335 | * - flush | |
1336 | * - data endian | |
1337 | * - prefetch | |
1338 | * | |
1339 | */ | |
1340 | ||
1341 | event = event_alloc(gpu); | |
1342 | if (unlikely(event == ~0U)) { | |
1343 | DRM_ERROR("no free event\n"); | |
1344 | ret = -EBUSY; | |
1345 | goto out_unlock; | |
1346 | } | |
1347 | ||
1348 | fence = etnaviv_gpu_fence_alloc(gpu); | |
1349 | if (!fence) { | |
1350 | event_free(gpu, event); | |
1351 | ret = -ENOMEM; | |
1352 | goto out_unlock; | |
1353 | } | |
1354 | ||
1355 | gpu->event[event].fence = fence; | |
1356 | submit->fence = fence->seqno; | |
1357 | gpu->active_fence = submit->fence; | |
1358 | ||
1359 | if (gpu->lastctx != cmdbuf->ctx) { | |
1360 | gpu->mmu->need_flush = true; | |
1361 | gpu->switch_context = true; | |
1362 | gpu->lastctx = cmdbuf->ctx; | |
1363 | } | |
1364 | ||
1365 | etnaviv_buffer_queue(gpu, event, cmdbuf); | |
1366 | ||
1367 | cmdbuf->fence = fence; | |
1368 | list_add_tail(&cmdbuf->node, &gpu->active_cmd_list); | |
1369 | ||
1370 | /* We're committed to adding this command buffer, hold a PM reference */ | |
1371 | pm_runtime_get_noresume(gpu->dev); | |
1372 | ||
1373 | for (i = 0; i < submit->nr_bos; i++) { | |
1374 | struct etnaviv_gem_object *etnaviv_obj = submit->bos[i].obj; | |
a8c21a54 | 1375 | |
b6325f40 RK |
1376 | /* Each cmdbuf takes a refcount on the mapping */ |
1377 | etnaviv_gem_mapping_reference(submit->bos[i].mapping); | |
1378 | cmdbuf->bo_map[i] = submit->bos[i].mapping; | |
a8c21a54 T |
1379 | atomic_inc(&etnaviv_obj->gpu_active); |
1380 | ||
1381 | if (submit->bos[i].flags & ETNA_SUBMIT_BO_WRITE) | |
1382 | reservation_object_add_excl_fence(etnaviv_obj->resv, | |
1383 | fence); | |
1384 | else | |
1385 | reservation_object_add_shared_fence(etnaviv_obj->resv, | |
1386 | fence); | |
1387 | } | |
1388 | cmdbuf->nr_bos = submit->nr_bos; | |
1389 | hangcheck_timer_reset(gpu); | |
1390 | ret = 0; | |
1391 | ||
1392 | out_unlock: | |
1393 | mutex_unlock(&gpu->lock); | |
1394 | ||
1395 | etnaviv_gpu_pm_put(gpu); | |
1396 | ||
1397 | return ret; | |
1398 | } | |
1399 | ||
1400 | /* | |
1401 | * Init/Cleanup: | |
1402 | */ | |
1403 | static irqreturn_t irq_handler(int irq, void *data) | |
1404 | { | |
1405 | struct etnaviv_gpu *gpu = data; | |
1406 | irqreturn_t ret = IRQ_NONE; | |
1407 | ||
1408 | u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE); | |
1409 | ||
1410 | if (intr != 0) { | |
1411 | int event; | |
1412 | ||
1413 | pm_runtime_mark_last_busy(gpu->dev); | |
1414 | ||
1415 | dev_dbg(gpu->dev, "intr 0x%08x\n", intr); | |
1416 | ||
1417 | if (intr & VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR) { | |
1418 | dev_err(gpu->dev, "AXI bus error\n"); | |
1419 | intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR; | |
1420 | } | |
1421 | ||
1422 | while ((event = ffs(intr)) != 0) { | |
1423 | struct fence *fence; | |
1424 | ||
1425 | event -= 1; | |
1426 | ||
1427 | intr &= ~(1 << event); | |
1428 | ||
1429 | dev_dbg(gpu->dev, "event %u\n", event); | |
1430 | ||
1431 | fence = gpu->event[event].fence; | |
1432 | gpu->event[event].fence = NULL; | |
1433 | fence_signal(fence); | |
1434 | ||
1435 | /* | |
1436 | * Events can be processed out of order. Eg, | |
1437 | * - allocate and queue event 0 | |
1438 | * - allocate event 1 | |
1439 | * - event 0 completes, we process it | |
1440 | * - allocate and queue event 0 | |
1441 | * - event 1 and event 0 complete | |
1442 | * we can end up processing event 0 first, then 1. | |
1443 | */ | |
1444 | if (fence_after(fence->seqno, gpu->completed_fence)) | |
1445 | gpu->completed_fence = fence->seqno; | |
1446 | ||
1447 | event_free(gpu, event); | |
a8c21a54 T |
1448 | } |
1449 | ||
1450 | /* Retire the buffer objects in a work */ | |
1451 | etnaviv_queue_work(gpu->drm, &gpu->retire_work); | |
1452 | ||
1453 | ret = IRQ_HANDLED; | |
1454 | } | |
1455 | ||
1456 | return ret; | |
1457 | } | |
1458 | ||
1459 | static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu) | |
1460 | { | |
1461 | int ret; | |
1462 | ||
1463 | ret = enable_clk(gpu); | |
1464 | if (ret) | |
1465 | return ret; | |
1466 | ||
1467 | ret = enable_axi(gpu); | |
1468 | if (ret) { | |
1469 | disable_clk(gpu); | |
1470 | return ret; | |
1471 | } | |
1472 | ||
1473 | return 0; | |
1474 | } | |
1475 | ||
1476 | static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu) | |
1477 | { | |
1478 | int ret; | |
1479 | ||
1480 | ret = disable_axi(gpu); | |
1481 | if (ret) | |
1482 | return ret; | |
1483 | ||
1484 | ret = disable_clk(gpu); | |
1485 | if (ret) | |
1486 | return ret; | |
1487 | ||
1488 | return 0; | |
1489 | } | |
1490 | ||
1491 | static int etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu) | |
1492 | { | |
1493 | if (gpu->buffer) { | |
1494 | unsigned long timeout; | |
1495 | ||
1496 | /* Replace the last WAIT with END */ | |
1497 | etnaviv_buffer_end(gpu); | |
1498 | ||
1499 | /* | |
1500 | * We know that only the FE is busy here, this should | |
1501 | * happen quickly (as the WAIT is only 200 cycles). If | |
1502 | * we fail, just warn and continue. | |
1503 | */ | |
1504 | timeout = jiffies + msecs_to_jiffies(100); | |
1505 | do { | |
1506 | u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); | |
1507 | ||
1508 | if ((idle & gpu->idle_mask) == gpu->idle_mask) | |
1509 | break; | |
1510 | ||
1511 | if (time_is_before_jiffies(timeout)) { | |
1512 | dev_warn(gpu->dev, | |
1513 | "timed out waiting for idle: idle=0x%x\n", | |
1514 | idle); | |
1515 | break; | |
1516 | } | |
1517 | ||
1518 | udelay(5); | |
1519 | } while (1); | |
1520 | } | |
1521 | ||
1522 | return etnaviv_gpu_clk_disable(gpu); | |
1523 | } | |
1524 | ||
1525 | #ifdef CONFIG_PM | |
1526 | static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu) | |
1527 | { | |
1528 | u32 clock; | |
1529 | int ret; | |
1530 | ||
1531 | ret = mutex_lock_killable(&gpu->lock); | |
1532 | if (ret) | |
1533 | return ret; | |
1534 | ||
1535 | clock = VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS | | |
1536 | VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(0x40); | |
1537 | ||
1538 | etnaviv_gpu_load_clock(gpu, clock); | |
1539 | etnaviv_gpu_hw_init(gpu); | |
1540 | ||
1541 | gpu->switch_context = true; | |
f6086311 | 1542 | gpu->exec_state = -1; |
a8c21a54 T |
1543 | |
1544 | mutex_unlock(&gpu->lock); | |
1545 | ||
1546 | return 0; | |
1547 | } | |
1548 | #endif | |
1549 | ||
1550 | static int etnaviv_gpu_bind(struct device *dev, struct device *master, | |
1551 | void *data) | |
1552 | { | |
1553 | struct drm_device *drm = data; | |
1554 | struct etnaviv_drm_private *priv = drm->dev_private; | |
1555 | struct etnaviv_gpu *gpu = dev_get_drvdata(dev); | |
1556 | int ret; | |
1557 | ||
1558 | #ifdef CONFIG_PM | |
1559 | ret = pm_runtime_get_sync(gpu->dev); | |
1560 | #else | |
1561 | ret = etnaviv_gpu_clk_enable(gpu); | |
1562 | #endif | |
1563 | if (ret < 0) | |
1564 | return ret; | |
1565 | ||
1566 | gpu->drm = drm; | |
1567 | gpu->fence_context = fence_context_alloc(1); | |
1568 | spin_lock_init(&gpu->fence_spinlock); | |
1569 | ||
1570 | INIT_LIST_HEAD(&gpu->active_cmd_list); | |
1571 | INIT_WORK(&gpu->retire_work, retire_worker); | |
1572 | INIT_WORK(&gpu->recover_work, recover_worker); | |
1573 | init_waitqueue_head(&gpu->fence_event); | |
1574 | ||
946dd8d5 LS |
1575 | setup_deferrable_timer(&gpu->hangcheck_timer, hangcheck_handler, |
1576 | (unsigned long)gpu); | |
a8c21a54 T |
1577 | |
1578 | priv->gpu[priv->num_gpus++] = gpu; | |
1579 | ||
1580 | pm_runtime_mark_last_busy(gpu->dev); | |
1581 | pm_runtime_put_autosuspend(gpu->dev); | |
1582 | ||
1583 | return 0; | |
1584 | } | |
1585 | ||
1586 | static void etnaviv_gpu_unbind(struct device *dev, struct device *master, | |
1587 | void *data) | |
1588 | { | |
1589 | struct etnaviv_gpu *gpu = dev_get_drvdata(dev); | |
1590 | ||
1591 | DBG("%s", dev_name(gpu->dev)); | |
1592 | ||
1593 | hangcheck_disable(gpu); | |
1594 | ||
1595 | #ifdef CONFIG_PM | |
1596 | pm_runtime_get_sync(gpu->dev); | |
1597 | pm_runtime_put_sync_suspend(gpu->dev); | |
1598 | #else | |
1599 | etnaviv_gpu_hw_suspend(gpu); | |
1600 | #endif | |
1601 | ||
1602 | if (gpu->buffer) { | |
1603 | etnaviv_gpu_cmdbuf_free(gpu->buffer); | |
1604 | gpu->buffer = NULL; | |
1605 | } | |
1606 | ||
1607 | if (gpu->mmu) { | |
1608 | etnaviv_iommu_destroy(gpu->mmu); | |
1609 | gpu->mmu = NULL; | |
1610 | } | |
1611 | ||
1612 | gpu->drm = NULL; | |
1613 | } | |
1614 | ||
1615 | static const struct component_ops gpu_ops = { | |
1616 | .bind = etnaviv_gpu_bind, | |
1617 | .unbind = etnaviv_gpu_unbind, | |
1618 | }; | |
1619 | ||
1620 | static const struct of_device_id etnaviv_gpu_match[] = { | |
1621 | { | |
1622 | .compatible = "vivante,gc" | |
1623 | }, | |
1624 | { /* sentinel */ } | |
1625 | }; | |
1626 | ||
1627 | static int etnaviv_gpu_platform_probe(struct platform_device *pdev) | |
1628 | { | |
1629 | struct device *dev = &pdev->dev; | |
1630 | struct etnaviv_gpu *gpu; | |
1631 | int err = 0; | |
1632 | ||
1633 | gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL); | |
1634 | if (!gpu) | |
1635 | return -ENOMEM; | |
1636 | ||
1637 | gpu->dev = &pdev->dev; | |
1638 | mutex_init(&gpu->lock); | |
1639 | ||
a8c21a54 T |
1640 | /* Map registers: */ |
1641 | gpu->mmio = etnaviv_ioremap(pdev, NULL, dev_name(gpu->dev)); | |
1642 | if (IS_ERR(gpu->mmio)) | |
1643 | return PTR_ERR(gpu->mmio); | |
1644 | ||
1645 | /* Get Interrupt: */ | |
1646 | gpu->irq = platform_get_irq(pdev, 0); | |
1647 | if (gpu->irq < 0) { | |
1648 | err = gpu->irq; | |
1649 | dev_err(dev, "failed to get irq: %d\n", err); | |
1650 | goto fail; | |
1651 | } | |
1652 | ||
1653 | err = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 0, | |
1654 | dev_name(gpu->dev), gpu); | |
1655 | if (err) { | |
1656 | dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err); | |
1657 | goto fail; | |
1658 | } | |
1659 | ||
1660 | /* Get Clocks: */ | |
1661 | gpu->clk_bus = devm_clk_get(&pdev->dev, "bus"); | |
1662 | DBG("clk_bus: %p", gpu->clk_bus); | |
1663 | if (IS_ERR(gpu->clk_bus)) | |
1664 | gpu->clk_bus = NULL; | |
1665 | ||
1666 | gpu->clk_core = devm_clk_get(&pdev->dev, "core"); | |
1667 | DBG("clk_core: %p", gpu->clk_core); | |
1668 | if (IS_ERR(gpu->clk_core)) | |
1669 | gpu->clk_core = NULL; | |
1670 | ||
1671 | gpu->clk_shader = devm_clk_get(&pdev->dev, "shader"); | |
1672 | DBG("clk_shader: %p", gpu->clk_shader); | |
1673 | if (IS_ERR(gpu->clk_shader)) | |
1674 | gpu->clk_shader = NULL; | |
1675 | ||
1676 | /* TODO: figure out max mapped size */ | |
1677 | dev_set_drvdata(dev, gpu); | |
1678 | ||
1679 | /* | |
1680 | * We treat the device as initially suspended. The runtime PM | |
1681 | * autosuspend delay is rather arbitary: no measurements have | |
1682 | * yet been performed to determine an appropriate value. | |
1683 | */ | |
1684 | pm_runtime_use_autosuspend(gpu->dev); | |
1685 | pm_runtime_set_autosuspend_delay(gpu->dev, 200); | |
1686 | pm_runtime_enable(gpu->dev); | |
1687 | ||
1688 | err = component_add(&pdev->dev, &gpu_ops); | |
1689 | if (err < 0) { | |
1690 | dev_err(&pdev->dev, "failed to register component: %d\n", err); | |
1691 | goto fail; | |
1692 | } | |
1693 | ||
1694 | return 0; | |
1695 | ||
1696 | fail: | |
1697 | return err; | |
1698 | } | |
1699 | ||
1700 | static int etnaviv_gpu_platform_remove(struct platform_device *pdev) | |
1701 | { | |
1702 | component_del(&pdev->dev, &gpu_ops); | |
1703 | pm_runtime_disable(&pdev->dev); | |
1704 | return 0; | |
1705 | } | |
1706 | ||
1707 | #ifdef CONFIG_PM | |
1708 | static int etnaviv_gpu_rpm_suspend(struct device *dev) | |
1709 | { | |
1710 | struct etnaviv_gpu *gpu = dev_get_drvdata(dev); | |
1711 | u32 idle, mask; | |
1712 | ||
1713 | /* If we have outstanding fences, we're not idle */ | |
1714 | if (gpu->completed_fence != gpu->active_fence) | |
1715 | return -EBUSY; | |
1716 | ||
1717 | /* Check whether the hardware (except FE) is idle */ | |
1718 | mask = gpu->idle_mask & ~VIVS_HI_IDLE_STATE_FE; | |
1719 | idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask; | |
1720 | if (idle != mask) | |
1721 | return -EBUSY; | |
1722 | ||
1723 | return etnaviv_gpu_hw_suspend(gpu); | |
1724 | } | |
1725 | ||
1726 | static int etnaviv_gpu_rpm_resume(struct device *dev) | |
1727 | { | |
1728 | struct etnaviv_gpu *gpu = dev_get_drvdata(dev); | |
1729 | int ret; | |
1730 | ||
1731 | ret = etnaviv_gpu_clk_enable(gpu); | |
1732 | if (ret) | |
1733 | return ret; | |
1734 | ||
1735 | /* Re-initialise the basic hardware state */ | |
1736 | if (gpu->drm && gpu->buffer) { | |
1737 | ret = etnaviv_gpu_hw_resume(gpu); | |
1738 | if (ret) { | |
1739 | etnaviv_gpu_clk_disable(gpu); | |
1740 | return ret; | |
1741 | } | |
1742 | } | |
1743 | ||
1744 | return 0; | |
1745 | } | |
1746 | #endif | |
1747 | ||
1748 | static const struct dev_pm_ops etnaviv_gpu_pm_ops = { | |
1749 | SET_RUNTIME_PM_OPS(etnaviv_gpu_rpm_suspend, etnaviv_gpu_rpm_resume, | |
1750 | NULL) | |
1751 | }; | |
1752 | ||
1753 | struct platform_driver etnaviv_gpu_driver = { | |
1754 | .driver = { | |
1755 | .name = "etnaviv-gpu", | |
1756 | .owner = THIS_MODULE, | |
1757 | .pm = &etnaviv_gpu_pm_ops, | |
1758 | .of_match_table = etnaviv_gpu_match, | |
1759 | }, | |
1760 | .probe = etnaviv_gpu_platform_probe, | |
1761 | .remove = etnaviv_gpu_platform_remove, | |
1762 | .id_table = gpu_ids, | |
1763 | }; |