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drm/etnaviv: better track GPU state
[linux-2.6-block.git] / drivers / gpu / drm / etnaviv / etnaviv_gpu.c
CommitLineData
f6ffbd4f 1// SPDX-License-Identifier: GPL-2.0
a8c21a54 2/*
f6ffbd4f 3 * Copyright (C) 2015-2018 Etnaviv Project
a8c21a54
T		 4 */
5
f9d255f4 6#include <linux/clk.h>
a8c21a54 7#include <linux/component.h>
6eae41fe 8#include <linux/delay.h>
f54d1867 9#include <linux/dma-fence.h>
6eae41fe 10#include <linux/dma-mapping.h>
2e737e52 11#include <linux/module.h>
a8c21a54 12#include <linux/of_device.h>
2e737e52
LS		 13#include <linux/platform_device.h>
14#include <linux/pm_runtime.h>
f9d255f4 15#include <linux/regulator/consumer.h>
bcdfb5e5 16#include <linux/thermal.h>
ea1f5729
LS		 17
18#include "etnaviv_cmdbuf.h"
a8c21a54
T		 19#include "etnaviv_dump.h"
20#include "etnaviv_gpu.h"
21#include "etnaviv_gem.h"
22#include "etnaviv_mmu.h"
357713ce 23#include "etnaviv_perfmon.h"
e93b6dee 24#include "etnaviv_sched.h"
a8c21a54
T		 25#include "common.xml.h"
26#include "state.xml.h"
27#include "state_hi.xml.h"
28#include "cmdstream.xml.h"
29
30static const struct platform_device_id gpu_ids[] = {
31 { .name = "etnaviv-gpu,2d" },
32 { },
33};
34
a8c21a54
T		 35/*
36 * Driver functions:
37 */
38
39int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value)
40{
088880dd
LS		 41 struct etnaviv_drm_private *priv = gpu->drm->dev_private;
42
a8c21a54
T		 43 switch (param) {
44 case ETNAVIV_PARAM_GPU_MODEL:
45 *value = gpu->identity.model;
46 break;
47
48 case ETNAVIV_PARAM_GPU_REVISION:
49 *value = gpu->identity.revision;
50 break;
51
52 case ETNAVIV_PARAM_GPU_FEATURES_0:
53 *value = gpu->identity.features;
54 break;
55
56 case ETNAVIV_PARAM_GPU_FEATURES_1:
57 *value = gpu->identity.minor_features0;
58 break;
59
60 case ETNAVIV_PARAM_GPU_FEATURES_2:
61 *value = gpu->identity.minor_features1;
62 break;
63
64 case ETNAVIV_PARAM_GPU_FEATURES_3:
65 *value = gpu->identity.minor_features2;
66 break;
67
68 case ETNAVIV_PARAM_GPU_FEATURES_4:
69 *value = gpu->identity.minor_features3;
70 break;
71
602eb489
RK		 72 case ETNAVIV_PARAM_GPU_FEATURES_5:
73 *value = gpu->identity.minor_features4;
74 break;
75
76 case ETNAVIV_PARAM_GPU_FEATURES_6:
77 *value = gpu->identity.minor_features5;
78 break;
79
0538aaf9
LS		 80 case ETNAVIV_PARAM_GPU_FEATURES_7:
81 *value = gpu->identity.minor_features6;
82 break;
83
84 case ETNAVIV_PARAM_GPU_FEATURES_8:
85 *value = gpu->identity.minor_features7;
86 break;
87
88 case ETNAVIV_PARAM_GPU_FEATURES_9:
89 *value = gpu->identity.minor_features8;
90 break;
91
92 case ETNAVIV_PARAM_GPU_FEATURES_10:
93 *value = gpu->identity.minor_features9;
94 break;
95
96 case ETNAVIV_PARAM_GPU_FEATURES_11:
97 *value = gpu->identity.minor_features10;
98 break;
99
100 case ETNAVIV_PARAM_GPU_FEATURES_12:
101 *value = gpu->identity.minor_features11;
102 break;
103
a8c21a54
T		 104 case ETNAVIV_PARAM_GPU_STREAM_COUNT:
105 *value = gpu->identity.stream_count;
106 break;
107
108 case ETNAVIV_PARAM_GPU_REGISTER_MAX:
109 *value = gpu->identity.register_max;
110 break;
111
112 case ETNAVIV_PARAM_GPU_THREAD_COUNT:
113 *value = gpu->identity.thread_count;
114 break;
115
116 case ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE:
117 *value = gpu->identity.vertex_cache_size;
118 break;
119
120 case ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT:
121 *value = gpu->identity.shader_core_count;
122 break;
123
124 case ETNAVIV_PARAM_GPU_PIXEL_PIPES:
125 *value = gpu->identity.pixel_pipes;
126 break;
127
128 case ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE:
129 *value = gpu->identity.vertex_output_buffer_size;
130 break;
131
132 case ETNAVIV_PARAM_GPU_BUFFER_SIZE:
133 *value = gpu->identity.buffer_size;
134 break;
135
136 case ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT:
137 *value = gpu->identity.instruction_count;
138 break;
139
140 case ETNAVIV_PARAM_GPU_NUM_CONSTANTS:
141 *value = gpu->identity.num_constants;
142 break;
143
602eb489
RK		 144 case ETNAVIV_PARAM_GPU_NUM_VARYINGS:
145 *value = gpu->identity.varyings_count;
146 break;
147
088880dd
LS		 148 case ETNAVIV_PARAM_SOFTPIN_START_ADDR:
149 if (priv->mmu_global->version == ETNAVIV_IOMMU_V2)
150 *value = ETNAVIV_SOFTPIN_START_ADDRESS;
151 else
152 *value = ~0ULL;
153 break;
154
1ff79a4a
CG		 155 case ETNAVIV_PARAM_GPU_PRODUCT_ID:
156 *value = gpu->identity.product_id;
157 break;
158
159 case ETNAVIV_PARAM_GPU_CUSTOMER_ID:
160 *value = gpu->identity.customer_id;
161 break;
162
163 case ETNAVIV_PARAM_GPU_ECO_ID:
164 *value = gpu->identity.eco_id;
165 break;
166
a8c21a54
T		 167 default:
168 DBG("%s: invalid param: %u", dev_name(gpu->dev), param);
169 return -EINVAL;
170 }
171
172 return 0;
173}
174
472f79dc
RK		 175
176#define etnaviv_is_model_rev(gpu, mod, rev) \
177 ((gpu)->identity.model == chipModel_##mod && \
178 (gpu)->identity.revision == rev)
52f36ba1
RK		 179#define etnaviv_field(val, field) \
180 (((val) & field##__MASK) >> field##__SHIFT)
181
a8c21a54
T		 182static void etnaviv_hw_specs(struct etnaviv_gpu *gpu)
183{
184 if (gpu->identity.minor_features0 &
185 chipMinorFeatures0_MORE_MINOR_FEATURES) {
602eb489
RK		 186 u32 specs[4];
187 unsigned int streams;
a8c21a54
T		 188
189 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS);
190 specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2);
602eb489
RK		 191 specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3);
192 specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4);
a8c21a54 193
52f36ba1
RK		 194 gpu->identity.stream_count = etnaviv_field(specs[0],
195 VIVS_HI_CHIP_SPECS_STREAM_COUNT);
196 gpu->identity.register_max = etnaviv_field(specs[0],
197 VIVS_HI_CHIP_SPECS_REGISTER_MAX);
198 gpu->identity.thread_count = etnaviv_field(specs[0],
199 VIVS_HI_CHIP_SPECS_THREAD_COUNT);
200 gpu->identity.vertex_cache_size = etnaviv_field(specs[0],
201 VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE);
202 gpu->identity.shader_core_count = etnaviv_field(specs[0],
203 VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT);
204 gpu->identity.pixel_pipes = etnaviv_field(specs[0],
205 VIVS_HI_CHIP_SPECS_PIXEL_PIPES);
a8c21a54 206 gpu->identity.vertex_output_buffer_size =
52f36ba1
RK		 207 etnaviv_field(specs[0],
208 VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE);
209
210 gpu->identity.buffer_size = etnaviv_field(specs[1],
211 VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE);
212 gpu->identity.instruction_count = etnaviv_field(specs[1],
213 VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT);
214 gpu->identity.num_constants = etnaviv_field(specs[1],
215 VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS);
602eb489
RK		 216
217 gpu->identity.varyings_count = etnaviv_field(specs[2],
218 VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT);
219
220 /* This overrides the value from older register if non-zero */
221 streams = etnaviv_field(specs[3],
222 VIVS_HI_CHIP_SPECS_4_STREAM_COUNT);
223 if (streams)
224 gpu->identity.stream_count = streams;
a8c21a54
T		 225 }
226
227 /* Fill in the stream count if not specified */
228 if (gpu->identity.stream_count == 0) {
229 if (gpu->identity.model >= 0x1000)
230 gpu->identity.stream_count = 4;
231 else
232 gpu->identity.stream_count = 1;
233 }
234
235 /* Convert the register max value */
236 if (gpu->identity.register_max)
237 gpu->identity.register_max = 1 << gpu->identity.register_max;
507f8991 238 else if (gpu->identity.model == chipModel_GC400)
a8c21a54
T		 239 gpu->identity.register_max = 32;
240 else
241 gpu->identity.register_max = 64;
242
243 /* Convert thread count */
244 if (gpu->identity.thread_count)
245 gpu->identity.thread_count = 1 << gpu->identity.thread_count;
507f8991 246 else if (gpu->identity.model == chipModel_GC400)
a8c21a54 247 gpu->identity.thread_count = 64;
507f8991
RK		 248 else if (gpu->identity.model == chipModel_GC500 ||
249 gpu->identity.model == chipModel_GC530)
a8c21a54
T		 250 gpu->identity.thread_count = 128;
251 else
252 gpu->identity.thread_count = 256;
253
254 if (gpu->identity.vertex_cache_size == 0)
255 gpu->identity.vertex_cache_size = 8;
256
257 if (gpu->identity.shader_core_count == 0) {
258 if (gpu->identity.model >= 0x1000)
259 gpu->identity.shader_core_count = 2;
260 else
261 gpu->identity.shader_core_count = 1;
262 }
263
264 if (gpu->identity.pixel_pipes == 0)
265 gpu->identity.pixel_pipes = 1;
266
267 /* Convert virtex buffer size */
268 if (gpu->identity.vertex_output_buffer_size) {
269 gpu->identity.vertex_output_buffer_size =
270 1 << gpu->identity.vertex_output_buffer_size;
507f8991 271 } else if (gpu->identity.model == chipModel_GC400) {
a8c21a54
T		 272 if (gpu->identity.revision < 0x4000)
273 gpu->identity.vertex_output_buffer_size = 512;
274 else if (gpu->identity.revision < 0x4200)
275 gpu->identity.vertex_output_buffer_size = 256;
276 else
277 gpu->identity.vertex_output_buffer_size = 128;
278 } else {
279 gpu->identity.vertex_output_buffer_size = 512;
280 }
281
282 switch (gpu->identity.instruction_count) {
283 case 0:
472f79dc 284 if (etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
507f8991 285 gpu->identity.model == chipModel_GC880)
a8c21a54
T		 286 gpu->identity.instruction_count = 512;
287 else
288 gpu->identity.instruction_count = 256;
289 break;
290
291 case 1:
292 gpu->identity.instruction_count = 1024;
293 break;
294
295 case 2:
296 gpu->identity.instruction_count = 2048;
297 break;
298
299 default:
300 gpu->identity.instruction_count = 256;
301 break;
302 }
303
304 if (gpu->identity.num_constants == 0)
305 gpu->identity.num_constants = 168;
602eb489
RK		 306
307 if (gpu->identity.varyings_count == 0) {
308 if (gpu->identity.minor_features1 & chipMinorFeatures1_HALTI0)
309 gpu->identity.varyings_count = 12;
310 else
311 gpu->identity.varyings_count = 8;
312 }
313
314 /*
315 * For some cores, two varyings are consumed for position, so the
316 * maximum varying count needs to be reduced by one.
317 */
318 if (etnaviv_is_model_rev(gpu, GC5000, 0x5434) ||
319 etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
320 etnaviv_is_model_rev(gpu, GC4000, 0x5245) ||
321 etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
322 etnaviv_is_model_rev(gpu, GC3000, 0x5435) ||
323 etnaviv_is_model_rev(gpu, GC2200, 0x5244) ||
324 etnaviv_is_model_rev(gpu, GC2100, 0x5108) ||
325 etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
326 etnaviv_is_model_rev(gpu, GC1500, 0x5246) ||
327 etnaviv_is_model_rev(gpu, GC880, 0x5107) ||
328 etnaviv_is_model_rev(gpu, GC880, 0x5106))
329 gpu->identity.varyings_count -= 1;
a8c21a54
T		 330}
331
332static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
333{
334 u32 chipIdentity;
335
336 chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY);
337
338 /* Special case for older graphic cores. */
52f36ba1 339 if (etnaviv_field(chipIdentity, VIVS_HI_CHIP_IDENTITY_FAMILY) == 0x01) {
507f8991 340 gpu->identity.model = chipModel_GC500;
52f36ba1
RK		 341 gpu->identity.revision = etnaviv_field(chipIdentity,
342 VIVS_HI_CHIP_IDENTITY_REVISION);
a8c21a54 343 } else {
815e45bb 344 u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE);
a8c21a54
T		 345
346 gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL);
347 gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV);
815e45bb 348 gpu->identity.customer_id = gpu_read(gpu, VIVS_HI_CHIP_CUSTOMER_ID);
2c5bf028
CG		 349
350 /*
351 * Reading these two registers on GC600 rev 0x19 result in a
352 * unhandled fault: external abort on non-linefetch
353 */
354 if (!etnaviv_is_model_rev(gpu, GC600, 0x19)) {
355 gpu->identity.product_id = gpu_read(gpu, VIVS_HI_CHIP_PRODUCT_ID);
356 gpu->identity.eco_id = gpu_read(gpu, VIVS_HI_CHIP_ECO_ID);
357 }
a8c21a54
T		 358
359 /*
360 * !!!! HACK ALERT !!!!
361 * Because people change device IDs without letting software
362 * know about it - here is the hack to make it all look the
363 * same. Only for GC400 family.
364 */
365 if ((gpu->identity.model & 0xff00) == 0x0400 &&
507f8991 366 gpu->identity.model != chipModel_GC420) {
a8c21a54
T		 367 gpu->identity.model = gpu->identity.model & 0x0400;
368 }
369
370 /* Another special case */
472f79dc 371 if (etnaviv_is_model_rev(gpu, GC300, 0x2201)) {
a8c21a54
T		 372 u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME);
373
374 if (chipDate == 0x20080814 && chipTime == 0x12051100) {
375 /*
376 * This IP has an ECO; put the correct
377 * revision in it.
378 */
379 gpu->identity.revision = 0x1051;
380 }
381 }
12ff4bde
LS		 382
383 /*
384 * NXP likes to call the GPU on the i.MX6QP GC2000+, but in
385 * reality it's just a re-branded GC3000. We can identify this
386 * core by the upper half of the revision register being all 1.
387 * Fix model/rev here, so all other places can refer to this
388 * core by its real identity.
389 */
390 if (etnaviv_is_model_rev(gpu, GC2000, 0xffff5450)) {
391 gpu->identity.model = chipModel_GC3000;
392 gpu->identity.revision &= 0xffff;
393 }
815e45bb
CG		 394
395 if (etnaviv_is_model_rev(gpu, GC1000, 0x5037) && (chipDate == 0x20120617))
396 gpu->identity.eco_id = 1;
397
398 if (etnaviv_is_model_rev(gpu, GC320, 0x5303) && (chipDate == 0x20140511))
399 gpu->identity.eco_id = 1;
a8c21a54
T		 400 }
401
402 dev_info(gpu->dev, "model: GC%x, revision: %x\n",
403 gpu->identity.model, gpu->identity.revision);
404
2b76f5be 405 gpu->idle_mask = ~VIVS_HI_IDLE_STATE_AXI_LP;
681c19c8
LS		 406 /*
407 * If there is a match in the HWDB, we aren't interested in the
408 * remaining register values, as they might be wrong.
409 */
410 if (etnaviv_fill_identity_from_hwdb(gpu))
411 return;
412
a8c21a54
T		 413 gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE);
414
415 /* Disable fast clear on GC700. */
507f8991 416 if (gpu->identity.model == chipModel_GC700)
a8c21a54
T		 417 gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
418
cc7d3fb4
DB		 419 /* These models/revisions don't have the 2D pipe bit */
420 if ((gpu->identity.model == chipModel_GC500 &&
421 gpu->identity.revision <= 2) ||
422 gpu->identity.model == chipModel_GC300)
423 gpu->identity.features |= chipFeatures_PIPE_2D;
424
507f8991
RK		 425 if ((gpu->identity.model == chipModel_GC500 &&
426 gpu->identity.revision < 2) ||
427 (gpu->identity.model == chipModel_GC300 &&
428 gpu->identity.revision < 0x2000)) {
a8c21a54
T		 429
430 /*
431 * GC500 rev 1.x and GC300 rev < 2.0 doesn't have these
432 * registers.
433 */
434 gpu->identity.minor_features0 = 0;
435 gpu->identity.minor_features1 = 0;
436 gpu->identity.minor_features2 = 0;
437 gpu->identity.minor_features3 = 0;
602eb489
RK		 438 gpu->identity.minor_features4 = 0;
439 gpu->identity.minor_features5 = 0;
a8c21a54
T		 440 } else
441 gpu->identity.minor_features0 =
442 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0);
443
444 if (gpu->identity.minor_features0 &
445 chipMinorFeatures0_MORE_MINOR_FEATURES) {
446 gpu->identity.minor_features1 =
447 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1);
448 gpu->identity.minor_features2 =
449 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2);
450 gpu->identity.minor_features3 =
451 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3);
602eb489
RK		 452 gpu->identity.minor_features4 =
453 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4);
454 gpu->identity.minor_features5 =
455 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5);
a8c21a54
T		 456 }
457
cc7d3fb4
DB		 458 /* GC600/300 idle register reports zero bits where modules aren't present */
459 if (gpu->identity.model == chipModel_GC600 ||
460 gpu->identity.model == chipModel_GC300)
a8c21a54
T		 461 gpu->idle_mask = VIVS_HI_IDLE_STATE_TX |
462 VIVS_HI_IDLE_STATE_RA |
463 VIVS_HI_IDLE_STATE_SE |
464 VIVS_HI_IDLE_STATE_PA |
465 VIVS_HI_IDLE_STATE_SH |
466 VIVS_HI_IDLE_STATE_PE |
467 VIVS_HI_IDLE_STATE_DE |
468 VIVS_HI_IDLE_STATE_FE;
a8c21a54
T		 469
470 etnaviv_hw_specs(gpu);
471}
472
473static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock)
474{
475 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock |
476 VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD);
477 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock);
478}
479
bcdfb5e5
RK		 480static void etnaviv_gpu_update_clock(struct etnaviv_gpu *gpu)
481{
d79fd1cc
LS		 482 if (gpu->identity.minor_features2 &
483 chipMinorFeatures2_DYNAMIC_FREQUENCY_SCALING) {
484 clk_set_rate(gpu->clk_core,
485 gpu->base_rate_core >> gpu->freq_scale);
486 clk_set_rate(gpu->clk_shader,
487 gpu->base_rate_shader >> gpu->freq_scale);
488 } else {
489 unsigned int fscale = 1 << (6 - gpu->freq_scale);
6eb3ecc3 490 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
bcdfb5e5 491
6eb3ecc3
LS		 492 clock &= ~VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK;
493 clock |= VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
d79fd1cc
LS		 494 etnaviv_gpu_load_clock(gpu, clock);
495 }
295b6c02
LS		 496
497 /*
498 * Choose number of wait cycles to target a ~30us (1/32768) max latency
499 * until new work is picked up by the FE when it polls in the idle loop.
500 * If the GPU base frequency is unknown use 200 wait cycles.
501 */
502 gpu->fe_waitcycles = clamp(gpu->base_rate_core >> (15 - gpu->freq_scale),
503 200UL, 0xffffUL);
bcdfb5e5
RK		 504}
505
a8c21a54
T		 506static int etnaviv_hw_reset(struct etnaviv_gpu *gpu)
507{
508 u32 control, idle;
509 unsigned long timeout;
510 bool failed = true;
511
a8c21a54
T		 512 /* We hope that the GPU resets in under one second */
513 timeout = jiffies + msecs_to_jiffies(1000);
514
515 while (time_is_after_jiffies(timeout)) {
a8c21a54 516 /* enable clock */
6eb3ecc3
LS		 517 unsigned int fscale = 1 << (6 - gpu->freq_scale);
518 control = VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
519 etnaviv_gpu_load_clock(gpu, control);
a8c21a54
T		 520
521 /* isolate the GPU. */
522 control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
523 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
524
c997c3df
LS		 525 if (gpu->sec_mode == ETNA_SEC_KERNEL) {
526 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL,
527 VIVS_MMUv2_AHB_CONTROL_RESET);
528 } else {
529 /* set soft reset. */
530 control |= VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
531 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
532 }
a8c21a54
T		 533
534 /* wait for reset. */
40462179 535 usleep_range(10, 20);
a8c21a54
T		 536
537 /* reset soft reset bit. */
538 control &= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
539 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
540
541 /* reset GPU isolation. */
542 control &= ~VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
543 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
544
545 /* read idle register. */
546 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
547
ea4ed4a5 548 /* try resetting again if FE is not idle */
a8c21a54
T		 549 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) {
550 dev_dbg(gpu->dev, "FE is not idle\n");
551 continue;
552 }
553
554 /* read reset register. */
555 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
556
557 /* is the GPU idle? */
558 if (((control & VIVS_HI_CLOCK_CONTROL_IDLE_3D) == 0) ||
559 ((control & VIVS_HI_CLOCK_CONTROL_IDLE_2D) == 0)) {
560 dev_dbg(gpu->dev, "GPU is not idle\n");
561 continue;
562 }
563
6eb3ecc3
LS		 564 /* disable debug registers, as they are not normally needed */
565 control |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
566 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
567
a8c21a54
T		 568 failed = false;
569 break;
570 }
571
572 if (failed) {
573 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
574 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
575
576 dev_err(gpu->dev, "GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidle\n",
577 idle & VIVS_HI_IDLE_STATE_FE ? "" : "not ",
578 control & VIVS_HI_CLOCK_CONTROL_IDLE_3D ? "" : "not ",
579 control & VIVS_HI_CLOCK_CONTROL_IDLE_2D ? "" : "not ");
580
581 return -EBUSY;
582 }
583
584 /* We rely on the GPU running, so program the clock */
bcdfb5e5 585 etnaviv_gpu_update_clock(gpu);
a8c21a54 586
647d817d 587 gpu->state = ETNA_GPU_STATE_RESET;
725cbc78 588 gpu->exec_state = -1;
f978a530
LS		 589 if (gpu->mmu_context)
590 etnaviv_iommu_context_put(gpu->mmu_context);
725cbc78 591 gpu->mmu_context = NULL;
23e0f5a5 592
a8c21a54
T		 593 return 0;
594}
595
7d0c6e71
RK		 596static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu)
597{
598 u32 pmc, ppc;
599
600 /* enable clock gating */
61a6920b 601 ppc = gpu_read_power(gpu, VIVS_PM_POWER_CONTROLS);
7d0c6e71
RK		 602 ppc |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
603
604 /* Disable stall module clock gating for 4.3.0.1 and 4.3.0.2 revs */
605 if (gpu->identity.revision == 0x4301 ||
606 gpu->identity.revision == 0x4302)
607 ppc |= VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING;
608
61a6920b 609 gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, ppc);
7d0c6e71 610
61a6920b 611 pmc = gpu_read_power(gpu, VIVS_PM_MODULE_CONTROLS);
7d0c6e71 612
7cef6004 613 /* Disable PA clock gating for GC400+ without bugfix except for GC420 */
7d0c6e71 614 if (gpu->identity.model >= chipModel_GC400 &&
7cef6004
LS		 615 gpu->identity.model != chipModel_GC420 &&
616 !(gpu->identity.minor_features3 & chipMinorFeatures3_BUG_FIXES12))
7d0c6e71
RK		 617 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA;
618
619 /*
620 * Disable PE clock gating on revs < 5.0.0.0 when HZ is
621 * present without a bug fix.
622 */
623 if (gpu->identity.revision < 0x5000 &&
624 gpu->identity.minor_features0 & chipMinorFeatures0_HZ &&
625 !(gpu->identity.minor_features1 &
626 chipMinorFeatures1_DISABLE_PE_GATING))
627 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE;
628
629 if (gpu->identity.revision < 0x5422)
630 pmc |= BIT(15); /* Unknown bit */
631
7cef6004
LS		 632 /* Disable TX clock gating on affected core revisions. */
633 if (etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
4bce2442
MF		 634 etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
635 etnaviv_is_model_rev(gpu, GC2000, 0x6202) ||
636 etnaviv_is_model_rev(gpu, GC2000, 0x6203))
7cef6004
LS		 637 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX;
638
4bce2442 639 /* Disable SE and RA clock gating on affected core revisions. */
432f51e7
MW		 640 if (etnaviv_is_model_rev(gpu, GC7000, 0x6202))
641 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SE |
4bce2442 642 VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA;
432f51e7 643
7d0c6e71
RK		 644 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ;
645 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ;
646
61a6920b 647 gpu_write_power(gpu, VIVS_PM_MODULE_CONTROLS, pmc);
7d0c6e71
RK		 648}
649
229855b6
LS		 650void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch)
651{
652 gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS, address);
653 gpu_write(gpu, VIVS_FE_COMMAND_CONTROL,
654 VIVS_FE_COMMAND_CONTROL_ENABLE |
655 VIVS_FE_COMMAND_CONTROL_PREFETCH(prefetch));
c997c3df
LS		 656
657 if (gpu->sec_mode == ETNA_SEC_KERNEL) {
658 gpu_write(gpu, VIVS_MMUv2_SEC_COMMAND_CONTROL,
659 VIVS_MMUv2_SEC_COMMAND_CONTROL_ENABLE |
660 VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH(prefetch));
661 }
229855b6
LS		 662}
663
d6408538
LS		 664static void etnaviv_gpu_start_fe_idleloop(struct etnaviv_gpu *gpu,
665 struct etnaviv_iommu_context *context)
d80d842a 666{
d80d842a 667 u16 prefetch;
d6408538 668 u32 address;
d80d842a 669
647d817d
LS		 670 WARN_ON(gpu->state != ETNA_GPU_STATE_INITIALIZED);
671
d80d842a 672 /* setup the MMU */
d6408538 673 etnaviv_iommu_restore(gpu, context);
d80d842a
LS		 674
675 /* Start command processor */
676 prefetch = etnaviv_buffer_init(gpu);
d6408538
LS		 677 address = etnaviv_cmdbuf_get_va(&gpu->buffer,
678 &gpu->mmu_context->cmdbuf_mapping);
d80d842a
LS		 679
680 etnaviv_gpu_start_fe(gpu, address, prefetch);
647d817d
LS		 681
682 gpu->state = ETNA_GPU_STATE_RUNNING;
d80d842a
LS		 683}
684
e17a0ded
WL		 685static void etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu)
686{
687 /*
688 * Base value for VIVS_PM_PULSE_EATER register on models where it
689 * cannot be read, extracted from vivante kernel driver.
690 */
691 u32 pulse_eater = 0x01590880;
692
693 if (etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
694 etnaviv_is_model_rev(gpu, GC4000, 0x5222)) {
695 pulse_eater |= BIT(23);
696
697 }
698
699 if (etnaviv_is_model_rev(gpu, GC1000, 0x5039) ||
700 etnaviv_is_model_rev(gpu, GC1000, 0x5040)) {
701 pulse_eater &= ~BIT(16);
702 pulse_eater |= BIT(17);
703 }
704
705 if ((gpu->identity.revision > 0x5420) &&
706 (gpu->identity.features & chipFeatures_PIPE_3D))
707 {
708 /* Performance fix: disable internal DFS */
61a6920b 709 pulse_eater = gpu_read_power(gpu, VIVS_PM_PULSE_EATER);
e17a0ded
WL		 710 pulse_eater |= BIT(18);
711 }
712
61a6920b 713 gpu_write_power(gpu, VIVS_PM_PULSE_EATER, pulse_eater);
e17a0ded
WL		 714}
715
a8c21a54
T		 716static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu)
717{
647d817d
LS		 718 WARN_ON(!(gpu->state == ETNA_GPU_STATE_IDENTIFIED ||
719 gpu->state == ETNA_GPU_STATE_RESET));
720
472f79dc
RK		 721 if ((etnaviv_is_model_rev(gpu, GC320, 0x5007) ||
722 etnaviv_is_model_rev(gpu, GC320, 0x5220)) &&
723 gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) {
a8c21a54
T		 724 u32 mc_memory_debug;
725
726 mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff;
727
728 if (gpu->identity.revision == 0x5007)
729 mc_memory_debug |= 0x0c;
730 else
731 mc_memory_debug |= 0x08;
732
733 gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug);
734 }
735
7d0c6e71
RK		 736 /* enable module-level clock gating */
737 etnaviv_gpu_enable_mlcg(gpu);
738
a8c21a54
T		 739 /*
740 * Update GPU AXI cache atttribute to "cacheable, no allocate".
741 * This is necessary to prevent the iMX6 SoC locking up.
742 */
743 gpu_write(gpu, VIVS_HI_AXI_CONFIG,
744 VIVS_HI_AXI_CONFIG_AWCACHE(2) |
745 VIVS_HI_AXI_CONFIG_ARCACHE(2));
746
747 /* GC2000 rev 5108 needs a special bus config */
472f79dc 748 if (etnaviv_is_model_rev(gpu, GC2000, 0x5108)) {
a8c21a54
T		 749 u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG);
750 bus_config &= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK |
751 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK);
752 bus_config |= VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(1) |
753 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(0);
754 gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config);
755 }
756
c997c3df
LS		 757 if (gpu->sec_mode == ETNA_SEC_KERNEL) {
758 u32 val = gpu_read(gpu, VIVS_MMUv2_AHB_CONTROL);
759 val |= VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS;
760 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, val);
761 }
762
e17a0ded
WL		 763 /* setup the pulse eater */
764 etnaviv_gpu_setup_pulse_eater(gpu);
765
a8c21a54 766 gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U);
647d817d
LS		 767
768 gpu->state = ETNA_GPU_STATE_INITIALIZED;
a8c21a54
T		 769}
770
771int etnaviv_gpu_init(struct etnaviv_gpu *gpu)
772{
bffe5db8 773 struct etnaviv_drm_private *priv = gpu->drm->dev_private;
4bfdd2aa 774 dma_addr_t cmdbuf_paddr;
a8c21a54 775 int ret, i;
a8c21a54
T		 776
777 ret = pm_runtime_get_sync(gpu->dev);
1409df04
LS		 778 if (ret < 0) {
779 dev_err(gpu->dev, "Failed to enable GPU power domain\n");
c5d5a32e 780 goto pm_put;
1409df04 781 }
a8c21a54
T		 782
783 etnaviv_hw_identify(gpu);
784
785 if (gpu->identity.model == 0) {
786 dev_err(gpu->dev, "Unknown GPU model\n");
f6427760
RK		 787 ret = -ENXIO;
788 goto fail;
a8c21a54
T		 789 }
790
d801e6f4
TV		 791 if (gpu->identity.nn_core_count > 0)
792 dev_warn(gpu->dev, "etnaviv has been instantiated on a NPU, "
793 "for which the UAPI is still experimental\n");
794
b98c6688
RK		 795 /* Exclude VG cores with FE2.0 */
796 if (gpu->identity.features & chipFeatures_PIPE_VG &&
797 gpu->identity.features & chipFeatures_FE20) {
798 dev_info(gpu->dev, "Ignoring GPU with VG and FE2.0\n");
799 ret = -ENXIO;
800 goto fail;
801 }
802
c997c3df
LS		 803 /*
804 * On cores with security features supported, we claim control over the
805 * security states.
806 */
807 if ((gpu->identity.minor_features7 & chipMinorFeatures7_BIT_SECURITY) &&
808 (gpu->identity.minor_features10 & chipMinorFeatures10_SECURITY_AHB))
809 gpu->sec_mode = ETNA_SEC_KERNEL;
810
647d817d
LS		 811 gpu->state = ETNA_GPU_STATE_IDENTIFIED;
812
a8c21a54 813 ret = etnaviv_hw_reset(gpu);
1409df04
LS		 814 if (ret) {
815 dev_err(gpu->dev, "GPU reset failed\n");
a8c21a54 816 goto fail;
1409df04 817 }
a8c21a54 818
27b67278
LS		 819 ret = etnaviv_iommu_global_init(gpu);
820 if (ret)
a8c21a54 821 goto fail;
27b67278 822
b72af445
LS		 823 /*
824 * If the GPU is part of a system with DMA addressing limitations,
825 * request pages for our SHM backend buffers from the DMA32 zone to
826 * hopefully avoid performance killing SWIOTLB bounce buffering.
827 */
828 if (dma_addressing_limited(gpu->dev))
829 priv->shm_gfp_mask |= GFP_DMA32;
830
a8c21a54 831 /* Create buffer: */
bffe5db8 832 ret = etnaviv_cmdbuf_init(priv->cmdbuf_suballoc, &gpu->buffer,
2f9225db
LS		 833 PAGE_SIZE);
834 if (ret) {
a8c21a54 835 dev_err(gpu->dev, "could not create command buffer\n");
17e4660a 836 goto fail;
a8c21a54
T		 837 }
838
4bfdd2aa
LS		 839 /*
840 * Set the GPU linear window to cover the cmdbuf region, as the GPU
841 * won't be able to start execution otherwise. The alignment to 128M is
842 * chosen arbitrarily but helps in debugging, as the MMU offset
843 * calculations are much more straight forward this way.
844 *
845 * On MC1.0 cores the linear window offset is ignored by the TS engine,
846 * leading to inconsistent memory views. Avoid using the offset on those
847 * cores if possible, otherwise disable the TS feature.
848 */
849 cmdbuf_paddr = ALIGN_DOWN(etnaviv_cmdbuf_get_pa(&gpu->buffer), SZ_128M);
850
851 if (!(gpu->identity.features & chipFeatures_PIPE_3D) ||
852 (gpu->identity.minor_features0 & chipMinorFeatures0_MC20)) {
853 if (cmdbuf_paddr >= SZ_2G)
854 priv->mmu_global->memory_base = SZ_2G;
855 else
856 priv->mmu_global->memory_base = cmdbuf_paddr;
857 } else if (cmdbuf_paddr + SZ_128M >= SZ_2G) {
858 dev_info(gpu->dev,
859 "Need to move linear window on MC1.0, disabling TS\n");
860 gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
861 priv->mmu_global->memory_base = SZ_2G;
862 }
863
a8c21a54
T		 864 /* Setup event management */
865 spin_lock_init(&gpu->event_spinlock);
866 init_completion(&gpu->event_free);
355502e0
CG		 867 bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS);
868 for (i = 0; i < ARRAY_SIZE(gpu->event); i++)
a8c21a54 869 complete(&gpu->event_free);
a8c21a54
T		 870
871 /* Now program the hardware */
872 mutex_lock(&gpu->lock);
873 etnaviv_gpu_hw_init(gpu);
874 mutex_unlock(&gpu->lock);
875
876 pm_runtime_mark_last_busy(gpu->dev);
877 pm_runtime_put_autosuspend(gpu->dev);
878
db41fe7d
LS		 879 gpu->initialized = true;
880
a8c21a54
T		 881 return 0;
882
a8c21a54
T		 883fail:
884 pm_runtime_mark_last_busy(gpu->dev);
c5d5a32e 885pm_put:
a8c21a54
T		 886 pm_runtime_put_autosuspend(gpu->dev);
887
888 return ret;
889}
890
891#ifdef CONFIG_DEBUG_FS
892struct dma_debug {
893 u32 address[2];
894 u32 state[2];
895};
896
897static void verify_dma(struct etnaviv_gpu *gpu, struct dma_debug *debug)
898{
899 u32 i;
900
901 debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
902 debug->state[0] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
903
904 for (i = 0; i < 500; i++) {
905 debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
906 debug->state[1] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
907
908 if (debug->address[0] != debug->address[1])
909 break;
910
911 if (debug->state[0] != debug->state[1])
912 break;
913 }
914}
915
916int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m)
917{
918 struct dma_debug debug;
919 u32 dma_lo, dma_hi, axi, idle;
920 int ret;
921
922 seq_printf(m, "%s Status:\n", dev_name(gpu->dev));
923
924 ret = pm_runtime_get_sync(gpu->dev);
925 if (ret < 0)
c5d5a32e 926 goto pm_put;
a8c21a54
T		 927
928 dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW);
929 dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH);
930 axi = gpu_read(gpu, VIVS_HI_AXI_STATUS);
931 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
932
933 verify_dma(gpu, &debug);
934
00080663
CG		 935 seq_puts(m, "\tidentity\n");
936 seq_printf(m, "\t model: 0x%x\n", gpu->identity.model);
937 seq_printf(m, "\t revision: 0x%x\n", gpu->identity.revision);
938 seq_printf(m, "\t product_id: 0x%x\n", gpu->identity.product_id);
939 seq_printf(m, "\t customer_id: 0x%x\n", gpu->identity.customer_id);
940 seq_printf(m, "\t eco_id: 0x%x\n", gpu->identity.eco_id);
941
a8c21a54 942 seq_puts(m, "\tfeatures\n");
3d9fc642
LS		 943 seq_printf(m, "\t major_features: 0x%08x\n",
944 gpu->identity.features);
a8c21a54
T		 945 seq_printf(m, "\t minor_features0: 0x%08x\n",
946 gpu->identity.minor_features0);
947 seq_printf(m, "\t minor_features1: 0x%08x\n",
948 gpu->identity.minor_features1);
949 seq_printf(m, "\t minor_features2: 0x%08x\n",
950 gpu->identity.minor_features2);
951 seq_printf(m, "\t minor_features3: 0x%08x\n",
952 gpu->identity.minor_features3);
602eb489
RK		 953 seq_printf(m, "\t minor_features4: 0x%08x\n",
954 gpu->identity.minor_features4);
955 seq_printf(m, "\t minor_features5: 0x%08x\n",
956 gpu->identity.minor_features5);
0538aaf9
LS		 957 seq_printf(m, "\t minor_features6: 0x%08x\n",
958 gpu->identity.minor_features6);
959 seq_printf(m, "\t minor_features7: 0x%08x\n",
960 gpu->identity.minor_features7);
961 seq_printf(m, "\t minor_features8: 0x%08x\n",
962 gpu->identity.minor_features8);
963 seq_printf(m, "\t minor_features9: 0x%08x\n",
964 gpu->identity.minor_features9);
965 seq_printf(m, "\t minor_features10: 0x%08x\n",
966 gpu->identity.minor_features10);
967 seq_printf(m, "\t minor_features11: 0x%08x\n",
968 gpu->identity.minor_features11);
a8c21a54
T		 969
970 seq_puts(m, "\tspecs\n");
971 seq_printf(m, "\t stream_count: %d\n",
972 gpu->identity.stream_count);
973 seq_printf(m, "\t register_max: %d\n",
974 gpu->identity.register_max);
975 seq_printf(m, "\t thread_count: %d\n",
976 gpu->identity.thread_count);
977 seq_printf(m, "\t vertex_cache_size: %d\n",
978 gpu->identity.vertex_cache_size);
979 seq_printf(m, "\t shader_core_count: %d\n",
980 gpu->identity.shader_core_count);
4c22c61e
LS		 981 seq_printf(m, "\t nn_core_count: %d\n",
982 gpu->identity.nn_core_count);
a8c21a54
T		 983 seq_printf(m, "\t pixel_pipes: %d\n",
984 gpu->identity.pixel_pipes);
985 seq_printf(m, "\t vertex_output_buffer_size: %d\n",
986 gpu->identity.vertex_output_buffer_size);
987 seq_printf(m, "\t buffer_size: %d\n",
988 gpu->identity.buffer_size);
989 seq_printf(m, "\t instruction_count: %d\n",
990 gpu->identity.instruction_count);
991 seq_printf(m, "\t num_constants: %d\n",
992 gpu->identity.num_constants);
602eb489
RK		 993 seq_printf(m, "\t varyings_count: %d\n",
994 gpu->identity.varyings_count);
a8c21a54
T		 995
996 seq_printf(m, "\taxi: 0x%08x\n", axi);
997 seq_printf(m, "\tidle: 0x%08x\n", idle);
998 idle |= ~gpu->idle_mask & ~VIVS_HI_IDLE_STATE_AXI_LP;
999 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0)
1000 seq_puts(m, "\t FE is not idle\n");
1001 if ((idle & VIVS_HI_IDLE_STATE_DE) == 0)
1002 seq_puts(m, "\t DE is not idle\n");
1003 if ((idle & VIVS_HI_IDLE_STATE_PE) == 0)
1004 seq_puts(m, "\t PE is not idle\n");
1005 if ((idle & VIVS_HI_IDLE_STATE_SH) == 0)
1006 seq_puts(m, "\t SH is not idle\n");
1007 if ((idle & VIVS_HI_IDLE_STATE_PA) == 0)
1008 seq_puts(m, "\t PA is not idle\n");
1009 if ((idle & VIVS_HI_IDLE_STATE_SE) == 0)
1010 seq_puts(m, "\t SE is not idle\n");
1011 if ((idle & VIVS_HI_IDLE_STATE_RA) == 0)
1012 seq_puts(m, "\t RA is not idle\n");
1013 if ((idle & VIVS_HI_IDLE_STATE_TX) == 0)
1014 seq_puts(m, "\t TX is not idle\n");
1015 if ((idle & VIVS_HI_IDLE_STATE_VG) == 0)
1016 seq_puts(m, "\t VG is not idle\n");
1017 if ((idle & VIVS_HI_IDLE_STATE_IM) == 0)
1018 seq_puts(m, "\t IM is not idle\n");
1019 if ((idle & VIVS_HI_IDLE_STATE_FP) == 0)
1020 seq_puts(m, "\t FP is not idle\n");
1021 if ((idle & VIVS_HI_IDLE_STATE_TS) == 0)
1022 seq_puts(m, "\t TS is not idle\n");
b1704551
GG		 1023 if ((idle & VIVS_HI_IDLE_STATE_BL) == 0)
1024 seq_puts(m, "\t BL is not idle\n");
1025 if ((idle & VIVS_HI_IDLE_STATE_ASYNCFE) == 0)
1026 seq_puts(m, "\t ASYNCFE is not idle\n");
1027 if ((idle & VIVS_HI_IDLE_STATE_MC) == 0)
1028 seq_puts(m, "\t MC is not idle\n");
1029 if ((idle & VIVS_HI_IDLE_STATE_PPA) == 0)
1030 seq_puts(m, "\t PPA is not idle\n");
1031 if ((idle & VIVS_HI_IDLE_STATE_WD) == 0)
1032 seq_puts(m, "\t WD is not idle\n");
1033 if ((idle & VIVS_HI_IDLE_STATE_NN) == 0)
1034 seq_puts(m, "\t NN is not idle\n");
1035 if ((idle & VIVS_HI_IDLE_STATE_TP) == 0)
1036 seq_puts(m, "\t TP is not idle\n");
a8c21a54
T		 1037 if (idle & VIVS_HI_IDLE_STATE_AXI_LP)
1038 seq_puts(m, "\t AXI low power mode\n");
1039
1040 if (gpu->identity.features & chipFeatures_DEBUG_MODE) {
1041 u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0);
1042 u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1);
1043 u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE);
1044
1045 seq_puts(m, "\tMC\n");
1046 seq_printf(m, "\t read0: 0x%08x\n", read0);
1047 seq_printf(m, "\t read1: 0x%08x\n", read1);
1048 seq_printf(m, "\t write: 0x%08x\n", write);
1049 }
1050
1051 seq_puts(m, "\tDMA ");
1052
1053 if (debug.address[0] == debug.address[1] &&
1054 debug.state[0] == debug.state[1]) {
1055 seq_puts(m, "seems to be stuck\n");
1056 } else if (debug.address[0] == debug.address[1]) {
c01e0159 1057 seq_puts(m, "address is constant\n");
a8c21a54 1058 } else {
c01e0159 1059 seq_puts(m, "is running\n");
a8c21a54
T		 1060 }
1061
1062 seq_printf(m, "\t address 0: 0x%08x\n", debug.address[0]);
1063 seq_printf(m, "\t address 1: 0x%08x\n", debug.address[1]);
1064 seq_printf(m, "\t state 0: 0x%08x\n", debug.state[0]);
1065 seq_printf(m, "\t state 1: 0x%08x\n", debug.state[1]);
1066 seq_printf(m, "\t last fetch 64 bit word: 0x%08x 0x%08x\n",
1067 dma_lo, dma_hi);
1068
1069 ret = 0;
1070
1071 pm_runtime_mark_last_busy(gpu->dev);
c5d5a32e 1072pm_put:
a8c21a54
T		 1073 pm_runtime_put_autosuspend(gpu->dev);
1074
1075 return ret;
1076}
1077#endif
1078
a8c21a54
T		 1079/* fence object management */
1080struct etnaviv_fence {
1081 struct etnaviv_gpu *gpu;
f54d1867 1082 struct dma_fence base;
a8c21a54
T		 1083};
1084
f54d1867 1085static inline struct etnaviv_fence *to_etnaviv_fence(struct dma_fence *fence)
a8c21a54
T		 1086{
1087 return container_of(fence, struct etnaviv_fence, base);
1088}
1089
f54d1867 1090static const char *etnaviv_fence_get_driver_name(struct dma_fence *fence)
a8c21a54
T		 1091{
1092 return "etnaviv";
1093}
1094
f54d1867 1095static const char *etnaviv_fence_get_timeline_name(struct dma_fence *fence)
a8c21a54
T		 1096{
1097 struct etnaviv_fence *f = to_etnaviv_fence(fence);
1098
1099 return dev_name(f->gpu->dev);
1100}
1101
f54d1867 1102static bool etnaviv_fence_signaled(struct dma_fence *fence)
a8c21a54
T		 1103{
1104 struct etnaviv_fence *f = to_etnaviv_fence(fence);
1105
3283ee77 1106 return (s32)(f->gpu->completed_fence - f->base.seqno) >= 0;
a8c21a54
T		 1107}
1108
f54d1867 1109static void etnaviv_fence_release(struct dma_fence *fence)
a8c21a54
T		 1110{
1111 struct etnaviv_fence *f = to_etnaviv_fence(fence);
1112
1113 kfree_rcu(f, base.rcu);
1114}
1115
f54d1867 1116static const struct dma_fence_ops etnaviv_fence_ops = {
a8c21a54
T		 1117 .get_driver_name = etnaviv_fence_get_driver_name,
1118 .get_timeline_name = etnaviv_fence_get_timeline_name,
a8c21a54 1119 .signaled = etnaviv_fence_signaled,
a8c21a54
T		 1120 .release = etnaviv_fence_release,
1121};
1122
f54d1867 1123static struct dma_fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu)
a8c21a54
T		 1124{
1125 struct etnaviv_fence *f;
1126
b27734c2
LS		 1127 /*
1128 * GPU lock must already be held, otherwise fence completion order might
1129 * not match the seqno order assigned here.
1130 */
1131 lockdep_assert_held(&gpu->lock);
1132
a8c21a54
T		 1133 f = kzalloc(sizeof(*f), GFP_KERNEL);
1134 if (!f)
1135 return NULL;
1136
1137 f->gpu = gpu;
1138
f54d1867
CW		 1139 dma_fence_init(&f->base, &etnaviv_fence_ops, &gpu->fence_spinlock,
1140 gpu->fence_context, ++gpu->next_fence);
a8c21a54
T		 1141
1142 return &f->base;
1143}
1144
3283ee77
LS		 1145/* returns true if fence a comes after fence b */
1146static inline bool fence_after(u32 a, u32 b)
1147{
1148 return (s32)(a - b) > 0;
1149}
1150
a8c21a54
T		 1151/*
1152 * event management:
1153 */
1154
95a428c1
CG		 1155static int event_alloc(struct etnaviv_gpu *gpu, unsigned nr_events,
1156 unsigned int *events)
a8c21a54 1157{
5a23144c 1158 unsigned long timeout = msecs_to_jiffies(10 * 10000);
f098f9b8
LS		 1159 unsigned i, acquired = 0, rpm_count = 0;
1160 int ret;
a8c21a54 1161
95a428c1
CG		 1162 for (i = 0; i < nr_events; i++) {
1163 unsigned long ret;
a8c21a54 1164
95a428c1 1165 ret = wait_for_completion_timeout(&gpu->event_free, timeout);
a8c21a54 1166
95a428c1
CG		 1167 if (!ret) {
1168 dev_err(gpu->dev, "wait_for_completion_timeout failed");
f098f9b8 1169 ret = -EBUSY;
95a428c1 1170 goto out;
a8c21a54 1171 }
95a428c1
CG		 1172
1173 acquired++;
1174 timeout = ret;
1175 }
a8c21a54 1176
5a23144c 1177 spin_lock(&gpu->event_spinlock);
a8c21a54 1178
95a428c1
CG		 1179 for (i = 0; i < nr_events; i++) {
1180 int event = find_first_zero_bit(gpu->event_bitmap, ETNA_NR_EVENTS);
1181
1182 events[i] = event;
547d340d 1183 memset(&gpu->event[event], 0, sizeof(struct etnaviv_event));
355502e0 1184 set_bit(event, gpu->event_bitmap);
a8c21a54
T		 1185 }
1186
5a23144c 1187 spin_unlock(&gpu->event_spinlock);
a8c21a54 1188
f098f9b8
LS		 1189 for (i = 0; i < nr_events; i++) {
1190 ret = pm_runtime_resume_and_get(gpu->dev);
1191 if (ret)
1192 goto out_rpm;
1193 rpm_count++;
1194 }
1195
95a428c1
CG		 1196 return 0;
1197
f098f9b8
LS		 1198out_rpm:
1199 for (i = 0; i < rpm_count; i++)
1200 pm_runtime_put_autosuspend(gpu->dev);
95a428c1
CG		 1201out:
1202 for (i = 0; i < acquired; i++)
1203 complete(&gpu->event_free);
1204
f098f9b8 1205 return ret;
a8c21a54
T		 1206}
1207
1208static void event_free(struct etnaviv_gpu *gpu, unsigned int event)
1209{
355502e0 1210 if (!test_bit(event, gpu->event_bitmap)) {
a8c21a54
T		 1211 dev_warn(gpu->dev, "event %u is already marked as free",
1212 event);
a8c21a54 1213 } else {
355502e0 1214 clear_bit(event, gpu->event_bitmap);
a8c21a54
T		 1215 complete(&gpu->event_free);
1216 }
f098f9b8
LS		 1217
1218 pm_runtime_put_autosuspend(gpu->dev);
a8c21a54
T		 1219}
1220
1221/*
1222 * Cmdstream submission/retirement:
1223 */
a8c21a54 1224int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu,
38c4a4cf 1225 u32 id, struct drm_etnaviv_timespec *timeout)
a8c21a54 1226{
8bc4d885 1227 struct dma_fence *fence;
a8c21a54
T		 1228 int ret;
1229
8bc4d885 1230 /*
e93b6dee 1231 * Look up the fence and take a reference. We might still find a fence
8bc4d885
LS		 1232 * whose refcount has already dropped to zero. dma_fence_get_rcu
1233 * pretends we didn't find a fence in that case.
1234 */
e93b6dee 1235 rcu_read_lock();
764be123 1236 fence = xa_load(&gpu->user_fences, id);
8bc4d885
LS		 1237 if (fence)
1238 fence = dma_fence_get_rcu(fence);
e93b6dee 1239 rcu_read_unlock();
8bc4d885
LS		 1240
1241 if (!fence)
1242 return 0;
a8c21a54
T		 1243
1244 if (!timeout) {
1245 /* No timeout was requested: just test for completion */
8bc4d885 1246 ret = dma_fence_is_signaled(fence) ? 0 : -EBUSY;
a8c21a54
T		 1247 } else {
1248 unsigned long remaining = etnaviv_timeout_to_jiffies(timeout);
1249
8bc4d885
LS		 1250 ret = dma_fence_wait_timeout(fence, true, remaining);
1251 if (ret == 0)
a8c21a54 1252 ret = -ETIMEDOUT;
8bc4d885 1253 else if (ret != -ERESTARTSYS)
a8c21a54 1254 ret = 0;
8bc4d885 1255
a8c21a54
T		 1256 }
1257
8bc4d885 1258 dma_fence_put(fence);
a8c21a54
T		 1259 return ret;
1260}
1261
1262/*
1263 * Wait for an object to become inactive. This, on it's own, is not race
e93b6dee 1264 * free: the object is moved by the scheduler off the active list, and
a8c21a54
T		 1265 * then the iova is put. Moreover, the object could be re-submitted just
1266 * after we notice that it's become inactive.
1267 *
1268 * Although the retirement happens under the gpu lock, we don't want to hold
1269 * that lock in this function while waiting.
1270 */
1271int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu,
38c4a4cf
AB		 1272 struct etnaviv_gem_object *etnaviv_obj,
1273 struct drm_etnaviv_timespec *timeout)
a8c21a54
T		 1274{
1275 unsigned long remaining;
1276 long ret;
1277
1278 if (!timeout)
1279 return !is_active(etnaviv_obj) ? 0 : -EBUSY;
1280
1281 remaining = etnaviv_timeout_to_jiffies(timeout);
1282
1283 ret = wait_event_interruptible_timeout(gpu->fence_event,
1284 !is_active(etnaviv_obj),
1285 remaining);
fa67ac84 1286 if (ret > 0)
a8c21a54 1287 return 0;
fa67ac84 1288 else if (ret == -ERESTARTSYS)
a8c21a54 1289 return -ERESTARTSYS;
fa67ac84 1290 else
a8c21a54 1291 return -ETIMEDOUT;
a8c21a54
T		 1292}
1293
68dc0b29
CG		 1294static void sync_point_perfmon_sample(struct etnaviv_gpu *gpu,
1295 struct etnaviv_event *event, unsigned int flags)
1296{
ef146c00 1297 const struct etnaviv_gem_submit *submit = event->submit;
68dc0b29
CG		 1298 unsigned int i;
1299
ef146c00
LS		 1300 for (i = 0; i < submit->nr_pmrs; i++) {
1301 const struct etnaviv_perfmon_request *pmr = submit->pmrs + i;
68dc0b29
CG		 1302
1303 if (pmr->flags == flags)
7a9c0fe2 1304 etnaviv_perfmon_process(gpu, pmr, submit->exec_state);
68dc0b29
CG		 1305 }
1306}
1307
1308static void sync_point_perfmon_sample_pre(struct etnaviv_gpu *gpu,
1309 struct etnaviv_event *event)
1310{
2c8b0c5a
CG		 1311 u32 val;
1312
1313 /* disable clock gating */
61a6920b 1314 val = gpu_read_power(gpu, VIVS_PM_POWER_CONTROLS);
2c8b0c5a 1315 val &= ~VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
61a6920b 1316 gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, val);
2c8b0c5a 1317
04a7d18d
CG		 1318 /* enable debug register */
1319 val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
1320 val &= ~VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
1321 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val);
1322
68dc0b29
CG		 1323 sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_PRE);
1324}
1325
1326static void sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu,
1327 struct etnaviv_event *event)
1328{
ef146c00 1329 const struct etnaviv_gem_submit *submit = event->submit;
68dc0b29 1330 unsigned int i;
2c8b0c5a 1331 u32 val;
68dc0b29
CG		 1332
1333 sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_POST);
1334
ef146c00
LS		 1335 for (i = 0; i < submit->nr_pmrs; i++) {
1336 const struct etnaviv_perfmon_request *pmr = submit->pmrs + i;
68dc0b29
CG		 1337
1338 *pmr->bo_vma = pmr->sequence;
1339 }
2c8b0c5a 1340
04a7d18d
CG		 1341 /* disable debug register */
1342 val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
1343 val |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
1344 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val);
1345
2c8b0c5a 1346 /* enable clock gating */
61a6920b 1347 val = gpu_read_power(gpu, VIVS_PM_POWER_CONTROLS);
2c8b0c5a 1348 val |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
61a6920b 1349 gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, val);
68dc0b29
CG		 1350}
1351
1352
a8c21a54 1353/* add bo's to gpu's ring, and kick gpu: */
e93b6dee 1354struct dma_fence *etnaviv_gpu_submit(struct etnaviv_gem_submit *submit)
a8c21a54 1355{
e93b6dee
LS		 1356 struct etnaviv_gpu *gpu = submit->gpu;
1357 struct dma_fence *gpu_fence;
68dc0b29 1358 unsigned int i, nr_events = 1, event[3];
a8c21a54
T		 1359 int ret;
1360
68dc0b29
CG		 1361 /*
1362 * if there are performance monitor requests we need to have
1363 * - a sync point to re-configure gpu and process ETNA_PM_PROCESS_PRE
1364 * requests.
1365 * - a sync point to re-configure gpu, process ETNA_PM_PROCESS_POST requests
1366 * and update the sequence number for userspace.
1367 */
ef146c00 1368 if (submit->nr_pmrs)
68dc0b29
CG		 1369 nr_events = 3;
1370
1371 ret = event_alloc(gpu, nr_events, event);
95a428c1 1372 if (ret) {
68dc0b29 1373 DRM_ERROR("no free events\n");
c5d5a32e 1374 pm_runtime_put_noidle(gpu->dev);
e93b6dee 1375 return NULL;
a8c21a54
T		 1376 }
1377
f3cd1b06
LS		 1378 mutex_lock(&gpu->lock);
1379
e93b6dee
LS		 1380 gpu_fence = etnaviv_gpu_fence_alloc(gpu);
1381 if (!gpu_fence) {
68dc0b29
CG		 1382 for (i = 0; i < nr_events; i++)
1383 event_free(gpu, event[i]);
1384
45abdf35 1385 goto out_unlock;
a8c21a54
T		 1386 }
1387
647d817d 1388 if (gpu->state == ETNA_GPU_STATE_INITIALIZED)
d6408538
LS		 1389 etnaviv_gpu_start_fe_idleloop(gpu, submit->mmu_context);
1390
1391 if (submit->prev_mmu_context)
1392 etnaviv_iommu_context_put(submit->prev_mmu_context);
1393 submit->prev_mmu_context = etnaviv_iommu_context_get(gpu->mmu_context);
17e4660a 1394
ef146c00 1395 if (submit->nr_pmrs) {
68dc0b29 1396 gpu->event[event[1]].sync_point = &sync_point_perfmon_sample_pre;
ef146c00
LS		 1397 kref_get(&submit->refcount);
1398 gpu->event[event[1]].submit = submit;
68dc0b29
CG		 1399 etnaviv_sync_point_queue(gpu, event[1]);
1400 }
1401
e93b6dee 1402 gpu->event[event[0]].fence = gpu_fence;
6d7a20c0 1403 submit->cmdbuf.user_size = submit->cmdbuf.size - 8;
17e4660a
LS		 1404 etnaviv_buffer_queue(gpu, submit->exec_state, submit->mmu_context,
1405 event[0], &submit->cmdbuf);
68dc0b29 1406
ef146c00 1407 if (submit->nr_pmrs) {
68dc0b29 1408 gpu->event[event[2]].sync_point = &sync_point_perfmon_sample_post;
ef146c00
LS		 1409 kref_get(&submit->refcount);
1410 gpu->event[event[2]].submit = submit;
68dc0b29
CG		 1411 etnaviv_sync_point_queue(gpu, event[2]);
1412 }
a8c21a54 1413
45abdf35 1414out_unlock:
a8c21a54
T		 1415 mutex_unlock(&gpu->lock);
1416
e93b6dee 1417 return gpu_fence;
a8c21a54
T		 1418}
1419
357713ce
CG		 1420static void sync_point_worker(struct work_struct *work)
1421{
1422 struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu,
1423 sync_point_work);
b9a48aa7
LS		 1424 struct etnaviv_event *event = &gpu->event[gpu->sync_point_event];
1425 u32 addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
357713ce 1426
b9a48aa7 1427 event->sync_point(gpu, event);
ef146c00 1428 etnaviv_submit_put(event->submit);
357713ce 1429 event_free(gpu, gpu->sync_point_event);
b9a48aa7
LS		 1430
1431 /* restart FE last to avoid GPU and IRQ racing against this worker */
1432 etnaviv_gpu_start_fe(gpu, addr + 2, 2);
357713ce
CG		 1433}
1434
5cefcf9f
LS		 1435void etnaviv_gpu_recover_hang(struct etnaviv_gem_submit *submit)
1436{
1437 struct etnaviv_gpu *gpu = submit->gpu;
1438 char *comm = NULL, *cmd = NULL;
1439 struct task_struct *task;
1440 unsigned int i;
1441
1442 dev_err(gpu->dev, "recover hung GPU!\n");
1443
1444 task = get_pid_task(submit->pid, PIDTYPE_PID);
1445 if (task) {
1446 comm = kstrdup(task->comm, GFP_KERNEL);
1447 cmd = kstrdup_quotable_cmdline(task, GFP_KERNEL);
1448 put_task_struct(task);
1449 }
1450
1451 if (comm && cmd)
1452 dev_err(gpu->dev, "offending task: %s (%s)\n", comm, cmd);
1453
1454 kfree(cmd);
1455 kfree(comm);
1456
1457 if (pm_runtime_get_sync(gpu->dev) < 0)
1458 goto pm_put;
1459
1460 mutex_lock(&gpu->lock);
1461
1462 etnaviv_hw_reset(gpu);
1463
1464 /* complete all events, the GPU won't do it after the reset */
1465 spin_lock(&gpu->event_spinlock);
1466 for_each_set_bit(i, gpu->event_bitmap, ETNA_NR_EVENTS)
80f6b63e 1467 event_free(gpu, i);
5cefcf9f
LS		 1468 spin_unlock(&gpu->event_spinlock);
1469
1470 etnaviv_gpu_hw_init(gpu);
1471
1472 mutex_unlock(&gpu->lock);
1473 pm_runtime_mark_last_busy(gpu->dev);
1474pm_put:
1475 pm_runtime_put_autosuspend(gpu->dev);
1476}
1477
4df3000e
LS		 1478static void dump_mmu_fault(struct etnaviv_gpu *gpu)
1479{
b4bc0e74
CG		 1480 static const char *fault_reasons[] = {
1481 "slave not present",
1482 "page not present",
1483 "write violation",
1484 "out of bounds",
1485 "read security violation",
1486 "write security violation",
1487 };
1488
c997c3df 1489 u32 status_reg, status;
4df3000e
LS		 1490 int i;
1491
c997c3df
LS		 1492 if (gpu->sec_mode == ETNA_SEC_NONE)
1493 status_reg = VIVS_MMUv2_STATUS;
1494 else
1495 status_reg = VIVS_MMUv2_SEC_STATUS;
1496
1497 status = gpu_read(gpu, status_reg);
4df3000e
LS		 1498 dev_err_ratelimited(gpu->dev, "MMU fault status 0x%08x\n", status);
1499
1500 for (i = 0; i < 4; i++) {
b4bc0e74 1501 const char *reason = "unknown";
c997c3df 1502 u32 address_reg;
b4bc0e74 1503 u32 mmu_status;
c997c3df 1504
b4bc0e74
CG		 1505 mmu_status = (status >> (i * 4)) & VIVS_MMUv2_STATUS_EXCEPTION0__MASK;
1506 if (!mmu_status)
4df3000e
LS		 1507 continue;
1508
b4bc0e74
CG		 1509 if ((mmu_status - 1) < ARRAY_SIZE(fault_reasons))
1510 reason = fault_reasons[mmu_status - 1];
1511
c997c3df
LS		 1512 if (gpu->sec_mode == ETNA_SEC_NONE)
1513 address_reg = VIVS_MMUv2_EXCEPTION_ADDR(i);
1514 else
1515 address_reg = VIVS_MMUv2_SEC_EXCEPTION_ADDR;
1516
b4bc0e74
CG		 1517 dev_err_ratelimited(gpu->dev,
1518 "MMU %d fault (%s) addr 0x%08x\n",
1519 i, reason, gpu_read(gpu, address_reg));
4df3000e
LS		 1520 }
1521}
1522
a8c21a54
T		 1523static irqreturn_t irq_handler(int irq, void *data)
1524{
1525 struct etnaviv_gpu *gpu = data;
1526 irqreturn_t ret = IRQ_NONE;
1527
1528 u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE);
1529
1530 if (intr != 0) {
1531 int event;
1532
1533 pm_runtime_mark_last_busy(gpu->dev);
1534
1535 dev_dbg(gpu->dev, "intr 0x%08x\n", intr);
1536
1537 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR) {
1538 dev_err(gpu->dev, "AXI bus error\n");
1539 intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR;
1540 }
1541
128a9b1d 1542 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION) {
4df3000e 1543 dump_mmu_fault(gpu);
128a9b1d
LS		 1544 intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION;
1545 }
1546
a8c21a54 1547 while ((event = ffs(intr)) != 0) {
f54d1867 1548 struct dma_fence *fence;
a8c21a54
T		 1549
1550 event -= 1;
1551
1552 intr &= ~(1 << event);
1553
1554 dev_dbg(gpu->dev, "event %u\n", event);
1555
357713ce
CG		 1556 if (gpu->event[event].sync_point) {
1557 gpu->sync_point_event = event;
a7790d78 1558 queue_work(gpu->wq, &gpu->sync_point_work);
357713ce
CG		 1559 }
1560
a8c21a54 1561 fence = gpu->event[event].fence;
68dc0b29
CG		 1562 if (!fence)
1563 continue;
1564
a8c21a54 1565 gpu->event[event].fence = NULL;
a8c21a54
T		 1566
1567 /*
1568 * Events can be processed out of order. Eg,
1569 * - allocate and queue event 0
1570 * - allocate event 1
1571 * - event 0 completes, we process it
1572 * - allocate and queue event 0
1573 * - event 1 and event 0 complete
1574 * we can end up processing event 0 first, then 1.
1575 */
1576 if (fence_after(fence->seqno, gpu->completed_fence))
1577 gpu->completed_fence = fence->seqno;
8bc4d885 1578 dma_fence_signal(fence);
a8c21a54
T		 1579
1580 event_free(gpu, event);
a8c21a54
T		 1581 }
1582
a8c21a54
T		 1583 ret = IRQ_HANDLED;
1584 }
1585
1586 return ret;
1587}
1588
1589static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu)
1590{
1591 int ret;
1592
6a5ef3b2
LR		 1593 ret = clk_prepare_enable(gpu->clk_reg);
1594 if (ret)
1595 return ret;
65f037e8 1596
6a5ef3b2
LR		 1597 ret = clk_prepare_enable(gpu->clk_bus);
1598 if (ret)
1599 goto disable_clk_reg;
a8c21a54 1600
6a5ef3b2
LR		 1601 ret = clk_prepare_enable(gpu->clk_core);
1602 if (ret)
1603 goto disable_clk_bus;
9c7310c0 1604
6a5ef3b2
LR		 1605 ret = clk_prepare_enable(gpu->clk_shader);
1606 if (ret)
1607 goto disable_clk_core;
a8c21a54
T		 1608
1609 return 0;
9c7310c0
LS		 1610
1611disable_clk_core:
6a5ef3b2 1612 clk_disable_unprepare(gpu->clk_core);
9c7310c0 1613disable_clk_bus:
6a5ef3b2 1614 clk_disable_unprepare(gpu->clk_bus);
f8794fea 1615disable_clk_reg:
6a5ef3b2 1616 clk_disable_unprepare(gpu->clk_reg);
9c7310c0
LS		 1617
1618 return ret;
a8c21a54
T		 1619}
1620
1621static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu)
1622{
6a5ef3b2
LR		 1623 clk_disable_unprepare(gpu->clk_shader);
1624 clk_disable_unprepare(gpu->clk_core);
1625 clk_disable_unprepare(gpu->clk_bus);
1626 clk_disable_unprepare(gpu->clk_reg);
a8c21a54
T		 1627
1628 return 0;
1629}
1630
b88163e3
LS		 1631int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms)
1632{
1633 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
1634
1635 do {
1636 u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
1637
1638 if ((idle & gpu->idle_mask) == gpu->idle_mask)
1639 return 0;
1640
1641 if (time_is_before_jiffies(timeout)) {
1642 dev_warn(gpu->dev,
1643 "timed out waiting for idle: idle=0x%x\n",
1644 idle);
1645 return -ETIMEDOUT;
1646 }
1647
1648 udelay(5);
1649 } while (1);
1650}
1651
7cb54494 1652static void etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu)
a8c21a54 1653{
647d817d 1654 if (gpu->state == ETNA_GPU_STATE_RUNNING) {
a8c21a54 1655 /* Replace the last WAIT with END */
40c27bde 1656 mutex_lock(&gpu->lock);
a8c21a54 1657 etnaviv_buffer_end(gpu);
40c27bde 1658 mutex_unlock(&gpu->lock);
a8c21a54
T		 1659
1660 /*
1661 * We know that only the FE is busy here, this should
1662 * happen quickly (as the WAIT is only 200 cycles). If
1663 * we fail, just warn and continue.
1664 */
b88163e3 1665 etnaviv_gpu_wait_idle(gpu, 100);
17e4660a 1666
647d817d 1667 gpu->state = ETNA_GPU_STATE_INITIALIZED;
a8c21a54
T		 1668 }
1669
17e4660a 1670 gpu->exec_state = -1;
a8c21a54
T		 1671}
1672
a8c21a54
T		 1673static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu)
1674{
a8c21a54
T		 1675 int ret;
1676
1677 ret = mutex_lock_killable(&gpu->lock);
1678 if (ret)
1679 return ret;
1680
bcdfb5e5 1681 etnaviv_gpu_update_clock(gpu);
a8c21a54
T		 1682 etnaviv_gpu_hw_init(gpu);
1683
a8c21a54
T		 1684 mutex_unlock(&gpu->lock);
1685
1686 return 0;
1687}
a8c21a54 1688
bcdfb5e5
RK		 1689static int
1690etnaviv_gpu_cooling_get_max_state(struct thermal_cooling_device *cdev,
1691 unsigned long *state)
1692{
1693 *state = 6;
1694
1695 return 0;
1696}
1697
1698static int
1699etnaviv_gpu_cooling_get_cur_state(struct thermal_cooling_device *cdev,
1700 unsigned long *state)
1701{
1702 struct etnaviv_gpu *gpu = cdev->devdata;
1703
1704 *state = gpu->freq_scale;
1705
1706 return 0;
1707}
1708
1709static int
1710etnaviv_gpu_cooling_set_cur_state(struct thermal_cooling_device *cdev,
1711 unsigned long state)
1712{
1713 struct etnaviv_gpu *gpu = cdev->devdata;
1714
1715 mutex_lock(&gpu->lock);
1716 gpu->freq_scale = state;
1717 if (!pm_runtime_suspended(gpu->dev))
1718 etnaviv_gpu_update_clock(gpu);
1719 mutex_unlock(&gpu->lock);
1720
1721 return 0;
1722}
1723
96894b79 1724static const struct thermal_cooling_device_ops cooling_ops = {
bcdfb5e5
RK		 1725 .get_max_state = etnaviv_gpu_cooling_get_max_state,
1726 .get_cur_state = etnaviv_gpu_cooling_get_cur_state,
1727 .set_cur_state = etnaviv_gpu_cooling_set_cur_state,
1728};
1729
a8c21a54
T		 1730static int etnaviv_gpu_bind(struct device *dev, struct device *master,
1731 void *data)
1732{
1733 struct drm_device *drm = data;
1734 struct etnaviv_drm_private *priv = drm->dev_private;
1735 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1736 int ret;
1737
49b82c38 1738 if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL)) {
5247e2aa 1739 gpu->cooling = thermal_of_cooling_device_register(dev->of_node,
bcdfb5e5 1740 (char *)dev_name(dev), gpu, &cooling_ops);
5247e2aa
LS		 1741 if (IS_ERR(gpu->cooling))
1742 return PTR_ERR(gpu->cooling);
1743 }
bcdfb5e5 1744
a7790d78
LS		 1745 gpu->wq = alloc_ordered_workqueue(dev_name(dev), 0);
1746 if (!gpu->wq) {
e93b6dee
LS		 1747 ret = -ENOMEM;
1748 goto out_thermal;
a7790d78
LS		 1749 }
1750
e93b6dee
LS		 1751 ret = etnaviv_sched_init(gpu);
1752 if (ret)
1753 goto out_workqueue;
1754
448406ea 1755 if (!IS_ENABLED(CONFIG_PM)) {
6b05266a 1756 ret = etnaviv_gpu_clk_enable(gpu);
448406ea
LS		 1757 if (ret < 0)
1758 goto out_sched;
1759 }
a8c21a54
T		 1760
1761 gpu->drm = drm;
f54d1867 1762 gpu->fence_context = dma_fence_context_alloc(1);
764be123 1763 xa_init_flags(&gpu->user_fences, XA_FLAGS_ALLOC);
a8c21a54
T		 1764 spin_lock_init(&gpu->fence_spinlock);
1765
357713ce 1766 INIT_WORK(&gpu->sync_point_work, sync_point_worker);
a8c21a54
T		 1767 init_waitqueue_head(&gpu->fence_event);
1768
a8c21a54
T		 1769 priv->gpu[priv->num_gpus++] = gpu;
1770
a8c21a54 1771 return 0;
e93b6dee
LS		 1772
1773out_sched:
1774 etnaviv_sched_fini(gpu);
1775
1776out_workqueue:
1777 destroy_workqueue(gpu->wq);
1778
1779out_thermal:
1780 if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL))
1781 thermal_cooling_device_unregister(gpu->cooling);
1782
1783 return ret;
a8c21a54
T		 1784}
1785
1786static void etnaviv_gpu_unbind(struct device *dev, struct device *master,
1787 void *data)
1788{
1789 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1790
1791 DBG("%s", dev_name(gpu->dev));
1792
a7790d78
LS		 1793 destroy_workqueue(gpu->wq);
1794
e93b6dee
LS		 1795 etnaviv_sched_fini(gpu);
1796
6b05266a
PC		 1797 if (IS_ENABLED(CONFIG_PM)) {
1798 pm_runtime_get_sync(gpu->dev);
1799 pm_runtime_put_sync_suspend(gpu->dev);
1800 } else {
1801 etnaviv_gpu_hw_suspend(gpu);
7cb54494 1802 etnaviv_gpu_clk_disable(gpu);
6b05266a 1803 }
a8c21a54 1804
8f3eea9d
LS		 1805 if (gpu->mmu_context)
1806 etnaviv_iommu_context_put(gpu->mmu_context);
1807
db41fe7d 1808 if (gpu->initialized) {
2f9225db 1809 etnaviv_cmdbuf_free(&gpu->buffer);
27b67278 1810 etnaviv_iommu_global_fini(gpu);
db41fe7d 1811 gpu->initialized = false;
a8c21a54
T		 1812 }
1813
1814 gpu->drm = NULL;
764be123 1815 xa_destroy(&gpu->user_fences);
bcdfb5e5 1816
49b82c38
PZ		 1817 if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL))
1818 thermal_cooling_device_unregister(gpu->cooling);
bcdfb5e5 1819 gpu->cooling = NULL;
a8c21a54
T		 1820}
1821
1822static const struct component_ops gpu_ops = {
1823 .bind = etnaviv_gpu_bind,
1824 .unbind = etnaviv_gpu_unbind,
1825};
1826
1827static const struct of_device_id etnaviv_gpu_match[] = {
1828 {
1829 .compatible = "vivante,gc"
1830 },
1831 { /* sentinel */ }
1832};
246774d1 1833MODULE_DEVICE_TABLE(of, etnaviv_gpu_match);
a8c21a54
T		 1834
1835static int etnaviv_gpu_platform_probe(struct platform_device *pdev)
1836{
1837 struct device *dev = &pdev->dev;
1838 struct etnaviv_gpu *gpu;
dc227890 1839 int err;
a8c21a54
T		 1840
1841 gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL);
1842 if (!gpu)
1843 return -ENOMEM;
1844
1845 gpu->dev = &pdev->dev;
1846 mutex_init(&gpu->lock);
2cd5bd98 1847 mutex_init(&gpu->sched_lock);
a8c21a54 1848
a8c21a54 1849 /* Map registers: */
facb180d 1850 gpu->mmio = devm_platform_ioremap_resource(pdev, 0);
a8c21a54
T		 1851 if (IS_ERR(gpu->mmio))
1852 return PTR_ERR(gpu->mmio);
1853
1854 /* Get Interrupt: */
1855 gpu->irq = platform_get_irq(pdev, 0);
0e63302d 1856 if (gpu->irq < 0)
db60eda3 1857 return gpu->irq;
a8c21a54
T		 1858
1859 err = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 0,
1860 dev_name(gpu->dev), gpu);
1861 if (err) {
1862 dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err);
db60eda3 1863 return err;
a8c21a54
T		 1864 }
1865
1866 /* Get Clocks: */
f76fc5ff 1867 gpu->clk_reg = devm_clk_get_optional(&pdev->dev, "reg");
65f037e8
LS		 1868 DBG("clk_reg: %p", gpu->clk_reg);
1869 if (IS_ERR(gpu->clk_reg))
f76fc5ff 1870 return PTR_ERR(gpu->clk_reg);
65f037e8 1871
f76fc5ff 1872 gpu->clk_bus = devm_clk_get_optional(&pdev->dev, "bus");
a8c21a54
T		 1873 DBG("clk_bus: %p", gpu->clk_bus);
1874 if (IS_ERR(gpu->clk_bus))
f76fc5ff 1875 return PTR_ERR(gpu->clk_bus);
a8c21a54 1876
a59052d2 1877 gpu->clk_core = devm_clk_get(&pdev->dev, "core");
a8c21a54
T		 1878 DBG("clk_core: %p", gpu->clk_core);
1879 if (IS_ERR(gpu->clk_core))
f76fc5ff 1880 return PTR_ERR(gpu->clk_core);
d79fd1cc 1881 gpu->base_rate_core = clk_get_rate(gpu->clk_core);
a8c21a54 1882
f76fc5ff 1883 gpu->clk_shader = devm_clk_get_optional(&pdev->dev, "shader");
a8c21a54
T		 1884 DBG("clk_shader: %p", gpu->clk_shader);
1885 if (IS_ERR(gpu->clk_shader))
f76fc5ff 1886 return PTR_ERR(gpu->clk_shader);
d79fd1cc 1887 gpu->base_rate_shader = clk_get_rate(gpu->clk_shader);
a8c21a54
T		 1888
1889 /* TODO: figure out max mapped size */
1890 dev_set_drvdata(dev, gpu);
1891
1892 /*
1893 * We treat the device as initially suspended. The runtime PM
1894 * autosuspend delay is rather arbitary: no measurements have
1895 * yet been performed to determine an appropriate value.
1896 */
1897 pm_runtime_use_autosuspend(gpu->dev);
1898 pm_runtime_set_autosuspend_delay(gpu->dev, 200);
1899 pm_runtime_enable(gpu->dev);
1900
1901 err = component_add(&pdev->dev, &gpu_ops);
1902 if (err < 0) {
1903 dev_err(&pdev->dev, "failed to register component: %d\n", err);
db60eda3 1904 return err;
a8c21a54
T		 1905 }
1906
1907 return 0;
a8c21a54
T		 1908}
1909
1910static int etnaviv_gpu_platform_remove(struct platform_device *pdev)
1911{
1912 component_del(&pdev->dev, &gpu_ops);
1913 pm_runtime_disable(&pdev->dev);
1914 return 0;
1915}
1916
a8c21a54
T		 1917static int etnaviv_gpu_rpm_suspend(struct device *dev)
1918{
1919 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1920 u32 idle, mask;
1921
f4163814
LS		 1922 /* If there are any jobs in the HW queue, we're not idle */
1923 if (atomic_read(&gpu->sched.hw_rq_count))
a8c21a54
T		 1924 return -EBUSY;
1925
1a910c11
GG		 1926 /* Check whether the hardware (except FE and MC) is idle */
1927 mask = gpu->idle_mask & ~(VIVS_HI_IDLE_STATE_FE |
1928 VIVS_HI_IDLE_STATE_MC);
a8c21a54 1929 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask;
78f2bfa3
GG		 1930 if (idle != mask) {
1931 dev_warn_ratelimited(dev, "GPU not yet idle, mask: 0x%08x\n",
1932 idle);
a8c21a54 1933 return -EBUSY;
78f2bfa3 1934 }
a8c21a54 1935
7cb54494
LS		 1936 etnaviv_gpu_hw_suspend(gpu);
1937
647d817d
LS		 1938 gpu->state = ETNA_GPU_STATE_IDENTIFIED;
1939
7cb54494 1940 return etnaviv_gpu_clk_disable(gpu);
a8c21a54
T		 1941}
1942
1943static int etnaviv_gpu_rpm_resume(struct device *dev)
1944{
1945 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1946 int ret;
1947
1948 ret = etnaviv_gpu_clk_enable(gpu);
1949 if (ret)
1950 return ret;
1951
1952 /* Re-initialise the basic hardware state */
647d817d 1953 if (gpu->state == ETNA_GPU_STATE_IDENTIFIED) {
a8c21a54
T		 1954 ret = etnaviv_gpu_hw_resume(gpu);
1955 if (ret) {
1956 etnaviv_gpu_clk_disable(gpu);
1957 return ret;
1958 }
1959 }
1960
1961 return 0;
1962}
a8c21a54
T		 1963
1964static const struct dev_pm_ops etnaviv_gpu_pm_ops = {
6b05266a 1965 RUNTIME_PM_OPS(etnaviv_gpu_rpm_suspend, etnaviv_gpu_rpm_resume, NULL)
a8c21a54
T		 1966};
1967
1968struct platform_driver etnaviv_gpu_driver = {
1969 .driver = {
1970 .name = "etnaviv-gpu",
1971 .owner = THIS_MODULE,
6b05266a 1972 .pm = pm_ptr(&etnaviv_gpu_pm_ops),
a8c21a54
T		 1973 .of_match_table = etnaviv_gpu_match,
1974 },
1975 .probe = etnaviv_gpu_platform_probe,
1976 .remove = etnaviv_gpu_platform_remove,
1977 .id_table = gpu_ids,
1978};
Linux 6.x block layer and io_uring tree(s)