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drm/etnaviv: Ignore MC when checking runtime suspend idleness
[linux-2.6-block.git] / drivers / gpu / drm / etnaviv / etnaviv_gpu.c
CommitLineData
f6ffbd4f 1// SPDX-License-Identifier: GPL-2.0
a8c21a54 2/*
f6ffbd4f 3 * Copyright (C) 2015-2018 Etnaviv Project
a8c21a54
T		 4 */
5
f9d255f4 6#include <linux/clk.h>
a8c21a54 7#include <linux/component.h>
6eae41fe 8#include <linux/delay.h>
f54d1867 9#include <linux/dma-fence.h>
6eae41fe 10#include <linux/dma-mapping.h>
2e737e52 11#include <linux/module.h>
a8c21a54 12#include <linux/of_device.h>
2e737e52
LS		 13#include <linux/platform_device.h>
14#include <linux/pm_runtime.h>
f9d255f4 15#include <linux/regulator/consumer.h>
bcdfb5e5 16#include <linux/thermal.h>
ea1f5729
LS		 17
18#include "etnaviv_cmdbuf.h"
a8c21a54
T		 19#include "etnaviv_dump.h"
20#include "etnaviv_gpu.h"
21#include "etnaviv_gem.h"
22#include "etnaviv_mmu.h"
357713ce 23#include "etnaviv_perfmon.h"
e93b6dee 24#include "etnaviv_sched.h"
a8c21a54
T		 25#include "common.xml.h"
26#include "state.xml.h"
27#include "state_hi.xml.h"
28#include "cmdstream.xml.h"
29
c09d7f79
LS		 30#ifndef PHYS_OFFSET
31#define PHYS_OFFSET 0
32#endif
33
a8c21a54
T		 34static const struct platform_device_id gpu_ids[] = {
35 { .name = "etnaviv-gpu,2d" },
36 { },
37};
38
a8c21a54
T		 39/*
40 * Driver functions:
41 */
42
43int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value)
44{
088880dd
LS		 45 struct etnaviv_drm_private *priv = gpu->drm->dev_private;
46
a8c21a54
T		 47 switch (param) {
48 case ETNAVIV_PARAM_GPU_MODEL:
49 *value = gpu->identity.model;
50 break;
51
52 case ETNAVIV_PARAM_GPU_REVISION:
53 *value = gpu->identity.revision;
54 break;
55
56 case ETNAVIV_PARAM_GPU_FEATURES_0:
57 *value = gpu->identity.features;
58 break;
59
60 case ETNAVIV_PARAM_GPU_FEATURES_1:
61 *value = gpu->identity.minor_features0;
62 break;
63
64 case ETNAVIV_PARAM_GPU_FEATURES_2:
65 *value = gpu->identity.minor_features1;
66 break;
67
68 case ETNAVIV_PARAM_GPU_FEATURES_3:
69 *value = gpu->identity.minor_features2;
70 break;
71
72 case ETNAVIV_PARAM_GPU_FEATURES_4:
73 *value = gpu->identity.minor_features3;
74 break;
75
602eb489
RK		 76 case ETNAVIV_PARAM_GPU_FEATURES_5:
77 *value = gpu->identity.minor_features4;
78 break;
79
80 case ETNAVIV_PARAM_GPU_FEATURES_6:
81 *value = gpu->identity.minor_features5;
82 break;
83
0538aaf9
LS		 84 case ETNAVIV_PARAM_GPU_FEATURES_7:
85 *value = gpu->identity.minor_features6;
86 break;
87
88 case ETNAVIV_PARAM_GPU_FEATURES_8:
89 *value = gpu->identity.minor_features7;
90 break;
91
92 case ETNAVIV_PARAM_GPU_FEATURES_9:
93 *value = gpu->identity.minor_features8;
94 break;
95
96 case ETNAVIV_PARAM_GPU_FEATURES_10:
97 *value = gpu->identity.minor_features9;
98 break;
99
100 case ETNAVIV_PARAM_GPU_FEATURES_11:
101 *value = gpu->identity.minor_features10;
102 break;
103
104 case ETNAVIV_PARAM_GPU_FEATURES_12:
105 *value = gpu->identity.minor_features11;
106 break;
107
a8c21a54
T		 108 case ETNAVIV_PARAM_GPU_STREAM_COUNT:
109 *value = gpu->identity.stream_count;
110 break;
111
112 case ETNAVIV_PARAM_GPU_REGISTER_MAX:
113 *value = gpu->identity.register_max;
114 break;
115
116 case ETNAVIV_PARAM_GPU_THREAD_COUNT:
117 *value = gpu->identity.thread_count;
118 break;
119
120 case ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE:
121 *value = gpu->identity.vertex_cache_size;
122 break;
123
124 case ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT:
125 *value = gpu->identity.shader_core_count;
126 break;
127
128 case ETNAVIV_PARAM_GPU_PIXEL_PIPES:
129 *value = gpu->identity.pixel_pipes;
130 break;
131
132 case ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE:
133 *value = gpu->identity.vertex_output_buffer_size;
134 break;
135
136 case ETNAVIV_PARAM_GPU_BUFFER_SIZE:
137 *value = gpu->identity.buffer_size;
138 break;
139
140 case ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT:
141 *value = gpu->identity.instruction_count;
142 break;
143
144 case ETNAVIV_PARAM_GPU_NUM_CONSTANTS:
145 *value = gpu->identity.num_constants;
146 break;
147
602eb489
RK		 148 case ETNAVIV_PARAM_GPU_NUM_VARYINGS:
149 *value = gpu->identity.varyings_count;
150 break;
151
088880dd
LS		 152 case ETNAVIV_PARAM_SOFTPIN_START_ADDR:
153 if (priv->mmu_global->version == ETNAVIV_IOMMU_V2)
154 *value = ETNAVIV_SOFTPIN_START_ADDRESS;
155 else
156 *value = ~0ULL;
157 break;
158
a8c21a54
T		 159 default:
160 DBG("%s: invalid param: %u", dev_name(gpu->dev), param);
161 return -EINVAL;
162 }
163
164 return 0;
165}
166
472f79dc
RK		 167
168#define etnaviv_is_model_rev(gpu, mod, rev) \
169 ((gpu)->identity.model == chipModel_##mod && \
170 (gpu)->identity.revision == rev)
52f36ba1
RK		 171#define etnaviv_field(val, field) \
172 (((val) & field##__MASK) >> field##__SHIFT)
173
a8c21a54
T		 174static void etnaviv_hw_specs(struct etnaviv_gpu *gpu)
175{
176 if (gpu->identity.minor_features0 &
177 chipMinorFeatures0_MORE_MINOR_FEATURES) {
602eb489
RK		 178 u32 specs[4];
179 unsigned int streams;
a8c21a54
T		 180
181 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS);
182 specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2);
602eb489
RK		 183 specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3);
184 specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4);
a8c21a54 185
52f36ba1
RK		 186 gpu->identity.stream_count = etnaviv_field(specs[0],
187 VIVS_HI_CHIP_SPECS_STREAM_COUNT);
188 gpu->identity.register_max = etnaviv_field(specs[0],
189 VIVS_HI_CHIP_SPECS_REGISTER_MAX);
190 gpu->identity.thread_count = etnaviv_field(specs[0],
191 VIVS_HI_CHIP_SPECS_THREAD_COUNT);
192 gpu->identity.vertex_cache_size = etnaviv_field(specs[0],
193 VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE);
194 gpu->identity.shader_core_count = etnaviv_field(specs[0],
195 VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT);
196 gpu->identity.pixel_pipes = etnaviv_field(specs[0],
197 VIVS_HI_CHIP_SPECS_PIXEL_PIPES);
a8c21a54 198 gpu->identity.vertex_output_buffer_size =
52f36ba1
RK		 199 etnaviv_field(specs[0],
200 VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE);
201
202 gpu->identity.buffer_size = etnaviv_field(specs[1],
203 VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE);
204 gpu->identity.instruction_count = etnaviv_field(specs[1],
205 VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT);
206 gpu->identity.num_constants = etnaviv_field(specs[1],
207 VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS);
602eb489
RK		 208
209 gpu->identity.varyings_count = etnaviv_field(specs[2],
210 VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT);
211
212 /* This overrides the value from older register if non-zero */
213 streams = etnaviv_field(specs[3],
214 VIVS_HI_CHIP_SPECS_4_STREAM_COUNT);
215 if (streams)
216 gpu->identity.stream_count = streams;
a8c21a54
T		 217 }
218
219 /* Fill in the stream count if not specified */
220 if (gpu->identity.stream_count == 0) {
221 if (gpu->identity.model >= 0x1000)
222 gpu->identity.stream_count = 4;
223 else
224 gpu->identity.stream_count = 1;
225 }
226
227 /* Convert the register max value */
228 if (gpu->identity.register_max)
229 gpu->identity.register_max = 1 << gpu->identity.register_max;
507f8991 230 else if (gpu->identity.model == chipModel_GC400)
a8c21a54
T		 231 gpu->identity.register_max = 32;
232 else
233 gpu->identity.register_max = 64;
234
235 /* Convert thread count */
236 if (gpu->identity.thread_count)
237 gpu->identity.thread_count = 1 << gpu->identity.thread_count;
507f8991 238 else if (gpu->identity.model == chipModel_GC400)
a8c21a54 239 gpu->identity.thread_count = 64;
507f8991
RK		 240 else if (gpu->identity.model == chipModel_GC500 ||
241 gpu->identity.model == chipModel_GC530)
a8c21a54
T		 242 gpu->identity.thread_count = 128;
243 else
244 gpu->identity.thread_count = 256;
245
246 if (gpu->identity.vertex_cache_size == 0)
247 gpu->identity.vertex_cache_size = 8;
248
249 if (gpu->identity.shader_core_count == 0) {
250 if (gpu->identity.model >= 0x1000)
251 gpu->identity.shader_core_count = 2;
252 else
253 gpu->identity.shader_core_count = 1;
254 }
255
256 if (gpu->identity.pixel_pipes == 0)
257 gpu->identity.pixel_pipes = 1;
258
259 /* Convert virtex buffer size */
260 if (gpu->identity.vertex_output_buffer_size) {
261 gpu->identity.vertex_output_buffer_size =
262 1 << gpu->identity.vertex_output_buffer_size;
507f8991 263 } else if (gpu->identity.model == chipModel_GC400) {
a8c21a54
T		 264 if (gpu->identity.revision < 0x4000)
265 gpu->identity.vertex_output_buffer_size = 512;
266 else if (gpu->identity.revision < 0x4200)
267 gpu->identity.vertex_output_buffer_size = 256;
268 else
269 gpu->identity.vertex_output_buffer_size = 128;
270 } else {
271 gpu->identity.vertex_output_buffer_size = 512;
272 }
273
274 switch (gpu->identity.instruction_count) {
275 case 0:
472f79dc 276 if (etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
507f8991 277 gpu->identity.model == chipModel_GC880)
a8c21a54
T		 278 gpu->identity.instruction_count = 512;
279 else
280 gpu->identity.instruction_count = 256;
281 break;
282
283 case 1:
284 gpu->identity.instruction_count = 1024;
285 break;
286
287 case 2:
288 gpu->identity.instruction_count = 2048;
289 break;
290
291 default:
292 gpu->identity.instruction_count = 256;
293 break;
294 }
295
296 if (gpu->identity.num_constants == 0)
297 gpu->identity.num_constants = 168;
602eb489
RK		 298
299 if (gpu->identity.varyings_count == 0) {
300 if (gpu->identity.minor_features1 & chipMinorFeatures1_HALTI0)
301 gpu->identity.varyings_count = 12;
302 else
303 gpu->identity.varyings_count = 8;
304 }
305
306 /*
307 * For some cores, two varyings are consumed for position, so the
308 * maximum varying count needs to be reduced by one.
309 */
310 if (etnaviv_is_model_rev(gpu, GC5000, 0x5434) ||
311 etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
312 etnaviv_is_model_rev(gpu, GC4000, 0x5245) ||
313 etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
314 etnaviv_is_model_rev(gpu, GC3000, 0x5435) ||
315 etnaviv_is_model_rev(gpu, GC2200, 0x5244) ||
316 etnaviv_is_model_rev(gpu, GC2100, 0x5108) ||
317 etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
318 etnaviv_is_model_rev(gpu, GC1500, 0x5246) ||
319 etnaviv_is_model_rev(gpu, GC880, 0x5107) ||
320 etnaviv_is_model_rev(gpu, GC880, 0x5106))
321 gpu->identity.varyings_count -= 1;
a8c21a54
T		 322}
323
324static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
325{
326 u32 chipIdentity;
327
328 chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY);
329
330 /* Special case for older graphic cores. */
52f36ba1 331 if (etnaviv_field(chipIdentity, VIVS_HI_CHIP_IDENTITY_FAMILY) == 0x01) {
507f8991 332 gpu->identity.model = chipModel_GC500;
52f36ba1
RK		 333 gpu->identity.revision = etnaviv_field(chipIdentity,
334 VIVS_HI_CHIP_IDENTITY_REVISION);
a8c21a54 335 } else {
815e45bb 336 u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE);
a8c21a54
T		 337
338 gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL);
339 gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV);
815e45bb
CG		 340 gpu->identity.product_id = gpu_read(gpu, VIVS_HI_CHIP_PRODUCT_ID);
341 gpu->identity.customer_id = gpu_read(gpu, VIVS_HI_CHIP_CUSTOMER_ID);
342 gpu->identity.eco_id = gpu_read(gpu, VIVS_HI_CHIP_ECO_ID);
a8c21a54
T		 343
344 /*
345 * !!!! HACK ALERT !!!!
346 * Because people change device IDs without letting software
347 * know about it - here is the hack to make it all look the
348 * same. Only for GC400 family.
349 */
350 if ((gpu->identity.model & 0xff00) == 0x0400 &&
507f8991 351 gpu->identity.model != chipModel_GC420) {
a8c21a54
T		 352 gpu->identity.model = gpu->identity.model & 0x0400;
353 }
354
355 /* Another special case */
472f79dc 356 if (etnaviv_is_model_rev(gpu, GC300, 0x2201)) {
a8c21a54
T		 357 u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME);
358
359 if (chipDate == 0x20080814 && chipTime == 0x12051100) {
360 /*
361 * This IP has an ECO; put the correct
362 * revision in it.
363 */
364 gpu->identity.revision = 0x1051;
365 }
366 }
12ff4bde
LS		 367
368 /*
369 * NXP likes to call the GPU on the i.MX6QP GC2000+, but in
370 * reality it's just a re-branded GC3000. We can identify this
371 * core by the upper half of the revision register being all 1.
372 * Fix model/rev here, so all other places can refer to this
373 * core by its real identity.
374 */
375 if (etnaviv_is_model_rev(gpu, GC2000, 0xffff5450)) {
376 gpu->identity.model = chipModel_GC3000;
377 gpu->identity.revision &= 0xffff;
378 }
815e45bb
CG		 379
380 if (etnaviv_is_model_rev(gpu, GC1000, 0x5037) && (chipDate == 0x20120617))
381 gpu->identity.eco_id = 1;
382
383 if (etnaviv_is_model_rev(gpu, GC320, 0x5303) && (chipDate == 0x20140511))
384 gpu->identity.eco_id = 1;
a8c21a54
T		 385 }
386
387 dev_info(gpu->dev, "model: GC%x, revision: %x\n",
388 gpu->identity.model, gpu->identity.revision);
389
2b76f5be 390 gpu->idle_mask = ~VIVS_HI_IDLE_STATE_AXI_LP;
681c19c8
LS		 391 /*
392 * If there is a match in the HWDB, we aren't interested in the
393 * remaining register values, as they might be wrong.
394 */
395 if (etnaviv_fill_identity_from_hwdb(gpu))
396 return;
397
a8c21a54
T		 398 gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE);
399
400 /* Disable fast clear on GC700. */
507f8991 401 if (gpu->identity.model == chipModel_GC700)
a8c21a54
T		 402 gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
403
507f8991
RK		 404 if ((gpu->identity.model == chipModel_GC500 &&
405 gpu->identity.revision < 2) ||
406 (gpu->identity.model == chipModel_GC300 &&
407 gpu->identity.revision < 0x2000)) {
a8c21a54
T		 408
409 /*
410 * GC500 rev 1.x and GC300 rev < 2.0 doesn't have these
411 * registers.
412 */
413 gpu->identity.minor_features0 = 0;
414 gpu->identity.minor_features1 = 0;
415 gpu->identity.minor_features2 = 0;
416 gpu->identity.minor_features3 = 0;
602eb489
RK		 417 gpu->identity.minor_features4 = 0;
418 gpu->identity.minor_features5 = 0;
a8c21a54
T		 419 } else
420 gpu->identity.minor_features0 =
421 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0);
422
423 if (gpu->identity.minor_features0 &
424 chipMinorFeatures0_MORE_MINOR_FEATURES) {
425 gpu->identity.minor_features1 =
426 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1);
427 gpu->identity.minor_features2 =
428 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2);
429 gpu->identity.minor_features3 =
430 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3);
602eb489
RK		 431 gpu->identity.minor_features4 =
432 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4);
433 gpu->identity.minor_features5 =
434 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5);
a8c21a54
T		 435 }
436
437 /* GC600 idle register reports zero bits where modules aren't present */
2b76f5be 438 if (gpu->identity.model == chipModel_GC600)
a8c21a54
T		 439 gpu->idle_mask = VIVS_HI_IDLE_STATE_TX |
440 VIVS_HI_IDLE_STATE_RA |
441 VIVS_HI_IDLE_STATE_SE |
442 VIVS_HI_IDLE_STATE_PA |
443 VIVS_HI_IDLE_STATE_SH |
444 VIVS_HI_IDLE_STATE_PE |
445 VIVS_HI_IDLE_STATE_DE |
446 VIVS_HI_IDLE_STATE_FE;
a8c21a54
T		 447
448 etnaviv_hw_specs(gpu);
449}
450
451static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock)
452{
453 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock |
454 VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD);
455 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock);
456}
457
bcdfb5e5
RK		 458static void etnaviv_gpu_update_clock(struct etnaviv_gpu *gpu)
459{
d79fd1cc
LS		 460 if (gpu->identity.minor_features2 &
461 chipMinorFeatures2_DYNAMIC_FREQUENCY_SCALING) {
462 clk_set_rate(gpu->clk_core,
463 gpu->base_rate_core >> gpu->freq_scale);
464 clk_set_rate(gpu->clk_shader,
465 gpu->base_rate_shader >> gpu->freq_scale);
466 } else {
467 unsigned int fscale = 1 << (6 - gpu->freq_scale);
6eb3ecc3 468 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
bcdfb5e5 469
6eb3ecc3
LS		 470 clock &= ~VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK;
471 clock |= VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
d79fd1cc
LS		 472 etnaviv_gpu_load_clock(gpu, clock);
473 }
bcdfb5e5
RK		 474}
475
a8c21a54
T		 476static int etnaviv_hw_reset(struct etnaviv_gpu *gpu)
477{
478 u32 control, idle;
479 unsigned long timeout;
480 bool failed = true;
481
a8c21a54
T		 482 /* We hope that the GPU resets in under one second */
483 timeout = jiffies + msecs_to_jiffies(1000);
484
485 while (time_is_after_jiffies(timeout)) {
a8c21a54 486 /* enable clock */
6eb3ecc3
LS		 487 unsigned int fscale = 1 << (6 - gpu->freq_scale);
488 control = VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
489 etnaviv_gpu_load_clock(gpu, control);
a8c21a54
T		 490
491 /* isolate the GPU. */
492 control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
493 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
494
c997c3df
LS		 495 if (gpu->sec_mode == ETNA_SEC_KERNEL) {
496 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL,
497 VIVS_MMUv2_AHB_CONTROL_RESET);
498 } else {
499 /* set soft reset. */
500 control |= VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
501 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
502 }
a8c21a54
T		 503
504 /* wait for reset. */
40462179 505 usleep_range(10, 20);
a8c21a54
T		 506
507 /* reset soft reset bit. */
508 control &= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
509 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
510
511 /* reset GPU isolation. */
512 control &= ~VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
513 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
514
515 /* read idle register. */
516 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
517
ea4ed4a5 518 /* try resetting again if FE is not idle */
a8c21a54
T		 519 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) {
520 dev_dbg(gpu->dev, "FE is not idle\n");
521 continue;
522 }
523
524 /* read reset register. */
525 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
526
527 /* is the GPU idle? */
528 if (((control & VIVS_HI_CLOCK_CONTROL_IDLE_3D) == 0) ||
529 ((control & VIVS_HI_CLOCK_CONTROL_IDLE_2D) == 0)) {
530 dev_dbg(gpu->dev, "GPU is not idle\n");
531 continue;
532 }
533
6eb3ecc3
LS		 534 /* disable debug registers, as they are not normally needed */
535 control |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
536 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
537
a8c21a54
T		 538 failed = false;
539 break;
540 }
541
542 if (failed) {
543 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
544 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
545
546 dev_err(gpu->dev, "GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidle\n",
547 idle & VIVS_HI_IDLE_STATE_FE ? "" : "not ",
548 control & VIVS_HI_CLOCK_CONTROL_IDLE_3D ? "" : "not ",
549 control & VIVS_HI_CLOCK_CONTROL_IDLE_2D ? "" : "not ");
550
551 return -EBUSY;
552 }
553
554 /* We rely on the GPU running, so program the clock */
bcdfb5e5 555 etnaviv_gpu_update_clock(gpu);
a8c21a54
T		 556
557 return 0;
558}
559
7d0c6e71
RK		 560static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu)
561{
562 u32 pmc, ppc;
563
564 /* enable clock gating */
565 ppc = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
566 ppc |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
567
568 /* Disable stall module clock gating for 4.3.0.1 and 4.3.0.2 revs */
569 if (gpu->identity.revision == 0x4301 ||
570 gpu->identity.revision == 0x4302)
571 ppc |= VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING;
572
573 gpu_write(gpu, VIVS_PM_POWER_CONTROLS, ppc);
574
575 pmc = gpu_read(gpu, VIVS_PM_MODULE_CONTROLS);
576
7cef6004 577 /* Disable PA clock gating for GC400+ without bugfix except for GC420 */
7d0c6e71 578 if (gpu->identity.model >= chipModel_GC400 &&
7cef6004
LS		 579 gpu->identity.model != chipModel_GC420 &&
580 !(gpu->identity.minor_features3 & chipMinorFeatures3_BUG_FIXES12))
7d0c6e71
RK		 581 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA;
582
583 /*
584 * Disable PE clock gating on revs < 5.0.0.0 when HZ is
585 * present without a bug fix.
586 */
587 if (gpu->identity.revision < 0x5000 &&
588 gpu->identity.minor_features0 & chipMinorFeatures0_HZ &&
589 !(gpu->identity.minor_features1 &
590 chipMinorFeatures1_DISABLE_PE_GATING))
591 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE;
592
593 if (gpu->identity.revision < 0x5422)
594 pmc |= BIT(15); /* Unknown bit */
595
7cef6004
LS		 596 /* Disable TX clock gating on affected core revisions. */
597 if (etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
598 etnaviv_is_model_rev(gpu, GC2000, 0x5108))
599 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX;
600
7d0c6e71
RK		 601 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ;
602 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ;
603
604 gpu_write(gpu, VIVS_PM_MODULE_CONTROLS, pmc);
605}
606
229855b6
LS		 607void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch)
608{
609 gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS, address);
610 gpu_write(gpu, VIVS_FE_COMMAND_CONTROL,
611 VIVS_FE_COMMAND_CONTROL_ENABLE |
612 VIVS_FE_COMMAND_CONTROL_PREFETCH(prefetch));
c997c3df
LS		 613
614 if (gpu->sec_mode == ETNA_SEC_KERNEL) {
615 gpu_write(gpu, VIVS_MMUv2_SEC_COMMAND_CONTROL,
616 VIVS_MMUv2_SEC_COMMAND_CONTROL_ENABLE |
617 VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH(prefetch));
618 }
229855b6
LS		 619}
620
d80d842a
LS		 621static void etnaviv_gpu_start_fe_idleloop(struct etnaviv_gpu *gpu)
622{
17e4660a
LS		 623 u32 address = etnaviv_cmdbuf_get_va(&gpu->buffer,
624 &gpu->mmu_context->cmdbuf_mapping);
d80d842a
LS		 625 u16 prefetch;
626
627 /* setup the MMU */
628 etnaviv_iommu_restore(gpu, gpu->mmu_context);
629
630 /* Start command processor */
631 prefetch = etnaviv_buffer_init(gpu);
632
633 etnaviv_gpu_start_fe(gpu, address, prefetch);
634}
635
e17a0ded
WL		 636static void etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu)
637{
638 /*
639 * Base value for VIVS_PM_PULSE_EATER register on models where it
640 * cannot be read, extracted from vivante kernel driver.
641 */
642 u32 pulse_eater = 0x01590880;
643
644 if (etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
645 etnaviv_is_model_rev(gpu, GC4000, 0x5222)) {
646 pulse_eater |= BIT(23);
647
648 }
649
650 if (etnaviv_is_model_rev(gpu, GC1000, 0x5039) ||
651 etnaviv_is_model_rev(gpu, GC1000, 0x5040)) {
652 pulse_eater &= ~BIT(16);
653 pulse_eater |= BIT(17);
654 }
655
656 if ((gpu->identity.revision > 0x5420) &&
657 (gpu->identity.features & chipFeatures_PIPE_3D))
658 {
659 /* Performance fix: disable internal DFS */
660 pulse_eater = gpu_read(gpu, VIVS_PM_PULSE_EATER);
661 pulse_eater |= BIT(18);
662 }
663
664 gpu_write(gpu, VIVS_PM_PULSE_EATER, pulse_eater);
665}
666
a8c21a54
T		 667static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu)
668{
472f79dc
RK		 669 if ((etnaviv_is_model_rev(gpu, GC320, 0x5007) ||
670 etnaviv_is_model_rev(gpu, GC320, 0x5220)) &&
671 gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) {
a8c21a54
T		 672 u32 mc_memory_debug;
673
674 mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff;
675
676 if (gpu->identity.revision == 0x5007)
677 mc_memory_debug |= 0x0c;
678 else
679 mc_memory_debug |= 0x08;
680
681 gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug);
682 }
683
7d0c6e71
RK		 684 /* enable module-level clock gating */
685 etnaviv_gpu_enable_mlcg(gpu);
686
a8c21a54
T		 687 /*
688 * Update GPU AXI cache atttribute to "cacheable, no allocate".
689 * This is necessary to prevent the iMX6 SoC locking up.
690 */
691 gpu_write(gpu, VIVS_HI_AXI_CONFIG,
692 VIVS_HI_AXI_CONFIG_AWCACHE(2) |
693 VIVS_HI_AXI_CONFIG_ARCACHE(2));
694
695 /* GC2000 rev 5108 needs a special bus config */
472f79dc 696 if (etnaviv_is_model_rev(gpu, GC2000, 0x5108)) {
a8c21a54
T		 697 u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG);
698 bus_config &= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK |
699 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK);
700 bus_config |= VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(1) |
701 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(0);
702 gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config);
703 }
704
c997c3df
LS		 705 if (gpu->sec_mode == ETNA_SEC_KERNEL) {
706 u32 val = gpu_read(gpu, VIVS_MMUv2_AHB_CONTROL);
707 val |= VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS;
708 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, val);
709 }
710
e17a0ded
WL		 711 /* setup the pulse eater */
712 etnaviv_gpu_setup_pulse_eater(gpu);
713
a8c21a54 714 gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U);
a8c21a54
T		 715}
716
717int etnaviv_gpu_init(struct etnaviv_gpu *gpu)
718{
bffe5db8 719 struct etnaviv_drm_private *priv = gpu->drm->dev_private;
a8c21a54 720 int ret, i;
a8c21a54
T		 721
722 ret = pm_runtime_get_sync(gpu->dev);
1409df04
LS		 723 if (ret < 0) {
724 dev_err(gpu->dev, "Failed to enable GPU power domain\n");
a8c21a54 725 return ret;
1409df04 726 }
a8c21a54
T		 727
728 etnaviv_hw_identify(gpu);
729
730 if (gpu->identity.model == 0) {
731 dev_err(gpu->dev, "Unknown GPU model\n");
f6427760
RK		 732 ret = -ENXIO;
733 goto fail;
a8c21a54
T		 734 }
735
b98c6688
RK		 736 /* Exclude VG cores with FE2.0 */
737 if (gpu->identity.features & chipFeatures_PIPE_VG &&
738 gpu->identity.features & chipFeatures_FE20) {
739 dev_info(gpu->dev, "Ignoring GPU with VG and FE2.0\n");
740 ret = -ENXIO;
741 goto fail;
742 }
743
c997c3df
LS		 744 /*
745 * On cores with security features supported, we claim control over the
746 * security states.
747 */
748 if ((gpu->identity.minor_features7 & chipMinorFeatures7_BIT_SECURITY) &&
749 (gpu->identity.minor_features10 & chipMinorFeatures10_SECURITY_AHB))
750 gpu->sec_mode = ETNA_SEC_KERNEL;
751
a8c21a54 752 ret = etnaviv_hw_reset(gpu);
1409df04
LS		 753 if (ret) {
754 dev_err(gpu->dev, "GPU reset failed\n");
a8c21a54 755 goto fail;
1409df04 756 }
a8c21a54 757
27b67278
LS		 758 ret = etnaviv_iommu_global_init(gpu);
759 if (ret)
a8c21a54 760 goto fail;
27b67278 761
17e4660a
LS		 762 /*
763 * Set the GPU linear window to be at the end of the DMA window, where
764 * the CMA area is likely to reside. This ensures that we are able to
765 * map the command buffers while having the linear window overlap as
766 * much RAM as possible, so we can optimize mappings for other buffers.
767 *
768 * For 3D cores only do this if MC2.0 is present, as with MC1.0 it leads
769 * to different views of the memory on the individual engines.
770 */
771 if (!(gpu->identity.features & chipFeatures_PIPE_3D) ||
772 (gpu->identity.minor_features0 & chipMinorFeatures0_MC20)) {
773 u32 dma_mask = (u32)dma_get_required_mask(gpu->dev);
774 if (dma_mask < PHYS_OFFSET + SZ_2G)
775 priv->mmu_global->memory_base = PHYS_OFFSET;
776 else
777 priv->mmu_global->memory_base = dma_mask - SZ_2G + 1;
778 } else if (PHYS_OFFSET >= SZ_2G) {
779 dev_info(gpu->dev, "Need to move linear window on MC1.0, disabling TS\n");
780 priv->mmu_global->memory_base = PHYS_OFFSET;
781 gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
db82a043
LS		 782 }
783
a8c21a54 784 /* Create buffer: */
bffe5db8 785 ret = etnaviv_cmdbuf_init(priv->cmdbuf_suballoc, &gpu->buffer,
2f9225db
LS		 786 PAGE_SIZE);
787 if (ret) {
a8c21a54 788 dev_err(gpu->dev, "could not create command buffer\n");
17e4660a 789 goto fail;
a8c21a54
T		 790 }
791
792 /* Setup event management */
793 spin_lock_init(&gpu->event_spinlock);
794 init_completion(&gpu->event_free);
355502e0
CG		 795 bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS);
796 for (i = 0; i < ARRAY_SIZE(gpu->event); i++)
a8c21a54 797 complete(&gpu->event_free);
a8c21a54
T		 798
799 /* Now program the hardware */
800 mutex_lock(&gpu->lock);
801 etnaviv_gpu_hw_init(gpu);
f6086311 802 gpu->exec_state = -1;
a8c21a54
T		 803 mutex_unlock(&gpu->lock);
804
805 pm_runtime_mark_last_busy(gpu->dev);
806 pm_runtime_put_autosuspend(gpu->dev);
807
db41fe7d
LS		 808 gpu->initialized = true;
809
a8c21a54
T		 810 return 0;
811
a8c21a54
T		 812fail:
813 pm_runtime_mark_last_busy(gpu->dev);
814 pm_runtime_put_autosuspend(gpu->dev);
815
816 return ret;
817}
818
819#ifdef CONFIG_DEBUG_FS
820struct dma_debug {
821 u32 address[2];
822 u32 state[2];
823};
824
825static void verify_dma(struct etnaviv_gpu *gpu, struct dma_debug *debug)
826{
827 u32 i;
828
829 debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
830 debug->state[0] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
831
832 for (i = 0; i < 500; i++) {
833 debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
834 debug->state[1] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
835
836 if (debug->address[0] != debug->address[1])
837 break;
838
839 if (debug->state[0] != debug->state[1])
840 break;
841 }
842}
843
844int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m)
845{
846 struct dma_debug debug;
847 u32 dma_lo, dma_hi, axi, idle;
848 int ret;
849
850 seq_printf(m, "%s Status:\n", dev_name(gpu->dev));
851
852 ret = pm_runtime_get_sync(gpu->dev);
853 if (ret < 0)
854 return ret;
855
856 dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW);
857 dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH);
858 axi = gpu_read(gpu, VIVS_HI_AXI_STATUS);
859 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
860
861 verify_dma(gpu, &debug);
862
00080663
CG		 863 seq_puts(m, "\tidentity\n");
864 seq_printf(m, "\t model: 0x%x\n", gpu->identity.model);
865 seq_printf(m, "\t revision: 0x%x\n", gpu->identity.revision);
866 seq_printf(m, "\t product_id: 0x%x\n", gpu->identity.product_id);
867 seq_printf(m, "\t customer_id: 0x%x\n", gpu->identity.customer_id);
868 seq_printf(m, "\t eco_id: 0x%x\n", gpu->identity.eco_id);
869
a8c21a54 870 seq_puts(m, "\tfeatures\n");
3d9fc642
LS		 871 seq_printf(m, "\t major_features: 0x%08x\n",
872 gpu->identity.features);
a8c21a54
T		 873 seq_printf(m, "\t minor_features0: 0x%08x\n",
874 gpu->identity.minor_features0);
875 seq_printf(m, "\t minor_features1: 0x%08x\n",
876 gpu->identity.minor_features1);
877 seq_printf(m, "\t minor_features2: 0x%08x\n",
878 gpu->identity.minor_features2);
879 seq_printf(m, "\t minor_features3: 0x%08x\n",
880 gpu->identity.minor_features3);
602eb489
RK		 881 seq_printf(m, "\t minor_features4: 0x%08x\n",
882 gpu->identity.minor_features4);
883 seq_printf(m, "\t minor_features5: 0x%08x\n",
884 gpu->identity.minor_features5);
0538aaf9
LS		 885 seq_printf(m, "\t minor_features6: 0x%08x\n",
886 gpu->identity.minor_features6);
887 seq_printf(m, "\t minor_features7: 0x%08x\n",
888 gpu->identity.minor_features7);
889 seq_printf(m, "\t minor_features8: 0x%08x\n",
890 gpu->identity.minor_features8);
891 seq_printf(m, "\t minor_features9: 0x%08x\n",
892 gpu->identity.minor_features9);
893 seq_printf(m, "\t minor_features10: 0x%08x\n",
894 gpu->identity.minor_features10);
895 seq_printf(m, "\t minor_features11: 0x%08x\n",
896 gpu->identity.minor_features11);
a8c21a54
T		 897
898 seq_puts(m, "\tspecs\n");
899 seq_printf(m, "\t stream_count: %d\n",
900 gpu->identity.stream_count);
901 seq_printf(m, "\t register_max: %d\n",
902 gpu->identity.register_max);
903 seq_printf(m, "\t thread_count: %d\n",
904 gpu->identity.thread_count);
905 seq_printf(m, "\t vertex_cache_size: %d\n",
906 gpu->identity.vertex_cache_size);
907 seq_printf(m, "\t shader_core_count: %d\n",
908 gpu->identity.shader_core_count);
909 seq_printf(m, "\t pixel_pipes: %d\n",
910 gpu->identity.pixel_pipes);
911 seq_printf(m, "\t vertex_output_buffer_size: %d\n",
912 gpu->identity.vertex_output_buffer_size);
913 seq_printf(m, "\t buffer_size: %d\n",
914 gpu->identity.buffer_size);
915 seq_printf(m, "\t instruction_count: %d\n",
916 gpu->identity.instruction_count);
917 seq_printf(m, "\t num_constants: %d\n",
918 gpu->identity.num_constants);
602eb489
RK		 919 seq_printf(m, "\t varyings_count: %d\n",
920 gpu->identity.varyings_count);
a8c21a54
T		 921
922 seq_printf(m, "\taxi: 0x%08x\n", axi);
923 seq_printf(m, "\tidle: 0x%08x\n", idle);
924 idle |= ~gpu->idle_mask & ~VIVS_HI_IDLE_STATE_AXI_LP;
925 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0)
926 seq_puts(m, "\t FE is not idle\n");
927 if ((idle & VIVS_HI_IDLE_STATE_DE) == 0)
928 seq_puts(m, "\t DE is not idle\n");
929 if ((idle & VIVS_HI_IDLE_STATE_PE) == 0)
930 seq_puts(m, "\t PE is not idle\n");
931 if ((idle & VIVS_HI_IDLE_STATE_SH) == 0)
932 seq_puts(m, "\t SH is not idle\n");
933 if ((idle & VIVS_HI_IDLE_STATE_PA) == 0)
934 seq_puts(m, "\t PA is not idle\n");
935 if ((idle & VIVS_HI_IDLE_STATE_SE) == 0)
936 seq_puts(m, "\t SE is not idle\n");
937 if ((idle & VIVS_HI_IDLE_STATE_RA) == 0)
938 seq_puts(m, "\t RA is not idle\n");
939 if ((idle & VIVS_HI_IDLE_STATE_TX) == 0)
940 seq_puts(m, "\t TX is not idle\n");
941 if ((idle & VIVS_HI_IDLE_STATE_VG) == 0)
942 seq_puts(m, "\t VG is not idle\n");
943 if ((idle & VIVS_HI_IDLE_STATE_IM) == 0)
944 seq_puts(m, "\t IM is not idle\n");
945 if ((idle & VIVS_HI_IDLE_STATE_FP) == 0)
946 seq_puts(m, "\t FP is not idle\n");
947 if ((idle & VIVS_HI_IDLE_STATE_TS) == 0)
948 seq_puts(m, "\t TS is not idle\n");
b1704551
GG		 949 if ((idle & VIVS_HI_IDLE_STATE_BL) == 0)
950 seq_puts(m, "\t BL is not idle\n");
951 if ((idle & VIVS_HI_IDLE_STATE_ASYNCFE) == 0)
952 seq_puts(m, "\t ASYNCFE is not idle\n");
953 if ((idle & VIVS_HI_IDLE_STATE_MC) == 0)
954 seq_puts(m, "\t MC is not idle\n");
955 if ((idle & VIVS_HI_IDLE_STATE_PPA) == 0)
956 seq_puts(m, "\t PPA is not idle\n");
957 if ((idle & VIVS_HI_IDLE_STATE_WD) == 0)
958 seq_puts(m, "\t WD is not idle\n");
959 if ((idle & VIVS_HI_IDLE_STATE_NN) == 0)
960 seq_puts(m, "\t NN is not idle\n");
961 if ((idle & VIVS_HI_IDLE_STATE_TP) == 0)
962 seq_puts(m, "\t TP is not idle\n");
a8c21a54
T		 963 if (idle & VIVS_HI_IDLE_STATE_AXI_LP)
964 seq_puts(m, "\t AXI low power mode\n");
965
966 if (gpu->identity.features & chipFeatures_DEBUG_MODE) {
967 u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0);
968 u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1);
969 u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE);
970
971 seq_puts(m, "\tMC\n");
972 seq_printf(m, "\t read0: 0x%08x\n", read0);
973 seq_printf(m, "\t read1: 0x%08x\n", read1);
974 seq_printf(m, "\t write: 0x%08x\n", write);
975 }
976
977 seq_puts(m, "\tDMA ");
978
979 if (debug.address[0] == debug.address[1] &&
980 debug.state[0] == debug.state[1]) {
981 seq_puts(m, "seems to be stuck\n");
982 } else if (debug.address[0] == debug.address[1]) {
c01e0159 983 seq_puts(m, "address is constant\n");
a8c21a54 984 } else {
c01e0159 985 seq_puts(m, "is running\n");
a8c21a54
T		 986 }
987
988 seq_printf(m, "\t address 0: 0x%08x\n", debug.address[0]);
989 seq_printf(m, "\t address 1: 0x%08x\n", debug.address[1]);
990 seq_printf(m, "\t state 0: 0x%08x\n", debug.state[0]);
991 seq_printf(m, "\t state 1: 0x%08x\n", debug.state[1]);
992 seq_printf(m, "\t last fetch 64 bit word: 0x%08x 0x%08x\n",
993 dma_lo, dma_hi);
994
995 ret = 0;
996
997 pm_runtime_mark_last_busy(gpu->dev);
998 pm_runtime_put_autosuspend(gpu->dev);
999
1000 return ret;
1001}
1002#endif
1003
6d7a20c0 1004void etnaviv_gpu_recover_hang(struct etnaviv_gpu *gpu)
a8c21a54 1005{
355502e0 1006 unsigned int i = 0;
a8c21a54 1007
6d7a20c0 1008 dev_err(gpu->dev, "recover hung GPU!\n");
a8c21a54
T		 1009
1010 if (pm_runtime_get_sync(gpu->dev) < 0)
1011 return;
1012
1013 mutex_lock(&gpu->lock);
1014
a8c21a54
T		 1015 etnaviv_hw_reset(gpu);
1016
1017 /* complete all events, the GPU won't do it after the reset */
5a23144c 1018 spin_lock(&gpu->event_spinlock);
6d7a20c0 1019 for_each_set_bit_from(i, gpu->event_bitmap, ETNA_NR_EVENTS)
a8c21a54 1020 complete(&gpu->event_free);
355502e0 1021 bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS);
5a23144c 1022 spin_unlock(&gpu->event_spinlock);
a8c21a54
T		 1023
1024 etnaviv_gpu_hw_init(gpu);
f6086311 1025 gpu->exec_state = -1;
17e4660a 1026 gpu->mmu_context = NULL;
a8c21a54
T		 1027
1028 mutex_unlock(&gpu->lock);
1029 pm_runtime_mark_last_busy(gpu->dev);
1030 pm_runtime_put_autosuspend(gpu->dev);
a8c21a54
T		 1031}
1032
a8c21a54
T		 1033/* fence object management */
1034struct etnaviv_fence {
1035 struct etnaviv_gpu *gpu;
f54d1867 1036 struct dma_fence base;
a8c21a54
T		 1037};
1038
f54d1867 1039static inline struct etnaviv_fence *to_etnaviv_fence(struct dma_fence *fence)
a8c21a54
T		 1040{
1041 return container_of(fence, struct etnaviv_fence, base);
1042}
1043
f54d1867 1044static const char *etnaviv_fence_get_driver_name(struct dma_fence *fence)
a8c21a54
T		 1045{
1046 return "etnaviv";
1047}
1048
f54d1867 1049static const char *etnaviv_fence_get_timeline_name(struct dma_fence *fence)
a8c21a54
T		 1050{
1051 struct etnaviv_fence *f = to_etnaviv_fence(fence);
1052
1053 return dev_name(f->gpu->dev);
1054}
1055
f54d1867 1056static bool etnaviv_fence_signaled(struct dma_fence *fence)
a8c21a54
T		 1057{
1058 struct etnaviv_fence *f = to_etnaviv_fence(fence);
1059
3283ee77 1060 return (s32)(f->gpu->completed_fence - f->base.seqno) >= 0;
a8c21a54
T		 1061}
1062
f54d1867 1063static void etnaviv_fence_release(struct dma_fence *fence)
a8c21a54
T		 1064{
1065 struct etnaviv_fence *f = to_etnaviv_fence(fence);
1066
1067 kfree_rcu(f, base.rcu);
1068}
1069
f54d1867 1070static const struct dma_fence_ops etnaviv_fence_ops = {
a8c21a54
T		 1071 .get_driver_name = etnaviv_fence_get_driver_name,
1072 .get_timeline_name = etnaviv_fence_get_timeline_name,
a8c21a54 1073 .signaled = etnaviv_fence_signaled,
a8c21a54
T		 1074 .release = etnaviv_fence_release,
1075};
1076
f54d1867 1077static struct dma_fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu)
a8c21a54
T		 1078{
1079 struct etnaviv_fence *f;
1080
b27734c2
LS		 1081 /*
1082 * GPU lock must already be held, otherwise fence completion order might
1083 * not match the seqno order assigned here.
1084 */
1085 lockdep_assert_held(&gpu->lock);
1086
a8c21a54
T		 1087 f = kzalloc(sizeof(*f), GFP_KERNEL);
1088 if (!f)
1089 return NULL;
1090
1091 f->gpu = gpu;
1092
f54d1867
CW		 1093 dma_fence_init(&f->base, &etnaviv_fence_ops, &gpu->fence_spinlock,
1094 gpu->fence_context, ++gpu->next_fence);
a8c21a54
T		 1095
1096 return &f->base;
1097}
1098
3283ee77
LS		 1099/* returns true if fence a comes after fence b */
1100static inline bool fence_after(u32 a, u32 b)
1101{
1102 return (s32)(a - b) > 0;
1103}
1104
a8c21a54
T		 1105/*
1106 * event management:
1107 */
1108
95a428c1
CG		 1109static int event_alloc(struct etnaviv_gpu *gpu, unsigned nr_events,
1110 unsigned int *events)
a8c21a54 1111{
5a23144c 1112 unsigned long timeout = msecs_to_jiffies(10 * 10000);
95a428c1 1113 unsigned i, acquired = 0;
a8c21a54 1114
95a428c1
CG		 1115 for (i = 0; i < nr_events; i++) {
1116 unsigned long ret;
a8c21a54 1117
95a428c1 1118 ret = wait_for_completion_timeout(&gpu->event_free, timeout);
a8c21a54 1119
95a428c1
CG		 1120 if (!ret) {
1121 dev_err(gpu->dev, "wait_for_completion_timeout failed");
1122 goto out;
a8c21a54 1123 }
95a428c1
CG		 1124
1125 acquired++;
1126 timeout = ret;
1127 }
a8c21a54 1128
5a23144c 1129 spin_lock(&gpu->event_spinlock);
a8c21a54 1130
95a428c1
CG		 1131 for (i = 0; i < nr_events; i++) {
1132 int event = find_first_zero_bit(gpu->event_bitmap, ETNA_NR_EVENTS);
1133
1134 events[i] = event;
547d340d 1135 memset(&gpu->event[event], 0, sizeof(struct etnaviv_event));
355502e0 1136 set_bit(event, gpu->event_bitmap);
a8c21a54
T		 1137 }
1138
5a23144c 1139 spin_unlock(&gpu->event_spinlock);
a8c21a54 1140
95a428c1
CG		 1141 return 0;
1142
1143out:
1144 for (i = 0; i < acquired; i++)
1145 complete(&gpu->event_free);
1146
1147 return -EBUSY;
a8c21a54
T		 1148}
1149
1150static void event_free(struct etnaviv_gpu *gpu, unsigned int event)
1151{
355502e0 1152 if (!test_bit(event, gpu->event_bitmap)) {
a8c21a54
T		 1153 dev_warn(gpu->dev, "event %u is already marked as free",
1154 event);
a8c21a54 1155 } else {
355502e0 1156 clear_bit(event, gpu->event_bitmap);
a8c21a54
T		 1157 complete(&gpu->event_free);
1158 }
1159}
1160
1161/*
1162 * Cmdstream submission/retirement:
1163 */
a8c21a54 1164int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu,
38c4a4cf 1165 u32 id, struct drm_etnaviv_timespec *timeout)
a8c21a54 1166{
8bc4d885 1167 struct dma_fence *fence;
a8c21a54
T		 1168 int ret;
1169
8bc4d885 1170 /*
e93b6dee 1171 * Look up the fence and take a reference. We might still find a fence
8bc4d885
LS		 1172 * whose refcount has already dropped to zero. dma_fence_get_rcu
1173 * pretends we didn't find a fence in that case.
1174 */
e93b6dee 1175 rcu_read_lock();
8bc4d885
LS		 1176 fence = idr_find(&gpu->fence_idr, id);
1177 if (fence)
1178 fence = dma_fence_get_rcu(fence);
e93b6dee 1179 rcu_read_unlock();
8bc4d885
LS		 1180
1181 if (!fence)
1182 return 0;
a8c21a54
T		 1183
1184 if (!timeout) {
1185 /* No timeout was requested: just test for completion */
8bc4d885 1186 ret = dma_fence_is_signaled(fence) ? 0 : -EBUSY;
a8c21a54
T		 1187 } else {
1188 unsigned long remaining = etnaviv_timeout_to_jiffies(timeout);
1189
8bc4d885
LS		 1190 ret = dma_fence_wait_timeout(fence, true, remaining);
1191 if (ret == 0)
a8c21a54 1192 ret = -ETIMEDOUT;
8bc4d885 1193 else if (ret != -ERESTARTSYS)
a8c21a54 1194 ret = 0;
8bc4d885 1195
a8c21a54
T		 1196 }
1197
8bc4d885 1198 dma_fence_put(fence);
a8c21a54
T		 1199 return ret;
1200}
1201
1202/*
1203 * Wait for an object to become inactive. This, on it's own, is not race
e93b6dee 1204 * free: the object is moved by the scheduler off the active list, and
a8c21a54
T		 1205 * then the iova is put. Moreover, the object could be re-submitted just
1206 * after we notice that it's become inactive.
1207 *
1208 * Although the retirement happens under the gpu lock, we don't want to hold
1209 * that lock in this function while waiting.
1210 */
1211int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu,
38c4a4cf
AB		 1212 struct etnaviv_gem_object *etnaviv_obj,
1213 struct drm_etnaviv_timespec *timeout)
a8c21a54
T		 1214{
1215 unsigned long remaining;
1216 long ret;
1217
1218 if (!timeout)
1219 return !is_active(etnaviv_obj) ? 0 : -EBUSY;
1220
1221 remaining = etnaviv_timeout_to_jiffies(timeout);
1222
1223 ret = wait_event_interruptible_timeout(gpu->fence_event,
1224 !is_active(etnaviv_obj),
1225 remaining);
fa67ac84 1226 if (ret > 0)
a8c21a54 1227 return 0;
fa67ac84 1228 else if (ret == -ERESTARTSYS)
a8c21a54 1229 return -ERESTARTSYS;
fa67ac84 1230 else
a8c21a54 1231 return -ETIMEDOUT;
a8c21a54
T		 1232}
1233
68dc0b29
CG		 1234static void sync_point_perfmon_sample(struct etnaviv_gpu *gpu,
1235 struct etnaviv_event *event, unsigned int flags)
1236{
ef146c00 1237 const struct etnaviv_gem_submit *submit = event->submit;
68dc0b29
CG		 1238 unsigned int i;
1239
ef146c00
LS		 1240 for (i = 0; i < submit->nr_pmrs; i++) {
1241 const struct etnaviv_perfmon_request *pmr = submit->pmrs + i;
68dc0b29
CG		 1242
1243 if (pmr->flags == flags)
7a9c0fe2 1244 etnaviv_perfmon_process(gpu, pmr, submit->exec_state);
68dc0b29
CG		 1245 }
1246}
1247
1248static void sync_point_perfmon_sample_pre(struct etnaviv_gpu *gpu,
1249 struct etnaviv_event *event)
1250{
2c8b0c5a
CG		 1251 u32 val;
1252
1253 /* disable clock gating */
1254 val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
1255 val &= ~VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
1256 gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val);
1257
04a7d18d
CG		 1258 /* enable debug register */
1259 val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
1260 val &= ~VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
1261 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val);
1262
68dc0b29
CG		 1263 sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_PRE);
1264}
1265
1266static void sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu,
1267 struct etnaviv_event *event)
1268{
ef146c00 1269 const struct etnaviv_gem_submit *submit = event->submit;
68dc0b29 1270 unsigned int i;
2c8b0c5a 1271 u32 val;
68dc0b29
CG		 1272
1273 sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_POST);
1274
ef146c00
LS		 1275 for (i = 0; i < submit->nr_pmrs; i++) {
1276 const struct etnaviv_perfmon_request *pmr = submit->pmrs + i;
68dc0b29
CG		 1277
1278 *pmr->bo_vma = pmr->sequence;
1279 }
2c8b0c5a 1280
04a7d18d
CG		 1281 /* disable debug register */
1282 val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
1283 val |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
1284 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val);
1285
2c8b0c5a
CG		 1286 /* enable clock gating */
1287 val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
1288 val |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
1289 gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val);
68dc0b29
CG		 1290}
1291
1292
a8c21a54 1293/* add bo's to gpu's ring, and kick gpu: */
e93b6dee 1294struct dma_fence *etnaviv_gpu_submit(struct etnaviv_gem_submit *submit)
a8c21a54 1295{
e93b6dee
LS		 1296 struct etnaviv_gpu *gpu = submit->gpu;
1297 struct dma_fence *gpu_fence;
68dc0b29 1298 unsigned int i, nr_events = 1, event[3];
a8c21a54
T		 1299 int ret;
1300
6d7a20c0
LS		 1301 if (!submit->runtime_resumed) {
1302 ret = pm_runtime_get_sync(gpu->dev);
1303 if (ret < 0)
1304 return NULL;
1305 submit->runtime_resumed = true;
1306 }
a8c21a54 1307
68dc0b29
CG		 1308 /*
1309 * if there are performance monitor requests we need to have
1310 * - a sync point to re-configure gpu and process ETNA_PM_PROCESS_PRE
1311 * requests.
1312 * - a sync point to re-configure gpu, process ETNA_PM_PROCESS_POST requests
1313 * and update the sequence number for userspace.
1314 */
ef146c00 1315 if (submit->nr_pmrs)
68dc0b29
CG		 1316 nr_events = 3;
1317
1318 ret = event_alloc(gpu, nr_events, event);
95a428c1 1319 if (ret) {
68dc0b29 1320 DRM_ERROR("no free events\n");
e93b6dee 1321 return NULL;
a8c21a54
T		 1322 }
1323
f3cd1b06
LS		 1324 mutex_lock(&gpu->lock);
1325
e93b6dee
LS		 1326 gpu_fence = etnaviv_gpu_fence_alloc(gpu);
1327 if (!gpu_fence) {
68dc0b29
CG		 1328 for (i = 0; i < nr_events; i++)
1329 event_free(gpu, event[i]);
1330
45abdf35 1331 goto out_unlock;
a8c21a54
T		 1332 }
1333
17e4660a
LS		 1334 if (!gpu->mmu_context) {
1335 etnaviv_iommu_context_get(submit->mmu_context);
1336 gpu->mmu_context = submit->mmu_context;
1337 etnaviv_gpu_start_fe_idleloop(gpu);
1338 } else {
1339 etnaviv_iommu_context_get(gpu->mmu_context);
1340 submit->prev_mmu_context = gpu->mmu_context;
1341 }
1342
ef146c00 1343 if (submit->nr_pmrs) {
68dc0b29 1344 gpu->event[event[1]].sync_point = &sync_point_perfmon_sample_pre;
ef146c00
LS		 1345 kref_get(&submit->refcount);
1346 gpu->event[event[1]].submit = submit;
68dc0b29
CG		 1347 etnaviv_sync_point_queue(gpu, event[1]);
1348 }
1349
e93b6dee 1350 gpu->event[event[0]].fence = gpu_fence;
6d7a20c0 1351 submit->cmdbuf.user_size = submit->cmdbuf.size - 8;
17e4660a
LS		 1352 etnaviv_buffer_queue(gpu, submit->exec_state, submit->mmu_context,
1353 event[0], &submit->cmdbuf);
68dc0b29 1354
ef146c00 1355 if (submit->nr_pmrs) {
68dc0b29 1356 gpu->event[event[2]].sync_point = &sync_point_perfmon_sample_post;
ef146c00
LS		 1357 kref_get(&submit->refcount);
1358 gpu->event[event[2]].submit = submit;
68dc0b29
CG		 1359 etnaviv_sync_point_queue(gpu, event[2]);
1360 }
a8c21a54 1361
45abdf35 1362out_unlock:
a8c21a54
T		 1363 mutex_unlock(&gpu->lock);
1364
e93b6dee 1365 return gpu_fence;
a8c21a54
T		 1366}
1367
357713ce
CG		 1368static void sync_point_worker(struct work_struct *work)
1369{
1370 struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu,
1371 sync_point_work);
b9a48aa7
LS		 1372 struct etnaviv_event *event = &gpu->event[gpu->sync_point_event];
1373 u32 addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
357713ce 1374
b9a48aa7 1375 event->sync_point(gpu, event);
ef146c00 1376 etnaviv_submit_put(event->submit);
357713ce 1377 event_free(gpu, gpu->sync_point_event);
b9a48aa7
LS		 1378
1379 /* restart FE last to avoid GPU and IRQ racing against this worker */
1380 etnaviv_gpu_start_fe(gpu, addr + 2, 2);
357713ce
CG		 1381}
1382
4df3000e
LS		 1383static void dump_mmu_fault(struct etnaviv_gpu *gpu)
1384{
c997c3df 1385 u32 status_reg, status;
4df3000e
LS		 1386 int i;
1387
c997c3df
LS		 1388 if (gpu->sec_mode == ETNA_SEC_NONE)
1389 status_reg = VIVS_MMUv2_STATUS;
1390 else
1391 status_reg = VIVS_MMUv2_SEC_STATUS;
1392
1393 status = gpu_read(gpu, status_reg);
4df3000e
LS		 1394 dev_err_ratelimited(gpu->dev, "MMU fault status 0x%08x\n", status);
1395
1396 for (i = 0; i < 4; i++) {
c997c3df
LS		 1397 u32 address_reg;
1398
4df3000e
LS		 1399 if (!(status & (VIVS_MMUv2_STATUS_EXCEPTION0__MASK << (i * 4))))
1400 continue;
1401
c997c3df
LS		 1402 if (gpu->sec_mode == ETNA_SEC_NONE)
1403 address_reg = VIVS_MMUv2_EXCEPTION_ADDR(i);
1404 else
1405 address_reg = VIVS_MMUv2_SEC_EXCEPTION_ADDR;
1406
4df3000e 1407 dev_err_ratelimited(gpu->dev, "MMU %d fault addr 0x%08x\n", i,
c997c3df 1408 gpu_read(gpu, address_reg));
4df3000e
LS		 1409 }
1410}
1411
a8c21a54
T		 1412static irqreturn_t irq_handler(int irq, void *data)
1413{
1414 struct etnaviv_gpu *gpu = data;
1415 irqreturn_t ret = IRQ_NONE;
1416
1417 u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE);
1418
1419 if (intr != 0) {
1420 int event;
1421
1422 pm_runtime_mark_last_busy(gpu->dev);
1423
1424 dev_dbg(gpu->dev, "intr 0x%08x\n", intr);
1425
1426 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR) {
1427 dev_err(gpu->dev, "AXI bus error\n");
1428 intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR;
1429 }
1430
128a9b1d 1431 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION) {
4df3000e 1432 dump_mmu_fault(gpu);
128a9b1d
LS		 1433 intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION;
1434 }
1435
a8c21a54 1436 while ((event = ffs(intr)) != 0) {
f54d1867 1437 struct dma_fence *fence;
a8c21a54
T		 1438
1439 event -= 1;
1440
1441 intr &= ~(1 << event);
1442
1443 dev_dbg(gpu->dev, "event %u\n", event);
1444
357713ce
CG		 1445 if (gpu->event[event].sync_point) {
1446 gpu->sync_point_event = event;
a7790d78 1447 queue_work(gpu->wq, &gpu->sync_point_work);
357713ce
CG		 1448 }
1449
a8c21a54 1450 fence = gpu->event[event].fence;
68dc0b29
CG		 1451 if (!fence)
1452 continue;
1453
a8c21a54 1454 gpu->event[event].fence = NULL;
a8c21a54
T		 1455
1456 /*
1457 * Events can be processed out of order. Eg,
1458 * - allocate and queue event 0
1459 * - allocate event 1
1460 * - event 0 completes, we process it
1461 * - allocate and queue event 0
1462 * - event 1 and event 0 complete
1463 * we can end up processing event 0 first, then 1.
1464 */
1465 if (fence_after(fence->seqno, gpu->completed_fence))
1466 gpu->completed_fence = fence->seqno;
8bc4d885 1467 dma_fence_signal(fence);
a8c21a54
T		 1468
1469 event_free(gpu, event);
a8c21a54
T		 1470 }
1471
a8c21a54
T		 1472 ret = IRQ_HANDLED;
1473 }
1474
1475 return ret;
1476}
1477
1478static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu)
1479{
1480 int ret;
1481
65f037e8
LS		 1482 if (gpu->clk_reg) {
1483 ret = clk_prepare_enable(gpu->clk_reg);
1484 if (ret)
1485 return ret;
1486 }
1487
9c7310c0
LS		 1488 if (gpu->clk_bus) {
1489 ret = clk_prepare_enable(gpu->clk_bus);
1490 if (ret)
1491 return ret;
1492 }
a8c21a54 1493
9c7310c0
LS		 1494 if (gpu->clk_core) {
1495 ret = clk_prepare_enable(gpu->clk_core);
1496 if (ret)
1497 goto disable_clk_bus;
1498 }
1499
1500 if (gpu->clk_shader) {
1501 ret = clk_prepare_enable(gpu->clk_shader);
1502 if (ret)
1503 goto disable_clk_core;
a8c21a54
T		 1504 }
1505
1506 return 0;
9c7310c0
LS		 1507
1508disable_clk_core:
1509 if (gpu->clk_core)
1510 clk_disable_unprepare(gpu->clk_core);
1511disable_clk_bus:
1512 if (gpu->clk_bus)
1513 clk_disable_unprepare(gpu->clk_bus);
1514
1515 return ret;
a8c21a54
T		 1516}
1517
1518static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu)
1519{
9c7310c0
LS		 1520 if (gpu->clk_shader)
1521 clk_disable_unprepare(gpu->clk_shader);
1522 if (gpu->clk_core)
1523 clk_disable_unprepare(gpu->clk_core);
1524 if (gpu->clk_bus)
1525 clk_disable_unprepare(gpu->clk_bus);
65f037e8
LS		 1526 if (gpu->clk_reg)
1527 clk_disable_unprepare(gpu->clk_reg);
a8c21a54
T		 1528
1529 return 0;
1530}
1531
b88163e3
LS		 1532int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms)
1533{
1534 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
1535
1536 do {
1537 u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
1538
1539 if ((idle & gpu->idle_mask) == gpu->idle_mask)
1540 return 0;
1541
1542 if (time_is_before_jiffies(timeout)) {
1543 dev_warn(gpu->dev,
1544 "timed out waiting for idle: idle=0x%x\n",
1545 idle);
1546 return -ETIMEDOUT;
1547 }
1548
1549 udelay(5);
1550 } while (1);
1551}
1552
a8c21a54
T		 1553static int etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu)
1554{
17e4660a 1555 if (gpu->initialized && gpu->mmu_context) {
a8c21a54 1556 /* Replace the last WAIT with END */
40c27bde 1557 mutex_lock(&gpu->lock);
a8c21a54 1558 etnaviv_buffer_end(gpu);
40c27bde 1559 mutex_unlock(&gpu->lock);
a8c21a54
T		 1560
1561 /*
1562 * We know that only the FE is busy here, this should
1563 * happen quickly (as the WAIT is only 200 cycles). If
1564 * we fail, just warn and continue.
1565 */
b88163e3 1566 etnaviv_gpu_wait_idle(gpu, 100);
17e4660a
LS		 1567
1568 etnaviv_iommu_context_put(gpu->mmu_context);
1569 gpu->mmu_context = NULL;
a8c21a54
T		 1570 }
1571
17e4660a
LS		 1572 gpu->exec_state = -1;
1573
a8c21a54
T		 1574 return etnaviv_gpu_clk_disable(gpu);
1575}
1576
1577#ifdef CONFIG_PM
1578static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu)
1579{
a8c21a54
T		 1580 int ret;
1581
1582 ret = mutex_lock_killable(&gpu->lock);
1583 if (ret)
1584 return ret;
1585
bcdfb5e5 1586 etnaviv_gpu_update_clock(gpu);
a8c21a54
T		 1587 etnaviv_gpu_hw_init(gpu);
1588
a8c21a54
T		 1589 mutex_unlock(&gpu->lock);
1590
1591 return 0;
1592}
1593#endif
1594
bcdfb5e5
RK		 1595static int
1596etnaviv_gpu_cooling_get_max_state(struct thermal_cooling_device *cdev,
1597 unsigned long *state)
1598{
1599 *state = 6;
1600
1601 return 0;
1602}
1603
1604static int
1605etnaviv_gpu_cooling_get_cur_state(struct thermal_cooling_device *cdev,
1606 unsigned long *state)
1607{
1608 struct etnaviv_gpu *gpu = cdev->devdata;
1609
1610 *state = gpu->freq_scale;
1611
1612 return 0;
1613}
1614
1615static int
1616etnaviv_gpu_cooling_set_cur_state(struct thermal_cooling_device *cdev,
1617 unsigned long state)
1618{
1619 struct etnaviv_gpu *gpu = cdev->devdata;
1620
1621 mutex_lock(&gpu->lock);
1622 gpu->freq_scale = state;
1623 if (!pm_runtime_suspended(gpu->dev))
1624 etnaviv_gpu_update_clock(gpu);
1625 mutex_unlock(&gpu->lock);
1626
1627 return 0;
1628}
1629
1630static struct thermal_cooling_device_ops cooling_ops = {
1631 .get_max_state = etnaviv_gpu_cooling_get_max_state,
1632 .get_cur_state = etnaviv_gpu_cooling_get_cur_state,
1633 .set_cur_state = etnaviv_gpu_cooling_set_cur_state,
1634};
1635
a8c21a54
T		 1636static int etnaviv_gpu_bind(struct device *dev, struct device *master,
1637 void *data)
1638{
1639 struct drm_device *drm = data;
1640 struct etnaviv_drm_private *priv = drm->dev_private;
1641 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1642 int ret;
1643
49b82c38 1644 if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL)) {
5247e2aa 1645 gpu->cooling = thermal_of_cooling_device_register(dev->of_node,
bcdfb5e5 1646 (char *)dev_name(dev), gpu, &cooling_ops);
5247e2aa
LS		 1647 if (IS_ERR(gpu->cooling))
1648 return PTR_ERR(gpu->cooling);
1649 }
bcdfb5e5 1650
a7790d78
LS		 1651 gpu->wq = alloc_ordered_workqueue(dev_name(dev), 0);
1652 if (!gpu->wq) {
e93b6dee
LS		 1653 ret = -ENOMEM;
1654 goto out_thermal;
a7790d78
LS		 1655 }
1656
e93b6dee
LS		 1657 ret = etnaviv_sched_init(gpu);
1658 if (ret)
1659 goto out_workqueue;
1660
a8c21a54
T		 1661#ifdef CONFIG_PM
1662 ret = pm_runtime_get_sync(gpu->dev);
1663#else
1664 ret = etnaviv_gpu_clk_enable(gpu);
1665#endif
e93b6dee
LS		 1666 if (ret < 0)
1667 goto out_sched;
1668
a8c21a54
T		 1669
1670 gpu->drm = drm;
f54d1867 1671 gpu->fence_context = dma_fence_context_alloc(1);
8bc4d885 1672 idr_init(&gpu->fence_idr);
a8c21a54
T		 1673 spin_lock_init(&gpu->fence_spinlock);
1674
357713ce 1675 INIT_WORK(&gpu->sync_point_work, sync_point_worker);
a8c21a54
T		 1676 init_waitqueue_head(&gpu->fence_event);
1677
a8c21a54
T		 1678 priv->gpu[priv->num_gpus++] = gpu;
1679
1680 pm_runtime_mark_last_busy(gpu->dev);
1681 pm_runtime_put_autosuspend(gpu->dev);
1682
1683 return 0;
e93b6dee
LS		 1684
1685out_sched:
1686 etnaviv_sched_fini(gpu);
1687
1688out_workqueue:
1689 destroy_workqueue(gpu->wq);
1690
1691out_thermal:
1692 if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL))
1693 thermal_cooling_device_unregister(gpu->cooling);
1694
1695 return ret;
a8c21a54
T		 1696}
1697
1698static void etnaviv_gpu_unbind(struct device *dev, struct device *master,
1699 void *data)
1700{
1701 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1702
1703 DBG("%s", dev_name(gpu->dev));
1704
a7790d78
LS		 1705 flush_workqueue(gpu->wq);
1706 destroy_workqueue(gpu->wq);
1707
e93b6dee
LS		 1708 etnaviv_sched_fini(gpu);
1709
a8c21a54
T		 1710#ifdef CONFIG_PM
1711 pm_runtime_get_sync(gpu->dev);
1712 pm_runtime_put_sync_suspend(gpu->dev);
1713#else
1714 etnaviv_gpu_hw_suspend(gpu);
1715#endif
1716
db41fe7d 1717 if (gpu->initialized) {
2f9225db 1718 etnaviv_cmdbuf_free(&gpu->buffer);
27b67278 1719 etnaviv_iommu_global_fini(gpu);
db41fe7d 1720 gpu->initialized = false;
a8c21a54
T		 1721 }
1722
1723 gpu->drm = NULL;
8bc4d885 1724 idr_destroy(&gpu->fence_idr);
bcdfb5e5 1725
49b82c38
PZ		 1726 if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL))
1727 thermal_cooling_device_unregister(gpu->cooling);
bcdfb5e5 1728 gpu->cooling = NULL;
a8c21a54
T		 1729}
1730
1731static const struct component_ops gpu_ops = {
1732 .bind = etnaviv_gpu_bind,
1733 .unbind = etnaviv_gpu_unbind,
1734};
1735
1736static const struct of_device_id etnaviv_gpu_match[] = {
1737 {
1738 .compatible = "vivante,gc"
1739 },
1740 { /* sentinel */ }
1741};
246774d1 1742MODULE_DEVICE_TABLE(of, etnaviv_gpu_match);
a8c21a54
T		 1743
1744static int etnaviv_gpu_platform_probe(struct platform_device *pdev)
1745{
1746 struct device *dev = &pdev->dev;
1747 struct etnaviv_gpu *gpu;
dc227890 1748 int err;
a8c21a54
T		 1749
1750 gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL);
1751 if (!gpu)
1752 return -ENOMEM;
1753
1754 gpu->dev = &pdev->dev;
1755 mutex_init(&gpu->lock);
a0780bb1 1756 mutex_init(&gpu->fence_lock);
a8c21a54 1757
a8c21a54 1758 /* Map registers: */
facb180d 1759 gpu->mmio = devm_platform_ioremap_resource(pdev, 0);
a8c21a54
T		 1760 if (IS_ERR(gpu->mmio))
1761 return PTR_ERR(gpu->mmio);
1762
1763 /* Get Interrupt: */
1764 gpu->irq = platform_get_irq(pdev, 0);
1765 if (gpu->irq < 0) {
db60eda3
FE		 1766 dev_err(dev, "failed to get irq: %d\n", gpu->irq);
1767 return gpu->irq;
a8c21a54
T		 1768 }
1769
1770 err = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 0,
1771 dev_name(gpu->dev), gpu);
1772 if (err) {
1773 dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err);
db60eda3 1774 return err;
a8c21a54
T		 1775 }
1776
1777 /* Get Clocks: */
65f037e8
LS		 1778 gpu->clk_reg = devm_clk_get(&pdev->dev, "reg");
1779 DBG("clk_reg: %p", gpu->clk_reg);
1780 if (IS_ERR(gpu->clk_reg))
1781 gpu->clk_reg = NULL;
1782
a8c21a54
T		 1783 gpu->clk_bus = devm_clk_get(&pdev->dev, "bus");
1784 DBG("clk_bus: %p", gpu->clk_bus);
1785 if (IS_ERR(gpu->clk_bus))
1786 gpu->clk_bus = NULL;
1787
1788 gpu->clk_core = devm_clk_get(&pdev->dev, "core");
1789 DBG("clk_core: %p", gpu->clk_core);
1790 if (IS_ERR(gpu->clk_core))
1791 gpu->clk_core = NULL;
d79fd1cc 1792 gpu->base_rate_core = clk_get_rate(gpu->clk_core);
a8c21a54
T		 1793
1794 gpu->clk_shader = devm_clk_get(&pdev->dev, "shader");
1795 DBG("clk_shader: %p", gpu->clk_shader);
1796 if (IS_ERR(gpu->clk_shader))
1797 gpu->clk_shader = NULL;
d79fd1cc 1798 gpu->base_rate_shader = clk_get_rate(gpu->clk_shader);
a8c21a54
T		 1799
1800 /* TODO: figure out max mapped size */
1801 dev_set_drvdata(dev, gpu);
1802
1803 /*
1804 * We treat the device as initially suspended. The runtime PM
1805 * autosuspend delay is rather arbitary: no measurements have
1806 * yet been performed to determine an appropriate value.
1807 */
1808 pm_runtime_use_autosuspend(gpu->dev);
1809 pm_runtime_set_autosuspend_delay(gpu->dev, 200);
1810 pm_runtime_enable(gpu->dev);
1811
1812 err = component_add(&pdev->dev, &gpu_ops);
1813 if (err < 0) {
1814 dev_err(&pdev->dev, "failed to register component: %d\n", err);
db60eda3 1815 return err;
a8c21a54
T		 1816 }
1817
1818 return 0;
a8c21a54
T		 1819}
1820
1821static int etnaviv_gpu_platform_remove(struct platform_device *pdev)
1822{
1823 component_del(&pdev->dev, &gpu_ops);
1824 pm_runtime_disable(&pdev->dev);
1825 return 0;
1826}
1827
1828#ifdef CONFIG_PM
1829static int etnaviv_gpu_rpm_suspend(struct device *dev)
1830{
1831 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1832 u32 idle, mask;
1833
f4163814
LS		 1834 /* If there are any jobs in the HW queue, we're not idle */
1835 if (atomic_read(&gpu->sched.hw_rq_count))
a8c21a54
T		 1836 return -EBUSY;
1837
1a910c11
GG		 1838 /* Check whether the hardware (except FE and MC) is idle */
1839 mask = gpu->idle_mask & ~(VIVS_HI_IDLE_STATE_FE |
1840 VIVS_HI_IDLE_STATE_MC);
a8c21a54
T		 1841 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask;
1842 if (idle != mask)
1843 return -EBUSY;
1844
1845 return etnaviv_gpu_hw_suspend(gpu);
1846}
1847
1848static int etnaviv_gpu_rpm_resume(struct device *dev)
1849{
1850 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1851 int ret;
1852
1853 ret = etnaviv_gpu_clk_enable(gpu);
1854 if (ret)
1855 return ret;
1856
1857 /* Re-initialise the basic hardware state */
db41fe7d 1858 if (gpu->drm && gpu->initialized) {
a8c21a54
T		 1859 ret = etnaviv_gpu_hw_resume(gpu);
1860 if (ret) {
1861 etnaviv_gpu_clk_disable(gpu);
1862 return ret;
1863 }
1864 }
1865
1866 return 0;
1867}
1868#endif
1869
1870static const struct dev_pm_ops etnaviv_gpu_pm_ops = {
1871 SET_RUNTIME_PM_OPS(etnaviv_gpu_rpm_suspend, etnaviv_gpu_rpm_resume,
1872 NULL)
1873};
1874
1875struct platform_driver etnaviv_gpu_driver = {
1876 .driver = {
1877 .name = "etnaviv-gpu",
1878 .owner = THIS_MODULE,
1879 .pm = &etnaviv_gpu_pm_ops,
1880 .of_match_table = etnaviv_gpu_match,
1881 },
1882 .probe = etnaviv_gpu_platform_probe,
1883 .remove = etnaviv_gpu_platform_remove,
1884 .id_table = gpu_ids,
1885};
Linux 6.x block layer and io_uring tree(s)