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Merge tag 'pci-v6.16-fixes-3' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci
[linux-2.6-block.git] / drivers / gpu / drm / drm_edid.c
CommitLineData
f453ba04
DA		 1/*
2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
61e57a8d 5 * Copyright 2010 Red Hat, Inc.
f453ba04
DA		 6 *
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
8 * FB layer.
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 */
9c79edec 30
18a9cbbe 31#include <linux/bitfield.h>
3f56e551 32#include <linux/byteorder/generic.h>
82b599ec 33#include <linux/cec.h>
10a85120 34#include <linux/hdmi.h>
f453ba04 35#include <linux/i2c.h>
9c79edec 36#include <linux/kernel.h>
47819ba2 37#include <linux/module.h>
36b73b05 38#include <linux/pci.h>
3f56e551 39#include <linux/seq_buf.h>
9c79edec 40#include <linux/slab.h>
5cb8eaa2 41#include <linux/vga_switcheroo.h>
9c79edec 42
9c79edec 43#include <drm/drm_drv.h>
760285e7 44#include <drm/drm_edid.h>
439590ac 45#include <drm/drm_eld.h>
9338203c 46#include <drm/drm_encoder.h>
9c79edec 47#include <drm/drm_print.h>
f453ba04 48
969218fe 49#include "drm_crtc_internal.h"
44e030d8 50#include "drm_displayid_internal.h"
8af46811 51#include "drm_internal.h"
969218fe 52
37eab1fe
JN		 53static int oui(u8 first, u8 second, u8 third)
54{
55 return (first << 16) | (second << 8) | third;
56}
57
d1ff6409
AJ		 58#define EDID_EST_TIMINGS 16
59#define EDID_STD_TIMINGS 8
60#define EDID_DETAILED_TIMINGS 4
f453ba04
DA		 61
62/*
63 * EDID blocks out in the wild have a variety of bugs, try to collect
64 * them here (note that userspace may work around broken monitors first,
65 * but fixes should make their way here so that the kernel "just works"
66 * on as many displays as possible).
67 */
68
69/* First detailed mode wrong, use largest 60Hz mode */
70#define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
71/* Reported 135MHz pixel clock is too high, needs adjustment */
72#define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
73/* Prefer the largest mode at 75 Hz */
74#define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
75/* Detail timing is in cm not mm */
76#define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
77/* Detailed timing descriptors have bogus size values, so just take the
78 * maximum size and use that.
79 */
80#define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
f453ba04
DA		 81/* use +hsync +vsync for detailed mode */
82#define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
bc42aabc
AJ		 83/* Force reduced-blanking timings for detailed modes */
84#define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
49d45a31
RM		 85/* Force 8bpc */
86#define EDID_QUIRK_FORCE_8BPC (1 << 8)
bc5b9641
MK		 87/* Force 12bpc */
88#define EDID_QUIRK_FORCE_12BPC (1 << 9)
e10aec65
MK		 89/* Force 6bpc */
90#define EDID_QUIRK_FORCE_6BPC (1 << 10)
e345da82
MK		 91/* Force 10bpc */
92#define EDID_QUIRK_FORCE_10BPC (1 << 11)
66660d4c
DA		 93/* Non desktop display (i.e. HMD) */
94#define EDID_QUIRK_NON_DESKTOP (1 << 12)
aa193f7e
HM		 95/* Cap the DSC target bitrate to 15bpp */
96#define EDID_QUIRK_CAP_DSC_15BPP (1 << 13)
3c537889 97
2869f599
PZ		 98#define MICROSOFT_IEEE_OUI 0xca125c
99
13931579
AJ		 100struct detailed_mode_closure {
101 struct drm_connector *connector;
dd0f4470 102 const struct drm_edid *drm_edid;
13931579 103 bool preferred;
13931579
AJ		 104 int modes;
105};
f453ba04 106
6e3fdedc
HYW		 107struct drm_edid_match_closure {
108 const struct drm_edid_ident *ident;
109 bool matched;
110};
111
5c61259e
ZY		 112#define LEVEL_DMT 0
113#define LEVEL_GTF 1
7a374350
AJ		 114#define LEVEL_GTF2 2
115#define LEVEL_CVT 3
5c61259e 116
7d1be0a0 117#define EDID_QUIRK(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _quirks) \
e8de4d55 118{ \
7ff53c2f
HYW		 119 .ident = { \
120 .panel_id = drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, \
121 vend_chr_2, product_id), \
122 }, \
e8de4d55
DA		 123 .quirks = _quirks \
124}
125
23c4cfbd 126static const struct edid_quirk {
7ff53c2f 127 const struct drm_edid_ident ident;
f453ba04
DA		 128 u32 quirks;
129} edid_quirk_list[] = {
130 /* Acer AL1706 */
7d1be0a0 131 EDID_QUIRK('A', 'C', 'R', 44358, EDID_QUIRK_PREFER_LARGE_60),
f453ba04 132 /* Acer F51 */
7d1be0a0 133 EDID_QUIRK('A', 'P', 'I', 0x7602, EDID_QUIRK_PREFER_LARGE_60),
f453ba04 134
e10aec65 135 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
7d1be0a0 136 EDID_QUIRK('A', 'E', 'O', 0, EDID_QUIRK_FORCE_6BPC),
e10aec65 137
88630e91
HM		 138 /* BenQ GW2765 */
139 EDID_QUIRK('B', 'N', 'Q', 0x78d6, EDID_QUIRK_FORCE_8BPC),
140
0711a43b 141 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
7d1be0a0 142 EDID_QUIRK('B', 'O', 'E', 0x78b, EDID_QUIRK_FORCE_6BPC),
0711a43b 143
06998a75 144 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
7d1be0a0 145 EDID_QUIRK('C', 'P', 'T', 0x17df, EDID_QUIRK_FORCE_6BPC),
06998a75 146
25da7504 147 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
7d1be0a0 148 EDID_QUIRK('S', 'D', 'C', 0x3652, EDID_QUIRK_FORCE_6BPC),
25da7504 149
922dceff 150 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
7d1be0a0 151 EDID_QUIRK('B', 'O', 'E', 0x0771, EDID_QUIRK_FORCE_6BPC),
922dceff 152
f453ba04 153 /* Belinea 10 15 55 */
7d1be0a0
DA		 154 EDID_QUIRK('M', 'A', 'X', 1516, EDID_QUIRK_PREFER_LARGE_60),
155 EDID_QUIRK('M', 'A', 'X', 0x77e, EDID_QUIRK_PREFER_LARGE_60),
f453ba04
DA		 156
157 /* Envision Peripherals, Inc. EN-7100e */
7d1be0a0 158 EDID_QUIRK('E', 'P', 'I', 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH),
ba1163de 159 /* Envision EN2028 */
7d1be0a0 160 EDID_QUIRK('E', 'P', 'I', 8232, EDID_QUIRK_PREFER_LARGE_60),
f453ba04
DA		 161
162 /* Funai Electronics PM36B */
7d1be0a0 163 EDID_QUIRK('F', 'C', 'M', 13600, EDID_QUIRK_PREFER_LARGE_75 |
e8de4d55 164 EDID_QUIRK_DETAILED_IN_CM),
f453ba04 165
aa193f7e
HM		 166 /* LG 27GP950 */
167 EDID_QUIRK('G', 'S', 'M', 0x5bbf, EDID_QUIRK_CAP_DSC_15BPP),
168
169 /* LG 27GN950 */
170 EDID_QUIRK('G', 'S', 'M', 0x5b9a, EDID_QUIRK_CAP_DSC_15BPP),
171
e345da82 172 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
7d1be0a0 173 EDID_QUIRK('L', 'G', 'D', 764, EDID_QUIRK_FORCE_10BPC),
e345da82 174
f453ba04 175 /* LG Philips LCD LP154W01-A5 */
7d1be0a0
DA		 176 EDID_QUIRK('L', 'P', 'L', 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
177 EDID_QUIRK('L', 'P', 'L', 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
f453ba04 178
f453ba04 179 /* Samsung SyncMaster 205BW. Note: irony */
7d1be0a0 180 EDID_QUIRK('S', 'A', 'M', 541, EDID_QUIRK_DETAILED_SYNC_PP),
f453ba04 181 /* Samsung SyncMaster 22[5-6]BW */
7d1be0a0
DA		 182 EDID_QUIRK('S', 'A', 'M', 596, EDID_QUIRK_PREFER_LARGE_60),
183 EDID_QUIRK('S', 'A', 'M', 638, EDID_QUIRK_PREFER_LARGE_60),
bc42aabc 184
bc5b9641 185 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
7d1be0a0 186 EDID_QUIRK('S', 'N', 'Y', 0x2541, EDID_QUIRK_FORCE_12BPC),
bc5b9641 187
bc42aabc 188 /* ViewSonic VA2026w */
7d1be0a0 189 EDID_QUIRK('V', 'S', 'C', 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING),
118bdbd8
AD		 190
191 /* Medion MD 30217 PG */
7d1be0a0 192 EDID_QUIRK('M', 'E', 'D', 0x7b8, EDID_QUIRK_PREFER_LARGE_75),
49d45a31 193
11bcf5f7 194 /* Lenovo G50 */
7d1be0a0 195 EDID_QUIRK('S', 'D', 'C', 18514, EDID_QUIRK_FORCE_6BPC),
11bcf5f7 196
49d45a31 197 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
7d1be0a0 198 EDID_QUIRK('S', 'E', 'C', 0xd033, EDID_QUIRK_FORCE_8BPC),
36fc5797
TV		 199
200 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
7d1be0a0 201 EDID_QUIRK('E', 'T', 'R', 13896, EDID_QUIRK_FORCE_8BPC),
acb1d8ee 202
30d62d44 203 /* Valve Index Headset */
7d1be0a0
DA		 204 EDID_QUIRK('V', 'L', 'V', 0x91a8, EDID_QUIRK_NON_DESKTOP),
205 EDID_QUIRK('V', 'L', 'V', 0x91b0, EDID_QUIRK_NON_DESKTOP),
206 EDID_QUIRK('V', 'L', 'V', 0x91b1, EDID_QUIRK_NON_DESKTOP),
207 EDID_QUIRK('V', 'L', 'V', 0x91b2, EDID_QUIRK_NON_DESKTOP),
208 EDID_QUIRK('V', 'L', 'V', 0x91b3, EDID_QUIRK_NON_DESKTOP),
209 EDID_QUIRK('V', 'L', 'V', 0x91b4, EDID_QUIRK_NON_DESKTOP),
210 EDID_QUIRK('V', 'L', 'V', 0x91b5, EDID_QUIRK_NON_DESKTOP),
211 EDID_QUIRK('V', 'L', 'V', 0x91b6, EDID_QUIRK_NON_DESKTOP),
212 EDID_QUIRK('V', 'L', 'V', 0x91b7, EDID_QUIRK_NON_DESKTOP),
213 EDID_QUIRK('V', 'L', 'V', 0x91b8, EDID_QUIRK_NON_DESKTOP),
214 EDID_QUIRK('V', 'L', 'V', 0x91b9, EDID_QUIRK_NON_DESKTOP),
215 EDID_QUIRK('V', 'L', 'V', 0x91ba, EDID_QUIRK_NON_DESKTOP),
216 EDID_QUIRK('V', 'L', 'V', 0x91bb, EDID_QUIRK_NON_DESKTOP),
217 EDID_QUIRK('V', 'L', 'V', 0x91bc, EDID_QUIRK_NON_DESKTOP),
218 EDID_QUIRK('V', 'L', 'V', 0x91bd, EDID_QUIRK_NON_DESKTOP),
219 EDID_QUIRK('V', 'L', 'V', 0x91be, EDID_QUIRK_NON_DESKTOP),
220 EDID_QUIRK('V', 'L', 'V', 0x91bf, EDID_QUIRK_NON_DESKTOP),
30d62d44 221
6931317c 222 /* HTC Vive and Vive Pro VR Headsets */
7d1be0a0
DA		 223 EDID_QUIRK('H', 'V', 'R', 0xaa01, EDID_QUIRK_NON_DESKTOP),
224 EDID_QUIRK('H', 'V', 'R', 0xaa02, EDID_QUIRK_NON_DESKTOP),
b3b12ea3 225
5a3f6108 226 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */
7d1be0a0
DA		 227 EDID_QUIRK('O', 'V', 'R', 0x0001, EDID_QUIRK_NON_DESKTOP),
228 EDID_QUIRK('O', 'V', 'R', 0x0003, EDID_QUIRK_NON_DESKTOP),
229 EDID_QUIRK('O', 'V', 'R', 0x0004, EDID_QUIRK_NON_DESKTOP),
230 EDID_QUIRK('O', 'V', 'R', 0x0012, EDID_QUIRK_NON_DESKTOP),
90eda8fc
PZ		 231
232 /* Windows Mixed Reality Headsets */
7d1be0a0 233 EDID_QUIRK('A', 'C', 'R', 0x7fce, EDID_QUIRK_NON_DESKTOP),
7d1be0a0 234 EDID_QUIRK('L', 'E', 'N', 0x0408, EDID_QUIRK_NON_DESKTOP),
7d1be0a0
DA		 235 EDID_QUIRK('F', 'U', 'J', 0x1970, EDID_QUIRK_NON_DESKTOP),
236 EDID_QUIRK('D', 'E', 'L', 0x7fce, EDID_QUIRK_NON_DESKTOP),
237 EDID_QUIRK('S', 'E', 'C', 0x144a, EDID_QUIRK_NON_DESKTOP),
238 EDID_QUIRK('A', 'U', 'S', 0xc102, EDID_QUIRK_NON_DESKTOP),
ccffc9eb
PZ		 239
240 /* Sony PlayStation VR Headset */
7d1be0a0 241 EDID_QUIRK('S', 'N', 'Y', 0x0704, EDID_QUIRK_NON_DESKTOP),
29054230
RP		 242
243 /* Sensics VR Headsets */
7d1be0a0 244 EDID_QUIRK('S', 'E', 'N', 0x1019, EDID_QUIRK_NON_DESKTOP),
29054230
RP		 245
246 /* OSVR HDK and HDK2 VR Headsets */
7d1be0a0 247 EDID_QUIRK('S', 'V', 'R', 0x1019, EDID_QUIRK_NON_DESKTOP),
98d4cb70 248 EDID_QUIRK('A', 'U', 'O', 0x1111, EDID_QUIRK_NON_DESKTOP),
f453ba04
DA		 249};
250
a6b21831
TR		 251/*
252 * Autogenerated from the DMT spec.
253 * This table is copied from xfree86/modes/xf86EdidModes.c.
254 */
255static const struct drm_display_mode drm_dmt_modes[] = {
24b856b1 256 /* 0x01 - 640x350@85Hz */
a6b21831
TR		 257 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
258 736, 832, 0, 350, 382, 385, 445, 0,
259 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 260 /* 0x02 - 640x400@85Hz */
a6b21831
TR		 261 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
262 736, 832, 0, 400, 401, 404, 445, 0,
263 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 264 /* 0x03 - 720x400@85Hz */
a6b21831
TR		 265 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
266 828, 936, 0, 400, 401, 404, 446, 0,
267 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 268 /* 0x04 - 640x480@60Hz */
a6b21831 269 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
fcf22d05 270 752, 800, 0, 480, 490, 492, 525, 0,
a6b21831 271 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 272 /* 0x05 - 640x480@72Hz */
a6b21831
TR		 273 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
274 704, 832, 0, 480, 489, 492, 520, 0,
275 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 276 /* 0x06 - 640x480@75Hz */
a6b21831
TR		 277 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
278 720, 840, 0, 480, 481, 484, 500, 0,
279 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 280 /* 0x07 - 640x480@85Hz */
a6b21831
TR		 281 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
282 752, 832, 0, 480, 481, 484, 509, 0,
283 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 284 /* 0x08 - 800x600@56Hz */
a6b21831
TR		 285 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
286 896, 1024, 0, 600, 601, 603, 625, 0,
287 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 288 /* 0x09 - 800x600@60Hz */
a6b21831
TR		 289 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
290 968, 1056, 0, 600, 601, 605, 628, 0,
291 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 292 /* 0x0a - 800x600@72Hz */
a6b21831
TR		 293 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
294 976, 1040, 0, 600, 637, 643, 666, 0,
295 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 296 /* 0x0b - 800x600@75Hz */
a6b21831
TR		 297 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
298 896, 1056, 0, 600, 601, 604, 625, 0,
299 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 300 /* 0x0c - 800x600@85Hz */
a6b21831
TR		 301 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
302 896, 1048, 0, 600, 601, 604, 631, 0,
303 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 304 /* 0x0d - 800x600@120Hz RB */
a6b21831
TR		 305 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
306 880, 960, 0, 600, 603, 607, 636, 0,
307 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 308 /* 0x0e - 848x480@60Hz */
a6b21831
TR		 309 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
310 976, 1088, 0, 480, 486, 494, 517, 0,
311 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 312 /* 0x0f - 1024x768@43Hz, interlace */
a6b21831 313 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
735b100f 314 1208, 1264, 0, 768, 768, 776, 817, 0,
a6b21831 315 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
fcf22d05 316 DRM_MODE_FLAG_INTERLACE) },
24b856b1 317 /* 0x10 - 1024x768@60Hz */
a6b21831
TR		 318 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
319 1184, 1344, 0, 768, 771, 777, 806, 0,
320 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 321 /* 0x11 - 1024x768@70Hz */
a6b21831
TR		 322 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
323 1184, 1328, 0, 768, 771, 777, 806, 0,
324 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 325 /* 0x12 - 1024x768@75Hz */
a6b21831
TR		 326 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
327 1136, 1312, 0, 768, 769, 772, 800, 0,
328 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 329 /* 0x13 - 1024x768@85Hz */
a6b21831
TR		 330 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
331 1168, 1376, 0, 768, 769, 772, 808, 0,
332 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 333 /* 0x14 - 1024x768@120Hz RB */
a6b21831
TR		 334 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
335 1104, 1184, 0, 768, 771, 775, 813, 0,
336 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 337 /* 0x15 - 1152x864@75Hz */
a6b21831
TR		 338 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
339 1344, 1600, 0, 864, 865, 868, 900, 0,
340 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
bfcd74d2
VS		 341 /* 0x55 - 1280x720@60Hz */
342 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
343 1430, 1650, 0, 720, 725, 730, 750, 0,
344 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 345 /* 0x16 - 1280x768@60Hz RB */
a6b21831
TR		 346 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
347 1360, 1440, 0, 768, 771, 778, 790, 0,
348 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 349 /* 0x17 - 1280x768@60Hz */
a6b21831
TR		 350 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
351 1472, 1664, 0, 768, 771, 778, 798, 0,
352 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 353 /* 0x18 - 1280x768@75Hz */
a6b21831
TR		 354 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
355 1488, 1696, 0, 768, 771, 778, 805, 0,
fcf22d05 356 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 357 /* 0x19 - 1280x768@85Hz */
a6b21831
TR		 358 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
359 1496, 1712, 0, 768, 771, 778, 809, 0,
360 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 361 /* 0x1a - 1280x768@120Hz RB */
a6b21831
TR		 362 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
363 1360, 1440, 0, 768, 771, 778, 813, 0,
364 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 365 /* 0x1b - 1280x800@60Hz RB */
a6b21831
TR		 366 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
367 1360, 1440, 0, 800, 803, 809, 823, 0,
368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 369 /* 0x1c - 1280x800@60Hz */
a6b21831
TR		 370 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
371 1480, 1680, 0, 800, 803, 809, 831, 0,
fcf22d05 372 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 373 /* 0x1d - 1280x800@75Hz */
a6b21831
TR		 374 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
375 1488, 1696, 0, 800, 803, 809, 838, 0,
376 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 377 /* 0x1e - 1280x800@85Hz */
a6b21831
TR		 378 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
379 1496, 1712, 0, 800, 803, 809, 843, 0,
380 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 381 /* 0x1f - 1280x800@120Hz RB */
a6b21831
TR		 382 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
383 1360, 1440, 0, 800, 803, 809, 847, 0,
384 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 385 /* 0x20 - 1280x960@60Hz */
a6b21831
TR		 386 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
387 1488, 1800, 0, 960, 961, 964, 1000, 0,
388 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 389 /* 0x21 - 1280x960@85Hz */
a6b21831
TR		 390 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
391 1504, 1728, 0, 960, 961, 964, 1011, 0,
392 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 393 /* 0x22 - 1280x960@120Hz RB */
a6b21831
TR		 394 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
395 1360, 1440, 0, 960, 963, 967, 1017, 0,
396 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 397 /* 0x23 - 1280x1024@60Hz */
a6b21831
TR		 398 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
399 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
400 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 401 /* 0x24 - 1280x1024@75Hz */
a6b21831
TR		 402 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
403 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
404 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 405 /* 0x25 - 1280x1024@85Hz */
a6b21831
TR		 406 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
407 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
408 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 409 /* 0x26 - 1280x1024@120Hz RB */
a6b21831
TR		 410 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
411 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
412 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 413 /* 0x27 - 1360x768@60Hz */
a6b21831
TR		 414 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
415 1536, 1792, 0, 768, 771, 777, 795, 0,
416 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 417 /* 0x28 - 1360x768@120Hz RB */
a6b21831
TR		 418 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
419 1440, 1520, 0, 768, 771, 776, 813, 0,
420 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 421 /* 0x51 - 1366x768@60Hz */
422 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
423 1579, 1792, 0, 768, 771, 774, 798, 0,
424 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
425 /* 0x56 - 1366x768@60Hz */
426 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
427 1436, 1500, 0, 768, 769, 772, 800, 0,
428 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 429 /* 0x29 - 1400x1050@60Hz RB */
a6b21831
TR		 430 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
431 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
432 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 433 /* 0x2a - 1400x1050@60Hz */
a6b21831
TR		 434 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
435 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
436 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 437 /* 0x2b - 1400x1050@75Hz */
a6b21831
TR		 438 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
439 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
440 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 441 /* 0x2c - 1400x1050@85Hz */
a6b21831
TR		 442 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
443 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
444 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 445 /* 0x2d - 1400x1050@120Hz RB */
a6b21831
TR		 446 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
447 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
448 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 449 /* 0x2e - 1440x900@60Hz RB */
a6b21831
TR		 450 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
451 1520, 1600, 0, 900, 903, 909, 926, 0,
452 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 453 /* 0x2f - 1440x900@60Hz */
a6b21831
TR		 454 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
455 1672, 1904, 0, 900, 903, 909, 934, 0,
456 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 457 /* 0x30 - 1440x900@75Hz */
a6b21831
TR		 458 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
459 1688, 1936, 0, 900, 903, 909, 942, 0,
460 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 461 /* 0x31 - 1440x900@85Hz */
a6b21831
TR		 462 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
463 1696, 1952, 0, 900, 903, 909, 948, 0,
464 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 465 /* 0x32 - 1440x900@120Hz RB */
a6b21831
TR		 466 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
467 1520, 1600, 0, 900, 903, 909, 953, 0,
468 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 469 /* 0x53 - 1600x900@60Hz */
470 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
471 1704, 1800, 0, 900, 901, 904, 1000, 0,
472 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 473 /* 0x33 - 1600x1200@60Hz */
a6b21831
TR		 474 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
475 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
476 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 477 /* 0x34 - 1600x1200@65Hz */
a6b21831
TR		 478 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
479 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
480 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 481 /* 0x35 - 1600x1200@70Hz */
a6b21831
TR		 482 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
483 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
484 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 485 /* 0x36 - 1600x1200@75Hz */
a6b21831
TR		 486 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
487 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
488 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 489 /* 0x37 - 1600x1200@85Hz */
a6b21831
TR		 490 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
491 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
492 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 493 /* 0x38 - 1600x1200@120Hz RB */
a6b21831
TR		 494 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
495 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
496 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 497 /* 0x39 - 1680x1050@60Hz RB */
a6b21831
TR		 498 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
499 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
500 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 501 /* 0x3a - 1680x1050@60Hz */
a6b21831
TR		 502 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
503 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
504 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 505 /* 0x3b - 1680x1050@75Hz */
a6b21831
TR		 506 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
507 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
508 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 509 /* 0x3c - 1680x1050@85Hz */
a6b21831
TR		 510 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
511 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
512 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 513 /* 0x3d - 1680x1050@120Hz RB */
a6b21831
TR		 514 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
515 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
516 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 517 /* 0x3e - 1792x1344@60Hz */
a6b21831
TR		 518 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
519 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
520 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 521 /* 0x3f - 1792x1344@75Hz */
a6b21831
TR		 522 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
523 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
524 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 525 /* 0x40 - 1792x1344@120Hz RB */
a6b21831
TR		 526 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
527 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
528 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 529 /* 0x41 - 1856x1392@60Hz */
a6b21831
TR		 530 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
531 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
532 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 533 /* 0x42 - 1856x1392@75Hz */
a6b21831 534 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
fcf22d05 535 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
a6b21831 536 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 537 /* 0x43 - 1856x1392@120Hz RB */
a6b21831
TR		 538 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
539 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
540 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 541 /* 0x52 - 1920x1080@60Hz */
542 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
543 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
544 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 545 /* 0x44 - 1920x1200@60Hz RB */
a6b21831
TR		 546 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
547 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
548 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 549 /* 0x45 - 1920x1200@60Hz */
a6b21831
TR		 550 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
551 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
552 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 553 /* 0x46 - 1920x1200@75Hz */
a6b21831
TR		 554 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
555 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
556 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 557 /* 0x47 - 1920x1200@85Hz */
a6b21831
TR		 558 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
559 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
560 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 561 /* 0x48 - 1920x1200@120Hz RB */
a6b21831
TR		 562 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
563 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
564 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 565 /* 0x49 - 1920x1440@60Hz */
a6b21831
TR		 566 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
567 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
568 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 569 /* 0x4a - 1920x1440@75Hz */
a6b21831
TR		 570 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
571 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
572 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 573 /* 0x4b - 1920x1440@120Hz RB */
a6b21831
TR		 574 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
575 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
576 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 577 /* 0x54 - 2048x1152@60Hz */
578 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
579 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
580 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 581 /* 0x4c - 2560x1600@60Hz RB */
a6b21831
TR		 582 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
583 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
584 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 585 /* 0x4d - 2560x1600@60Hz */
a6b21831
TR		 586 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
587 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
588 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 589 /* 0x4e - 2560x1600@75Hz */
a6b21831
TR		 590 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
591 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
592 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 593 /* 0x4f - 2560x1600@85Hz */
a6b21831
TR		 594 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
595 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
596 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 597 /* 0x50 - 2560x1600@120Hz RB */
a6b21831
TR		 598 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
599 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
600 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 601 /* 0x57 - 4096x2160@60Hz RB */
602 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
603 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
604 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
605 /* 0x58 - 4096x2160@59.94Hz RB */
606 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
607 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
608 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
a6b21831
TR		 609};
610
e7bfa5c4
VS		 611/*
612 * These more or less come from the DMT spec. The 720x400 modes are
613 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
614 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
615 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
616 * mode.
617 *
618 * The DMT modes have been fact-checked; the rest are mild guesses.
619 */
a6b21831
TR		 620static const struct drm_display_mode edid_est_modes[] = {
621 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
622 968, 1056, 0, 600, 601, 605, 628, 0,
623 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
624 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
625 896, 1024, 0, 600, 601, 603, 625, 0,
626 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
627 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
628 720, 840, 0, 480, 481, 484, 500, 0,
629 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
630 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
87707cfd 631 704, 832, 0, 480, 489, 492, 520, 0,
a6b21831
TR		 632 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
633 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
634 768, 864, 0, 480, 483, 486, 525, 0,
635 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
87707cfd 636 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
a6b21831
TR		 637 752, 800, 0, 480, 490, 492, 525, 0,
638 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
639 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
640 846, 900, 0, 400, 421, 423, 449, 0,
641 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
642 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
643 846, 900, 0, 400, 412, 414, 449, 0,
644 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
645 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
646 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
647 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
87707cfd 648 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
a6b21831
TR		 649 1136, 1312, 0, 768, 769, 772, 800, 0,
650 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
651 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
652 1184, 1328, 0, 768, 771, 777, 806, 0,
653 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
654 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
655 1184, 1344, 0, 768, 771, 777, 806, 0,
656 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
657 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
658 1208, 1264, 0, 768, 768, 776, 817, 0,
659 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
660 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
661 928, 1152, 0, 624, 625, 628, 667, 0,
662 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
663 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
664 896, 1056, 0, 600, 601, 604, 625, 0,
665 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
666 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
667 976, 1040, 0, 600, 637, 643, 666, 0,
668 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
669 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
670 1344, 1600, 0, 864, 865, 868, 900, 0,
671 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
672};
673
674struct minimode {
675 short w;
676 short h;
677 short r;
678 short rb;
679};
680
681static const struct minimode est3_modes[] = {
682 /* byte 6 */
683 { 640, 350, 85, 0 },
684 { 640, 400, 85, 0 },
685 { 720, 400, 85, 0 },
686 { 640, 480, 85, 0 },
687 { 848, 480, 60, 0 },
688 { 800, 600, 85, 0 },
689 { 1024, 768, 85, 0 },
690 { 1152, 864, 75, 0 },
691 /* byte 7 */
692 { 1280, 768, 60, 1 },
693 { 1280, 768, 60, 0 },
694 { 1280, 768, 75, 0 },
695 { 1280, 768, 85, 0 },
696 { 1280, 960, 60, 0 },
697 { 1280, 960, 85, 0 },
698 { 1280, 1024, 60, 0 },
699 { 1280, 1024, 85, 0 },
700 /* byte 8 */
701 { 1360, 768, 60, 0 },
702 { 1440, 900, 60, 1 },
703 { 1440, 900, 60, 0 },
704 { 1440, 900, 75, 0 },
705 { 1440, 900, 85, 0 },
706 { 1400, 1050, 60, 1 },
707 { 1400, 1050, 60, 0 },
708 { 1400, 1050, 75, 0 },
709 /* byte 9 */
710 { 1400, 1050, 85, 0 },
711 { 1680, 1050, 60, 1 },
712 { 1680, 1050, 60, 0 },
713 { 1680, 1050, 75, 0 },
714 { 1680, 1050, 85, 0 },
715 { 1600, 1200, 60, 0 },
716 { 1600, 1200, 65, 0 },
717 { 1600, 1200, 70, 0 },
718 /* byte 10 */
719 { 1600, 1200, 75, 0 },
720 { 1600, 1200, 85, 0 },
721 { 1792, 1344, 60, 0 },
c068b32a 722 { 1792, 1344, 75, 0 },
a6b21831
TR		 723 { 1856, 1392, 60, 0 },
724 { 1856, 1392, 75, 0 },
725 { 1920, 1200, 60, 1 },
726 { 1920, 1200, 60, 0 },
727 /* byte 11 */
728 { 1920, 1200, 75, 0 },
729 { 1920, 1200, 85, 0 },
730 { 1920, 1440, 60, 0 },
731 { 1920, 1440, 75, 0 },
732};
733
734static const struct minimode extra_modes[] = {
735 { 1024, 576, 60, 0 },
736 { 1366, 768, 60, 0 },
737 { 1600, 900, 60, 0 },
738 { 1680, 945, 60, 0 },
739 { 1920, 1080, 60, 0 },
740 { 2048, 1152, 60, 0 },
741 { 2048, 1536, 60, 0 },
742};
743
744/*
7befe621 745 * From CEA/CTA-861 spec.
d9278b4c 746 *
7befe621 747 * Do not access directly, instead always use cea_mode_for_vic().
a6b21831 748 */
8c1b2bd9 749static const struct drm_display_mode edid_cea_modes_1[] = {
78691960 750 /* 1 - 640x480@60Hz 4:3 */
a6b21831
TR		 751 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
752 752, 800, 0, 480, 490, 492, 525, 0,
ee7925bb 753 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 754 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 755 /* 2 - 720x480@60Hz 4:3 */
a6b21831
TR		 756 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
757 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 758 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 759 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 760 /* 3 - 720x480@60Hz 16:9 */
a6b21831
TR		 761 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
762 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 763 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 764 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 765 /* 4 - 1280x720@60Hz 16:9 */
a6b21831
TR		 766 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
767 1430, 1650, 0, 720, 725, 730, 750, 0,
ee7925bb 768 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 769 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 770 /* 5 - 1920x1080i@60Hz 16:9 */
a6b21831
TR		 771 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
772 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
773 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 774 DRM_MODE_FLAG_INTERLACE),
0425662f 775 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 776 /* 6 - 720(1440)x480i@60Hz 4:3 */
fb01d280
CT		 777 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
778 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 779 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 780 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 781 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 782 /* 7 - 720(1440)x480i@60Hz 16:9 */
fb01d280
CT		 783 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
784 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 785 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 786 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 787 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 788 /* 8 - 720(1440)x240@60Hz 4:3 */
fb01d280
CT		 789 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
790 801, 858, 0, 240, 244, 247, 262, 0,
a6b21831 791 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 792 DRM_MODE_FLAG_DBLCLK),
0425662f 793 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 794 /* 9 - 720(1440)x240@60Hz 16:9 */
fb01d280
CT		 795 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
796 801, 858, 0, 240, 244, 247, 262, 0,
a6b21831 797 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 798 DRM_MODE_FLAG_DBLCLK),
0425662f 799 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 800 /* 10 - 2880x480i@60Hz 4:3 */
a6b21831
TR		 801 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
802 3204, 3432, 0, 480, 488, 494, 525, 0,
803 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 804 DRM_MODE_FLAG_INTERLACE),
0425662f 805 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 806 /* 11 - 2880x480i@60Hz 16:9 */
a6b21831
TR		 807 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
808 3204, 3432, 0, 480, 488, 494, 525, 0,
809 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 810 DRM_MODE_FLAG_INTERLACE),
0425662f 811 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 812 /* 12 - 2880x240@60Hz 4:3 */
a6b21831
TR		 813 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
814 3204, 3432, 0, 240, 244, 247, 262, 0,
ee7925bb 815 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 816 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 817 /* 13 - 2880x240@60Hz 16:9 */
a6b21831
TR		 818 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
819 3204, 3432, 0, 240, 244, 247, 262, 0,
ee7925bb 820 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 821 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 822 /* 14 - 1440x480@60Hz 4:3 */
a6b21831
TR		 823 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
824 1596, 1716, 0, 480, 489, 495, 525, 0,
ee7925bb 825 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 826 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 827 /* 15 - 1440x480@60Hz 16:9 */
a6b21831
TR		 828 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
829 1596, 1716, 0, 480, 489, 495, 525, 0,
ee7925bb 830 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 831 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 832 /* 16 - 1920x1080@60Hz 16:9 */
a6b21831
TR		 833 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
834 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 835 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 836 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 837 /* 17 - 720x576@50Hz 4:3 */
a6b21831
TR		 838 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
839 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 840 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 841 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 842 /* 18 - 720x576@50Hz 16:9 */
a6b21831
TR		 843 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
844 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 845 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 846 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 847 /* 19 - 1280x720@50Hz 16:9 */
a6b21831
TR		 848 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
849 1760, 1980, 0, 720, 725, 730, 750, 0,
ee7925bb 850 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 851 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 852 /* 20 - 1920x1080i@50Hz 16:9 */
a6b21831
TR		 853 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
854 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
855 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 856 DRM_MODE_FLAG_INTERLACE),
0425662f 857 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 858 /* 21 - 720(1440)x576i@50Hz 4:3 */
fb01d280
CT		 859 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
860 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 861 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 862 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 863 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 864 /* 22 - 720(1440)x576i@50Hz 16:9 */
fb01d280
CT		 865 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
866 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 867 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 868 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 869 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 870 /* 23 - 720(1440)x288@50Hz 4:3 */
fb01d280
CT		 871 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
872 795, 864, 0, 288, 290, 293, 312, 0,
a6b21831 873 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 874 DRM_MODE_FLAG_DBLCLK),
0425662f 875 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 876 /* 24 - 720(1440)x288@50Hz 16:9 */
fb01d280
CT		 877 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
878 795, 864, 0, 288, 290, 293, 312, 0,
a6b21831 879 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 880 DRM_MODE_FLAG_DBLCLK),
0425662f 881 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 882 /* 25 - 2880x576i@50Hz 4:3 */
a6b21831
TR		 883 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
884 3180, 3456, 0, 576, 580, 586, 625, 0,
885 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 886 DRM_MODE_FLAG_INTERLACE),
0425662f 887 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 888 /* 26 - 2880x576i@50Hz 16:9 */
a6b21831
TR		 889 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
890 3180, 3456, 0, 576, 580, 586, 625, 0,
891 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 892 DRM_MODE_FLAG_INTERLACE),
0425662f 893 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 894 /* 27 - 2880x288@50Hz 4:3 */
a6b21831
TR		 895 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
896 3180, 3456, 0, 288, 290, 293, 312, 0,
ee7925bb 897 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 898 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 899 /* 28 - 2880x288@50Hz 16:9 */
a6b21831
TR		 900 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
901 3180, 3456, 0, 288, 290, 293, 312, 0,
ee7925bb 902 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 903 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 904 /* 29 - 1440x576@50Hz 4:3 */
a6b21831
TR		 905 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
906 1592, 1728, 0, 576, 581, 586, 625, 0,
ee7925bb 907 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 908 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 909 /* 30 - 1440x576@50Hz 16:9 */
a6b21831
TR		 910 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
911 1592, 1728, 0, 576, 581, 586, 625, 0,
ee7925bb 912 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 913 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 914 /* 31 - 1920x1080@50Hz 16:9 */
a6b21831
TR		 915 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
916 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 917 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 918 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 919 /* 32 - 1920x1080@24Hz 16:9 */
a6b21831
TR		 920 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
921 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 922 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 923 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 924 /* 33 - 1920x1080@25Hz 16:9 */
a6b21831
TR		 925 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
926 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 927 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 928 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 929 /* 34 - 1920x1080@30Hz 16:9 */
a6b21831
TR		 930 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
931 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 932 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 933 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 934 /* 35 - 2880x480@60Hz 4:3 */
a6b21831
TR		 935 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
936 3192, 3432, 0, 480, 489, 495, 525, 0,
ee7925bb 937 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 938 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 939 /* 36 - 2880x480@60Hz 16:9 */
a6b21831
TR		 940 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
941 3192, 3432, 0, 480, 489, 495, 525, 0,
ee7925bb 942 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 943 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 944 /* 37 - 2880x576@50Hz 4:3 */
a6b21831
TR		 945 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
946 3184, 3456, 0, 576, 581, 586, 625, 0,
ee7925bb 947 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 948 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 949 /* 38 - 2880x576@50Hz 16:9 */
a6b21831
TR		 950 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
951 3184, 3456, 0, 576, 581, 586, 625, 0,
ee7925bb 952 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 953 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 954 /* 39 - 1920x1080i@50Hz 16:9 */
a6b21831
TR		 955 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
956 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
957 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 958 DRM_MODE_FLAG_INTERLACE),
0425662f 959 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 960 /* 40 - 1920x1080i@100Hz 16:9 */
a6b21831
TR		 961 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
962 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
963 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 964 DRM_MODE_FLAG_INTERLACE),
0425662f 965 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 966 /* 41 - 1280x720@100Hz 16:9 */
a6b21831
TR		 967 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
968 1760, 1980, 0, 720, 725, 730, 750, 0,
ee7925bb 969 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 970 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 971 /* 42 - 720x576@100Hz 4:3 */
a6b21831
TR		 972 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
973 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 974 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 975 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 976 /* 43 - 720x576@100Hz 16:9 */
a6b21831
TR		 977 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
978 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 979 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 980 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 981 /* 44 - 720(1440)x576i@100Hz 4:3 */
fb01d280
CT		 982 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
983 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 984 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 985 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 986 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 987 /* 45 - 720(1440)x576i@100Hz 16:9 */
fb01d280
CT		 988 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
989 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 990 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 991 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 992 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 993 /* 46 - 1920x1080i@120Hz 16:9 */
a6b21831
TR		 994 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
995 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
996 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 997 DRM_MODE_FLAG_INTERLACE),
0425662f 998 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 999 /* 47 - 1280x720@120Hz 16:9 */
a6b21831
TR		 1000 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1001 1430, 1650, 0, 720, 725, 730, 750, 0,
ee7925bb 1002 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1003 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1004 /* 48 - 720x480@120Hz 4:3 */
a6b21831
TR		 1005 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
1006 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 1007 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 1008 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1009 /* 49 - 720x480@120Hz 16:9 */
a6b21831
TR		 1010 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
1011 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 1012 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 1013 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1014 /* 50 - 720(1440)x480i@120Hz 4:3 */
fb01d280
CT		 1015 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
1016 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 1017 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1018 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1019 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1020 /* 51 - 720(1440)x480i@120Hz 16:9 */
fb01d280
CT		 1021 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
1022 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 1023 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1024 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1025 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1026 /* 52 - 720x576@200Hz 4:3 */
a6b21831
TR		 1027 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1028 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 1029 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 1030 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1031 /* 53 - 720x576@200Hz 16:9 */
a6b21831
TR		 1032 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1033 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 1034 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 1035 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1036 /* 54 - 720(1440)x576i@200Hz 4:3 */
fb01d280
CT		 1037 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1038 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 1039 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1040 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1041 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1042 /* 55 - 720(1440)x576i@200Hz 16:9 */
fb01d280
CT		 1043 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1044 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 1045 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1046 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1047 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1048 /* 56 - 720x480@240Hz 4:3 */
a6b21831
TR		 1049 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1050 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 1051 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 1052 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1053 /* 57 - 720x480@240Hz 16:9 */
a6b21831
TR		 1054 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1055 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 1056 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 1057 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1058 /* 58 - 720(1440)x480i@240Hz 4:3 */
fb01d280
CT		 1059 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1060 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 1061 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1062 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1063 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1064 /* 59 - 720(1440)x480i@240Hz 16:9 */
fb01d280
CT		 1065 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1066 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 1067 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1068 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1069 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1070 /* 60 - 1280x720@24Hz 16:9 */
a6b21831
TR		 1071 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1072 3080, 3300, 0, 720, 725, 730, 750, 0,
ee7925bb 1073 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1074 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1075 /* 61 - 1280x720@25Hz 16:9 */
a6b21831
TR		 1076 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1077 3740, 3960, 0, 720, 725, 730, 750, 0,
ee7925bb 1078 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1079 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1080 /* 62 - 1280x720@30Hz 16:9 */
a6b21831
TR		 1081 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1082 3080, 3300, 0, 720, 725, 730, 750, 0,
ee7925bb 1083 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1084 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1085 /* 63 - 1920x1080@120Hz 16:9 */
a6b21831
TR		 1086 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1087 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 1088 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1089 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1090 /* 64 - 1920x1080@100Hz 16:9 */
a6b21831 1091 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
8f0e4907 1092 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 1093 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1094 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1095 /* 65 - 1280x720@24Hz 64:27 */
8ec6e075
SS		 1096 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1097 3080, 3300, 0, 720, 725, 730, 750, 0,
1098 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1099 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1100 /* 66 - 1280x720@25Hz 64:27 */
8ec6e075
SS		 1101 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1102 3740, 3960, 0, 720, 725, 730, 750, 0,
1103 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1104 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1105 /* 67 - 1280x720@30Hz 64:27 */
8ec6e075
SS		 1106 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1107 3080, 3300, 0, 720, 725, 730, 750, 0,
1108 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1109 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1110 /* 68 - 1280x720@50Hz 64:27 */
8ec6e075
SS		 1111 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1112 1760, 1980, 0, 720, 725, 730, 750, 0,
1113 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1114 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1115 /* 69 - 1280x720@60Hz 64:27 */
8ec6e075
SS		 1116 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1117 1430, 1650, 0, 720, 725, 730, 750, 0,
1118 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1119 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1120 /* 70 - 1280x720@100Hz 64:27 */
8ec6e075
SS		 1121 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1122 1760, 1980, 0, 720, 725, 730, 750, 0,
1123 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1124 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1125 /* 71 - 1280x720@120Hz 64:27 */
8ec6e075
SS		 1126 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1127 1430, 1650, 0, 720, 725, 730, 750, 0,
1128 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1129 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1130 /* 72 - 1920x1080@24Hz 64:27 */
8ec6e075
SS		 1131 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1132 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1133 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1134 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1135 /* 73 - 1920x1080@25Hz 64:27 */
8ec6e075
SS		 1136 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1137 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1138 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1139 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1140 /* 74 - 1920x1080@30Hz 64:27 */
8ec6e075
SS		 1141 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1142 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1143 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1144 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1145 /* 75 - 1920x1080@50Hz 64:27 */
8ec6e075
SS		 1146 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1147 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1148 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1149 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1150 /* 76 - 1920x1080@60Hz 64:27 */
8ec6e075
SS		 1151 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1152 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1153 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1154 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1155 /* 77 - 1920x1080@100Hz 64:27 */
8ec6e075
SS		 1156 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1157 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1158 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1159 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1160 /* 78 - 1920x1080@120Hz 64:27 */
8ec6e075
SS		 1161 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1162 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1163 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1164 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1165 /* 79 - 1680x720@24Hz 64:27 */
8ec6e075
SS		 1166 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1167 3080, 3300, 0, 720, 725, 730, 750, 0,
1168 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1169 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1170 /* 80 - 1680x720@25Hz 64:27 */
8ec6e075
SS		 1171 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1172 2948, 3168, 0, 720, 725, 730, 750, 0,
1173 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1174 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1175 /* 81 - 1680x720@30Hz 64:27 */
8ec6e075
SS		 1176 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1177 2420, 2640, 0, 720, 725, 730, 750, 0,
1178 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1179 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1180 /* 82 - 1680x720@50Hz 64:27 */
8ec6e075
SS		 1181 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1182 1980, 2200, 0, 720, 725, 730, 750, 0,
1183 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1184 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1185 /* 83 - 1680x720@60Hz 64:27 */
8ec6e075
SS		 1186 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1187 1980, 2200, 0, 720, 725, 730, 750, 0,
1188 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1189 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1190 /* 84 - 1680x720@100Hz 64:27 */
8ec6e075
SS		 1191 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1192 1780, 2000, 0, 720, 725, 730, 825, 0,
1193 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1194 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1195 /* 85 - 1680x720@120Hz 64:27 */
8ec6e075
SS		 1196 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1197 1780, 2000, 0, 720, 725, 730, 825, 0,
1198 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1199 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1200 /* 86 - 2560x1080@24Hz 64:27 */
8ec6e075
SS		 1201 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1202 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1203 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1204 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1205 /* 87 - 2560x1080@25Hz 64:27 */
8ec6e075
SS		 1206 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1207 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1208 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1209 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1210 /* 88 - 2560x1080@30Hz 64:27 */
8ec6e075
SS		 1211 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1212 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1213 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1214 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1215 /* 89 - 2560x1080@50Hz 64:27 */
8ec6e075
SS		 1216 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1217 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1218 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1219 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1220 /* 90 - 2560x1080@60Hz 64:27 */
8ec6e075
SS		 1221 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1222 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1223 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1224 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1225 /* 91 - 2560x1080@100Hz 64:27 */
8ec6e075
SS		 1226 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1227 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1228 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1229 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1230 /* 92 - 2560x1080@120Hz 64:27 */
8ec6e075
SS		 1231 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1232 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1233 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1234 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1235 /* 93 - 3840x2160@24Hz 16:9 */
8ec6e075
SS		 1236 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1237 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1238 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1239 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1240 /* 94 - 3840x2160@25Hz 16:9 */
8ec6e075
SS		 1241 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1242 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1243 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1244 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1245 /* 95 - 3840x2160@30Hz 16:9 */
8ec6e075
SS		 1246 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1247 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1248 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1249 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1250 /* 96 - 3840x2160@50Hz 16:9 */
8ec6e075
SS		 1251 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1252 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1253 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1254 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1255 /* 97 - 3840x2160@60Hz 16:9 */
8ec6e075
SS		 1256 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1257 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1258 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1259 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1260 /* 98 - 4096x2160@24Hz 256:135 */
8ec6e075
SS		 1261 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1262 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1263 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1264 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1265 /* 99 - 4096x2160@25Hz 256:135 */
8ec6e075
SS		 1266 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1267 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1269 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1270 /* 100 - 4096x2160@30Hz 256:135 */
8ec6e075
SS		 1271 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1272 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1273 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1274 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1275 /* 101 - 4096x2160@50Hz 256:135 */
8ec6e075
SS		 1276 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1277 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1278 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1279 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1280 /* 102 - 4096x2160@60Hz 256:135 */
8ec6e075
SS		 1281 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1282 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1283 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1284 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1285 /* 103 - 3840x2160@24Hz 64:27 */
8ec6e075
SS		 1286 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1287 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1288 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1289 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1290 /* 104 - 3840x2160@25Hz 64:27 */
8ec6e075
SS		 1291 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1292 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1293 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1294 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1295 /* 105 - 3840x2160@30Hz 64:27 */
8ec6e075
SS		 1296 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1297 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1298 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1299 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1300 /* 106 - 3840x2160@50Hz 64:27 */
8ec6e075
SS		 1301 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1302 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1303 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1304 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1305 /* 107 - 3840x2160@60Hz 64:27 */
8ec6e075
SS		 1306 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1307 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1308 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1309 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1310 /* 108 - 1280x720@48Hz 16:9 */
1311 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1312 2280, 2500, 0, 720, 725, 730, 750, 0,
1313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1314 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1315 /* 109 - 1280x720@48Hz 64:27 */
1316 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1317 2280, 2500, 0, 720, 725, 730, 750, 0,
1318 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1319 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1320 /* 110 - 1680x720@48Hz 64:27 */
1321 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490,
1322 2530, 2750, 0, 720, 725, 730, 750, 0,
1323 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1324 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1325 /* 111 - 1920x1080@48Hz 16:9 */
1326 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1327 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1328 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1329 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1330 /* 112 - 1920x1080@48Hz 64:27 */
1331 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1332 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1334 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1335 /* 113 - 2560x1080@48Hz 64:27 */
1336 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558,
1337 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1338 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1339 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1340 /* 114 - 3840x2160@48Hz 16:9 */
1341 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1342 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1343 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1344 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1345 /* 115 - 4096x2160@48Hz 256:135 */
1346 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116,
1347 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1348 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1349 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
978f6b06
VS		 1350 /* 116 - 3840x2160@48Hz 64:27 */
1351 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1352 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1354 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1355 /* 117 - 3840x2160@100Hz 16:9 */
1356 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1357 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1358 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1359 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1360 /* 118 - 3840x2160@120Hz 16:9 */
1361 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1362 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1363 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1364 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1365 /* 119 - 3840x2160@100Hz 64:27 */
1366 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1367 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1369 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1370 /* 120 - 3840x2160@120Hz 64:27 */
1371 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1372 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1374 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1375 /* 121 - 5120x2160@24Hz 64:27 */
1376 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116,
1377 7204, 7500, 0, 2160, 2168, 2178, 2200, 0,
1378 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1379 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1380 /* 122 - 5120x2160@25Hz 64:27 */
1381 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816,
1382 6904, 7200, 0, 2160, 2168, 2178, 2200, 0,
1383 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1384 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1385 /* 123 - 5120x2160@30Hz 64:27 */
1386 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784,
1387 5872, 6000, 0, 2160, 2168, 2178, 2200, 0,
1388 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1389 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1390 /* 124 - 5120x2160@48Hz 64:27 */
1391 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866,
1392 5954, 6250, 0, 2160, 2168, 2178, 2475, 0,
1393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1394 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1395 /* 125 - 5120x2160@50Hz 64:27 */
1396 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216,
1397 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1398 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1399 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1400 /* 126 - 5120x2160@60Hz 64:27 */
1401 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284,
1402 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1403 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1404 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1405 /* 127 - 5120x2160@100Hz 64:27 */
1406 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216,
1407 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1408 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1409 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
a6b21831
TR		 1410};
1411
f7655d42
VS		 1412/*
1413 * From CEA/CTA-861 spec.
1414 *
1415 * Do not access directly, instead always use cea_mode_for_vic().
1416 */
1417static const struct drm_display_mode edid_cea_modes_193[] = {
1418 /* 193 - 5120x2160@120Hz 64:27 */
1419 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284,
1420 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1421 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1422 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1423 /* 194 - 7680x4320@24Hz 16:9 */
1424 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1425 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1426 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1427 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1428 /* 195 - 7680x4320@25Hz 16:9 */
1429 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1430 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1431 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1432 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1433 /* 196 - 7680x4320@30Hz 16:9 */
1434 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1435 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1436 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1437 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1438 /* 197 - 7680x4320@48Hz 16:9 */
1439 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1440 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1441 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1442 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1443 /* 198 - 7680x4320@50Hz 16:9 */
1444 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1445 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1446 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1447 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1448 /* 199 - 7680x4320@60Hz 16:9 */
1449 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1450 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1451 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1452 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1453 /* 200 - 7680x4320@100Hz 16:9 */
1454 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1455 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1456 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1457 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1458 /* 201 - 7680x4320@120Hz 16:9 */
1459 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1460 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1462 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1463 /* 202 - 7680x4320@24Hz 64:27 */
1464 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1465 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1466 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1467 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1468 /* 203 - 7680x4320@25Hz 64:27 */
1469 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1470 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1471 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1472 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1473 /* 204 - 7680x4320@30Hz 64:27 */
1474 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1475 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1476 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1477 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1478 /* 205 - 7680x4320@48Hz 64:27 */
1479 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1480 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1482 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1483 /* 206 - 7680x4320@50Hz 64:27 */
1484 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1485 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1486 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1487 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1488 /* 207 - 7680x4320@60Hz 64:27 */
1489 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1490 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1491 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1492 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1493 /* 208 - 7680x4320@100Hz 64:27 */
1494 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1495 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1496 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1497 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1498 /* 209 - 7680x4320@120Hz 64:27 */
1499 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1500 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1501 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1502 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1503 /* 210 - 10240x4320@24Hz 64:27 */
1504 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732,
1505 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1506 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1507 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1508 /* 211 - 10240x4320@25Hz 64:27 */
1509 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732,
1510 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1511 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1512 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1513 /* 212 - 10240x4320@30Hz 64:27 */
1514 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528,
1515 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1516 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1517 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1518 /* 213 - 10240x4320@48Hz 64:27 */
1519 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732,
1520 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1521 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1522 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1523 /* 214 - 10240x4320@50Hz 64:27 */
1524 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732,
1525 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1526 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1527 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1528 /* 215 - 10240x4320@60Hz 64:27 */
1529 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528,
1530 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1531 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1532 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1533 /* 216 - 10240x4320@100Hz 64:27 */
1534 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432,
1535 12608, 13200, 0, 4320, 4336, 4356, 4500, 0,
1536 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1537 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1538 /* 217 - 10240x4320@120Hz 64:27 */
1539 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528,
1540 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1541 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1542 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1543 /* 218 - 4096x2160@100Hz 256:135 */
1544 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896,
1545 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1546 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1547 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
f7655d42
VS		 1548 /* 219 - 4096x2160@120Hz 256:135 */
1549 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184,
1550 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1551 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1552 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
f7655d42
VS		 1553};
1554
7ebe1963 1555/*
d9278b4c 1556 * HDMI 1.4 4k modes. Index using the VIC.
7ebe1963
LD		 1557 */
1558static const struct drm_display_mode edid_4k_modes[] = {
d9278b4c
JN		 1559 /* 0 - dummy, VICs start at 1 */
1560 { },
7ebe1963
LD		 1561 /* 1 - 3840x2160@30Hz */
1562 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1563 3840, 4016, 4104, 4400, 0,
1564 2160, 2168, 2178, 2250, 0,
1565 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1566 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
7ebe1963
LD		 1567 /* 2 - 3840x2160@25Hz */
1568 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1569 3840, 4896, 4984, 5280, 0,
1570 2160, 2168, 2178, 2250, 0,
1571 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1572 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
7ebe1963
LD		 1573 /* 3 - 3840x2160@24Hz */
1574 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1575 3840, 5116, 5204, 5500, 0,
1576 2160, 2168, 2178, 2250, 0,
1577 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1578 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
7ebe1963
LD		 1579 /* 4 - 4096x2160@24Hz (SMPTE) */
1580 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1581 4096, 5116, 5204, 5500, 0,
1582 2160, 2168, 2178, 2250, 0,
1583 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1584 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
7ebe1963
LD		 1585};
1586
61e57a8d 1587/*** DDC fetch and block validation ***/
f453ba04 1588
e4ccf9a7
JN		 1589/*
1590 * The opaque EDID type, internal to drm_edid.c.
1591 */
1592struct drm_edid {
1593 /* Size allocated for edid */
1594 size_t size;
1595 const struct edid *edid;
1596};
1597
18e3c1d5
JN		 1598static int edid_hfeeodb_extension_block_count(const struct edid *edid);
1599
1600static int edid_hfeeodb_block_count(const struct edid *edid)
1601{
1602 int eeodb = edid_hfeeodb_extension_block_count(edid);
1603
1604 return eeodb ? eeodb + 1 : 0;
1605}
1606
f1e4c916
JN		 1607static int edid_extension_block_count(const struct edid *edid)
1608{
1609 return edid->extensions;
1610}
1611
1612static int edid_block_count(const struct edid *edid)
1613{
1614 return edid_extension_block_count(edid) + 1;
1615}
1616
1617static int edid_size_by_blocks(int num_blocks)
1618{
1619 return num_blocks * EDID_LENGTH;
1620}
1621
1622static int edid_size(const struct edid *edid)
1623{
1624 return edid_size_by_blocks(edid_block_count(edid));
1625}
1626
1627static const void *edid_block_data(const struct edid *edid, int index)
1628{
1629 BUILD_BUG_ON(sizeof(*edid) != EDID_LENGTH);
1630
1631 return edid + index;
1632}
1633
1634static const void *edid_extension_block_data(const struct edid *edid, int index)
1635{
1636 return edid_block_data(edid, index + 1);
1637}
1638
b16c9e6c
JN		 1639/* EDID block count indicated in EDID, may exceed allocated size */
1640static int __drm_edid_block_count(const struct drm_edid *drm_edid)
d9307f27
JN		 1641{
1642 int num_blocks;
1643
1644 /* Starting point */
1645 num_blocks = edid_block_count(drm_edid->edid);
1646
b1dee952
JN		 1647 /* HF-EEODB override */
1648 if (drm_edid->size >= edid_size_by_blocks(2)) {
1649 int eeodb;
1650
1651 /*
1652 * Note: HF-EEODB may specify a smaller extension count than the
1653 * regular one. Unlike in buffer allocation, here we can use it.
1654 */
1655 eeodb = edid_hfeeodb_block_count(drm_edid->edid);
1656 if (eeodb)
1657 num_blocks = eeodb;
1658 }
1659
d9307f27
JN		 1660 return num_blocks;
1661}
1662
b16c9e6c
JN		 1663/* EDID block count, limited by allocated size */
1664static int drm_edid_block_count(const struct drm_edid *drm_edid)
1665{
1666 /* Limit by allocated size */
1667 return min(__drm_edid_block_count(drm_edid),
1668 (int)drm_edid->size / EDID_LENGTH);
1669}
1670
1671/* EDID extension block count, limited by allocated size */
d9307f27
JN		 1672static int drm_edid_extension_block_count(const struct drm_edid *drm_edid)
1673{
1674 return drm_edid_block_count(drm_edid) - 1;
1675}
1676
1677static const void *drm_edid_block_data(const struct drm_edid *drm_edid, int index)
1678{
1679 return edid_block_data(drm_edid->edid, index);
1680}
1681
1682static const void *drm_edid_extension_block_data(const struct drm_edid *drm_edid,
1683 int index)
1684{
1685 return edid_extension_block_data(drm_edid->edid, index);
1686}
1687
22a27e05
JN		 1688/*
1689 * Initializer helper for legacy interfaces, where we have no choice but to
1690 * trust edid size. Not for general purpose use.
1691 */
1692static const struct drm_edid *drm_edid_legacy_init(struct drm_edid *drm_edid,
1693 const struct edid *edid)
1694{
1695 if (!edid)
1696 return NULL;
1697
1698 memset(drm_edid, 0, sizeof(*drm_edid));
1699
1700 drm_edid->edid = edid;
1701 drm_edid->size = edid_size(edid);
1702
1703 return drm_edid;
1704}
1705
94afc538
JN		 1706/*
1707 * EDID base and extension block iterator.
1708 *
1709 * struct drm_edid_iter iter;
1710 * const u8 *block;
1711 *
bbded689 1712 * drm_edid_iter_begin(drm_edid, &iter);
94afc538
JN		 1713 * drm_edid_iter_for_each(block, &iter) {
1714 * // do stuff with block
1715 * }
1716 * drm_edid_iter_end(&iter);
1717 */
1718struct drm_edid_iter {
bbded689 1719 const struct drm_edid *drm_edid;
94afc538
JN		 1720
1721 /* Current block index. */
1722 int index;
1723};
1724
bbded689 1725static void drm_edid_iter_begin(const struct drm_edid *drm_edid,
94afc538
JN		 1726 struct drm_edid_iter *iter)
1727{
1728 memset(iter, 0, sizeof(*iter));
1729
bbded689 1730 iter->drm_edid = drm_edid;
94afc538
JN		 1731}
1732
1733static const void *__drm_edid_iter_next(struct drm_edid_iter *iter)
1734{
1735 const void *block = NULL;
1736
bbded689 1737 if (!iter->drm_edid)
94afc538
JN		 1738 return NULL;
1739
d9307f27
JN		 1740 if (iter->index < drm_edid_block_count(iter->drm_edid))
1741 block = drm_edid_block_data(iter->drm_edid, iter->index++);
94afc538
JN		 1742
1743 return block;
1744}
1745
1746#define drm_edid_iter_for_each(__block, __iter) \
1747 while (((__block) = __drm_edid_iter_next(__iter)))
1748
1749static void drm_edid_iter_end(struct drm_edid_iter *iter)
1750{
1751 memset(iter, 0, sizeof(*iter));
1752}
1753
083ae056
AJ		 1754static const u8 edid_header[] = {
1755 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1756};
f453ba04 1757
0a612bbd
JN		 1758static void edid_header_fix(void *edid)
1759{
1760 memcpy(edid, edid_header, sizeof(edid_header));
1761}
1762
db6cf833
TR		 1763/**
1764 * drm_edid_header_is_valid - sanity check the header of the base EDID block
5d96fc9c 1765 * @_edid: pointer to raw base EDID block
db6cf833
TR		 1766 *
1767 * Sanity check the header of the base EDID block.
1768 *
1769 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
051963d4 1770 */
6d987ddd 1771int drm_edid_header_is_valid(const void *_edid)
051963d4 1772{
6d987ddd 1773 const struct edid *edid = _edid;
051963d4
TR		 1774 int i, score = 0;
1775
6d987ddd
JN		 1776 for (i = 0; i < sizeof(edid_header); i++) {
1777 if (edid->header[i] == edid_header[i])
051963d4 1778 score++;
6d987ddd 1779 }
051963d4
TR		 1780
1781 return score;
1782}
1783EXPORT_SYMBOL(drm_edid_header_is_valid);
1784
47819ba2
AJ		 1785static int edid_fixup __read_mostly = 6;
1786module_param_named(edid_fixup, edid_fixup, int, 0400);
1787MODULE_PARM_DESC(edid_fixup,
1788 "Minimum number of valid EDID header bytes (0-8, default 6)");
051963d4 1789
70e49ebe 1790static int edid_block_compute_checksum(const void *_block)
c465bbc8 1791{
70e49ebe 1792 const u8 *block = _block;
c465bbc8 1793 int i;
e11f5bd8
JFZ		 1794 u8 csum = 0, crc = 0;
1795
1796 for (i = 0; i < EDID_LENGTH - 1; i++)
70e49ebe 1797 csum += block[i];
c465bbc8 1798
e11f5bd8
JFZ		 1799 crc = 0x100 - csum;
1800
1801 return crc;
1802}
1803
70e49ebe 1804static int edid_block_get_checksum(const void *_block)
e11f5bd8 1805{
70e49ebe
JN		 1806 const struct edid *block = _block;
1807
1808 return block->checksum;
c465bbc8
SB		 1809}
1810
4ba0f53c
JN		 1811static int edid_block_tag(const void *_block)
1812{
1813 const u8 *block = _block;
1814
1815 return block[0];
1816}
1817
8baccb27 1818static bool edid_block_is_zero(const void *edid)
d6885d65 1819{
f7650635 1820 return mem_is_zero(edid, EDID_LENGTH);
d6885d65
SB		 1821}
1822
00c7a010
JN		 1823static bool drm_edid_eq(const struct drm_edid *drm_edid,
1824 const void *raw_edid, size_t raw_edid_size)
536faa45 1825{
00c7a010
JN		 1826 bool edid1_present = drm_edid && drm_edid->edid && drm_edid->size;
1827 bool edid2_present = raw_edid && raw_edid_size;
536faa45
SL		 1828
1829 if (edid1_present != edid2_present)
1830 return false;
1831
00c7a010
JN		 1832 if (edid1_present) {
1833 if (drm_edid->size != raw_edid_size)
536faa45
SL		 1834 return false;
1835
00c7a010 1836 if (memcmp(drm_edid->edid, raw_edid, drm_edid->size))
536faa45
SL		 1837 return false;
1838 }
1839
1840 return true;
1841}
536faa45 1842
1f221284
JN		 1843enum edid_block_status {
1844 EDID_BLOCK_OK = 0,
2deaf1c2 1845 EDID_BLOCK_READ_FAIL,
1f221284 1846 EDID_BLOCK_NULL,
49dc0558 1847 EDID_BLOCK_ZERO,
1f221284
JN		 1848 EDID_BLOCK_HEADER_CORRUPT,
1849 EDID_BLOCK_HEADER_REPAIR,
1850 EDID_BLOCK_HEADER_FIXED,
1851 EDID_BLOCK_CHECKSUM,
1852 EDID_BLOCK_VERSION,
1853};
1854
1855static enum edid_block_status edid_block_check(const void *_block,
1856 bool is_base_block)
1857{
1858 const struct edid *block = _block;
1859
1860 if (!block)
1861 return EDID_BLOCK_NULL;
1862
1863 if (is_base_block) {
1864 int score = drm_edid_header_is_valid(block);
1865
49dc0558
JN		 1866 if (score < clamp(edid_fixup, 0, 8)) {
1867 if (edid_block_is_zero(block))
1868 return EDID_BLOCK_ZERO;
1869 else
1870 return EDID_BLOCK_HEADER_CORRUPT;
1871 }
1f221284
JN		 1872
1873 if (score < 8)
1874 return EDID_BLOCK_HEADER_REPAIR;
1875 }
1876
49dc0558
JN		 1877 if (edid_block_compute_checksum(block) != edid_block_get_checksum(block)) {
1878 if (edid_block_is_zero(block))
1879 return EDID_BLOCK_ZERO;
1880 else
1881 return EDID_BLOCK_CHECKSUM;
1882 }
1f221284
JN		 1883
1884 if (is_base_block) {
1885 if (block->version != 1)
1886 return EDID_BLOCK_VERSION;
1887 }
1888
1889 return EDID_BLOCK_OK;
1890}
1891
1892static bool edid_block_status_valid(enum edid_block_status status, int tag)
1893{
1894 return status == EDID_BLOCK_OK ||
1895 status == EDID_BLOCK_HEADER_FIXED ||
1896 (status == EDID_BLOCK_CHECKSUM && tag == CEA_EXT);
1897}
1898
23e38d7b
JN		 1899static bool edid_block_valid(const void *block, bool base)
1900{
1901 return edid_block_status_valid(edid_block_check(block, base),
1902 edid_block_tag(block));
1903}
1904
cee2ce1a
JN		 1905static void edid_block_status_print(enum edid_block_status status,
1906 const struct edid *block,
1907 int block_num)
1908{
1909 switch (status) {
1910 case EDID_BLOCK_OK:
1911 break;
2deaf1c2
JN		 1912 case EDID_BLOCK_READ_FAIL:
1913 pr_debug("EDID block %d read failed\n", block_num);
1914 break;
cee2ce1a
JN		 1915 case EDID_BLOCK_NULL:
1916 pr_debug("EDID block %d pointer is NULL\n", block_num);
1917 break;
1918 case EDID_BLOCK_ZERO:
1919 pr_notice("EDID block %d is all zeroes\n", block_num);
1920 break;
1921 case EDID_BLOCK_HEADER_CORRUPT:
1922 pr_notice("EDID has corrupt header\n");
1923 break;
1924 case EDID_BLOCK_HEADER_REPAIR:
1925 pr_debug("EDID corrupt header needs repair\n");
1926 break;
1927 case EDID_BLOCK_HEADER_FIXED:
1928 pr_debug("EDID corrupt header fixed\n");
1929 break;
1930 case EDID_BLOCK_CHECKSUM:
1931 if (edid_block_status_valid(status, edid_block_tag(block))) {
1932 pr_debug("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d, ignoring\n",
1933 block_num, edid_block_tag(block),
1934 edid_block_compute_checksum(block));
1935 } else {
1936 pr_notice("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d\n",
1937 block_num, edid_block_tag(block),
1938 edid_block_compute_checksum(block));
1939 }
1940 break;
1941 case EDID_BLOCK_VERSION:
1942 pr_notice("EDID has major version %d, instead of 1\n",
1943 block->version);
1944 break;
1945 default:
1946 WARN(1, "EDID block %d unknown edid block status code %d\n",
1947 block_num, status);
1948 break;
1949 }
1950}
1951
9c7345de
JN		 1952static void edid_block_dump(const char *level, const void *block, int block_num)
1953{
1954 enum edid_block_status status;
1955 char prefix[20];
1956
1957 status = edid_block_check(block, block_num == 0);
1958 if (status == EDID_BLOCK_ZERO)
1959 sprintf(prefix, "\t[%02x] ZERO ", block_num);
1960 else if (!edid_block_status_valid(status, edid_block_tag(block)))
1961 sprintf(prefix, "\t[%02x] BAD ", block_num);
1962 else
1963 sprintf(prefix, "\t[%02x] GOOD ", block_num);
1964
1965 print_hex_dump(level, prefix, DUMP_PREFIX_NONE, 16, 1,
1966 block, EDID_LENGTH, false);
1967}
1968
dfa55431 1969/*
db6cf833
TR		 1970 * Validate a base or extension EDID block and optionally dump bad blocks to
1971 * the console.
f453ba04 1972 */
dfa55431
JN		 1973static bool drm_edid_block_valid(void *_block, int block_num, bool print_bad_edid,
1974 bool *edid_corrupt)
f453ba04 1975{
dfa55431 1976 struct edid *block = _block;
1f221284
JN		 1977 enum edid_block_status status;
1978 bool is_base_block = block_num == 0;
1979 bool valid;
f453ba04 1980
1f221284 1981 if (WARN_ON(!block))
fe2ef780
SWK		 1982 return false;
1983
1f221284
JN		 1984 status = edid_block_check(block, is_base_block);
1985 if (status == EDID_BLOCK_HEADER_REPAIR) {
e1e7bc48 1986 DRM_DEBUG_KMS("Fixing EDID header, your hardware may be failing\n");
1f221284
JN		 1987 edid_header_fix(block);
1988
1989 /* Retry with fixed header, update status if that worked. */
1990 status = edid_block_check(block, is_base_block);
1991 if (status == EDID_BLOCK_OK)
1992 status = EDID_BLOCK_HEADER_FIXED;
61e57a8d 1993 }
f453ba04 1994
1f221284
JN		 1995 if (edid_corrupt) {
1996 /*
1997 * Unknown major version isn't corrupt but we can't use it. Only
1998 * the base block can reset edid_corrupt to false.
1999 */
2000 if (is_base_block &&
2001 (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION))
2002 *edid_corrupt = false;
2003 else if (status != EDID_BLOCK_OK)
ac6f2e29 2004 *edid_corrupt = true;
f453ba04
DA		 2005 }
2006
cee2ce1a
JN		 2007 edid_block_status_print(status, block, block_num);
2008
1f221284
JN		 2009 /* Determine whether we can use this block with this status. */
2010 valid = edid_block_status_valid(status, edid_block_tag(block));
2011
cee2ce1a
JN		 2012 if (!valid && print_bad_edid && status != EDID_BLOCK_ZERO) {
2013 pr_notice("Raw EDID:\n");
9c7345de 2014 edid_block_dump(KERN_NOTICE, block, block_num);
f453ba04 2015 }
1f221284
JN		 2016
2017 return valid;
f453ba04 2018}
61e57a8d
AJ		 2019
2020/**
2021 * drm_edid_is_valid - sanity check EDID data
2022 * @edid: EDID data
2023 *
2024 * Sanity-check an entire EDID record (including extensions)
db6cf833
TR		 2025 *
2026 * Return: True if the EDID data is valid, false otherwise.
61e57a8d
AJ		 2027 */
2028bool drm_edid_is_valid(struct edid *edid)
2029{
2030 int i;
61e57a8d
AJ		 2031
2032 if (!edid)
2033 return false;
2034
f1e4c916
JN		 2035 for (i = 0; i < edid_block_count(edid); i++) {
2036 void *block = (void *)edid_block_data(edid, i);
2037
2038 if (!drm_edid_block_valid(block, i, true, NULL))
61e57a8d 2039 return false;
f1e4c916 2040 }
61e57a8d
AJ		 2041
2042 return true;
2043}
3c537889 2044EXPORT_SYMBOL(drm_edid_is_valid);
f453ba04 2045
6c9b3db7
JN		 2046/**
2047 * drm_edid_valid - sanity check EDID data
2048 * @drm_edid: EDID data
2049 *
2050 * Sanity check an EDID. Cross check block count against allocated size and
2051 * checksum the blocks.
2052 *
2053 * Return: True if the EDID data is valid, false otherwise.
2054 */
2055bool drm_edid_valid(const struct drm_edid *drm_edid)
2056{
2057 int i;
2058
2059 if (!drm_edid)
2060 return false;
2061
2062 if (edid_size_by_blocks(__drm_edid_block_count(drm_edid)) != drm_edid->size)
2063 return false;
2064
2065 for (i = 0; i < drm_edid_block_count(drm_edid); i++) {
2066 const void *block = drm_edid_block_data(drm_edid, i);
2067
2068 if (!edid_block_valid(block, i == 0))
2069 return false;
2070 }
2071
2072 return true;
2073}
2074EXPORT_SYMBOL(drm_edid_valid);
2075
89f4b4c5 2076static struct edid *edid_filter_invalid_blocks(struct edid *edid,
407d63b3 2077 size_t *alloc_size)
4ec53461 2078{
89f4b4c5
JN		 2079 struct edid *new;
2080 int i, valid_blocks = 0;
4ec53461 2081
18e3c1d5
JN		 2082 /*
2083 * Note: If the EDID uses HF-EEODB, but has invalid blocks, we'll revert
2084 * back to regular extension count here. We don't want to start
2085 * modifying the HF-EEODB extension too.
2086 */
89f4b4c5
JN		 2087 for (i = 0; i < edid_block_count(edid); i++) {
2088 const void *src_block = edid_block_data(edid, i);
407d63b3 2089
89f4b4c5
JN		 2090 if (edid_block_valid(src_block, i == 0)) {
2091 void *dst_block = (void *)edid_block_data(edid, valid_blocks);
4ec53461 2092
89f4b4c5
JN		 2093 memmove(dst_block, src_block, EDID_LENGTH);
2094 valid_blocks++;
2095 }
2096 }
4ec53461 2097
89f4b4c5
JN		 2098 /* We already trusted the base block to be valid here... */
2099 if (WARN_ON(!valid_blocks)) {
2100 kfree(edid);
2101 return NULL;
4ec53461
JN		 2102 }
2103
89f4b4c5
JN		 2104 edid->extensions = valid_blocks - 1;
2105 edid->checksum = edid_block_compute_checksum(edid);
4ec53461 2106
89f4b4c5
JN		 2107 *alloc_size = edid_size_by_blocks(valid_blocks);
2108
2109 new = krealloc(edid, *alloc_size, GFP_KERNEL);
2110 if (!new)
2111 kfree(edid);
4ec53461
JN		 2112
2113 return new;
2114}
2115
61e57a8d
AJ		 2116#define DDC_SEGMENT_ADDR 0x30
2117/**
db6cf833 2118 * drm_do_probe_ddc_edid() - get EDID information via I2C
7c58e87e 2119 * @data: I2C device adapter
fc66811c
DV		 2120 * @buf: EDID data buffer to be filled
2121 * @block: 128 byte EDID block to start fetching from
2122 * @len: EDID data buffer length to fetch
2123 *
db6cf833 2124 * Try to fetch EDID information by calling I2C driver functions.
61e57a8d 2125 *
db6cf833 2126 * Return: 0 on success or -1 on failure.
61e57a8d
AJ		 2127 */
2128static int
18df89fe 2129drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
61e57a8d 2130{
18df89fe 2131 struct i2c_adapter *adapter = data;
61e57a8d 2132 unsigned char start = block * EDID_LENGTH;
cd004b3f
S		 2133 unsigned char segment = block >> 1;
2134 unsigned char xfers = segment ? 3 : 2;
4819d2e4
CW		 2135 int ret, retries = 5;
2136
db6cf833
TR		 2137 /*
2138 * The core I2C driver will automatically retry the transfer if the
4819d2e4
CW		 2139 * adapter reports EAGAIN. However, we find that bit-banging transfers
2140 * are susceptible to errors under a heavily loaded machine and
2141 * generate spurious NAKs and timeouts. Retrying the transfer
2142 * of the individual block a few times seems to overcome this.
2143 */
2144 do {
2145 struct i2c_msg msgs[] = {
2146 {
cd004b3f
S		 2147 .addr = DDC_SEGMENT_ADDR,
2148 .flags = 0,
2149 .len = 1,
2150 .buf = &segment,
2151 }, {
4819d2e4
CW		 2152 .addr = DDC_ADDR,
2153 .flags = 0,
2154 .len = 1,
2155 .buf = &start,
2156 }, {
2157 .addr = DDC_ADDR,
2158 .flags = I2C_M_RD,
2159 .len = len,
2160 .buf = buf,
2161 }
2162 };
cd004b3f 2163
db6cf833
TR		 2164 /*
2165 * Avoid sending the segment addr to not upset non-compliant
2166 * DDC monitors.
2167 */
cd004b3f
S		 2168 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
2169
9292f37e
ED		 2170 if (ret == -ENXIO) {
2171 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
2172 adapter->name);
2173 break;
2174 }
cd004b3f 2175 } while (ret != xfers && --retries);
4819d2e4 2176
cd004b3f 2177 return ret == xfers ? 0 : -1;
61e57a8d
AJ		 2178}
2179
14544d09 2180static void connector_bad_edid(struct drm_connector *connector,
63cae081 2181 const struct edid *edid, int num_blocks)
14544d09
CW		 2182{
2183 int i;
97794170
DA		 2184 u8 last_block;
2185
2186 /*
2187 * 0x7e in the EDID is the number of extension blocks. The EDID
2188 * is 1 (base block) + num_ext_blocks big. That means we can think
2189 * of 0x7e in the EDID of the _index_ of the last block in the
2190 * combined chunk of memory.
2191 */
63cae081 2192 last_block = edid->extensions;
e11f5bd8
JFZ		 2193
2194 /* Calculate real checksum for the last edid extension block data */
97794170
DA		 2195 if (last_block < num_blocks)
2196 connector->real_edid_checksum =
63cae081 2197 edid_block_compute_checksum(edid + last_block);
14544d09 2198
f0a8f533 2199 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
14544d09
CW		 2200 return;
2201
66d17ecd
JN		 2202 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID is invalid:\n",
2203 connector->base.id, connector->name);
63cae081
JN		 2204 for (i = 0; i < num_blocks; i++)
2205 edid_block_dump(KERN_DEBUG, edid + i, i);
14544d09
CW		 2206}
2207
56a2b7f2 2208/* Get override or firmware EDID */
794aca0e 2209static const struct drm_edid *drm_edid_override_get(struct drm_connector *connector)
56a2b7f2 2210{
794aca0e 2211 const struct drm_edid *override = NULL;
56a2b7f2 2212
90b575f5
JN		 2213 mutex_lock(&connector->edid_override_mutex);
2214
2215 if (connector->edid_override)
794aca0e 2216 override = drm_edid_dup(connector->edid_override);
90b575f5
JN		 2217
2218 mutex_unlock(&connector->edid_override_mutex);
56a2b7f2
JN		 2219
2220 if (!override)
a05992d5 2221 override = drm_edid_load_firmware(connector);
56a2b7f2
JN		 2222
2223 return IS_ERR(override) ? NULL : override;
2224}
2225
91ec9ab4
JN		 2226/* For debugfs edid_override implementation */
2227int drm_edid_override_show(struct drm_connector *connector, struct seq_file *m)
2228{
90b575f5 2229 const struct drm_edid *drm_edid;
91ec9ab4 2230
90b575f5
JN		 2231 mutex_lock(&connector->edid_override_mutex);
2232
2233 drm_edid = connector->edid_override;
2234 if (drm_edid)
2235 seq_write(m, drm_edid->edid, drm_edid->size);
2236
2237 mutex_unlock(&connector->edid_override_mutex);
91ec9ab4
JN		 2238
2239 return 0;
2240}
2241
6aa145bc
JN		 2242/* For debugfs edid_override implementation */
2243int drm_edid_override_set(struct drm_connector *connector, const void *edid,
2244 size_t size)
2245{
90b575f5 2246 const struct drm_edid *drm_edid;
6aa145bc 2247
90b575f5
JN		 2248 drm_edid = drm_edid_alloc(edid, size);
2249 if (!drm_edid_valid(drm_edid)) {
2250 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override invalid\n",
2251 connector->base.id, connector->name);
2252 drm_edid_free(drm_edid);
6aa145bc 2253 return -EINVAL;
90b575f5 2254 }
6aa145bc 2255
2c9332de
JN		 2256 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override set\n",
2257 connector->base.id, connector->name);
2258
90b575f5 2259 mutex_lock(&connector->edid_override_mutex);
6aa145bc 2260
90b575f5
JN		 2261 drm_edid_free(connector->edid_override);
2262 connector->edid_override = drm_edid;
2263
2264 mutex_unlock(&connector->edid_override_mutex);
2265
2266 return 0;
6aa145bc
JN		 2267}
2268
2269/* For debugfs edid_override implementation */
2270int drm_edid_override_reset(struct drm_connector *connector)
2271{
2c9332de
JN		 2272 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override reset\n",
2273 connector->base.id, connector->name);
2274
90b575f5
JN		 2275 mutex_lock(&connector->edid_override_mutex);
2276
2277 drm_edid_free(connector->edid_override);
2278 connector->edid_override = NULL;
2279
2280 mutex_unlock(&connector->edid_override_mutex);
2281
2282 return 0;
6aa145bc
JN		 2283}
2284
48eaeb76 2285/**
019b9387 2286 * drm_edid_override_connector_update - add modes from override/firmware EDID
48eaeb76
JN		 2287 * @connector: connector we're probing
2288 *
2289 * Add modes from the override/firmware EDID, if available. Only to be used from
2290 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
2291 * failed during drm_get_edid() and caused the override/firmware EDID to be
2292 * skipped.
2293 *
2294 * Return: The number of modes added or 0 if we couldn't find any.
2295 */
019b9387 2296int drm_edid_override_connector_update(struct drm_connector *connector)
48eaeb76 2297{
794aca0e 2298 const struct drm_edid *override;
48eaeb76
JN		 2299 int num_modes = 0;
2300
794aca0e 2301 override = drm_edid_override_get(connector);
48eaeb76 2302 if (override) {
759f14e2
JN		 2303 if (drm_edid_connector_update(connector, override) == 0)
2304 num_modes = drm_edid_connector_add_modes(connector);
794aca0e
JN		 2305
2306 drm_edid_free(override);
48eaeb76 2307
e1e7bc48
JN		 2308 drm_dbg_kms(connector->dev,
2309 "[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
2310 connector->base.id, connector->name, num_modes);
48eaeb76
JN		 2311 }
2312
2313 return num_modes;
2314}
019b9387 2315EXPORT_SYMBOL(drm_edid_override_connector_update);
48eaeb76 2316
89fb7536
JN		 2317typedef int read_block_fn(void *context, u8 *buf, unsigned int block, size_t len);
2318
2deaf1c2
JN		 2319static enum edid_block_status edid_block_read(void *block, unsigned int block_num,
2320 read_block_fn read_block,
2321 void *context)
2322{
2323 enum edid_block_status status;
2324 bool is_base_block = block_num == 0;
2325 int try;
2326
2327 for (try = 0; try < 4; try++) {
2328 if (read_block(context, block, block_num, EDID_LENGTH))
2329 return EDID_BLOCK_READ_FAIL;
2330
2331 status = edid_block_check(block, is_base_block);
2332 if (status == EDID_BLOCK_HEADER_REPAIR) {
2333 edid_header_fix(block);
2334
2335 /* Retry with fixed header, update status if that worked. */
2336 status = edid_block_check(block, is_base_block);
2337 if (status == EDID_BLOCK_OK)
2338 status = EDID_BLOCK_HEADER_FIXED;
2339 }
2340
2341 if (edid_block_status_valid(status, edid_block_tag(block)))
2342 break;
2343
2344 /* Fail early for unrepairable base block all zeros. */
2345 if (try == 0 && is_base_block && status == EDID_BLOCK_ZERO)
2346 break;
2347 }
2348
2349 return status;
2350}
2351
6537f79a
JN		 2352static struct edid *_drm_do_get_edid(struct drm_connector *connector,
2353 read_block_fn read_block, void *context,
2354 size_t *size)
61e57a8d 2355{
c12561ce 2356 enum edid_block_status status;
18e3c1d5 2357 int i, num_blocks, invalid_blocks = 0;
794aca0e 2358 const struct drm_edid *override;
b3eb97b6 2359 struct edid *edid, *new;
407d63b3 2360 size_t alloc_size = EDID_LENGTH;
53fd40a9 2361
794aca0e
JN		 2362 override = drm_edid_override_get(connector);
2363 if (override) {
2364 alloc_size = override->size;
2365 edid = kmemdup(override->edid, alloc_size, GFP_KERNEL);
2366 drm_edid_free(override);
2367 if (!edid)
2368 return NULL;
1c788f69 2369 goto ok;
794aca0e 2370 }
61e57a8d 2371
407d63b3 2372 edid = kmalloc(alloc_size, GFP_KERNEL);
e7bd95a7 2373 if (!edid)
61e57a8d 2374 return NULL;
61e57a8d 2375
c12561ce
JN		 2376 status = edid_block_read(edid, 0, read_block, context);
2377
2378 edid_block_status_print(status, edid, 0);
2379
2380 if (status == EDID_BLOCK_READ_FAIL)
1c788f69 2381 goto fail;
c12561ce
JN		 2382
2383 /* FIXME: Clarify what a corrupt EDID actually means. */
2384 if (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION)
2385 connector->edid_corrupt = false;
2386 else
2387 connector->edid_corrupt = true;
2388
2389 if (!edid_block_status_valid(status, edid_block_tag(edid))) {
2390 if (status == EDID_BLOCK_ZERO)
2391 connector->null_edid_counter++;
2392
2393 connector_bad_edid(connector, edid, 1);
1c788f69 2394 goto fail;
c12561ce
JN		 2395 }
2396
f1e4c916 2397 if (!edid_extension_block_count(edid))
1c788f69 2398 goto ok;
61e57a8d 2399
407d63b3
JN		 2400 alloc_size = edid_size(edid);
2401 new = krealloc(edid, alloc_size, GFP_KERNEL);
61e57a8d 2402 if (!new)
1c788f69 2403 goto fail;
f14f3686 2404 edid = new;
61e57a8d 2405
18e3c1d5
JN		 2406 num_blocks = edid_block_count(edid);
2407 for (i = 1; i < num_blocks; i++) {
f1e4c916 2408 void *block = (void *)edid_block_data(edid, i);
a28187cc 2409
f1e4c916 2410 status = edid_block_read(block, i, read_block, context);
d3da3f40 2411
f1e4c916 2412 edid_block_status_print(status, block, i);
f934ec8c 2413
d3da3f40
JN		 2414 if (!edid_block_status_valid(status, edid_block_tag(block))) {
2415 if (status == EDID_BLOCK_READ_FAIL)
1c788f69 2416 goto fail;
ccc97def 2417 invalid_blocks++;
18e3c1d5
JN		 2418 } else if (i == 1) {
2419 /*
2420 * If the first EDID extension is a CTA extension, and
2421 * the first Data Block is HF-EEODB, override the
2422 * extension block count.
2423 *
2424 * Note: HF-EEODB could specify a smaller extension
2425 * count too, but we can't risk allocating a smaller
2426 * amount.
2427 */
2428 int eeodb = edid_hfeeodb_block_count(edid);
2429
2430 if (eeodb > num_blocks) {
2431 num_blocks = eeodb;
2432 alloc_size = edid_size_by_blocks(num_blocks);
2433 new = krealloc(edid, alloc_size, GFP_KERNEL);
2434 if (!new)
2435 goto fail;
2436 edid = new;
2437 }
d3da3f40 2438 }
0ea75e23
ST		 2439 }
2440
ccc97def 2441 if (invalid_blocks) {
18e3c1d5 2442 connector_bad_edid(connector, edid, num_blocks);
14544d09 2443
89f4b4c5 2444 edid = edid_filter_invalid_blocks(edid, &alloc_size);
61e57a8d
AJ		 2445 }
2446
1c788f69 2447ok:
6537f79a
JN		 2448 if (size)
2449 *size = alloc_size;
2450
e9a9e076 2451 return edid;
61e57a8d 2452
1c788f69 2453fail:
f14f3686 2454 kfree(edid);
61e57a8d
AJ		 2455 return NULL;
2456}
6537f79a 2457
3d1ab66e
JN		 2458/**
2459 * drm_edid_raw - Get a pointer to the raw EDID data.
2460 * @drm_edid: drm_edid container
2461 *
2462 * Get a pointer to the raw EDID data.
2463 *
2464 * This is for transition only. Avoid using this like the plague.
2465 *
2466 * Return: Pointer to raw EDID data.
2467 */
2468const struct edid *drm_edid_raw(const struct drm_edid *drm_edid)
2469{
2470 if (!drm_edid || !drm_edid->size)
2471 return NULL;
2472
2473 /*
2474 * Do not return pointers where relying on EDID extension count would
2475 * lead to buffer overflow.
2476 */
2477 if (WARN_ON(edid_size(drm_edid->edid) > drm_edid->size))
2478 return NULL;
2479
2480 return drm_edid->edid;
2481}
2482EXPORT_SYMBOL(drm_edid_raw);
2483
6537f79a
JN		 2484/* Allocate struct drm_edid container *without* duplicating the edid data */
2485static const struct drm_edid *_drm_edid_alloc(const void *edid, size_t size)
2486{
2487 struct drm_edid *drm_edid;
2488
2489 if (!edid || !size || size < EDID_LENGTH)
2490 return NULL;
2491
2492 drm_edid = kzalloc(sizeof(*drm_edid), GFP_KERNEL);
2493 if (drm_edid) {
2494 drm_edid->edid = edid;
2495 drm_edid->size = size;
2496 }
2497
2498 return drm_edid;
2499}
2500
2501/**
2502 * drm_edid_alloc - Allocate a new drm_edid container
2503 * @edid: Pointer to raw EDID data
2504 * @size: Size of memory allocated for EDID
2505 *
2506 * Allocate a new drm_edid container. Do not calculate edid size from edid, pass
2507 * the actual size that has been allocated for the data. There is no validation
2508 * of the raw EDID data against the size, but at least the EDID base block must
2509 * fit in the buffer.
2510 *
2511 * The returned pointer must be freed using drm_edid_free().
2512 *
2513 * Return: drm_edid container, or NULL on errors
2514 */
2515const struct drm_edid *drm_edid_alloc(const void *edid, size_t size)
2516{
2517 const struct drm_edid *drm_edid;
2518
2519 if (!edid || !size || size < EDID_LENGTH)
2520 return NULL;
2521
2522 edid = kmemdup(edid, size, GFP_KERNEL);
2523 if (!edid)
2524 return NULL;
2525
2526 drm_edid = _drm_edid_alloc(edid, size);
2527 if (!drm_edid)
2528 kfree(edid);
2529
2530 return drm_edid;
2531}
2532EXPORT_SYMBOL(drm_edid_alloc);
2533
2534/**
2535 * drm_edid_dup - Duplicate a drm_edid container
2536 * @drm_edid: EDID to duplicate
2537 *
2538 * The returned pointer must be freed using drm_edid_free().
2539 *
2540 * Returns: drm_edid container copy, or NULL on errors
2541 */
2542const struct drm_edid *drm_edid_dup(const struct drm_edid *drm_edid)
2543{
2544 if (!drm_edid)
2545 return NULL;
2546
2547 return drm_edid_alloc(drm_edid->edid, drm_edid->size);
2548}
2549EXPORT_SYMBOL(drm_edid_dup);
2550
2551/**
2552 * drm_edid_free - Free the drm_edid container
2553 * @drm_edid: EDID to free
2554 */
2555void drm_edid_free(const struct drm_edid *drm_edid)
2556{
2557 if (!drm_edid)
2558 return;
2559
2560 kfree(drm_edid->edid);
2561 kfree(drm_edid);
2562}
2563EXPORT_SYMBOL(drm_edid_free);
2564
61e57a8d 2565/**
db6cf833
TR		 2566 * drm_probe_ddc() - probe DDC presence
2567 * @adapter: I2C adapter to probe
fc66811c 2568 *
db6cf833 2569 * Return: True on success, false on failure.
61e57a8d 2570 */
fbff4690 2571bool
61e57a8d
AJ		 2572drm_probe_ddc(struct i2c_adapter *adapter)
2573{
2574 unsigned char out;
2575
2576 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
2577}
fbff4690 2578EXPORT_SYMBOL(drm_probe_ddc);
61e57a8d
AJ		 2579
2580/**
2581 * drm_get_edid - get EDID data, if available
2582 * @connector: connector we're probing
db6cf833 2583 * @adapter: I2C adapter to use for DDC
61e57a8d 2584 *
db6cf833 2585 * Poke the given I2C channel to grab EDID data if possible. If found,
61e57a8d
AJ		 2586 * attach it to the connector.
2587 *
db6cf833 2588 * Return: Pointer to valid EDID or NULL if we couldn't find any.
61e57a8d
AJ		 2589 */
2590struct edid *drm_get_edid(struct drm_connector *connector,
2591 struct i2c_adapter *adapter)
2592{
5186421c
SL		 2593 struct edid *edid;
2594
15f080f0
JN		 2595 if (connector->force == DRM_FORCE_OFF)
2596 return NULL;
2597
2598 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
18df89fe 2599 return NULL;
61e57a8d 2600
6537f79a 2601 edid = _drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter, NULL);
5186421c
SL		 2602 drm_connector_update_edid_property(connector, edid);
2603 return edid;
61e57a8d
AJ		 2604}
2605EXPORT_SYMBOL(drm_get_edid);
2606
6537f79a
JN		 2607/**
2608 * drm_edid_read_custom - Read EDID data using given EDID block read function
2609 * @connector: Connector to use
2610 * @read_block: EDID block read function
2611 * @context: Private data passed to the block read function
2612 *
2613 * When the I2C adapter connected to the DDC bus is hidden behind a device that
2614 * exposes a different interface to read EDID blocks this function can be used
2615 * to get EDID data using a custom block read function.
2616 *
2617 * As in the general case the DDC bus is accessible by the kernel at the I2C
2618 * level, drivers must make all reasonable efforts to expose it as an I2C
2619 * adapter and use drm_edid_read() or drm_edid_read_ddc() instead of abusing
2620 * this function.
2621 *
2622 * The EDID may be overridden using debugfs override_edid or firmware EDID
a05992d5 2623 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
6537f79a
JN		 2624 * order. Having either of them bypasses actual EDID reads.
2625 *
2626 * The returned pointer must be freed using drm_edid_free().
2627 *
2628 * Return: Pointer to EDID, or NULL if probe/read failed.
2629 */
2630const struct drm_edid *drm_edid_read_custom(struct drm_connector *connector,
2631 read_block_fn read_block,
2632 void *context)
2633{
2634 const struct drm_edid *drm_edid;
2635 struct edid *edid;
2636 size_t size = 0;
2637
2638 edid = _drm_do_get_edid(connector, read_block, context, &size);
2639 if (!edid)
2640 return NULL;
2641
2642 /* Sanity check for now */
2643 drm_WARN_ON(connector->dev, !size);
2644
2645 drm_edid = _drm_edid_alloc(edid, size);
2646 if (!drm_edid)
2647 kfree(edid);
2648
2649 return drm_edid;
2650}
2651EXPORT_SYMBOL(drm_edid_read_custom);
2652
2653/**
2654 * drm_edid_read_ddc - Read EDID data using given I2C adapter
2655 * @connector: Connector to use
2656 * @adapter: I2C adapter to use for DDC
2657 *
2658 * Read EDID using the given I2C adapter.
2659 *
2660 * The EDID may be overridden using debugfs override_edid or firmware EDID
a05992d5 2661 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
6537f79a
JN		 2662 * order. Having either of them bypasses actual EDID reads.
2663 *
2664 * Prefer initializing connector->ddc with drm_connector_init_with_ddc() and
2665 * using drm_edid_read() instead of this function.
2666 *
2667 * The returned pointer must be freed using drm_edid_free().
2668 *
2669 * Return: Pointer to EDID, or NULL if probe/read failed.
2670 */
2671const struct drm_edid *drm_edid_read_ddc(struct drm_connector *connector,
2672 struct i2c_adapter *adapter)
2673{
2674 const struct drm_edid *drm_edid;
2675
2676 if (connector->force == DRM_FORCE_OFF)
2677 return NULL;
2678
2679 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2680 return NULL;
2681
2682 drm_edid = drm_edid_read_custom(connector, drm_do_probe_ddc_edid, adapter);
2683
2684 /* Note: Do *not* call connector updates here. */
2685
2686 return drm_edid;
2687}
2688EXPORT_SYMBOL(drm_edid_read_ddc);
2689
2690/**
2691 * drm_edid_read - Read EDID data using connector's I2C adapter
2692 * @connector: Connector to use
2693 *
2694 * Read EDID using the connector's I2C adapter.
2695 *
2696 * The EDID may be overridden using debugfs override_edid or firmware EDID
a05992d5 2697 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
6537f79a
JN		 2698 * order. Having either of them bypasses actual EDID reads.
2699 *
2700 * The returned pointer must be freed using drm_edid_free().
2701 *
2702 * Return: Pointer to EDID, or NULL if probe/read failed.
2703 */
2704const struct drm_edid *drm_edid_read(struct drm_connector *connector)
2705{
2706 if (drm_WARN_ON(connector->dev, !connector->ddc))
2707 return NULL;
2708
2709 return drm_edid_read_ddc(connector, connector->ddc);
2710}
2711EXPORT_SYMBOL(drm_edid_read);
2712
3ddbd345
JN		 2713/**
2714 * drm_edid_get_product_id - Get the vendor and product identification
2715 * @drm_edid: EDID
2716 * @id: Where to place the product id
2717 */
2718void drm_edid_get_product_id(const struct drm_edid *drm_edid,
2719 struct drm_edid_product_id *id)
2720{
2721 if (drm_edid && drm_edid->edid && drm_edid->size >= EDID_LENGTH)
2722 memcpy(id, &drm_edid->edid->product_id, sizeof(*id));
2723 else
2724 memset(id, 0, sizeof(*id));
2725}
2726EXPORT_SYMBOL(drm_edid_get_product_id);
2727
3f56e551
JN		 2728static void decode_date(struct seq_buf *s, const struct drm_edid_product_id *id)
2729{
2730 int week = id->week_of_manufacture;
2731 int year = id->year_of_manufacture + 1990;
2732
2733 if (week == 0xff)
2734 seq_buf_printf(s, "model year: %d", year);
2735 else if (!week)
2736 seq_buf_printf(s, "year of manufacture: %d", year);
2737 else
2738 seq_buf_printf(s, "week/year of manufacture: %d/%d", week, year);
2739}
2740
2741/**
2742 * drm_edid_print_product_id - Print decoded product id to printer
2743 * @p: drm printer
2744 * @id: EDID product id
2745 * @raw: If true, also print the raw hex
2746 *
2747 * See VESA E-EDID 1.4 section 3.4.
2748 */
2749void drm_edid_print_product_id(struct drm_printer *p,
2750 const struct drm_edid_product_id *id, bool raw)
2751{
2752 DECLARE_SEQ_BUF(date, 40);
2753 char vend[4];
2754
2755 drm_edid_decode_mfg_id(be16_to_cpu(id->manufacturer_name), vend);
2756
2757 decode_date(&date, id);
2758
2759 drm_printf(p, "manufacturer name: %s, product code: %u, serial number: %u, %s\n",
2760 vend, le16_to_cpu(id->product_code),
2761 le32_to_cpu(id->serial_number), seq_buf_str(&date));
2762
2763 if (raw)
2764 drm_printf(p, "raw product id: %*ph\n", (int)sizeof(*id), id);
2765
2766 WARN_ON(seq_buf_has_overflowed(&date));
2767}
2768EXPORT_SYMBOL(drm_edid_print_product_id);
2769
a0b39da1
HYW		 2770/**
2771 * drm_edid_get_panel_id - Get a panel's ID from EDID
2772 * @drm_edid: EDID that contains panel ID.
2773 *
2774 * This function uses the first block of the EDID of a panel and (assuming
2775 * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value
2776 * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's
2777 * supposed to be different for each different modem of panel.
2778 *
2779 * Return: A 32-bit ID that should be different for each make/model of panel.
2780 * See the functions drm_edid_encode_panel_id() and
2781 * drm_edid_decode_panel_id() for some details on the structure of this
2782 * ID. Return 0 if the EDID size is less than a base block.
2783 */
2784u32 drm_edid_get_panel_id(const struct drm_edid *drm_edid)
d9f91a10 2785{
a0b39da1
HYW		 2786 const struct edid *edid = drm_edid->edid;
2787
2788 if (drm_edid->size < EDID_LENGTH)
2789 return 0;
2790
d9f91a10 2791 /*
e8de4d55
DA		 2792 * We represent the ID as a 32-bit number so it can easily be compared
2793 * with "==".
d9f91a10
DA		 2794 *
2795 * NOTE that we deal with endianness differently for the top half
2796 * of this ID than for the bottom half. The bottom half (the product
2797 * id) gets decoded as little endian by the EDID_PRODUCT_ID because
2798 * that's how everyone seems to interpret it. The top half (the mfg_id)
2799 * gets stored as big endian because that makes
2800 * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier
2801 * to write (it's easier to extract the ASCII). It doesn't really
2802 * matter, though, as long as the number here is unique.
2803 */
2804 return (u32)edid->mfg_id[0] << 24 |
2805 (u32)edid->mfg_id[1] << 16 |
2806 (u32)EDID_PRODUCT_ID(edid);
2807}
a0b39da1 2808EXPORT_SYMBOL(drm_edid_get_panel_id);
d9f91a10
DA		 2809
2810/**
a0b39da1 2811 * drm_edid_read_base_block - Get a panel's EDID base block
d9f91a10
DA		 2812 * @adapter: I2C adapter to use for DDC
2813 *
a0b39da1
HYW		 2814 * This function returns the drm_edid containing the first block of the EDID of
2815 * a panel.
d9f91a10
DA		 2816 *
2817 * This function is intended to be used during early probing on devices where
2818 * more than one panel might be present. Because of its intended use it must
a0b39da1
HYW		 2819 * assume that the EDID of the panel is correct, at least as far as the base
2820 * block is concerned (in other words, we don't process any overrides here).
2821 *
2822 * Caller should call drm_edid_free() after use.
d9f91a10
DA		 2823 *
2824 * NOTE: it's expected that this function and drm_do_get_edid() will both
2825 * be read the EDID, but there is no caching between them. Since we're only
2826 * reading the first block, hopefully this extra overhead won't be too big.
2827 *
a0b39da1
HYW		 2828 * WARNING: Only use this function when the connector is unknown. For example,
2829 * during the early probe of panel. The EDID read from the function is temporary
2830 * and should be replaced by the full EDID returned from other drm_edid_read.
2831 *
2832 * Return: Pointer to allocated EDID base block, or NULL on any failure.
d9f91a10 2833 */
a0b39da1 2834const struct drm_edid *drm_edid_read_base_block(struct i2c_adapter *adapter)
d9f91a10 2835{
2deaf1c2
JN		 2836 enum edid_block_status status;
2837 void *base_block;
2deaf1c2 2838
4d8457fe 2839 base_block = kzalloc(EDID_LENGTH, GFP_KERNEL);
2deaf1c2 2840 if (!base_block)
a0b39da1 2841 return NULL;
d9f91a10 2842
2deaf1c2
JN		 2843 status = edid_block_read(base_block, 0, drm_do_probe_ddc_edid, adapter);
2844
2845 edid_block_status_print(status, base_block, 0);
2846
a0b39da1 2847 if (!edid_block_status_valid(status, edid_block_tag(base_block))) {
69c7717c 2848 edid_block_dump(KERN_NOTICE, base_block, 0);
a0b39da1
HYW		 2849 kfree(base_block);
2850 return NULL;
2851 }
2deaf1c2 2852
a0b39da1 2853 return _drm_edid_alloc(base_block, EDID_LENGTH);
d9f91a10 2854}
a0b39da1 2855EXPORT_SYMBOL(drm_edid_read_base_block);
d9f91a10 2856
5cb8eaa2
LW		 2857/**
2858 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
2859 * @connector: connector we're probing
2860 * @adapter: I2C adapter to use for DDC
2861 *
2862 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
2863 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
2864 * switch DDC to the GPU which is retrieving EDID.
2865 *
2866 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2867 */
2868struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
2869 struct i2c_adapter *adapter)
2870{
36b73b05
TZ		 2871 struct drm_device *dev = connector->dev;
2872 struct pci_dev *pdev = to_pci_dev(dev->dev);
5cb8eaa2
LW		 2873 struct edid *edid;
2874
36b73b05
TZ		 2875 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev)))
2876 return NULL;
2877
5cb8eaa2
LW		 2878 vga_switcheroo_lock_ddc(pdev);
2879 edid = drm_get_edid(connector, adapter);
2880 vga_switcheroo_unlock_ddc(pdev);
2881
2882 return edid;
2883}
2884EXPORT_SYMBOL(drm_get_edid_switcheroo);
2885
6c46f644
JN		 2886/**
2887 * drm_edid_read_switcheroo - get EDID data for a vga_switcheroo output
2888 * @connector: connector we're probing
2889 * @adapter: I2C adapter to use for DDC
2890 *
2891 * Wrapper around drm_edid_read_ddc() for laptops with dual GPUs using one set
2892 * of outputs. The wrapper adds the requisite vga_switcheroo calls to
2893 * temporarily switch DDC to the GPU which is retrieving EDID.
2894 *
2895 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2896 */
2897const struct drm_edid *drm_edid_read_switcheroo(struct drm_connector *connector,
2898 struct i2c_adapter *adapter)
2899{
2900 struct drm_device *dev = connector->dev;
2901 struct pci_dev *pdev = to_pci_dev(dev->dev);
2902 const struct drm_edid *drm_edid;
2903
2904 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev)))
2905 return NULL;
2906
2907 vga_switcheroo_lock_ddc(pdev);
2908 drm_edid = drm_edid_read_ddc(connector, adapter);
2909 vga_switcheroo_unlock_ddc(pdev);
2910
2911 return drm_edid;
2912}
2913EXPORT_SYMBOL(drm_edid_read_switcheroo);
2914
51f8da59
JN		 2915/**
2916 * drm_edid_duplicate - duplicate an EDID and the extensions
2917 * @edid: EDID to duplicate
2918 *
db6cf833 2919 * Return: Pointer to duplicated EDID or NULL on allocation failure.
51f8da59
JN		 2920 */
2921struct edid *drm_edid_duplicate(const struct edid *edid)
2922{
d60d2bcc
JN		 2923 if (!edid)
2924 return NULL;
2925
f1e4c916 2926 return kmemdup(edid, edid_size(edid), GFP_KERNEL);
51f8da59
JN		 2927}
2928EXPORT_SYMBOL(drm_edid_duplicate);
2929
61e57a8d
AJ		 2930/*** EDID parsing ***/
2931
f453ba04
DA		 2932/**
2933 * edid_get_quirks - return quirk flags for a given EDID
e42192b4 2934 * @drm_edid: EDID to process
f453ba04
DA		 2935 *
2936 * This tells subsequent routines what fixes they need to apply.
7ff53c2f
HYW		 2937 *
2938 * Return: A u32 represents the quirks to apply.
f453ba04 2939 */
e42192b4 2940static u32 edid_get_quirks(const struct drm_edid *drm_edid)
f453ba04 2941{
23c4cfbd 2942 const struct edid_quirk *quirk;
f453ba04
DA		 2943 int i;
2944
2945 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
2946 quirk = &edid_quirk_list[i];
7ff53c2f 2947 if (drm_edid_match(drm_edid, &quirk->ident))
f453ba04
DA		 2948 return quirk->quirks;
2949 }
2950
2951 return 0;
2952}
2953
2954#define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
339d202c 2955#define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
f453ba04 2956
17edb8e1
JN		 2957/*
2958 * Walk the mode list for connector, clearing the preferred status on existing
2959 * modes and setting it anew for the right mode ala quirks.
f453ba04 2960 */
4959b693 2961static void edid_fixup_preferred(struct drm_connector *connector)
f453ba04 2962{
4959b693 2963 const struct drm_display_info *info = &connector->display_info;
f453ba04 2964 struct drm_display_mode *t, *cur_mode, *preferred_mode;
f890607b 2965 int target_refresh = 0;
339d202c 2966 int cur_vrefresh, preferred_vrefresh;
f453ba04
DA		 2967
2968 if (list_empty(&connector->probed_modes))
2969 return;
2970
4959b693 2971 if (info->quirks & EDID_QUIRK_PREFER_LARGE_60)
f453ba04 2972 target_refresh = 60;
4959b693 2973 if (info->quirks & EDID_QUIRK_PREFER_LARGE_75)
f453ba04
DA		 2974 target_refresh = 75;
2975
2976 preferred_mode = list_first_entry(&connector->probed_modes,
2977 struct drm_display_mode, head);
2978
2979 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
2980 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
2981
2982 if (cur_mode == preferred_mode)
2983 continue;
2984
2985 /* Largest mode is preferred */
2986 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
2987 preferred_mode = cur_mode;
2988
0425662f
VS		 2989 cur_vrefresh = drm_mode_vrefresh(cur_mode);
2990 preferred_vrefresh = drm_mode_vrefresh(preferred_mode);
f453ba04
DA		 2991 /* At a given size, try to get closest to target refresh */
2992 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
339d202c
AD		 2993 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
2994 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
f453ba04
DA		 2995 preferred_mode = cur_mode;
2996 }
2997 }
2998
2999 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
3000}
3001
f6e252ba
AJ		 3002static bool
3003mode_is_rb(const struct drm_display_mode *mode)
3004{
3005 return (mode->htotal - mode->hdisplay == 160) &&
3006 (mode->hsync_end - mode->hdisplay == 80) &&
3007 (mode->hsync_end - mode->hsync_start == 32) &&
3008 (mode->vsync_start - mode->vdisplay == 3);
3009}
3010
33c7531d
AJ		 3011/*
3012 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
3013 * @dev: Device to duplicate against
3014 * @hsize: Mode width
3015 * @vsize: Mode height
3016 * @fresh: Mode refresh rate
f6e252ba 3017 * @rb: Mode reduced-blanking-ness
33c7531d
AJ		 3018 *
3019 * Walk the DMT mode list looking for a match for the given parameters.
db6cf833
TR		 3020 *
3021 * Return: A newly allocated copy of the mode, or NULL if not found.
33c7531d 3022 */
1d42bbc8 3023struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
f6e252ba
AJ		 3024 int hsize, int vsize, int fresh,
3025 bool rb)
559ee21d 3026{
07a5e632 3027 int i;
559ee21d 3028
a6b21831 3029 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
b1f559ec 3030 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
948de842 3031
f8b46a05
AJ		 3032 if (hsize != ptr->hdisplay)
3033 continue;
3034 if (vsize != ptr->vdisplay)
3035 continue;
3036 if (fresh != drm_mode_vrefresh(ptr))
3037 continue;
f6e252ba
AJ		 3038 if (rb != mode_is_rb(ptr))
3039 continue;
f8b46a05
AJ		 3040
3041 return drm_mode_duplicate(dev, ptr);
559ee21d 3042 }
f8b46a05
AJ		 3043
3044 return NULL;
559ee21d 3045}
1d42bbc8 3046EXPORT_SYMBOL(drm_mode_find_dmt);
23425cae 3047
e379814b 3048static bool is_display_descriptor(const struct detailed_timing *descriptor, u8 type)
a7a131ac 3049{
e379814b
JN		 3050 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
3051 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.pad1) != 2);
3052 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.type) != 3);
3053
3054 return descriptor->pixel_clock == 0 &&
3055 descriptor->data.other_data.pad1 == 0 &&
3056 descriptor->data.other_data.type == type;
a7a131ac
VS		 3057}
3058
a9b1f15f 3059static bool is_detailed_timing_descriptor(const struct detailed_timing *descriptor)
f447dd1f 3060{
a9b1f15f
JN		 3061 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
3062
3063 return descriptor->pixel_clock != 0;
f447dd1f
VS		 3064}
3065
4194442d 3066typedef void detailed_cb(const struct detailed_timing *timing, void *closure);
d1ff6409 3067
4d76a221 3068static void
eed628f1 3069cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
4d76a221 3070{
7304b981 3071 int i, n;
4966b2a9 3072 u8 d = ext[0x02];
eed628f1 3073 const u8 *det_base = ext + d;
4d76a221 3074
7304b981
VS		 3075 if (d < 4 || d > 127)
3076 return;
3077
4966b2a9 3078 n = (127 - d) / 18;
4d76a221 3079 for (i = 0; i < n; i++)
eed628f1 3080 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
4d76a221
AJ		 3081}
3082
cbba98f8 3083static void
eed628f1 3084vtb_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
cbba98f8
AJ		 3085{
3086 unsigned int i, n = min((int)ext[0x02], 6);
eed628f1 3087 const u8 *det_base = ext + 5;
cbba98f8
AJ		 3088
3089 if (ext[0x01] != 1)
3090 return; /* unknown version */
3091
3092 for (i = 0; i < n; i++)
eed628f1 3093 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
cbba98f8
AJ		 3094}
3095
45aa2336
JN		 3096static void drm_for_each_detailed_block(const struct drm_edid *drm_edid,
3097 detailed_cb *cb, void *closure)
d1ff6409 3098{
ab1747cc
JN		 3099 struct drm_edid_iter edid_iter;
3100 const u8 *ext;
d1ff6409 3101 int i;
d1ff6409 3102
45aa2336 3103 if (!drm_edid)
d1ff6409
AJ		 3104 return;
3105
3106 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
45aa2336 3107 cb(&drm_edid->edid->detailed_timings[i], closure);
d1ff6409 3108
bbded689 3109 drm_edid_iter_begin(drm_edid, &edid_iter);
ab1747cc 3110 drm_edid_iter_for_each(ext, &edid_iter) {
4d76a221
AJ		 3111 switch (*ext) {
3112 case CEA_EXT:
3113 cea_for_each_detailed_block(ext, cb, closure);
3114 break;
cbba98f8
AJ		 3115 case VTB_EXT:
3116 vtb_for_each_detailed_block(ext, cb, closure);
3117 break;
4d76a221
AJ		 3118 default:
3119 break;
3120 }
3121 }
ab1747cc 3122 drm_edid_iter_end(&edid_iter);
d1ff6409
AJ		 3123}
3124
3125static void
4194442d 3126is_rb(const struct detailed_timing *descriptor, void *data)
d1ff6409 3127{
90fd588f 3128 bool *res = data;
a7a131ac 3129
90fd588f 3130 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
a7a131ac
VS		 3131 return;
3132
90fd588f
JN		 3133 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3134 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.cvt.flags) != 15);
3135
3136 if (descriptor->data.other_data.data.range.flags == DRM_EDID_CVT_SUPPORT_FLAG &&
afd4429e 3137 descriptor->data.other_data.data.range.formula.cvt.flags & DRM_EDID_CVT_FLAGS_REDUCED_BLANKING)
90fd588f 3138 *res = true;
d1ff6409
AJ		 3139}
3140
3141/* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
3142static bool
874d98ee 3143drm_monitor_supports_rb(const struct drm_edid *drm_edid)
d1ff6409 3144{
874d98ee 3145 if (drm_edid->edid->revision >= 4) {
b196a498 3146 bool ret = false;
948de842 3147
45aa2336 3148 drm_for_each_detailed_block(drm_edid, is_rb, &ret);
d1ff6409
AJ		 3149 return ret;
3150 }
3151
7218779e 3152 return drm_edid_is_digital(drm_edid);
d1ff6409
AJ		 3153}
3154
7a374350 3155static void
4194442d 3156find_gtf2(const struct detailed_timing *descriptor, void *data)
7a374350 3157{
4194442d 3158 const struct detailed_timing **res = data;
a7a131ac 3159
c8a4beba 3160 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
a7a131ac
VS		 3161 return;
3162
c8a4beba
JN		 3163 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3164
afd4429e 3165 if (descriptor->data.other_data.data.range.flags == DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG)
c8a4beba 3166 *res = descriptor;
7a374350
AJ		 3167}
3168
3169/* Secondary GTF curve kicks in above some break frequency */
3170static int
67d87fac 3171drm_gtf2_hbreak(const struct drm_edid *drm_edid)
7a374350 3172{
4194442d 3173 const struct detailed_timing *descriptor = NULL;
c8a4beba 3174
45aa2336 3175 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
948de842 3176
c8a4beba
JN		 3177 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12);
3178
3179 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.hfreq_start_khz * 2 : 0;
7a374350
AJ		 3180}
3181
3182static int
67d87fac 3183drm_gtf2_2c(const struct drm_edid *drm_edid)
7a374350 3184{
4194442d 3185 const struct detailed_timing *descriptor = NULL;
c8a4beba 3186
45aa2336 3187 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
c8a4beba
JN		 3188
3189 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.c) != 13);
948de842 3190
c8a4beba 3191 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.c : 0;
7a374350
AJ		 3192}
3193
3194static int
67d87fac 3195drm_gtf2_m(const struct drm_edid *drm_edid)
7a374350 3196{
4194442d 3197 const struct detailed_timing *descriptor = NULL;
948de842 3198
45aa2336 3199 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
c8a4beba
JN		 3200
3201 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.m) != 14);
3202
3203 return descriptor ? le16_to_cpu(descriptor->data.other_data.data.range.formula.gtf2.m) : 0;
7a374350
AJ		 3204}
3205
3206static int
67d87fac 3207drm_gtf2_k(const struct drm_edid *drm_edid)
7a374350 3208{
4194442d 3209 const struct detailed_timing *descriptor = NULL;
c8a4beba 3210
45aa2336 3211 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
948de842 3212
c8a4beba
JN		 3213 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.k) != 16);
3214
3215 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.k : 0;
7a374350
AJ		 3216}
3217
3218static int
67d87fac 3219drm_gtf2_2j(const struct drm_edid *drm_edid)
7a374350 3220{
4194442d 3221 const struct detailed_timing *descriptor = NULL;
c8a4beba 3222
45aa2336 3223 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
c8a4beba
JN		 3224
3225 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.j) != 17);
948de842 3226
c8a4beba 3227 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.j : 0;
7a374350
AJ		 3228}
3229
bf72b5ef
VS		 3230static void
3231get_timing_level(const struct detailed_timing *descriptor, void *data)
3232{
3233 int *res = data;
3234
3235 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3236 return;
3237
3238 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3239
3240 switch (descriptor->data.other_data.data.range.flags) {
3241 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG:
3242 *res = LEVEL_GTF;
3243 break;
3244 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG:
3245 *res = LEVEL_GTF2;
3246 break;
3247 case DRM_EDID_CVT_SUPPORT_FLAG:
3248 *res = LEVEL_CVT;
3249 break;
3250 default:
3251 break;
3252 }
3253}
3254
17edb8e1 3255/* Get standard timing level (CVT/GTF/DMT). */
67d87fac 3256static int standard_timing_level(const struct drm_edid *drm_edid)
7a374350 3257{
67d87fac
JN		 3258 const struct edid *edid = drm_edid->edid;
3259
bf72b5ef
VS		 3260 if (edid->revision >= 4) {
3261 /*
3262 * If the range descriptor doesn't
3263 * indicate otherwise default to CVT
3264 */
3265 int ret = LEVEL_CVT;
3266
3267 drm_for_each_detailed_block(drm_edid, get_timing_level, &ret);
3268
3269 return ret;
3270 } else if (edid->revision >= 3 && drm_gtf2_hbreak(drm_edid)) {
3271 return LEVEL_GTF2;
3272 } else if (edid->revision >= 2) {
3273 return LEVEL_GTF;
3274 } else {
3275 return LEVEL_DMT;
7a374350 3276 }
7a374350
AJ		 3277}
3278
23425cae
AJ		 3279/*
3280 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
3281 * monitors fill with ascii space (0x20) instead.
3282 */
3283static int
3284bad_std_timing(u8 a, u8 b)
3285{
3286 return (a == 0x00 && b == 0x00) ||
3287 (a == 0x01 && b == 0x01) ||
3288 (a == 0x20 && b == 0x20);
3289}
3290
58911c24
VS		 3291static int drm_mode_hsync(const struct drm_display_mode *mode)
3292{
3293 if (mode->htotal <= 0)
3294 return 0;
3295
3296 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal);
3297}
3298
86101bb7
VS		 3299static struct drm_display_mode *
3300drm_gtf2_mode(struct drm_device *dev,
3301 const struct drm_edid *drm_edid,
3302 int hsize, int vsize, int vrefresh_rate)
3303{
3304 struct drm_display_mode *mode;
3305
3306 /*
3307 * This is potentially wrong if there's ever a monitor with
3308 * more than one ranges section, each claiming a different
3309 * secondary GTF curve. Please don't do that.
3310 */
3311 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
3312 if (!mode)
3313 return NULL;
3314
3315 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(drm_edid)) {
3316 drm_mode_destroy(dev, mode);
3317 mode = drm_gtf_mode_complex(dev, hsize, vsize,
3318 vrefresh_rate, 0, 0,
3319 drm_gtf2_m(drm_edid),
3320 drm_gtf2_2c(drm_edid),
3321 drm_gtf2_k(drm_edid),
3322 drm_gtf2_2j(drm_edid));
3323 }
3324
3325 return mode;
3326}
3327
17edb8e1 3328/*
f453ba04 3329 * Take the standard timing params (in this case width, aspect, and refresh)
5c61259e 3330 * and convert them into a real mode using CVT/GTF/DMT.
f453ba04 3331 */
67d87fac
JN		 3332static struct drm_display_mode *drm_mode_std(struct drm_connector *connector,
3333 const struct drm_edid *drm_edid,
3334 const struct std_timing *t)
f453ba04 3335{
7ca6adb3
AJ		 3336 struct drm_device *dev = connector->dev;
3337 struct drm_display_mode *m, *mode = NULL;
5c61259e
ZY		 3338 int hsize, vsize;
3339 int vrefresh_rate;
0454beab
MD		 3340 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
3341 >> EDID_TIMING_ASPECT_SHIFT;
5c61259e
ZY		 3342 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
3343 >> EDID_TIMING_VFREQ_SHIFT;
67d87fac 3344 int timing_level = standard_timing_level(drm_edid);
5c61259e 3345
23425cae
AJ		 3346 if (bad_std_timing(t->hsize, t->vfreq_aspect))
3347 return NULL;
3348
5c61259e
ZY		 3349 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
3350 hsize = t->hsize * 8 + 248;
3351 /* vrefresh_rate = vfreq + 60 */
3352 vrefresh_rate = vfreq + 60;
3353 /* the vdisplay is calculated based on the aspect ratio */
f066a17d 3354 if (aspect_ratio == 0) {
67d87fac 3355 if (drm_edid->edid->revision < 3)
f066a17d
AJ		 3356 vsize = hsize;
3357 else
3358 vsize = (hsize * 10) / 16;
3359 } else if (aspect_ratio == 1)
f453ba04 3360 vsize = (hsize * 3) / 4;
0454beab 3361 else if (aspect_ratio == 2)
f453ba04
DA		 3362 vsize = (hsize * 4) / 5;
3363 else
3364 vsize = (hsize * 9) / 16;
a0910c8e
AJ		 3365
3366 /* HDTV hack, part 1 */
3367 if (vrefresh_rate == 60 &&
3368 ((hsize == 1360 && vsize == 765) ||
3369 (hsize == 1368 && vsize == 769))) {
3370 hsize = 1366;
3371 vsize = 768;
3372 }
3373
7ca6adb3
AJ		 3374 /*
3375 * If this connector already has a mode for this size and refresh
3376 * rate (because it came from detailed or CVT info), use that
3377 * instead. This way we don't have to guess at interlace or
3378 * reduced blanking.
3379 */
522032da 3380 list_for_each_entry(m, &connector->probed_modes, head)
7ca6adb3
AJ		 3381 if (m->hdisplay == hsize && m->vdisplay == vsize &&
3382 drm_mode_vrefresh(m) == vrefresh_rate)
3383 return NULL;
3384
a0910c8e
AJ		 3385 /* HDTV hack, part 2 */
3386 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
3387 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
d50ba256 3388 false);
a5ef6567
JM		 3389 if (!mode)
3390 return NULL;
559ee21d 3391 mode->hdisplay = 1366;
a4967de6
AJ		 3392 mode->hsync_start = mode->hsync_start - 1;
3393 mode->hsync_end = mode->hsync_end - 1;
559ee21d
ZY		 3394 return mode;
3395 }
a0910c8e 3396
559ee21d 3397 /* check whether it can be found in default mode table */
874d98ee 3398 if (drm_monitor_supports_rb(drm_edid)) {
f6e252ba
AJ		 3399 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
3400 true);
3401 if (mode)
3402 return mode;
3403 }
3404 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
559ee21d
ZY		 3405 if (mode)
3406 return mode;
3407
f6e252ba 3408 /* okay, generate it */
5c61259e
ZY		 3409 switch (timing_level) {
3410 case LEVEL_DMT:
5c61259e
ZY		 3411 break;
3412 case LEVEL_GTF:
3413 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
3414 break;
7a374350 3415 case LEVEL_GTF2:
86101bb7 3416 mode = drm_gtf2_mode(dev, drm_edid, hsize, vsize, vrefresh_rate);
7a374350 3417 break;
5c61259e 3418 case LEVEL_CVT:
d50ba256
DA		 3419 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
3420 false);
5c61259e
ZY		 3421 break;
3422 }
f453ba04
DA		 3423 return mode;
3424}
3425
b58db2c6
AJ		 3426/*
3427 * EDID is delightfully ambiguous about how interlaced modes are to be
3428 * encoded. Our internal representation is of frame height, but some
3429 * HDTV detailed timings are encoded as field height.
3430 *
3431 * The format list here is from CEA, in frame size. Technically we
3432 * should be checking refresh rate too. Whatever.
3433 */
3434static void
3435drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
fcfb2ea1 3436 const struct detailed_pixel_timing *pt)
b58db2c6
AJ		 3437{
3438 int i;
3439 static const struct {
3440 int w, h;
3441 } cea_interlaced[] = {
3442 { 1920, 1080 },
3443 { 720, 480 },
3444 { 1440, 480 },
3445 { 2880, 480 },
3446 { 720, 576 },
3447 { 1440, 576 },
3448 { 2880, 576 },
3449 };
b58db2c6
AJ		 3450
3451 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
3452 return;
3453
3c581411 3454 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
b58db2c6
AJ		 3455 if ((mode->hdisplay == cea_interlaced[i].w) &&
3456 (mode->vdisplay == cea_interlaced[i].h / 2)) {
3457 mode->vdisplay *= 2;
3458 mode->vsync_start *= 2;
3459 mode->vsync_end *= 2;
3460 mode->vtotal *= 2;
3461 mode->vtotal |= 1;
3462 }
3463 }
3464
3465 mode->flags |= DRM_MODE_FLAG_INTERLACE;
3466}
3467
17edb8e1
JN		 3468/*
3469 * Create a new mode from an EDID detailed timing section. An EDID detailed
3470 * timing block contains enough info for us to create and return a new struct
3471 * drm_display_mode.
f453ba04 3472 */
e1e7bc48 3473static struct drm_display_mode *drm_mode_detailed(struct drm_connector *connector,
f0d080ff 3474 const struct drm_edid *drm_edid,
4959b693 3475 const struct detailed_timing *timing)
f453ba04 3476{
4959b693 3477 const struct drm_display_info *info = &connector->display_info;
e1e7bc48 3478 struct drm_device *dev = connector->dev;
f453ba04 3479 struct drm_display_mode *mode;
fcfb2ea1 3480 const struct detailed_pixel_timing *pt = &timing->data.pixel_data;
0454beab
MD		 3481 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
3482 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
3483 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
3484 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
e14cbee4
MD		 3485 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
3486 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
16dad1d7 3487 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
e14cbee4 3488 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
f453ba04 3489
fc438966 3490 /* ignore tiny modes */
0454beab 3491 if (hactive < 64 || vactive < 64)
fc438966
AJ		 3492 return NULL;
3493
0454beab 3494 if (pt->misc & DRM_EDID_PT_STEREO) {
e1e7bc48
JN		 3495 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Stereo mode not supported\n",
3496 connector->base.id, connector->name);
f453ba04
DA		 3497 return NULL;
3498 }
50b6f2c8
JN		 3499 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
3500 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Composite sync not supported\n",
3501 connector->base.id, connector->name);
3502 }
f453ba04 3503
fcb45611
ZY		 3504 /* it is incorrect if hsync/vsync width is zero */
3505 if (!hsync_pulse_width || !vsync_pulse_width) {
e1e7bc48
JN		 3506 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Incorrect Detailed timing. Wrong Hsync/Vsync pulse width\n",
3507 connector->base.id, connector->name);
fcb45611
ZY		 3508 return NULL;
3509 }
bc42aabc 3510
4959b693 3511 if (info->quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
bc42aabc
AJ		 3512 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
3513 if (!mode)
3514 return NULL;
3515
3516 goto set_size;
3517 }
3518
f453ba04
DA		 3519 mode = drm_mode_create(dev);
3520 if (!mode)
3521 return NULL;
3522
4959b693 3523 if (info->quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
faacff8e
JN		 3524 mode->clock = 1088 * 10;
3525 else
3526 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
0454beab
MD		 3527
3528 mode->hdisplay = hactive;
3529 mode->hsync_start = mode->hdisplay + hsync_offset;
3530 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
3531 mode->htotal = mode->hdisplay + hblank;
3532
3533 mode->vdisplay = vactive;
3534 mode->vsync_start = mode->vdisplay + vsync_offset;
3535 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
3536 mode->vtotal = mode->vdisplay + vblank;
f453ba04 3537
2682768b
VS		 3538 /* Some EDIDs have bogus h/vsync_end values */
3539 if (mode->hsync_end > mode->htotal) {
3540 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] reducing hsync_end %d->%d\n",
3541 connector->base.id, connector->name,
3542 mode->hsync_end, mode->htotal);
3543 mode->hsync_end = mode->htotal;
3544 }
3545 if (mode->vsync_end > mode->vtotal) {
3546 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] reducing vsync_end %d->%d\n",
3547 connector->base.id, connector->name,
3548 mode->vsync_end, mode->vtotal);
3549 mode->vsync_end = mode->vtotal;
3550 }
7064fef5 3551
b58db2c6 3552 drm_mode_do_interlace_quirk(mode, pt);
f453ba04 3553
4959b693 3554 if (info->quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
faacff8e
JN		 3555 mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC;
3556 } else {
50b6f2c8
JN		 3557 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
3558 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
3559 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
3560 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
f453ba04
DA		 3561 }
3562
bc42aabc 3563set_size:
e14cbee4
MD		 3564 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
3565 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
f453ba04 3566
4959b693 3567 if (info->quirks & EDID_QUIRK_DETAILED_IN_CM) {
f453ba04
DA		 3568 mode->width_mm *= 10;
3569 mode->height_mm *= 10;
3570 }
3571
4959b693 3572 if (info->quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
f0d080ff
JN		 3573 mode->width_mm = drm_edid->edid->width_cm * 10;
3574 mode->height_mm = drm_edid->edid->height_cm * 10;
f453ba04
DA		 3575 }
3576
bc42aabc
AJ		 3577 mode->type = DRM_MODE_TYPE_DRIVER;
3578 drm_mode_set_name(mode);
3579
f453ba04
DA		 3580 return mode;
3581}
3582
b17e52ef 3583static bool
b1f559ec 3584mode_in_hsync_range(const struct drm_display_mode *mode,
c14e7241 3585 const struct edid *edid, const u8 *t)
b17e52ef
AJ		 3586{
3587 int hsync, hmin, hmax;
3588
3589 hmin = t[7];
3590 if (edid->revision >= 4)
3591 hmin += ((t[4] & 0x04) ? 255 : 0);
3592 hmax = t[8];
3593 if (edid->revision >= 4)
3594 hmax += ((t[4] & 0x08) ? 255 : 0);
07a5e632 3595 hsync = drm_mode_hsync(mode);
07a5e632 3596
b17e52ef
AJ		 3597 return (hsync <= hmax && hsync >= hmin);
3598}
3599
3600static bool
b1f559ec 3601mode_in_vsync_range(const struct drm_display_mode *mode,
c14e7241 3602 const struct edid *edid, const u8 *t)
b17e52ef
AJ		 3603{
3604 int vsync, vmin, vmax;
3605
3606 vmin = t[5];
3607 if (edid->revision >= 4)
3608 vmin += ((t[4] & 0x01) ? 255 : 0);
3609 vmax = t[6];
3610 if (edid->revision >= 4)
3611 vmax += ((t[4] & 0x02) ? 255 : 0);
3612 vsync = drm_mode_vrefresh(mode);
3613
3614 return (vsync <= vmax && vsync >= vmin);
3615}
3616
3617static u32
c14e7241 3618range_pixel_clock(const struct edid *edid, const u8 *t)
b17e52ef
AJ		 3619{
3620 /* unspecified */
3621 if (t[9] == 0 || t[9] == 255)
3622 return 0;
3623
3624 /* 1.4 with CVT support gives us real precision, yay */
afd4429e 3625 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG)
b17e52ef
AJ		 3626 return (t[9] * 10000) - ((t[12] >> 2) * 250);
3627
3628 /* 1.3 is pathetic, so fuzz up a bit */
3629 return t[9] * 10000 + 5001;
3630}
3631
874d98ee
JN		 3632static bool mode_in_range(const struct drm_display_mode *mode,
3633 const struct drm_edid *drm_edid,
3634 const struct detailed_timing *timing)
b17e52ef 3635{
874d98ee 3636 const struct edid *edid = drm_edid->edid;
b17e52ef 3637 u32 max_clock;
fcfb2ea1 3638 const u8 *t = (const u8 *)timing;
b17e52ef
AJ		 3639
3640 if (!mode_in_hsync_range(mode, edid, t))
07a5e632
AJ		 3641 return false;
3642
b17e52ef 3643 if (!mode_in_vsync_range(mode, edid, t))
07a5e632
AJ		 3644 return false;
3645
cbe7cea7 3646 max_clock = range_pixel_clock(edid, t);
3647 if (max_clock)
07a5e632
AJ		 3648 if (mode->clock > max_clock)
3649 return false;
b17e52ef
AJ		 3650
3651 /* 1.4 max horizontal check */
afd4429e 3652 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG)
b17e52ef
AJ		 3653 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
3654 return false;
3655
874d98ee 3656 if (mode_is_rb(mode) && !drm_monitor_supports_rb(drm_edid))
b17e52ef 3657 return false;
07a5e632
AJ		 3658
3659 return true;
3660}
3661
7b668ebe
TI		 3662static bool valid_inferred_mode(const struct drm_connector *connector,
3663 const struct drm_display_mode *mode)
3664{
85f8fcd6 3665 const struct drm_display_mode *m;
7b668ebe
TI		 3666 bool ok = false;
3667
3668 list_for_each_entry(m, &connector->probed_modes, head) {
3669 if (mode->hdisplay == m->hdisplay &&
3670 mode->vdisplay == m->vdisplay &&
3671 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
3672 return false; /* duplicated */
3673 if (mode->hdisplay <= m->hdisplay &&
3674 mode->vdisplay <= m->vdisplay)
3675 ok = true;
3676 }
3677 return ok;
3678}
3679
084c7a7c
JN		 3680static int drm_dmt_modes_for_range(struct drm_connector *connector,
3681 const struct drm_edid *drm_edid,
3682 const struct detailed_timing *timing)
07a5e632
AJ		 3683{
3684 int i, modes = 0;
3685 struct drm_display_mode *newmode;
3686 struct drm_device *dev = connector->dev;
3687
a6b21831 3688 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
874d98ee 3689 if (mode_in_range(drm_dmt_modes + i, drm_edid, timing) &&
7b668ebe 3690 valid_inferred_mode(connector, drm_dmt_modes + i)) {
07a5e632
AJ		 3691 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
3692 if (newmode) {
3693 drm_mode_probed_add(connector, newmode);
3694 modes++;
3695 }
3696 }
3697 }
3698
3699 return modes;
3700}
3701
c09dedb7
TI		 3702/* fix up 1366x768 mode from 1368x768;
3703 * GFT/CVT can't express 1366 width which isn't dividable by 8
3704 */
969218fe 3705void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
c09dedb7
TI		 3706{
3707 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
3708 mode->hdisplay = 1366;
3709 mode->hsync_start--;
3710 mode->hsync_end--;
3711 drm_mode_set_name(mode);
3712 }
3713}
3714
a77f7c89
JN		 3715static int drm_gtf_modes_for_range(struct drm_connector *connector,
3716 const struct drm_edid *drm_edid,
3717 const struct detailed_timing *timing)
b309bd37
AJ		 3718{
3719 int i, modes = 0;
3720 struct drm_display_mode *newmode;
3721 struct drm_device *dev = connector->dev;
3722
a6b21831 3723 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
b309bd37 3724 const struct minimode *m = &extra_modes[i];
948de842 3725
b309bd37 3726 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
fc48f169
TI		 3727 if (!newmode)
3728 return modes;
b309bd37 3729
969218fe 3730 drm_mode_fixup_1366x768(newmode);
874d98ee 3731 if (!mode_in_range(newmode, drm_edid, timing) ||
7b668ebe 3732 !valid_inferred_mode(connector, newmode)) {
b309bd37
AJ		 3733 drm_mode_destroy(dev, newmode);
3734 continue;
3735 }
3736
3737 drm_mode_probed_add(connector, newmode);
3738 modes++;
3739 }
3740
3741 return modes;
3742}
3743
9ed15f91
VS		 3744static int drm_gtf2_modes_for_range(struct drm_connector *connector,
3745 const struct drm_edid *drm_edid,
3746 const struct detailed_timing *timing)
3747{
3748 int i, modes = 0;
3749 struct drm_display_mode *newmode;
3750 struct drm_device *dev = connector->dev;
3751
3752 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3753 const struct minimode *m = &extra_modes[i];
3754
3755 newmode = drm_gtf2_mode(dev, drm_edid, m->w, m->h, m->r);
3756 if (!newmode)
3757 return modes;
3758
3759 drm_mode_fixup_1366x768(newmode);
3760 if (!mode_in_range(newmode, drm_edid, timing) ||
3761 !valid_inferred_mode(connector, newmode)) {
3762 drm_mode_destroy(dev, newmode);
3763 continue;
3764 }
3765
3766 drm_mode_probed_add(connector, newmode);
3767 modes++;
3768 }
3769
3770 return modes;
3771}
3772
7428bfbd
JN		 3773static int drm_cvt_modes_for_range(struct drm_connector *connector,
3774 const struct drm_edid *drm_edid,
3775 const struct detailed_timing *timing)
b309bd37
AJ		 3776{
3777 int i, modes = 0;
3778 struct drm_display_mode *newmode;
3779 struct drm_device *dev = connector->dev;
874d98ee 3780 bool rb = drm_monitor_supports_rb(drm_edid);
b309bd37 3781
a6b21831 3782 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
b309bd37 3783 const struct minimode *m = &extra_modes[i];
948de842 3784
b309bd37 3785 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
fc48f169
TI		 3786 if (!newmode)
3787 return modes;
b309bd37 3788
969218fe 3789 drm_mode_fixup_1366x768(newmode);
874d98ee 3790 if (!mode_in_range(newmode, drm_edid, timing) ||
7b668ebe 3791 !valid_inferred_mode(connector, newmode)) {
b309bd37
AJ		 3792 drm_mode_destroy(dev, newmode);
3793 continue;
3794 }
3795
3796 drm_mode_probed_add(connector, newmode);
3797 modes++;
3798 }
3799
3800 return modes;
3801}
3802
13931579 3803static void
4194442d 3804do_inferred_modes(const struct detailed_timing *timing, void *c)
9340d8cf 3805{
13931579 3806 struct detailed_mode_closure *closure = c;
fcfb2ea1
JN		 3807 const struct detailed_non_pixel *data = &timing->data.other_data;
3808 const struct detailed_data_monitor_range *range = &data->data.range;
9340d8cf 3809
e379814b 3810 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
cb21aafe
AJ		 3811 return;
3812
3813 closure->modes += drm_dmt_modes_for_range(closure->connector,
084c7a7c 3814 closure->drm_edid,
cb21aafe 3815 timing);
4d23f484 3816
dd3abfe4 3817 if (closure->drm_edid->edid->revision < 2)
b309bd37
AJ		 3818 return; /* GTF not defined yet */
3819
3820 switch (range->flags) {
9ed15f91
VS		 3821 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG:
3822 closure->modes += drm_gtf2_modes_for_range(closure->connector,
3823 closure->drm_edid,
3824 timing);
3825 break;
afd4429e 3826 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG:
b309bd37 3827 closure->modes += drm_gtf_modes_for_range(closure->connector,
a77f7c89 3828 closure->drm_edid,
b309bd37
AJ		 3829 timing);
3830 break;
afd4429e 3831 case DRM_EDID_CVT_SUPPORT_FLAG:
dd3abfe4 3832 if (closure->drm_edid->edid->revision < 4)
b309bd37
AJ		 3833 break;
3834
3835 closure->modes += drm_cvt_modes_for_range(closure->connector,
7428bfbd 3836 closure->drm_edid,
b309bd37
AJ		 3837 timing);
3838 break;
afd4429e 3839 case DRM_EDID_RANGE_LIMITS_ONLY_FLAG:
b309bd37
AJ		 3840 default:
3841 break;
3842 }
13931579 3843}
69da3015 3844
40f71f5b
JN		 3845static int add_inferred_modes(struct drm_connector *connector,
3846 const struct drm_edid *drm_edid)
13931579
AJ		 3847{
3848 struct detailed_mode_closure closure = {
d456ea2e 3849 .connector = connector,
dd0f4470 3850 .drm_edid = drm_edid,
13931579 3851 };
9340d8cf 3852
dd3abfe4 3853 if (drm_edid->edid->revision >= 1)
45aa2336 3854 drm_for_each_detailed_block(drm_edid, do_inferred_modes, &closure);
9340d8cf 3855
13931579 3856 return closure.modes;
9340d8cf
AJ		 3857}
3858
2255be14 3859static int
fcfb2ea1 3860drm_est3_modes(struct drm_connector *connector, const struct detailed_timing *timing)
2255be14
AJ		 3861{
3862 int i, j, m, modes = 0;
3863 struct drm_display_mode *mode;
fcfb2ea1 3864 const u8 *est = ((const u8 *)timing) + 6;
2255be14
AJ		 3865
3866 for (i = 0; i < 6; i++) {
891a7469 3867 for (j = 7; j >= 0; j--) {
2255be14 3868 m = (i * 8) + (7 - j);
3c581411 3869 if (m >= ARRAY_SIZE(est3_modes))
2255be14
AJ		 3870 break;
3871 if (est[i] & (1 << j)) {
1d42bbc8
DA		 3872 mode = drm_mode_find_dmt(connector->dev,
3873 est3_modes[m].w,
3874 est3_modes[m].h,
f6e252ba
AJ		 3875 est3_modes[m].r,
3876 est3_modes[m].rb);
2255be14
AJ		 3877 if (mode) {
3878 drm_mode_probed_add(connector, mode);
3879 modes++;
3880 }
3881 }
3882 }
3883 }
3884
3885 return modes;
3886}
3887
13931579 3888static void
4194442d 3889do_established_modes(const struct detailed_timing *timing, void *c)
9cf00977 3890{
13931579 3891 struct detailed_mode_closure *closure = c;
9cf00977 3892
e379814b 3893 if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS))
a7a131ac
VS		 3894 return;
3895
3896 closure->modes += drm_est3_modes(closure->connector, timing);
13931579 3897}
9cf00977 3898
17edb8e1
JN		 3899/*
3900 * Get established modes from EDID and add them. Each EDID block contains a
3901 * bitmap of the supported "established modes" list (defined above). Tease them
3902 * out and add them to the global modes list.
13931579 3903 */
40f71f5b
JN		 3904static int add_established_modes(struct drm_connector *connector,
3905 const struct drm_edid *drm_edid)
13931579
AJ		 3906{
3907 struct drm_device *dev = connector->dev;
40f71f5b 3908 const struct edid *edid = drm_edid->edid;
13931579
AJ		 3909 unsigned long est_bits = edid->established_timings.t1 |
3910 (edid->established_timings.t2 << 8) |
3911 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
3912 int i, modes = 0;
3913 struct detailed_mode_closure closure = {
d456ea2e 3914 .connector = connector,
dd0f4470 3915 .drm_edid = drm_edid,
13931579 3916 };
9cf00977 3917
13931579
AJ		 3918 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
3919 if (est_bits & (1<<i)) {
3920 struct drm_display_mode *newmode;
948de842 3921
13931579
AJ		 3922 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
3923 if (newmode) {
3924 drm_mode_probed_add(connector, newmode);
3925 modes++;
3926 }
3927 }
9cf00977
AJ		 3928 }
3929
dd3abfe4 3930 if (edid->revision >= 1)
45aa2336 3931 drm_for_each_detailed_block(drm_edid, do_established_modes,
eed628f1 3932 &closure);
13931579
AJ		 3933
3934 return modes + closure.modes;
3935}
3936
3937static void
4194442d 3938do_standard_modes(const struct detailed_timing *timing, void *c)
13931579
AJ		 3939{
3940 struct detailed_mode_closure *closure = c;
fcfb2ea1 3941 const struct detailed_non_pixel *data = &timing->data.other_data;
13931579 3942 struct drm_connector *connector = closure->connector;
a7a131ac 3943 int i;
13931579 3944
e379814b 3945 if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES))
a7a131ac 3946 return;
9cf00977 3947
a7a131ac 3948 for (i = 0; i < 6; i++) {
fcfb2ea1 3949 const struct std_timing *std = &data->data.timings[i];
a7a131ac
VS		 3950 struct drm_display_mode *newmode;
3951
67d87fac 3952 newmode = drm_mode_std(connector, closure->drm_edid, std);
a7a131ac
VS		 3953 if (newmode) {
3954 drm_mode_probed_add(connector, newmode);
3955 closure->modes++;
9cf00977 3956 }
9cf00977 3957 }
9cf00977
AJ		 3958}
3959
17edb8e1
JN		 3960/*
3961 * Get standard modes from EDID and add them. Standard modes can be calculated
3962 * using the appropriate standard (DMT, GTF, or CVT). Grab them from EDID and
3963 * add them to the list.
f453ba04 3964 */
40f71f5b
JN		 3965static int add_standard_modes(struct drm_connector *connector,
3966 const struct drm_edid *drm_edid)
f453ba04 3967{
9cf00977 3968 int i, modes = 0;
13931579 3969 struct detailed_mode_closure closure = {
d456ea2e 3970 .connector = connector,
dd0f4470 3971 .drm_edid = drm_edid,
13931579
AJ		 3972 };
3973
3974 for (i = 0; i < EDID_STD_TIMINGS; i++) {
3975 struct drm_display_mode *newmode;
3976
67d87fac 3977 newmode = drm_mode_std(connector, drm_edid,
40f71f5b 3978 &drm_edid->edid->standard_timings[i]);
13931579
AJ		 3979 if (newmode) {
3980 drm_mode_probed_add(connector, newmode);
3981 modes++;
3982 }
3983 }
3984
dd3abfe4 3985 if (drm_edid->edid->revision >= 1)
45aa2336 3986 drm_for_each_detailed_block(drm_edid, do_standard_modes,
13931579
AJ		 3987 &closure);
3988
3989 /* XXX should also look for standard codes in VTB blocks */
3990
3991 return modes + closure.modes;
3992}
f453ba04 3993
13931579 3994static int drm_cvt_modes(struct drm_connector *connector,
fcfb2ea1 3995 const struct detailed_timing *timing)
13931579
AJ		 3996{
3997 int i, j, modes = 0;
3998 struct drm_display_mode *newmode;
3999 struct drm_device *dev = connector->dev;
fcfb2ea1 4000 const struct cvt_timing *cvt;
bce1eb50 4001 static const int rates[] = { 60, 85, 75, 60, 50 };
13931579 4002 const u8 empty[3] = { 0, 0, 0 };
a327f6b8 4003
13931579 4004 for (i = 0; i < 4; i++) {
3f649ab7 4005 int width, height;
948de842 4006
13931579 4007 cvt = &(timing->data.other_data.data.cvt[i]);
f453ba04 4008
13931579 4009 if (!memcmp(cvt->code, empty, 3))
9cf00977 4010 continue;
f453ba04 4011
13931579
AJ		 4012 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
4013 switch (cvt->code[1] & 0x0c) {
d652d5f1
LT		 4014 /* default - because compiler doesn't see that we've enumerated all cases */
4015 default:
13931579
AJ		 4016 case 0x00:
4017 width = height * 4 / 3;
4018 break;
4019 case 0x04:
4020 width = height * 16 / 9;
4021 break;
4022 case 0x08:
4023 width = height * 16 / 10;
4024 break;
4025 case 0x0c:
4026 width = height * 15 / 9;
4027 break;
4028 }
4029
4030 for (j = 1; j < 5; j++) {
4031 if (cvt->code[2] & (1 << j)) {
4032 newmode = drm_cvt_mode(dev, width, height,
4033 rates[j], j == 0,
4034 false, false);
4035 if (newmode) {
4036 drm_mode_probed_add(connector, newmode);
4037 modes++;
4038 }
4039 }
4040 }
f453ba04
DA		 4041 }
4042
4043 return modes;
4044}
9cf00977 4045
13931579 4046static void
4194442d 4047do_cvt_mode(const struct detailed_timing *timing, void *c)
882f0219 4048{
13931579 4049 struct detailed_mode_closure *closure = c;
882f0219 4050
e379814b 4051 if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE))
a7a131ac
VS		 4052 return;
4053
4054 closure->modes += drm_cvt_modes(closure->connector, timing);
13931579 4055}
882f0219 4056
13931579 4057static int
40f71f5b 4058add_cvt_modes(struct drm_connector *connector, const struct drm_edid *drm_edid)
4d23f484 4059{
13931579 4060 struct detailed_mode_closure closure = {
d456ea2e 4061 .connector = connector,
dd0f4470 4062 .drm_edid = drm_edid,
13931579 4063 };
882f0219 4064
dd3abfe4 4065 if (drm_edid->edid->revision >= 3)
45aa2336 4066 drm_for_each_detailed_block(drm_edid, do_cvt_mode, &closure);
882f0219 4067
13931579 4068 /* XXX should also look for CVT codes in VTB blocks */
882f0219 4069
13931579
AJ		 4070 return closure.modes;
4071}
4072
e1e7bc48
JN		 4073static void fixup_detailed_cea_mode_clock(struct drm_connector *connector,
4074 struct drm_display_mode *mode);
fa3a7340 4075
13931579 4076static void
4194442d 4077do_detailed_mode(const struct detailed_timing *timing, void *c)
13931579
AJ		 4078{
4079 struct detailed_mode_closure *closure = c;
4080 struct drm_display_mode *newmode;
4081
a9b1f15f 4082 if (!is_detailed_timing_descriptor(timing))
f447dd1f
VS		 4083 return;
4084
e1e7bc48 4085 newmode = drm_mode_detailed(closure->connector,
4959b693 4086 closure->drm_edid, timing);
f447dd1f
VS		 4087 if (!newmode)
4088 return;
13931579 4089
f447dd1f
VS		 4090 if (closure->preferred)
4091 newmode->type |= DRM_MODE_TYPE_PREFERRED;
13931579 4092
f447dd1f
VS		 4093 /*
4094 * Detailed modes are limited to 10kHz pixel clock resolution,
4095 * so fix up anything that looks like CEA/HDMI mode, but the clock
4096 * is just slightly off.
4097 */
e1e7bc48 4098 fixup_detailed_cea_mode_clock(closure->connector, newmode);
fa3a7340 4099
f447dd1f
VS		 4100 drm_mode_probed_add(closure->connector, newmode);
4101 closure->modes++;
4102 closure->preferred = false;
13931579 4103}
882f0219 4104
13931579
AJ		 4105/*
4106 * add_detailed_modes - Add modes from detailed timings
4107 * @connector: attached connector
40f71f5b 4108 * @drm_edid: EDID block to scan
13931579 4109 */
40f71f5b 4110static int add_detailed_modes(struct drm_connector *connector,
4959b693 4111 const struct drm_edid *drm_edid)
13931579
AJ		 4112{
4113 struct detailed_mode_closure closure = {
d456ea2e 4114 .connector = connector,
dd0f4470 4115 .drm_edid = drm_edid,
13931579
AJ		 4116 };
4117
dd3abfe4 4118 if (drm_edid->edid->revision >= 4)
f72f9529
VS		 4119 closure.preferred = true; /* first detailed timing is always preferred */
4120 else
13931579 4121 closure.preferred =
f72f9529 4122 drm_edid->edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING;
13931579 4123
45aa2336 4124 drm_for_each_detailed_block(drm_edid, do_detailed_mode, &closure);
13931579
AJ		 4125
4126 return closure.modes;
882f0219 4127}
f453ba04 4128
9d72b7e2
JN		 4129/* CTA-861-H Table 60 - CTA Tag Codes */
4130#define CTA_DB_AUDIO 1
4131#define CTA_DB_VIDEO 2
4132#define CTA_DB_VENDOR 3
4133#define CTA_DB_SPEAKER 4
4134#define CTA_DB_EXTENDED_TAG 7
4135
4136/* CTA-861-H Table 62 - CTA Extended Tag Codes */
4137#define CTA_EXT_DB_VIDEO_CAP 0
4138#define CTA_EXT_DB_VENDOR 1
4139#define CTA_EXT_DB_HDR_STATIC_METADATA 6
4140#define CTA_EXT_DB_420_VIDEO_DATA 14
4141#define CTA_EXT_DB_420_VIDEO_CAP_MAP 15
18e3c1d5 4142#define CTA_EXT_DB_HF_EEODB 0x78
9d72b7e2
JN		 4143#define CTA_EXT_DB_HF_SCDB 0x79
4144
8fe9790d 4145#define EDID_BASIC_AUDIO (1 << 6)
a988bc72
LPC		 4146#define EDID_CEA_YCRCB444 (1 << 5)
4147#define EDID_CEA_YCRCB422 (1 << 4)
b1edd6a6 4148#define EDID_CEA_VCDB_QS (1 << 6)
8fe9790d 4149
d4e4a31d 4150/*
8fe9790d 4151 * Search EDID for CEA extension block.
d9ba1b4c
JN		 4152 *
4153 * FIXME: Prefer not returning pointers to raw EDID data.
f23c20c8 4154 */
64ac4a14 4155const u8 *drm_edid_find_extension(const struct drm_edid *drm_edid,
4cc4f09e 4156 int ext_id, int *ext_index)
f23c20c8 4157{
43d16d84 4158 const u8 *edid_ext = NULL;
8fe9790d 4159 int i;
f23c20c8
ML		 4160
4161 /* No EDID or EDID extensions */
d9307f27 4162 if (!drm_edid || !drm_edid_extension_block_count(drm_edid))
8fe9790d 4163 return NULL;
f23c20c8 4164
f23c20c8 4165 /* Find CEA extension */
d9307f27
JN		 4166 for (i = *ext_index; i < drm_edid_extension_block_count(drm_edid); i++) {
4167 edid_ext = drm_edid_extension_block_data(drm_edid, i);
4ba0f53c 4168 if (edid_block_tag(edid_ext) == ext_id)
f23c20c8
ML		 4169 break;
4170 }
4171
d9307f27 4172 if (i >= drm_edid_extension_block_count(drm_edid))
8fe9790d
ZW		 4173 return NULL;
4174
8873cfa3
VS		 4175 *ext_index = i + 1;
4176
8fe9790d
ZW		 4177 return edid_ext;
4178}
4179
6ff1c19f 4180/* Return true if the EDID has a CTA extension or a DisplayID CTA data block */
40f71f5b 4181static bool drm_edid_has_cta_extension(const struct drm_edid *drm_edid)
e28ad544 4182{
43d16d84 4183 const struct displayid_block *block;
1ba63caf 4184 struct displayid_iter iter;
0ac57ca3
JN		 4185 struct drm_edid_iter edid_iter;
4186 const u8 *ext;
6ff1c19f 4187 bool found = false;
e28ad544
AR		 4188
4189 /* Look for a top level CEA extension block */
0ac57ca3
JN		 4190 drm_edid_iter_begin(drm_edid, &edid_iter);
4191 drm_edid_iter_for_each(ext, &edid_iter) {
4192 if (ext[0] == CEA_EXT) {
4193 found = true;
4194 break;
4195 }
4196 }
4197 drm_edid_iter_end(&edid_iter);
4198
4199 if (found)
6ff1c19f 4200 return true;
e28ad544
AR		 4201
4202 /* CEA blocks can also be found embedded in a DisplayID block */
d9ba1b4c 4203 displayid_iter_edid_begin(drm_edid, &iter);
1ba63caf
JN		 4204 displayid_iter_for_each(block, &iter) {
4205 if (block->tag == DATA_BLOCK_CTA) {
6ff1c19f 4206 found = true;
1ba63caf 4207 break;
e28ad544
AR		 4208 }
4209 }
1ba63caf 4210 displayid_iter_end(&iter);
e28ad544 4211
6ff1c19f 4212 return found;
e28ad544
AR		 4213}
4214
e1cf35b9 4215static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic)
7befe621 4216{
9212f8ee
VS		 4217 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127);
4218 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219);
4219
8c1b2bd9
VS		 4220 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1))
4221 return &edid_cea_modes_1[vic - 1];
f7655d42
VS		 4222 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193))
4223 return &edid_cea_modes_193[vic - 193];
7befe621
VS		 4224 return NULL;
4225}
4226
4227static u8 cea_num_vics(void)
4228{
f7655d42 4229 return 193 + ARRAY_SIZE(edid_cea_modes_193);
7befe621
VS		 4230}
4231
4232static u8 cea_next_vic(u8 vic)
4233{
8c1b2bd9 4234 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1))
f7655d42
VS		 4235 vic = 193;
4236 return vic;
7befe621
VS		 4237}
4238
e6e79209
VS		 4239/*
4240 * Calculate the alternate clock for the CEA mode
4241 * (60Hz vs. 59.94Hz etc.)
4242 */
4243static unsigned int
4244cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
4245{
4246 unsigned int clock = cea_mode->clock;
4247
0425662f 4248 if (drm_mode_vrefresh(cea_mode) % 6 != 0)
e6e79209
VS		 4249 return clock;
4250
4251 /*
4252 * edid_cea_modes contains the 59.94Hz
4253 * variant for 240 and 480 line modes,
4254 * and the 60Hz variant otherwise.
4255 */
4256 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
9afd808c 4257 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
e6e79209 4258 else
9afd808c 4259 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
e6e79209
VS		 4260
4261 return clock;
4262}
4263
c45a4e46
VS		 4264static bool
4265cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
4266{
4267 /*
4268 * For certain VICs the spec allows the vertical
4269 * front porch to vary by one or two lines.
4270 *
4271 * cea_modes[] stores the variant with the shortest
4272 * vertical front porch. We can adjust the mode to
4273 * get the other variants by simply increasing the
4274 * vertical front porch length.
4275 */
7befe621
VS		 4276 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 ||
4277 cea_mode_for_vic(9)->vtotal != 262 ||
4278 cea_mode_for_vic(12)->vtotal != 262 ||
4279 cea_mode_for_vic(13)->vtotal != 262 ||
4280 cea_mode_for_vic(23)->vtotal != 312 ||
4281 cea_mode_for_vic(24)->vtotal != 312 ||
4282 cea_mode_for_vic(27)->vtotal != 312 ||
4283 cea_mode_for_vic(28)->vtotal != 312);
c45a4e46
VS		 4284
4285 if (((vic == 8 || vic == 9 ||
4286 vic == 12 || vic == 13) && mode->vtotal < 263) ||
4287 ((vic == 23 || vic == 24 ||
4288 vic == 27 || vic == 28) && mode->vtotal < 314)) {
4289 mode->vsync_start++;
4290 mode->vsync_end++;
4291 mode->vtotal++;
4292
4293 return true;
4294 }
4295
4296 return false;
4297}
4298
4c6bcf44
VS		 4299static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
4300 unsigned int clock_tolerance)
4301{
357768cc 4302 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 4303 u8 vic;
4c6bcf44
VS		 4304
4305 if (!to_match->clock)
4306 return 0;
4307
357768cc
VS		 4308 if (to_match->picture_aspect_ratio)
4309 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4310
7befe621 4311 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
563c4a75 4312 struct drm_display_mode cea_mode;
4c6bcf44
VS		 4313 unsigned int clock1, clock2;
4314
563c4a75
VS		 4315 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
4316
4c6bcf44 4317 /* Check both 60Hz and 59.94Hz */
c45a4e46
VS		 4318 clock1 = cea_mode.clock;
4319 clock2 = cea_mode_alternate_clock(&cea_mode);
4c6bcf44
VS		 4320
4321 if (abs(to_match->clock - clock1) > clock_tolerance &&
4322 abs(to_match->clock - clock2) > clock_tolerance)
4323 continue;
4324
c45a4e46 4325 do {
357768cc 4326 if (drm_mode_match(to_match, &cea_mode, match_flags))
c45a4e46
VS		 4327 return vic;
4328 } while (cea_mode_alternate_timings(vic, &cea_mode));
4c6bcf44
VS		 4329 }
4330
4331 return 0;
4332}
4333
18316c8c
TR		 4334/**
4335 * drm_match_cea_mode - look for a CEA mode matching given mode
4336 * @to_match: display mode
4337 *
db6cf833 4338 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
18316c8c 4339 * mode.
a4799037 4340 */
18316c8c 4341u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
a4799037 4342{
357768cc 4343 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 4344 u8 vic;
a4799037 4345
a90b590e
VS		 4346 if (!to_match->clock)
4347 return 0;
4348
357768cc
VS		 4349 if (to_match->picture_aspect_ratio)
4350 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4351
7befe621 4352 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
563c4a75 4353 struct drm_display_mode cea_mode;
a90b590e
VS		 4354 unsigned int clock1, clock2;
4355
563c4a75
VS		 4356 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
4357
a90b590e 4358 /* Check both 60Hz and 59.94Hz */
c45a4e46
VS		 4359 clock1 = cea_mode.clock;
4360 clock2 = cea_mode_alternate_clock(&cea_mode);
a4799037 4361
c45a4e46
VS		 4362 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
4363 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
4364 continue;
4365
4366 do {
357768cc 4367 if (drm_mode_match(to_match, &cea_mode, match_flags))
c45a4e46
VS		 4368 return vic;
4369 } while (cea_mode_alternate_timings(vic, &cea_mode));
a4799037 4370 }
c45a4e46 4371
a4799037
SM		 4372 return 0;
4373}
4374EXPORT_SYMBOL(drm_match_cea_mode);
4375
d9278b4c
JN		 4376static bool drm_valid_cea_vic(u8 vic)
4377{
7befe621 4378 return cea_mode_for_vic(vic) != NULL;
d9278b4c
JN		 4379}
4380
28c03a44 4381static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
0967e6a5 4382{
7befe621
VS		 4383 const struct drm_display_mode *mode = cea_mode_for_vic(video_code);
4384
4385 if (mode)
4386 return mode->picture_aspect_ratio;
4387
4388 return HDMI_PICTURE_ASPECT_NONE;
0967e6a5 4389}
0967e6a5 4390
d2b43473
WL		 4391static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code)
4392{
4393 return edid_4k_modes[video_code].picture_aspect_ratio;
4394}
4395
3f2f6533
LD		 4396/*
4397 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
4398 * specific block).
3f2f6533
LD		 4399 */
4400static unsigned int
4401hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
4402{
3f2f6533
LD		 4403 return cea_mode_alternate_clock(hdmi_mode);
4404}
4405
4c6bcf44
VS		 4406static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
4407 unsigned int clock_tolerance)
4408{
357768cc 4409 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 4410 u8 vic;
4c6bcf44
VS		 4411
4412 if (!to_match->clock)
4413 return 0;
4414
d2b43473
WL		 4415 if (to_match->picture_aspect_ratio)
4416 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4417
d9278b4c
JN		 4418 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
4419 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4c6bcf44
VS		 4420 unsigned int clock1, clock2;
4421
4422 /* Make sure to also match alternate clocks */
4423 clock1 = hdmi_mode->clock;
4424 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
4425
4426 if (abs(to_match->clock - clock1) > clock_tolerance &&
4427 abs(to_match->clock - clock2) > clock_tolerance)
4428 continue;
4429
357768cc 4430 if (drm_mode_match(to_match, hdmi_mode, match_flags))
d9278b4c 4431 return vic;
4c6bcf44
VS		 4432 }
4433
4434 return 0;
4435}
4436
3f2f6533
LD		 4437/*
4438 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
4439 * @to_match: display mode
4440 *
4441 * An HDMI mode is one defined in the HDMI vendor specific block.
4442 *
4443 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
4444 */
4445static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
4446{
357768cc 4447 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 4448 u8 vic;
3f2f6533
LD		 4449
4450 if (!to_match->clock)
4451 return 0;
4452
d2b43473
WL		 4453 if (to_match->picture_aspect_ratio)
4454 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4455
d9278b4c
JN		 4456 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
4457 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3f2f6533
LD		 4458 unsigned int clock1, clock2;
4459
4460 /* Make sure to also match alternate clocks */
4461 clock1 = hdmi_mode->clock;
4462 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
4463
4464 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
4465 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
357768cc 4466 drm_mode_match(to_match, hdmi_mode, match_flags))
d9278b4c 4467 return vic;
3f2f6533
LD		 4468 }
4469 return 0;
4470}
4471
d9278b4c
JN		 4472static bool drm_valid_hdmi_vic(u8 vic)
4473{
4474 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
4475}
4476
40f71f5b
JN		 4477static int add_alternate_cea_modes(struct drm_connector *connector,
4478 const struct drm_edid *drm_edid)
e6e79209
VS		 4479{
4480 struct drm_device *dev = connector->dev;
4481 struct drm_display_mode *mode, *tmp;
4482 LIST_HEAD(list);
4483 int modes = 0;
4484
6ff1c19f 4485 /* Don't add CTA modes if the CTA extension block is missing */
40f71f5b 4486 if (!drm_edid_has_cta_extension(drm_edid))
e6e79209
VS		 4487 return 0;
4488
4489 /*
4490 * Go through all probed modes and create a new mode
4491 * with the alternate clock for certain CEA modes.
4492 */
4493 list_for_each_entry(mode, &connector->probed_modes, head) {
3f2f6533 4494 const struct drm_display_mode *cea_mode = NULL;
e6e79209 4495 struct drm_display_mode *newmode;
d9278b4c 4496 u8 vic = drm_match_cea_mode(mode);
e6e79209
VS		 4497 unsigned int clock1, clock2;
4498
d9278b4c 4499 if (drm_valid_cea_vic(vic)) {
7befe621 4500 cea_mode = cea_mode_for_vic(vic);
3f2f6533
LD		 4501 clock2 = cea_mode_alternate_clock(cea_mode);
4502 } else {
d9278b4c
JN		 4503 vic = drm_match_hdmi_mode(mode);
4504 if (drm_valid_hdmi_vic(vic)) {
4505 cea_mode = &edid_4k_modes[vic];
3f2f6533
LD		 4506 clock2 = hdmi_mode_alternate_clock(cea_mode);
4507 }
4508 }
e6e79209 4509
3f2f6533
LD		 4510 if (!cea_mode)
4511 continue;
e6e79209
VS		 4512
4513 clock1 = cea_mode->clock;
e6e79209
VS		 4514
4515 if (clock1 == clock2)
4516 continue;
4517
4518 if (mode->clock != clock1 && mode->clock != clock2)
4519 continue;
4520
4521 newmode = drm_mode_duplicate(dev, cea_mode);
4522 if (!newmode)
4523 continue;
4524
27130212
DL		 4525 /* Carry over the stereo flags */
4526 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
4527
e6e79209
VS		 4528 /*
4529 * The current mode could be either variant. Make
4530 * sure to pick the "other" clock for the new mode.
4531 */
4532 if (mode->clock != clock1)
4533 newmode->clock = clock1;
4534 else
4535 newmode->clock = clock2;
4536
4537 list_add_tail(&newmode->head, &list);
4538 }
4539
4540 list_for_each_entry_safe(mode, tmp, &list, head) {
4541 list_del(&mode->head);
4542 drm_mode_probed_add(connector, mode);
4543 modes++;
4544 }
4545
4546 return modes;
4547}
a4799037 4548
8ec6e075
SS		 4549static u8 svd_to_vic(u8 svd)
4550{
4551 /* 0-6 bit vic, 7th bit native mode indicator */
4552 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
4553 return svd & 127;
4554
4555 return svd;
4556}
4557
6a40a75f
JN		 4558/*
4559 * Return a display mode for the 0-based vic_index'th VIC across all CTA VDBs in
4560 * the EDID, or NULL on errors.
4561 */
aff04ace 4562static struct drm_display_mode *
6a40a75f 4563drm_display_mode_from_vic_index(struct drm_connector *connector, int vic_index)
54ac76f8 4564{
6a40a75f 4565 const struct drm_display_info *info = &connector->display_info;
54ac76f8 4566 struct drm_device *dev = connector->dev;
54ac76f8 4567
6a40a75f 4568 if (!info->vics || vic_index >= info->vics_len || !info->vics[vic_index])
aff04ace
TW		 4569 return NULL;
4570
6a40a75f 4571 return drm_display_mode_from_cea_vic(dev, info->vics[vic_index]);
aff04ace
TW		 4572}
4573
832d4f2f
SS		 4574/*
4575 * do_y420vdb_modes - Parse YCBCR 420 only modes
4576 * @connector: connector corresponding to the HDMI sink
4577 * @svds: start of the data block of CEA YCBCR 420 VDB
4578 * @len: length of the CEA YCBCR 420 VDB
4579 *
4580 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
4581 * which contains modes which can be supported in YCBCR 420
4582 * output format only.
4583 */
4584static int do_y420vdb_modes(struct drm_connector *connector,
4585 const u8 *svds, u8 svds_len)
4586{
832d4f2f 4587 struct drm_device *dev = connector->dev;
c54e2e23 4588 int modes = 0, i;
832d4f2f
SS		 4589
4590 for (i = 0; i < svds_len; i++) {
4591 u8 vic = svd_to_vic(svds[i]);
4592 struct drm_display_mode *newmode;
4593
4594 if (!drm_valid_cea_vic(vic))
4595 continue;
4596
7befe621 4597 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
832d4f2f
SS		 4598 if (!newmode)
4599 break;
832d4f2f
SS		 4600 drm_mode_probed_add(connector, newmode);
4601 modes++;
4602 }
4603
832d4f2f
SS		 4604 return modes;
4605}
4606
7af655bc
VS		 4607/**
4608 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC
4609 * @dev: DRM device
8d7d8c0a 4610 * @video_code: CEA VIC of the mode
7af655bc
VS		 4611 *
4612 * Creates a new mode matching the specified CEA VIC.
4613 *
4614 * Returns: A new drm_display_mode on success or NULL on failure
4615 */
4616struct drm_display_mode *
4617drm_display_mode_from_cea_vic(struct drm_device *dev,
4618 u8 video_code)
4619{
4620 const struct drm_display_mode *cea_mode;
4621 struct drm_display_mode *newmode;
4622
4623 cea_mode = cea_mode_for_vic(video_code);
4624 if (!cea_mode)
4625 return NULL;
4626
4627 newmode = drm_mode_duplicate(dev, cea_mode);
4628 if (!newmode)
4629 return NULL;
4630
4631 return newmode;
4632}
4633EXPORT_SYMBOL(drm_display_mode_from_cea_vic);
4634
6a40a75f
JN		 4635/* Add modes based on VICs parsed in parse_cta_vdb() */
4636static int add_cta_vdb_modes(struct drm_connector *connector)
aff04ace 4637{
6a40a75f 4638 const struct drm_display_info *info = &connector->display_info;
aff04ace
TW		 4639 int i, modes = 0;
4640
6a40a75f
JN		 4641 if (!info->vics)
4642 return 0;
4643
4644 for (i = 0; i < info->vics_len; i++) {
aff04ace 4645 struct drm_display_mode *mode;
948de842 4646
6a40a75f 4647 mode = drm_display_mode_from_vic_index(connector, i);
aff04ace
TW		 4648 if (mode) {
4649 drm_mode_probed_add(connector, mode);
4650 modes++;
54ac76f8
CS		 4651 }
4652 }
4653
4654 return modes;
4655}
4656
c858cfca
DL		 4657struct stereo_mandatory_mode {
4658 int width, height, vrefresh;
4659 unsigned int flags;
4660};
4661
4662static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
f7e121b7
DL		 4663 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4664 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
c858cfca
DL		 4665 { 1920, 1080, 50,
4666 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
4667 { 1920, 1080, 60,
4668 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
f7e121b7
DL		 4669 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4670 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
4671 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4672 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
c858cfca
DL		 4673};
4674
4675static bool
4676stereo_match_mandatory(const struct drm_display_mode *mode,
4677 const struct stereo_mandatory_mode *stereo_mode)
4678{
4679 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
4680
4681 return mode->hdisplay == stereo_mode->width &&
4682 mode->vdisplay == stereo_mode->height &&
4683 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
4684 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
4685}
4686
c858cfca
DL		 4687static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
4688{
4689 struct drm_device *dev = connector->dev;
4690 const struct drm_display_mode *mode;
4691 struct list_head stereo_modes;
f7e121b7 4692 int modes = 0, i;
c858cfca
DL		 4693
4694 INIT_LIST_HEAD(&stereo_modes);
4695
4696 list_for_each_entry(mode, &connector->probed_modes, head) {
f7e121b7
DL		 4697 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
4698 const struct stereo_mandatory_mode *mandatory;
c858cfca
DL		 4699 struct drm_display_mode *new_mode;
4700
f7e121b7
DL		 4701 if (!stereo_match_mandatory(mode,
4702 &stereo_mandatory_modes[i]))
4703 continue;
c858cfca 4704
f7e121b7 4705 mandatory = &stereo_mandatory_modes[i];
c858cfca
DL		 4706 new_mode = drm_mode_duplicate(dev, mode);
4707 if (!new_mode)
4708 continue;
4709
f7e121b7 4710 new_mode->flags |= mandatory->flags;
c858cfca
DL		 4711 list_add_tail(&new_mode->head, &stereo_modes);
4712 modes++;
f7e121b7 4713 }
c858cfca
DL		 4714 }
4715
4716 list_splice_tail(&stereo_modes, &connector->probed_modes);
4717
4718 return modes;
4719}
4720
1deee8d7
DL		 4721static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
4722{
4723 struct drm_device *dev = connector->dev;
4724 struct drm_display_mode *newmode;
4725
d9278b4c 4726 if (!drm_valid_hdmi_vic(vic)) {
e1e7bc48
JN		 4727 drm_err(connector->dev, "[CONNECTOR:%d:%s] Unknown HDMI VIC: %d\n",
4728 connector->base.id, connector->name, vic);
1deee8d7
DL		 4729 return 0;
4730 }
4731
4732 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
4733 if (!newmode)
4734 return 0;
4735
4736 drm_mode_probed_add(connector, newmode);
4737
4738 return 1;
4739}
4740
fbf46025 4741static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
6a40a75f 4742 int vic_index)
fbf46025 4743{
fbf46025
TW		 4744 struct drm_display_mode *newmode;
4745 int modes = 0;
fbf46025
TW		 4746
4747 if (structure & (1 << 0)) {
6a40a75f 4748 newmode = drm_display_mode_from_vic_index(connector, vic_index);
fbf46025
TW		 4749 if (newmode) {
4750 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
4751 drm_mode_probed_add(connector, newmode);
4752 modes++;
4753 }
4754 }
4755 if (structure & (1 << 6)) {
6a40a75f 4756 newmode = drm_display_mode_from_vic_index(connector, vic_index);
fbf46025
TW		 4757 if (newmode) {
4758 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4759 drm_mode_probed_add(connector, newmode);
4760 modes++;
4761 }
4762 }
4763 if (structure & (1 << 8)) {
6a40a75f 4764 newmode = drm_display_mode_from_vic_index(connector, vic_index);
fbf46025 4765 if (newmode) {
89570eeb 4766 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
fbf46025
TW		 4767 drm_mode_probed_add(connector, newmode);
4768 modes++;
4769 }
4770 }
4771
4772 return modes;
4773}
4774
1ee3e217
JN		 4775static bool hdmi_vsdb_latency_present(const u8 *db)
4776{
4777 return db[8] & BIT(7);
4778}
4779
4780static bool hdmi_vsdb_i_latency_present(const u8 *db)
4781{
4782 return hdmi_vsdb_latency_present(db) && db[8] & BIT(6);
4783}
4784
cba83c1f
JN		 4785static int hdmi_vsdb_latency_length(const u8 *db)
4786{
4787 if (hdmi_vsdb_i_latency_present(db))
4788 return 4;
4789 else if (hdmi_vsdb_latency_present(db))
4790 return 2;
4791 else
4792 return 0;
4793}
4794
7ebe1963
LD		 4795/*
4796 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
4797 * @connector: connector corresponding to the HDMI sink
4798 * @db: start of the CEA vendor specific block
4799 * @len: length of the CEA block payload, ie. one can access up to db[len]
4800 *
c858cfca
DL		 4801 * Parses the HDMI VSDB looking for modes to add to @connector. This function
4802 * also adds the stereo 3d modes when applicable.
7ebe1963
LD		 4803 */
4804static int
6a40a75f 4805do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len)
7ebe1963 4806{
0e5083aa 4807 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
fbf46025
TW		 4808 u8 vic_len, hdmi_3d_len = 0;
4809 u16 mask;
4810 u16 structure_all;
7ebe1963
LD		 4811
4812 if (len < 8)
4813 goto out;
4814
4815 /* no HDMI_Video_Present */
4816 if (!(db[8] & (1 << 5)))
4817 goto out;
4818
cba83c1f 4819 offset += hdmi_vsdb_latency_length(db);
7ebe1963
LD		 4820
4821 /* the declared length is not long enough for the 2 first bytes
4822 * of additional video format capabilities */
c858cfca 4823 if (len < (8 + offset + 2))
7ebe1963
LD		 4824 goto out;
4825
c858cfca
DL		 4826 /* 3D_Present */
4827 offset++;
fbf46025 4828 if (db[8 + offset] & (1 << 7)) {
c858cfca
DL		 4829 modes += add_hdmi_mandatory_stereo_modes(connector);
4830
fbf46025
TW		 4831 /* 3D_Multi_present */
4832 multi_present = (db[8 + offset] & 0x60) >> 5;
4833 }
4834
c858cfca 4835 offset++;
7ebe1963 4836 vic_len = db[8 + offset] >> 5;
fbf46025 4837 hdmi_3d_len = db[8 + offset] & 0x1f;
7ebe1963
LD		 4838
4839 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
7ebe1963
LD		 4840 u8 vic;
4841
4842 vic = db[9 + offset + i];
1deee8d7 4843 modes += add_hdmi_mode(connector, vic);
7ebe1963 4844 }
fbf46025
TW		 4845 offset += 1 + vic_len;
4846
0e5083aa
TW		 4847 if (multi_present == 1)
4848 multi_len = 2;
4849 else if (multi_present == 2)
4850 multi_len = 4;
4851 else
4852 multi_len = 0;
fbf46025 4853
0e5083aa 4854 if (len < (8 + offset + hdmi_3d_len - 1))
fbf46025
TW		 4855 goto out;
4856
0e5083aa 4857 if (hdmi_3d_len < multi_len)
fbf46025
TW		 4858 goto out;
4859
0e5083aa
TW		 4860 if (multi_present == 1 || multi_present == 2) {
4861 /* 3D_Structure_ALL */
4862 structure_all = (db[8 + offset] << 8) | db[9 + offset];
fbf46025 4863
0e5083aa
TW		 4864 /* check if 3D_MASK is present */
4865 if (multi_present == 2)
4866 mask = (db[10 + offset] << 8) | db[11 + offset];
4867 else
4868 mask = 0xffff;
4869
4870 for (i = 0; i < 16; i++) {
4871 if (mask & (1 << i))
4872 modes += add_3d_struct_modes(connector,
6a40a75f 4873 structure_all, i);
0e5083aa
TW		 4874 }
4875 }
4876
4877 offset += multi_len;
4878
4879 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
4880 int vic_index;
4881 struct drm_display_mode *newmode = NULL;
4882 unsigned int newflag = 0;
4883 bool detail_present;
4884
4885 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
4886
4887 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
4888 break;
4889
4890 /* 2D_VIC_order_X */
4891 vic_index = db[8 + offset + i] >> 4;
4892
4893 /* 3D_Structure_X */
4894 switch (db[8 + offset + i] & 0x0f) {
4895 case 0:
4896 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
4897 break;
4898 case 6:
4899 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4900 break;
4901 case 8:
4902 /* 3D_Detail_X */
4903 if ((db[9 + offset + i] >> 4) == 1)
4904 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4905 break;
4906 }
4907
4908 if (newflag != 0) {
4909 newmode = drm_display_mode_from_vic_index(connector,
0e5083aa
TW		 4910 vic_index);
4911
4912 if (newmode) {
4913 newmode->flags |= newflag;
4914 drm_mode_probed_add(connector, newmode);
4915 modes++;
4916 }
4917 }
4918
4919 if (detail_present)
4920 i++;
fbf46025 4921 }
7ebe1963
LD		 4922
4923out:
4924 return modes;
4925}
4926
9e50b9d5
VS		 4927static int
4928cea_revision(const u8 *cea)
4929{
5036c0d0
VS		 4930 /*
4931 * FIXME is this correct for the DispID variant?
4932 * The DispID spec doesn't really specify whether
4933 * this is the revision of the CEA extension or
4934 * the DispID CEA data block. And the only value
4935 * given as an example is 0.
4936 */
9e50b9d5
VS		 4937 return cea[1];
4938}
4939
aba58254
JN		 4940/*
4941 * CTA Data Block iterator.
4942 *
4943 * Iterate through all CTA Data Blocks in both EDID CTA Extensions and DisplayID
4944 * CTA Data Blocks.
4945 *
4946 * struct cea_db *db:
4947 * struct cea_db_iter iter;
4948 *
4949 * cea_db_iter_edid_begin(edid, &iter);
4950 * cea_db_iter_for_each(db, &iter) {
4951 * // do stuff with db
4952 * }
4953 * cea_db_iter_end(&iter);
4954 */
4955struct cea_db_iter {
4956 struct drm_edid_iter edid_iter;
4957 struct displayid_iter displayid_iter;
4958
4959 /* Current Data Block Collection. */
4960 const u8 *collection;
4961
4962 /* Current Data Block index in current collection. */
4963 int index;
4964
4965 /* End index in current collection. */
4966 int end;
4967};
4968
4969/* CTA-861-H section 7.4 CTA Data BLock Collection */
4970struct cea_db {
4971 u8 tag_length;
4972 u8 data[];
4973} __packed;
4974
49a62a29 4975static int cea_db_tag(const struct cea_db *db)
aba58254 4976{
aba58254
JN		 4977 return db->tag_length >> 5;
4978}
4979
4980static int cea_db_payload_len(const void *_db)
4981{
4982 /* FIXME: Transition to passing struct cea_db * everywhere. */
4983 const struct cea_db *db = _db;
4984
4985 return db->tag_length & 0x1f;
4986}
4987
4988static const void *cea_db_data(const struct cea_db *db)
4989{
4990 return db->data;
4991}
4992
a9ec4fd0
JN		 4993static bool cea_db_is_extended_tag(const struct cea_db *db, int tag)
4994{
4995 return cea_db_tag(db) == CTA_DB_EXTENDED_TAG &&
4996 cea_db_payload_len(db) >= 1 &&
4997 db->data[0] == tag;
4998}
4999
5000static bool cea_db_is_vendor(const struct cea_db *db, int vendor_oui)
5001{
5002 const u8 *data = cea_db_data(db);
5003
5004 return cea_db_tag(db) == CTA_DB_VENDOR &&
5005 cea_db_payload_len(db) >= 3 &&
5006 oui(data[2], data[1], data[0]) == vendor_oui;
5007}
5008
5e87b2e5
JN		 5009static void cea_db_iter_edid_begin(const struct drm_edid *drm_edid,
5010 struct cea_db_iter *iter)
aba58254
JN		 5011{
5012 memset(iter, 0, sizeof(*iter));
5013
bbded689 5014 drm_edid_iter_begin(drm_edid, &iter->edid_iter);
d9ba1b4c 5015 displayid_iter_edid_begin(drm_edid, &iter->displayid_iter);
aba58254
JN		 5016}
5017
5018static const struct cea_db *
5019__cea_db_iter_current_block(const struct cea_db_iter *iter)
5020{
5021 const struct cea_db *db;
5022
5023 if (!iter->collection)
5024 return NULL;
5025
5026 db = (const struct cea_db *)&iter->collection[iter->index];
5027
5028 if (iter->index + sizeof(*db) <= iter->end &&
5029 iter->index + sizeof(*db) + cea_db_payload_len(db) <= iter->end)
5030 return db;
5031
5032 return NULL;
5033}
5034
11a8d095
JN		 5035/*
5036 * References:
5037 * - CTA-861-H section 7.3.3 CTA Extension Version 3
5038 */
5039static int cea_db_collection_size(const u8 *cta)
5040{
5041 u8 d = cta[2];
5042
5043 if (d < 4 || d > 127)
5044 return 0;
5045
5046 return d - 4;
5047}
5048
aba58254
JN		 5049/*
5050 * References:
5051 * - VESA E-EDID v1.4
5052 * - CTA-861-H section 7.3.3 CTA Extension Version 3
5053 */
5054static const void *__cea_db_iter_edid_next(struct cea_db_iter *iter)
5055{
5056 const u8 *ext;
5057
5058 drm_edid_iter_for_each(ext, &iter->edid_iter) {
11a8d095
JN		 5059 int size;
5060
aba58254
JN		 5061 /* Only support CTA Extension revision 3+ */
5062 if (ext[0] != CEA_EXT || cea_revision(ext) < 3)
5063 continue;
5064
11a8d095
JN		 5065 size = cea_db_collection_size(ext);
5066 if (!size)
aba58254
JN		 5067 continue;
5068
11a8d095
JN		 5069 iter->index = 4;
5070 iter->end = iter->index + size;
5071
aba58254
JN		 5072 return ext;
5073 }
5074
5075 return NULL;
5076}
5077
5078/*
5079 * References:
5080 * - DisplayID v1.3 Appendix C: CEA Data Block within a DisplayID Data Block
5081 * - DisplayID v2.0 section 4.10 CTA DisplayID Data Block
5082 *
5083 * Note that the above do not specify any connection between DisplayID Data
5084 * Block revision and CTA Extension versions.
5085 */
5086static const void *__cea_db_iter_displayid_next(struct cea_db_iter *iter)
5087{
5088 const struct displayid_block *block;
5089
5090 displayid_iter_for_each(block, &iter->displayid_iter) {
5091 if (block->tag != DATA_BLOCK_CTA)
5092 continue;
5093
5094 /*
5095 * The displayid iterator has already verified the block bounds
5096 * in displayid_iter_block().
5097 */
5098 iter->index = sizeof(*block);
5099 iter->end = iter->index + block->num_bytes;
5100
5101 return block;
5102 }
5103
5104 return NULL;
5105}
5106
5107static const struct cea_db *__cea_db_iter_next(struct cea_db_iter *iter)
5108{
5109 const struct cea_db *db;
5110
5111 if (iter->collection) {
5112 /* Current collection should always be valid. */
5113 db = __cea_db_iter_current_block(iter);
5114 if (WARN_ON(!db)) {
5115 iter->collection = NULL;
5116 return NULL;
5117 }
5118
5119 /* Next block in CTA Data Block Collection */
5120 iter->index += sizeof(*db) + cea_db_payload_len(db);
5121
5122 db = __cea_db_iter_current_block(iter);
5123 if (db)
5124 return db;
5125 }
5126
5127 for (;;) {
5128 /*
5129 * Find the next CTA Data Block Collection. First iterate all
5130 * the EDID CTA Extensions, then all the DisplayID CTA blocks.
5131 *
5132 * Per DisplayID v1.3 Appendix B: DisplayID as an EDID
5133 * Extension, it's recommended that DisplayID extensions are
5134 * exposed after all of the CTA Extensions.
5135 */
5136 iter->collection = __cea_db_iter_edid_next(iter);
5137 if (!iter->collection)
5138 iter->collection = __cea_db_iter_displayid_next(iter);
5139
5140 if (!iter->collection)
5141 return NULL;
5142
5143 db = __cea_db_iter_current_block(iter);
5144 if (db)
5145 return db;
5146 }
5147}
5148
5149#define cea_db_iter_for_each(__db, __iter) \
5150 while (((__db) = __cea_db_iter_next(__iter)))
5151
5152static void cea_db_iter_end(struct cea_db_iter *iter)
5153{
5154 displayid_iter_end(&iter->displayid_iter);
5155 drm_edid_iter_end(&iter->edid_iter);
5156
5157 memset(iter, 0, sizeof(*iter));
5158}
5159
49a62a29 5160static bool cea_db_is_hdmi_vsdb(const struct cea_db *db)
7ebe1963 5161{
a9ec4fd0
JN		 5162 return cea_db_is_vendor(db, HDMI_IEEE_OUI) &&
5163 cea_db_payload_len(db) >= 5;
7ebe1963
LD		 5164}
5165
49a62a29 5166static bool cea_db_is_hdmi_forum_vsdb(const struct cea_db *db)
50dd1bd1 5167{
a9ec4fd0
JN		 5168 return cea_db_is_vendor(db, HDMI_FORUM_IEEE_OUI) &&
5169 cea_db_payload_len(db) >= 7;
50dd1bd1
TR		 5170}
5171
18e3c1d5
JN		 5172static bool cea_db_is_hdmi_forum_eeodb(const void *db)
5173{
5174 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_EEODB) &&
5175 cea_db_payload_len(db) >= 2;
5176}
5177
49a62a29 5178static bool cea_db_is_microsoft_vsdb(const struct cea_db *db)
2869f599 5179{
a9ec4fd0
JN		 5180 return cea_db_is_vendor(db, MICROSOFT_IEEE_OUI) &&
5181 cea_db_payload_len(db) == 21;
2869f599
PZ		 5182}
5183
49a62a29 5184static bool cea_db_is_vcdb(const struct cea_db *db)
1581b2df 5185{
a9ec4fd0
JN		 5186 return cea_db_is_extended_tag(db, CTA_EXT_DB_VIDEO_CAP) &&
5187 cea_db_payload_len(db) == 2;
1581b2df
VS		 5188}
5189
49a62a29 5190static bool cea_db_is_hdmi_forum_scdb(const struct cea_db *db)
115fcf58 5191{
a9ec4fd0
JN		 5192 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_SCDB) &&
5193 cea_db_payload_len(db) >= 7;
115fcf58
LS		 5194}
5195
49a62a29 5196static bool cea_db_is_y420cmdb(const struct cea_db *db)
832d4f2f 5197{
a9ec4fd0 5198 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_CAP_MAP);
832d4f2f
SS		 5199}
5200
49a62a29 5201static bool cea_db_is_y420vdb(const struct cea_db *db)
832d4f2f 5202{
a9ec4fd0
JN		 5203 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_DATA);
5204}
832d4f2f 5205
49a62a29 5206static bool cea_db_is_hdmi_hdr_metadata_block(const struct cea_db *db)
a9ec4fd0
JN		 5207{
5208 return cea_db_is_extended_tag(db, CTA_EXT_DB_HDR_STATIC_METADATA) &&
5209 cea_db_payload_len(db) >= 3;
832d4f2f
SS		 5210}
5211
18e3c1d5
JN		 5212/*
5213 * Get the HF-EEODB override extension block count from EDID.
5214 *
5215 * The passed in EDID may be partially read, as long as it has at least two
5216 * blocks (base block and one extension block) if EDID extension count is > 0.
5217 *
5218 * Note that this is *not* how you should parse CTA Data Blocks in general; this
5219 * is only to handle partially read EDIDs. Normally, use the CTA Data Block
5220 * iterators instead.
5221 *
5222 * References:
5223 * - HDMI 2.1 section 10.3.6 HDMI Forum EDID Extension Override Data Block
5224 */
5225static int edid_hfeeodb_extension_block_count(const struct edid *edid)
5226{
5227 const u8 *cta;
5228
5229 /* No extensions according to base block, no HF-EEODB. */
5230 if (!edid_extension_block_count(edid))
5231 return 0;
5232
5233 /* HF-EEODB is always in the first EDID extension block only */
5234 cta = edid_extension_block_data(edid, 0);
5235 if (edid_block_tag(cta) != CEA_EXT || cea_revision(cta) < 3)
5236 return 0;
5237
5238 /* Need to have the data block collection, and at least 3 bytes. */
5239 if (cea_db_collection_size(cta) < 3)
5240 return 0;
5241
5242 /*
5243 * Sinks that include the HF-EEODB in their E-EDID shall include one and
5244 * only one instance of the HF-EEODB in the E-EDID, occupying bytes 4
5245 * through 6 of Block 1 of the E-EDID.
5246 */
5247 if (!cea_db_is_hdmi_forum_eeodb(&cta[4]))
5248 return 0;
5249
5250 return cta[4 + 2];
5251}
5252
61e05fdc
JN		 5253/*
5254 * CTA-861 YCbCr 4:2:0 Capability Map Data Block (CTA Y420CMDB)
5255 *
5256 * Y420CMDB contains a bitmap which gives the index of CTA modes from CTA VDB,
5257 * which can support YCBCR 420 sampling output also (apart from RGB/YCBCR444
5258 * etc). For example, if the bit 0 in bitmap is set, first mode in VDB can
5259 * support YCBCR420 output too.
5260 */
5261static void parse_cta_y420cmdb(struct drm_connector *connector,
5262 const struct cea_db *db, u64 *y420cmdb_map)
832d4f2f
SS		 5263{
5264 struct drm_display_info *info = &connector->display_info;
61e05fdc
JN		 5265 int i, map_len = cea_db_payload_len(db) - 1;
5266 const u8 *data = cea_db_data(db) + 1;
832d4f2f
SS		 5267 u64 map = 0;
5268
5269 if (map_len == 0) {
5270 /* All CEA modes support ycbcr420 sampling also.*/
61e05fdc
JN		 5271 map = U64_MAX;
5272 goto out;
832d4f2f
SS		 5273 }
5274
5275 /*
5276 * This map indicates which of the existing CEA block modes
5277 * from VDB can support YCBCR420 output too. So if bit=0 is
5278 * set, first mode from VDB can support YCBCR420 output too.
5279 * We will parse and keep this map, before parsing VDB itself
5280 * to avoid going through the same block again and again.
5281 *
5282 * Spec is not clear about max possible size of this block.
5283 * Clamping max bitmap block size at 8 bytes. Every byte can
5284 * address 8 CEA modes, in this way this map can address
5285 * 8*8 = first 64 SVDs.
5286 */
5287 if (WARN_ON_ONCE(map_len > 8))
5288 map_len = 8;
5289
61e05fdc
JN		 5290 for (i = 0; i < map_len; i++)
5291 map |= (u64)data[i] << (8 * i);
832d4f2f 5292
61e05fdc 5293out:
832d4f2f 5294 if (map)
c03d0b52 5295 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
832d4f2f 5296
61e05fdc 5297 *y420cmdb_map = map;
832d4f2f
SS		 5298}
5299
40f71f5b
JN		 5300static int add_cea_modes(struct drm_connector *connector,
5301 const struct drm_edid *drm_edid)
54ac76f8 5302{
537d9ed2
JN		 5303 const struct cea_db *db;
5304 struct cea_db_iter iter;
6a40a75f
JN		 5305 int modes;
5306
5307 /* CTA VDB block VICs parsed earlier */
5308 modes = add_cta_vdb_modes(connector);
54ac76f8 5309
5e87b2e5 5310 cea_db_iter_edid_begin(drm_edid, &iter);
537d9ed2 5311 cea_db_iter_for_each(db, &iter) {
6a40a75f
JN		 5312 if (cea_db_is_hdmi_vsdb(db)) {
5313 modes += do_hdmi_vsdb_modes(connector, (const u8 *)db,
5314 cea_db_payload_len(db));
537d9ed2
JN		 5315 } else if (cea_db_is_y420vdb(db)) {
5316 const u8 *vdb420 = cea_db_data(db) + 1;
5317
5318 /* Add 4:2:0(only) modes present in EDID */
5319 modes += do_y420vdb_modes(connector, vdb420,
5320 cea_db_payload_len(db) - 1);
54ac76f8 5321 }
537d9ed2
JN		 5322 }
5323 cea_db_iter_end(&iter);
c858cfca 5324
54ac76f8
CS		 5325 return modes;
5326}
5327
e1e7bc48
JN		 5328static void fixup_detailed_cea_mode_clock(struct drm_connector *connector,
5329 struct drm_display_mode *mode)
fa3a7340
VS		 5330{
5331 const struct drm_display_mode *cea_mode;
5332 int clock1, clock2, clock;
d9278b4c 5333 u8 vic;
fa3a7340
VS		 5334 const char *type;
5335
4c6bcf44
VS		 5336 /*
5337 * allow 5kHz clock difference either way to account for
5338 * the 10kHz clock resolution limit of detailed timings.
5339 */
d9278b4c
JN		 5340 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
5341 if (drm_valid_cea_vic(vic)) {
fa3a7340 5342 type = "CEA";
7befe621 5343 cea_mode = cea_mode_for_vic(vic);
fa3a7340
VS		 5344 clock1 = cea_mode->clock;
5345 clock2 = cea_mode_alternate_clock(cea_mode);
5346 } else {
d9278b4c
JN		 5347 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
5348 if (drm_valid_hdmi_vic(vic)) {
fa3a7340 5349 type = "HDMI";
d9278b4c 5350 cea_mode = &edid_4k_modes[vic];
fa3a7340
VS		 5351 clock1 = cea_mode->clock;
5352 clock2 = hdmi_mode_alternate_clock(cea_mode);
5353 } else {
5354 return;
5355 }
5356 }
5357
5358 /* pick whichever is closest */
5359 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
5360 clock = clock1;
5361 else
5362 clock = clock2;
5363
5364 if (mode->clock == clock)
5365 return;
5366
e1e7bc48
JN		 5367 drm_dbg_kms(connector->dev,
5368 "[CONNECTOR:%d:%s] detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
5369 connector->base.id, connector->name,
5370 type, vic, mode->clock, clock);
fa3a7340
VS		 5371 mode->clock = clock;
5372}
5373
82068ede
JH		 5374static void drm_calculate_luminance_range(struct drm_connector *connector)
5375{
5376 struct hdr_static_metadata *hdr_metadata = &connector->hdr_sink_metadata.hdmi_type1;
5377 struct drm_luminance_range_info *luminance_range =
5378 &connector->display_info.luminance_range;
5379 static const u8 pre_computed_values[] = {
5380 50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69,
5381 71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98
5382 };
5383 u32 max_avg, min_cll, max, min, q, r;
5384
5385 if (!(hdr_metadata->metadata_type & BIT(HDMI_STATIC_METADATA_TYPE1)))
5386 return;
5387
5388 max_avg = hdr_metadata->max_fall;
5389 min_cll = hdr_metadata->min_cll;
5390
5391 /*
5392 * From the specification (CTA-861-G), for calculating the maximum
5393 * luminance we need to use:
5394 * Luminance = 50*2**(CV/32)
5395 * Where CV is a one-byte value.
5396 * For calculating this expression we may need float point precision;
5397 * to avoid this complexity level, we take advantage that CV is divided
5398 * by a constant. From the Euclids division algorithm, we know that CV
5399 * can be written as: CV = 32*q + r. Next, we replace CV in the
5400 * Luminance expression and get 50*(2**q)*(2**(r/32)), hence we just
5401 * need to pre-compute the value of r/32. For pre-computing the values
5402 * We just used the following Ruby line:
5403 * (0...32).each {|cv| puts (50*2**(cv/32.0)).round}
5404 * The results of the above expressions can be verified at
5405 * pre_computed_values.
5406 */
5407 q = max_avg >> 5;
5408 r = max_avg % 32;
5409 max = (1 << q) * pre_computed_values[r];
5410
5411 /* min luminance: maxLum * (CV/255)^2 / 100 */
5412 q = DIV_ROUND_CLOSEST(min_cll, 255);
5413 min = max * DIV_ROUND_CLOSEST((q * q), 100);
5414
5415 luminance_range->min_luminance = min;
5416 luminance_range->max_luminance = max;
5417}
5418
e85959d6
US		 5419static uint8_t eotf_supported(const u8 *edid_ext)
5420{
5421 return edid_ext[2] &
5422 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
5423 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
b5e3eed1
VS		 5424 BIT(HDMI_EOTF_SMPTE_ST2084) |
5425 BIT(HDMI_EOTF_BT_2100_HLG));
e85959d6
US		 5426}
5427
5428static uint8_t hdr_metadata_type(const u8 *edid_ext)
5429{
5430 return edid_ext[3] &
5431 BIT(HDMI_STATIC_METADATA_TYPE1);
5432}
5433
5434static void
5435drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
5436{
5437 u16 len;
5438
5439 len = cea_db_payload_len(db);
5440
5441 connector->hdr_sink_metadata.hdmi_type1.eotf =
5442 eotf_supported(db);
5443 connector->hdr_sink_metadata.hdmi_type1.metadata_type =
5444 hdr_metadata_type(db);
5445
5446 if (len >= 4)
5447 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4];
5448 if (len >= 5)
5449 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5];
82068ede 5450 if (len >= 6) {
e85959d6 5451 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6];
82068ede
JH		 5452
5453 /* Calculate only when all values are available */
5454 drm_calculate_luminance_range(connector);
5455 }
e85959d6
US		 5456}
5457
1ee3e217 5458/* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */
76adaa34 5459static void
23ebf8b9 5460drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
76adaa34 5461{
8504072a 5462 u8 len = cea_db_payload_len(db);
76adaa34 5463
f7da7785
JN		 5464 if (len >= 6 && (db[6] & (1 << 7)))
5465 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
1ee3e217
JN		 5466
5467 if (len >= 10 && hdmi_vsdb_latency_present(db)) {
5468 connector->latency_present[0] = true;
8504072a 5469 connector->video_latency[0] = db[9];
8504072a 5470 connector->audio_latency[0] = db[10];
1ee3e217
JN		 5471 }
5472
5473 if (len >= 12 && hdmi_vsdb_i_latency_present(db)) {
5474 connector->latency_present[1] = true;
8504072a 5475 connector->video_latency[1] = db[11];
8504072a 5476 connector->audio_latency[1] = db[12];
1ee3e217 5477 }
76adaa34 5478
e1e7bc48
JN		 5479 drm_dbg_kms(connector->dev,
5480 "[CONNECTOR:%d:%s] HDMI: latency present %d %d, video latency %d %d, audio latency %d %d\n",
5481 connector->base.id, connector->name,
5482 connector->latency_present[0], connector->latency_present[1],
5483 connector->video_latency[0], connector->video_latency[1],
5484 connector->audio_latency[0], connector->audio_latency[1]);
76adaa34
WF		 5485}
5486
6e3fdedc
HYW		 5487static void
5488match_identity(const struct detailed_timing *timing, void *data)
5489{
5490 struct drm_edid_match_closure *closure = data;
5491 unsigned int i;
5492 const char *name = closure->ident->name;
5493 unsigned int name_len = strlen(name);
5494 const char *desc = timing->data.other_data.data.str.str;
5495 unsigned int desc_len = ARRAY_SIZE(timing->data.other_data.data.str.str);
5496
5497 if (name_len > desc_len ||
5498 !(is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME) ||
5499 is_display_descriptor(timing, EDID_DETAIL_MONITOR_STRING)))
5500 return;
5501
5502 if (strncmp(name, desc, name_len))
5503 return;
5504
5505 for (i = name_len; i < desc_len; i++) {
5506 if (desc[i] == '\n')
5507 break;
5508 /* Allow white space before EDID string terminator. */
5509 if (!isspace(desc[i]))
5510 return;
5511 }
5512
5513 closure->matched = true;
5514}
5515
5516/**
5517 * drm_edid_match - match drm_edid with given identity
5518 * @drm_edid: EDID
5519 * @ident: the EDID identity to match with
5520 *
5521 * Check if the EDID matches with the given identity.
5522 *
5523 * Return: True if the given identity matched with EDID, false otherwise.
5524 */
5525bool drm_edid_match(const struct drm_edid *drm_edid,
5526 const struct drm_edid_ident *ident)
5527{
5528 if (!drm_edid || drm_edid_get_panel_id(drm_edid) != ident->panel_id)
5529 return false;
5530
5531 /* Match with name only if it's not NULL. */
5532 if (ident->name) {
5533 struct drm_edid_match_closure closure = {
5534 .ident = ident,
5535 .matched = false,
5536 };
5537
5538 drm_for_each_detailed_block(drm_edid, match_identity, &closure);
5539
5540 return closure.matched;
5541 }
5542
5543 return true;
5544}
5545EXPORT_SYMBOL(drm_edid_match);
5546
76adaa34 5547static void
4194442d 5548monitor_name(const struct detailed_timing *timing, void *data)
76adaa34 5549{
4194442d
JN		 5550 const char **res = data;
5551
5552 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME))
a7a131ac
VS		 5553 return;
5554
4194442d 5555 *res = timing->data.other_data.data.str.str;
14f77fdd
VS		 5556}
5557
2c54f87c 5558static int get_monitor_name(const struct drm_edid *drm_edid, char name[13])
59f7c0fa 5559{
4194442d 5560 const char *edid_name = NULL;
59f7c0fa
JB		 5561 int mnl;
5562
2c54f87c 5563 if (!drm_edid || !name)
59f7c0fa
JB		 5564 return 0;
5565
45aa2336 5566 drm_for_each_detailed_block(drm_edid, monitor_name, &edid_name);
59f7c0fa
JB		 5567 for (mnl = 0; edid_name && mnl < 13; mnl++) {
5568 if (edid_name[mnl] == 0x0a)
5569 break;
5570
5571 name[mnl] = edid_name[mnl];
5572 }
5573
5574 return mnl;
5575}
5576
5577/**
5578 * drm_edid_get_monitor_name - fetch the monitor name from the edid
5579 * @edid: monitor EDID information
5580 * @name: pointer to a character array to hold the name of the monitor
5581 * @bufsize: The size of the name buffer (should be at least 14 chars.)
5582 *
5583 */
f4e558ec 5584void drm_edid_get_monitor_name(const struct edid *edid, char *name, int bufsize)
59f7c0fa 5585{
2c54f87c 5586 int name_length = 0;
4d23f484 5587
59f7c0fa
JB		 5588 if (bufsize <= 0)
5589 return;
5590
2c54f87c
JN		 5591 if (edid) {
5592 char buf[13];
5593 struct drm_edid drm_edid = {
5594 .edid = edid,
5595 .size = edid_size(edid),
5596 };
5597
5598 name_length = min(get_monitor_name(&drm_edid, buf), bufsize - 1);
5599 memcpy(name, buf, name_length);
5600 }
5601
59f7c0fa
JB		 5602 name[name_length] = '\0';
5603}
5604EXPORT_SYMBOL(drm_edid_get_monitor_name);
5605
42750d39
JN		 5606static void clear_eld(struct drm_connector *connector)
5607{
df7c8e3d 5608 mutex_lock(&connector->eld_mutex);
42750d39 5609 memset(connector->eld, 0, sizeof(connector->eld));
df7c8e3d 5610 mutex_unlock(&connector->eld_mutex);
42750d39
JN		 5611
5612 connector->latency_present[0] = false;
5613 connector->latency_present[1] = false;
5614 connector->video_latency[0] = 0;
5615 connector->audio_latency[0] = 0;
5616 connector->video_latency[1] = 0;
5617 connector->audio_latency[1] = 0;
5618}
5619
8af46811
JN		 5620/*
5621 * Get 3-byte SAD buffer from struct cea_sad.
5622 */
5623void drm_edid_cta_sad_get(const struct cea_sad *cta_sad, u8 *sad)
5624{
5625 sad[0] = cta_sad->format << 3 | cta_sad->channels;
5626 sad[1] = cta_sad->freq;
5627 sad[2] = cta_sad->byte2;
5628}
5629
5630/*
5631 * Set struct cea_sad from 3-byte SAD buffer.
5632 */
5633void drm_edid_cta_sad_set(struct cea_sad *cta_sad, const u8 *sad)
5634{
5635 cta_sad->format = (sad[0] & 0x78) >> 3;
5636 cta_sad->channels = sad[0] & 0x07;
5637 cta_sad->freq = sad[1] & 0x7f;
5638 cta_sad->byte2 = sad[2];
5639}
5640
79436a1c 5641/*
76adaa34
WF		 5642 * drm_edid_to_eld - build ELD from EDID
5643 * @connector: connector corresponding to the HDMI/DP sink
a2f9790d 5644 * @drm_edid: EDID to parse
76adaa34 5645 *
db6cf833 5646 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
1d1c3665 5647 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
76adaa34 5648 */
f4e558ec 5649static void drm_edid_to_eld(struct drm_connector *connector,
a2f9790d 5650 const struct drm_edid *drm_edid)
76adaa34 5651{
58304630 5652 const struct drm_display_info *info = &connector->display_info;
37852141
JN		 5653 const struct cea_db *db;
5654 struct cea_db_iter iter;
76adaa34 5655 uint8_t *eld = connector->eld;
7c018782 5656 int total_sad_count = 0;
76adaa34 5657 int mnl;
76adaa34 5658
a2f9790d 5659 if (!drm_edid)
e9bd0b84
JN		 5660 return;
5661
df7c8e3d
DB		 5662 mutex_lock(&connector->eld_mutex);
5663
2c54f87c 5664 mnl = get_monitor_name(drm_edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
e1e7bc48
JN		 5665 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD monitor %s\n",
5666 connector->base.id, connector->name,
5667 &eld[DRM_ELD_MONITOR_NAME_STRING]);
59f7c0fa 5668
58304630 5669 eld[DRM_ELD_CEA_EDID_VER_MNL] = info->cea_rev << DRM_ELD_CEA_EDID_VER_SHIFT;
f7da7785 5670 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
76adaa34 5671
f7da7785 5672 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
76adaa34 5673
a2f9790d
JN		 5674 eld[DRM_ELD_MANUFACTURER_NAME0] = drm_edid->edid->mfg_id[0];
5675 eld[DRM_ELD_MANUFACTURER_NAME1] = drm_edid->edid->mfg_id[1];
5676 eld[DRM_ELD_PRODUCT_CODE0] = drm_edid->edid->prod_code[0];
5677 eld[DRM_ELD_PRODUCT_CODE1] = drm_edid->edid->prod_code[1];
76adaa34 5678
5e87b2e5 5679 cea_db_iter_edid_begin(drm_edid, &iter);
37852141
JN		 5680 cea_db_iter_for_each(db, &iter) {
5681 const u8 *data = cea_db_data(db);
5682 int len = cea_db_payload_len(db);
deec222e 5683 int sad_count;
9e50b9d5 5684
37852141
JN		 5685 switch (cea_db_tag(db)) {
5686 case CTA_DB_AUDIO:
5687 /* Audio Data Block, contains SADs */
5688 sad_count = min(len / 3, 15 - total_sad_count);
5689 if (sad_count >= 1)
5690 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
5691 data, sad_count * 3);
5692 total_sad_count += sad_count;
5693 break;
5694 case CTA_DB_SPEAKER:
5695 /* Speaker Allocation Data Block */
5696 if (len >= 1)
5697 eld[DRM_ELD_SPEAKER] = data[0];
5698 break;
5699 case CTA_DB_VENDOR:
5700 /* HDMI Vendor-Specific Data Block */
5701 if (cea_db_is_hdmi_vsdb(db))
5702 drm_parse_hdmi_vsdb_audio(connector, (const u8 *)db);
5703 break;
5704 default:
5705 break;
76adaa34 5706 }
9e50b9d5 5707 }
37852141
JN		 5708 cea_db_iter_end(&iter);
5709
f7da7785 5710 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
76adaa34 5711
1d1c3665
JN		 5712 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5713 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5714 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
5715 else
5716 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
76adaa34 5717
938fd8aa
JN		 5718 eld[DRM_ELD_BASELINE_ELD_LEN] =
5719 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
5720
e1e7bc48
JN		 5721 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD size %d, SAD count %d\n",
5722 connector->base.id, connector->name,
5723 drm_eld_size(eld), total_sad_count);
df7c8e3d
DB		 5724
5725 mutex_unlock(&connector->eld_mutex);
76adaa34 5726}
76adaa34 5727
bba4b647 5728static int _drm_edid_to_sad(const struct drm_edid *drm_edid,
e8d0b2c0 5729 struct cea_sad **psads)
fe214163 5730{
b07debc2
JN		 5731 const struct cea_db *db;
5732 struct cea_db_iter iter;
fe214163 5733 int count = 0;
fe214163 5734
5e87b2e5 5735 cea_db_iter_edid_begin(drm_edid, &iter);
b07debc2 5736 cea_db_iter_for_each(db, &iter) {
9d72b7e2 5737 if (cea_db_tag(db) == CTA_DB_AUDIO) {
e8d0b2c0 5738 struct cea_sad *sads;
8af46811 5739 int i;
948de842 5740
b07debc2 5741 count = cea_db_payload_len(db) / 3; /* SAD is 3B */
e8d0b2c0
JN		 5742 sads = kcalloc(count, sizeof(*sads), GFP_KERNEL);
5743 *psads = sads;
5744 if (!sads)
fe214163 5745 return -ENOMEM;
8af46811
JN		 5746 for (i = 0; i < count; i++)
5747 drm_edid_cta_sad_set(&sads[i], &db->data[i * 3]);
fe214163
RM		 5748 break;
5749 }
5750 }
b07debc2
JN		 5751 cea_db_iter_end(&iter);
5752
5753 DRM_DEBUG_KMS("Found %d Short Audio Descriptors\n", count);
fe214163
RM		 5754
5755 return count;
5756}
bba4b647
JN		 5757
5758/**
5759 * drm_edid_to_sad - extracts SADs from EDID
5760 * @edid: EDID to parse
5761 * @sads: pointer that will be set to the extracted SADs
5762 *
5763 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
5764 *
5765 * Note: The returned pointer needs to be freed using kfree().
5766 *
5767 * Return: The number of found SADs or negative number on error.
5768 */
5769int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads)
5770{
5771 struct drm_edid drm_edid;
5772
5773 return _drm_edid_to_sad(drm_edid_legacy_init(&drm_edid, edid), sads);
5774}
fe214163
RM		 5775EXPORT_SYMBOL(drm_edid_to_sad);
5776
02703451
JN		 5777static int _drm_edid_to_speaker_allocation(const struct drm_edid *drm_edid,
5778 u8 **sadb)
d105f476 5779{
ed317307
JN		 5780 const struct cea_db *db;
5781 struct cea_db_iter iter;
d105f476 5782 int count = 0;
d105f476 5783
5e87b2e5 5784 cea_db_iter_edid_begin(drm_edid, &iter);
ed317307
JN		 5785 cea_db_iter_for_each(db, &iter) {
5786 if (cea_db_tag(db) == CTA_DB_SPEAKER &&
5787 cea_db_payload_len(db) == 3) {
5788 *sadb = kmemdup(db->data, cea_db_payload_len(db),
5789 GFP_KERNEL);
5790 if (!*sadb)
5791 return -ENOMEM;
5792 count = cea_db_payload_len(db);
5793 break;
d105f476
AD		 5794 }
5795 }
ed317307
JN		 5796 cea_db_iter_end(&iter);
5797
5798 DRM_DEBUG_KMS("Found %d Speaker Allocation Data Blocks\n", count);
d105f476
AD		 5799
5800 return count;
5801}
02703451
JN		 5802
5803/**
5804 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
5805 * @edid: EDID to parse
5806 * @sadb: pointer to the speaker block
5807 *
5808 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
5809 *
5810 * Note: The returned pointer needs to be freed using kfree().
5811 *
5812 * Return: The number of found Speaker Allocation Blocks or negative number on
5813 * error.
5814 */
5815int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb)
5816{
5817 struct drm_edid drm_edid;
5818
5819 return _drm_edid_to_speaker_allocation(drm_edid_legacy_init(&drm_edid, edid),
5820 sadb);
5821}
d105f476
AD		 5822EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
5823
76adaa34 5824/**
db6cf833 5825 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
76adaa34
WF		 5826 * @connector: connector associated with the HDMI/DP sink
5827 * @mode: the display mode
db6cf833
TR		 5828 *
5829 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
5830 * the sink doesn't support audio or video.
76adaa34
WF		 5831 */
5832int drm_av_sync_delay(struct drm_connector *connector,
3a818d35 5833 const struct drm_display_mode *mode)
76adaa34
WF		 5834{
5835 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
5836 int a, v;
5837
5838 if (!connector->latency_present[0])
5839 return 0;
5840 if (!connector->latency_present[1])
5841 i = 0;
5842
5843 a = connector->audio_latency[i];
5844 v = connector->video_latency[i];
5845
5846 /*
5847 * HDMI/DP sink doesn't support audio or video?
5848 */
5849 if (a == 255 || v == 255)
5850 return 0;
5851
5852 /*
5853 * Convert raw EDID values to millisecond.
5854 * Treat unknown latency as 0ms.
5855 */
5856 if (a)
5857 a = min(2 * (a - 1), 500);
5858 if (v)
5859 v = min(2 * (v - 1), 500);
5860
5861 return max(v - a, 0);
5862}
5863EXPORT_SYMBOL(drm_av_sync_delay);
5864
3176d092 5865static bool _drm_detect_hdmi_monitor(const struct drm_edid *drm_edid)
8fe9790d 5866{
4ce08703
JN		 5867 const struct cea_db *db;
5868 struct cea_db_iter iter;
5869 bool hdmi = false;
f23c20c8
ML		 5870
5871 /*
5872 * Because HDMI identifier is in Vendor Specific Block,
5873 * search it from all data blocks of CEA extension.
5874 */
5e87b2e5 5875 cea_db_iter_edid_begin(drm_edid, &iter);
4ce08703
JN		 5876 cea_db_iter_for_each(db, &iter) {
5877 if (cea_db_is_hdmi_vsdb(db)) {
5878 hdmi = true;
5879 break;
5880 }
f23c20c8 5881 }
4ce08703 5882 cea_db_iter_end(&iter);
f23c20c8 5883
4ce08703 5884 return hdmi;
f23c20c8 5885}
3176d092
JN		 5886
5887/**
5888 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
5889 * @edid: monitor EDID information
5890 *
5891 * Parse the CEA extension according to CEA-861-B.
5892 *
5893 * Drivers that have added the modes parsed from EDID to drm_display_info
5894 * should use &drm_display_info.is_hdmi instead of calling this function.
5895 *
5896 * Return: True if the monitor is HDMI, false if not or unknown.
5897 */
5898bool drm_detect_hdmi_monitor(const struct edid *edid)
5899{
5900 struct drm_edid drm_edid;
5901
5902 return _drm_detect_hdmi_monitor(drm_edid_legacy_init(&drm_edid, edid));
5903}
f23c20c8
ML		 5904EXPORT_SYMBOL(drm_detect_hdmi_monitor);
5905
0c057877 5906static bool _drm_detect_monitor_audio(const struct drm_edid *drm_edid)
8fe9790d 5907{
705bec3e 5908 struct drm_edid_iter edid_iter;
9975af04
JN		 5909 const struct cea_db *db;
5910 struct cea_db_iter iter;
43d16d84 5911 const u8 *edid_ext;
8fe9790d 5912 bool has_audio = false;
8fe9790d 5913
bbded689 5914 drm_edid_iter_begin(drm_edid, &edid_iter);
705bec3e
JN		 5915 drm_edid_iter_for_each(edid_ext, &edid_iter) {
5916 if (edid_ext[0] == CEA_EXT) {
5917 has_audio = edid_ext[3] & EDID_BASIC_AUDIO;
5918 if (has_audio)
5919 break;
5920 }
5921 }
5922 drm_edid_iter_end(&edid_iter);
8fe9790d
ZW		 5923
5924 if (has_audio) {
5925 DRM_DEBUG_KMS("Monitor has basic audio support\n");
5926 goto end;
5927 }
5928
5e87b2e5 5929 cea_db_iter_edid_begin(drm_edid, &iter);
9975af04
JN		 5930 cea_db_iter_for_each(db, &iter) {
5931 if (cea_db_tag(db) == CTA_DB_AUDIO) {
5932 const u8 *data = cea_db_data(db);
5933 int i;
8fe9790d 5934
9975af04 5935 for (i = 0; i < cea_db_payload_len(db); i += 3)
8fe9790d 5936 DRM_DEBUG_KMS("CEA audio format %d\n",
9975af04
JN		 5937 (data[i] >> 3) & 0xf);
5938 has_audio = true;
5939 break;
8fe9790d
ZW		 5940 }
5941 }
9975af04
JN		 5942 cea_db_iter_end(&iter);
5943
8fe9790d
ZW		 5944end:
5945 return has_audio;
5946}
0c057877
JN		 5947
5948/**
5949 * drm_detect_monitor_audio - check monitor audio capability
5950 * @edid: EDID block to scan
5951 *
5952 * Monitor should have CEA extension block.
5953 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
5954 * audio' only. If there is any audio extension block and supported
5955 * audio format, assume at least 'basic audio' support, even if 'basic
5956 * audio' is not defined in EDID.
5957 *
5958 * Return: True if the monitor supports audio, false otherwise.
5959 */
5960bool drm_detect_monitor_audio(const struct edid *edid)
5961{
5962 struct drm_edid drm_edid;
5963
5964 return _drm_detect_monitor_audio(drm_edid_legacy_init(&drm_edid, edid));
5965}
8fe9790d
ZW		 5966EXPORT_SYMBOL(drm_detect_monitor_audio);
5967
b1edd6a6 5968
c8127cf0
VS		 5969/**
5970 * drm_default_rgb_quant_range - default RGB quantization range
5971 * @mode: display mode
5972 *
5973 * Determine the default RGB quantization range for the mode,
5974 * as specified in CEA-861.
5975 *
5976 * Return: The default RGB quantization range for the mode
5977 */
5978enum hdmi_quantization_range
5979drm_default_rgb_quant_range(const struct drm_display_mode *mode)
5980{
5981 /* All CEA modes other than VIC 1 use limited quantization range. */
5982 return drm_match_cea_mode(mode) > 1 ?
5983 HDMI_QUANTIZATION_RANGE_LIMITED :
5984 HDMI_QUANTIZATION_RANGE_FULL;
5985}
5986EXPORT_SYMBOL(drm_default_rgb_quant_range);
5987
c3292ab5
JN		 5988/* CTA-861 Video Data Block (CTA VDB) */
5989static void parse_cta_vdb(struct drm_connector *connector, const struct cea_db *db)
5990{
5991 struct drm_display_info *info = &connector->display_info;
5992 int i, vic_index, len = cea_db_payload_len(db);
5993 const u8 *svds = cea_db_data(db);
5994 u8 *vics;
5995
5996 if (!len)
5997 return;
5998
5999 /* Gracefully handle multiple VDBs, however unlikely that is */
6000 vics = krealloc(info->vics, info->vics_len + len, GFP_KERNEL);
6001 if (!vics)
6002 return;
6003
6004 vic_index = info->vics_len;
6005 info->vics_len += len;
6006 info->vics = vics;
6007
6008 for (i = 0; i < len; i++) {
6009 u8 vic = svd_to_vic(svds[i]);
6010
6011 if (!drm_valid_cea_vic(vic))
6012 vic = 0;
6013
6014 info->vics[vic_index++] = vic;
6015 }
6016}
6017
61e05fdc
JN		 6018/*
6019 * Update y420_cmdb_modes based on previously parsed CTA VDB and Y420CMDB.
6020 *
6021 * Translate the y420cmdb_map based on VIC indexes to y420_cmdb_modes indexed
6022 * using the VICs themselves.
6023 */
6024static void update_cta_y420cmdb(struct drm_connector *connector, u64 y420cmdb_map)
6025{
6026 struct drm_display_info *info = &connector->display_info;
6027 struct drm_hdmi_info *hdmi = &info->hdmi;
6028 int i, len = min_t(int, info->vics_len, BITS_PER_TYPE(y420cmdb_map));
6029
6030 for (i = 0; i < len; i++) {
6031 u8 vic = info->vics[i];
6032
6033 if (vic && y420cmdb_map & BIT_ULL(i))
6034 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
6035 }
6036}
6037
4ed29f39
JN		 6038static bool cta_vdb_has_vic(const struct drm_connector *connector, u8 vic)
6039{
6040 const struct drm_display_info *info = &connector->display_info;
6041 int i;
6042
6043 if (!vic || !info->vics)
6044 return false;
6045
6046 for (i = 0; i < info->vics_len; i++) {
6047 if (info->vics[i] == vic)
6048 return true;
6049 }
6050
6051 return false;
6052}
6053
c54e2e23
JN		 6054/* CTA-861-H YCbCr 4:2:0 Video Data Block (CTA Y420VDB) */
6055static void parse_cta_y420vdb(struct drm_connector *connector,
6056 const struct cea_db *db)
6057{
6058 struct drm_display_info *info = &connector->display_info;
6059 struct drm_hdmi_info *hdmi = &info->hdmi;
6060 const u8 *svds = cea_db_data(db) + 1;
6061 int i;
6062
6063 for (i = 0; i < cea_db_payload_len(db) - 1; i++) {
6064 u8 vic = svd_to_vic(svds[i]);
6065
6066 if (!drm_valid_cea_vic(vic))
6067 continue;
6068
6069 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
6070 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
6071 }
6072}
6073
1581b2df
VS		 6074static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
6075{
6076 struct drm_display_info *info = &connector->display_info;
6077
e1e7bc48
JN		 6078 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] CEA VCDB 0x%02x\n",
6079 connector->base.id, connector->name, db[2]);
1581b2df
VS		 6080
6081 if (db[2] & EDID_CEA_VCDB_QS)
6082 info->rgb_quant_range_selectable = true;
6083}
6084
4499d488
SS		 6085static
6086void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane)
6087{
6088 switch (max_frl_rate) {
6089 case 1:
6090 *max_lanes = 3;
6091 *max_rate_per_lane = 3;
6092 break;
6093 case 2:
6094 *max_lanes = 3;
6095 *max_rate_per_lane = 6;
6096 break;
6097 case 3:
6098 *max_lanes = 4;
6099 *max_rate_per_lane = 6;
6100 break;
6101 case 4:
6102 *max_lanes = 4;
6103 *max_rate_per_lane = 8;
6104 break;
6105 case 5:
6106 *max_lanes = 4;
6107 *max_rate_per_lane = 10;
6108 break;
6109 case 6:
6110 *max_lanes = 4;
6111 *max_rate_per_lane = 12;
6112 break;
6113 case 0:
6114 default:
6115 *max_lanes = 0;
6116 *max_rate_per_lane = 0;
6117 }
6118}
6119
e6a9a2c3
SS		 6120static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
6121 const u8 *db)
6122{
6123 u8 dc_mask;
6124 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
6125
6126 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
9068e02f 6127 hdmi->y420_dc_modes = dc_mask;
e6a9a2c3
SS		 6128}
6129
5e706c4d
AN		 6130static void drm_parse_dsc_info(struct drm_hdmi_dsc_cap *hdmi_dsc,
6131 const u8 *hf_scds)
6132{
5e706c4d
AN		 6133 hdmi_dsc->v_1p2 = hf_scds[11] & DRM_EDID_DSC_1P2;
6134
6135 if (!hdmi_dsc->v_1p2)
6136 return;
6137
6138 hdmi_dsc->native_420 = hf_scds[11] & DRM_EDID_DSC_NATIVE_420;
6139 hdmi_dsc->all_bpp = hf_scds[11] & DRM_EDID_DSC_ALL_BPP;
6140
6141 if (hf_scds[11] & DRM_EDID_DSC_16BPC)
6142 hdmi_dsc->bpc_supported = 16;
6143 else if (hf_scds[11] & DRM_EDID_DSC_12BPC)
6144 hdmi_dsc->bpc_supported = 12;
6145 else if (hf_scds[11] & DRM_EDID_DSC_10BPC)
6146 hdmi_dsc->bpc_supported = 10;
6147 else
6148 /* Supports min 8 BPC if DSC 1.2 is supported*/
6149 hdmi_dsc->bpc_supported = 8;
6150
a07e6f56
AN		 6151 if (cea_db_payload_len(hf_scds) >= 12 && hf_scds[12]) {
6152 u8 dsc_max_slices;
6153 u8 dsc_max_frl_rate;
5e706c4d 6154
a07e6f56
AN		 6155 dsc_max_frl_rate = (hf_scds[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4;
6156 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes,
6157 &hdmi_dsc->max_frl_rate_per_lane);
5e706c4d 6158
a07e6f56
AN		 6159 dsc_max_slices = hf_scds[12] & DRM_EDID_DSC_MAX_SLICES;
6160
6161 switch (dsc_max_slices) {
6162 case 1:
6163 hdmi_dsc->max_slices = 1;
6164 hdmi_dsc->clk_per_slice = 340;
6165 break;
6166 case 2:
6167 hdmi_dsc->max_slices = 2;
6168 hdmi_dsc->clk_per_slice = 340;
6169 break;
6170 case 3:
6171 hdmi_dsc->max_slices = 4;
6172 hdmi_dsc->clk_per_slice = 340;
6173 break;
6174 case 4:
6175 hdmi_dsc->max_slices = 8;
6176 hdmi_dsc->clk_per_slice = 340;
6177 break;
6178 case 5:
6179 hdmi_dsc->max_slices = 8;
6180 hdmi_dsc->clk_per_slice = 400;
6181 break;
6182 case 6:
6183 hdmi_dsc->max_slices = 12;
6184 hdmi_dsc->clk_per_slice = 400;
6185 break;
6186 case 7:
6187 hdmi_dsc->max_slices = 16;
6188 hdmi_dsc->clk_per_slice = 400;
6189 break;
6190 case 0:
6191 default:
6192 hdmi_dsc->max_slices = 0;
6193 hdmi_dsc->clk_per_slice = 0;
6194 }
5e706c4d 6195 }
a07e6f56
AN		 6196
6197 if (cea_db_payload_len(hf_scds) >= 13 && hf_scds[13])
6198 hdmi_dsc->total_chunk_kbytes = hf_scds[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES;
5e706c4d
AN		 6199}
6200
d8cb49d2
JN		 6201/* Sink Capability Data Structure */
6202static void drm_parse_hdmi_forum_scds(struct drm_connector *connector,
6203 const u8 *hf_scds)
afa1c763 6204{
26c2ff77
JN		 6205 struct drm_display_info *info = &connector->display_info;
6206 struct drm_hdmi_info *hdmi = &info->hdmi;
a07e6f56 6207 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap;
5e931c88
AN		 6208 int max_tmds_clock = 0;
6209 u8 max_frl_rate = 0;
6210 bool dsc_support = false;
afa1c763 6211
26c2ff77 6212 info->has_hdmi_infoframe = true;
f1781e9b 6213
d8cb49d2 6214 if (hf_scds[6] & 0x80) {
afa1c763 6215 hdmi->scdc.supported = true;
d8cb49d2 6216 if (hf_scds[6] & 0x40)
afa1c763
SS		 6217 hdmi->scdc.read_request = true;
6218 }
62c58af3
SS		 6219
6220 /*
6221 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
6222 * And as per the spec, three factors confirm this:
6223 * * Availability of a HF-VSDB block in EDID (check)
6224 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
6225 * * SCDC support available (let's check)
6226 * Lets check it out.
6227 */
6228
d8cb49d2 6229 if (hf_scds[5]) {
62c58af3
SS		 6230 struct drm_scdc *scdc = &hdmi->scdc;
6231
5e931c88
AN		 6232 /* max clock is 5000 KHz times block value */
6233 max_tmds_clock = hf_scds[5] * 5000;
6234
62c58af3 6235 if (max_tmds_clock > 340000) {
26c2ff77 6236 info->max_tmds_clock = max_tmds_clock;
62c58af3
SS		 6237 }
6238
6239 if (scdc->supported) {
6240 scdc->scrambling.supported = true;
6241
dbe2d2bf 6242 /* Few sinks support scrambling for clocks < 340M */
d8cb49d2 6243 if ((hf_scds[6] & 0x8))
62c58af3
SS		 6244 scdc->scrambling.low_rates = true;
6245 }
6246 }
e6a9a2c3 6247
d8cb49d2 6248 if (hf_scds[7]) {
d8cb49d2 6249 max_frl_rate = (hf_scds[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4;
4499d488
SS		 6250 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes,
6251 &hdmi->max_frl_rate_per_lane);
6252 }
6253
d8cb49d2 6254 drm_parse_ycbcr420_deep_color_info(connector, hf_scds);
a07e6f56 6255
5e931c88 6256 if (cea_db_payload_len(hf_scds) >= 11 && hf_scds[11]) {
a07e6f56 6257 drm_parse_dsc_info(hdmi_dsc, hf_scds);
5e931c88
AN		 6258 dsc_support = true;
6259 }
6260
6261 drm_dbg_kms(connector->dev,
66d17ecd
JN		 6262 "[CONNECTOR:%d:%s] HF-VSDB: max TMDS clock: %d KHz, HDMI 2.1 support: %s, DSC 1.2 support: %s\n",
6263 connector->base.id, connector->name,
5e931c88 6264 max_tmds_clock, str_yes_no(max_frl_rate), str_yes_no(dsc_support));
afa1c763
SS		 6265}
6266
1cea146a
VS		 6267static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
6268 const u8 *hdmi)
d0c94692 6269{
1826750f 6270 struct drm_display_info *info = &connector->display_info;
d0c94692
MK		 6271 unsigned int dc_bpc = 0;
6272
1cea146a
VS		 6273 /* HDMI supports at least 8 bpc */
6274 info->bpc = 8;
d0c94692 6275
1cea146a
VS		 6276 if (cea_db_payload_len(hdmi) < 6)
6277 return;
6278
6279 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
6280 dc_bpc = 10;
4adc33f3 6281 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_30;
e1e7bc48
JN		 6282 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 30.\n",
6283 connector->base.id, connector->name);
1cea146a
VS		 6284 }
6285
6286 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
6287 dc_bpc = 12;
4adc33f3 6288 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_36;
e1e7bc48
JN		 6289 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 36.\n",
6290 connector->base.id, connector->name);
1cea146a
VS		 6291 }
6292
6293 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
6294 dc_bpc = 16;
4adc33f3 6295 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_48;
e1e7bc48
JN		 6296 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 48.\n",
6297 connector->base.id, connector->name);
1cea146a
VS		 6298 }
6299
6300 if (dc_bpc == 0) {
e1e7bc48
JN		 6301 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] No deep color support on this HDMI sink.\n",
6302 connector->base.id, connector->name);
1cea146a
VS		 6303 return;
6304 }
6305
e1e7bc48
JN		 6306 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Assigning HDMI sink color depth as %d bpc.\n",
6307 connector->base.id, connector->name, dc_bpc);
1cea146a 6308 info->bpc = dc_bpc;
d0c94692 6309
1cea146a
VS		 6310 /* YCRCB444 is optional according to spec. */
6311 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
4adc33f3 6312 info->edid_hdmi_ycbcr444_dc_modes = info->edid_hdmi_rgb444_dc_modes;
e1e7bc48
JN		 6313 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does YCRCB444 in deep color.\n",
6314 connector->base.id, connector->name);
1cea146a 6315 }
d0c94692 6316
1cea146a
VS		 6317 /*
6318 * Spec says that if any deep color mode is supported at all,
6319 * then deep color 36 bit must be supported.
6320 */
6321 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
e1e7bc48
JN		 6322 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink should do DC_36, but does not!\n",
6323 connector->base.id, connector->name);
1cea146a
VS		 6324 }
6325}
d0c94692 6326
919d320f 6327/* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */
23ebf8b9
VS		 6328static void
6329drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
6330{
6331 struct drm_display_info *info = &connector->display_info;
6332 u8 len = cea_db_payload_len(db);
6333
a92d083d
LP		 6334 info->is_hdmi = true;
6335
82b599ec
JN		 6336 info->source_physical_address = (db[4] << 8) | db[5];
6337
23ebf8b9
VS		 6338 if (len >= 6)
6339 info->dvi_dual = db[6] & 1;
6340 if (len >= 7)
6341 info->max_tmds_clock = db[7] * 5000;
6342
919d320f
JN		 6343 /*
6344 * Try to infer whether the sink supports HDMI infoframes.
6345 *
6346 * HDMI infoframe support was first added in HDMI 1.4. Assume the sink
6347 * supports infoframes if HDMI_Video_present is set.
6348 */
6349 if (len >= 8 && db[8] & BIT(5))
6350 info->has_hdmi_infoframe = true;
6351
e1e7bc48
JN		 6352 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI: DVI dual %d, max TMDS clock %d kHz\n",
6353 connector->base.id, connector->name,
6354 info->dvi_dual, info->max_tmds_clock);
23ebf8b9
VS		 6355
6356 drm_parse_hdmi_deep_color_info(connector, db);
6357}
6358
2869f599
PZ		 6359/*
6360 * See EDID extension for head-mounted and specialized monitors, specified at:
6361 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/specialized-monitors-edid-extension
6362 */
6363static void drm_parse_microsoft_vsdb(struct drm_connector *connector,
6364 const u8 *db)
6365{
6366 struct drm_display_info *info = &connector->display_info;
6367 u8 version = db[4];
6368 bool desktop_usage = db[5] & BIT(6);
6369
6370 /* Version 1 and 2 for HMDs, version 3 flags desktop usage explicitly */
6371 if (version == 1 || version == 2 || (version == 3 && !desktop_usage))
6372 info->non_desktop = true;
6373
66d17ecd
JN		 6374 drm_dbg_kms(connector->dev,
6375 "[CONNECTOR:%d:%s] HMD or specialized display VSDB version %u: 0x%02x\n",
6376 connector->base.id, connector->name, version, db[5]);
2869f599
PZ		 6377}
6378
1cea146a 6379static void drm_parse_cea_ext(struct drm_connector *connector,
e42192b4 6380 const struct drm_edid *drm_edid)
1cea146a
VS		 6381{
6382 struct drm_display_info *info = &connector->display_info;
8db73897 6383 struct drm_edid_iter edid_iter;
dfc03125
JN		 6384 const struct cea_db *db;
6385 struct cea_db_iter iter;
1cea146a 6386 const u8 *edid_ext;
61e05fdc 6387 u64 y420cmdb_map = 0;
d0c94692 6388
bbded689 6389 drm_edid_iter_begin(drm_edid, &edid_iter);
8db73897
JN		 6390 drm_edid_iter_for_each(edid_ext, &edid_iter) {
6391 if (edid_ext[0] != CEA_EXT)
6392 continue;
d0c94692 6393
8db73897
JN		 6394 if (!info->cea_rev)
6395 info->cea_rev = edid_ext[1];
d0c94692 6396
8db73897 6397 if (info->cea_rev != edid_ext[1])
e1e7bc48
JN		 6398 drm_dbg_kms(connector->dev,
6399 "[CONNECTOR:%d:%s] CEA extension version mismatch %u != %u\n",
6400 connector->base.id, connector->name,
6401 info->cea_rev, edid_ext[1]);
7344bad7 6402
8db73897
JN		 6403 /* The existence of a CTA extension should imply RGB support */
6404 info->color_formats = DRM_COLOR_FORMAT_RGB444;
7344bad7
JN		 6405 if (edid_ext[3] & EDID_CEA_YCRCB444)
6406 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
6407 if (edid_ext[3] & EDID_CEA_YCRCB422)
6408 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
0374ffa5
JN		 6409 if (edid_ext[3] & EDID_BASIC_AUDIO)
6410 info->has_audio = true;
6411
7344bad7 6412 }
8db73897 6413 drm_edid_iter_end(&edid_iter);
1cea146a 6414
5e87b2e5 6415 cea_db_iter_edid_begin(drm_edid, &iter);
dfc03125
JN		 6416 cea_db_iter_for_each(db, &iter) {
6417 /* FIXME: convert parsers to use struct cea_db */
6418 const u8 *data = (const u8 *)db;
1cea146a 6419
23ebf8b9 6420 if (cea_db_is_hdmi_vsdb(db))
dfc03125 6421 drm_parse_hdmi_vsdb_video(connector, data);
be982415
JN		 6422 else if (cea_db_is_hdmi_forum_vsdb(db) ||
6423 cea_db_is_hdmi_forum_scdb(db))
dfc03125 6424 drm_parse_hdmi_forum_scds(connector, data);
be982415 6425 else if (cea_db_is_microsoft_vsdb(db))
dfc03125 6426 drm_parse_microsoft_vsdb(connector, data);
be982415 6427 else if (cea_db_is_y420cmdb(db))
61e05fdc 6428 parse_cta_y420cmdb(connector, db, &y420cmdb_map);
c54e2e23
JN		 6429 else if (cea_db_is_y420vdb(db))
6430 parse_cta_y420vdb(connector, db);
be982415 6431 else if (cea_db_is_vcdb(db))
dfc03125 6432 drm_parse_vcdb(connector, data);
be982415 6433 else if (cea_db_is_hdmi_hdr_metadata_block(db))
dfc03125 6434 drm_parse_hdr_metadata_block(connector, data);
c3292ab5
JN		 6435 else if (cea_db_tag(db) == CTA_DB_VIDEO)
6436 parse_cta_vdb(connector, db);
0374ffa5
JN		 6437 else if (cea_db_tag(db) == CTA_DB_AUDIO)
6438 info->has_audio = true;
1cea146a 6439 }
dfc03125 6440 cea_db_iter_end(&iter);
61e05fdc
JN		 6441
6442 if (y420cmdb_map)
6443 update_cta_y420cmdb(connector, y420cmdb_map);
d0c94692
MK		 6444}
6445
a1d11d1e 6446static
c7943bb3 6447void get_monitor_range(const struct detailed_timing *timing, void *c)
a1d11d1e 6448{
c7943bb3
VS		 6449 struct detailed_mode_closure *closure = c;
6450 struct drm_display_info *info = &closure->connector->display_info;
6451 struct drm_monitor_range_info *monitor_range = &info->monitor_range;
a1d11d1e
MN		 6452 const struct detailed_non_pixel *data = &timing->data.other_data;
6453 const struct detailed_data_monitor_range *range = &data->data.range;
c7943bb3 6454 const struct edid *edid = closure->drm_edid->edid;
a1d11d1e 6455
e379814b 6456 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
a1d11d1e
MN		 6457 return;
6458
6459 /*
67d7469a
VS		 6460 * These limits are used to determine the VRR refresh
6461 * rate range. Only the "range limits only" variant
6462 * of the range descriptor seems to guarantee that
6463 * any and all timings are accepted by the sink, as
6464 * opposed to just timings conforming to the indicated
6465 * formula (GTF/GTF2/CVT). Thus other variants of the
6466 * range descriptor are not accepted here.
a1d11d1e
MN		 6467 */
6468 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG)
6469 return;
6470
6471 monitor_range->min_vfreq = range->min_vfreq;
6472 monitor_range->max_vfreq = range->max_vfreq;
c7943bb3
VS		 6473
6474 if (edid->revision >= 4) {
6475 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ)
6476 monitor_range->min_vfreq += 255;
6477 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MAX_VFREQ)
6478 monitor_range->max_vfreq += 255;
6479 }
a1d11d1e
MN		 6480}
6481
e42192b4
JN		 6482static void drm_get_monitor_range(struct drm_connector *connector,
6483 const struct drm_edid *drm_edid)
a1d11d1e 6484{
c7943bb3
VS		 6485 const struct drm_display_info *info = &connector->display_info;
6486 struct detailed_mode_closure closure = {
6487 .connector = connector,
6488 .drm_edid = drm_edid,
6489 };
a1d11d1e 6490
dd3abfe4 6491 if (drm_edid->edid->revision < 4)
ca2582c6
VS		 6492 return;
6493
6494 if (!(drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ))
a1d11d1e
MN		 6495 return;
6496
c7943bb3 6497 drm_for_each_detailed_block(drm_edid, get_monitor_range, &closure);
a1d11d1e 6498
e1e7bc48
JN		 6499 drm_dbg_kms(connector->dev,
6500 "[CONNECTOR:%d:%s] Supported Monitor Refresh rate range is %d Hz - %d Hz\n",
6501 connector->base.id, connector->name,
6502 info->monitor_range.min_vfreq, info->monitor_range.max_vfreq);
a1d11d1e
MN		 6503}
6504
18a9cbbe
JN		 6505static void drm_parse_vesa_mso_data(struct drm_connector *connector,
6506 const struct displayid_block *block)
6507{
6508 struct displayid_vesa_vendor_specific_block *vesa =
6509 (struct displayid_vesa_vendor_specific_block *)block;
6510 struct drm_display_info *info = &connector->display_info;
6511
6512 if (block->num_bytes < 3) {
66d17ecd
JN		 6513 drm_dbg_kms(connector->dev,
6514 "[CONNECTOR:%d:%s] Unexpected vendor block size %u\n",
6515 connector->base.id, connector->name, block->num_bytes);
18a9cbbe
JN		 6516 return;
6517 }
6518
6519 if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI)
6520 return;
6521
6522 if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
66d17ecd
JN		 6523 drm_dbg_kms(connector->dev,
6524 "[CONNECTOR:%d:%s] Unexpected VESA vendor block size\n",
6525 connector->base.id, connector->name);
18a9cbbe
JN		 6526 return;
6527 }
6528
6529 switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
6530 default:
66d17ecd
JN		 6531 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved MSO mode value\n",
6532 connector->base.id, connector->name);
18a9cbbe
JN		 6533 fallthrough;
6534 case 0:
6535 info->mso_stream_count = 0;
6536 break;
6537 case 1:
6538 info->mso_stream_count = 2; /* 2 or 4 links */
6539 break;
6540 case 2:
6541 info->mso_stream_count = 4; /* 4 links */
6542 break;
6543 }
6544
6545 if (!info->mso_stream_count) {
6546 info->mso_pixel_overlap = 0;
6547 return;
6548 }
6549
6550 info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
6551 if (info->mso_pixel_overlap > 8) {
66d17ecd
JN		 6552 drm_dbg_kms(connector->dev,
6553 "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n",
6554 connector->base.id, connector->name,
18a9cbbe
JN		 6555 info->mso_pixel_overlap);
6556 info->mso_pixel_overlap = 8;
6557 }
6558
66d17ecd
JN		 6559 drm_dbg_kms(connector->dev,
6560 "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n",
6561 connector->base.id, connector->name,
18a9cbbe
JN		 6562 info->mso_stream_count, info->mso_pixel_overlap);
6563}
6564
e42192b4
JN		 6565static void drm_update_mso(struct drm_connector *connector,
6566 const struct drm_edid *drm_edid)
18a9cbbe
JN		 6567{
6568 const struct displayid_block *block;
6569 struct displayid_iter iter;
6570
d9ba1b4c 6571 displayid_iter_edid_begin(drm_edid, &iter);
18a9cbbe
JN		 6572 displayid_iter_for_each(block, &iter) {
6573 if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC)
6574 drm_parse_vesa_mso_data(connector, block);
6575 }
6576 displayid_iter_end(&iter);
6577}
6578
170178fe
KP		 6579/* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
6580 * all of the values which would have been set from EDID
6581 */
02b16fbc 6582static void drm_reset_display_info(struct drm_connector *connector)
170178fe
KP		 6583{
6584 struct drm_display_info *info = &connector->display_info;
6585
6586 info->width_mm = 0;
6587 info->height_mm = 0;
6588
6589 info->bpc = 0;
6590 info->color_formats = 0;
6591 info->cea_rev = 0;
6592 info->max_tmds_clock = 0;
6593 info->dvi_dual = false;
a92d083d 6594 info->is_hdmi = false;
0374ffa5 6595 info->has_audio = false;
170178fe 6596 info->has_hdmi_infoframe = false;
1581b2df 6597 info->rgb_quant_range_selectable = false;
1f6b8eef 6598 memset(&info->hdmi, 0, sizeof(info->hdmi));
6692dbc1 6599 memset(&connector->hdr_sink_metadata, 0, sizeof(connector->hdr_sink_metadata));
170178fe 6600
70c0b80d
MR		 6601 info->edid_hdmi_rgb444_dc_modes = 0;
6602 info->edid_hdmi_ycbcr444_dc_modes = 0;
6603
170178fe 6604 info->non_desktop = 0;
a1d11d1e 6605 memset(&info->monitor_range, 0, sizeof(info->monitor_range));
82068ede 6606 memset(&info->luminance_range, 0, sizeof(info->luminance_range));
18a9cbbe
JN		 6607
6608 info->mso_stream_count = 0;
6609 info->mso_pixel_overlap = 0;
aa193f7e 6610 info->max_dsc_bpp = 0;
c3292ab5
JN		 6611
6612 kfree(info->vics);
6613 info->vics = NULL;
6614 info->vics_len = 0;
783dedc5
JN		 6615
6616 info->quirks = 0;
82b599ec
JN		 6617
6618 info->source_physical_address = CEC_PHYS_ADDR_INVALID;
170178fe 6619}
170178fe 6620
217a8c63
JN		 6621static void update_displayid_info(struct drm_connector *connector,
6622 const struct drm_edid *drm_edid)
6623{
6624 struct drm_display_info *info = &connector->display_info;
6625 const struct displayid_block *block;
6626 struct displayid_iter iter;
6627
6628 displayid_iter_edid_begin(drm_edid, &iter);
6629 displayid_iter_for_each(block, &iter) {
fde7679a
JN		 6630 drm_dbg_kms(connector->dev,
6631 "[CONNECTOR:%d:%s] DisplayID extension version 0x%02x, primary use 0x%02x\n",
6632 connector->base.id, connector->name,
6633 displayid_version(&iter),
6634 displayid_primary_use(&iter));
217a8c63
JN		 6635 if (displayid_version(&iter) == DISPLAY_ID_STRUCTURE_VER_20 &&
6636 (displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_VR ||
6637 displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_AR))
6638 info->non_desktop = true;
6639
6640 /*
6641 * We're only interested in the base section here, no need to
6642 * iterate further.
6643 */
6644 break;
6645 }
6646 displayid_iter_end(&iter);
6647}
6648
783dedc5
JN		 6649static void update_display_info(struct drm_connector *connector,
6650 const struct drm_edid *drm_edid)
3b11228b 6651{
1826750f 6652 struct drm_display_info *info = &connector->display_info;
45ea02d1 6653 const struct edid *edid;
ebec9a7b 6654
1f6b8eef 6655 drm_reset_display_info(connector);
45ea02d1
JN		 6656 clear_eld(connector);
6657
6658 if (!drm_edid)
6659 return;
6660
6661 edid = drm_edid->edid;
1f6b8eef 6662
783dedc5
JN		 6663 info->quirks = edid_get_quirks(drm_edid);
6664
3b11228b
JB		 6665 info->width_mm = edid->width_cm * 10;
6666 info->height_mm = edid->height_cm * 10;
6667
e42192b4 6668 drm_get_monitor_range(connector, drm_edid);
a1d11d1e 6669
a988bc72 6670 if (edid->revision < 3)
ce99534e 6671 goto out;
3b11228b 6672
7218779e 6673 if (!drm_edid_is_digital(drm_edid))
ce99534e 6674 goto out;
3b11228b 6675
ecbd4912 6676 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
e42192b4 6677 drm_parse_cea_ext(connector, drm_edid);
d0c94692 6678
217a8c63
JN		 6679 update_displayid_info(connector, drm_edid);
6680
210a021d
MK		 6681 /*
6682 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
6683 *
6684 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
6685 * tells us to assume 8 bpc color depth if the EDID doesn't have
6686 * extensions which tell otherwise.
6687 */
3bde449f
VS		 6688 if (info->bpc == 0 && edid->revision == 3 &&
6689 edid->input & DRM_EDID_DIGITAL_DFP_1_X) {
210a021d 6690 info->bpc = 8;
e1e7bc48
JN		 6691 drm_dbg_kms(connector->dev,
6692 "[CONNECTOR:%d:%s] Assigning DFP sink color depth as %d bpc.\n",
6693 connector->base.id, connector->name, info->bpc);
210a021d
MK		 6694 }
6695
a988bc72
LPC		 6696 /* Only defined for 1.4 with digital displays */
6697 if (edid->revision < 4)
ce99534e 6698 goto out;
a988bc72 6699
3b11228b
JB		 6700 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
6701 case DRM_EDID_DIGITAL_DEPTH_6:
6702 info->bpc = 6;
6703 break;
6704 case DRM_EDID_DIGITAL_DEPTH_8:
6705 info->bpc = 8;
6706 break;
6707 case DRM_EDID_DIGITAL_DEPTH_10:
6708 info->bpc = 10;
6709 break;
6710 case DRM_EDID_DIGITAL_DEPTH_12:
6711 info->bpc = 12;
6712 break;
6713 case DRM_EDID_DIGITAL_DEPTH_14:
6714 info->bpc = 14;
6715 break;
6716 case DRM_EDID_DIGITAL_DEPTH_16:
6717 info->bpc = 16;
6718 break;
6719 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
6720 default:
6721 info->bpc = 0;
6722 break;
6723 }
da05a5a7 6724
e1e7bc48
JN		 6725 drm_dbg_kms(connector->dev,
6726 "[CONNECTOR:%d:%s] Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
6727 connector->base.id, connector->name, info->bpc);
d0c94692 6728
ee58808d 6729 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
c03d0b52 6730 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
ee58808d 6731 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
c03d0b52 6732 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
18a9cbbe 6733
e42192b4 6734 drm_update_mso(connector, drm_edid);
18a9cbbe 6735
ce99534e 6736out:
783dedc5 6737 if (info->quirks & EDID_QUIRK_NON_DESKTOP) {
66d17ecd
JN		 6738 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Non-desktop display%s\n",
6739 connector->base.id, connector->name,
ce99534e
JN		 6740 info->non_desktop ? " (redundant quirk)" : "");
6741 info->non_desktop = true;
6742 }
6743
783dedc5 6744 if (info->quirks & EDID_QUIRK_CAP_DSC_15BPP)
aa193f7e 6745 info->max_dsc_bpp = 15;
45ea02d1 6746
43bde505
JN		 6747 if (info->quirks & EDID_QUIRK_FORCE_6BPC)
6748 info->bpc = 6;
6749
6750 if (info->quirks & EDID_QUIRK_FORCE_8BPC)
6751 info->bpc = 8;
6752
6753 if (info->quirks & EDID_QUIRK_FORCE_10BPC)
6754 info->bpc = 10;
6755
6756 if (info->quirks & EDID_QUIRK_FORCE_12BPC)
6757 info->bpc = 12;
6758
45ea02d1
JN		 6759 /* Depends on info->cea_rev set by drm_parse_cea_ext() above */
6760 drm_edid_to_eld(connector, drm_edid);
3b11228b
JB		 6761}
6762
a39ed680 6763static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
d2310f04 6764 const struct displayid_detailed_timings_1 *timings,
80ecb5d7 6765 bool type_7)
a39ed680
DA		 6766{
6767 struct drm_display_mode *mode;
d2310f04
EV		 6768 unsigned int pixel_clock = (timings->pixel_clock[0] |
6769 (timings->pixel_clock[1] << 8) |
6770 (timings->pixel_clock[2] << 16)) + 1;
6771 unsigned int hactive = le16_to_cpu(timings->hactive) + 1;
6772 unsigned int hblank = le16_to_cpu(timings->hblank) + 1;
6773 unsigned int hsync = (le16_to_cpu(timings->hsync) & 0x7fff) + 1;
6774 unsigned int hsync_width = le16_to_cpu(timings->hsw) + 1;
6775 unsigned int vactive = le16_to_cpu(timings->vactive) + 1;
6776 unsigned int vblank = le16_to_cpu(timings->vblank) + 1;
6777 unsigned int vsync = (le16_to_cpu(timings->vsync) & 0x7fff) + 1;
6778 unsigned int vsync_width = le16_to_cpu(timings->vsw) + 1;
6779 bool hsync_positive = le16_to_cpu(timings->hsync) & (1 << 15);
6780 bool vsync_positive = le16_to_cpu(timings->vsync) & (1 << 15);
948de842 6781
a39ed680
DA		 6782 mode = drm_mode_create(dev);
6783 if (!mode)
6784 return NULL;
6785
80ecb5d7
YB		 6786 /* resolution is kHz for type VII, and 10 kHz for type I */
6787 mode->clock = type_7 ? pixel_clock : pixel_clock * 10;
a39ed680
DA		 6788 mode->hdisplay = hactive;
6789 mode->hsync_start = mode->hdisplay + hsync;
6790 mode->hsync_end = mode->hsync_start + hsync_width;
6791 mode->htotal = mode->hdisplay + hblank;
6792
6793 mode->vdisplay = vactive;
6794 mode->vsync_start = mode->vdisplay + vsync;
6795 mode->vsync_end = mode->vsync_start + vsync_width;
6796 mode->vtotal = mode->vdisplay + vblank;
6797
6798 mode->flags = 0;
6799 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
6800 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
6801 mode->type = DRM_MODE_TYPE_DRIVER;
6802
6803 if (timings->flags & 0x80)
6804 mode->type |= DRM_MODE_TYPE_PREFERRED;
a39ed680
DA		 6805 drm_mode_set_name(mode);
6806
6807 return mode;
6808}
6809
6810static int add_displayid_detailed_1_modes(struct drm_connector *connector,
43d16d84 6811 const struct displayid_block *block)
a39ed680
DA		 6812{
6813 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
6814 int i;
6815 int num_timings;
6816 struct drm_display_mode *newmode;
6817 int num_modes = 0;
80ecb5d7 6818 bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING;
a39ed680
DA		 6819 /* blocks must be multiple of 20 bytes length */
6820 if (block->num_bytes % 20)
6821 return 0;
6822
6823 num_timings = block->num_bytes / 20;
6824 for (i = 0; i < num_timings; i++) {
6825 struct displayid_detailed_timings_1 *timings = &det->timings[i];
6826
80ecb5d7 6827 newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7);
a39ed680
DA		 6828 if (!newmode)
6829 continue;
6830
6831 drm_mode_probed_add(connector, newmode);
6832 num_modes++;
6833 }
6834 return num_modes;
6835}
6836
e79ce163
EV		 6837static struct drm_display_mode *drm_mode_displayid_formula(struct drm_device *dev,
6838 const struct displayid_formula_timings_9 *timings,
6839 bool type_10)
6840{
6841 struct drm_display_mode *mode;
6842 u16 hactive = le16_to_cpu(timings->hactive) + 1;
6843 u16 vactive = le16_to_cpu(timings->vactive) + 1;
6844 u8 timing_formula = timings->flags & 0x7;
6845
6846 /* TODO: support RB-v2 & RB-v3 */
6847 if (timing_formula > 1)
6848 return NULL;
6849
6850 /* TODO: support video-optimized refresh rate */
6851 if (timings->flags & (1 << 4))
6852 drm_dbg_kms(dev, "Fractional vrefresh is not implemented, proceeding with non-video-optimized refresh rate");
6853
6854 mode = drm_cvt_mode(dev, hactive, vactive, timings->vrefresh + 1, timing_formula == 1, false, false);
6855 if (!mode)
6856 return NULL;
6857
6858 /* TODO: interpret S3D flags */
6859
6860 mode->type = DRM_MODE_TYPE_DRIVER;
6861 drm_mode_set_name(mode);
6862
6863 return mode;
6864}
6865
6866static int add_displayid_formula_modes(struct drm_connector *connector,
6867 const struct displayid_block *block)
6868{
6869 const struct displayid_formula_timing_block *formula_block = (struct displayid_formula_timing_block *)block;
6870 int num_timings;
6871 struct drm_display_mode *newmode;
6872 int num_modes = 0;
6873 bool type_10 = block->tag == DATA_BLOCK_2_TYPE_10_FORMULA_TIMING;
6874 int timing_size = 6 + ((formula_block->base.rev & 0x70) >> 4);
6875
6876 /* extended blocks are not supported yet */
6877 if (timing_size != 6)
6878 return 0;
6879
6880 if (block->num_bytes % timing_size)
6881 return 0;
6882
6883 num_timings = block->num_bytes / timing_size;
6884 for (int i = 0; i < num_timings; i++) {
6885 const struct displayid_formula_timings_9 *timings = &formula_block->timings[i];
6886
6887 newmode = drm_mode_displayid_formula(connector->dev, timings, type_10);
6888 if (!newmode)
6889 continue;
6890
6891 drm_mode_probed_add(connector, newmode);
6892 num_modes++;
6893 }
6894 return num_modes;
6895}
6896
a39ed680 6897static int add_displayid_detailed_modes(struct drm_connector *connector,
40f71f5b 6898 const struct drm_edid *drm_edid)
a39ed680 6899{
43d16d84 6900 const struct displayid_block *block;
5ef88dc5 6901 struct displayid_iter iter;
a39ed680
DA		 6902 int num_modes = 0;
6903
d9ba1b4c 6904 displayid_iter_edid_begin(drm_edid, &iter);
5ef88dc5 6905 displayid_iter_for_each(block, &iter) {
80ecb5d7
YB		 6906 if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING ||
6907 block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING)
5ef88dc5 6908 num_modes += add_displayid_detailed_1_modes(connector, block);
e79ce163
EV		 6909 else if (block->tag == DATA_BLOCK_2_TYPE_9_FORMULA_TIMING ||
6910 block->tag == DATA_BLOCK_2_TYPE_10_FORMULA_TIMING)
6911 num_modes += add_displayid_formula_modes(connector, block);
a39ed680 6912 }
5ef88dc5 6913 displayid_iter_end(&iter);
7f261afd 6914
a39ed680
DA		 6915 return num_modes;
6916}
6917
e8b1f0d4
JN		 6918static int _drm_edid_connector_add_modes(struct drm_connector *connector,
6919 const struct drm_edid *drm_edid)
f453ba04 6920{
43bde505 6921 const struct drm_display_info *info = &connector->display_info;
f453ba04 6922 int num_modes = 0;
f453ba04 6923
45ea02d1
JN		 6924 if (!drm_edid)
6925 return 0;
58304630 6926
c867df70
AJ		 6927 /*
6928 * EDID spec says modes should be preferred in this order:
6929 * - preferred detailed mode
6930 * - other detailed modes from base block
6931 * - detailed modes from extension blocks
6932 * - CVT 3-byte code modes
6933 * - standard timing codes
6934 * - established timing codes
6935 * - modes inferred from GTF or CVT range information
6936 *
13931579 6937 * We get this pretty much right.
c867df70
AJ		 6938 *
6939 * XXX order for additional mode types in extension blocks?
6940 */
4959b693 6941 num_modes += add_detailed_modes(connector, drm_edid);
40f71f5b
JN		 6942 num_modes += add_cvt_modes(connector, drm_edid);
6943 num_modes += add_standard_modes(connector, drm_edid);
6944 num_modes += add_established_modes(connector, drm_edid);
6945 num_modes += add_cea_modes(connector, drm_edid);
6946 num_modes += add_alternate_cea_modes(connector, drm_edid);
6947 num_modes += add_displayid_detailed_modes(connector, drm_edid);
afd4429e 6948 if (drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ)
40f71f5b 6949 num_modes += add_inferred_modes(connector, drm_edid);
f453ba04 6950
783dedc5 6951 if (info->quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
4959b693 6952 edid_fixup_preferred(connector);
f453ba04 6953
f453ba04
DA		 6954 return num_modes;
6955}
f40ab034 6956
a819451e
JN		 6957static void _drm_update_tile_info(struct drm_connector *connector,
6958 const struct drm_edid *drm_edid);
02b16fbc 6959
b71c0aaa 6960static int _drm_edid_connector_property_update(struct drm_connector *connector,
a819451e 6961 const struct drm_edid *drm_edid)
02b16fbc
JN		 6962{
6963 struct drm_device *dev = connector->dev;
02b16fbc 6964 int ret;
02b16fbc 6965
02b16fbc 6966 if (connector->edid_blob_ptr) {
00c7a010
JN		 6967 const void *old_edid = connector->edid_blob_ptr->data;
6968 size_t old_edid_size = connector->edid_blob_ptr->length;
6969
6970 if (old_edid && !drm_edid_eq(drm_edid, old_edid, old_edid_size)) {
6971 connector->epoch_counter++;
6972 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID changed, epoch counter %llu\n",
6973 connector->base.id, connector->name,
6974 connector->epoch_counter);
02b16fbc
JN		 6975 }
6976 }
6977
02b16fbc
JN		 6978 ret = drm_property_replace_global_blob(dev,
6979 &connector->edid_blob_ptr,
a819451e
JN		 6980 drm_edid ? drm_edid->size : 0,
6981 drm_edid ? drm_edid->edid : NULL,
02b16fbc
JN		 6982 &connector->base,
6983 dev->mode_config.edid_property);
f999b37e
JN		 6984 if (ret) {
6985 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID property update failed (%d)\n",
6986 connector->base.id, connector->name, ret);
6987 goto out;
6988 }
6989
6990 ret = drm_object_property_set_value(&connector->base,
6991 dev->mode_config.non_desktop_property,
6992 connector->display_info.non_desktop);
6993 if (ret) {
6994 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Non-desktop property update failed (%d)\n",
6995 connector->base.id, connector->name, ret);
6996 goto out;
6997 }
6998
6999 ret = drm_connector_set_tile_property(connector);
7000 if (ret) {
7001 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Tile property update failed (%d)\n",
7002 connector->base.id, connector->name, ret);
7003 goto out;
7004 }
7005
7006out:
7007 return ret;
02b16fbc 7008}
a819451e 7009
adcea136
JN		 7010/* For sysfs edid show implementation */
7011ssize_t drm_edid_connector_property_show(struct drm_connector *connector,
7012 char *buf, loff_t off, size_t count)
7013{
7014 const void *edid;
7015 size_t size;
7016 ssize_t ret = 0;
7017
7018 mutex_lock(&connector->dev->mode_config.mutex);
7019
7020 if (!connector->edid_blob_ptr)
7021 goto unlock;
7022
7023 edid = connector->edid_blob_ptr->data;
7024 size = connector->edid_blob_ptr->length;
7025 if (!edid)
7026 goto unlock;
7027
7028 if (off >= size)
7029 goto unlock;
7030
7031 if (off + count > size)
7032 count = size - off;
7033
7034 memcpy(buf, edid + off, count);
7035
7036 ret = count;
7037unlock:
7038 mutex_unlock(&connector->dev->mode_config.mutex);
7039
7040 return ret;
7041}
7042
b71c0aaa
JN		 7043/**
7044 * drm_edid_connector_update - Update connector information from EDID
7045 * @connector: Connector
7046 * @drm_edid: EDID
7047 *
c533b516
JN		 7048 * Update the connector display info, ELD, HDR metadata, relevant properties,
7049 * etc. from the passed in EDID.
b71c0aaa
JN		 7050 *
7051 * If EDID is NULL, reset the information.
7052 *
c533b516
JN		 7053 * Must be called before calling drm_edid_connector_add_modes().
7054 *
7055 * Return: 0 on success, negative error on errors.
b71c0aaa
JN		 7056 */
7057int drm_edid_connector_update(struct drm_connector *connector,
7058 const struct drm_edid *drm_edid)
7059{
c533b516
JN		 7060 update_display_info(connector, drm_edid);
7061
7062 _drm_update_tile_info(connector, drm_edid);
7063
7064 return _drm_edid_connector_property_update(connector, drm_edid);
7065}
7066EXPORT_SYMBOL(drm_edid_connector_update);
7067
7068/**
7069 * drm_edid_connector_add_modes - Update probed modes from the EDID property
7070 * @connector: Connector
7071 *
7072 * Add the modes from the previously updated EDID property to the connector
7073 * probed modes list.
7074 *
7075 * drm_edid_connector_update() must have been called before this to update the
7076 * EDID property.
7077 *
7078 * Return: The number of modes added, or 0 if we couldn't find any.
7079 */
7080int drm_edid_connector_add_modes(struct drm_connector *connector)
7081{
7082 const struct drm_edid *drm_edid = NULL;
b71c0aaa
JN		 7083 int count;
7084
c533b516
JN		 7085 if (connector->edid_blob_ptr)
7086 drm_edid = drm_edid_alloc(connector->edid_blob_ptr->data,
7087 connector->edid_blob_ptr->length);
e8b1f0d4
JN		 7088
7089 count = _drm_edid_connector_add_modes(connector, drm_edid);
b71c0aaa 7090
c533b516 7091 drm_edid_free(drm_edid);
b71c0aaa
JN		 7092
7093 return count;
7094}
c533b516 7095EXPORT_SYMBOL(drm_edid_connector_add_modes);
b71c0aaa 7096
a819451e
JN		 7097/**
7098 * drm_connector_update_edid_property - update the edid property of a connector
7099 * @connector: drm connector
7100 * @edid: new value of the edid property
7101 *
7102 * This function creates a new blob modeset object and assigns its id to the
7103 * connector's edid property.
7104 * Since we also parse tile information from EDID's displayID block, we also
7105 * set the connector's tile property here. See drm_connector_set_tile_property()
7106 * for more details.
7107 *
b71c0aaa
JN		 7108 * This function is deprecated. Use drm_edid_connector_update() instead.
7109 *
a819451e
JN		 7110 * Returns:
7111 * Zero on success, negative errno on failure.
7112 */
7113int drm_connector_update_edid_property(struct drm_connector *connector,
7114 const struct edid *edid)
7115{
7116 struct drm_edid drm_edid;
7117
b494d628 7118 return drm_edid_connector_update(connector, drm_edid_legacy_init(&drm_edid, edid));
a819451e 7119}
02b16fbc
JN		 7120EXPORT_SYMBOL(drm_connector_update_edid_property);
7121
f40ab034
JN		 7122/**
7123 * drm_add_edid_modes - add modes from EDID data, if available
7124 * @connector: connector we're probing
7125 * @edid: EDID data
7126 *
7127 * Add the specified modes to the connector's mode list. Also fills out the
7128 * &drm_display_info structure and ELD in @connector with any information which
7129 * can be derived from the edid.
7130 *
c533b516 7131 * This function is deprecated. Use drm_edid_connector_add_modes() instead.
b71c0aaa 7132 *
f40ab034
JN		 7133 * Return: The number of modes added or 0 if we couldn't find any.
7134 */
7135int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
7136{
e8b1f0d4
JN		 7137 struct drm_edid _drm_edid;
7138 const struct drm_edid *drm_edid;
22a27e05 7139
f40ab034 7140 if (edid && !drm_edid_is_valid(edid)) {
66d17ecd
JN		 7141 drm_warn(connector->dev, "[CONNECTOR:%d:%s] EDID invalid.\n",
7142 connector->base.id, connector->name);
f40ab034
JN		 7143 edid = NULL;
7144 }
7145
e8b1f0d4
JN		 7146 drm_edid = drm_edid_legacy_init(&_drm_edid, edid);
7147
7148 update_display_info(connector, drm_edid);
7149
7150 return _drm_edid_connector_add_modes(connector, drm_edid);
f40ab034 7151}
f453ba04 7152EXPORT_SYMBOL(drm_add_edid_modes);
f0fda0a4
ZY		 7153
7154/**
7155 * drm_add_modes_noedid - add modes for the connectors without EDID
7156 * @connector: connector we're probing
7157 * @hdisplay: the horizontal display limit
7158 * @vdisplay: the vertical display limit
7159 *
7160 * Add the specified modes to the connector's mode list. Only when the
7161 * hdisplay/vdisplay is not beyond the given limit, it will be added.
7162 *
db6cf833 7163 * Return: The number of modes added or 0 if we couldn't find any.
f0fda0a4
ZY		 7164 */
7165int drm_add_modes_noedid(struct drm_connector *connector,
4190aa3a 7166 unsigned int hdisplay, unsigned int vdisplay)
f0fda0a4 7167{
4190aa3a 7168 int i, count = ARRAY_SIZE(drm_dmt_modes), num_modes = 0;
b1f559ec 7169 struct drm_display_mode *mode;
f0fda0a4
ZY		 7170 struct drm_device *dev = connector->dev;
7171
f0fda0a4 7172 for (i = 0; i < count; i++) {
b1f559ec 7173 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
948de842 7174
f0fda0a4
ZY		 7175 if (hdisplay && vdisplay) {
7176 /*
7177 * Only when two are valid, they will be used to check
7178 * whether the mode should be added to the mode list of
7179 * the connector.
7180 */
7181 if (ptr->hdisplay > hdisplay ||
7182 ptr->vdisplay > vdisplay)
7183 continue;
7184 }
f985dedb
AJ		 7185 if (drm_mode_vrefresh(ptr) > 61)
7186 continue;
f0fda0a4
ZY		 7187 mode = drm_mode_duplicate(dev, ptr);
7188 if (mode) {
7189 drm_mode_probed_add(connector, mode);
7190 num_modes++;
7191 }
7192 }
7193 return num_modes;
7194}
7195EXPORT_SYMBOL(drm_add_modes_noedid);
10a85120 7196
192a3aa0 7197static bool is_hdmi2_sink(const struct drm_connector *connector)
13d0add3
VS		 7198{
7199 /*
7200 * FIXME: sil-sii8620 doesn't have a connector around when
7201 * we need one, so we have to be prepared for a NULL connector.
7202 */
7203 if (!connector)
7204 return true;
7205
7206 return connector->display_info.hdmi.scdc.supported ||
c03d0b52 7207 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR420;
13d0add3
VS		 7208}
7209
192a3aa0 7210static u8 drm_mode_hdmi_vic(const struct drm_connector *connector,
949561eb
VS		 7211 const struct drm_display_mode *mode)
7212{
7213 bool has_hdmi_infoframe = connector ?
7214 connector->display_info.has_hdmi_infoframe : false;
7215
7216 if (!has_hdmi_infoframe)
7217 return 0;
7218
7219 /* No HDMI VIC when signalling 3D video format */
7220 if (mode->flags & DRM_MODE_FLAG_3D_MASK)
7221 return 0;
7222
7223 return drm_match_hdmi_mode(mode);
7224}
7225
192a3aa0 7226static u8 drm_mode_cea_vic(const struct drm_connector *connector,
cfd6f8c3
VS		 7227 const struct drm_display_mode *mode)
7228{
cfd6f8c3
VS		 7229 /*
7230 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
7231 * we should send its VIC in vendor infoframes, else send the
7232 * VIC in AVI infoframes. Lets check if this mode is present in
7233 * HDMI 1.4b 4K modes
7234 */
949561eb 7235 if (drm_mode_hdmi_vic(connector, mode))
cfd6f8c3
VS		 7236 return 0;
7237
1cbc1f0d
JN		 7238 return drm_match_cea_mode(mode);
7239}
cfd6f8c3 7240
1cbc1f0d
JN		 7241/*
7242 * Avoid sending VICs defined in HDMI 2.0 in AVI infoframes to sinks that
7243 * conform to HDMI 1.4.
7244 *
7245 * HDMI 1.4 (CTA-861-D) VIC range: [1..64]
7246 * HDMI 2.0 (CTA-861-F) VIC range: [1..107]
4ed29f39
JN		 7247 *
7248 * If the sink lists the VIC in CTA VDB, assume it's fine, regardless of HDMI
7249 * version.
1cbc1f0d
JN		 7250 */
7251static u8 vic_for_avi_infoframe(const struct drm_connector *connector, u8 vic)
7252{
4ed29f39
JN		 7253 if (!is_hdmi2_sink(connector) && vic > 64 &&
7254 !cta_vdb_has_vic(connector, vic))
cfd6f8c3
VS		 7255 return 0;
7256
7257 return vic;
7258}
7259
10a85120
TR		 7260/**
7261 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
7262 * data from a DRM display mode
7263 * @frame: HDMI AVI infoframe
13d0add3 7264 * @connector: the connector
10a85120
TR		 7265 * @mode: DRM display mode
7266 *
db6cf833 7267 * Return: 0 on success or a negative error code on failure.
10a85120
TR		 7268 */
7269int
7270drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
192a3aa0 7271 const struct drm_connector *connector,
13d0add3 7272 const struct drm_display_mode *mode)
10a85120 7273{
a9c266c2 7274 enum hdmi_picture_aspect picture_aspect;
d2b43473 7275 u8 vic, hdmi_vic;
10a85120
TR		 7276
7277 if (!frame || !mode)
7278 return -EINVAL;
7279
5ee0caf1 7280 hdmi_avi_infoframe_init(frame);
10a85120 7281
bf02db99
DL		 7282 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
7283 frame->pixel_repeat = 1;
7284
d2b43473
WL		 7285 vic = drm_mode_cea_vic(connector, mode);
7286 hdmi_vic = drm_mode_hdmi_vic(connector, mode);
0c1f528c 7287
10a85120 7288 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
0967e6a5 7289
50525c33
SL		 7290 /*
7291 * As some drivers don't support atomic, we can't use connector state.
7292 * So just initialize the frame with default values, just the same way
7293 * as it's done with other properties here.
7294 */
7295 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
7296 frame->itc = 0;
7297
69ab6d35
VK		 7298 /*
7299 * Populate picture aspect ratio from either
d2b43473 7300 * user input (if specified) or from the CEA/HDMI mode lists.
69ab6d35 7301 */
a9c266c2 7302 picture_aspect = mode->picture_aspect_ratio;
d2b43473
WL		 7303 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) {
7304 if (vic)
7305 picture_aspect = drm_get_cea_aspect_ratio(vic);
7306 else if (hdmi_vic)
7307 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic);
7308 }
0967e6a5 7309
a9c266c2
VS		 7310 /*
7311 * The infoframe can't convey anything but none, 4:3
7312 * and 16:9, so if the user has asked for anything else
7313 * we can only satisfy it by specifying the right VIC.
7314 */
7315 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
d2b43473
WL		 7316 if (vic) {
7317 if (picture_aspect != drm_get_cea_aspect_ratio(vic))
7318 return -EINVAL;
7319 } else if (hdmi_vic) {
7320 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic))
7321 return -EINVAL;
7322 } else {
a9c266c2 7323 return -EINVAL;
d2b43473
WL		 7324 }
7325
a9c266c2
VS		 7326 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
7327 }
7328
1cbc1f0d 7329 frame->video_code = vic_for_avi_infoframe(connector, vic);
a9c266c2 7330 frame->picture_aspect = picture_aspect;
10a85120 7331 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
24d01805 7332 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
10a85120
TR		 7333
7334 return 0;
7335}
7336EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
83dd0008 7337
a2ce26f8
VS		 7338/**
7339 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
7340 * quantization range information
7341 * @frame: HDMI AVI infoframe
13d0add3 7342 * @connector: the connector
779c4c28 7343 * @mode: DRM display mode
a2ce26f8 7344 * @rgb_quant_range: RGB quantization range (Q)
a2ce26f8
VS		 7345 */
7346void
7347drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
192a3aa0 7348 const struct drm_connector *connector,
779c4c28 7349 const struct drm_display_mode *mode,
1581b2df 7350 enum hdmi_quantization_range rgb_quant_range)
a2ce26f8 7351{
1581b2df
VS		 7352 const struct drm_display_info *info = &connector->display_info;
7353
a2ce26f8
VS		 7354 /*
7355 * CEA-861:
7356 * "A Source shall not send a non-zero Q value that does not correspond
7357 * to the default RGB Quantization Range for the transmitted Picture
7358 * unless the Sink indicates support for the Q bit in a Video
7359 * Capabilities Data Block."
779c4c28
VS		 7360 *
7361 * HDMI 2.0 recommends sending non-zero Q when it does match the
7362 * default RGB quantization range for the mode, even when QS=0.
a2ce26f8 7363 */
1581b2df 7364 if (info->rgb_quant_range_selectable ||
779c4c28 7365 rgb_quant_range == drm_default_rgb_quant_range(mode))
a2ce26f8
VS		 7366 frame->quantization_range = rgb_quant_range;
7367 else
7368 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
fcc8a22c
VS		 7369
7370 /*
7371 * CEA-861-F:
7372 * "When transmitting any RGB colorimetry, the Source should set the
7373 * YQ-field to match the RGB Quantization Range being transmitted
7374 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
7375 * set YQ=1) and the Sink shall ignore the YQ-field."
9271c0ca
VS		 7376 *
7377 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
7378 * by non-zero YQ when receiving RGB. There doesn't seem to be any
7379 * good way to tell which version of CEA-861 the sink supports, so
7380 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
96c92551 7381 * on CEA-861-F.
fcc8a22c 7382 */
13d0add3 7383 if (!is_hdmi2_sink(connector) ||
9271c0ca 7384 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
fcc8a22c
VS		 7385 frame->ycc_quantization_range =
7386 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
7387 else
7388 frame->ycc_quantization_range =
7389 HDMI_YCC_QUANTIZATION_RANGE_FULL;
a2ce26f8
VS		 7390}
7391EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
7392
4eed4a0a
DL		 7393static enum hdmi_3d_structure
7394s3d_structure_from_display_mode(const struct drm_display_mode *mode)
7395{
7396 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
7397
7398 switch (layout) {
7399 case DRM_MODE_FLAG_3D_FRAME_PACKING:
7400 return HDMI_3D_STRUCTURE_FRAME_PACKING;
7401 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
7402 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
7403 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
7404 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
7405 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
7406 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
7407 case DRM_MODE_FLAG_3D_L_DEPTH:
7408 return HDMI_3D_STRUCTURE_L_DEPTH;
7409 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
7410 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
7411 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
7412 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
7413 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
7414 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
7415 default:
7416 return HDMI_3D_STRUCTURE_INVALID;
7417 }
7418}
7419
83dd0008
LD		 7420/**
7421 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
7422 * data from a DRM display mode
7423 * @frame: HDMI vendor infoframe
f1781e9b 7424 * @connector: the connector
83dd0008
LD		 7425 * @mode: DRM display mode
7426 *
7427 * Note that there's is a need to send HDMI vendor infoframes only when using a
7428 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
7429 * function will return -EINVAL, error that can be safely ignored.
7430 *
db6cf833 7431 * Return: 0 on success or a negative error code on failure.
83dd0008
LD		 7432 */
7433int
7434drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
192a3aa0 7435 const struct drm_connector *connector,
83dd0008
LD		 7436 const struct drm_display_mode *mode)
7437{
f1781e9b
VS		 7438 /*
7439 * FIXME: sil-sii8620 doesn't have a connector around when
7440 * we need one, so we have to be prepared for a NULL connector.
7441 */
7442 bool has_hdmi_infoframe = connector ?
7443 connector->display_info.has_hdmi_infoframe : false;
83dd0008 7444 int err;
83dd0008
LD		 7445
7446 if (!frame || !mode)
7447 return -EINVAL;
7448
f1781e9b
VS		 7449 if (!has_hdmi_infoframe)
7450 return -EINVAL;
7451
949561eb
VS		 7452 err = hdmi_vendor_infoframe_init(frame);
7453 if (err < 0)
7454 return err;
4eed4a0a 7455
f1781e9b
VS		 7456 /*
7457 * Even if it's not absolutely necessary to send the infoframe
7458 * (ie.vic==0 and s3d_struct==0) we will still send it if we
7459 * know that the sink can handle it. This is based on a
7460 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
0ae865ef 7461 * have trouble realizing that they should switch from 3D to 2D
f1781e9b
VS		 7462 * mode if the source simply stops sending the infoframe when
7463 * it wants to switch from 3D to 2D.
7464 */
949561eb 7465 frame->vic = drm_mode_hdmi_vic(connector, mode);
f1781e9b 7466 frame->s3d_struct = s3d_structure_from_display_mode(mode);
83dd0008
LD		 7467
7468 return 0;
7469}
7470EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
40d9b043 7471
7f261afd
VS		 7472static void drm_parse_tiled_block(struct drm_connector *connector,
7473 const struct displayid_block *block)
5e546cd5 7474{
092c367a 7475 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
5e546cd5
DA		 7476 u16 w, h;
7477 u8 tile_v_loc, tile_h_loc;
7478 u8 num_v_tile, num_h_tile;
7479 struct drm_tile_group *tg;
7480
7481 w = tile->tile_size[0] | tile->tile_size[1] << 8;
7482 h = tile->tile_size[2] | tile->tile_size[3] << 8;
7483
7484 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
7485 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
7486 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
7487 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
7488
7489 connector->has_tile = true;
7490 if (tile->tile_cap & 0x80)
7491 connector->tile_is_single_monitor = true;
7492
7493 connector->num_h_tile = num_h_tile + 1;
7494 connector->num_v_tile = num_v_tile + 1;
7495 connector->tile_h_loc = tile_h_loc;
7496 connector->tile_v_loc = tile_v_loc;
7497 connector->tile_h_size = w + 1;
7498 connector->tile_v_size = h + 1;
7499
e1e7bc48
JN		 7500 drm_dbg_kms(connector->dev,
7501 "[CONNECTOR:%d:%s] tile cap 0x%x, size %dx%d, num tiles %dx%d, location %dx%d, vend %c%c%c",
7502 connector->base.id, connector->name,
7503 tile->tile_cap,
7504 connector->tile_h_size, connector->tile_v_size,
7505 connector->num_h_tile, connector->num_v_tile,
7506 connector->tile_h_loc, connector->tile_v_loc,
7507 tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
5e546cd5
DA		 7508
7509 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
392f9fcb 7510 if (!tg)
5e546cd5 7511 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
5e546cd5 7512 if (!tg)
7f261afd 7513 return;
5e546cd5
DA		 7514
7515 if (connector->tile_group != tg) {
7516 /* if we haven't got a pointer,
7517 take the reference, drop ref to old tile group */
392f9fcb 7518 if (connector->tile_group)
5e546cd5 7519 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5e546cd5 7520 connector->tile_group = tg;
392f9fcb 7521 } else {
5e546cd5
DA		 7522 /* if same tile group, then release the ref we just took. */
7523 drm_mode_put_tile_group(connector->dev, tg);
392f9fcb 7524 }
5e546cd5
DA		 7525}
7526
c5a486af
JN		 7527static bool displayid_is_tiled_block(const struct displayid_iter *iter,
7528 const struct displayid_block *block)
7529{
e0a200ab 7530 return (displayid_version(iter) < DISPLAY_ID_STRUCTURE_VER_20 &&
c5a486af
JN		 7531 block->tag == DATA_BLOCK_TILED_DISPLAY) ||
7532 (displayid_version(iter) == DISPLAY_ID_STRUCTURE_VER_20 &&
7533 block->tag == DATA_BLOCK_2_TILED_DISPLAY_TOPOLOGY);
7534}
7535
c7b2dee4
JN		 7536static void _drm_update_tile_info(struct drm_connector *connector,
7537 const struct drm_edid *drm_edid)
40d9b043 7538{
bfd4e192
JN		 7539 const struct displayid_block *block;
7540 struct displayid_iter iter;
36881184 7541
40d9b043 7542 connector->has_tile = false;
7f261afd 7543
d9ba1b4c 7544 displayid_iter_edid_begin(drm_edid, &iter);
bfd4e192 7545 displayid_iter_for_each(block, &iter) {
c5a486af 7546 if (displayid_is_tiled_block(&iter, block))
bfd4e192 7547 drm_parse_tiled_block(connector, block);
40d9b043 7548 }
bfd4e192 7549 displayid_iter_end(&iter);
40d9b043 7550
7f261afd 7551 if (!connector->has_tile && connector->tile_group) {
40d9b043
DA		 7552 drm_mode_put_tile_group(connector->dev, connector->tile_group);
7553 connector->tile_group = NULL;
7554 }
40d9b043 7555}
7218779e
JN		 7556
7557/**
7558 * drm_edid_is_digital - is digital?
7559 * @drm_edid: The EDID
7560 *
7561 * Return true if input is digital.
7562 */
7563bool drm_edid_is_digital(const struct drm_edid *drm_edid)
7564{
7565 return drm_edid && drm_edid->edid &&
7566 drm_edid->edid->input & DRM_EDID_INPUT_DIGITAL;
7567}
7568EXPORT_SYMBOL(drm_edid_is_digital);
Linux 6.x block layer and io_uring tree(s)