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drm/edid: constify struct detailed_timing in lower level parsing
[linux-2.6-block.git] / drivers / gpu / drm / drm_edid.c
CommitLineData
f453ba04
DA		 1/*
2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
61e57a8d 5 * Copyright 2010 Red Hat, Inc.
f453ba04
DA		 6 *
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
8 * FB layer.
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 */
9c79edec 30
18a9cbbe 31#include <linux/bitfield.h>
10a85120 32#include <linux/hdmi.h>
f453ba04 33#include <linux/i2c.h>
9c79edec 34#include <linux/kernel.h>
47819ba2 35#include <linux/module.h>
36b73b05 36#include <linux/pci.h>
9c79edec 37#include <linux/slab.h>
5cb8eaa2 38#include <linux/vga_switcheroo.h>
9c79edec
JN		 39
40#include <drm/drm_displayid.h>
41#include <drm/drm_drv.h>
760285e7 42#include <drm/drm_edid.h>
9338203c 43#include <drm/drm_encoder.h>
9c79edec 44#include <drm/drm_print.h>
62c58af3 45#include <drm/drm_scdc_helper.h>
f453ba04 46
969218fe
TI		 47#include "drm_crtc_internal.h"
48
13931579
AJ		 49#define version_greater(edid, maj, min) \
50 (((edid)->version > (maj)) || \
51 ((edid)->version == (maj) && (edid)->revision > (min)))
f453ba04 52
37eab1fe
JN		 53static int oui(u8 first, u8 second, u8 third)
54{
55 return (first << 16) | (second << 8) | third;
56}
57
d1ff6409
AJ		 58#define EDID_EST_TIMINGS 16
59#define EDID_STD_TIMINGS 8
60#define EDID_DETAILED_TIMINGS 4
f453ba04
DA		 61
62/*
63 * EDID blocks out in the wild have a variety of bugs, try to collect
64 * them here (note that userspace may work around broken monitors first,
65 * but fixes should make their way here so that the kernel "just works"
66 * on as many displays as possible).
67 */
68
69/* First detailed mode wrong, use largest 60Hz mode */
70#define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
71/* Reported 135MHz pixel clock is too high, needs adjustment */
72#define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
73/* Prefer the largest mode at 75 Hz */
74#define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
75/* Detail timing is in cm not mm */
76#define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
77/* Detailed timing descriptors have bogus size values, so just take the
78 * maximum size and use that.
79 */
80#define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
f453ba04
DA		 81/* use +hsync +vsync for detailed mode */
82#define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
bc42aabc
AJ		 83/* Force reduced-blanking timings for detailed modes */
84#define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
49d45a31
RM		 85/* Force 8bpc */
86#define EDID_QUIRK_FORCE_8BPC (1 << 8)
bc5b9641
MK		 87/* Force 12bpc */
88#define EDID_QUIRK_FORCE_12BPC (1 << 9)
e10aec65
MK		 89/* Force 6bpc */
90#define EDID_QUIRK_FORCE_6BPC (1 << 10)
e345da82
MK		 91/* Force 10bpc */
92#define EDID_QUIRK_FORCE_10BPC (1 << 11)
66660d4c
DA		 93/* Non desktop display (i.e. HMD) */
94#define EDID_QUIRK_NON_DESKTOP (1 << 12)
3c537889 95
2869f599
PZ		 96#define MICROSOFT_IEEE_OUI 0xca125c
97
13931579
AJ		 98struct detailed_mode_closure {
99 struct drm_connector *connector;
100 struct edid *edid;
101 bool preferred;
102 u32 quirks;
103 int modes;
104};
f453ba04 105
5c61259e
ZY		 106#define LEVEL_DMT 0
107#define LEVEL_GTF 1
7a374350
AJ		 108#define LEVEL_GTF2 2
109#define LEVEL_CVT 3
5c61259e 110
7d1be0a0 111#define EDID_QUIRK(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _quirks) \
e8de4d55 112{ \
7d1be0a0
DA		 113 .panel_id = drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, \
114 product_id), \
e8de4d55
DA		 115 .quirks = _quirks \
116}
117
23c4cfbd 118static const struct edid_quirk {
e8de4d55 119 u32 panel_id;
f453ba04
DA		 120 u32 quirks;
121} edid_quirk_list[] = {
122 /* Acer AL1706 */
7d1be0a0 123 EDID_QUIRK('A', 'C', 'R', 44358, EDID_QUIRK_PREFER_LARGE_60),
f453ba04 124 /* Acer F51 */
7d1be0a0 125 EDID_QUIRK('A', 'P', 'I', 0x7602, EDID_QUIRK_PREFER_LARGE_60),
f453ba04 126
e10aec65 127 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
7d1be0a0 128 EDID_QUIRK('A', 'E', 'O', 0, EDID_QUIRK_FORCE_6BPC),
e10aec65 129
0711a43b 130 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
7d1be0a0 131 EDID_QUIRK('B', 'O', 'E', 0x78b, EDID_QUIRK_FORCE_6BPC),
0711a43b 132
06998a75 133 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
7d1be0a0 134 EDID_QUIRK('C', 'P', 'T', 0x17df, EDID_QUIRK_FORCE_6BPC),
06998a75 135
25da7504 136 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
7d1be0a0 137 EDID_QUIRK('S', 'D', 'C', 0x3652, EDID_QUIRK_FORCE_6BPC),
25da7504 138
922dceff 139 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
7d1be0a0 140 EDID_QUIRK('B', 'O', 'E', 0x0771, EDID_QUIRK_FORCE_6BPC),
922dceff 141
f453ba04 142 /* Belinea 10 15 55 */
7d1be0a0
DA		 143 EDID_QUIRK('M', 'A', 'X', 1516, EDID_QUIRK_PREFER_LARGE_60),
144 EDID_QUIRK('M', 'A', 'X', 0x77e, EDID_QUIRK_PREFER_LARGE_60),
f453ba04
DA		 145
146 /* Envision Peripherals, Inc. EN-7100e */
7d1be0a0 147 EDID_QUIRK('E', 'P', 'I', 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH),
ba1163de 148 /* Envision EN2028 */
7d1be0a0 149 EDID_QUIRK('E', 'P', 'I', 8232, EDID_QUIRK_PREFER_LARGE_60),
f453ba04
DA		 150
151 /* Funai Electronics PM36B */
7d1be0a0 152 EDID_QUIRK('F', 'C', 'M', 13600, EDID_QUIRK_PREFER_LARGE_75 |
e8de4d55 153 EDID_QUIRK_DETAILED_IN_CM),
f453ba04 154
e345da82 155 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
7d1be0a0 156 EDID_QUIRK('L', 'G', 'D', 764, EDID_QUIRK_FORCE_10BPC),
e345da82 157
f453ba04 158 /* LG Philips LCD LP154W01-A5 */
7d1be0a0
DA		 159 EDID_QUIRK('L', 'P', 'L', 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
160 EDID_QUIRK('L', 'P', 'L', 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
f453ba04 161
f453ba04 162 /* Samsung SyncMaster 205BW. Note: irony */
7d1be0a0 163 EDID_QUIRK('S', 'A', 'M', 541, EDID_QUIRK_DETAILED_SYNC_PP),
f453ba04 164 /* Samsung SyncMaster 22[5-6]BW */
7d1be0a0
DA		 165 EDID_QUIRK('S', 'A', 'M', 596, EDID_QUIRK_PREFER_LARGE_60),
166 EDID_QUIRK('S', 'A', 'M', 638, EDID_QUIRK_PREFER_LARGE_60),
bc42aabc 167
bc5b9641 168 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
7d1be0a0 169 EDID_QUIRK('S', 'N', 'Y', 0x2541, EDID_QUIRK_FORCE_12BPC),
bc5b9641 170
bc42aabc 171 /* ViewSonic VA2026w */
7d1be0a0 172 EDID_QUIRK('V', 'S', 'C', 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING),
118bdbd8
AD		 173
174 /* Medion MD 30217 PG */
7d1be0a0 175 EDID_QUIRK('M', 'E', 'D', 0x7b8, EDID_QUIRK_PREFER_LARGE_75),
49d45a31 176
11bcf5f7 177 /* Lenovo G50 */
7d1be0a0 178 EDID_QUIRK('S', 'D', 'C', 18514, EDID_QUIRK_FORCE_6BPC),
11bcf5f7 179
49d45a31 180 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
7d1be0a0 181 EDID_QUIRK('S', 'E', 'C', 0xd033, EDID_QUIRK_FORCE_8BPC),
36fc5797
TV		 182
183 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
7d1be0a0 184 EDID_QUIRK('E', 'T', 'R', 13896, EDID_QUIRK_FORCE_8BPC),
acb1d8ee 185
30d62d44 186 /* Valve Index Headset */
7d1be0a0
DA		 187 EDID_QUIRK('V', 'L', 'V', 0x91a8, EDID_QUIRK_NON_DESKTOP),
188 EDID_QUIRK('V', 'L', 'V', 0x91b0, EDID_QUIRK_NON_DESKTOP),
189 EDID_QUIRK('V', 'L', 'V', 0x91b1, EDID_QUIRK_NON_DESKTOP),
190 EDID_QUIRK('V', 'L', 'V', 0x91b2, EDID_QUIRK_NON_DESKTOP),
191 EDID_QUIRK('V', 'L', 'V', 0x91b3, EDID_QUIRK_NON_DESKTOP),
192 EDID_QUIRK('V', 'L', 'V', 0x91b4, EDID_QUIRK_NON_DESKTOP),
193 EDID_QUIRK('V', 'L', 'V', 0x91b5, EDID_QUIRK_NON_DESKTOP),
194 EDID_QUIRK('V', 'L', 'V', 0x91b6, EDID_QUIRK_NON_DESKTOP),
195 EDID_QUIRK('V', 'L', 'V', 0x91b7, EDID_QUIRK_NON_DESKTOP),
196 EDID_QUIRK('V', 'L', 'V', 0x91b8, EDID_QUIRK_NON_DESKTOP),
197 EDID_QUIRK('V', 'L', 'V', 0x91b9, EDID_QUIRK_NON_DESKTOP),
198 EDID_QUIRK('V', 'L', 'V', 0x91ba, EDID_QUIRK_NON_DESKTOP),
199 EDID_QUIRK('V', 'L', 'V', 0x91bb, EDID_QUIRK_NON_DESKTOP),
200 EDID_QUIRK('V', 'L', 'V', 0x91bc, EDID_QUIRK_NON_DESKTOP),
201 EDID_QUIRK('V', 'L', 'V', 0x91bd, EDID_QUIRK_NON_DESKTOP),
202 EDID_QUIRK('V', 'L', 'V', 0x91be, EDID_QUIRK_NON_DESKTOP),
203 EDID_QUIRK('V', 'L', 'V', 0x91bf, EDID_QUIRK_NON_DESKTOP),
30d62d44 204
6931317c 205 /* HTC Vive and Vive Pro VR Headsets */
7d1be0a0
DA		 206 EDID_QUIRK('H', 'V', 'R', 0xaa01, EDID_QUIRK_NON_DESKTOP),
207 EDID_QUIRK('H', 'V', 'R', 0xaa02, EDID_QUIRK_NON_DESKTOP),
b3b12ea3 208
5a3f6108 209 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */
7d1be0a0
DA		 210 EDID_QUIRK('O', 'V', 'R', 0x0001, EDID_QUIRK_NON_DESKTOP),
211 EDID_QUIRK('O', 'V', 'R', 0x0003, EDID_QUIRK_NON_DESKTOP),
212 EDID_QUIRK('O', 'V', 'R', 0x0004, EDID_QUIRK_NON_DESKTOP),
213 EDID_QUIRK('O', 'V', 'R', 0x0012, EDID_QUIRK_NON_DESKTOP),
90eda8fc
PZ		 214
215 /* Windows Mixed Reality Headsets */
7d1be0a0 216 EDID_QUIRK('A', 'C', 'R', 0x7fce, EDID_QUIRK_NON_DESKTOP),
7d1be0a0 217 EDID_QUIRK('L', 'E', 'N', 0x0408, EDID_QUIRK_NON_DESKTOP),
7d1be0a0
DA		 218 EDID_QUIRK('F', 'U', 'J', 0x1970, EDID_QUIRK_NON_DESKTOP),
219 EDID_QUIRK('D', 'E', 'L', 0x7fce, EDID_QUIRK_NON_DESKTOP),
220 EDID_QUIRK('S', 'E', 'C', 0x144a, EDID_QUIRK_NON_DESKTOP),
221 EDID_QUIRK('A', 'U', 'S', 0xc102, EDID_QUIRK_NON_DESKTOP),
ccffc9eb
PZ		 222
223 /* Sony PlayStation VR Headset */
7d1be0a0 224 EDID_QUIRK('S', 'N', 'Y', 0x0704, EDID_QUIRK_NON_DESKTOP),
29054230
RP		 225
226 /* Sensics VR Headsets */
7d1be0a0 227 EDID_QUIRK('S', 'E', 'N', 0x1019, EDID_QUIRK_NON_DESKTOP),
29054230
RP		 228
229 /* OSVR HDK and HDK2 VR Headsets */
7d1be0a0 230 EDID_QUIRK('S', 'V', 'R', 0x1019, EDID_QUIRK_NON_DESKTOP),
f453ba04
DA		 231};
232
a6b21831
TR		 233/*
234 * Autogenerated from the DMT spec.
235 * This table is copied from xfree86/modes/xf86EdidModes.c.
236 */
237static const struct drm_display_mode drm_dmt_modes[] = {
24b856b1 238 /* 0x01 - 640x350@85Hz */
a6b21831
TR		 239 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
240 736, 832, 0, 350, 382, 385, 445, 0,
241 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 242 /* 0x02 - 640x400@85Hz */
a6b21831
TR		 243 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
244 736, 832, 0, 400, 401, 404, 445, 0,
245 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 246 /* 0x03 - 720x400@85Hz */
a6b21831
TR		 247 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
248 828, 936, 0, 400, 401, 404, 446, 0,
249 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 250 /* 0x04 - 640x480@60Hz */
a6b21831 251 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
fcf22d05 252 752, 800, 0, 480, 490, 492, 525, 0,
a6b21831 253 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 254 /* 0x05 - 640x480@72Hz */
a6b21831
TR		 255 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
256 704, 832, 0, 480, 489, 492, 520, 0,
257 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 258 /* 0x06 - 640x480@75Hz */
a6b21831
TR		 259 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
260 720, 840, 0, 480, 481, 484, 500, 0,
261 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 262 /* 0x07 - 640x480@85Hz */
a6b21831
TR		 263 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
264 752, 832, 0, 480, 481, 484, 509, 0,
265 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 266 /* 0x08 - 800x600@56Hz */
a6b21831
TR		 267 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
268 896, 1024, 0, 600, 601, 603, 625, 0,
269 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 270 /* 0x09 - 800x600@60Hz */
a6b21831
TR		 271 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
272 968, 1056, 0, 600, 601, 605, 628, 0,
273 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 274 /* 0x0a - 800x600@72Hz */
a6b21831
TR		 275 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
276 976, 1040, 0, 600, 637, 643, 666, 0,
277 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 278 /* 0x0b - 800x600@75Hz */
a6b21831
TR		 279 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
280 896, 1056, 0, 600, 601, 604, 625, 0,
281 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 282 /* 0x0c - 800x600@85Hz */
a6b21831
TR		 283 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
284 896, 1048, 0, 600, 601, 604, 631, 0,
285 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 286 /* 0x0d - 800x600@120Hz RB */
a6b21831
TR		 287 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
288 880, 960, 0, 600, 603, 607, 636, 0,
289 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 290 /* 0x0e - 848x480@60Hz */
a6b21831
TR		 291 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
292 976, 1088, 0, 480, 486, 494, 517, 0,
293 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 294 /* 0x0f - 1024x768@43Hz, interlace */
a6b21831 295 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
735b100f 296 1208, 1264, 0, 768, 768, 776, 817, 0,
a6b21831 297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
fcf22d05 298 DRM_MODE_FLAG_INTERLACE) },
24b856b1 299 /* 0x10 - 1024x768@60Hz */
a6b21831
TR		 300 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
301 1184, 1344, 0, 768, 771, 777, 806, 0,
302 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 303 /* 0x11 - 1024x768@70Hz */
a6b21831
TR		 304 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
305 1184, 1328, 0, 768, 771, 777, 806, 0,
306 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 307 /* 0x12 - 1024x768@75Hz */
a6b21831
TR		 308 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
309 1136, 1312, 0, 768, 769, 772, 800, 0,
310 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 311 /* 0x13 - 1024x768@85Hz */
a6b21831
TR		 312 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
313 1168, 1376, 0, 768, 769, 772, 808, 0,
314 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 315 /* 0x14 - 1024x768@120Hz RB */
a6b21831
TR		 316 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
317 1104, 1184, 0, 768, 771, 775, 813, 0,
318 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 319 /* 0x15 - 1152x864@75Hz */
a6b21831
TR		 320 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
321 1344, 1600, 0, 864, 865, 868, 900, 0,
322 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
bfcd74d2
VS		 323 /* 0x55 - 1280x720@60Hz */
324 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
325 1430, 1650, 0, 720, 725, 730, 750, 0,
326 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 327 /* 0x16 - 1280x768@60Hz RB */
a6b21831
TR		 328 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
329 1360, 1440, 0, 768, 771, 778, 790, 0,
330 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 331 /* 0x17 - 1280x768@60Hz */
a6b21831
TR		 332 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
333 1472, 1664, 0, 768, 771, 778, 798, 0,
334 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 335 /* 0x18 - 1280x768@75Hz */
a6b21831
TR		 336 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
337 1488, 1696, 0, 768, 771, 778, 805, 0,
fcf22d05 338 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 339 /* 0x19 - 1280x768@85Hz */
a6b21831
TR		 340 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
341 1496, 1712, 0, 768, 771, 778, 809, 0,
342 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 343 /* 0x1a - 1280x768@120Hz RB */
a6b21831
TR		 344 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
345 1360, 1440, 0, 768, 771, 778, 813, 0,
346 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 347 /* 0x1b - 1280x800@60Hz RB */
a6b21831
TR		 348 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
349 1360, 1440, 0, 800, 803, 809, 823, 0,
350 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 351 /* 0x1c - 1280x800@60Hz */
a6b21831
TR		 352 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
353 1480, 1680, 0, 800, 803, 809, 831, 0,
fcf22d05 354 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 355 /* 0x1d - 1280x800@75Hz */
a6b21831
TR		 356 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
357 1488, 1696, 0, 800, 803, 809, 838, 0,
358 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 359 /* 0x1e - 1280x800@85Hz */
a6b21831
TR		 360 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
361 1496, 1712, 0, 800, 803, 809, 843, 0,
362 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 363 /* 0x1f - 1280x800@120Hz RB */
a6b21831
TR		 364 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
365 1360, 1440, 0, 800, 803, 809, 847, 0,
366 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 367 /* 0x20 - 1280x960@60Hz */
a6b21831
TR		 368 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
369 1488, 1800, 0, 960, 961, 964, 1000, 0,
370 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 371 /* 0x21 - 1280x960@85Hz */
a6b21831
TR		 372 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
373 1504, 1728, 0, 960, 961, 964, 1011, 0,
374 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 375 /* 0x22 - 1280x960@120Hz RB */
a6b21831
TR		 376 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
377 1360, 1440, 0, 960, 963, 967, 1017, 0,
378 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 379 /* 0x23 - 1280x1024@60Hz */
a6b21831
TR		 380 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
381 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
382 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 383 /* 0x24 - 1280x1024@75Hz */
a6b21831
TR		 384 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
385 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
386 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 387 /* 0x25 - 1280x1024@85Hz */
a6b21831
TR		 388 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
389 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
390 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 391 /* 0x26 - 1280x1024@120Hz RB */
a6b21831
TR		 392 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
393 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
394 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 395 /* 0x27 - 1360x768@60Hz */
a6b21831
TR		 396 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
397 1536, 1792, 0, 768, 771, 777, 795, 0,
398 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 399 /* 0x28 - 1360x768@120Hz RB */
a6b21831
TR		 400 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
401 1440, 1520, 0, 768, 771, 776, 813, 0,
402 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 403 /* 0x51 - 1366x768@60Hz */
404 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
405 1579, 1792, 0, 768, 771, 774, 798, 0,
406 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
407 /* 0x56 - 1366x768@60Hz */
408 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
409 1436, 1500, 0, 768, 769, 772, 800, 0,
410 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 411 /* 0x29 - 1400x1050@60Hz RB */
a6b21831
TR		 412 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
413 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
414 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 415 /* 0x2a - 1400x1050@60Hz */
a6b21831
TR		 416 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
417 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
418 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 419 /* 0x2b - 1400x1050@75Hz */
a6b21831
TR		 420 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
421 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
422 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 423 /* 0x2c - 1400x1050@85Hz */
a6b21831
TR		 424 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
425 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
426 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 427 /* 0x2d - 1400x1050@120Hz RB */
a6b21831
TR		 428 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
429 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
430 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 431 /* 0x2e - 1440x900@60Hz RB */
a6b21831
TR		 432 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
433 1520, 1600, 0, 900, 903, 909, 926, 0,
434 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 435 /* 0x2f - 1440x900@60Hz */
a6b21831
TR		 436 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
437 1672, 1904, 0, 900, 903, 909, 934, 0,
438 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 439 /* 0x30 - 1440x900@75Hz */
a6b21831
TR		 440 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
441 1688, 1936, 0, 900, 903, 909, 942, 0,
442 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 443 /* 0x31 - 1440x900@85Hz */
a6b21831
TR		 444 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
445 1696, 1952, 0, 900, 903, 909, 948, 0,
446 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 447 /* 0x32 - 1440x900@120Hz RB */
a6b21831
TR		 448 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
449 1520, 1600, 0, 900, 903, 909, 953, 0,
450 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 451 /* 0x53 - 1600x900@60Hz */
452 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
453 1704, 1800, 0, 900, 901, 904, 1000, 0,
454 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 455 /* 0x33 - 1600x1200@60Hz */
a6b21831
TR		 456 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
457 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
458 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 459 /* 0x34 - 1600x1200@65Hz */
a6b21831
TR		 460 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
461 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
462 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 463 /* 0x35 - 1600x1200@70Hz */
a6b21831
TR		 464 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
465 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
466 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 467 /* 0x36 - 1600x1200@75Hz */
a6b21831
TR		 468 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
469 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
470 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 471 /* 0x37 - 1600x1200@85Hz */
a6b21831
TR		 472 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
473 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
474 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 475 /* 0x38 - 1600x1200@120Hz RB */
a6b21831
TR		 476 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
477 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
478 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 479 /* 0x39 - 1680x1050@60Hz RB */
a6b21831
TR		 480 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
481 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
482 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 483 /* 0x3a - 1680x1050@60Hz */
a6b21831
TR		 484 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
485 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
486 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 487 /* 0x3b - 1680x1050@75Hz */
a6b21831
TR		 488 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
489 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
490 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 491 /* 0x3c - 1680x1050@85Hz */
a6b21831
TR		 492 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
493 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
494 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 495 /* 0x3d - 1680x1050@120Hz RB */
a6b21831
TR		 496 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
497 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
498 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 499 /* 0x3e - 1792x1344@60Hz */
a6b21831
TR		 500 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
501 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
502 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 503 /* 0x3f - 1792x1344@75Hz */
a6b21831
TR		 504 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
505 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
506 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 507 /* 0x40 - 1792x1344@120Hz RB */
a6b21831
TR		 508 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
509 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
510 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 511 /* 0x41 - 1856x1392@60Hz */
a6b21831
TR		 512 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
513 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
514 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 515 /* 0x42 - 1856x1392@75Hz */
a6b21831 516 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
fcf22d05 517 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
a6b21831 518 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 519 /* 0x43 - 1856x1392@120Hz RB */
a6b21831
TR		 520 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
521 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
522 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 523 /* 0x52 - 1920x1080@60Hz */
524 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
525 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
526 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 527 /* 0x44 - 1920x1200@60Hz RB */
a6b21831
TR		 528 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
529 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
530 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 531 /* 0x45 - 1920x1200@60Hz */
a6b21831
TR		 532 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
533 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
534 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 535 /* 0x46 - 1920x1200@75Hz */
a6b21831
TR		 536 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
537 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
538 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 539 /* 0x47 - 1920x1200@85Hz */
a6b21831
TR		 540 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
541 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
542 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 543 /* 0x48 - 1920x1200@120Hz RB */
a6b21831
TR		 544 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
545 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
546 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 547 /* 0x49 - 1920x1440@60Hz */
a6b21831
TR		 548 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
549 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
550 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 551 /* 0x4a - 1920x1440@75Hz */
a6b21831
TR		 552 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
553 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
554 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 555 /* 0x4b - 1920x1440@120Hz RB */
a6b21831
TR		 556 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
557 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
558 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 559 /* 0x54 - 2048x1152@60Hz */
560 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
561 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
562 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 563 /* 0x4c - 2560x1600@60Hz RB */
a6b21831
TR		 564 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
565 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
566 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 567 /* 0x4d - 2560x1600@60Hz */
a6b21831
TR		 568 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
569 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
570 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 571 /* 0x4e - 2560x1600@75Hz */
a6b21831
TR		 572 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
573 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
574 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 575 /* 0x4f - 2560x1600@85Hz */
a6b21831
TR		 576 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
577 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
578 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 579 /* 0x50 - 2560x1600@120Hz RB */
a6b21831
TR		 580 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
581 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
582 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 583 /* 0x57 - 4096x2160@60Hz RB */
584 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
585 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
586 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
587 /* 0x58 - 4096x2160@59.94Hz RB */
588 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
589 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
590 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
a6b21831
TR		 591};
592
e7bfa5c4
VS		 593/*
594 * These more or less come from the DMT spec. The 720x400 modes are
595 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
596 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
597 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
598 * mode.
599 *
600 * The DMT modes have been fact-checked; the rest are mild guesses.
601 */
a6b21831
TR		 602static const struct drm_display_mode edid_est_modes[] = {
603 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
604 968, 1056, 0, 600, 601, 605, 628, 0,
605 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
606 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
607 896, 1024, 0, 600, 601, 603, 625, 0,
608 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
609 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
610 720, 840, 0, 480, 481, 484, 500, 0,
611 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
612 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
87707cfd 613 704, 832, 0, 480, 489, 492, 520, 0,
a6b21831
TR		 614 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
615 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
616 768, 864, 0, 480, 483, 486, 525, 0,
617 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
87707cfd 618 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
a6b21831
TR		 619 752, 800, 0, 480, 490, 492, 525, 0,
620 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
621 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
622 846, 900, 0, 400, 421, 423, 449, 0,
623 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
624 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
625 846, 900, 0, 400, 412, 414, 449, 0,
626 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
627 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
628 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
629 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
87707cfd 630 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
a6b21831
TR		 631 1136, 1312, 0, 768, 769, 772, 800, 0,
632 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
633 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
634 1184, 1328, 0, 768, 771, 777, 806, 0,
635 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
636 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
637 1184, 1344, 0, 768, 771, 777, 806, 0,
638 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
639 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
640 1208, 1264, 0, 768, 768, 776, 817, 0,
641 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
642 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
643 928, 1152, 0, 624, 625, 628, 667, 0,
644 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
645 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
646 896, 1056, 0, 600, 601, 604, 625, 0,
647 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
648 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
649 976, 1040, 0, 600, 637, 643, 666, 0,
650 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
651 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
652 1344, 1600, 0, 864, 865, 868, 900, 0,
653 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
654};
655
656struct minimode {
657 short w;
658 short h;
659 short r;
660 short rb;
661};
662
663static const struct minimode est3_modes[] = {
664 /* byte 6 */
665 { 640, 350, 85, 0 },
666 { 640, 400, 85, 0 },
667 { 720, 400, 85, 0 },
668 { 640, 480, 85, 0 },
669 { 848, 480, 60, 0 },
670 { 800, 600, 85, 0 },
671 { 1024, 768, 85, 0 },
672 { 1152, 864, 75, 0 },
673 /* byte 7 */
674 { 1280, 768, 60, 1 },
675 { 1280, 768, 60, 0 },
676 { 1280, 768, 75, 0 },
677 { 1280, 768, 85, 0 },
678 { 1280, 960, 60, 0 },
679 { 1280, 960, 85, 0 },
680 { 1280, 1024, 60, 0 },
681 { 1280, 1024, 85, 0 },
682 /* byte 8 */
683 { 1360, 768, 60, 0 },
684 { 1440, 900, 60, 1 },
685 { 1440, 900, 60, 0 },
686 { 1440, 900, 75, 0 },
687 { 1440, 900, 85, 0 },
688 { 1400, 1050, 60, 1 },
689 { 1400, 1050, 60, 0 },
690 { 1400, 1050, 75, 0 },
691 /* byte 9 */
692 { 1400, 1050, 85, 0 },
693 { 1680, 1050, 60, 1 },
694 { 1680, 1050, 60, 0 },
695 { 1680, 1050, 75, 0 },
696 { 1680, 1050, 85, 0 },
697 { 1600, 1200, 60, 0 },
698 { 1600, 1200, 65, 0 },
699 { 1600, 1200, 70, 0 },
700 /* byte 10 */
701 { 1600, 1200, 75, 0 },
702 { 1600, 1200, 85, 0 },
703 { 1792, 1344, 60, 0 },
c068b32a 704 { 1792, 1344, 75, 0 },
a6b21831
TR		 705 { 1856, 1392, 60, 0 },
706 { 1856, 1392, 75, 0 },
707 { 1920, 1200, 60, 1 },
708 { 1920, 1200, 60, 0 },
709 /* byte 11 */
710 { 1920, 1200, 75, 0 },
711 { 1920, 1200, 85, 0 },
712 { 1920, 1440, 60, 0 },
713 { 1920, 1440, 75, 0 },
714};
715
716static const struct minimode extra_modes[] = {
717 { 1024, 576, 60, 0 },
718 { 1366, 768, 60, 0 },
719 { 1600, 900, 60, 0 },
720 { 1680, 945, 60, 0 },
721 { 1920, 1080, 60, 0 },
722 { 2048, 1152, 60, 0 },
723 { 2048, 1536, 60, 0 },
724};
725
726/*
7befe621 727 * From CEA/CTA-861 spec.
d9278b4c 728 *
7befe621 729 * Do not access directly, instead always use cea_mode_for_vic().
a6b21831 730 */
8c1b2bd9 731static const struct drm_display_mode edid_cea_modes_1[] = {
78691960 732 /* 1 - 640x480@60Hz 4:3 */
a6b21831
TR		 733 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
734 752, 800, 0, 480, 490, 492, 525, 0,
ee7925bb 735 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 736 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 737 /* 2 - 720x480@60Hz 4:3 */
a6b21831
TR		 738 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
739 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 740 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 741 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 742 /* 3 - 720x480@60Hz 16:9 */
a6b21831
TR		 743 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
744 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 745 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 746 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 747 /* 4 - 1280x720@60Hz 16:9 */
a6b21831
TR		 748 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
749 1430, 1650, 0, 720, 725, 730, 750, 0,
ee7925bb 750 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 751 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 752 /* 5 - 1920x1080i@60Hz 16:9 */
a6b21831
TR		 753 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
754 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
755 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 756 DRM_MODE_FLAG_INTERLACE),
0425662f 757 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 758 /* 6 - 720(1440)x480i@60Hz 4:3 */
fb01d280
CT		 759 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
760 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 761 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 762 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 763 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 764 /* 7 - 720(1440)x480i@60Hz 16:9 */
fb01d280
CT		 765 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
766 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 767 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 768 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 769 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 770 /* 8 - 720(1440)x240@60Hz 4:3 */
fb01d280
CT		 771 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
772 801, 858, 0, 240, 244, 247, 262, 0,
a6b21831 773 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 774 DRM_MODE_FLAG_DBLCLK),
0425662f 775 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 776 /* 9 - 720(1440)x240@60Hz 16:9 */
fb01d280
CT		 777 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
778 801, 858, 0, 240, 244, 247, 262, 0,
a6b21831 779 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 780 DRM_MODE_FLAG_DBLCLK),
0425662f 781 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 782 /* 10 - 2880x480i@60Hz 4:3 */
a6b21831
TR		 783 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
784 3204, 3432, 0, 480, 488, 494, 525, 0,
785 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 786 DRM_MODE_FLAG_INTERLACE),
0425662f 787 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 788 /* 11 - 2880x480i@60Hz 16:9 */
a6b21831
TR		 789 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
790 3204, 3432, 0, 480, 488, 494, 525, 0,
791 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 792 DRM_MODE_FLAG_INTERLACE),
0425662f 793 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 794 /* 12 - 2880x240@60Hz 4:3 */
a6b21831
TR		 795 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
796 3204, 3432, 0, 240, 244, 247, 262, 0,
ee7925bb 797 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 798 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 799 /* 13 - 2880x240@60Hz 16:9 */
a6b21831
TR		 800 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
801 3204, 3432, 0, 240, 244, 247, 262, 0,
ee7925bb 802 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 803 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 804 /* 14 - 1440x480@60Hz 4:3 */
a6b21831
TR		 805 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
806 1596, 1716, 0, 480, 489, 495, 525, 0,
ee7925bb 807 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 808 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 809 /* 15 - 1440x480@60Hz 16:9 */
a6b21831
TR		 810 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
811 1596, 1716, 0, 480, 489, 495, 525, 0,
ee7925bb 812 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 813 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 814 /* 16 - 1920x1080@60Hz 16:9 */
a6b21831
TR		 815 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
816 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 817 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 818 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 819 /* 17 - 720x576@50Hz 4:3 */
a6b21831
TR		 820 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
821 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 822 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 823 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 824 /* 18 - 720x576@50Hz 16:9 */
a6b21831
TR		 825 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
826 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 827 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 828 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 829 /* 19 - 1280x720@50Hz 16:9 */
a6b21831
TR		 830 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
831 1760, 1980, 0, 720, 725, 730, 750, 0,
ee7925bb 832 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 833 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 834 /* 20 - 1920x1080i@50Hz 16:9 */
a6b21831
TR		 835 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
836 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
837 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 838 DRM_MODE_FLAG_INTERLACE),
0425662f 839 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 840 /* 21 - 720(1440)x576i@50Hz 4:3 */
fb01d280
CT		 841 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
842 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 843 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 844 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 845 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 846 /* 22 - 720(1440)x576i@50Hz 16:9 */
fb01d280
CT		 847 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
848 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 849 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 850 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 851 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 852 /* 23 - 720(1440)x288@50Hz 4:3 */
fb01d280
CT		 853 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
854 795, 864, 0, 288, 290, 293, 312, 0,
a6b21831 855 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 856 DRM_MODE_FLAG_DBLCLK),
0425662f 857 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 858 /* 24 - 720(1440)x288@50Hz 16:9 */
fb01d280
CT		 859 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
860 795, 864, 0, 288, 290, 293, 312, 0,
a6b21831 861 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 862 DRM_MODE_FLAG_DBLCLK),
0425662f 863 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 864 /* 25 - 2880x576i@50Hz 4:3 */
a6b21831
TR		 865 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
866 3180, 3456, 0, 576, 580, 586, 625, 0,
867 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 868 DRM_MODE_FLAG_INTERLACE),
0425662f 869 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 870 /* 26 - 2880x576i@50Hz 16:9 */
a6b21831
TR		 871 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
872 3180, 3456, 0, 576, 580, 586, 625, 0,
873 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 874 DRM_MODE_FLAG_INTERLACE),
0425662f 875 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 876 /* 27 - 2880x288@50Hz 4:3 */
a6b21831
TR		 877 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
878 3180, 3456, 0, 288, 290, 293, 312, 0,
ee7925bb 879 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 880 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 881 /* 28 - 2880x288@50Hz 16:9 */
a6b21831
TR		 882 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
883 3180, 3456, 0, 288, 290, 293, 312, 0,
ee7925bb 884 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 885 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 886 /* 29 - 1440x576@50Hz 4:3 */
a6b21831
TR		 887 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
888 1592, 1728, 0, 576, 581, 586, 625, 0,
ee7925bb 889 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 890 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 891 /* 30 - 1440x576@50Hz 16:9 */
a6b21831
TR		 892 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
893 1592, 1728, 0, 576, 581, 586, 625, 0,
ee7925bb 894 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 895 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 896 /* 31 - 1920x1080@50Hz 16:9 */
a6b21831
TR		 897 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
898 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 899 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 900 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 901 /* 32 - 1920x1080@24Hz 16:9 */
a6b21831
TR		 902 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
903 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 904 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 905 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 906 /* 33 - 1920x1080@25Hz 16:9 */
a6b21831
TR		 907 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
908 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 909 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 910 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 911 /* 34 - 1920x1080@30Hz 16:9 */
a6b21831
TR		 912 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
913 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 914 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 915 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 916 /* 35 - 2880x480@60Hz 4:3 */
a6b21831
TR		 917 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
918 3192, 3432, 0, 480, 489, 495, 525, 0,
ee7925bb 919 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 920 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 921 /* 36 - 2880x480@60Hz 16:9 */
a6b21831
TR		 922 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
923 3192, 3432, 0, 480, 489, 495, 525, 0,
ee7925bb 924 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 925 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 926 /* 37 - 2880x576@50Hz 4:3 */
a6b21831
TR		 927 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
928 3184, 3456, 0, 576, 581, 586, 625, 0,
ee7925bb 929 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 930 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 931 /* 38 - 2880x576@50Hz 16:9 */
a6b21831
TR		 932 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
933 3184, 3456, 0, 576, 581, 586, 625, 0,
ee7925bb 934 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 935 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 936 /* 39 - 1920x1080i@50Hz 16:9 */
a6b21831
TR		 937 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
938 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
939 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 940 DRM_MODE_FLAG_INTERLACE),
0425662f 941 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 942 /* 40 - 1920x1080i@100Hz 16:9 */
a6b21831
TR		 943 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
944 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
945 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 946 DRM_MODE_FLAG_INTERLACE),
0425662f 947 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 948 /* 41 - 1280x720@100Hz 16:9 */
a6b21831
TR		 949 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
950 1760, 1980, 0, 720, 725, 730, 750, 0,
ee7925bb 951 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 952 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 953 /* 42 - 720x576@100Hz 4:3 */
a6b21831
TR		 954 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
955 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 956 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 957 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 958 /* 43 - 720x576@100Hz 16:9 */
a6b21831
TR		 959 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
960 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 961 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 962 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 963 /* 44 - 720(1440)x576i@100Hz 4:3 */
fb01d280
CT		 964 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
965 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 966 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 967 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 968 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 969 /* 45 - 720(1440)x576i@100Hz 16:9 */
fb01d280
CT		 970 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
971 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 972 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 973 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 974 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 975 /* 46 - 1920x1080i@120Hz 16:9 */
a6b21831
TR		 976 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
977 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
978 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 979 DRM_MODE_FLAG_INTERLACE),
0425662f 980 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 981 /* 47 - 1280x720@120Hz 16:9 */
a6b21831
TR		 982 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
983 1430, 1650, 0, 720, 725, 730, 750, 0,
ee7925bb 984 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 985 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 986 /* 48 - 720x480@120Hz 4:3 */
a6b21831
TR		 987 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
988 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 989 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 990 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 991 /* 49 - 720x480@120Hz 16:9 */
a6b21831
TR		 992 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
993 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 994 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 995 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 996 /* 50 - 720(1440)x480i@120Hz 4:3 */
fb01d280
CT		 997 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
998 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 999 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1000 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1001 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1002 /* 51 - 720(1440)x480i@120Hz 16:9 */
fb01d280
CT		 1003 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
1004 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 1005 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1006 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1007 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1008 /* 52 - 720x576@200Hz 4:3 */
a6b21831
TR		 1009 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1010 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 1011 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 1012 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1013 /* 53 - 720x576@200Hz 16:9 */
a6b21831
TR		 1014 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1015 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 1016 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 1017 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1018 /* 54 - 720(1440)x576i@200Hz 4:3 */
fb01d280
CT		 1019 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1020 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 1021 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1022 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1023 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1024 /* 55 - 720(1440)x576i@200Hz 16:9 */
fb01d280
CT		 1025 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1026 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 1027 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1028 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1029 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1030 /* 56 - 720x480@240Hz 4:3 */
a6b21831
TR		 1031 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1032 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 1033 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 1034 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1035 /* 57 - 720x480@240Hz 16:9 */
a6b21831
TR		 1036 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1037 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 1038 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 1039 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1040 /* 58 - 720(1440)x480i@240Hz 4:3 */
fb01d280
CT		 1041 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1042 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 1043 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1044 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1045 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1046 /* 59 - 720(1440)x480i@240Hz 16:9 */
fb01d280
CT		 1047 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1048 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 1049 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1050 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1051 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1052 /* 60 - 1280x720@24Hz 16:9 */
a6b21831
TR		 1053 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1054 3080, 3300, 0, 720, 725, 730, 750, 0,
ee7925bb 1055 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1056 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1057 /* 61 - 1280x720@25Hz 16:9 */
a6b21831
TR		 1058 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1059 3740, 3960, 0, 720, 725, 730, 750, 0,
ee7925bb 1060 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1061 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1062 /* 62 - 1280x720@30Hz 16:9 */
a6b21831
TR		 1063 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1064 3080, 3300, 0, 720, 725, 730, 750, 0,
ee7925bb 1065 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1066 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1067 /* 63 - 1920x1080@120Hz 16:9 */
a6b21831
TR		 1068 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1069 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 1070 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1071 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1072 /* 64 - 1920x1080@100Hz 16:9 */
a6b21831 1073 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
8f0e4907 1074 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 1075 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1076 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1077 /* 65 - 1280x720@24Hz 64:27 */
8ec6e075
SS		 1078 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1079 3080, 3300, 0, 720, 725, 730, 750, 0,
1080 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1081 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1082 /* 66 - 1280x720@25Hz 64:27 */
8ec6e075
SS		 1083 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1084 3740, 3960, 0, 720, 725, 730, 750, 0,
1085 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1086 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1087 /* 67 - 1280x720@30Hz 64:27 */
8ec6e075
SS		 1088 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1089 3080, 3300, 0, 720, 725, 730, 750, 0,
1090 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1091 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1092 /* 68 - 1280x720@50Hz 64:27 */
8ec6e075
SS		 1093 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1094 1760, 1980, 0, 720, 725, 730, 750, 0,
1095 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1096 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1097 /* 69 - 1280x720@60Hz 64:27 */
8ec6e075
SS		 1098 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1099 1430, 1650, 0, 720, 725, 730, 750, 0,
1100 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1101 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1102 /* 70 - 1280x720@100Hz 64:27 */
8ec6e075
SS		 1103 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1104 1760, 1980, 0, 720, 725, 730, 750, 0,
1105 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1106 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1107 /* 71 - 1280x720@120Hz 64:27 */
8ec6e075
SS		 1108 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1109 1430, 1650, 0, 720, 725, 730, 750, 0,
1110 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1111 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1112 /* 72 - 1920x1080@24Hz 64:27 */
8ec6e075
SS		 1113 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1114 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1115 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1116 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1117 /* 73 - 1920x1080@25Hz 64:27 */
8ec6e075
SS		 1118 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1119 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1120 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1121 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1122 /* 74 - 1920x1080@30Hz 64:27 */
8ec6e075
SS		 1123 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1124 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1125 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1126 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1127 /* 75 - 1920x1080@50Hz 64:27 */
8ec6e075
SS		 1128 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1129 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1130 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1131 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1132 /* 76 - 1920x1080@60Hz 64:27 */
8ec6e075
SS		 1133 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1134 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1135 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1136 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1137 /* 77 - 1920x1080@100Hz 64:27 */
8ec6e075
SS		 1138 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1139 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1140 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1141 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1142 /* 78 - 1920x1080@120Hz 64:27 */
8ec6e075
SS		 1143 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1144 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1145 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1146 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1147 /* 79 - 1680x720@24Hz 64:27 */
8ec6e075
SS		 1148 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1149 3080, 3300, 0, 720, 725, 730, 750, 0,
1150 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1151 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1152 /* 80 - 1680x720@25Hz 64:27 */
8ec6e075
SS		 1153 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1154 2948, 3168, 0, 720, 725, 730, 750, 0,
1155 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1156 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1157 /* 81 - 1680x720@30Hz 64:27 */
8ec6e075
SS		 1158 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1159 2420, 2640, 0, 720, 725, 730, 750, 0,
1160 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1161 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1162 /* 82 - 1680x720@50Hz 64:27 */
8ec6e075
SS		 1163 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1164 1980, 2200, 0, 720, 725, 730, 750, 0,
1165 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1166 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1167 /* 83 - 1680x720@60Hz 64:27 */
8ec6e075
SS		 1168 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1169 1980, 2200, 0, 720, 725, 730, 750, 0,
1170 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1171 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1172 /* 84 - 1680x720@100Hz 64:27 */
8ec6e075
SS		 1173 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1174 1780, 2000, 0, 720, 725, 730, 825, 0,
1175 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1176 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1177 /* 85 - 1680x720@120Hz 64:27 */
8ec6e075
SS		 1178 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1179 1780, 2000, 0, 720, 725, 730, 825, 0,
1180 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1181 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1182 /* 86 - 2560x1080@24Hz 64:27 */
8ec6e075
SS		 1183 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1184 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1185 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1186 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1187 /* 87 - 2560x1080@25Hz 64:27 */
8ec6e075
SS		 1188 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1189 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1190 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1191 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1192 /* 88 - 2560x1080@30Hz 64:27 */
8ec6e075
SS		 1193 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1194 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1195 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1196 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1197 /* 89 - 2560x1080@50Hz 64:27 */
8ec6e075
SS		 1198 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1199 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1200 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1201 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1202 /* 90 - 2560x1080@60Hz 64:27 */
8ec6e075
SS		 1203 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1204 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1205 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1206 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1207 /* 91 - 2560x1080@100Hz 64:27 */
8ec6e075
SS		 1208 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1209 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1210 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1211 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1212 /* 92 - 2560x1080@120Hz 64:27 */
8ec6e075
SS		 1213 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1214 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1215 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1216 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1217 /* 93 - 3840x2160@24Hz 16:9 */
8ec6e075
SS		 1218 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1219 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1220 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1221 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1222 /* 94 - 3840x2160@25Hz 16:9 */
8ec6e075
SS		 1223 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1224 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1225 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1226 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1227 /* 95 - 3840x2160@30Hz 16:9 */
8ec6e075
SS		 1228 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1229 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1230 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1231 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1232 /* 96 - 3840x2160@50Hz 16:9 */
8ec6e075
SS		 1233 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1234 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1235 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1236 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1237 /* 97 - 3840x2160@60Hz 16:9 */
8ec6e075
SS		 1238 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1239 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1240 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1241 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1242 /* 98 - 4096x2160@24Hz 256:135 */
8ec6e075
SS		 1243 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1244 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1245 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1246 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1247 /* 99 - 4096x2160@25Hz 256:135 */
8ec6e075
SS		 1248 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1249 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1250 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1251 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1252 /* 100 - 4096x2160@30Hz 256:135 */
8ec6e075
SS		 1253 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1254 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1255 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1256 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1257 /* 101 - 4096x2160@50Hz 256:135 */
8ec6e075
SS		 1258 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1259 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1260 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1261 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1262 /* 102 - 4096x2160@60Hz 256:135 */
8ec6e075
SS		 1263 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1264 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1265 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1266 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1267 /* 103 - 3840x2160@24Hz 64:27 */
8ec6e075
SS		 1268 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1269 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1270 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1271 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1272 /* 104 - 3840x2160@25Hz 64:27 */
8ec6e075
SS		 1273 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1274 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1275 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1276 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1277 /* 105 - 3840x2160@30Hz 64:27 */
8ec6e075
SS		 1278 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1279 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1281 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1282 /* 106 - 3840x2160@50Hz 64:27 */
8ec6e075
SS		 1283 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1284 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1285 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1286 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1287 /* 107 - 3840x2160@60Hz 64:27 */
8ec6e075
SS		 1288 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1289 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1290 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1291 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1292 /* 108 - 1280x720@48Hz 16:9 */
1293 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1294 2280, 2500, 0, 720, 725, 730, 750, 0,
1295 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1296 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1297 /* 109 - 1280x720@48Hz 64:27 */
1298 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1299 2280, 2500, 0, 720, 725, 730, 750, 0,
1300 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1301 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1302 /* 110 - 1680x720@48Hz 64:27 */
1303 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490,
1304 2530, 2750, 0, 720, 725, 730, 750, 0,
1305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1306 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1307 /* 111 - 1920x1080@48Hz 16:9 */
1308 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1309 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1310 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1311 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1312 /* 112 - 1920x1080@48Hz 64:27 */
1313 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1314 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1315 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1316 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1317 /* 113 - 2560x1080@48Hz 64:27 */
1318 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558,
1319 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1320 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1321 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1322 /* 114 - 3840x2160@48Hz 16:9 */
1323 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1324 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1325 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1326 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1327 /* 115 - 4096x2160@48Hz 256:135 */
1328 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116,
1329 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1330 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1331 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
978f6b06
VS		 1332 /* 116 - 3840x2160@48Hz 64:27 */
1333 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1334 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1335 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1336 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1337 /* 117 - 3840x2160@100Hz 16:9 */
1338 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1339 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1340 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1341 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1342 /* 118 - 3840x2160@120Hz 16:9 */
1343 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1344 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1345 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1346 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1347 /* 119 - 3840x2160@100Hz 64:27 */
1348 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1349 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1350 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1351 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1352 /* 120 - 3840x2160@120Hz 64:27 */
1353 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1354 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1355 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1356 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1357 /* 121 - 5120x2160@24Hz 64:27 */
1358 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116,
1359 7204, 7500, 0, 2160, 2168, 2178, 2200, 0,
1360 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1361 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1362 /* 122 - 5120x2160@25Hz 64:27 */
1363 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816,
1364 6904, 7200, 0, 2160, 2168, 2178, 2200, 0,
1365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1366 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1367 /* 123 - 5120x2160@30Hz 64:27 */
1368 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784,
1369 5872, 6000, 0, 2160, 2168, 2178, 2200, 0,
1370 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1371 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1372 /* 124 - 5120x2160@48Hz 64:27 */
1373 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866,
1374 5954, 6250, 0, 2160, 2168, 2178, 2475, 0,
1375 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1376 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1377 /* 125 - 5120x2160@50Hz 64:27 */
1378 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216,
1379 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1380 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1381 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1382 /* 126 - 5120x2160@60Hz 64:27 */
1383 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284,
1384 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1386 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1387 /* 127 - 5120x2160@100Hz 64:27 */
1388 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216,
1389 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1390 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1391 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
a6b21831
TR		 1392};
1393
f7655d42
VS		 1394/*
1395 * From CEA/CTA-861 spec.
1396 *
1397 * Do not access directly, instead always use cea_mode_for_vic().
1398 */
1399static const struct drm_display_mode edid_cea_modes_193[] = {
1400 /* 193 - 5120x2160@120Hz 64:27 */
1401 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284,
1402 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1403 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1404 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1405 /* 194 - 7680x4320@24Hz 16:9 */
1406 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1407 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1408 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1409 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1410 /* 195 - 7680x4320@25Hz 16:9 */
1411 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1412 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1413 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1414 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1415 /* 196 - 7680x4320@30Hz 16:9 */
1416 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1417 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1418 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1419 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1420 /* 197 - 7680x4320@48Hz 16:9 */
1421 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1422 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1423 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1424 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1425 /* 198 - 7680x4320@50Hz 16:9 */
1426 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1427 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1428 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1429 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1430 /* 199 - 7680x4320@60Hz 16:9 */
1431 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1432 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1433 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1434 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1435 /* 200 - 7680x4320@100Hz 16:9 */
1436 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1437 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1438 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1439 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1440 /* 201 - 7680x4320@120Hz 16:9 */
1441 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1442 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1443 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1444 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1445 /* 202 - 7680x4320@24Hz 64:27 */
1446 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1447 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1448 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1449 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1450 /* 203 - 7680x4320@25Hz 64:27 */
1451 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1452 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1454 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1455 /* 204 - 7680x4320@30Hz 64:27 */
1456 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1457 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1458 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1459 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1460 /* 205 - 7680x4320@48Hz 64:27 */
1461 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1462 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1463 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1464 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1465 /* 206 - 7680x4320@50Hz 64:27 */
1466 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1467 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1468 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1469 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1470 /* 207 - 7680x4320@60Hz 64:27 */
1471 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1472 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1473 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1474 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1475 /* 208 - 7680x4320@100Hz 64:27 */
1476 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1477 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1478 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1479 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1480 /* 209 - 7680x4320@120Hz 64:27 */
1481 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1482 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1483 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1484 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1485 /* 210 - 10240x4320@24Hz 64:27 */
1486 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732,
1487 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1488 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1489 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1490 /* 211 - 10240x4320@25Hz 64:27 */
1491 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732,
1492 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1493 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1494 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1495 /* 212 - 10240x4320@30Hz 64:27 */
1496 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528,
1497 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1498 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1499 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1500 /* 213 - 10240x4320@48Hz 64:27 */
1501 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732,
1502 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1503 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1504 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1505 /* 214 - 10240x4320@50Hz 64:27 */
1506 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732,
1507 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1508 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1509 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1510 /* 215 - 10240x4320@60Hz 64:27 */
1511 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528,
1512 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1513 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1514 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1515 /* 216 - 10240x4320@100Hz 64:27 */
1516 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432,
1517 12608, 13200, 0, 4320, 4336, 4356, 4500, 0,
1518 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1519 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1520 /* 217 - 10240x4320@120Hz 64:27 */
1521 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528,
1522 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1523 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1524 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1525 /* 218 - 4096x2160@100Hz 256:135 */
1526 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896,
1527 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1528 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1529 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
f7655d42
VS		 1530 /* 219 - 4096x2160@120Hz 256:135 */
1531 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184,
1532 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1533 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1534 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
f7655d42
VS		 1535};
1536
7ebe1963 1537/*
d9278b4c 1538 * HDMI 1.4 4k modes. Index using the VIC.
7ebe1963
LD		 1539 */
1540static const struct drm_display_mode edid_4k_modes[] = {
d9278b4c
JN		 1541 /* 0 - dummy, VICs start at 1 */
1542 { },
7ebe1963
LD		 1543 /* 1 - 3840x2160@30Hz */
1544 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1545 3840, 4016, 4104, 4400, 0,
1546 2160, 2168, 2178, 2250, 0,
1547 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1548 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
7ebe1963
LD		 1549 /* 2 - 3840x2160@25Hz */
1550 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1551 3840, 4896, 4984, 5280, 0,
1552 2160, 2168, 2178, 2250, 0,
1553 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1554 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
7ebe1963
LD		 1555 /* 3 - 3840x2160@24Hz */
1556 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1557 3840, 5116, 5204, 5500, 0,
1558 2160, 2168, 2178, 2250, 0,
1559 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1560 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
7ebe1963
LD		 1561 /* 4 - 4096x2160@24Hz (SMPTE) */
1562 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1563 4096, 5116, 5204, 5500, 0,
1564 2160, 2168, 2178, 2250, 0,
1565 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1566 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
7ebe1963
LD		 1567};
1568
61e57a8d 1569/*** DDC fetch and block validation ***/
f453ba04 1570
083ae056
AJ		 1571static const u8 edid_header[] = {
1572 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1573};
f453ba04 1574
db6cf833
TR		 1575/**
1576 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1577 * @raw_edid: pointer to raw base EDID block
1578 *
1579 * Sanity check the header of the base EDID block.
1580 *
1581 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
051963d4
TR		 1582 */
1583int drm_edid_header_is_valid(const u8 *raw_edid)
1584{
1585 int i, score = 0;
1586
1587 for (i = 0; i < sizeof(edid_header); i++)
1588 if (raw_edid[i] == edid_header[i])
1589 score++;
1590
1591 return score;
1592}
1593EXPORT_SYMBOL(drm_edid_header_is_valid);
1594
47819ba2
AJ		 1595static int edid_fixup __read_mostly = 6;
1596module_param_named(edid_fixup, edid_fixup, int, 0400);
1597MODULE_PARM_DESC(edid_fixup,
1598 "Minimum number of valid EDID header bytes (0-8, default 6)");
051963d4 1599
c465bbc8
SB		 1600static int drm_edid_block_checksum(const u8 *raw_edid)
1601{
1602 int i;
e11f5bd8
JFZ		 1603 u8 csum = 0, crc = 0;
1604
1605 for (i = 0; i < EDID_LENGTH - 1; i++)
c465bbc8
SB		 1606 csum += raw_edid[i];
1607
e11f5bd8
JFZ		 1608 crc = 0x100 - csum;
1609
1610 return crc;
1611}
1612
1613static bool drm_edid_block_checksum_diff(const u8 *raw_edid, u8 real_checksum)
1614{
1615 if (raw_edid[EDID_LENGTH - 1] != real_checksum)
1616 return true;
1617 else
1618 return false;
c465bbc8
SB		 1619}
1620
d6885d65
SB		 1621static bool drm_edid_is_zero(const u8 *in_edid, int length)
1622{
1623 if (memchr_inv(in_edid, 0, length))
1624 return false;
1625
1626 return true;
1627}
1628
536faa45
SL		 1629/**
1630 * drm_edid_are_equal - compare two edid blobs.
1631 * @edid1: pointer to first blob
1632 * @edid2: pointer to second blob
1633 * This helper can be used during probing to determine if
1634 * edid had changed.
1635 */
1636bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2)
1637{
1638 int edid1_len, edid2_len;
1639 bool edid1_present = edid1 != NULL;
1640 bool edid2_present = edid2 != NULL;
1641
1642 if (edid1_present != edid2_present)
1643 return false;
1644
1645 if (edid1) {
536faa45
SL		 1646 edid1_len = EDID_LENGTH * (1 + edid1->extensions);
1647 edid2_len = EDID_LENGTH * (1 + edid2->extensions);
1648
1649 if (edid1_len != edid2_len)
1650 return false;
1651
1652 if (memcmp(edid1, edid2, edid1_len))
1653 return false;
1654 }
1655
1656 return true;
1657}
1658EXPORT_SYMBOL(drm_edid_are_equal);
1659
db6cf833
TR		 1660/**
1661 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1662 * @raw_edid: pointer to raw EDID block
1663 * @block: type of block to validate (0 for base, extension otherwise)
1664 * @print_bad_edid: if true, dump bad EDID blocks to the console
6ba2bd3d 1665 * @edid_corrupt: if true, the header or checksum is invalid
db6cf833
TR		 1666 *
1667 * Validate a base or extension EDID block and optionally dump bad blocks to
1668 * the console.
1669 *
1670 * Return: True if the block is valid, false otherwise.
f453ba04 1671 */
6ba2bd3d
TP		 1672bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
1673 bool *edid_corrupt)
f453ba04 1674{
c465bbc8 1675 u8 csum;
61e57a8d 1676 struct edid *edid = (struct edid *)raw_edid;
f453ba04 1677
fe2ef780
SWK		 1678 if (WARN_ON(!raw_edid))
1679 return false;
1680
47819ba2
AJ		 1681 if (edid_fixup > 8 || edid_fixup < 0)
1682 edid_fixup = 6;
1683
f89ec8a4 1684 if (block == 0) {
051963d4 1685 int score = drm_edid_header_is_valid(raw_edid);
948de842 1686
6ba2bd3d
TP		 1687 if (score == 8) {
1688 if (edid_corrupt)
ac6f2e29 1689 *edid_corrupt = false;
6ba2bd3d
TP		 1690 } else if (score >= edid_fixup) {
1691 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
1692 * The corrupt flag needs to be set here otherwise, the
1693 * fix-up code here will correct the problem, the
1694 * checksum is correct and the test fails
1695 */
1696 if (edid_corrupt)
ac6f2e29 1697 *edid_corrupt = true;
61e57a8d
AJ		 1698 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1699 memcpy(raw_edid, edid_header, sizeof(edid_header));
1700 } else {
6ba2bd3d 1701 if (edid_corrupt)
ac6f2e29 1702 *edid_corrupt = true;
61e57a8d
AJ		 1703 goto bad;
1704 }
1705 }
f453ba04 1706
c465bbc8 1707 csum = drm_edid_block_checksum(raw_edid);
e11f5bd8 1708 if (drm_edid_block_checksum_diff(raw_edid, csum)) {
6ba2bd3d 1709 if (edid_corrupt)
ac6f2e29 1710 *edid_corrupt = true;
6ba2bd3d 1711
4a638b4e 1712 /* allow CEA to slide through, switches mangle this */
82d75356
TV		 1713 if (raw_edid[0] == CEA_EXT) {
1714 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum);
1715 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n");
1716 } else {
1717 if (print_bad_edid)
813a7878 1718 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum);
82d75356 1719
4a638b4e 1720 goto bad;
82d75356 1721 }
f453ba04
DA		 1722 }
1723
61e57a8d
AJ		 1724 /* per-block-type checks */
1725 switch (raw_edid[0]) {
1726 case 0: /* base */
1727 if (edid->version != 1) {
813a7878 1728 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version);
61e57a8d
AJ		 1729 goto bad;
1730 }
862b89c0 1731
61e57a8d
AJ		 1732 if (edid->revision > 4)
1733 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1734 break;
862b89c0 1735
61e57a8d
AJ		 1736 default:
1737 break;
1738 }
47ee4ccf 1739
fe2ef780 1740 return true;
f453ba04
DA		 1741
1742bad:
fe2ef780 1743 if (print_bad_edid) {
da4c07b7 1744 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
499447db 1745 pr_notice("EDID block is all zeroes\n");
da4c07b7 1746 } else {
499447db 1747 pr_notice("Raw EDID:\n");
813a7878
CW		 1748 print_hex_dump(KERN_NOTICE,
1749 " \t", DUMP_PREFIX_NONE, 16, 1,
1750 raw_edid, EDID_LENGTH, false);
da4c07b7 1751 }
f453ba04 1752 }
fe2ef780 1753 return false;
f453ba04 1754}
da0df92b 1755EXPORT_SYMBOL(drm_edid_block_valid);
61e57a8d
AJ		 1756
1757/**
1758 * drm_edid_is_valid - sanity check EDID data
1759 * @edid: EDID data
1760 *
1761 * Sanity-check an entire EDID record (including extensions)
db6cf833
TR		 1762 *
1763 * Return: True if the EDID data is valid, false otherwise.
61e57a8d
AJ		 1764 */
1765bool drm_edid_is_valid(struct edid *edid)
1766{
1767 int i;
1768 u8 *raw = (u8 *)edid;
1769
1770 if (!edid)
1771 return false;
1772
1773 for (i = 0; i <= edid->extensions; i++)
6ba2bd3d 1774 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
61e57a8d
AJ		 1775 return false;
1776
1777 return true;
1778}
3c537889 1779EXPORT_SYMBOL(drm_edid_is_valid);
f453ba04 1780
61e57a8d
AJ		 1781#define DDC_SEGMENT_ADDR 0x30
1782/**
db6cf833 1783 * drm_do_probe_ddc_edid() - get EDID information via I2C
7c58e87e 1784 * @data: I2C device adapter
fc66811c
DV		 1785 * @buf: EDID data buffer to be filled
1786 * @block: 128 byte EDID block to start fetching from
1787 * @len: EDID data buffer length to fetch
1788 *
db6cf833 1789 * Try to fetch EDID information by calling I2C driver functions.
61e57a8d 1790 *
db6cf833 1791 * Return: 0 on success or -1 on failure.
61e57a8d
AJ		 1792 */
1793static int
18df89fe 1794drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
61e57a8d 1795{
18df89fe 1796 struct i2c_adapter *adapter = data;
61e57a8d 1797 unsigned char start = block * EDID_LENGTH;
cd004b3f
S		 1798 unsigned char segment = block >> 1;
1799 unsigned char xfers = segment ? 3 : 2;
4819d2e4
CW		 1800 int ret, retries = 5;
1801
db6cf833
TR		 1802 /*
1803 * The core I2C driver will automatically retry the transfer if the
4819d2e4
CW		 1804 * adapter reports EAGAIN. However, we find that bit-banging transfers
1805 * are susceptible to errors under a heavily loaded machine and
1806 * generate spurious NAKs and timeouts. Retrying the transfer
1807 * of the individual block a few times seems to overcome this.
1808 */
1809 do {
1810 struct i2c_msg msgs[] = {
1811 {
cd004b3f
S		 1812 .addr = DDC_SEGMENT_ADDR,
1813 .flags = 0,
1814 .len = 1,
1815 .buf = &segment,
1816 }, {
4819d2e4
CW		 1817 .addr = DDC_ADDR,
1818 .flags = 0,
1819 .len = 1,
1820 .buf = &start,
1821 }, {
1822 .addr = DDC_ADDR,
1823 .flags = I2C_M_RD,
1824 .len = len,
1825 .buf = buf,
1826 }
1827 };
cd004b3f 1828
db6cf833
TR		 1829 /*
1830 * Avoid sending the segment addr to not upset non-compliant
1831 * DDC monitors.
1832 */
cd004b3f
S		 1833 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1834
9292f37e
ED		 1835 if (ret == -ENXIO) {
1836 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1837 adapter->name);
1838 break;
1839 }
cd004b3f 1840 } while (ret != xfers && --retries);
4819d2e4 1841
cd004b3f 1842 return ret == xfers ? 0 : -1;
61e57a8d
AJ		 1843}
1844
14544d09
CW		 1845static void connector_bad_edid(struct drm_connector *connector,
1846 u8 *edid, int num_blocks)
1847{
1848 int i;
97794170
DA		 1849 u8 last_block;
1850
1851 /*
1852 * 0x7e in the EDID is the number of extension blocks. The EDID
1853 * is 1 (base block) + num_ext_blocks big. That means we can think
1854 * of 0x7e in the EDID of the _index_ of the last block in the
1855 * combined chunk of memory.
1856 */
1857 last_block = edid[0x7e];
e11f5bd8
JFZ		 1858
1859 /* Calculate real checksum for the last edid extension block data */
97794170
DA		 1860 if (last_block < num_blocks)
1861 connector->real_edid_checksum =
1862 drm_edid_block_checksum(edid + last_block * EDID_LENGTH);
14544d09 1863
f0a8f533 1864 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
14544d09
CW		 1865 return;
1866
fa3bfa35 1867 drm_dbg_kms(connector->dev, "%s: EDID is invalid:\n", connector->name);
14544d09
CW		 1868 for (i = 0; i < num_blocks; i++) {
1869 u8 *block = edid + i * EDID_LENGTH;
1870 char prefix[20];
1871
1872 if (drm_edid_is_zero(block, EDID_LENGTH))
1873 sprintf(prefix, "\t[%02x] ZERO ", i);
1874 else if (!drm_edid_block_valid(block, i, false, NULL))
1875 sprintf(prefix, "\t[%02x] BAD ", i);
1876 else
1877 sprintf(prefix, "\t[%02x] GOOD ", i);
1878
fa3bfa35 1879 print_hex_dump(KERN_DEBUG,
14544d09
CW		 1880 prefix, DUMP_PREFIX_NONE, 16, 1,
1881 block, EDID_LENGTH, false);
1882 }
1883}
1884
56a2b7f2
JN		 1885/* Get override or firmware EDID */
1886static struct edid *drm_get_override_edid(struct drm_connector *connector)
1887{
1888 struct edid *override = NULL;
1889
1890 if (connector->override_edid)
1891 override = drm_edid_duplicate(connector->edid_blob_ptr->data);
1892
1893 if (!override)
1894 override = drm_load_edid_firmware(connector);
1895
1896 return IS_ERR(override) ? NULL : override;
1897}
1898
48eaeb76
JN		 1899/**
1900 * drm_add_override_edid_modes - add modes from override/firmware EDID
1901 * @connector: connector we're probing
1902 *
1903 * Add modes from the override/firmware EDID, if available. Only to be used from
1904 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
1905 * failed during drm_get_edid() and caused the override/firmware EDID to be
1906 * skipped.
1907 *
1908 * Return: The number of modes added or 0 if we couldn't find any.
1909 */
1910int drm_add_override_edid_modes(struct drm_connector *connector)
1911{
1912 struct edid *override;
1913 int num_modes = 0;
1914
1915 override = drm_get_override_edid(connector);
1916 if (override) {
1917 drm_connector_update_edid_property(connector, override);
1918 num_modes = drm_add_edid_modes(connector, override);
1919 kfree(override);
1920
1921 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
1922 connector->base.id, connector->name, num_modes);
1923 }
1924
1925 return num_modes;
1926}
1927EXPORT_SYMBOL(drm_add_override_edid_modes);
1928
e7bd95a7 1929static struct edid *drm_do_get_edid_base_block(struct drm_connector *connector,
bac9c294
DA		 1930 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
1931 size_t len),
e7bd95a7 1932 void *data)
bac9c294 1933{
e7bd95a7
DA		 1934 int *null_edid_counter = connector ? &connector->null_edid_counter : NULL;
1935 bool *edid_corrupt = connector ? &connector->edid_corrupt : NULL;
bac9c294 1936 void *edid;
e7bd95a7 1937 int i;
bac9c294
DA		 1938
1939 edid = kmalloc(EDID_LENGTH, GFP_KERNEL);
1940 if (edid == NULL)
1941 return NULL;
1942
1943 /* base block fetch */
1944 for (i = 0; i < 4; i++) {
1945 if (get_edid_block(data, edid, 0, EDID_LENGTH))
1946 goto out;
1947 if (drm_edid_block_valid(edid, 0, false, edid_corrupt))
1948 break;
1949 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) {
1950 if (null_edid_counter)
1951 (*null_edid_counter)++;
1952 goto carp;
1953 }
1954 }
1955 if (i == 4)
1956 goto carp;
1957
1958 return edid;
1959
1960carp:
e7bd95a7
DA		 1961 if (connector)
1962 connector_bad_edid(connector, edid, 1);
bac9c294
DA		 1963out:
1964 kfree(edid);
1965 return NULL;
1966}
1967
18df89fe
LPC		 1968/**
1969 * drm_do_get_edid - get EDID data using a custom EDID block read function
1970 * @connector: connector we're probing
1971 * @get_edid_block: EDID block read function
1972 * @data: private data passed to the block read function
1973 *
1974 * When the I2C adapter connected to the DDC bus is hidden behind a device that
1975 * exposes a different interface to read EDID blocks this function can be used
1976 * to get EDID data using a custom block read function.
1977 *
1978 * As in the general case the DDC bus is accessible by the kernel at the I2C
1979 * level, drivers must make all reasonable efforts to expose it as an I2C
1980 * adapter and use drm_get_edid() instead of abusing this function.
1981 *
0ae865ef 1982 * The EDID may be overridden using debugfs override_edid or firmware EDID
53fd40a9
JN		 1983 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
1984 * order. Having either of them bypasses actual EDID reads.
1985 *
18df89fe
LPC		 1986 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1987 */
1988struct edid *drm_do_get_edid(struct drm_connector *connector,
1989 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
1990 size_t len),
1991 void *data)
61e57a8d 1992{
0ea75e23 1993 int i, j = 0, valid_extensions = 0;
f14f3686 1994 u8 *edid, *new;
56a2b7f2 1995 struct edid *override;
53fd40a9 1996
56a2b7f2
JN		 1997 override = drm_get_override_edid(connector);
1998 if (override)
53fd40a9 1999 return override;
61e57a8d 2000
e7bd95a7
DA		 2001 edid = (u8 *)drm_do_get_edid_base_block(connector, get_edid_block, data);
2002 if (!edid)
61e57a8d 2003 return NULL;
61e57a8d 2004
bac9c294 2005 /* if there's no extensions or no connector, we're done */
14544d09
CW		 2006 valid_extensions = edid[0x7e];
2007 if (valid_extensions == 0)
f14f3686 2008 return (struct edid *)edid;
61e57a8d 2009
14544d09 2010 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
61e57a8d
AJ		 2011 if (!new)
2012 goto out;
f14f3686 2013 edid = new;
61e57a8d 2014
f14f3686 2015 for (j = 1; j <= edid[0x7e]; j++) {
14544d09 2016 u8 *block = edid + j * EDID_LENGTH;
a28187cc 2017
61e57a8d 2018 for (i = 0; i < 4; i++) {
a28187cc 2019 if (get_edid_block(data, block, j, EDID_LENGTH))
61e57a8d 2020 goto out;
14544d09 2021 if (drm_edid_block_valid(block, j, false, NULL))
61e57a8d
AJ		 2022 break;
2023 }
f934ec8c 2024
14544d09
CW		 2025 if (i == 4)
2026 valid_extensions--;
0ea75e23
ST		 2027 }
2028
f14f3686 2029 if (valid_extensions != edid[0x7e]) {
14544d09
CW		 2030 u8 *base;
2031
2032 connector_bad_edid(connector, edid, edid[0x7e] + 1);
2033
f14f3686
CW		 2034 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions;
2035 edid[0x7e] = valid_extensions;
14544d09 2036
6da2ec56
KC		 2037 new = kmalloc_array(valid_extensions + 1, EDID_LENGTH,
2038 GFP_KERNEL);
0ea75e23
ST		 2039 if (!new)
2040 goto out;
14544d09
CW		 2041
2042 base = new;
2043 for (i = 0; i <= edid[0x7e]; i++) {
2044 u8 *block = edid + i * EDID_LENGTH;
2045
2046 if (!drm_edid_block_valid(block, i, false, NULL))
2047 continue;
2048
2049 memcpy(base, block, EDID_LENGTH);
2050 base += EDID_LENGTH;
2051 }
2052
2053 kfree(edid);
f14f3686 2054 edid = new;
61e57a8d
AJ		 2055 }
2056
f14f3686 2057 return (struct edid *)edid;
61e57a8d 2058
61e57a8d 2059out:
f14f3686 2060 kfree(edid);
61e57a8d
AJ		 2061 return NULL;
2062}
18df89fe 2063EXPORT_SYMBOL_GPL(drm_do_get_edid);
61e57a8d
AJ		 2064
2065/**
db6cf833
TR		 2066 * drm_probe_ddc() - probe DDC presence
2067 * @adapter: I2C adapter to probe
fc66811c 2068 *
db6cf833 2069 * Return: True on success, false on failure.
61e57a8d 2070 */
fbff4690 2071bool
61e57a8d
AJ		 2072drm_probe_ddc(struct i2c_adapter *adapter)
2073{
2074 unsigned char out;
2075
2076 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
2077}
fbff4690 2078EXPORT_SYMBOL(drm_probe_ddc);
61e57a8d
AJ		 2079
2080/**
2081 * drm_get_edid - get EDID data, if available
2082 * @connector: connector we're probing
db6cf833 2083 * @adapter: I2C adapter to use for DDC
61e57a8d 2084 *
db6cf833 2085 * Poke the given I2C channel to grab EDID data if possible. If found,
61e57a8d
AJ		 2086 * attach it to the connector.
2087 *
db6cf833 2088 * Return: Pointer to valid EDID or NULL if we couldn't find any.
61e57a8d
AJ		 2089 */
2090struct edid *drm_get_edid(struct drm_connector *connector,
2091 struct i2c_adapter *adapter)
2092{
5186421c
SL		 2093 struct edid *edid;
2094
15f080f0
JN		 2095 if (connector->force == DRM_FORCE_OFF)
2096 return NULL;
2097
2098 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
18df89fe 2099 return NULL;
61e57a8d 2100
5186421c
SL		 2101 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
2102 drm_connector_update_edid_property(connector, edid);
2103 return edid;
61e57a8d
AJ		 2104}
2105EXPORT_SYMBOL(drm_get_edid);
2106
d9f91a10
DA		 2107static u32 edid_extract_panel_id(const struct edid *edid)
2108{
2109 /*
e8de4d55
DA		 2110 * We represent the ID as a 32-bit number so it can easily be compared
2111 * with "==".
d9f91a10
DA		 2112 *
2113 * NOTE that we deal with endianness differently for the top half
2114 * of this ID than for the bottom half. The bottom half (the product
2115 * id) gets decoded as little endian by the EDID_PRODUCT_ID because
2116 * that's how everyone seems to interpret it. The top half (the mfg_id)
2117 * gets stored as big endian because that makes
2118 * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier
2119 * to write (it's easier to extract the ASCII). It doesn't really
2120 * matter, though, as long as the number here is unique.
2121 */
2122 return (u32)edid->mfg_id[0] << 24 |
2123 (u32)edid->mfg_id[1] << 16 |
2124 (u32)EDID_PRODUCT_ID(edid);
2125}
2126
2127/**
2128 * drm_edid_get_panel_id - Get a panel's ID through DDC
2129 * @adapter: I2C adapter to use for DDC
2130 *
2131 * This function reads the first block of the EDID of a panel and (assuming
2132 * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value
2133 * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's
2134 * supposed to be different for each different modem of panel.
2135 *
2136 * This function is intended to be used during early probing on devices where
2137 * more than one panel might be present. Because of its intended use it must
2138 * assume that the EDID of the panel is correct, at least as far as the ID
2139 * is concerned (in other words, we don't process any overrides here).
2140 *
2141 * NOTE: it's expected that this function and drm_do_get_edid() will both
2142 * be read the EDID, but there is no caching between them. Since we're only
2143 * reading the first block, hopefully this extra overhead won't be too big.
2144 *
2145 * Return: A 32-bit ID that should be different for each make/model of panel.
2146 * See the functions drm_edid_encode_panel_id() and
2147 * drm_edid_decode_panel_id() for some details on the structure of this
2148 * ID.
2149 */
2150
2151u32 drm_edid_get_panel_id(struct i2c_adapter *adapter)
2152{
2153 struct edid *edid;
2154 u32 panel_id;
2155
e7bd95a7 2156 edid = drm_do_get_edid_base_block(NULL, drm_do_probe_ddc_edid, adapter);
d9f91a10
DA		 2157
2158 /*
2159 * There are no manufacturer IDs of 0, so if there is a problem reading
2160 * the EDID then we'll just return 0.
2161 */
e7bd95a7 2162 if (!edid)
d9f91a10
DA		 2163 return 0;
2164
2165 panel_id = edid_extract_panel_id(edid);
2166 kfree(edid);
2167
2168 return panel_id;
2169}
2170EXPORT_SYMBOL(drm_edid_get_panel_id);
2171
5cb8eaa2
LW		 2172/**
2173 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
2174 * @connector: connector we're probing
2175 * @adapter: I2C adapter to use for DDC
2176 *
2177 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
2178 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
2179 * switch DDC to the GPU which is retrieving EDID.
2180 *
2181 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2182 */
2183struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
2184 struct i2c_adapter *adapter)
2185{
36b73b05
TZ		 2186 struct drm_device *dev = connector->dev;
2187 struct pci_dev *pdev = to_pci_dev(dev->dev);
5cb8eaa2
LW		 2188 struct edid *edid;
2189
36b73b05
TZ		 2190 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev)))
2191 return NULL;
2192
5cb8eaa2
LW		 2193 vga_switcheroo_lock_ddc(pdev);
2194 edid = drm_get_edid(connector, adapter);
2195 vga_switcheroo_unlock_ddc(pdev);
2196
2197 return edid;
2198}
2199EXPORT_SYMBOL(drm_get_edid_switcheroo);
2200
51f8da59
JN		 2201/**
2202 * drm_edid_duplicate - duplicate an EDID and the extensions
2203 * @edid: EDID to duplicate
2204 *
db6cf833 2205 * Return: Pointer to duplicated EDID or NULL on allocation failure.
51f8da59
JN		 2206 */
2207struct edid *drm_edid_duplicate(const struct edid *edid)
2208{
2209 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
2210}
2211EXPORT_SYMBOL(drm_edid_duplicate);
2212
61e57a8d
AJ		 2213/*** EDID parsing ***/
2214
f453ba04
DA		 2215/**
2216 * edid_get_quirks - return quirk flags for a given EDID
2217 * @edid: EDID to process
2218 *
2219 * This tells subsequent routines what fixes they need to apply.
2220 */
170178fe 2221static u32 edid_get_quirks(const struct edid *edid)
f453ba04 2222{
e8de4d55 2223 u32 panel_id = edid_extract_panel_id(edid);
23c4cfbd 2224 const struct edid_quirk *quirk;
f453ba04
DA		 2225 int i;
2226
2227 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
2228 quirk = &edid_quirk_list[i];
e8de4d55 2229 if (quirk->panel_id == panel_id)
f453ba04
DA		 2230 return quirk->quirks;
2231 }
2232
2233 return 0;
2234}
2235
2236#define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
339d202c 2237#define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
f453ba04 2238
f453ba04
DA		 2239/**
2240 * edid_fixup_preferred - set preferred modes based on quirk list
2241 * @connector: has mode list to fix up
2242 * @quirks: quirks list
2243 *
2244 * Walk the mode list for @connector, clearing the preferred status
2245 * on existing modes and setting it anew for the right mode ala @quirks.
2246 */
2247static void edid_fixup_preferred(struct drm_connector *connector,
2248 u32 quirks)
2249{
2250 struct drm_display_mode *t, *cur_mode, *preferred_mode;
f890607b 2251 int target_refresh = 0;
339d202c 2252 int cur_vrefresh, preferred_vrefresh;
f453ba04
DA		 2253
2254 if (list_empty(&connector->probed_modes))
2255 return;
2256
2257 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
2258 target_refresh = 60;
2259 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
2260 target_refresh = 75;
2261
2262 preferred_mode = list_first_entry(&connector->probed_modes,
2263 struct drm_display_mode, head);
2264
2265 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
2266 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
2267
2268 if (cur_mode == preferred_mode)
2269 continue;
2270
2271 /* Largest mode is preferred */
2272 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
2273 preferred_mode = cur_mode;
2274
0425662f
VS		 2275 cur_vrefresh = drm_mode_vrefresh(cur_mode);
2276 preferred_vrefresh = drm_mode_vrefresh(preferred_mode);
f453ba04
DA		 2277 /* At a given size, try to get closest to target refresh */
2278 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
339d202c
AD		 2279 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
2280 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
f453ba04
DA		 2281 preferred_mode = cur_mode;
2282 }
2283 }
2284
2285 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
2286}
2287
f6e252ba
AJ		 2288static bool
2289mode_is_rb(const struct drm_display_mode *mode)
2290{
2291 return (mode->htotal - mode->hdisplay == 160) &&
2292 (mode->hsync_end - mode->hdisplay == 80) &&
2293 (mode->hsync_end - mode->hsync_start == 32) &&
2294 (mode->vsync_start - mode->vdisplay == 3);
2295}
2296
33c7531d
AJ		 2297/*
2298 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
2299 * @dev: Device to duplicate against
2300 * @hsize: Mode width
2301 * @vsize: Mode height
2302 * @fresh: Mode refresh rate
f6e252ba 2303 * @rb: Mode reduced-blanking-ness
33c7531d
AJ		 2304 *
2305 * Walk the DMT mode list looking for a match for the given parameters.
db6cf833
TR		 2306 *
2307 * Return: A newly allocated copy of the mode, or NULL if not found.
33c7531d 2308 */
1d42bbc8 2309struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
f6e252ba
AJ		 2310 int hsize, int vsize, int fresh,
2311 bool rb)
559ee21d 2312{
07a5e632 2313 int i;
559ee21d 2314
a6b21831 2315 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
b1f559ec 2316 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
948de842 2317
f8b46a05
AJ		 2318 if (hsize != ptr->hdisplay)
2319 continue;
2320 if (vsize != ptr->vdisplay)
2321 continue;
2322 if (fresh != drm_mode_vrefresh(ptr))
2323 continue;
f6e252ba
AJ		 2324 if (rb != mode_is_rb(ptr))
2325 continue;
f8b46a05
AJ		 2326
2327 return drm_mode_duplicate(dev, ptr);
559ee21d 2328 }
f8b46a05
AJ		 2329
2330 return NULL;
559ee21d 2331}
1d42bbc8 2332EXPORT_SYMBOL(drm_mode_find_dmt);
23425cae 2333
e379814b 2334static bool is_display_descriptor(const struct detailed_timing *descriptor, u8 type)
a7a131ac 2335{
e379814b
JN		 2336 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
2337 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.pad1) != 2);
2338 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.type) != 3);
2339
2340 return descriptor->pixel_clock == 0 &&
2341 descriptor->data.other_data.pad1 == 0 &&
2342 descriptor->data.other_data.type == type;
a7a131ac
VS		 2343}
2344
a9b1f15f 2345static bool is_detailed_timing_descriptor(const struct detailed_timing *descriptor)
f447dd1f 2346{
a9b1f15f
JN		 2347 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
2348
2349 return descriptor->pixel_clock != 0;
f447dd1f
VS		 2350}
2351
d1ff6409
AJ		 2352typedef void detailed_cb(struct detailed_timing *timing, void *closure);
2353
4d76a221
AJ		 2354static void
2355cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
2356{
7304b981 2357 int i, n;
4966b2a9 2358 u8 d = ext[0x02];
4d76a221
AJ		 2359 u8 *det_base = ext + d;
2360
7304b981
VS		 2361 if (d < 4 || d > 127)
2362 return;
2363
4966b2a9 2364 n = (127 - d) / 18;
4d76a221
AJ		 2365 for (i = 0; i < n; i++)
2366 cb((struct detailed_timing *)(det_base + 18 * i), closure);
2367}
2368
cbba98f8
AJ		 2369static void
2370vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
2371{
2372 unsigned int i, n = min((int)ext[0x02], 6);
2373 u8 *det_base = ext + 5;
2374
2375 if (ext[0x01] != 1)
2376 return; /* unknown version */
2377
2378 for (i = 0; i < n; i++)
2379 cb((struct detailed_timing *)(det_base + 18 * i), closure);
2380}
2381
d1ff6409
AJ		 2382static void
2383drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
2384{
2385 int i;
2386 struct edid *edid = (struct edid *)raw_edid;
2387
2388 if (edid == NULL)
2389 return;
2390
2391 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
2392 cb(&(edid->detailed_timings[i]), closure);
2393
4d76a221
AJ		 2394 for (i = 1; i <= raw_edid[0x7e]; i++) {
2395 u8 *ext = raw_edid + (i * EDID_LENGTH);
948de842 2396
4d76a221
AJ		 2397 switch (*ext) {
2398 case CEA_EXT:
2399 cea_for_each_detailed_block(ext, cb, closure);
2400 break;
cbba98f8
AJ		 2401 case VTB_EXT:
2402 vtb_for_each_detailed_block(ext, cb, closure);
2403 break;
4d76a221
AJ		 2404 default:
2405 break;
2406 }
2407 }
d1ff6409
AJ		 2408}
2409
2410static void
90fd588f 2411is_rb(struct detailed_timing *descriptor, void *data)
d1ff6409 2412{
90fd588f 2413 bool *res = data;
a7a131ac 2414
90fd588f 2415 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
a7a131ac
VS		 2416 return;
2417
90fd588f
JN		 2418 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
2419 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.cvt.flags) != 15);
2420
2421 if (descriptor->data.other_data.data.range.flags == DRM_EDID_CVT_SUPPORT_FLAG &&
2422 descriptor->data.other_data.data.range.formula.cvt.flags & 0x10)
2423 *res = true;
d1ff6409
AJ		 2424}
2425
2426/* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
2427static bool
2428drm_monitor_supports_rb(struct edid *edid)
2429{
2430 if (edid->revision >= 4) {
b196a498 2431 bool ret = false;
948de842 2432
d1ff6409
AJ		 2433 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
2434 return ret;
2435 }
2436
2437 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
2438}
2439
7a374350 2440static void
c8a4beba 2441find_gtf2(struct detailed_timing *descriptor, void *data)
7a374350 2442{
c8a4beba 2443 struct detailed_timing **res = data;
a7a131ac 2444
c8a4beba 2445 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
a7a131ac
VS		 2446 return;
2447
c8a4beba
JN		 2448 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
2449
2450 if (descriptor->data.other_data.data.range.flags == 0x02)
2451 *res = descriptor;
7a374350
AJ		 2452}
2453
2454/* Secondary GTF curve kicks in above some break frequency */
2455static int
2456drm_gtf2_hbreak(struct edid *edid)
2457{
c8a4beba
JN		 2458 struct detailed_timing *descriptor = NULL;
2459
2460 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &descriptor);
948de842 2461
c8a4beba
JN		 2462 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12);
2463
2464 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.hfreq_start_khz * 2 : 0;
7a374350
AJ		 2465}
2466
2467static int
2468drm_gtf2_2c(struct edid *edid)
2469{
c8a4beba
JN		 2470 struct detailed_timing *descriptor = NULL;
2471
2472 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &descriptor);
2473
2474 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.c) != 13);
948de842 2475
c8a4beba 2476 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.c : 0;
7a374350
AJ		 2477}
2478
2479static int
2480drm_gtf2_m(struct edid *edid)
2481{
c8a4beba 2482 struct detailed_timing *descriptor = NULL;
948de842 2483
c8a4beba
JN		 2484 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &descriptor);
2485
2486 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.m) != 14);
2487
2488 return descriptor ? le16_to_cpu(descriptor->data.other_data.data.range.formula.gtf2.m) : 0;
7a374350
AJ		 2489}
2490
2491static int
2492drm_gtf2_k(struct edid *edid)
2493{
c8a4beba
JN		 2494 struct detailed_timing *descriptor = NULL;
2495
2496 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &descriptor);
948de842 2497
c8a4beba
JN		 2498 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.k) != 16);
2499
2500 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.k : 0;
7a374350
AJ		 2501}
2502
2503static int
2504drm_gtf2_2j(struct edid *edid)
2505{
c8a4beba
JN		 2506 struct detailed_timing *descriptor = NULL;
2507
2508 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &descriptor);
2509
2510 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.j) != 17);
948de842 2511
c8a4beba 2512 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.j : 0;
7a374350
AJ		 2513}
2514
2515/**
2516 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
2517 * @edid: EDID block to scan
2518 */
2519static int standard_timing_level(struct edid *edid)
2520{
2521 if (edid->revision >= 2) {
2522 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
2523 return LEVEL_CVT;
2524 if (drm_gtf2_hbreak(edid))
2525 return LEVEL_GTF2;
bfef04ad
LS		 2526 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
2527 return LEVEL_GTF;
7a374350
AJ		 2528 }
2529 return LEVEL_DMT;
2530}
2531
23425cae
AJ		 2532/*
2533 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
2534 * monitors fill with ascii space (0x20) instead.
2535 */
2536static int
2537bad_std_timing(u8 a, u8 b)
2538{
2539 return (a == 0x00 && b == 0x00) ||
2540 (a == 0x01 && b == 0x01) ||
2541 (a == 0x20 && b == 0x20);
2542}
2543
58911c24
VS		 2544static int drm_mode_hsync(const struct drm_display_mode *mode)
2545{
2546 if (mode->htotal <= 0)
2547 return 0;
2548
2549 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal);
2550}
2551
f453ba04
DA		 2552/**
2553 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
fc66811c
DV		 2554 * @connector: connector of for the EDID block
2555 * @edid: EDID block to scan
f453ba04
DA		 2556 * @t: standard timing params
2557 *
2558 * Take the standard timing params (in this case width, aspect, and refresh)
5c61259e 2559 * and convert them into a real mode using CVT/GTF/DMT.
f453ba04 2560 */
7ca6adb3 2561static struct drm_display_mode *
7a374350 2562drm_mode_std(struct drm_connector *connector, struct edid *edid,
fcfb2ea1 2563 const struct std_timing *t)
f453ba04 2564{
7ca6adb3
AJ		 2565 struct drm_device *dev = connector->dev;
2566 struct drm_display_mode *m, *mode = NULL;
5c61259e
ZY		 2567 int hsize, vsize;
2568 int vrefresh_rate;
0454beab
MD		 2569 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
2570 >> EDID_TIMING_ASPECT_SHIFT;
5c61259e
ZY		 2571 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
2572 >> EDID_TIMING_VFREQ_SHIFT;
7a374350 2573 int timing_level = standard_timing_level(edid);
5c61259e 2574
23425cae
AJ		 2575 if (bad_std_timing(t->hsize, t->vfreq_aspect))
2576 return NULL;
2577
5c61259e
ZY		 2578 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
2579 hsize = t->hsize * 8 + 248;
2580 /* vrefresh_rate = vfreq + 60 */
2581 vrefresh_rate = vfreq + 60;
2582 /* the vdisplay is calculated based on the aspect ratio */
f066a17d 2583 if (aspect_ratio == 0) {
464fdeca 2584 if (edid->revision < 3)
f066a17d
AJ		 2585 vsize = hsize;
2586 else
2587 vsize = (hsize * 10) / 16;
2588 } else if (aspect_ratio == 1)
f453ba04 2589 vsize = (hsize * 3) / 4;
0454beab 2590 else if (aspect_ratio == 2)
f453ba04
DA		 2591 vsize = (hsize * 4) / 5;
2592 else
2593 vsize = (hsize * 9) / 16;
a0910c8e
AJ		 2594
2595 /* HDTV hack, part 1 */
2596 if (vrefresh_rate == 60 &&
2597 ((hsize == 1360 && vsize == 765) ||
2598 (hsize == 1368 && vsize == 769))) {
2599 hsize = 1366;
2600 vsize = 768;
2601 }
2602
7ca6adb3
AJ		 2603 /*
2604 * If this connector already has a mode for this size and refresh
2605 * rate (because it came from detailed or CVT info), use that
2606 * instead. This way we don't have to guess at interlace or
2607 * reduced blanking.
2608 */
522032da 2609 list_for_each_entry(m, &connector->probed_modes, head)
7ca6adb3
AJ		 2610 if (m->hdisplay == hsize && m->vdisplay == vsize &&
2611 drm_mode_vrefresh(m) == vrefresh_rate)
2612 return NULL;
2613
a0910c8e
AJ		 2614 /* HDTV hack, part 2 */
2615 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
2616 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
d50ba256 2617 false);
a5ef6567
JM		 2618 if (!mode)
2619 return NULL;
559ee21d 2620 mode->hdisplay = 1366;
a4967de6
AJ		 2621 mode->hsync_start = mode->hsync_start - 1;
2622 mode->hsync_end = mode->hsync_end - 1;
559ee21d
ZY		 2623 return mode;
2624 }
a0910c8e 2625
559ee21d 2626 /* check whether it can be found in default mode table */
f6e252ba
AJ		 2627 if (drm_monitor_supports_rb(edid)) {
2628 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
2629 true);
2630 if (mode)
2631 return mode;
2632 }
2633 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
559ee21d
ZY		 2634 if (mode)
2635 return mode;
2636
f6e252ba 2637 /* okay, generate it */
5c61259e
ZY		 2638 switch (timing_level) {
2639 case LEVEL_DMT:
5c61259e
ZY		 2640 break;
2641 case LEVEL_GTF:
2642 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2643 break;
7a374350
AJ		 2644 case LEVEL_GTF2:
2645 /*
2646 * This is potentially wrong if there's ever a monitor with
2647 * more than one ranges section, each claiming a different
2648 * secondary GTF curve. Please don't do that.
2649 */
2650 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
fc48f169
TI		 2651 if (!mode)
2652 return NULL;
7a374350 2653 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
aefd330e 2654 drm_mode_destroy(dev, mode);
7a374350
AJ		 2655 mode = drm_gtf_mode_complex(dev, hsize, vsize,
2656 vrefresh_rate, 0, 0,
2657 drm_gtf2_m(edid),
2658 drm_gtf2_2c(edid),
2659 drm_gtf2_k(edid),
2660 drm_gtf2_2j(edid));
2661 }
2662 break;
5c61259e 2663 case LEVEL_CVT:
d50ba256
DA		 2664 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
2665 false);
5c61259e
ZY		 2666 break;
2667 }
f453ba04
DA		 2668 return mode;
2669}
2670
b58db2c6
AJ		 2671/*
2672 * EDID is delightfully ambiguous about how interlaced modes are to be
2673 * encoded. Our internal representation is of frame height, but some
2674 * HDTV detailed timings are encoded as field height.
2675 *
2676 * The format list here is from CEA, in frame size. Technically we
2677 * should be checking refresh rate too. Whatever.
2678 */
2679static void
2680drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
fcfb2ea1 2681 const struct detailed_pixel_timing *pt)
b58db2c6
AJ		 2682{
2683 int i;
2684 static const struct {
2685 int w, h;
2686 } cea_interlaced[] = {
2687 { 1920, 1080 },
2688 { 720, 480 },
2689 { 1440, 480 },
2690 { 2880, 480 },
2691 { 720, 576 },
2692 { 1440, 576 },
2693 { 2880, 576 },
2694 };
b58db2c6
AJ		 2695
2696 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
2697 return;
2698
3c581411 2699 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
b58db2c6
AJ		 2700 if ((mode->hdisplay == cea_interlaced[i].w) &&
2701 (mode->vdisplay == cea_interlaced[i].h / 2)) {
2702 mode->vdisplay *= 2;
2703 mode->vsync_start *= 2;
2704 mode->vsync_end *= 2;
2705 mode->vtotal *= 2;
2706 mode->vtotal |= 1;
2707 }
2708 }
2709
2710 mode->flags |= DRM_MODE_FLAG_INTERLACE;
2711}
2712
f453ba04
DA		 2713/**
2714 * drm_mode_detailed - create a new mode from an EDID detailed timing section
2715 * @dev: DRM device (needed to create new mode)
2716 * @edid: EDID block
2717 * @timing: EDID detailed timing info
2718 * @quirks: quirks to apply
2719 *
2720 * An EDID detailed timing block contains enough info for us to create and
2721 * return a new struct drm_display_mode.
2722 */
2723static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
2724 struct edid *edid,
fcfb2ea1 2725 const struct detailed_timing *timing,
f453ba04
DA		 2726 u32 quirks)
2727{
2728 struct drm_display_mode *mode;
fcfb2ea1 2729 const struct detailed_pixel_timing *pt = &timing->data.pixel_data;
0454beab
MD		 2730 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
2731 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
2732 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
2733 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
e14cbee4
MD		 2734 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
2735 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
16dad1d7 2736 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
e14cbee4 2737 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
f453ba04 2738
fc438966 2739 /* ignore tiny modes */
0454beab 2740 if (hactive < 64 || vactive < 64)
fc438966
AJ		 2741 return NULL;
2742
0454beab 2743 if (pt->misc & DRM_EDID_PT_STEREO) {
c7d015f3 2744 DRM_DEBUG_KMS("stereo mode not supported\n");
f453ba04
DA		 2745 return NULL;
2746 }
0454beab 2747 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
c7d015f3 2748 DRM_DEBUG_KMS("composite sync not supported\n");
f453ba04
DA		 2749 }
2750
fcb45611
ZY		 2751 /* it is incorrect if hsync/vsync width is zero */
2752 if (!hsync_pulse_width || !vsync_pulse_width) {
2753 DRM_DEBUG_KMS("Incorrect Detailed timing. "
2754 "Wrong Hsync/Vsync pulse width\n");
2755 return NULL;
2756 }
bc42aabc
AJ		 2757
2758 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
2759 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
2760 if (!mode)
2761 return NULL;
2762
2763 goto set_size;
2764 }
2765
f453ba04
DA		 2766 mode = drm_mode_create(dev);
2767 if (!mode)
2768 return NULL;
2769
f453ba04 2770 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
faacff8e
JN		 2771 mode->clock = 1088 * 10;
2772 else
2773 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
0454beab
MD		 2774
2775 mode->hdisplay = hactive;
2776 mode->hsync_start = mode->hdisplay + hsync_offset;
2777 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
2778 mode->htotal = mode->hdisplay + hblank;
2779
2780 mode->vdisplay = vactive;
2781 mode->vsync_start = mode->vdisplay + vsync_offset;
2782 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
2783 mode->vtotal = mode->vdisplay + vblank;
f453ba04 2784
7064fef5
JB		 2785 /* Some EDIDs have bogus h/vtotal values */
2786 if (mode->hsync_end > mode->htotal)
2787 mode->htotal = mode->hsync_end + 1;
2788 if (mode->vsync_end > mode->vtotal)
2789 mode->vtotal = mode->vsync_end + 1;
2790
b58db2c6 2791 drm_mode_do_interlace_quirk(mode, pt);
f453ba04
DA		 2792
2793 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
faacff8e
JN		 2794 mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC;
2795 } else {
2796 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
2797 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
2798 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
2799 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
f453ba04
DA		 2800 }
2801
bc42aabc 2802set_size:
e14cbee4
MD		 2803 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
2804 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
f453ba04
DA		 2805
2806 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
2807 mode->width_mm *= 10;
2808 mode->height_mm *= 10;
2809 }
2810
2811 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
2812 mode->width_mm = edid->width_cm * 10;
2813 mode->height_mm = edid->height_cm * 10;
2814 }
2815
bc42aabc
AJ		 2816 mode->type = DRM_MODE_TYPE_DRIVER;
2817 drm_mode_set_name(mode);
2818
f453ba04
DA		 2819 return mode;
2820}
2821
b17e52ef 2822static bool
b1f559ec 2823mode_in_hsync_range(const struct drm_display_mode *mode,
fcfb2ea1 2824 struct edid *edid, const u8 *t)
b17e52ef
AJ		 2825{
2826 int hsync, hmin, hmax;
2827
2828 hmin = t[7];
2829 if (edid->revision >= 4)
2830 hmin += ((t[4] & 0x04) ? 255 : 0);
2831 hmax = t[8];
2832 if (edid->revision >= 4)
2833 hmax += ((t[4] & 0x08) ? 255 : 0);
07a5e632 2834 hsync = drm_mode_hsync(mode);
07a5e632 2835
b17e52ef
AJ		 2836 return (hsync <= hmax && hsync >= hmin);
2837}
2838
2839static bool
b1f559ec 2840mode_in_vsync_range(const struct drm_display_mode *mode,
fcfb2ea1 2841 struct edid *edid, const u8 *t)
b17e52ef
AJ		 2842{
2843 int vsync, vmin, vmax;
2844
2845 vmin = t[5];
2846 if (edid->revision >= 4)
2847 vmin += ((t[4] & 0x01) ? 255 : 0);
2848 vmax = t[6];
2849 if (edid->revision >= 4)
2850 vmax += ((t[4] & 0x02) ? 255 : 0);
2851 vsync = drm_mode_vrefresh(mode);
2852
2853 return (vsync <= vmax && vsync >= vmin);
2854}
2855
2856static u32
fcfb2ea1 2857range_pixel_clock(struct edid *edid, const u8 *t)
b17e52ef
AJ		 2858{
2859 /* unspecified */
2860 if (t[9] == 0 || t[9] == 255)
2861 return 0;
2862
2863 /* 1.4 with CVT support gives us real precision, yay */
2864 if (edid->revision >= 4 && t[10] == 0x04)
2865 return (t[9] * 10000) - ((t[12] >> 2) * 250);
2866
2867 /* 1.3 is pathetic, so fuzz up a bit */
2868 return t[9] * 10000 + 5001;
2869}
2870
b17e52ef 2871static bool
b1f559ec 2872mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
fcfb2ea1 2873 const struct detailed_timing *timing)
b17e52ef
AJ		 2874{
2875 u32 max_clock;
fcfb2ea1 2876 const u8 *t = (const u8 *)timing;
b17e52ef
AJ		 2877
2878 if (!mode_in_hsync_range(mode, edid, t))
07a5e632
AJ		 2879 return false;
2880
b17e52ef 2881 if (!mode_in_vsync_range(mode, edid, t))
07a5e632
AJ		 2882 return false;
2883
b17e52ef 2884 if ((max_clock = range_pixel_clock(edid, t)))
07a5e632
AJ		 2885 if (mode->clock > max_clock)
2886 return false;
b17e52ef
AJ		 2887
2888 /* 1.4 max horizontal check */
2889 if (edid->revision >= 4 && t[10] == 0x04)
2890 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
2891 return false;
2892
2893 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
2894 return false;
07a5e632
AJ		 2895
2896 return true;
2897}
2898
7b668ebe
TI		 2899static bool valid_inferred_mode(const struct drm_connector *connector,
2900 const struct drm_display_mode *mode)
2901{
85f8fcd6 2902 const struct drm_display_mode *m;
7b668ebe
TI		 2903 bool ok = false;
2904
2905 list_for_each_entry(m, &connector->probed_modes, head) {
2906 if (mode->hdisplay == m->hdisplay &&
2907 mode->vdisplay == m->vdisplay &&
2908 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
2909 return false; /* duplicated */
2910 if (mode->hdisplay <= m->hdisplay &&
2911 mode->vdisplay <= m->vdisplay)
2912 ok = true;
2913 }
2914 return ok;
2915}
2916
b17e52ef 2917static int
cd4cd3de 2918drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
fcfb2ea1 2919 const struct detailed_timing *timing)
07a5e632
AJ		 2920{
2921 int i, modes = 0;
2922 struct drm_display_mode *newmode;
2923 struct drm_device *dev = connector->dev;
2924
a6b21831 2925 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
7b668ebe
TI		 2926 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
2927 valid_inferred_mode(connector, drm_dmt_modes + i)) {
07a5e632
AJ		 2928 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
2929 if (newmode) {
2930 drm_mode_probed_add(connector, newmode);
2931 modes++;
2932 }
2933 }
2934 }
2935
2936 return modes;
2937}
2938
c09dedb7
TI		 2939/* fix up 1366x768 mode from 1368x768;
2940 * GFT/CVT can't express 1366 width which isn't dividable by 8
2941 */
969218fe 2942void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
c09dedb7
TI		 2943{
2944 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
2945 mode->hdisplay = 1366;
2946 mode->hsync_start--;
2947 mode->hsync_end--;
2948 drm_mode_set_name(mode);
2949 }
2950}
2951
b309bd37
AJ		 2952static int
2953drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
fcfb2ea1 2954 const struct detailed_timing *timing)
b309bd37
AJ		 2955{
2956 int i, modes = 0;
2957 struct drm_display_mode *newmode;
2958 struct drm_device *dev = connector->dev;
2959
a6b21831 2960 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
b309bd37 2961 const struct minimode *m = &extra_modes[i];
948de842 2962
b309bd37 2963 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
fc48f169
TI		 2964 if (!newmode)
2965 return modes;
b309bd37 2966
969218fe 2967 drm_mode_fixup_1366x768(newmode);
7b668ebe
TI		 2968 if (!mode_in_range(newmode, edid, timing) ||
2969 !valid_inferred_mode(connector, newmode)) {
b309bd37
AJ		 2970 drm_mode_destroy(dev, newmode);
2971 continue;
2972 }
2973
2974 drm_mode_probed_add(connector, newmode);
2975 modes++;
2976 }
2977
2978 return modes;
2979}
2980
2981static int
2982drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
fcfb2ea1 2983 const struct detailed_timing *timing)
b309bd37
AJ		 2984{
2985 int i, modes = 0;
2986 struct drm_display_mode *newmode;
2987 struct drm_device *dev = connector->dev;
2988 bool rb = drm_monitor_supports_rb(edid);
2989
a6b21831 2990 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
b309bd37 2991 const struct minimode *m = &extra_modes[i];
948de842 2992
b309bd37 2993 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
fc48f169
TI		 2994 if (!newmode)
2995 return modes;
b309bd37 2996
969218fe 2997 drm_mode_fixup_1366x768(newmode);
7b668ebe
TI		 2998 if (!mode_in_range(newmode, edid, timing) ||
2999 !valid_inferred_mode(connector, newmode)) {
b309bd37
AJ		 3000 drm_mode_destroy(dev, newmode);
3001 continue;
3002 }
3003
3004 drm_mode_probed_add(connector, newmode);
3005 modes++;
3006 }
3007
3008 return modes;
3009}
3010
13931579
AJ		 3011static void
3012do_inferred_modes(struct detailed_timing *timing, void *c)
9340d8cf 3013{
13931579 3014 struct detailed_mode_closure *closure = c;
fcfb2ea1
JN		 3015 const struct detailed_non_pixel *data = &timing->data.other_data;
3016 const struct detailed_data_monitor_range *range = &data->data.range;
9340d8cf 3017
e379814b 3018 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
cb21aafe
AJ		 3019 return;
3020
3021 closure->modes += drm_dmt_modes_for_range(closure->connector,
3022 closure->edid,
3023 timing);
4d23f484 3024
b309bd37
AJ		 3025 if (!version_greater(closure->edid, 1, 1))
3026 return; /* GTF not defined yet */
3027
3028 switch (range->flags) {
3029 case 0x02: /* secondary gtf, XXX could do more */
3030 case 0x00: /* default gtf */
3031 closure->modes += drm_gtf_modes_for_range(closure->connector,
3032 closure->edid,
3033 timing);
3034 break;
3035 case 0x04: /* cvt, only in 1.4+ */
3036 if (!version_greater(closure->edid, 1, 3))
3037 break;
3038
3039 closure->modes += drm_cvt_modes_for_range(closure->connector,
3040 closure->edid,
3041 timing);
3042 break;
3043 case 0x01: /* just the ranges, no formula */
3044 default:
3045 break;
3046 }
13931579 3047}
69da3015 3048
13931579
AJ		 3049static int
3050add_inferred_modes(struct drm_connector *connector, struct edid *edid)
3051{
3052 struct detailed_mode_closure closure = {
d456ea2e
JL		 3053 .connector = connector,
3054 .edid = edid,
13931579 3055 };
9340d8cf 3056
13931579
AJ		 3057 if (version_greater(edid, 1, 0))
3058 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
3059 &closure);
9340d8cf 3060
13931579 3061 return closure.modes;
9340d8cf
AJ		 3062}
3063
2255be14 3064static int
fcfb2ea1 3065drm_est3_modes(struct drm_connector *connector, const struct detailed_timing *timing)
2255be14
AJ		 3066{
3067 int i, j, m, modes = 0;
3068 struct drm_display_mode *mode;
fcfb2ea1 3069 const u8 *est = ((const u8 *)timing) + 6;
2255be14
AJ		 3070
3071 for (i = 0; i < 6; i++) {
891a7469 3072 for (j = 7; j >= 0; j--) {
2255be14 3073 m = (i * 8) + (7 - j);
3c581411 3074 if (m >= ARRAY_SIZE(est3_modes))
2255be14
AJ		 3075 break;
3076 if (est[i] & (1 << j)) {
1d42bbc8
DA		 3077 mode = drm_mode_find_dmt(connector->dev,
3078 est3_modes[m].w,
3079 est3_modes[m].h,
f6e252ba
AJ		 3080 est3_modes[m].r,
3081 est3_modes[m].rb);
2255be14
AJ		 3082 if (mode) {
3083 drm_mode_probed_add(connector, mode);
3084 modes++;
3085 }
3086 }
3087 }
3088 }
3089
3090 return modes;
3091}
3092
13931579
AJ		 3093static void
3094do_established_modes(struct detailed_timing *timing, void *c)
9cf00977 3095{
13931579 3096 struct detailed_mode_closure *closure = c;
9cf00977 3097
e379814b 3098 if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS))
a7a131ac
VS		 3099 return;
3100
3101 closure->modes += drm_est3_modes(closure->connector, timing);
13931579 3102}
9cf00977 3103
13931579
AJ		 3104/**
3105 * add_established_modes - get est. modes from EDID and add them
db6cf833 3106 * @connector: connector to add mode(s) to
13931579
AJ		 3107 * @edid: EDID block to scan
3108 *
3109 * Each EDID block contains a bitmap of the supported "established modes" list
3110 * (defined above). Tease them out and add them to the global modes list.
3111 */
3112static int
3113add_established_modes(struct drm_connector *connector, struct edid *edid)
3114{
3115 struct drm_device *dev = connector->dev;
3116 unsigned long est_bits = edid->established_timings.t1 |
3117 (edid->established_timings.t2 << 8) |
3118 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
3119 int i, modes = 0;
3120 struct detailed_mode_closure closure = {
d456ea2e
JL		 3121 .connector = connector,
3122 .edid = edid,
13931579 3123 };
9cf00977 3124
13931579
AJ		 3125 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
3126 if (est_bits & (1<<i)) {
3127 struct drm_display_mode *newmode;
948de842 3128
13931579
AJ		 3129 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
3130 if (newmode) {
3131 drm_mode_probed_add(connector, newmode);
3132 modes++;
3133 }
3134 }
9cf00977
AJ		 3135 }
3136
13931579
AJ		 3137 if (version_greater(edid, 1, 0))
3138 drm_for_each_detailed_block((u8 *)edid,
3139 do_established_modes, &closure);
3140
3141 return modes + closure.modes;
3142}
3143
3144static void
3145do_standard_modes(struct detailed_timing *timing, void *c)
3146{
3147 struct detailed_mode_closure *closure = c;
fcfb2ea1 3148 const struct detailed_non_pixel *data = &timing->data.other_data;
13931579
AJ		 3149 struct drm_connector *connector = closure->connector;
3150 struct edid *edid = closure->edid;
a7a131ac 3151 int i;
13931579 3152
e379814b 3153 if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES))
a7a131ac 3154 return;
9cf00977 3155
a7a131ac 3156 for (i = 0; i < 6; i++) {
fcfb2ea1 3157 const struct std_timing *std = &data->data.timings[i];
a7a131ac
VS		 3158 struct drm_display_mode *newmode;
3159
3160 newmode = drm_mode_std(connector, edid, std);
3161 if (newmode) {
3162 drm_mode_probed_add(connector, newmode);
3163 closure->modes++;
9cf00977 3164 }
9cf00977 3165 }
9cf00977
AJ		 3166}
3167
f453ba04 3168/**
13931579 3169 * add_standard_modes - get std. modes from EDID and add them
db6cf833 3170 * @connector: connector to add mode(s) to
f453ba04 3171 * @edid: EDID block to scan
f453ba04 3172 *
13931579
AJ		 3173 * Standard modes can be calculated using the appropriate standard (DMT,
3174 * GTF or CVT. Grab them from @edid and add them to the list.
f453ba04 3175 */
13931579
AJ		 3176static int
3177add_standard_modes(struct drm_connector *connector, struct edid *edid)
f453ba04 3178{
9cf00977 3179 int i, modes = 0;
13931579 3180 struct detailed_mode_closure closure = {
d456ea2e
JL		 3181 .connector = connector,
3182 .edid = edid,
13931579
AJ		 3183 };
3184
3185 for (i = 0; i < EDID_STD_TIMINGS; i++) {
3186 struct drm_display_mode *newmode;
3187
3188 newmode = drm_mode_std(connector, edid,
464fdeca 3189 &edid->standard_timings[i]);
13931579
AJ		 3190 if (newmode) {
3191 drm_mode_probed_add(connector, newmode);
3192 modes++;
3193 }
3194 }
3195
3196 if (version_greater(edid, 1, 0))
3197 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
3198 &closure);
3199
3200 /* XXX should also look for standard codes in VTB blocks */
3201
3202 return modes + closure.modes;
3203}
f453ba04 3204
13931579 3205static int drm_cvt_modes(struct drm_connector *connector,
fcfb2ea1 3206 const struct detailed_timing *timing)
13931579
AJ		 3207{
3208 int i, j, modes = 0;
3209 struct drm_display_mode *newmode;
3210 struct drm_device *dev = connector->dev;
fcfb2ea1 3211 const struct cvt_timing *cvt;
13931579
AJ		 3212 const int rates[] = { 60, 85, 75, 60, 50 };
3213 const u8 empty[3] = { 0, 0, 0 };
a327f6b8 3214
13931579 3215 for (i = 0; i < 4; i++) {
3f649ab7 3216 int width, height;
948de842 3217
13931579 3218 cvt = &(timing->data.other_data.data.cvt[i]);
f453ba04 3219
13931579 3220 if (!memcmp(cvt->code, empty, 3))
9cf00977 3221 continue;
f453ba04 3222
13931579
AJ		 3223 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
3224 switch (cvt->code[1] & 0x0c) {
d652d5f1
LT		 3225 /* default - because compiler doesn't see that we've enumerated all cases */
3226 default:
13931579
AJ		 3227 case 0x00:
3228 width = height * 4 / 3;
3229 break;
3230 case 0x04:
3231 width = height * 16 / 9;
3232 break;
3233 case 0x08:
3234 width = height * 16 / 10;
3235 break;
3236 case 0x0c:
3237 width = height * 15 / 9;
3238 break;
3239 }
3240
3241 for (j = 1; j < 5; j++) {
3242 if (cvt->code[2] & (1 << j)) {
3243 newmode = drm_cvt_mode(dev, width, height,
3244 rates[j], j == 0,
3245 false, false);
3246 if (newmode) {
3247 drm_mode_probed_add(connector, newmode);
3248 modes++;
3249 }
3250 }
3251 }
f453ba04
DA		 3252 }
3253
3254 return modes;
3255}
9cf00977 3256
13931579
AJ		 3257static void
3258do_cvt_mode(struct detailed_timing *timing, void *c)
882f0219 3259{
13931579 3260 struct detailed_mode_closure *closure = c;
882f0219 3261
e379814b 3262 if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE))
a7a131ac
VS		 3263 return;
3264
3265 closure->modes += drm_cvt_modes(closure->connector, timing);
13931579 3266}
882f0219 3267
13931579
AJ		 3268static int
3269add_cvt_modes(struct drm_connector *connector, struct edid *edid)
4d23f484 3270{
13931579 3271 struct detailed_mode_closure closure = {
d456ea2e
JL		 3272 .connector = connector,
3273 .edid = edid,
13931579 3274 };
882f0219 3275
13931579
AJ		 3276 if (version_greater(edid, 1, 2))
3277 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
882f0219 3278
13931579 3279 /* XXX should also look for CVT codes in VTB blocks */
882f0219 3280
13931579
AJ		 3281 return closure.modes;
3282}
3283
fa3a7340
VS		 3284static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
3285
13931579
AJ		 3286static void
3287do_detailed_mode(struct detailed_timing *timing, void *c)
3288{
3289 struct detailed_mode_closure *closure = c;
3290 struct drm_display_mode *newmode;
3291
a9b1f15f 3292 if (!is_detailed_timing_descriptor(timing))
f447dd1f
VS		 3293 return;
3294
3295 newmode = drm_mode_detailed(closure->connector->dev,
3296 closure->edid, timing,
3297 closure->quirks);
3298 if (!newmode)
3299 return;
13931579 3300
f447dd1f
VS		 3301 if (closure->preferred)
3302 newmode->type |= DRM_MODE_TYPE_PREFERRED;
13931579 3303
f447dd1f
VS		 3304 /*
3305 * Detailed modes are limited to 10kHz pixel clock resolution,
3306 * so fix up anything that looks like CEA/HDMI mode, but the clock
3307 * is just slightly off.
3308 */
3309 fixup_detailed_cea_mode_clock(newmode);
fa3a7340 3310
f447dd1f
VS		 3311 drm_mode_probed_add(closure->connector, newmode);
3312 closure->modes++;
3313 closure->preferred = false;
13931579 3314}
882f0219 3315
13931579
AJ		 3316/*
3317 * add_detailed_modes - Add modes from detailed timings
3318 * @connector: attached connector
3319 * @edid: EDID block to scan
3320 * @quirks: quirks to apply
3321 */
3322static int
3323add_detailed_modes(struct drm_connector *connector, struct edid *edid,
3324 u32 quirks)
3325{
3326 struct detailed_mode_closure closure = {
d456ea2e
JL		 3327 .connector = connector,
3328 .edid = edid,
c2925bde 3329 .preferred = true,
d456ea2e 3330 .quirks = quirks,
13931579
AJ		 3331 };
3332
3333 if (closure.preferred && !version_greater(edid, 1, 3))
3334 closure.preferred =
3335 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
3336
3337 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
3338
3339 return closure.modes;
882f0219 3340}
f453ba04 3341
8fe9790d 3342#define AUDIO_BLOCK 0x01
54ac76f8 3343#define VIDEO_BLOCK 0x02
f23c20c8 3344#define VENDOR_BLOCK 0x03
76adaa34 3345#define SPEAKER_BLOCK 0x04
e85959d6 3346#define HDR_STATIC_METADATA_BLOCK 0x6
87563fc0
SS		 3347#define USE_EXTENDED_TAG 0x07
3348#define EXT_VIDEO_CAPABILITY_BLOCK 0x00
832d4f2f
SS		 3349#define EXT_VIDEO_DATA_BLOCK_420 0x0E
3350#define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F
8fe9790d 3351#define EDID_BASIC_AUDIO (1 << 6)
a988bc72
LPC		 3352#define EDID_CEA_YCRCB444 (1 << 5)
3353#define EDID_CEA_YCRCB422 (1 << 4)
b1edd6a6 3354#define EDID_CEA_VCDB_QS (1 << 6)
8fe9790d 3355
d4e4a31d 3356/*
8fe9790d 3357 * Search EDID for CEA extension block.
f23c20c8 3358 */
4cc4f09e
JN		 3359const u8 *drm_find_edid_extension(const struct edid *edid,
3360 int ext_id, int *ext_index)
f23c20c8 3361{
43d16d84 3362 const u8 *edid_ext = NULL;
8fe9790d 3363 int i;
f23c20c8
ML		 3364
3365 /* No EDID or EDID extensions */
3366 if (edid == NULL || edid->extensions == 0)
8fe9790d 3367 return NULL;
f23c20c8 3368
f23c20c8 3369 /* Find CEA extension */
8873cfa3 3370 for (i = *ext_index; i < edid->extensions; i++) {
43d16d84 3371 edid_ext = (const u8 *)edid + EDID_LENGTH * (i + 1);
40d9b043 3372 if (edid_ext[0] == ext_id)
f23c20c8
ML		 3373 break;
3374 }
3375
8873cfa3 3376 if (i >= edid->extensions)
8fe9790d
ZW		 3377 return NULL;
3378
8873cfa3
VS		 3379 *ext_index = i + 1;
3380
8fe9790d
ZW		 3381 return edid_ext;
3382}
3383
43d16d84 3384static const u8 *drm_find_cea_extension(const struct edid *edid)
e28ad544 3385{
43d16d84 3386 const struct displayid_block *block;
1ba63caf 3387 struct displayid_iter iter;
43d16d84 3388 const u8 *cea;
1ba63caf 3389 int ext_index = 0;
e28ad544
AR		 3390
3391 /* Look for a top level CEA extension block */
7f261afd 3392 /* FIXME: make callers iterate through multiple CEA ext blocks? */
8873cfa3 3393 cea = drm_find_edid_extension(edid, CEA_EXT, &ext_index);
e28ad544
AR		 3394 if (cea)
3395 return cea;
3396
3397 /* CEA blocks can also be found embedded in a DisplayID block */
1ba63caf
JN		 3398 displayid_iter_edid_begin(edid, &iter);
3399 displayid_iter_for_each(block, &iter) {
3400 if (block->tag == DATA_BLOCK_CTA) {
3401 cea = (const u8 *)block;
3402 break;
e28ad544
AR		 3403 }
3404 }
1ba63caf 3405 displayid_iter_end(&iter);
e28ad544 3406
1ba63caf 3407 return cea;
e28ad544
AR		 3408}
3409
e1cf35b9 3410static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic)
7befe621 3411{
9212f8ee
VS		 3412 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127);
3413 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219);
3414
8c1b2bd9
VS		 3415 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1))
3416 return &edid_cea_modes_1[vic - 1];
f7655d42
VS		 3417 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193))
3418 return &edid_cea_modes_193[vic - 193];
7befe621
VS		 3419 return NULL;
3420}
3421
3422static u8 cea_num_vics(void)
3423{
f7655d42 3424 return 193 + ARRAY_SIZE(edid_cea_modes_193);
7befe621
VS		 3425}
3426
3427static u8 cea_next_vic(u8 vic)
3428{
8c1b2bd9 3429 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1))
f7655d42
VS		 3430 vic = 193;
3431 return vic;
7befe621
VS		 3432}
3433
e6e79209
VS		 3434/*
3435 * Calculate the alternate clock for the CEA mode
3436 * (60Hz vs. 59.94Hz etc.)
3437 */
3438static unsigned int
3439cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
3440{
3441 unsigned int clock = cea_mode->clock;
3442
0425662f 3443 if (drm_mode_vrefresh(cea_mode) % 6 != 0)
e6e79209
VS		 3444 return clock;
3445
3446 /*
3447 * edid_cea_modes contains the 59.94Hz
3448 * variant for 240 and 480 line modes,
3449 * and the 60Hz variant otherwise.
3450 */
3451 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
9afd808c 3452 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
e6e79209 3453 else
9afd808c 3454 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
e6e79209
VS		 3455
3456 return clock;
3457}
3458
c45a4e46
VS		 3459static bool
3460cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
3461{
3462 /*
3463 * For certain VICs the spec allows the vertical
3464 * front porch to vary by one or two lines.
3465 *
3466 * cea_modes[] stores the variant with the shortest
3467 * vertical front porch. We can adjust the mode to
3468 * get the other variants by simply increasing the
3469 * vertical front porch length.
3470 */
7befe621
VS		 3471 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 ||
3472 cea_mode_for_vic(9)->vtotal != 262 ||
3473 cea_mode_for_vic(12)->vtotal != 262 ||
3474 cea_mode_for_vic(13)->vtotal != 262 ||
3475 cea_mode_for_vic(23)->vtotal != 312 ||
3476 cea_mode_for_vic(24)->vtotal != 312 ||
3477 cea_mode_for_vic(27)->vtotal != 312 ||
3478 cea_mode_for_vic(28)->vtotal != 312);
c45a4e46
VS		 3479
3480 if (((vic == 8 || vic == 9 ||
3481 vic == 12 || vic == 13) && mode->vtotal < 263) ||
3482 ((vic == 23 || vic == 24 ||
3483 vic == 27 || vic == 28) && mode->vtotal < 314)) {
3484 mode->vsync_start++;
3485 mode->vsync_end++;
3486 mode->vtotal++;
3487
3488 return true;
3489 }
3490
3491 return false;
3492}
3493
4c6bcf44
VS		 3494static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
3495 unsigned int clock_tolerance)
3496{
357768cc 3497 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 3498 u8 vic;
4c6bcf44
VS		 3499
3500 if (!to_match->clock)
3501 return 0;
3502
357768cc
VS		 3503 if (to_match->picture_aspect_ratio)
3504 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3505
7befe621
VS		 3506 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
3507 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic);
4c6bcf44
VS		 3508 unsigned int clock1, clock2;
3509
3510 /* Check both 60Hz and 59.94Hz */
c45a4e46
VS		 3511 clock1 = cea_mode.clock;
3512 clock2 = cea_mode_alternate_clock(&cea_mode);
4c6bcf44
VS		 3513
3514 if (abs(to_match->clock - clock1) > clock_tolerance &&
3515 abs(to_match->clock - clock2) > clock_tolerance)
3516 continue;
3517
c45a4e46 3518 do {
357768cc 3519 if (drm_mode_match(to_match, &cea_mode, match_flags))
c45a4e46
VS		 3520 return vic;
3521 } while (cea_mode_alternate_timings(vic, &cea_mode));
4c6bcf44
VS		 3522 }
3523
3524 return 0;
3525}
3526
18316c8c
TR		 3527/**
3528 * drm_match_cea_mode - look for a CEA mode matching given mode
3529 * @to_match: display mode
3530 *
db6cf833 3531 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
18316c8c 3532 * mode.
a4799037 3533 */
18316c8c 3534u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
a4799037 3535{
357768cc 3536 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 3537 u8 vic;
a4799037 3538
a90b590e
VS		 3539 if (!to_match->clock)
3540 return 0;
3541
357768cc
VS		 3542 if (to_match->picture_aspect_ratio)
3543 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3544
7befe621
VS		 3545 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
3546 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic);
a90b590e
VS		 3547 unsigned int clock1, clock2;
3548
a90b590e 3549 /* Check both 60Hz and 59.94Hz */
c45a4e46
VS		 3550 clock1 = cea_mode.clock;
3551 clock2 = cea_mode_alternate_clock(&cea_mode);
a4799037 3552
c45a4e46
VS		 3553 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
3554 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
3555 continue;
3556
3557 do {
357768cc 3558 if (drm_mode_match(to_match, &cea_mode, match_flags))
c45a4e46
VS		 3559 return vic;
3560 } while (cea_mode_alternate_timings(vic, &cea_mode));
a4799037 3561 }
c45a4e46 3562
a4799037
SM		 3563 return 0;
3564}
3565EXPORT_SYMBOL(drm_match_cea_mode);
3566
d9278b4c
JN		 3567static bool drm_valid_cea_vic(u8 vic)
3568{
7befe621 3569 return cea_mode_for_vic(vic) != NULL;
d9278b4c
JN		 3570}
3571
28c03a44 3572static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
0967e6a5 3573{
7befe621
VS		 3574 const struct drm_display_mode *mode = cea_mode_for_vic(video_code);
3575
3576 if (mode)
3577 return mode->picture_aspect_ratio;
3578
3579 return HDMI_PICTURE_ASPECT_NONE;
0967e6a5 3580}
0967e6a5 3581
d2b43473
WL		 3582static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code)
3583{
3584 return edid_4k_modes[video_code].picture_aspect_ratio;
3585}
3586
3f2f6533
LD		 3587/*
3588 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
3589 * specific block).
3f2f6533
LD		 3590 */
3591static unsigned int
3592hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
3593{
3f2f6533
LD		 3594 return cea_mode_alternate_clock(hdmi_mode);
3595}
3596
4c6bcf44
VS		 3597static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
3598 unsigned int clock_tolerance)
3599{
357768cc 3600 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 3601 u8 vic;
4c6bcf44
VS		 3602
3603 if (!to_match->clock)
3604 return 0;
3605
d2b43473
WL		 3606 if (to_match->picture_aspect_ratio)
3607 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3608
d9278b4c
JN		 3609 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3610 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4c6bcf44
VS		 3611 unsigned int clock1, clock2;
3612
3613 /* Make sure to also match alternate clocks */
3614 clock1 = hdmi_mode->clock;
3615 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3616
3617 if (abs(to_match->clock - clock1) > clock_tolerance &&
3618 abs(to_match->clock - clock2) > clock_tolerance)
3619 continue;
3620
357768cc 3621 if (drm_mode_match(to_match, hdmi_mode, match_flags))
d9278b4c 3622 return vic;
4c6bcf44
VS		 3623 }
3624
3625 return 0;
3626}
3627
3f2f6533
LD		 3628/*
3629 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
3630 * @to_match: display mode
3631 *
3632 * An HDMI mode is one defined in the HDMI vendor specific block.
3633 *
3634 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
3635 */
3636static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
3637{
357768cc 3638 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 3639 u8 vic;
3f2f6533
LD		 3640
3641 if (!to_match->clock)
3642 return 0;
3643
d2b43473
WL		 3644 if (to_match->picture_aspect_ratio)
3645 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3646
d9278b4c
JN		 3647 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3648 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3f2f6533
LD		 3649 unsigned int clock1, clock2;
3650
3651 /* Make sure to also match alternate clocks */
3652 clock1 = hdmi_mode->clock;
3653 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3654
3655 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
3656 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
357768cc 3657 drm_mode_match(to_match, hdmi_mode, match_flags))
d9278b4c 3658 return vic;
3f2f6533
LD		 3659 }
3660 return 0;
3661}
3662
d9278b4c
JN		 3663static bool drm_valid_hdmi_vic(u8 vic)
3664{
3665 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
3666}
3667
e6e79209
VS		 3668static int
3669add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
3670{
3671 struct drm_device *dev = connector->dev;
3672 struct drm_display_mode *mode, *tmp;
3673 LIST_HEAD(list);
3674 int modes = 0;
3675
3676 /* Don't add CEA modes if the CEA extension block is missing */
3677 if (!drm_find_cea_extension(edid))
3678 return 0;
3679
3680 /*
3681 * Go through all probed modes and create a new mode
3682 * with the alternate clock for certain CEA modes.
3683 */
3684 list_for_each_entry(mode, &connector->probed_modes, head) {
3f2f6533 3685 const struct drm_display_mode *cea_mode = NULL;
e6e79209 3686 struct drm_display_mode *newmode;
d9278b4c 3687 u8 vic = drm_match_cea_mode(mode);
e6e79209
VS		 3688 unsigned int clock1, clock2;
3689
d9278b4c 3690 if (drm_valid_cea_vic(vic)) {
7befe621 3691 cea_mode = cea_mode_for_vic(vic);
3f2f6533
LD		 3692 clock2 = cea_mode_alternate_clock(cea_mode);
3693 } else {
d9278b4c
JN		 3694 vic = drm_match_hdmi_mode(mode);
3695 if (drm_valid_hdmi_vic(vic)) {
3696 cea_mode = &edid_4k_modes[vic];
3f2f6533
LD		 3697 clock2 = hdmi_mode_alternate_clock(cea_mode);
3698 }
3699 }
e6e79209 3700
3f2f6533
LD		 3701 if (!cea_mode)
3702 continue;
e6e79209
VS		 3703
3704 clock1 = cea_mode->clock;
e6e79209
VS		 3705
3706 if (clock1 == clock2)
3707 continue;
3708
3709 if (mode->clock != clock1 && mode->clock != clock2)
3710 continue;
3711
3712 newmode = drm_mode_duplicate(dev, cea_mode);
3713 if (!newmode)
3714 continue;
3715
27130212
DL		 3716 /* Carry over the stereo flags */
3717 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
3718
e6e79209
VS		 3719 /*
3720 * The current mode could be either variant. Make
3721 * sure to pick the "other" clock for the new mode.
3722 */
3723 if (mode->clock != clock1)
3724 newmode->clock = clock1;
3725 else
3726 newmode->clock = clock2;
3727
3728 list_add_tail(&newmode->head, &list);
3729 }
3730
3731 list_for_each_entry_safe(mode, tmp, &list, head) {
3732 list_del(&mode->head);
3733 drm_mode_probed_add(connector, mode);
3734 modes++;
3735 }
3736
3737 return modes;
3738}
a4799037 3739
8ec6e075
SS		 3740static u8 svd_to_vic(u8 svd)
3741{
3742 /* 0-6 bit vic, 7th bit native mode indicator */
3743 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
3744 return svd & 127;
3745
3746 return svd;
3747}
3748
aff04ace
TW		 3749static struct drm_display_mode *
3750drm_display_mode_from_vic_index(struct drm_connector *connector,
3751 const u8 *video_db, u8 video_len,
3752 u8 video_index)
54ac76f8
CS		 3753{
3754 struct drm_device *dev = connector->dev;
aff04ace 3755 struct drm_display_mode *newmode;
d9278b4c 3756 u8 vic;
54ac76f8 3757
aff04ace
TW		 3758 if (video_db == NULL || video_index >= video_len)
3759 return NULL;
3760
3761 /* CEA modes are numbered 1..127 */
8ec6e075 3762 vic = svd_to_vic(video_db[video_index]);
d9278b4c 3763 if (!drm_valid_cea_vic(vic))
aff04ace
TW		 3764 return NULL;
3765
7befe621 3766 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
409bbf1e
DL		 3767 if (!newmode)
3768 return NULL;
3769
aff04ace
TW		 3770 return newmode;
3771}
3772
832d4f2f
SS		 3773/*
3774 * do_y420vdb_modes - Parse YCBCR 420 only modes
3775 * @connector: connector corresponding to the HDMI sink
3776 * @svds: start of the data block of CEA YCBCR 420 VDB
3777 * @len: length of the CEA YCBCR 420 VDB
3778 *
3779 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
3780 * which contains modes which can be supported in YCBCR 420
3781 * output format only.
3782 */
3783static int do_y420vdb_modes(struct drm_connector *connector,
3784 const u8 *svds, u8 svds_len)
3785{
3786 int modes = 0, i;
3787 struct drm_device *dev = connector->dev;
3788 struct drm_display_info *info = &connector->display_info;
3789 struct drm_hdmi_info *hdmi = &info->hdmi;
3790
3791 for (i = 0; i < svds_len; i++) {
3792 u8 vic = svd_to_vic(svds[i]);
3793 struct drm_display_mode *newmode;
3794
3795 if (!drm_valid_cea_vic(vic))
3796 continue;
3797
7befe621 3798 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
832d4f2f
SS		 3799 if (!newmode)
3800 break;
3801 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
3802 drm_mode_probed_add(connector, newmode);
3803 modes++;
3804 }
3805
3806 if (modes > 0)
c03d0b52 3807 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
832d4f2f
SS		 3808 return modes;
3809}
3810
3811/*
3812 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap
3813 * @connector: connector corresponding to the HDMI sink
3814 * @vic: CEA vic for the video mode to be added in the map
3815 *
3816 * Makes an entry for a videomode in the YCBCR 420 bitmap
3817 */
3818static void
3819drm_add_cmdb_modes(struct drm_connector *connector, u8 svd)
3820{
3821 u8 vic = svd_to_vic(svd);
3822 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3823
3824 if (!drm_valid_cea_vic(vic))
3825 return;
3826
3827 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
3828}
3829
7af655bc
VS		 3830/**
3831 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC
3832 * @dev: DRM device
8d7d8c0a 3833 * @video_code: CEA VIC of the mode
7af655bc
VS		 3834 *
3835 * Creates a new mode matching the specified CEA VIC.
3836 *
3837 * Returns: A new drm_display_mode on success or NULL on failure
3838 */
3839struct drm_display_mode *
3840drm_display_mode_from_cea_vic(struct drm_device *dev,
3841 u8 video_code)
3842{
3843 const struct drm_display_mode *cea_mode;
3844 struct drm_display_mode *newmode;
3845
3846 cea_mode = cea_mode_for_vic(video_code);
3847 if (!cea_mode)
3848 return NULL;
3849
3850 newmode = drm_mode_duplicate(dev, cea_mode);
3851 if (!newmode)
3852 return NULL;
3853
3854 return newmode;
3855}
3856EXPORT_SYMBOL(drm_display_mode_from_cea_vic);
3857
aff04ace
TW		 3858static int
3859do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
3860{
3861 int i, modes = 0;
832d4f2f 3862 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
aff04ace
TW		 3863
3864 for (i = 0; i < len; i++) {
3865 struct drm_display_mode *mode;
948de842 3866
aff04ace
TW		 3867 mode = drm_display_mode_from_vic_index(connector, db, len, i);
3868 if (mode) {
832d4f2f
SS		 3869 /*
3870 * YCBCR420 capability block contains a bitmap which
3871 * gives the index of CEA modes from CEA VDB, which
3872 * can support YCBCR 420 sampling output also (apart
3873 * from RGB/YCBCR444 etc).
3874 * For example, if the bit 0 in bitmap is set,
3875 * first mode in VDB can support YCBCR420 output too.
3876 * Add YCBCR420 modes only if sink is HDMI 2.0 capable.
3877 */
3878 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i))
3879 drm_add_cmdb_modes(connector, db[i]);
3880
aff04ace
TW		 3881 drm_mode_probed_add(connector, mode);
3882 modes++;
54ac76f8
CS		 3883 }
3884 }
3885
3886 return modes;
3887}
3888
c858cfca
DL		 3889struct stereo_mandatory_mode {
3890 int width, height, vrefresh;
3891 unsigned int flags;
3892};
3893
3894static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
f7e121b7
DL		 3895 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3896 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
c858cfca
DL		 3897 { 1920, 1080, 50,
3898 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3899 { 1920, 1080, 60,
3900 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
f7e121b7
DL		 3901 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3902 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
3903 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3904 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
c858cfca
DL		 3905};
3906
3907static bool
3908stereo_match_mandatory(const struct drm_display_mode *mode,
3909 const struct stereo_mandatory_mode *stereo_mode)
3910{
3911 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
3912
3913 return mode->hdisplay == stereo_mode->width &&
3914 mode->vdisplay == stereo_mode->height &&
3915 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
3916 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
3917}
3918
c858cfca
DL		 3919static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
3920{
3921 struct drm_device *dev = connector->dev;
3922 const struct drm_display_mode *mode;
3923 struct list_head stereo_modes;
f7e121b7 3924 int modes = 0, i;
c858cfca
DL		 3925
3926 INIT_LIST_HEAD(&stereo_modes);
3927
3928 list_for_each_entry(mode, &connector->probed_modes, head) {
f7e121b7
DL		 3929 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
3930 const struct stereo_mandatory_mode *mandatory;
c858cfca
DL		 3931 struct drm_display_mode *new_mode;
3932
f7e121b7
DL		 3933 if (!stereo_match_mandatory(mode,
3934 &stereo_mandatory_modes[i]))
3935 continue;
c858cfca 3936
f7e121b7 3937 mandatory = &stereo_mandatory_modes[i];
c858cfca
DL		 3938 new_mode = drm_mode_duplicate(dev, mode);
3939 if (!new_mode)
3940 continue;
3941
f7e121b7 3942 new_mode->flags |= mandatory->flags;
c858cfca
DL		 3943 list_add_tail(&new_mode->head, &stereo_modes);
3944 modes++;
f7e121b7 3945 }
c858cfca
DL		 3946 }
3947
3948 list_splice_tail(&stereo_modes, &connector->probed_modes);
3949
3950 return modes;
3951}
3952
1deee8d7
DL		 3953static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
3954{
3955 struct drm_device *dev = connector->dev;
3956 struct drm_display_mode *newmode;
3957
d9278b4c 3958 if (!drm_valid_hdmi_vic(vic)) {
1deee8d7
DL		 3959 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
3960 return 0;
3961 }
3962
3963 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
3964 if (!newmode)
3965 return 0;
3966
3967 drm_mode_probed_add(connector, newmode);
3968
3969 return 1;
3970}
3971
fbf46025
TW		 3972static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
3973 const u8 *video_db, u8 video_len, u8 video_index)
3974{
fbf46025
TW		 3975 struct drm_display_mode *newmode;
3976 int modes = 0;
fbf46025
TW		 3977
3978 if (structure & (1 << 0)) {
aff04ace
TW		 3979 newmode = drm_display_mode_from_vic_index(connector, video_db,
3980 video_len,
3981 video_index);
fbf46025
TW		 3982 if (newmode) {
3983 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
3984 drm_mode_probed_add(connector, newmode);
3985 modes++;
3986 }
3987 }
3988 if (structure & (1 << 6)) {
aff04ace
TW		 3989 newmode = drm_display_mode_from_vic_index(connector, video_db,
3990 video_len,
3991 video_index);
fbf46025
TW		 3992 if (newmode) {
3993 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3994 drm_mode_probed_add(connector, newmode);
3995 modes++;
3996 }
3997 }
3998 if (structure & (1 << 8)) {
aff04ace
TW		 3999 newmode = drm_display_mode_from_vic_index(connector, video_db,
4000 video_len,
4001 video_index);
fbf46025 4002 if (newmode) {
89570eeb 4003 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
fbf46025
TW		 4004 drm_mode_probed_add(connector, newmode);
4005 modes++;
4006 }
4007 }
4008
4009 return modes;
4010}
4011
7ebe1963
LD		 4012/*
4013 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
4014 * @connector: connector corresponding to the HDMI sink
4015 * @db: start of the CEA vendor specific block
4016 * @len: length of the CEA block payload, ie. one can access up to db[len]
4017 *
c858cfca
DL		 4018 * Parses the HDMI VSDB looking for modes to add to @connector. This function
4019 * also adds the stereo 3d modes when applicable.
7ebe1963
LD		 4020 */
4021static int
fbf46025
TW		 4022do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
4023 const u8 *video_db, u8 video_len)
7ebe1963 4024{
f1781e9b 4025 struct drm_display_info *info = &connector->display_info;
0e5083aa 4026 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
fbf46025
TW		 4027 u8 vic_len, hdmi_3d_len = 0;
4028 u16 mask;
4029 u16 structure_all;
7ebe1963
LD		 4030
4031 if (len < 8)
4032 goto out;
4033
4034 /* no HDMI_Video_Present */
4035 if (!(db[8] & (1 << 5)))
4036 goto out;
4037
4038 /* Latency_Fields_Present */
4039 if (db[8] & (1 << 7))
4040 offset += 2;
4041
4042 /* I_Latency_Fields_Present */
4043 if (db[8] & (1 << 6))
4044 offset += 2;
4045
4046 /* the declared length is not long enough for the 2 first bytes
4047 * of additional video format capabilities */
c858cfca 4048 if (len < (8 + offset + 2))
7ebe1963
LD		 4049 goto out;
4050
c858cfca
DL		 4051 /* 3D_Present */
4052 offset++;
fbf46025 4053 if (db[8 + offset] & (1 << 7)) {
c858cfca
DL		 4054 modes += add_hdmi_mandatory_stereo_modes(connector);
4055
fbf46025
TW		 4056 /* 3D_Multi_present */
4057 multi_present = (db[8 + offset] & 0x60) >> 5;
4058 }
4059
c858cfca 4060 offset++;
7ebe1963 4061 vic_len = db[8 + offset] >> 5;
fbf46025 4062 hdmi_3d_len = db[8 + offset] & 0x1f;
7ebe1963
LD		 4063
4064 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
7ebe1963
LD		 4065 u8 vic;
4066
4067 vic = db[9 + offset + i];
1deee8d7 4068 modes += add_hdmi_mode(connector, vic);
7ebe1963 4069 }
fbf46025
TW		 4070 offset += 1 + vic_len;
4071
0e5083aa
TW		 4072 if (multi_present == 1)
4073 multi_len = 2;
4074 else if (multi_present == 2)
4075 multi_len = 4;
4076 else
4077 multi_len = 0;
fbf46025 4078
0e5083aa 4079 if (len < (8 + offset + hdmi_3d_len - 1))
fbf46025
TW		 4080 goto out;
4081
0e5083aa 4082 if (hdmi_3d_len < multi_len)
fbf46025
TW		 4083 goto out;
4084
0e5083aa
TW		 4085 if (multi_present == 1 || multi_present == 2) {
4086 /* 3D_Structure_ALL */
4087 structure_all = (db[8 + offset] << 8) | db[9 + offset];
fbf46025 4088
0e5083aa
TW		 4089 /* check if 3D_MASK is present */
4090 if (multi_present == 2)
4091 mask = (db[10 + offset] << 8) | db[11 + offset];
4092 else
4093 mask = 0xffff;
4094
4095 for (i = 0; i < 16; i++) {
4096 if (mask & (1 << i))
4097 modes += add_3d_struct_modes(connector,
4098 structure_all,
4099 video_db,
4100 video_len, i);
4101 }
4102 }
4103
4104 offset += multi_len;
4105
4106 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
4107 int vic_index;
4108 struct drm_display_mode *newmode = NULL;
4109 unsigned int newflag = 0;
4110 bool detail_present;
4111
4112 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
4113
4114 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
4115 break;
4116
4117 /* 2D_VIC_order_X */
4118 vic_index = db[8 + offset + i] >> 4;
4119
4120 /* 3D_Structure_X */
4121 switch (db[8 + offset + i] & 0x0f) {
4122 case 0:
4123 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
4124 break;
4125 case 6:
4126 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4127 break;
4128 case 8:
4129 /* 3D_Detail_X */
4130 if ((db[9 + offset + i] >> 4) == 1)
4131 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4132 break;
4133 }
4134
4135 if (newflag != 0) {
4136 newmode = drm_display_mode_from_vic_index(connector,
4137 video_db,
4138 video_len,
4139 vic_index);
4140
4141 if (newmode) {
4142 newmode->flags |= newflag;
4143 drm_mode_probed_add(connector, newmode);
4144 modes++;
4145 }
4146 }
4147
4148 if (detail_present)
4149 i++;
fbf46025 4150 }
7ebe1963
LD		 4151
4152out:
f1781e9b
VS		 4153 if (modes > 0)
4154 info->has_hdmi_infoframe = true;
7ebe1963
LD		 4155 return modes;
4156}
4157
9e50b9d5
VS		 4158static int
4159cea_db_payload_len(const u8 *db)
4160{
4161 return db[0] & 0x1f;
4162}
4163
87563fc0
SS		 4164static int
4165cea_db_extended_tag(const u8 *db)
4166{
4167 return db[1];
4168}
4169
9e50b9d5
VS		 4170static int
4171cea_db_tag(const u8 *db)
4172{
4173 return db[0] >> 5;
4174}
4175
4176static int
4177cea_revision(const u8 *cea)
4178{
5036c0d0
VS		 4179 /*
4180 * FIXME is this correct for the DispID variant?
4181 * The DispID spec doesn't really specify whether
4182 * this is the revision of the CEA extension or
4183 * the DispID CEA data block. And the only value
4184 * given as an example is 0.
4185 */
9e50b9d5
VS		 4186 return cea[1];
4187}
4188
4189static int
4190cea_db_offsets(const u8 *cea, int *start, int *end)
4191{
e28ad544
AR		 4192 /* DisplayID CTA extension blocks and top-level CEA EDID
4193 * block header definitions differ in the following bytes:
4194 * 1) Byte 2 of the header specifies length differently,
4195 * 2) Byte 3 is only present in the CEA top level block.
4196 *
4197 * The different definitions for byte 2 follow.
4198 *
4199 * DisplayID CTA extension block defines byte 2 as:
4200 * Number of payload bytes
4201 *
4202 * CEA EDID block defines byte 2 as:
4203 * Byte number (decimal) within this block where the 18-byte
4204 * DTDs begin. If no non-DTD data is present in this extension
4205 * block, the value should be set to 04h (the byte after next).
4206 * If set to 00h, there are no DTDs present in this block and
4207 * no non-DTD data.
4208 */
4209 if (cea[0] == DATA_BLOCK_CTA) {
6e8a942b
VS		 4210 /*
4211 * for_each_displayid_db() has already verified
4212 * that these stay within expected bounds.
4213 */
e28ad544
AR		 4214 *start = 3;
4215 *end = *start + cea[2];
4216 } else if (cea[0] == CEA_EXT) {
4217 /* Data block offset in CEA extension block */
4218 *start = 4;
4219 *end = cea[2];
4220 if (*end == 0)
4221 *end = 127;
4222 if (*end < 4 || *end > 127)
4223 return -ERANGE;
4224 } else {
c7581a41 4225 return -EOPNOTSUPP;
e28ad544
AR		 4226 }
4227
9e50b9d5
VS		 4228 return 0;
4229}
4230
7ebe1963
LD		 4231static bool cea_db_is_hdmi_vsdb(const u8 *db)
4232{
7ebe1963
LD		 4233 if (cea_db_tag(db) != VENDOR_BLOCK)
4234 return false;
4235
4236 if (cea_db_payload_len(db) < 5)
4237 return false;
4238
37eab1fe 4239 return oui(db[3], db[2], db[1]) == HDMI_IEEE_OUI;
7ebe1963
LD		 4240}
4241
50dd1bd1
TR		 4242static bool cea_db_is_hdmi_forum_vsdb(const u8 *db)
4243{
50dd1bd1
TR		 4244 if (cea_db_tag(db) != VENDOR_BLOCK)
4245 return false;
4246
4247 if (cea_db_payload_len(db) < 7)
4248 return false;
4249
37eab1fe 4250 return oui(db[3], db[2], db[1]) == HDMI_FORUM_IEEE_OUI;
50dd1bd1
TR		 4251}
4252
2869f599
PZ		 4253static bool cea_db_is_microsoft_vsdb(const u8 *db)
4254{
4255 if (cea_db_tag(db) != VENDOR_BLOCK)
4256 return false;
4257
4258 if (cea_db_payload_len(db) != 21)
4259 return false;
4260
4261 return oui(db[3], db[2], db[1]) == MICROSOFT_IEEE_OUI;
4262}
4263
1581b2df
VS		 4264static bool cea_db_is_vcdb(const u8 *db)
4265{
4266 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4267 return false;
4268
4269 if (cea_db_payload_len(db) != 2)
4270 return false;
4271
4272 if (cea_db_extended_tag(db) != EXT_VIDEO_CAPABILITY_BLOCK)
4273 return false;
4274
4275 return true;
4276}
4277
832d4f2f
SS		 4278static bool cea_db_is_y420cmdb(const u8 *db)
4279{
4280 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4281 return false;
4282
4283 if (!cea_db_payload_len(db))
4284 return false;
4285
4286 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB)
4287 return false;
4288
4289 return true;
4290}
4291
4292static bool cea_db_is_y420vdb(const u8 *db)
4293{
4294 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4295 return false;
4296
4297 if (!cea_db_payload_len(db))
4298 return false;
4299
4300 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420)
4301 return false;
4302
4303 return true;
4304}
4305
9e50b9d5
VS		 4306#define for_each_cea_db(cea, i, start, end) \
4307 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
4308
832d4f2f
SS		 4309static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector,
4310 const u8 *db)
4311{
4312 struct drm_display_info *info = &connector->display_info;
4313 struct drm_hdmi_info *hdmi = &info->hdmi;
4314 u8 map_len = cea_db_payload_len(db) - 1;
4315 u8 count;
4316 u64 map = 0;
4317
4318 if (map_len == 0) {
4319 /* All CEA modes support ycbcr420 sampling also.*/
4320 hdmi->y420_cmdb_map = U64_MAX;
c03d0b52 4321 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
832d4f2f
SS		 4322 return;
4323 }
4324
4325 /*
4326 * This map indicates which of the existing CEA block modes
4327 * from VDB can support YCBCR420 output too. So if bit=0 is
4328 * set, first mode from VDB can support YCBCR420 output too.
4329 * We will parse and keep this map, before parsing VDB itself
4330 * to avoid going through the same block again and again.
4331 *
4332 * Spec is not clear about max possible size of this block.
4333 * Clamping max bitmap block size at 8 bytes. Every byte can
4334 * address 8 CEA modes, in this way this map can address
4335 * 8*8 = first 64 SVDs.
4336 */
4337 if (WARN_ON_ONCE(map_len > 8))
4338 map_len = 8;
4339
4340 for (count = 0; count < map_len; count++)
4341 map |= (u64)db[2 + count] << (8 * count);
4342
4343 if (map)
c03d0b52 4344 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
832d4f2f
SS		 4345
4346 hdmi->y420_cmdb_map = map;
4347}
4348
54ac76f8
CS		 4349static int
4350add_cea_modes(struct drm_connector *connector, struct edid *edid)
4351{
13ac3f55 4352 const u8 *cea = drm_find_cea_extension(edid);
fbf46025
TW		 4353 const u8 *db, *hdmi = NULL, *video = NULL;
4354 u8 dbl, hdmi_len, video_len = 0;
54ac76f8
CS		 4355 int modes = 0;
4356
9e50b9d5
VS		 4357 if (cea && cea_revision(cea) >= 3) {
4358 int i, start, end;
4359
4360 if (cea_db_offsets(cea, &start, &end))
4361 return 0;
4362
4363 for_each_cea_db(cea, i, start, end) {
4364 db = &cea[i];
4365 dbl = cea_db_payload_len(db);
4366
fbf46025
TW		 4367 if (cea_db_tag(db) == VIDEO_BLOCK) {
4368 video = db + 1;
4369 video_len = dbl;
4370 modes += do_cea_modes(connector, video, dbl);
832d4f2f 4371 } else if (cea_db_is_hdmi_vsdb(db)) {
c858cfca
DL		 4372 hdmi = db;
4373 hdmi_len = dbl;
832d4f2f
SS		 4374 } else if (cea_db_is_y420vdb(db)) {
4375 const u8 *vdb420 = &db[2];
4376
4377 /* Add 4:2:0(only) modes present in EDID */
4378 modes += do_y420vdb_modes(connector,
4379 vdb420,
4380 dbl - 1);
c858cfca 4381 }
54ac76f8
CS		 4382 }
4383 }
4384
c858cfca
DL		 4385 /*
4386 * We parse the HDMI VSDB after having added the cea modes as we will
4387 * be patching their flags when the sink supports stereo 3D.
4388 */
4389 if (hdmi)
fbf46025
TW		 4390 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
4391 video_len);
c858cfca 4392
54ac76f8
CS		 4393 return modes;
4394}
4395
fa3a7340
VS		 4396static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
4397{
4398 const struct drm_display_mode *cea_mode;
4399 int clock1, clock2, clock;
d9278b4c 4400 u8 vic;
fa3a7340
VS		 4401 const char *type;
4402
4c6bcf44
VS		 4403 /*
4404 * allow 5kHz clock difference either way to account for
4405 * the 10kHz clock resolution limit of detailed timings.
4406 */
d9278b4c
JN		 4407 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
4408 if (drm_valid_cea_vic(vic)) {
fa3a7340 4409 type = "CEA";
7befe621 4410 cea_mode = cea_mode_for_vic(vic);
fa3a7340
VS		 4411 clock1 = cea_mode->clock;
4412 clock2 = cea_mode_alternate_clock(cea_mode);
4413 } else {
d9278b4c
JN		 4414 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
4415 if (drm_valid_hdmi_vic(vic)) {
fa3a7340 4416 type = "HDMI";
d9278b4c 4417 cea_mode = &edid_4k_modes[vic];
fa3a7340
VS		 4418 clock1 = cea_mode->clock;
4419 clock2 = hdmi_mode_alternate_clock(cea_mode);
4420 } else {
4421 return;
4422 }
4423 }
4424
4425 /* pick whichever is closest */
4426 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
4427 clock = clock1;
4428 else
4429 clock = clock2;
4430
4431 if (mode->clock == clock)
4432 return;
4433
4434 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
d9278b4c 4435 type, vic, mode->clock, clock);
fa3a7340
VS		 4436 mode->clock = clock;
4437}
4438
e85959d6
US		 4439static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db)
4440{
4441 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4442 return false;
4443
4444 if (db[1] != HDR_STATIC_METADATA_BLOCK)
4445 return false;
4446
4447 if (cea_db_payload_len(db) < 3)
4448 return false;
4449
4450 return true;
4451}
4452
4453static uint8_t eotf_supported(const u8 *edid_ext)
4454{
4455 return edid_ext[2] &
4456 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
4457 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
b5e3eed1
VS		 4458 BIT(HDMI_EOTF_SMPTE_ST2084) |
4459 BIT(HDMI_EOTF_BT_2100_HLG));
e85959d6
US		 4460}
4461
4462static uint8_t hdr_metadata_type(const u8 *edid_ext)
4463{
4464 return edid_ext[3] &
4465 BIT(HDMI_STATIC_METADATA_TYPE1);
4466}
4467
4468static void
4469drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
4470{
4471 u16 len;
4472
4473 len = cea_db_payload_len(db);
4474
4475 connector->hdr_sink_metadata.hdmi_type1.eotf =
4476 eotf_supported(db);
4477 connector->hdr_sink_metadata.hdmi_type1.metadata_type =
4478 hdr_metadata_type(db);
4479
4480 if (len >= 4)
4481 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4];
4482 if (len >= 5)
4483 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5];
4484 if (len >= 6)
4485 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6];
4486}
4487
76adaa34 4488static void
23ebf8b9 4489drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
76adaa34 4490{
8504072a 4491 u8 len = cea_db_payload_len(db);
76adaa34 4492
f7da7785
JN		 4493 if (len >= 6 && (db[6] & (1 << 7)))
4494 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
8504072a
VS		 4495 if (len >= 8) {
4496 connector->latency_present[0] = db[8] >> 7;
4497 connector->latency_present[1] = (db[8] >> 6) & 1;
4498 }
4499 if (len >= 9)
4500 connector->video_latency[0] = db[9];
4501 if (len >= 10)
4502 connector->audio_latency[0] = db[10];
4503 if (len >= 11)
4504 connector->video_latency[1] = db[11];
4505 if (len >= 12)
4506 connector->audio_latency[1] = db[12];
76adaa34 4507
23ebf8b9
VS		 4508 DRM_DEBUG_KMS("HDMI: latency present %d %d, "
4509 "video latency %d %d, "
4510 "audio latency %d %d\n",
4511 connector->latency_present[0],
4512 connector->latency_present[1],
4513 connector->video_latency[0],
4514 connector->video_latency[1],
4515 connector->audio_latency[0],
4516 connector->audio_latency[1]);
76adaa34
WF		 4517}
4518
4519static void
4520monitor_name(struct detailed_timing *t, void *data)
4521{
e379814b 4522 if (!is_display_descriptor(t, EDID_DETAIL_MONITOR_NAME))
a7a131ac
VS		 4523 return;
4524
4525 *(u8 **)data = t->data.other_data.data.str.str;
14f77fdd
VS		 4526}
4527
59f7c0fa
JB		 4528static int get_monitor_name(struct edid *edid, char name[13])
4529{
4530 char *edid_name = NULL;
4531 int mnl;
4532
4533 if (!edid || !name)
4534 return 0;
4535
4536 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name);
4537 for (mnl = 0; edid_name && mnl < 13; mnl++) {
4538 if (edid_name[mnl] == 0x0a)
4539 break;
4540
4541 name[mnl] = edid_name[mnl];
4542 }
4543
4544 return mnl;
4545}
4546
4547/**
4548 * drm_edid_get_monitor_name - fetch the monitor name from the edid
4549 * @edid: monitor EDID information
4550 * @name: pointer to a character array to hold the name of the monitor
4551 * @bufsize: The size of the name buffer (should be at least 14 chars.)
4552 *
4553 */
4554void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize)
4555{
4556 int name_length;
4557 char buf[13];
4d23f484 4558
59f7c0fa
JB		 4559 if (bufsize <= 0)
4560 return;
4561
4562 name_length = min(get_monitor_name(edid, buf), bufsize - 1);
4563 memcpy(name, buf, name_length);
4564 name[name_length] = '\0';
4565}
4566EXPORT_SYMBOL(drm_edid_get_monitor_name);
4567
42750d39
JN		 4568static void clear_eld(struct drm_connector *connector)
4569{
4570 memset(connector->eld, 0, sizeof(connector->eld));
4571
4572 connector->latency_present[0] = false;
4573 connector->latency_present[1] = false;
4574 connector->video_latency[0] = 0;
4575 connector->audio_latency[0] = 0;
4576 connector->video_latency[1] = 0;
4577 connector->audio_latency[1] = 0;
4578}
4579
79436a1c 4580/*
76adaa34
WF		 4581 * drm_edid_to_eld - build ELD from EDID
4582 * @connector: connector corresponding to the HDMI/DP sink
4583 * @edid: EDID to parse
4584 *
db6cf833 4585 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
1d1c3665 4586 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
76adaa34 4587 */
79436a1c 4588static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
76adaa34
WF		 4589{
4590 uint8_t *eld = connector->eld;
43d16d84
JN		 4591 const u8 *cea;
4592 const u8 *db;
7c018782 4593 int total_sad_count = 0;
76adaa34
WF		 4594 int mnl;
4595 int dbl;
4596
42750d39 4597 clear_eld(connector);
85c91580 4598
e9bd0b84
JN		 4599 if (!edid)
4600 return;
4601
76adaa34
WF		 4602 cea = drm_find_cea_extension(edid);
4603 if (!cea) {
4604 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
4605 return;
4606 }
4607
f7da7785
JN		 4608 mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
4609 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]);
59f7c0fa 4610
f7da7785
JN		 4611 eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT;
4612 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
76adaa34 4613
f7da7785 4614 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
76adaa34 4615
f7da7785
JN		 4616 eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0];
4617 eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1];
4618 eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0];
4619 eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1];
76adaa34 4620
9e50b9d5
VS		 4621 if (cea_revision(cea) >= 3) {
4622 int i, start, end;
deec222e 4623 int sad_count;
9e50b9d5
VS		 4624
4625 if (cea_db_offsets(cea, &start, &end)) {
4626 start = 0;
4627 end = 0;
4628 }
4629
4630 for_each_cea_db(cea, i, start, end) {
4631 db = &cea[i];
4632 dbl = cea_db_payload_len(db);
4633
4634 switch (cea_db_tag(db)) {
a0ab734d
CS		 4635 case AUDIO_BLOCK:
4636 /* Audio Data Block, contains SADs */
7c018782
VS		 4637 sad_count = min(dbl / 3, 15 - total_sad_count);
4638 if (sad_count >= 1)
f7da7785 4639 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
7c018782
VS		 4640 &db[1], sad_count * 3);
4641 total_sad_count += sad_count;
a0ab734d
CS		 4642 break;
4643 case SPEAKER_BLOCK:
9e50b9d5
VS		 4644 /* Speaker Allocation Data Block */
4645 if (dbl >= 1)
f7da7785 4646 eld[DRM_ELD_SPEAKER] = db[1];
a0ab734d
CS		 4647 break;
4648 case VENDOR_BLOCK:
4649 /* HDMI Vendor-Specific Data Block */
14f77fdd 4650 if (cea_db_is_hdmi_vsdb(db))
23ebf8b9 4651 drm_parse_hdmi_vsdb_audio(connector, db);
a0ab734d
CS		 4652 break;
4653 default:
4654 break;
4655 }
76adaa34 4656 }
9e50b9d5 4657 }
f7da7785 4658 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
76adaa34 4659
1d1c3665
JN		 4660 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
4661 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4662 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
4663 else
4664 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
76adaa34 4665
938fd8aa
JN		 4666 eld[DRM_ELD_BASELINE_ELD_LEN] =
4667 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
4668
4669 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
7c018782 4670 drm_eld_size(eld), total_sad_count);
76adaa34 4671}
76adaa34 4672
fe214163
RM		 4673/**
4674 * drm_edid_to_sad - extracts SADs from EDID
4675 * @edid: EDID to parse
4676 * @sads: pointer that will be set to the extracted SADs
4677 *
4678 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
fe214163 4679 *
db6cf833
TR		 4680 * Note: The returned pointer needs to be freed using kfree().
4681 *
4682 * Return: The number of found SADs or negative number on error.
fe214163
RM		 4683 */
4684int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
4685{
4686 int count = 0;
4687 int i, start, end, dbl;
43d16d84 4688 const u8 *cea;
fe214163
RM		 4689
4690 cea = drm_find_cea_extension(edid);
4691 if (!cea) {
4692 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
42908007 4693 return 0;
fe214163
RM		 4694 }
4695
4696 if (cea_revision(cea) < 3) {
4697 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
42908007 4698 return 0;
fe214163
RM		 4699 }
4700
4701 if (cea_db_offsets(cea, &start, &end)) {
4702 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4703 return -EPROTO;
4704 }
4705
4706 for_each_cea_db(cea, i, start, end) {
43d16d84 4707 const u8 *db = &cea[i];
fe214163
RM		 4708
4709 if (cea_db_tag(db) == AUDIO_BLOCK) {
4710 int j;
948de842 4711
fe214163
RM		 4712 dbl = cea_db_payload_len(db);
4713
4714 count = dbl / 3; /* SAD is 3B */
4715 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
4716 if (!*sads)
4717 return -ENOMEM;
4718 for (j = 0; j < count; j++) {
43d16d84 4719 const u8 *sad = &db[1 + j * 3];
fe214163
RM		 4720
4721 (*sads)[j].format = (sad[0] & 0x78) >> 3;
4722 (*sads)[j].channels = sad[0] & 0x7;
4723 (*sads)[j].freq = sad[1] & 0x7F;
4724 (*sads)[j].byte2 = sad[2];
4725 }
4726 break;
4727 }
4728 }
4729
4730 return count;
4731}
4732EXPORT_SYMBOL(drm_edid_to_sad);
4733
d105f476
AD		 4734/**
4735 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
4736 * @edid: EDID to parse
4737 * @sadb: pointer to the speaker block
4738 *
4739 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
d105f476 4740 *
db6cf833
TR		 4741 * Note: The returned pointer needs to be freed using kfree().
4742 *
4743 * Return: The number of found Speaker Allocation Blocks or negative number on
4744 * error.
d105f476
AD		 4745 */
4746int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
4747{
4748 int count = 0;
4749 int i, start, end, dbl;
4750 const u8 *cea;
4751
4752 cea = drm_find_cea_extension(edid);
4753 if (!cea) {
4754 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
42908007 4755 return 0;
d105f476
AD		 4756 }
4757
4758 if (cea_revision(cea) < 3) {
4759 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
42908007 4760 return 0;
d105f476
AD		 4761 }
4762
4763 if (cea_db_offsets(cea, &start, &end)) {
4764 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4765 return -EPROTO;
4766 }
4767
4768 for_each_cea_db(cea, i, start, end) {
4769 const u8 *db = &cea[i];
4770
4771 if (cea_db_tag(db) == SPEAKER_BLOCK) {
4772 dbl = cea_db_payload_len(db);
4773
4774 /* Speaker Allocation Data Block */
4775 if (dbl == 3) {
89086bca 4776 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
618e3776
AD		 4777 if (!*sadb)
4778 return -ENOMEM;
d105f476
AD		 4779 count = dbl;
4780 break;
4781 }
4782 }
4783 }
4784
4785 return count;
4786}
4787EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
4788
76adaa34 4789/**
db6cf833 4790 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
76adaa34
WF		 4791 * @connector: connector associated with the HDMI/DP sink
4792 * @mode: the display mode
db6cf833
TR		 4793 *
4794 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
4795 * the sink doesn't support audio or video.
76adaa34
WF		 4796 */
4797int drm_av_sync_delay(struct drm_connector *connector,
3a818d35 4798 const struct drm_display_mode *mode)
76adaa34
WF		 4799{
4800 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
4801 int a, v;
4802
4803 if (!connector->latency_present[0])
4804 return 0;
4805 if (!connector->latency_present[1])
4806 i = 0;
4807
4808 a = connector->audio_latency[i];
4809 v = connector->video_latency[i];
4810
4811 /*
4812 * HDMI/DP sink doesn't support audio or video?
4813 */
4814 if (a == 255 || v == 255)
4815 return 0;
4816
4817 /*
4818 * Convert raw EDID values to millisecond.
4819 * Treat unknown latency as 0ms.
4820 */
4821 if (a)
4822 a = min(2 * (a - 1), 500);
4823 if (v)
4824 v = min(2 * (v - 1), 500);
4825
4826 return max(v - a, 0);
4827}
4828EXPORT_SYMBOL(drm_av_sync_delay);
4829
8fe9790d 4830/**
db6cf833 4831 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
8fe9790d
ZW		 4832 * @edid: monitor EDID information
4833 *
4834 * Parse the CEA extension according to CEA-861-B.
db6cf833 4835 *
a92d083d
LP		 4836 * Drivers that have added the modes parsed from EDID to drm_display_info
4837 * should use &drm_display_info.is_hdmi instead of calling this function.
4838 *
db6cf833 4839 * Return: True if the monitor is HDMI, false if not or unknown.
8fe9790d
ZW		 4840 */
4841bool drm_detect_hdmi_monitor(struct edid *edid)
4842{
43d16d84 4843 const u8 *edid_ext;
14f77fdd 4844 int i;
8fe9790d 4845 int start_offset, end_offset;
8fe9790d
ZW		 4846
4847 edid_ext = drm_find_cea_extension(edid);
4848 if (!edid_ext)
14f77fdd 4849 return false;
f23c20c8 4850
9e50b9d5 4851 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
14f77fdd 4852 return false;
f23c20c8
ML		 4853
4854 /*
4855 * Because HDMI identifier is in Vendor Specific Block,
4856 * search it from all data blocks of CEA extension.
4857 */
9e50b9d5 4858 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
14f77fdd
VS		 4859 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
4860 return true;
f23c20c8
ML		 4861 }
4862
14f77fdd 4863 return false;
f23c20c8
ML		 4864}
4865EXPORT_SYMBOL(drm_detect_hdmi_monitor);
4866
8fe9790d
ZW		 4867/**
4868 * drm_detect_monitor_audio - check monitor audio capability
fc66811c 4869 * @edid: EDID block to scan
8fe9790d
ZW		 4870 *
4871 * Monitor should have CEA extension block.
4872 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
4873 * audio' only. If there is any audio extension block and supported
4874 * audio format, assume at least 'basic audio' support, even if 'basic
4875 * audio' is not defined in EDID.
4876 *
db6cf833 4877 * Return: True if the monitor supports audio, false otherwise.
8fe9790d
ZW		 4878 */
4879bool drm_detect_monitor_audio(struct edid *edid)
4880{
43d16d84 4881 const u8 *edid_ext;
8fe9790d
ZW		 4882 int i, j;
4883 bool has_audio = false;
4884 int start_offset, end_offset;
4885
4886 edid_ext = drm_find_cea_extension(edid);
4887 if (!edid_ext)
4888 goto end;
4889
4890 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
4891
4892 if (has_audio) {
4893 DRM_DEBUG_KMS("Monitor has basic audio support\n");
4894 goto end;
4895 }
4896
9e50b9d5
VS		 4897 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4898 goto end;
8fe9790d 4899
9e50b9d5
VS		 4900 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4901 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
8fe9790d 4902 has_audio = true;
9e50b9d5 4903 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
8fe9790d
ZW		 4904 DRM_DEBUG_KMS("CEA audio format %d\n",
4905 (edid_ext[i + j] >> 3) & 0xf);
4906 goto end;
4907 }
4908 }
4909end:
4910 return has_audio;
4911}
4912EXPORT_SYMBOL(drm_detect_monitor_audio);
4913
b1edd6a6 4914
c8127cf0
VS		 4915/**
4916 * drm_default_rgb_quant_range - default RGB quantization range
4917 * @mode: display mode
4918 *
4919 * Determine the default RGB quantization range for the mode,
4920 * as specified in CEA-861.
4921 *
4922 * Return: The default RGB quantization range for the mode
4923 */
4924enum hdmi_quantization_range
4925drm_default_rgb_quant_range(const struct drm_display_mode *mode)
4926{
4927 /* All CEA modes other than VIC 1 use limited quantization range. */
4928 return drm_match_cea_mode(mode) > 1 ?
4929 HDMI_QUANTIZATION_RANGE_LIMITED :
4930 HDMI_QUANTIZATION_RANGE_FULL;
4931}
4932EXPORT_SYMBOL(drm_default_rgb_quant_range);
4933
1581b2df
VS		 4934static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
4935{
4936 struct drm_display_info *info = &connector->display_info;
4937
4938 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]);
4939
4940 if (db[2] & EDID_CEA_VCDB_QS)
4941 info->rgb_quant_range_selectable = true;
4942}
4943
4499d488
SS		 4944static
4945void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane)
4946{
4947 switch (max_frl_rate) {
4948 case 1:
4949 *max_lanes = 3;
4950 *max_rate_per_lane = 3;
4951 break;
4952 case 2:
4953 *max_lanes = 3;
4954 *max_rate_per_lane = 6;
4955 break;
4956 case 3:
4957 *max_lanes = 4;
4958 *max_rate_per_lane = 6;
4959 break;
4960 case 4:
4961 *max_lanes = 4;
4962 *max_rate_per_lane = 8;
4963 break;
4964 case 5:
4965 *max_lanes = 4;
4966 *max_rate_per_lane = 10;
4967 break;
4968 case 6:
4969 *max_lanes = 4;
4970 *max_rate_per_lane = 12;
4971 break;
4972 case 0:
4973 default:
4974 *max_lanes = 0;
4975 *max_rate_per_lane = 0;
4976 }
4977}
4978
e6a9a2c3
SS		 4979static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
4980 const u8 *db)
4981{
4982 u8 dc_mask;
4983 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4984
4985 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
9068e02f 4986 hdmi->y420_dc_modes = dc_mask;
e6a9a2c3
SS		 4987}
4988
afa1c763
SS		 4989static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector,
4990 const u8 *hf_vsdb)
4991{
62c58af3
SS		 4992 struct drm_display_info *display = &connector->display_info;
4993 struct drm_hdmi_info *hdmi = &display->hdmi;
afa1c763 4994
f1781e9b
VS		 4995 display->has_hdmi_infoframe = true;
4996
afa1c763
SS		 4997 if (hf_vsdb[6] & 0x80) {
4998 hdmi->scdc.supported = true;
4999 if (hf_vsdb[6] & 0x40)
5000 hdmi->scdc.read_request = true;
5001 }
62c58af3
SS		 5002
5003 /*
5004 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
5005 * And as per the spec, three factors confirm this:
5006 * * Availability of a HF-VSDB block in EDID (check)
5007 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
5008 * * SCDC support available (let's check)
5009 * Lets check it out.
5010 */
5011
5012 if (hf_vsdb[5]) {
5013 /* max clock is 5000 KHz times block value */
5014 u32 max_tmds_clock = hf_vsdb[5] * 5000;
5015 struct drm_scdc *scdc = &hdmi->scdc;
5016
5017 if (max_tmds_clock > 340000) {
5018 display->max_tmds_clock = max_tmds_clock;
5019 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
5020 display->max_tmds_clock);
5021 }
5022
5023 if (scdc->supported) {
5024 scdc->scrambling.supported = true;
5025
dbe2d2bf 5026 /* Few sinks support scrambling for clocks < 340M */
62c58af3
SS		 5027 if ((hf_vsdb[6] & 0x8))
5028 scdc->scrambling.low_rates = true;
5029 }
5030 }
e6a9a2c3 5031
4499d488
SS		 5032 if (hf_vsdb[7]) {
5033 u8 max_frl_rate;
76ee7b90
AN		 5034 u8 dsc_max_frl_rate;
5035 u8 dsc_max_slices;
5036 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap;
4499d488
SS		 5037
5038 DRM_DEBUG_KMS("hdmi_21 sink detected. parsing edid\n");
5039 max_frl_rate = (hf_vsdb[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4;
5040 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes,
5041 &hdmi->max_frl_rate_per_lane);
76ee7b90
AN		 5042 hdmi_dsc->v_1p2 = hf_vsdb[11] & DRM_EDID_DSC_1P2;
5043
5044 if (hdmi_dsc->v_1p2) {
5045 hdmi_dsc->native_420 = hf_vsdb[11] & DRM_EDID_DSC_NATIVE_420;
5046 hdmi_dsc->all_bpp = hf_vsdb[11] & DRM_EDID_DSC_ALL_BPP;
5047
5048 if (hf_vsdb[11] & DRM_EDID_DSC_16BPC)
5049 hdmi_dsc->bpc_supported = 16;
5050 else if (hf_vsdb[11] & DRM_EDID_DSC_12BPC)
5051 hdmi_dsc->bpc_supported = 12;
5052 else if (hf_vsdb[11] & DRM_EDID_DSC_10BPC)
5053 hdmi_dsc->bpc_supported = 10;
5054 else
5055 hdmi_dsc->bpc_supported = 0;
5056
5057 dsc_max_frl_rate = (hf_vsdb[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4;
5058 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes,
5059 &hdmi_dsc->max_frl_rate_per_lane);
5060 hdmi_dsc->total_chunk_kbytes = hf_vsdb[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES;
5061
5062 dsc_max_slices = hf_vsdb[12] & DRM_EDID_DSC_MAX_SLICES;
5063 switch (dsc_max_slices) {
5064 case 1:
5065 hdmi_dsc->max_slices = 1;
5066 hdmi_dsc->clk_per_slice = 340;
5067 break;
5068 case 2:
5069 hdmi_dsc->max_slices = 2;
5070 hdmi_dsc->clk_per_slice = 340;
5071 break;
5072 case 3:
5073 hdmi_dsc->max_slices = 4;
5074 hdmi_dsc->clk_per_slice = 340;
5075 break;
5076 case 4:
5077 hdmi_dsc->max_slices = 8;
5078 hdmi_dsc->clk_per_slice = 340;
5079 break;
5080 case 5:
5081 hdmi_dsc->max_slices = 8;
5082 hdmi_dsc->clk_per_slice = 400;
5083 break;
5084 case 6:
5085 hdmi_dsc->max_slices = 12;
5086 hdmi_dsc->clk_per_slice = 400;
5087 break;
5088 case 7:
5089 hdmi_dsc->max_slices = 16;
5090 hdmi_dsc->clk_per_slice = 400;
5091 break;
5092 case 0:
5093 default:
5094 hdmi_dsc->max_slices = 0;
5095 hdmi_dsc->clk_per_slice = 0;
5096 }
5097 }
4499d488
SS		 5098 }
5099
e6a9a2c3 5100 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb);
afa1c763
SS		 5101}
5102
1cea146a
VS		 5103static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
5104 const u8 *hdmi)
d0c94692 5105{
1826750f 5106 struct drm_display_info *info = &connector->display_info;
d0c94692
MK		 5107 unsigned int dc_bpc = 0;
5108
1cea146a
VS		 5109 /* HDMI supports at least 8 bpc */
5110 info->bpc = 8;
d0c94692 5111
1cea146a
VS		 5112 if (cea_db_payload_len(hdmi) < 6)
5113 return;
5114
5115 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
5116 dc_bpc = 10;
4adc33f3 5117 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_30;
1cea146a
VS		 5118 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
5119 connector->name);
5120 }
5121
5122 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
5123 dc_bpc = 12;
4adc33f3 5124 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_36;
1cea146a
VS		 5125 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
5126 connector->name);
5127 }
5128
5129 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
5130 dc_bpc = 16;
4adc33f3 5131 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_48;
1cea146a
VS		 5132 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
5133 connector->name);
5134 }
5135
5136 if (dc_bpc == 0) {
5137 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
5138 connector->name);
5139 return;
5140 }
5141
5142 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
5143 connector->name, dc_bpc);
5144 info->bpc = dc_bpc;
d0c94692 5145
1cea146a
VS		 5146 /* YCRCB444 is optional according to spec. */
5147 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
4adc33f3 5148 info->edid_hdmi_ycbcr444_dc_modes = info->edid_hdmi_rgb444_dc_modes;
1cea146a
VS		 5149 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
5150 connector->name);
5151 }
d0c94692 5152
1cea146a
VS		 5153 /*
5154 * Spec says that if any deep color mode is supported at all,
5155 * then deep color 36 bit must be supported.
5156 */
5157 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
5158 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
5159 connector->name);
5160 }
5161}
d0c94692 5162
23ebf8b9
VS		 5163static void
5164drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
5165{
5166 struct drm_display_info *info = &connector->display_info;
5167 u8 len = cea_db_payload_len(db);
5168
a92d083d
LP		 5169 info->is_hdmi = true;
5170
23ebf8b9
VS		 5171 if (len >= 6)
5172 info->dvi_dual = db[6] & 1;
5173 if (len >= 7)
5174 info->max_tmds_clock = db[7] * 5000;
5175
5176 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
5177 "max TMDS clock %d kHz\n",
5178 info->dvi_dual,
5179 info->max_tmds_clock);
5180
5181 drm_parse_hdmi_deep_color_info(connector, db);
5182}
5183
2869f599
PZ		 5184/*
5185 * See EDID extension for head-mounted and specialized monitors, specified at:
5186 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/specialized-monitors-edid-extension
5187 */
5188static void drm_parse_microsoft_vsdb(struct drm_connector *connector,
5189 const u8 *db)
5190{
5191 struct drm_display_info *info = &connector->display_info;
5192 u8 version = db[4];
5193 bool desktop_usage = db[5] & BIT(6);
5194
5195 /* Version 1 and 2 for HMDs, version 3 flags desktop usage explicitly */
5196 if (version == 1 || version == 2 || (version == 3 && !desktop_usage))
5197 info->non_desktop = true;
5198
5199 drm_dbg_kms(connector->dev, "HMD or specialized display VSDB version %u: 0x%02x\n",
5200 version, db[5]);
5201}
5202
1cea146a 5203static void drm_parse_cea_ext(struct drm_connector *connector,
170178fe 5204 const struct edid *edid)
1cea146a
VS		 5205{
5206 struct drm_display_info *info = &connector->display_info;
5207 const u8 *edid_ext;
5208 int i, start, end;
d0c94692 5209
1cea146a
VS		 5210 edid_ext = drm_find_cea_extension(edid);
5211 if (!edid_ext)
5212 return;
d0c94692 5213
1cea146a 5214 info->cea_rev = edid_ext[1];
d0c94692 5215
1cea146a
VS		 5216 /* The existence of a CEA block should imply RGB support */
5217 info->color_formats = DRM_COLOR_FORMAT_RGB444;
5218 if (edid_ext[3] & EDID_CEA_YCRCB444)
c03d0b52 5219 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
1cea146a 5220 if (edid_ext[3] & EDID_CEA_YCRCB422)
c03d0b52 5221 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
1cea146a
VS		 5222
5223 if (cea_db_offsets(edid_ext, &start, &end))
5224 return;
5225
5226 for_each_cea_db(edid_ext, i, start, end) {
5227 const u8 *db = &edid_ext[i];
5228
23ebf8b9
VS		 5229 if (cea_db_is_hdmi_vsdb(db))
5230 drm_parse_hdmi_vsdb_video(connector, db);
afa1c763
SS		 5231 if (cea_db_is_hdmi_forum_vsdb(db))
5232 drm_parse_hdmi_forum_vsdb(connector, db);
2869f599
PZ		 5233 if (cea_db_is_microsoft_vsdb(db))
5234 drm_parse_microsoft_vsdb(connector, db);
832d4f2f
SS		 5235 if (cea_db_is_y420cmdb(db))
5236 drm_parse_y420cmdb_bitmap(connector, db);
1581b2df
VS		 5237 if (cea_db_is_vcdb(db))
5238 drm_parse_vcdb(connector, db);
e85959d6
US		 5239 if (cea_db_is_hdmi_hdr_metadata_block(db))
5240 drm_parse_hdr_metadata_block(connector, db);
1cea146a 5241 }
d0c94692
MK		 5242}
5243
a1d11d1e
MN		 5244static
5245void get_monitor_range(struct detailed_timing *timing,
5246 void *info_monitor_range)
5247{
5248 struct drm_monitor_range_info *monitor_range = info_monitor_range;
5249 const struct detailed_non_pixel *data = &timing->data.other_data;
5250 const struct detailed_data_monitor_range *range = &data->data.range;
5251
e379814b 5252 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
a1d11d1e
MN		 5253 return;
5254
5255 /*
5256 * Check for flag range limits only. If flag == 1 then
5257 * no additional timing information provided.
5258 * Default GTF, GTF Secondary curve and CVT are not
5259 * supported
5260 */
5261 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG)
5262 return;
5263
5264 monitor_range->min_vfreq = range->min_vfreq;
5265 monitor_range->max_vfreq = range->max_vfreq;
5266}
5267
5268static
5269void drm_get_monitor_range(struct drm_connector *connector,
5270 const struct edid *edid)
5271{
5272 struct drm_display_info *info = &connector->display_info;
5273
5274 if (!version_greater(edid, 1, 1))
5275 return;
5276
5277 drm_for_each_detailed_block((u8 *)edid, get_monitor_range,
5278 &info->monitor_range);
5279
5280 DRM_DEBUG_KMS("Supported Monitor Refresh rate range is %d Hz - %d Hz\n",
5281 info->monitor_range.min_vfreq,
5282 info->monitor_range.max_vfreq);
5283}
5284
18a9cbbe
JN		 5285static void drm_parse_vesa_mso_data(struct drm_connector *connector,
5286 const struct displayid_block *block)
5287{
5288 struct displayid_vesa_vendor_specific_block *vesa =
5289 (struct displayid_vesa_vendor_specific_block *)block;
5290 struct drm_display_info *info = &connector->display_info;
5291
5292 if (block->num_bytes < 3) {
5293 drm_dbg_kms(connector->dev, "Unexpected vendor block size %u\n",
5294 block->num_bytes);
5295 return;
5296 }
5297
5298 if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI)
5299 return;
5300
5301 if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
5302 drm_dbg_kms(connector->dev, "Unexpected VESA vendor block size\n");
5303 return;
5304 }
5305
5306 switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
5307 default:
5308 drm_dbg_kms(connector->dev, "Reserved MSO mode value\n");
5309 fallthrough;
5310 case 0:
5311 info->mso_stream_count = 0;
5312 break;
5313 case 1:
5314 info->mso_stream_count = 2; /* 2 or 4 links */
5315 break;
5316 case 2:
5317 info->mso_stream_count = 4; /* 4 links */
5318 break;
5319 }
5320
5321 if (!info->mso_stream_count) {
5322 info->mso_pixel_overlap = 0;
5323 return;
5324 }
5325
5326 info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
5327 if (info->mso_pixel_overlap > 8) {
5328 drm_dbg_kms(connector->dev, "Reserved MSO pixel overlap value %u\n",
5329 info->mso_pixel_overlap);
5330 info->mso_pixel_overlap = 8;
5331 }
5332
5333 drm_dbg_kms(connector->dev, "MSO stream count %u, pixel overlap %u\n",
5334 info->mso_stream_count, info->mso_pixel_overlap);
5335}
5336
5337static void drm_update_mso(struct drm_connector *connector, const struct edid *edid)
5338{
5339 const struct displayid_block *block;
5340 struct displayid_iter iter;
5341
5342 displayid_iter_edid_begin(edid, &iter);
5343 displayid_iter_for_each(block, &iter) {
5344 if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC)
5345 drm_parse_vesa_mso_data(connector, block);
5346 }
5347 displayid_iter_end(&iter);
5348}
5349
170178fe
KP		 5350/* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
5351 * all of the values which would have been set from EDID
5352 */
5353void
5354drm_reset_display_info(struct drm_connector *connector)
5355{
5356 struct drm_display_info *info = &connector->display_info;
5357
5358 info->width_mm = 0;
5359 info->height_mm = 0;
5360
5361 info->bpc = 0;
5362 info->color_formats = 0;
5363 info->cea_rev = 0;
5364 info->max_tmds_clock = 0;
5365 info->dvi_dual = false;
a92d083d 5366 info->is_hdmi = false;
170178fe 5367 info->has_hdmi_infoframe = false;
1581b2df 5368 info->rgb_quant_range_selectable = false;
1f6b8eef 5369 memset(&info->hdmi, 0, sizeof(info->hdmi));
170178fe 5370
70c0b80d
MR		 5371 info->edid_hdmi_rgb444_dc_modes = 0;
5372 info->edid_hdmi_ycbcr444_dc_modes = 0;
5373
170178fe 5374 info->non_desktop = 0;
a1d11d1e 5375 memset(&info->monitor_range, 0, sizeof(info->monitor_range));
18a9cbbe
JN		 5376
5377 info->mso_stream_count = 0;
5378 info->mso_pixel_overlap = 0;
170178fe 5379}
170178fe
KP		 5380
5381u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid)
3b11228b 5382{
1826750f 5383 struct drm_display_info *info = &connector->display_info;
ebec9a7b 5384
170178fe
KP		 5385 u32 quirks = edid_get_quirks(edid);
5386
1f6b8eef
VS		 5387 drm_reset_display_info(connector);
5388
3b11228b
JB		 5389 info->width_mm = edid->width_cm * 10;
5390 info->height_mm = edid->height_cm * 10;
5391
a1d11d1e
MN		 5392 drm_get_monitor_range(connector, edid);
5393
a988bc72 5394 if (edid->revision < 3)
ce99534e 5395 goto out;
3b11228b
JB		 5396
5397 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
ce99534e 5398 goto out;
3b11228b 5399
1cea146a 5400 drm_parse_cea_ext(connector, edid);
d0c94692 5401
210a021d
MK		 5402 /*
5403 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
5404 *
5405 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
5406 * tells us to assume 8 bpc color depth if the EDID doesn't have
5407 * extensions which tell otherwise.
5408 */
3bde449f
VS		 5409 if (info->bpc == 0 && edid->revision == 3 &&
5410 edid->input & DRM_EDID_DIGITAL_DFP_1_X) {
210a021d
MK		 5411 info->bpc = 8;
5412 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
5413 connector->name, info->bpc);
5414 }
5415
a988bc72
LPC		 5416 /* Only defined for 1.4 with digital displays */
5417 if (edid->revision < 4)
ce99534e 5418 goto out;
a988bc72 5419
3b11228b
JB		 5420 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
5421 case DRM_EDID_DIGITAL_DEPTH_6:
5422 info->bpc = 6;
5423 break;
5424 case DRM_EDID_DIGITAL_DEPTH_8:
5425 info->bpc = 8;
5426 break;
5427 case DRM_EDID_DIGITAL_DEPTH_10:
5428 info->bpc = 10;
5429 break;
5430 case DRM_EDID_DIGITAL_DEPTH_12:
5431 info->bpc = 12;
5432 break;
5433 case DRM_EDID_DIGITAL_DEPTH_14:
5434 info->bpc = 14;
5435 break;
5436 case DRM_EDID_DIGITAL_DEPTH_16:
5437 info->bpc = 16;
5438 break;
5439 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
5440 default:
5441 info->bpc = 0;
5442 break;
5443 }
da05a5a7 5444
d0c94692 5445 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
25933820 5446 connector->name, info->bpc);
d0c94692 5447
a988bc72 5448 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
ee58808d 5449 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
c03d0b52 5450 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
ee58808d 5451 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
c03d0b52 5452 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
18a9cbbe
JN		 5453
5454 drm_update_mso(connector, edid);
5455
ce99534e
JN		 5456out:
5457 if (quirks & EDID_QUIRK_NON_DESKTOP) {
5458 drm_dbg_kms(connector->dev, "Non-desktop display%s\n",
5459 info->non_desktop ? " (redundant quirk)" : "");
5460 info->non_desktop = true;
5461 }
5462
170178fe 5463 return quirks;
3b11228b
JB		 5464}
5465
a39ed680 5466static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
80ecb5d7
YB		 5467 struct displayid_detailed_timings_1 *timings,
5468 bool type_7)
a39ed680
DA		 5469{
5470 struct drm_display_mode *mode;
5471 unsigned pixel_clock = (timings->pixel_clock[0] |
5472 (timings->pixel_clock[1] << 8) |
6292b8ef 5473 (timings->pixel_clock[2] << 16)) + 1;
a39ed680
DA		 5474 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
5475 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
5476 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
5477 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
5478 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
5479 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
5480 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
5481 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
5482 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
5483 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
948de842 5484
a39ed680
DA		 5485 mode = drm_mode_create(dev);
5486 if (!mode)
5487 return NULL;
5488
80ecb5d7
YB		 5489 /* resolution is kHz for type VII, and 10 kHz for type I */
5490 mode->clock = type_7 ? pixel_clock : pixel_clock * 10;
a39ed680
DA		 5491 mode->hdisplay = hactive;
5492 mode->hsync_start = mode->hdisplay + hsync;
5493 mode->hsync_end = mode->hsync_start + hsync_width;
5494 mode->htotal = mode->hdisplay + hblank;
5495
5496 mode->vdisplay = vactive;
5497 mode->vsync_start = mode->vdisplay + vsync;
5498 mode->vsync_end = mode->vsync_start + vsync_width;
5499 mode->vtotal = mode->vdisplay + vblank;
5500
5501 mode->flags = 0;
5502 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
5503 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
5504 mode->type = DRM_MODE_TYPE_DRIVER;
5505
5506 if (timings->flags & 0x80)
5507 mode->type |= DRM_MODE_TYPE_PREFERRED;
a39ed680
DA		 5508 drm_mode_set_name(mode);
5509
5510 return mode;
5511}
5512
5513static int add_displayid_detailed_1_modes(struct drm_connector *connector,
43d16d84 5514 const struct displayid_block *block)
a39ed680
DA		 5515{
5516 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
5517 int i;
5518 int num_timings;
5519 struct drm_display_mode *newmode;
5520 int num_modes = 0;
80ecb5d7 5521 bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING;
a39ed680
DA		 5522 /* blocks must be multiple of 20 bytes length */
5523 if (block->num_bytes % 20)
5524 return 0;
5525
5526 num_timings = block->num_bytes / 20;
5527 for (i = 0; i < num_timings; i++) {
5528 struct displayid_detailed_timings_1 *timings = &det->timings[i];
5529
80ecb5d7 5530 newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7);
a39ed680
DA		 5531 if (!newmode)
5532 continue;
5533
5534 drm_mode_probed_add(connector, newmode);
5535 num_modes++;
5536 }
5537 return num_modes;
5538}
5539
5540static int add_displayid_detailed_modes(struct drm_connector *connector,
5541 struct edid *edid)
5542{
43d16d84 5543 const struct displayid_block *block;
5ef88dc5 5544 struct displayid_iter iter;
a39ed680
DA		 5545 int num_modes = 0;
5546
5ef88dc5
JN		 5547 displayid_iter_edid_begin(edid, &iter);
5548 displayid_iter_for_each(block, &iter) {
80ecb5d7
YB		 5549 if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING ||
5550 block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING)
5ef88dc5 5551 num_modes += add_displayid_detailed_1_modes(connector, block);
a39ed680 5552 }
5ef88dc5 5553 displayid_iter_end(&iter);
7f261afd 5554
a39ed680
DA		 5555 return num_modes;
5556}
5557
f453ba04
DA		 5558/**
5559 * drm_add_edid_modes - add modes from EDID data, if available
5560 * @connector: connector we're probing
db6cf833 5561 * @edid: EDID data
f453ba04 5562 *
b3c6c8bf 5563 * Add the specified modes to the connector's mode list. Also fills out the
c945b8c1
JN		 5564 * &drm_display_info structure and ELD in @connector with any information which
5565 * can be derived from the edid.
f453ba04 5566 *
db6cf833 5567 * Return: The number of modes added or 0 if we couldn't find any.
f453ba04
DA		 5568 */
5569int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
5570{
5571 int num_modes = 0;
5572 u32 quirks;
5573
5574 if (edid == NULL) {
c945b8c1 5575 clear_eld(connector);
f453ba04
DA		 5576 return 0;
5577 }
3c537889 5578 if (!drm_edid_is_valid(edid)) {
c945b8c1 5579 clear_eld(connector);
6d45fff5 5580 drm_warn(connector->dev, "%s: EDID invalid.\n",
25933820 5581 connector->name);
f453ba04
DA		 5582 return 0;
5583 }
5584
c945b8c1
JN		 5585 drm_edid_to_eld(connector, edid);
5586
0f0f8708
SS		 5587 /*
5588 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
5589 * To avoid multiple parsing of same block, lets parse that map
5590 * from sink info, before parsing CEA modes.
5591 */
170178fe 5592 quirks = drm_add_display_info(connector, edid);
0f0f8708 5593
c867df70
AJ		 5594 /*
5595 * EDID spec says modes should be preferred in this order:
5596 * - preferred detailed mode
5597 * - other detailed modes from base block
5598 * - detailed modes from extension blocks
5599 * - CVT 3-byte code modes
5600 * - standard timing codes
5601 * - established timing codes
5602 * - modes inferred from GTF or CVT range information
5603 *
13931579 5604 * We get this pretty much right.
c867df70
AJ		 5605 *
5606 * XXX order for additional mode types in extension blocks?
5607 */
13931579
AJ		 5608 num_modes += add_detailed_modes(connector, edid, quirks);
5609 num_modes += add_cvt_modes(connector, edid);
c867df70
AJ		 5610 num_modes += add_standard_modes(connector, edid);
5611 num_modes += add_established_modes(connector, edid);
54ac76f8 5612 num_modes += add_cea_modes(connector, edid);
e6e79209 5613 num_modes += add_alternate_cea_modes(connector, edid);
a39ed680 5614 num_modes += add_displayid_detailed_modes(connector, edid);
4d53dc0c
VS		 5615 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
5616 num_modes += add_inferred_modes(connector, edid);
f453ba04
DA		 5617
5618 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
5619 edid_fixup_preferred(connector, quirks);
5620
e10aec65
MK		 5621 if (quirks & EDID_QUIRK_FORCE_6BPC)
5622 connector->display_info.bpc = 6;
5623
49d45a31
RM		 5624 if (quirks & EDID_QUIRK_FORCE_8BPC)
5625 connector->display_info.bpc = 8;
5626
e345da82
MK		 5627 if (quirks & EDID_QUIRK_FORCE_10BPC)
5628 connector->display_info.bpc = 10;
5629
bc5b9641
MK		 5630 if (quirks & EDID_QUIRK_FORCE_12BPC)
5631 connector->display_info.bpc = 12;
5632
f453ba04
DA		 5633 return num_modes;
5634}
5635EXPORT_SYMBOL(drm_add_edid_modes);
f0fda0a4
ZY		 5636
5637/**
5638 * drm_add_modes_noedid - add modes for the connectors without EDID
5639 * @connector: connector we're probing
5640 * @hdisplay: the horizontal display limit
5641 * @vdisplay: the vertical display limit
5642 *
5643 * Add the specified modes to the connector's mode list. Only when the
5644 * hdisplay/vdisplay is not beyond the given limit, it will be added.
5645 *
db6cf833 5646 * Return: The number of modes added or 0 if we couldn't find any.
f0fda0a4
ZY		 5647 */
5648int drm_add_modes_noedid(struct drm_connector *connector,
5649 int hdisplay, int vdisplay)
5650{
5651 int i, count, num_modes = 0;
b1f559ec 5652 struct drm_display_mode *mode;
f0fda0a4
ZY		 5653 struct drm_device *dev = connector->dev;
5654
fbb40b28 5655 count = ARRAY_SIZE(drm_dmt_modes);
f0fda0a4
ZY		 5656 if (hdisplay < 0)
5657 hdisplay = 0;
5658 if (vdisplay < 0)
5659 vdisplay = 0;
5660
5661 for (i = 0; i < count; i++) {
b1f559ec 5662 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
948de842 5663
f0fda0a4
ZY		 5664 if (hdisplay && vdisplay) {
5665 /*
5666 * Only when two are valid, they will be used to check
5667 * whether the mode should be added to the mode list of
5668 * the connector.
5669 */
5670 if (ptr->hdisplay > hdisplay ||
5671 ptr->vdisplay > vdisplay)
5672 continue;
5673 }
f985dedb
AJ		 5674 if (drm_mode_vrefresh(ptr) > 61)
5675 continue;
f0fda0a4
ZY		 5676 mode = drm_mode_duplicate(dev, ptr);
5677 if (mode) {
5678 drm_mode_probed_add(connector, mode);
5679 num_modes++;
5680 }
5681 }
5682 return num_modes;
5683}
5684EXPORT_SYMBOL(drm_add_modes_noedid);
10a85120 5685
db6cf833
TR		 5686/**
5687 * drm_set_preferred_mode - Sets the preferred mode of a connector
5688 * @connector: connector whose mode list should be processed
5689 * @hpref: horizontal resolution of preferred mode
5690 * @vpref: vertical resolution of preferred mode
5691 *
5692 * Marks a mode as preferred if it matches the resolution specified by @hpref
5693 * and @vpref.
5694 */
3cf70daf
GH		 5695void drm_set_preferred_mode(struct drm_connector *connector,
5696 int hpref, int vpref)
5697{
5698 struct drm_display_mode *mode;
5699
5700 list_for_each_entry(mode, &connector->probed_modes, head) {
db6cf833 5701 if (mode->hdisplay == hpref &&
9d3de138 5702 mode->vdisplay == vpref)
3cf70daf
GH		 5703 mode->type |= DRM_MODE_TYPE_PREFERRED;
5704 }
5705}
5706EXPORT_SYMBOL(drm_set_preferred_mode);
5707
192a3aa0 5708static bool is_hdmi2_sink(const struct drm_connector *connector)
13d0add3
VS		 5709{
5710 /*
5711 * FIXME: sil-sii8620 doesn't have a connector around when
5712 * we need one, so we have to be prepared for a NULL connector.
5713 */
5714 if (!connector)
5715 return true;
5716
5717 return connector->display_info.hdmi.scdc.supported ||
c03d0b52 5718 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR420;
13d0add3
VS		 5719}
5720
2cdbfd66
US		 5721static inline bool is_eotf_supported(u8 output_eotf, u8 sink_eotf)
5722{
5723 return sink_eotf & BIT(output_eotf);
5724}
5725
5726/**
5727 * drm_hdmi_infoframe_set_hdr_metadata() - fill an HDMI DRM infoframe with
5728 * HDR metadata from userspace
5729 * @frame: HDMI DRM infoframe
6ac98829 5730 * @conn_state: Connector state containing HDR metadata
2cdbfd66
US		 5731 *
5732 * Return: 0 on success or a negative error code on failure.
5733 */
5734int
5735drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame,
5736 const struct drm_connector_state *conn_state)
5737{
5738 struct drm_connector *connector;
5739 struct hdr_output_metadata *hdr_metadata;
5740 int err;
5741
5742 if (!frame || !conn_state)
5743 return -EINVAL;
5744
5745 connector = conn_state->connector;
5746
5747 if (!conn_state->hdr_output_metadata)
5748 return -EINVAL;
5749
5750 hdr_metadata = conn_state->hdr_output_metadata->data;
5751
5752 if (!hdr_metadata || !connector)
5753 return -EINVAL;
5754
5755 /* Sink EOTF is Bit map while infoframe is absolute values */
5756 if (!is_eotf_supported(hdr_metadata->hdmi_metadata_type1.eotf,
5757 connector->hdr_sink_metadata.hdmi_type1.eotf)) {
5758 DRM_DEBUG_KMS("EOTF Not Supported\n");
5759 return -EINVAL;
5760 }
5761
5762 err = hdmi_drm_infoframe_init(frame);
5763 if (err < 0)
5764 return err;
5765
5766 frame->eotf = hdr_metadata->hdmi_metadata_type1.eotf;
5767 frame->metadata_type = hdr_metadata->hdmi_metadata_type1.metadata_type;
5768
5769 BUILD_BUG_ON(sizeof(frame->display_primaries) !=
5770 sizeof(hdr_metadata->hdmi_metadata_type1.display_primaries));
5771 BUILD_BUG_ON(sizeof(frame->white_point) !=
5772 sizeof(hdr_metadata->hdmi_metadata_type1.white_point));
5773
5774 memcpy(&frame->display_primaries,
5775 &hdr_metadata->hdmi_metadata_type1.display_primaries,
5776 sizeof(frame->display_primaries));
5777
5778 memcpy(&frame->white_point,
5779 &hdr_metadata->hdmi_metadata_type1.white_point,
5780 sizeof(frame->white_point));
5781
5782 frame->max_display_mastering_luminance =
5783 hdr_metadata->hdmi_metadata_type1.max_display_mastering_luminance;
5784 frame->min_display_mastering_luminance =
5785 hdr_metadata->hdmi_metadata_type1.min_display_mastering_luminance;
5786 frame->max_fall = hdr_metadata->hdmi_metadata_type1.max_fall;
5787 frame->max_cll = hdr_metadata->hdmi_metadata_type1.max_cll;
5788
5789 return 0;
5790}
5791EXPORT_SYMBOL(drm_hdmi_infoframe_set_hdr_metadata);
5792
192a3aa0 5793static u8 drm_mode_hdmi_vic(const struct drm_connector *connector,
949561eb
VS		 5794 const struct drm_display_mode *mode)
5795{
5796 bool has_hdmi_infoframe = connector ?
5797 connector->display_info.has_hdmi_infoframe : false;
5798
5799 if (!has_hdmi_infoframe)
5800 return 0;
5801
5802 /* No HDMI VIC when signalling 3D video format */
5803 if (mode->flags & DRM_MODE_FLAG_3D_MASK)
5804 return 0;
5805
5806 return drm_match_hdmi_mode(mode);
5807}
5808
192a3aa0 5809static u8 drm_mode_cea_vic(const struct drm_connector *connector,
cfd6f8c3
VS		 5810 const struct drm_display_mode *mode)
5811{
cfd6f8c3
VS		 5812 u8 vic;
5813
5814 /*
5815 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
5816 * we should send its VIC in vendor infoframes, else send the
5817 * VIC in AVI infoframes. Lets check if this mode is present in
5818 * HDMI 1.4b 4K modes
5819 */
949561eb 5820 if (drm_mode_hdmi_vic(connector, mode))
cfd6f8c3
VS		 5821 return 0;
5822
5823 vic = drm_match_cea_mode(mode);
5824
5825 /*
5826 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
5827 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
5828 * have to make sure we dont break HDMI 1.4 sinks.
5829 */
5830 if (!is_hdmi2_sink(connector) && vic > 64)
5831 return 0;
5832
5833 return vic;
5834}
5835
10a85120
TR		 5836/**
5837 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
5838 * data from a DRM display mode
5839 * @frame: HDMI AVI infoframe
13d0add3 5840 * @connector: the connector
10a85120
TR		 5841 * @mode: DRM display mode
5842 *
db6cf833 5843 * Return: 0 on success or a negative error code on failure.
10a85120
TR		 5844 */
5845int
5846drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
192a3aa0 5847 const struct drm_connector *connector,
13d0add3 5848 const struct drm_display_mode *mode)
10a85120 5849{
a9c266c2 5850 enum hdmi_picture_aspect picture_aspect;
d2b43473 5851 u8 vic, hdmi_vic;
10a85120
TR		 5852
5853 if (!frame || !mode)
5854 return -EINVAL;
5855
5ee0caf1 5856 hdmi_avi_infoframe_init(frame);
10a85120 5857
bf02db99
DL		 5858 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
5859 frame->pixel_repeat = 1;
5860
d2b43473
WL		 5861 vic = drm_mode_cea_vic(connector, mode);
5862 hdmi_vic = drm_mode_hdmi_vic(connector, mode);
0c1f528c 5863
10a85120 5864 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
0967e6a5 5865
50525c33
SL		 5866 /*
5867 * As some drivers don't support atomic, we can't use connector state.
5868 * So just initialize the frame with default values, just the same way
5869 * as it's done with other properties here.
5870 */
5871 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
5872 frame->itc = 0;
5873
69ab6d35
VK		 5874 /*
5875 * Populate picture aspect ratio from either
d2b43473 5876 * user input (if specified) or from the CEA/HDMI mode lists.
69ab6d35 5877 */
a9c266c2 5878 picture_aspect = mode->picture_aspect_ratio;
d2b43473
WL		 5879 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) {
5880 if (vic)
5881 picture_aspect = drm_get_cea_aspect_ratio(vic);
5882 else if (hdmi_vic)
5883 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic);
5884 }
0967e6a5 5885
a9c266c2
VS		 5886 /*
5887 * The infoframe can't convey anything but none, 4:3
5888 * and 16:9, so if the user has asked for anything else
5889 * we can only satisfy it by specifying the right VIC.
5890 */
5891 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
d2b43473
WL		 5892 if (vic) {
5893 if (picture_aspect != drm_get_cea_aspect_ratio(vic))
5894 return -EINVAL;
5895 } else if (hdmi_vic) {
5896 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic))
5897 return -EINVAL;
5898 } else {
a9c266c2 5899 return -EINVAL;
d2b43473
WL		 5900 }
5901
a9c266c2
VS		 5902 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
5903 }
5904
d2b43473 5905 frame->video_code = vic;
a9c266c2 5906 frame->picture_aspect = picture_aspect;
10a85120 5907 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
24d01805 5908 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
10a85120
TR		 5909
5910 return 0;
5911}
5912EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
83dd0008 5913
0d68b887
US		 5914/* HDMI Colorspace Spec Definitions */
5915#define FULL_COLORIMETRY_MASK 0x1FF
5916#define NORMAL_COLORIMETRY_MASK 0x3
5917#define EXTENDED_COLORIMETRY_MASK 0x7
5918#define EXTENDED_ACE_COLORIMETRY_MASK 0xF
5919
5920#define C(x) ((x) << 0)
5921#define EC(x) ((x) << 2)
5922#define ACE(x) ((x) << 5)
5923
5924#define HDMI_COLORIMETRY_NO_DATA 0x0
5925#define HDMI_COLORIMETRY_SMPTE_170M_YCC (C(1) | EC(0) | ACE(0))
5926#define HDMI_COLORIMETRY_BT709_YCC (C(2) | EC(0) | ACE(0))
5927#define HDMI_COLORIMETRY_XVYCC_601 (C(3) | EC(0) | ACE(0))
5928#define HDMI_COLORIMETRY_XVYCC_709 (C(3) | EC(1) | ACE(0))
5929#define HDMI_COLORIMETRY_SYCC_601 (C(3) | EC(2) | ACE(0))
5930#define HDMI_COLORIMETRY_OPYCC_601 (C(3) | EC(3) | ACE(0))
5931#define HDMI_COLORIMETRY_OPRGB (C(3) | EC(4) | ACE(0))
5932#define HDMI_COLORIMETRY_BT2020_CYCC (C(3) | EC(5) | ACE(0))
5933#define HDMI_COLORIMETRY_BT2020_RGB (C(3) | EC(6) | ACE(0))
5934#define HDMI_COLORIMETRY_BT2020_YCC (C(3) | EC(6) | ACE(0))
5935#define HDMI_COLORIMETRY_DCI_P3_RGB_D65 (C(3) | EC(7) | ACE(0))
5936#define HDMI_COLORIMETRY_DCI_P3_RGB_THEATER (C(3) | EC(7) | ACE(1))
5937
5938static const u32 hdmi_colorimetry_val[] = {
5939 [DRM_MODE_COLORIMETRY_NO_DATA] = HDMI_COLORIMETRY_NO_DATA,
5940 [DRM_MODE_COLORIMETRY_SMPTE_170M_YCC] = HDMI_COLORIMETRY_SMPTE_170M_YCC,
5941 [DRM_MODE_COLORIMETRY_BT709_YCC] = HDMI_COLORIMETRY_BT709_YCC,
5942 [DRM_MODE_COLORIMETRY_XVYCC_601] = HDMI_COLORIMETRY_XVYCC_601,
5943 [DRM_MODE_COLORIMETRY_XVYCC_709] = HDMI_COLORIMETRY_XVYCC_709,
5944 [DRM_MODE_COLORIMETRY_SYCC_601] = HDMI_COLORIMETRY_SYCC_601,
5945 [DRM_MODE_COLORIMETRY_OPYCC_601] = HDMI_COLORIMETRY_OPYCC_601,
5946 [DRM_MODE_COLORIMETRY_OPRGB] = HDMI_COLORIMETRY_OPRGB,
5947 [DRM_MODE_COLORIMETRY_BT2020_CYCC] = HDMI_COLORIMETRY_BT2020_CYCC,
5948 [DRM_MODE_COLORIMETRY_BT2020_RGB] = HDMI_COLORIMETRY_BT2020_RGB,
5949 [DRM_MODE_COLORIMETRY_BT2020_YCC] = HDMI_COLORIMETRY_BT2020_YCC,
5950};
5951
5952#undef C
5953#undef EC
5954#undef ACE
5955
5956/**
4a46e5d2
MR		 5957 * drm_hdmi_avi_infoframe_colorimetry() - fill the HDMI AVI infoframe
5958 * colorimetry information
0d68b887
US		 5959 * @frame: HDMI AVI infoframe
5960 * @conn_state: connector state
5961 */
5962void
4a46e5d2 5963drm_hdmi_avi_infoframe_colorimetry(struct hdmi_avi_infoframe *frame,
0d68b887
US		 5964 const struct drm_connector_state *conn_state)
5965{
5966 u32 colorimetry_val;
5967 u32 colorimetry_index = conn_state->colorspace & FULL_COLORIMETRY_MASK;
5968
5969 if (colorimetry_index >= ARRAY_SIZE(hdmi_colorimetry_val))
5970 colorimetry_val = HDMI_COLORIMETRY_NO_DATA;
5971 else
5972 colorimetry_val = hdmi_colorimetry_val[colorimetry_index];
5973
5974 frame->colorimetry = colorimetry_val & NORMAL_COLORIMETRY_MASK;
5975 /*
5976 * ToDo: Extend it for ACE formats as well. Modify the infoframe
5977 * structure and extend it in drivers/video/hdmi
5978 */
5979 frame->extended_colorimetry = (colorimetry_val >> 2) &
5980 EXTENDED_COLORIMETRY_MASK;
5981}
4a46e5d2 5982EXPORT_SYMBOL(drm_hdmi_avi_infoframe_colorimetry);
0d68b887 5983
a2ce26f8
VS		 5984/**
5985 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
5986 * quantization range information
5987 * @frame: HDMI AVI infoframe
13d0add3 5988 * @connector: the connector
779c4c28 5989 * @mode: DRM display mode
a2ce26f8 5990 * @rgb_quant_range: RGB quantization range (Q)
a2ce26f8
VS		 5991 */
5992void
5993drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
192a3aa0 5994 const struct drm_connector *connector,
779c4c28 5995 const struct drm_display_mode *mode,
1581b2df 5996 enum hdmi_quantization_range rgb_quant_range)
a2ce26f8 5997{
1581b2df
VS		 5998 const struct drm_display_info *info = &connector->display_info;
5999
a2ce26f8
VS		 6000 /*
6001 * CEA-861:
6002 * "A Source shall not send a non-zero Q value that does not correspond
6003 * to the default RGB Quantization Range for the transmitted Picture
6004 * unless the Sink indicates support for the Q bit in a Video
6005 * Capabilities Data Block."
779c4c28
VS		 6006 *
6007 * HDMI 2.0 recommends sending non-zero Q when it does match the
6008 * default RGB quantization range for the mode, even when QS=0.
a2ce26f8 6009 */
1581b2df 6010 if (info->rgb_quant_range_selectable ||
779c4c28 6011 rgb_quant_range == drm_default_rgb_quant_range(mode))
a2ce26f8
VS		 6012 frame->quantization_range = rgb_quant_range;
6013 else
6014 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
fcc8a22c
VS		 6015
6016 /*
6017 * CEA-861-F:
6018 * "When transmitting any RGB colorimetry, the Source should set the
6019 * YQ-field to match the RGB Quantization Range being transmitted
6020 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
6021 * set YQ=1) and the Sink shall ignore the YQ-field."
9271c0ca
VS		 6022 *
6023 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
6024 * by non-zero YQ when receiving RGB. There doesn't seem to be any
6025 * good way to tell which version of CEA-861 the sink supports, so
6026 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
6027 * on on CEA-861-F.
fcc8a22c 6028 */
13d0add3 6029 if (!is_hdmi2_sink(connector) ||
9271c0ca 6030 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
fcc8a22c
VS		 6031 frame->ycc_quantization_range =
6032 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
6033 else
6034 frame->ycc_quantization_range =
6035 HDMI_YCC_QUANTIZATION_RANGE_FULL;
a2ce26f8
VS		 6036}
6037EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
6038
076d9a5d
VS		 6039/**
6040 * drm_hdmi_avi_infoframe_bars() - fill the HDMI AVI infoframe
6041 * bar information
6042 * @frame: HDMI AVI infoframe
6043 * @conn_state: connector state
6044 */
6045void
6046drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe *frame,
6047 const struct drm_connector_state *conn_state)
6048{
6049 frame->right_bar = conn_state->tv.margins.right;
6050 frame->left_bar = conn_state->tv.margins.left;
6051 frame->top_bar = conn_state->tv.margins.top;
6052 frame->bottom_bar = conn_state->tv.margins.bottom;
6053}
6054EXPORT_SYMBOL(drm_hdmi_avi_infoframe_bars);
6055
4eed4a0a
DL		 6056static enum hdmi_3d_structure
6057s3d_structure_from_display_mode(const struct drm_display_mode *mode)
6058{
6059 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
6060
6061 switch (layout) {
6062 case DRM_MODE_FLAG_3D_FRAME_PACKING:
6063 return HDMI_3D_STRUCTURE_FRAME_PACKING;
6064 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
6065 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
6066 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
6067 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
6068 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
6069 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
6070 case DRM_MODE_FLAG_3D_L_DEPTH:
6071 return HDMI_3D_STRUCTURE_L_DEPTH;
6072 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
6073 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
6074 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
6075 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
6076 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
6077 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
6078 default:
6079 return HDMI_3D_STRUCTURE_INVALID;
6080 }
6081}
6082
83dd0008
LD		 6083/**
6084 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
6085 * data from a DRM display mode
6086 * @frame: HDMI vendor infoframe
f1781e9b 6087 * @connector: the connector
83dd0008
LD		 6088 * @mode: DRM display mode
6089 *
6090 * Note that there's is a need to send HDMI vendor infoframes only when using a
6091 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
6092 * function will return -EINVAL, error that can be safely ignored.
6093 *
db6cf833 6094 * Return: 0 on success or a negative error code on failure.
83dd0008
LD		 6095 */
6096int
6097drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
192a3aa0 6098 const struct drm_connector *connector,
83dd0008
LD		 6099 const struct drm_display_mode *mode)
6100{
f1781e9b
VS		 6101 /*
6102 * FIXME: sil-sii8620 doesn't have a connector around when
6103 * we need one, so we have to be prepared for a NULL connector.
6104 */
6105 bool has_hdmi_infoframe = connector ?
6106 connector->display_info.has_hdmi_infoframe : false;
83dd0008 6107 int err;
83dd0008
LD		 6108
6109 if (!frame || !mode)
6110 return -EINVAL;
6111
f1781e9b
VS		 6112 if (!has_hdmi_infoframe)
6113 return -EINVAL;
6114
949561eb
VS		 6115 err = hdmi_vendor_infoframe_init(frame);
6116 if (err < 0)
6117 return err;
4eed4a0a 6118
f1781e9b
VS		 6119 /*
6120 * Even if it's not absolutely necessary to send the infoframe
6121 * (ie.vic==0 and s3d_struct==0) we will still send it if we
6122 * know that the sink can handle it. This is based on a
6123 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
0ae865ef 6124 * have trouble realizing that they should switch from 3D to 2D
f1781e9b
VS		 6125 * mode if the source simply stops sending the infoframe when
6126 * it wants to switch from 3D to 2D.
6127 */
949561eb 6128 frame->vic = drm_mode_hdmi_vic(connector, mode);
f1781e9b 6129 frame->s3d_struct = s3d_structure_from_display_mode(mode);
83dd0008
LD		 6130
6131 return 0;
6132}
6133EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
40d9b043 6134
7f261afd
VS		 6135static void drm_parse_tiled_block(struct drm_connector *connector,
6136 const struct displayid_block *block)
5e546cd5 6137{
092c367a 6138 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
5e546cd5
DA		 6139 u16 w, h;
6140 u8 tile_v_loc, tile_h_loc;
6141 u8 num_v_tile, num_h_tile;
6142 struct drm_tile_group *tg;
6143
6144 w = tile->tile_size[0] | tile->tile_size[1] << 8;
6145 h = tile->tile_size[2] | tile->tile_size[3] << 8;
6146
6147 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
6148 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
6149 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
6150 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
6151
6152 connector->has_tile = true;
6153 if (tile->tile_cap & 0x80)
6154 connector->tile_is_single_monitor = true;
6155
6156 connector->num_h_tile = num_h_tile + 1;
6157 connector->num_v_tile = num_v_tile + 1;
6158 connector->tile_h_loc = tile_h_loc;
6159 connector->tile_v_loc = tile_v_loc;
6160 connector->tile_h_size = w + 1;
6161 connector->tile_v_size = h + 1;
6162
6163 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
6164 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
6165 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
6166 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
6167 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
6168
6169 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
392f9fcb 6170 if (!tg)
5e546cd5 6171 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
5e546cd5 6172 if (!tg)
7f261afd 6173 return;
5e546cd5
DA		 6174
6175 if (connector->tile_group != tg) {
6176 /* if we haven't got a pointer,
6177 take the reference, drop ref to old tile group */
392f9fcb 6178 if (connector->tile_group)
5e546cd5 6179 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5e546cd5 6180 connector->tile_group = tg;
392f9fcb 6181 } else {
5e546cd5
DA		 6182 /* if same tile group, then release the ref we just took. */
6183 drm_mode_put_tile_group(connector->dev, tg);
392f9fcb 6184 }
5e546cd5
DA		 6185}
6186
092c367a
VS		 6187void drm_update_tile_info(struct drm_connector *connector,
6188 const struct edid *edid)
40d9b043 6189{
bfd4e192
JN		 6190 const struct displayid_block *block;
6191 struct displayid_iter iter;
36881184 6192
40d9b043 6193 connector->has_tile = false;
7f261afd 6194
bfd4e192
JN		 6195 displayid_iter_edid_begin(edid, &iter);
6196 displayid_iter_for_each(block, &iter) {
6197 if (block->tag == DATA_BLOCK_TILED_DISPLAY)
6198 drm_parse_tiled_block(connector, block);
40d9b043 6199 }
bfd4e192 6200 displayid_iter_end(&iter);
40d9b043 6201
7f261afd 6202 if (!connector->has_tile && connector->tile_group) {
40d9b043
DA		 6203 drm_mode_put_tile_group(connector->dev, connector->tile_group);
6204 connector->tile_group = NULL;
6205 }
40d9b043 6206}
Linux 6.x block layer and io_uring tree(s)