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drm/edid: use a temp variable for sads to drop one level of dereferences
[linux-2.6-block.git] / drivers / gpu / drm / drm_edid.c
CommitLineData
f453ba04
DA		 1/*
2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
61e57a8d 5 * Copyright 2010 Red Hat, Inc.
f453ba04
DA		 6 *
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
8 * FB layer.
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 */
9c79edec 30
18a9cbbe 31#include <linux/bitfield.h>
82b599ec 32#include <linux/cec.h>
10a85120 33#include <linux/hdmi.h>
f453ba04 34#include <linux/i2c.h>
9c79edec 35#include <linux/kernel.h>
47819ba2 36#include <linux/module.h>
36b73b05 37#include <linux/pci.h>
9c79edec 38#include <linux/slab.h>
5cb8eaa2 39#include <linux/vga_switcheroo.h>
9c79edec
JN		 40
41#include <drm/drm_displayid.h>
42#include <drm/drm_drv.h>
760285e7 43#include <drm/drm_edid.h>
439590ac 44#include <drm/drm_eld.h>
9338203c 45#include <drm/drm_encoder.h>
9c79edec 46#include <drm/drm_print.h>
f453ba04 47
969218fe
TI		 48#include "drm_crtc_internal.h"
49
37eab1fe
JN		 50static int oui(u8 first, u8 second, u8 third)
51{
52 return (first << 16) | (second << 8) | third;
53}
54
d1ff6409
AJ		 55#define EDID_EST_TIMINGS 16
56#define EDID_STD_TIMINGS 8
57#define EDID_DETAILED_TIMINGS 4
f453ba04
DA		 58
59/*
60 * EDID blocks out in the wild have a variety of bugs, try to collect
61 * them here (note that userspace may work around broken monitors first,
62 * but fixes should make their way here so that the kernel "just works"
63 * on as many displays as possible).
64 */
65
66/* First detailed mode wrong, use largest 60Hz mode */
67#define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
68/* Reported 135MHz pixel clock is too high, needs adjustment */
69#define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
70/* Prefer the largest mode at 75 Hz */
71#define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
72/* Detail timing is in cm not mm */
73#define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
74/* Detailed timing descriptors have bogus size values, so just take the
75 * maximum size and use that.
76 */
77#define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
f453ba04
DA		 78/* use +hsync +vsync for detailed mode */
79#define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
bc42aabc
AJ		 80/* Force reduced-blanking timings for detailed modes */
81#define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
49d45a31
RM		 82/* Force 8bpc */
83#define EDID_QUIRK_FORCE_8BPC (1 << 8)
bc5b9641
MK		 84/* Force 12bpc */
85#define EDID_QUIRK_FORCE_12BPC (1 << 9)
e10aec65
MK		 86/* Force 6bpc */
87#define EDID_QUIRK_FORCE_6BPC (1 << 10)
e345da82
MK		 88/* Force 10bpc */
89#define EDID_QUIRK_FORCE_10BPC (1 << 11)
66660d4c
DA		 90/* Non desktop display (i.e. HMD) */
91#define EDID_QUIRK_NON_DESKTOP (1 << 12)
aa193f7e
HM		 92/* Cap the DSC target bitrate to 15bpp */
93#define EDID_QUIRK_CAP_DSC_15BPP (1 << 13)
3c537889 94
2869f599
PZ		 95#define MICROSOFT_IEEE_OUI 0xca125c
96
13931579
AJ		 97struct detailed_mode_closure {
98 struct drm_connector *connector;
dd0f4470 99 const struct drm_edid *drm_edid;
13931579 100 bool preferred;
13931579
AJ		 101 int modes;
102};
f453ba04 103
5c61259e
ZY		 104#define LEVEL_DMT 0
105#define LEVEL_GTF 1
7a374350
AJ		 106#define LEVEL_GTF2 2
107#define LEVEL_CVT 3
5c61259e 108
7d1be0a0 109#define EDID_QUIRK(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _quirks) \
e8de4d55 110{ \
7d1be0a0
DA		 111 .panel_id = drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, \
112 product_id), \
e8de4d55
DA		 113 .quirks = _quirks \
114}
115
23c4cfbd 116static const struct edid_quirk {
e8de4d55 117 u32 panel_id;
f453ba04
DA		 118 u32 quirks;
119} edid_quirk_list[] = {
120 /* Acer AL1706 */
7d1be0a0 121 EDID_QUIRK('A', 'C', 'R', 44358, EDID_QUIRK_PREFER_LARGE_60),
f453ba04 122 /* Acer F51 */
7d1be0a0 123 EDID_QUIRK('A', 'P', 'I', 0x7602, EDID_QUIRK_PREFER_LARGE_60),
f453ba04 124
e10aec65 125 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
7d1be0a0 126 EDID_QUIRK('A', 'E', 'O', 0, EDID_QUIRK_FORCE_6BPC),
e10aec65 127
0711a43b 128 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
7d1be0a0 129 EDID_QUIRK('B', 'O', 'E', 0x78b, EDID_QUIRK_FORCE_6BPC),
0711a43b 130
06998a75 131 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
7d1be0a0 132 EDID_QUIRK('C', 'P', 'T', 0x17df, EDID_QUIRK_FORCE_6BPC),
06998a75 133
25da7504 134 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
7d1be0a0 135 EDID_QUIRK('S', 'D', 'C', 0x3652, EDID_QUIRK_FORCE_6BPC),
25da7504 136
922dceff 137 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
7d1be0a0 138 EDID_QUIRK('B', 'O', 'E', 0x0771, EDID_QUIRK_FORCE_6BPC),
922dceff 139
f453ba04 140 /* Belinea 10 15 55 */
7d1be0a0
DA		 141 EDID_QUIRK('M', 'A', 'X', 1516, EDID_QUIRK_PREFER_LARGE_60),
142 EDID_QUIRK('M', 'A', 'X', 0x77e, EDID_QUIRK_PREFER_LARGE_60),
f453ba04
DA		 143
144 /* Envision Peripherals, Inc. EN-7100e */
7d1be0a0 145 EDID_QUIRK('E', 'P', 'I', 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH),
ba1163de 146 /* Envision EN2028 */
7d1be0a0 147 EDID_QUIRK('E', 'P', 'I', 8232, EDID_QUIRK_PREFER_LARGE_60),
f453ba04
DA		 148
149 /* Funai Electronics PM36B */
7d1be0a0 150 EDID_QUIRK('F', 'C', 'M', 13600, EDID_QUIRK_PREFER_LARGE_75 |
e8de4d55 151 EDID_QUIRK_DETAILED_IN_CM),
f453ba04 152
aa193f7e
HM		 153 /* LG 27GP950 */
154 EDID_QUIRK('G', 'S', 'M', 0x5bbf, EDID_QUIRK_CAP_DSC_15BPP),
155
156 /* LG 27GN950 */
157 EDID_QUIRK('G', 'S', 'M', 0x5b9a, EDID_QUIRK_CAP_DSC_15BPP),
158
e345da82 159 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
7d1be0a0 160 EDID_QUIRK('L', 'G', 'D', 764, EDID_QUIRK_FORCE_10BPC),
e345da82 161
f453ba04 162 /* LG Philips LCD LP154W01-A5 */
7d1be0a0
DA		 163 EDID_QUIRK('L', 'P', 'L', 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
164 EDID_QUIRK('L', 'P', 'L', 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
f453ba04 165
f453ba04 166 /* Samsung SyncMaster 205BW. Note: irony */
7d1be0a0 167 EDID_QUIRK('S', 'A', 'M', 541, EDID_QUIRK_DETAILED_SYNC_PP),
f453ba04 168 /* Samsung SyncMaster 22[5-6]BW */
7d1be0a0
DA		 169 EDID_QUIRK('S', 'A', 'M', 596, EDID_QUIRK_PREFER_LARGE_60),
170 EDID_QUIRK('S', 'A', 'M', 638, EDID_QUIRK_PREFER_LARGE_60),
bc42aabc 171
bc5b9641 172 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
7d1be0a0 173 EDID_QUIRK('S', 'N', 'Y', 0x2541, EDID_QUIRK_FORCE_12BPC),
bc5b9641 174
bc42aabc 175 /* ViewSonic VA2026w */
7d1be0a0 176 EDID_QUIRK('V', 'S', 'C', 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING),
118bdbd8
AD		 177
178 /* Medion MD 30217 PG */
7d1be0a0 179 EDID_QUIRK('M', 'E', 'D', 0x7b8, EDID_QUIRK_PREFER_LARGE_75),
49d45a31 180
11bcf5f7 181 /* Lenovo G50 */
7d1be0a0 182 EDID_QUIRK('S', 'D', 'C', 18514, EDID_QUIRK_FORCE_6BPC),
11bcf5f7 183
49d45a31 184 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
7d1be0a0 185 EDID_QUIRK('S', 'E', 'C', 0xd033, EDID_QUIRK_FORCE_8BPC),
36fc5797
TV		 186
187 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
7d1be0a0 188 EDID_QUIRK('E', 'T', 'R', 13896, EDID_QUIRK_FORCE_8BPC),
acb1d8ee 189
30d62d44 190 /* Valve Index Headset */
7d1be0a0
DA		 191 EDID_QUIRK('V', 'L', 'V', 0x91a8, EDID_QUIRK_NON_DESKTOP),
192 EDID_QUIRK('V', 'L', 'V', 0x91b0, EDID_QUIRK_NON_DESKTOP),
193 EDID_QUIRK('V', 'L', 'V', 0x91b1, EDID_QUIRK_NON_DESKTOP),
194 EDID_QUIRK('V', 'L', 'V', 0x91b2, EDID_QUIRK_NON_DESKTOP),
195 EDID_QUIRK('V', 'L', 'V', 0x91b3, EDID_QUIRK_NON_DESKTOP),
196 EDID_QUIRK('V', 'L', 'V', 0x91b4, EDID_QUIRK_NON_DESKTOP),
197 EDID_QUIRK('V', 'L', 'V', 0x91b5, EDID_QUIRK_NON_DESKTOP),
198 EDID_QUIRK('V', 'L', 'V', 0x91b6, EDID_QUIRK_NON_DESKTOP),
199 EDID_QUIRK('V', 'L', 'V', 0x91b7, EDID_QUIRK_NON_DESKTOP),
200 EDID_QUIRK('V', 'L', 'V', 0x91b8, EDID_QUIRK_NON_DESKTOP),
201 EDID_QUIRK('V', 'L', 'V', 0x91b9, EDID_QUIRK_NON_DESKTOP),
202 EDID_QUIRK('V', 'L', 'V', 0x91ba, EDID_QUIRK_NON_DESKTOP),
203 EDID_QUIRK('V', 'L', 'V', 0x91bb, EDID_QUIRK_NON_DESKTOP),
204 EDID_QUIRK('V', 'L', 'V', 0x91bc, EDID_QUIRK_NON_DESKTOP),
205 EDID_QUIRK('V', 'L', 'V', 0x91bd, EDID_QUIRK_NON_DESKTOP),
206 EDID_QUIRK('V', 'L', 'V', 0x91be, EDID_QUIRK_NON_DESKTOP),
207 EDID_QUIRK('V', 'L', 'V', 0x91bf, EDID_QUIRK_NON_DESKTOP),
30d62d44 208
6931317c 209 /* HTC Vive and Vive Pro VR Headsets */
7d1be0a0
DA		 210 EDID_QUIRK('H', 'V', 'R', 0xaa01, EDID_QUIRK_NON_DESKTOP),
211 EDID_QUIRK('H', 'V', 'R', 0xaa02, EDID_QUIRK_NON_DESKTOP),
b3b12ea3 212
5a3f6108 213 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */
7d1be0a0
DA		 214 EDID_QUIRK('O', 'V', 'R', 0x0001, EDID_QUIRK_NON_DESKTOP),
215 EDID_QUIRK('O', 'V', 'R', 0x0003, EDID_QUIRK_NON_DESKTOP),
216 EDID_QUIRK('O', 'V', 'R', 0x0004, EDID_QUIRK_NON_DESKTOP),
217 EDID_QUIRK('O', 'V', 'R', 0x0012, EDID_QUIRK_NON_DESKTOP),
90eda8fc
PZ		 218
219 /* Windows Mixed Reality Headsets */
7d1be0a0 220 EDID_QUIRK('A', 'C', 'R', 0x7fce, EDID_QUIRK_NON_DESKTOP),
7d1be0a0 221 EDID_QUIRK('L', 'E', 'N', 0x0408, EDID_QUIRK_NON_DESKTOP),
7d1be0a0
DA		 222 EDID_QUIRK('F', 'U', 'J', 0x1970, EDID_QUIRK_NON_DESKTOP),
223 EDID_QUIRK('D', 'E', 'L', 0x7fce, EDID_QUIRK_NON_DESKTOP),
224 EDID_QUIRK('S', 'E', 'C', 0x144a, EDID_QUIRK_NON_DESKTOP),
225 EDID_QUIRK('A', 'U', 'S', 0xc102, EDID_QUIRK_NON_DESKTOP),
ccffc9eb
PZ		 226
227 /* Sony PlayStation VR Headset */
7d1be0a0 228 EDID_QUIRK('S', 'N', 'Y', 0x0704, EDID_QUIRK_NON_DESKTOP),
29054230
RP		 229
230 /* Sensics VR Headsets */
7d1be0a0 231 EDID_QUIRK('S', 'E', 'N', 0x1019, EDID_QUIRK_NON_DESKTOP),
29054230
RP		 232
233 /* OSVR HDK and HDK2 VR Headsets */
7d1be0a0 234 EDID_QUIRK('S', 'V', 'R', 0x1019, EDID_QUIRK_NON_DESKTOP),
98d4cb70 235 EDID_QUIRK('A', 'U', 'O', 0x1111, EDID_QUIRK_NON_DESKTOP),
f453ba04
DA		 236};
237
a6b21831
TR		 238/*
239 * Autogenerated from the DMT spec.
240 * This table is copied from xfree86/modes/xf86EdidModes.c.
241 */
242static const struct drm_display_mode drm_dmt_modes[] = {
24b856b1 243 /* 0x01 - 640x350@85Hz */
a6b21831
TR		 244 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
245 736, 832, 0, 350, 382, 385, 445, 0,
246 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 247 /* 0x02 - 640x400@85Hz */
a6b21831
TR		 248 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
249 736, 832, 0, 400, 401, 404, 445, 0,
250 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 251 /* 0x03 - 720x400@85Hz */
a6b21831
TR		 252 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
253 828, 936, 0, 400, 401, 404, 446, 0,
254 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 255 /* 0x04 - 640x480@60Hz */
a6b21831 256 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
fcf22d05 257 752, 800, 0, 480, 490, 492, 525, 0,
a6b21831 258 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 259 /* 0x05 - 640x480@72Hz */
a6b21831
TR		 260 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
261 704, 832, 0, 480, 489, 492, 520, 0,
262 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 263 /* 0x06 - 640x480@75Hz */
a6b21831
TR		 264 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
265 720, 840, 0, 480, 481, 484, 500, 0,
266 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 267 /* 0x07 - 640x480@85Hz */
a6b21831
TR		 268 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
269 752, 832, 0, 480, 481, 484, 509, 0,
270 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 271 /* 0x08 - 800x600@56Hz */
a6b21831
TR		 272 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
273 896, 1024, 0, 600, 601, 603, 625, 0,
274 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 275 /* 0x09 - 800x600@60Hz */
a6b21831
TR		 276 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
277 968, 1056, 0, 600, 601, 605, 628, 0,
278 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 279 /* 0x0a - 800x600@72Hz */
a6b21831
TR		 280 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
281 976, 1040, 0, 600, 637, 643, 666, 0,
282 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 283 /* 0x0b - 800x600@75Hz */
a6b21831
TR		 284 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
285 896, 1056, 0, 600, 601, 604, 625, 0,
286 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 287 /* 0x0c - 800x600@85Hz */
a6b21831
TR		 288 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
289 896, 1048, 0, 600, 601, 604, 631, 0,
290 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 291 /* 0x0d - 800x600@120Hz RB */
a6b21831
TR		 292 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
293 880, 960, 0, 600, 603, 607, 636, 0,
294 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 295 /* 0x0e - 848x480@60Hz */
a6b21831
TR		 296 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
297 976, 1088, 0, 480, 486, 494, 517, 0,
298 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 299 /* 0x0f - 1024x768@43Hz, interlace */
a6b21831 300 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
735b100f 301 1208, 1264, 0, 768, 768, 776, 817, 0,
a6b21831 302 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
fcf22d05 303 DRM_MODE_FLAG_INTERLACE) },
24b856b1 304 /* 0x10 - 1024x768@60Hz */
a6b21831
TR		 305 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
306 1184, 1344, 0, 768, 771, 777, 806, 0,
307 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 308 /* 0x11 - 1024x768@70Hz */
a6b21831
TR		 309 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
310 1184, 1328, 0, 768, 771, 777, 806, 0,
311 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 312 /* 0x12 - 1024x768@75Hz */
a6b21831
TR		 313 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
314 1136, 1312, 0, 768, 769, 772, 800, 0,
315 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 316 /* 0x13 - 1024x768@85Hz */
a6b21831
TR		 317 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
318 1168, 1376, 0, 768, 769, 772, 808, 0,
319 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 320 /* 0x14 - 1024x768@120Hz RB */
a6b21831
TR		 321 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
322 1104, 1184, 0, 768, 771, 775, 813, 0,
323 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 324 /* 0x15 - 1152x864@75Hz */
a6b21831
TR		 325 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
326 1344, 1600, 0, 864, 865, 868, 900, 0,
327 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
bfcd74d2
VS		 328 /* 0x55 - 1280x720@60Hz */
329 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
330 1430, 1650, 0, 720, 725, 730, 750, 0,
331 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 332 /* 0x16 - 1280x768@60Hz RB */
a6b21831
TR		 333 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
334 1360, 1440, 0, 768, 771, 778, 790, 0,
335 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 336 /* 0x17 - 1280x768@60Hz */
a6b21831
TR		 337 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
338 1472, 1664, 0, 768, 771, 778, 798, 0,
339 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 340 /* 0x18 - 1280x768@75Hz */
a6b21831
TR		 341 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
342 1488, 1696, 0, 768, 771, 778, 805, 0,
fcf22d05 343 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 344 /* 0x19 - 1280x768@85Hz */
a6b21831
TR		 345 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
346 1496, 1712, 0, 768, 771, 778, 809, 0,
347 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 348 /* 0x1a - 1280x768@120Hz RB */
a6b21831
TR		 349 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
350 1360, 1440, 0, 768, 771, 778, 813, 0,
351 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 352 /* 0x1b - 1280x800@60Hz RB */
a6b21831
TR		 353 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
354 1360, 1440, 0, 800, 803, 809, 823, 0,
355 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 356 /* 0x1c - 1280x800@60Hz */
a6b21831
TR		 357 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
358 1480, 1680, 0, 800, 803, 809, 831, 0,
fcf22d05 359 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 360 /* 0x1d - 1280x800@75Hz */
a6b21831
TR		 361 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
362 1488, 1696, 0, 800, 803, 809, 838, 0,
363 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 364 /* 0x1e - 1280x800@85Hz */
a6b21831
TR		 365 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
366 1496, 1712, 0, 800, 803, 809, 843, 0,
367 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 368 /* 0x1f - 1280x800@120Hz RB */
a6b21831
TR		 369 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
370 1360, 1440, 0, 800, 803, 809, 847, 0,
371 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 372 /* 0x20 - 1280x960@60Hz */
a6b21831
TR		 373 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
374 1488, 1800, 0, 960, 961, 964, 1000, 0,
375 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 376 /* 0x21 - 1280x960@85Hz */
a6b21831
TR		 377 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
378 1504, 1728, 0, 960, 961, 964, 1011, 0,
379 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 380 /* 0x22 - 1280x960@120Hz RB */
a6b21831
TR		 381 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
382 1360, 1440, 0, 960, 963, 967, 1017, 0,
383 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 384 /* 0x23 - 1280x1024@60Hz */
a6b21831
TR		 385 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
386 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
387 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 388 /* 0x24 - 1280x1024@75Hz */
a6b21831
TR		 389 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
390 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
391 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 392 /* 0x25 - 1280x1024@85Hz */
a6b21831
TR		 393 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
394 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
395 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 396 /* 0x26 - 1280x1024@120Hz RB */
a6b21831
TR		 397 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
398 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
399 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 400 /* 0x27 - 1360x768@60Hz */
a6b21831
TR		 401 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
402 1536, 1792, 0, 768, 771, 777, 795, 0,
403 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 404 /* 0x28 - 1360x768@120Hz RB */
a6b21831
TR		 405 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
406 1440, 1520, 0, 768, 771, 776, 813, 0,
407 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 408 /* 0x51 - 1366x768@60Hz */
409 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
410 1579, 1792, 0, 768, 771, 774, 798, 0,
411 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
412 /* 0x56 - 1366x768@60Hz */
413 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
414 1436, 1500, 0, 768, 769, 772, 800, 0,
415 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 416 /* 0x29 - 1400x1050@60Hz RB */
a6b21831
TR		 417 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
418 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
419 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 420 /* 0x2a - 1400x1050@60Hz */
a6b21831
TR		 421 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
422 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
423 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 424 /* 0x2b - 1400x1050@75Hz */
a6b21831
TR		 425 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
426 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
427 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 428 /* 0x2c - 1400x1050@85Hz */
a6b21831
TR		 429 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
430 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
431 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 432 /* 0x2d - 1400x1050@120Hz RB */
a6b21831
TR		 433 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
434 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
435 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 436 /* 0x2e - 1440x900@60Hz RB */
a6b21831
TR		 437 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
438 1520, 1600, 0, 900, 903, 909, 926, 0,
439 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 440 /* 0x2f - 1440x900@60Hz */
a6b21831
TR		 441 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
442 1672, 1904, 0, 900, 903, 909, 934, 0,
443 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 444 /* 0x30 - 1440x900@75Hz */
a6b21831
TR		 445 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
446 1688, 1936, 0, 900, 903, 909, 942, 0,
447 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 448 /* 0x31 - 1440x900@85Hz */
a6b21831
TR		 449 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
450 1696, 1952, 0, 900, 903, 909, 948, 0,
451 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 452 /* 0x32 - 1440x900@120Hz RB */
a6b21831
TR		 453 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
454 1520, 1600, 0, 900, 903, 909, 953, 0,
455 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 456 /* 0x53 - 1600x900@60Hz */
457 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
458 1704, 1800, 0, 900, 901, 904, 1000, 0,
459 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 460 /* 0x33 - 1600x1200@60Hz */
a6b21831
TR		 461 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
462 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
463 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 464 /* 0x34 - 1600x1200@65Hz */
a6b21831
TR		 465 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
466 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
467 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 468 /* 0x35 - 1600x1200@70Hz */
a6b21831
TR		 469 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
470 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
471 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 472 /* 0x36 - 1600x1200@75Hz */
a6b21831
TR		 473 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
474 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
475 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 476 /* 0x37 - 1600x1200@85Hz */
a6b21831
TR		 477 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
478 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
479 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 480 /* 0x38 - 1600x1200@120Hz RB */
a6b21831
TR		 481 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
482 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
483 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 484 /* 0x39 - 1680x1050@60Hz RB */
a6b21831
TR		 485 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
486 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
487 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 488 /* 0x3a - 1680x1050@60Hz */
a6b21831
TR		 489 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
490 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
491 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 492 /* 0x3b - 1680x1050@75Hz */
a6b21831
TR		 493 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
494 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
495 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 496 /* 0x3c - 1680x1050@85Hz */
a6b21831
TR		 497 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
498 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
499 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 500 /* 0x3d - 1680x1050@120Hz RB */
a6b21831
TR		 501 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
502 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
503 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 504 /* 0x3e - 1792x1344@60Hz */
a6b21831
TR		 505 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
506 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
507 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 508 /* 0x3f - 1792x1344@75Hz */
a6b21831
TR		 509 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
510 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
511 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 512 /* 0x40 - 1792x1344@120Hz RB */
a6b21831
TR		 513 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
514 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
515 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 516 /* 0x41 - 1856x1392@60Hz */
a6b21831
TR		 517 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
518 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
519 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 520 /* 0x42 - 1856x1392@75Hz */
a6b21831 521 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
fcf22d05 522 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
a6b21831 523 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 524 /* 0x43 - 1856x1392@120Hz RB */
a6b21831
TR		 525 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
526 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
527 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 528 /* 0x52 - 1920x1080@60Hz */
529 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
530 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
531 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 532 /* 0x44 - 1920x1200@60Hz RB */
a6b21831
TR		 533 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
534 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
535 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 536 /* 0x45 - 1920x1200@60Hz */
a6b21831
TR		 537 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
538 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
539 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 540 /* 0x46 - 1920x1200@75Hz */
a6b21831
TR		 541 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
542 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
543 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 544 /* 0x47 - 1920x1200@85Hz */
a6b21831
TR		 545 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
546 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
547 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 548 /* 0x48 - 1920x1200@120Hz RB */
a6b21831
TR		 549 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
550 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
551 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 552 /* 0x49 - 1920x1440@60Hz */
a6b21831
TR		 553 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
554 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
555 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 556 /* 0x4a - 1920x1440@75Hz */
a6b21831
TR		 557 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
558 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
559 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 560 /* 0x4b - 1920x1440@120Hz RB */
a6b21831
TR		 561 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
562 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
563 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 564 /* 0x54 - 2048x1152@60Hz */
565 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
566 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
567 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 568 /* 0x4c - 2560x1600@60Hz RB */
a6b21831
TR		 569 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
570 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
571 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 572 /* 0x4d - 2560x1600@60Hz */
a6b21831
TR		 573 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
574 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
575 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 576 /* 0x4e - 2560x1600@75Hz */
a6b21831
TR		 577 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
578 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
579 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 580 /* 0x4f - 2560x1600@85Hz */
a6b21831
TR		 581 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
582 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
583 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 584 /* 0x50 - 2560x1600@120Hz RB */
a6b21831
TR		 585 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
586 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
587 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 588 /* 0x57 - 4096x2160@60Hz RB */
589 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
590 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
591 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
592 /* 0x58 - 4096x2160@59.94Hz RB */
593 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
594 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
595 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
a6b21831
TR		 596};
597
e7bfa5c4
VS		 598/*
599 * These more or less come from the DMT spec. The 720x400 modes are
600 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
601 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
602 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
603 * mode.
604 *
605 * The DMT modes have been fact-checked; the rest are mild guesses.
606 */
a6b21831
TR		 607static const struct drm_display_mode edid_est_modes[] = {
608 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
609 968, 1056, 0, 600, 601, 605, 628, 0,
610 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
611 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
612 896, 1024, 0, 600, 601, 603, 625, 0,
613 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
614 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
615 720, 840, 0, 480, 481, 484, 500, 0,
616 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
617 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
87707cfd 618 704, 832, 0, 480, 489, 492, 520, 0,
a6b21831
TR		 619 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
620 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
621 768, 864, 0, 480, 483, 486, 525, 0,
622 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
87707cfd 623 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
a6b21831
TR		 624 752, 800, 0, 480, 490, 492, 525, 0,
625 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
626 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
627 846, 900, 0, 400, 421, 423, 449, 0,
628 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
629 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
630 846, 900, 0, 400, 412, 414, 449, 0,
631 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
632 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
633 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
634 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
87707cfd 635 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
a6b21831
TR		 636 1136, 1312, 0, 768, 769, 772, 800, 0,
637 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
638 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
639 1184, 1328, 0, 768, 771, 777, 806, 0,
640 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
641 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
642 1184, 1344, 0, 768, 771, 777, 806, 0,
643 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
644 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
645 1208, 1264, 0, 768, 768, 776, 817, 0,
646 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
647 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
648 928, 1152, 0, 624, 625, 628, 667, 0,
649 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
650 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
651 896, 1056, 0, 600, 601, 604, 625, 0,
652 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
653 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
654 976, 1040, 0, 600, 637, 643, 666, 0,
655 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
656 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
657 1344, 1600, 0, 864, 865, 868, 900, 0,
658 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
659};
660
661struct minimode {
662 short w;
663 short h;
664 short r;
665 short rb;
666};
667
668static const struct minimode est3_modes[] = {
669 /* byte 6 */
670 { 640, 350, 85, 0 },
671 { 640, 400, 85, 0 },
672 { 720, 400, 85, 0 },
673 { 640, 480, 85, 0 },
674 { 848, 480, 60, 0 },
675 { 800, 600, 85, 0 },
676 { 1024, 768, 85, 0 },
677 { 1152, 864, 75, 0 },
678 /* byte 7 */
679 { 1280, 768, 60, 1 },
680 { 1280, 768, 60, 0 },
681 { 1280, 768, 75, 0 },
682 { 1280, 768, 85, 0 },
683 { 1280, 960, 60, 0 },
684 { 1280, 960, 85, 0 },
685 { 1280, 1024, 60, 0 },
686 { 1280, 1024, 85, 0 },
687 /* byte 8 */
688 { 1360, 768, 60, 0 },
689 { 1440, 900, 60, 1 },
690 { 1440, 900, 60, 0 },
691 { 1440, 900, 75, 0 },
692 { 1440, 900, 85, 0 },
693 { 1400, 1050, 60, 1 },
694 { 1400, 1050, 60, 0 },
695 { 1400, 1050, 75, 0 },
696 /* byte 9 */
697 { 1400, 1050, 85, 0 },
698 { 1680, 1050, 60, 1 },
699 { 1680, 1050, 60, 0 },
700 { 1680, 1050, 75, 0 },
701 { 1680, 1050, 85, 0 },
702 { 1600, 1200, 60, 0 },
703 { 1600, 1200, 65, 0 },
704 { 1600, 1200, 70, 0 },
705 /* byte 10 */
706 { 1600, 1200, 75, 0 },
707 { 1600, 1200, 85, 0 },
708 { 1792, 1344, 60, 0 },
c068b32a 709 { 1792, 1344, 75, 0 },
a6b21831
TR		 710 { 1856, 1392, 60, 0 },
711 { 1856, 1392, 75, 0 },
712 { 1920, 1200, 60, 1 },
713 { 1920, 1200, 60, 0 },
714 /* byte 11 */
715 { 1920, 1200, 75, 0 },
716 { 1920, 1200, 85, 0 },
717 { 1920, 1440, 60, 0 },
718 { 1920, 1440, 75, 0 },
719};
720
721static const struct minimode extra_modes[] = {
722 { 1024, 576, 60, 0 },
723 { 1366, 768, 60, 0 },
724 { 1600, 900, 60, 0 },
725 { 1680, 945, 60, 0 },
726 { 1920, 1080, 60, 0 },
727 { 2048, 1152, 60, 0 },
728 { 2048, 1536, 60, 0 },
729};
730
731/*
7befe621 732 * From CEA/CTA-861 spec.
d9278b4c 733 *
7befe621 734 * Do not access directly, instead always use cea_mode_for_vic().
a6b21831 735 */
8c1b2bd9 736static const struct drm_display_mode edid_cea_modes_1[] = {
78691960 737 /* 1 - 640x480@60Hz 4:3 */
a6b21831
TR		 738 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
739 752, 800, 0, 480, 490, 492, 525, 0,
ee7925bb 740 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 741 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 742 /* 2 - 720x480@60Hz 4:3 */
a6b21831
TR		 743 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
744 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 745 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 746 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 747 /* 3 - 720x480@60Hz 16:9 */
a6b21831
TR		 748 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
749 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 750 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 751 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 752 /* 4 - 1280x720@60Hz 16:9 */
a6b21831
TR		 753 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
754 1430, 1650, 0, 720, 725, 730, 750, 0,
ee7925bb 755 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 756 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 757 /* 5 - 1920x1080i@60Hz 16:9 */
a6b21831
TR		 758 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
759 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
760 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 761 DRM_MODE_FLAG_INTERLACE),
0425662f 762 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 763 /* 6 - 720(1440)x480i@60Hz 4:3 */
fb01d280
CT		 764 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
765 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 766 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 767 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 768 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 769 /* 7 - 720(1440)x480i@60Hz 16:9 */
fb01d280
CT		 770 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
771 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 772 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 773 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 774 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 775 /* 8 - 720(1440)x240@60Hz 4:3 */
fb01d280
CT		 776 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
777 801, 858, 0, 240, 244, 247, 262, 0,
a6b21831 778 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 779 DRM_MODE_FLAG_DBLCLK),
0425662f 780 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 781 /* 9 - 720(1440)x240@60Hz 16:9 */
fb01d280
CT		 782 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
783 801, 858, 0, 240, 244, 247, 262, 0,
a6b21831 784 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 785 DRM_MODE_FLAG_DBLCLK),
0425662f 786 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 787 /* 10 - 2880x480i@60Hz 4:3 */
a6b21831
TR		 788 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
789 3204, 3432, 0, 480, 488, 494, 525, 0,
790 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 791 DRM_MODE_FLAG_INTERLACE),
0425662f 792 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 793 /* 11 - 2880x480i@60Hz 16:9 */
a6b21831
TR		 794 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
795 3204, 3432, 0, 480, 488, 494, 525, 0,
796 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 797 DRM_MODE_FLAG_INTERLACE),
0425662f 798 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 799 /* 12 - 2880x240@60Hz 4:3 */
a6b21831
TR		 800 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
801 3204, 3432, 0, 240, 244, 247, 262, 0,
ee7925bb 802 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 803 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 804 /* 13 - 2880x240@60Hz 16:9 */
a6b21831
TR		 805 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
806 3204, 3432, 0, 240, 244, 247, 262, 0,
ee7925bb 807 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 808 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 809 /* 14 - 1440x480@60Hz 4:3 */
a6b21831
TR		 810 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
811 1596, 1716, 0, 480, 489, 495, 525, 0,
ee7925bb 812 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 813 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 814 /* 15 - 1440x480@60Hz 16:9 */
a6b21831
TR		 815 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
816 1596, 1716, 0, 480, 489, 495, 525, 0,
ee7925bb 817 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 818 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 819 /* 16 - 1920x1080@60Hz 16:9 */
a6b21831
TR		 820 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
821 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 822 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 823 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 824 /* 17 - 720x576@50Hz 4:3 */
a6b21831
TR		 825 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
826 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 827 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 828 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 829 /* 18 - 720x576@50Hz 16:9 */
a6b21831
TR		 830 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
831 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 832 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 833 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 834 /* 19 - 1280x720@50Hz 16:9 */
a6b21831
TR		 835 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
836 1760, 1980, 0, 720, 725, 730, 750, 0,
ee7925bb 837 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 838 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 839 /* 20 - 1920x1080i@50Hz 16:9 */
a6b21831
TR		 840 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
841 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
842 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 843 DRM_MODE_FLAG_INTERLACE),
0425662f 844 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 845 /* 21 - 720(1440)x576i@50Hz 4:3 */
fb01d280
CT		 846 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
847 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 848 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 849 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 850 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 851 /* 22 - 720(1440)x576i@50Hz 16:9 */
fb01d280
CT		 852 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
853 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 854 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 855 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 856 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 857 /* 23 - 720(1440)x288@50Hz 4:3 */
fb01d280
CT		 858 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
859 795, 864, 0, 288, 290, 293, 312, 0,
a6b21831 860 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 861 DRM_MODE_FLAG_DBLCLK),
0425662f 862 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 863 /* 24 - 720(1440)x288@50Hz 16:9 */
fb01d280
CT		 864 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
865 795, 864, 0, 288, 290, 293, 312, 0,
a6b21831 866 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 867 DRM_MODE_FLAG_DBLCLK),
0425662f 868 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 869 /* 25 - 2880x576i@50Hz 4:3 */
a6b21831
TR		 870 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
871 3180, 3456, 0, 576, 580, 586, 625, 0,
872 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 873 DRM_MODE_FLAG_INTERLACE),
0425662f 874 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 875 /* 26 - 2880x576i@50Hz 16:9 */
a6b21831
TR		 876 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
877 3180, 3456, 0, 576, 580, 586, 625, 0,
878 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 879 DRM_MODE_FLAG_INTERLACE),
0425662f 880 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 881 /* 27 - 2880x288@50Hz 4:3 */
a6b21831
TR		 882 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
883 3180, 3456, 0, 288, 290, 293, 312, 0,
ee7925bb 884 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 885 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 886 /* 28 - 2880x288@50Hz 16:9 */
a6b21831
TR		 887 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
888 3180, 3456, 0, 288, 290, 293, 312, 0,
ee7925bb 889 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 890 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 891 /* 29 - 1440x576@50Hz 4:3 */
a6b21831
TR		 892 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
893 1592, 1728, 0, 576, 581, 586, 625, 0,
ee7925bb 894 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 895 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 896 /* 30 - 1440x576@50Hz 16:9 */
a6b21831
TR		 897 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
898 1592, 1728, 0, 576, 581, 586, 625, 0,
ee7925bb 899 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 900 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 901 /* 31 - 1920x1080@50Hz 16:9 */
a6b21831
TR		 902 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
903 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 904 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 905 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 906 /* 32 - 1920x1080@24Hz 16:9 */
a6b21831
TR		 907 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
908 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 909 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 910 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 911 /* 33 - 1920x1080@25Hz 16:9 */
a6b21831
TR		 912 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
913 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 914 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 915 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 916 /* 34 - 1920x1080@30Hz 16:9 */
a6b21831
TR		 917 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
918 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 919 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 920 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 921 /* 35 - 2880x480@60Hz 4:3 */
a6b21831
TR		 922 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
923 3192, 3432, 0, 480, 489, 495, 525, 0,
ee7925bb 924 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 925 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 926 /* 36 - 2880x480@60Hz 16:9 */
a6b21831
TR		 927 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
928 3192, 3432, 0, 480, 489, 495, 525, 0,
ee7925bb 929 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 930 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 931 /* 37 - 2880x576@50Hz 4:3 */
a6b21831
TR		 932 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
933 3184, 3456, 0, 576, 581, 586, 625, 0,
ee7925bb 934 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 935 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 936 /* 38 - 2880x576@50Hz 16:9 */
a6b21831
TR		 937 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
938 3184, 3456, 0, 576, 581, 586, 625, 0,
ee7925bb 939 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 940 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 941 /* 39 - 1920x1080i@50Hz 16:9 */
a6b21831
TR		 942 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
943 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
944 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 945 DRM_MODE_FLAG_INTERLACE),
0425662f 946 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 947 /* 40 - 1920x1080i@100Hz 16:9 */
a6b21831
TR		 948 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
949 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
950 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 951 DRM_MODE_FLAG_INTERLACE),
0425662f 952 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 953 /* 41 - 1280x720@100Hz 16:9 */
a6b21831
TR		 954 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
955 1760, 1980, 0, 720, 725, 730, 750, 0,
ee7925bb 956 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 957 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 958 /* 42 - 720x576@100Hz 4:3 */
a6b21831
TR		 959 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
960 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 961 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 962 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 963 /* 43 - 720x576@100Hz 16:9 */
a6b21831
TR		 964 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
965 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 966 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 967 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 968 /* 44 - 720(1440)x576i@100Hz 4:3 */
fb01d280
CT		 969 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
970 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 971 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 972 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 973 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 974 /* 45 - 720(1440)x576i@100Hz 16:9 */
fb01d280
CT		 975 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
976 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 977 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 978 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 979 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 980 /* 46 - 1920x1080i@120Hz 16:9 */
a6b21831
TR		 981 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
982 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
983 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 984 DRM_MODE_FLAG_INTERLACE),
0425662f 985 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 986 /* 47 - 1280x720@120Hz 16:9 */
a6b21831
TR		 987 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
988 1430, 1650, 0, 720, 725, 730, 750, 0,
ee7925bb 989 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 990 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 991 /* 48 - 720x480@120Hz 4:3 */
a6b21831
TR		 992 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
993 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 994 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 995 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 996 /* 49 - 720x480@120Hz 16:9 */
a6b21831
TR		 997 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
998 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 999 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 1000 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1001 /* 50 - 720(1440)x480i@120Hz 4:3 */
fb01d280
CT		 1002 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
1003 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 1004 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1005 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1006 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1007 /* 51 - 720(1440)x480i@120Hz 16:9 */
fb01d280
CT		 1008 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
1009 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 1010 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1011 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1012 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1013 /* 52 - 720x576@200Hz 4:3 */
a6b21831
TR		 1014 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1015 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 1016 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 1017 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1018 /* 53 - 720x576@200Hz 16:9 */
a6b21831
TR		 1019 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1020 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 1021 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 1022 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1023 /* 54 - 720(1440)x576i@200Hz 4:3 */
fb01d280
CT		 1024 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1025 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 1026 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1027 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1028 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1029 /* 55 - 720(1440)x576i@200Hz 16:9 */
fb01d280
CT		 1030 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1031 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 1032 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1033 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1034 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1035 /* 56 - 720x480@240Hz 4:3 */
a6b21831
TR		 1036 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1037 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 1038 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 1039 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1040 /* 57 - 720x480@240Hz 16:9 */
a6b21831
TR		 1041 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1042 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 1043 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 1044 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1045 /* 58 - 720(1440)x480i@240Hz 4:3 */
fb01d280
CT		 1046 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1047 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 1048 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1049 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1050 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1051 /* 59 - 720(1440)x480i@240Hz 16:9 */
fb01d280
CT		 1052 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1053 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 1054 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1055 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1056 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1057 /* 60 - 1280x720@24Hz 16:9 */
a6b21831
TR		 1058 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1059 3080, 3300, 0, 720, 725, 730, 750, 0,
ee7925bb 1060 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1061 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1062 /* 61 - 1280x720@25Hz 16:9 */
a6b21831
TR		 1063 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1064 3740, 3960, 0, 720, 725, 730, 750, 0,
ee7925bb 1065 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1066 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1067 /* 62 - 1280x720@30Hz 16:9 */
a6b21831
TR		 1068 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1069 3080, 3300, 0, 720, 725, 730, 750, 0,
ee7925bb 1070 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1071 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1072 /* 63 - 1920x1080@120Hz 16:9 */
a6b21831
TR		 1073 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1074 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 1075 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1076 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1077 /* 64 - 1920x1080@100Hz 16:9 */
a6b21831 1078 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
8f0e4907 1079 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 1080 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1081 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1082 /* 65 - 1280x720@24Hz 64:27 */
8ec6e075
SS		 1083 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1084 3080, 3300, 0, 720, 725, 730, 750, 0,
1085 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1086 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1087 /* 66 - 1280x720@25Hz 64:27 */
8ec6e075
SS		 1088 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1089 3740, 3960, 0, 720, 725, 730, 750, 0,
1090 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1091 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1092 /* 67 - 1280x720@30Hz 64:27 */
8ec6e075
SS		 1093 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1094 3080, 3300, 0, 720, 725, 730, 750, 0,
1095 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1096 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1097 /* 68 - 1280x720@50Hz 64:27 */
8ec6e075
SS		 1098 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1099 1760, 1980, 0, 720, 725, 730, 750, 0,
1100 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1101 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1102 /* 69 - 1280x720@60Hz 64:27 */
8ec6e075
SS		 1103 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1104 1430, 1650, 0, 720, 725, 730, 750, 0,
1105 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1106 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1107 /* 70 - 1280x720@100Hz 64:27 */
8ec6e075
SS		 1108 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1109 1760, 1980, 0, 720, 725, 730, 750, 0,
1110 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1111 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1112 /* 71 - 1280x720@120Hz 64:27 */
8ec6e075
SS		 1113 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1114 1430, 1650, 0, 720, 725, 730, 750, 0,
1115 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1116 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1117 /* 72 - 1920x1080@24Hz 64:27 */
8ec6e075
SS		 1118 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1119 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1120 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1121 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1122 /* 73 - 1920x1080@25Hz 64:27 */
8ec6e075
SS		 1123 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1124 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1125 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1126 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1127 /* 74 - 1920x1080@30Hz 64:27 */
8ec6e075
SS		 1128 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1129 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1130 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1131 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1132 /* 75 - 1920x1080@50Hz 64:27 */
8ec6e075
SS		 1133 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1134 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1135 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1136 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1137 /* 76 - 1920x1080@60Hz 64:27 */
8ec6e075
SS		 1138 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1139 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1140 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1141 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1142 /* 77 - 1920x1080@100Hz 64:27 */
8ec6e075
SS		 1143 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1144 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1145 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1146 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1147 /* 78 - 1920x1080@120Hz 64:27 */
8ec6e075
SS		 1148 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1149 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1150 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1151 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1152 /* 79 - 1680x720@24Hz 64:27 */
8ec6e075
SS		 1153 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1154 3080, 3300, 0, 720, 725, 730, 750, 0,
1155 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1156 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1157 /* 80 - 1680x720@25Hz 64:27 */
8ec6e075
SS		 1158 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1159 2948, 3168, 0, 720, 725, 730, 750, 0,
1160 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1161 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1162 /* 81 - 1680x720@30Hz 64:27 */
8ec6e075
SS		 1163 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1164 2420, 2640, 0, 720, 725, 730, 750, 0,
1165 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1166 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1167 /* 82 - 1680x720@50Hz 64:27 */
8ec6e075
SS		 1168 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1169 1980, 2200, 0, 720, 725, 730, 750, 0,
1170 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1171 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1172 /* 83 - 1680x720@60Hz 64:27 */
8ec6e075
SS		 1173 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1174 1980, 2200, 0, 720, 725, 730, 750, 0,
1175 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1176 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1177 /* 84 - 1680x720@100Hz 64:27 */
8ec6e075
SS		 1178 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1179 1780, 2000, 0, 720, 725, 730, 825, 0,
1180 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1181 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1182 /* 85 - 1680x720@120Hz 64:27 */
8ec6e075
SS		 1183 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1184 1780, 2000, 0, 720, 725, 730, 825, 0,
1185 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1186 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1187 /* 86 - 2560x1080@24Hz 64:27 */
8ec6e075
SS		 1188 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1189 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1190 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1191 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1192 /* 87 - 2560x1080@25Hz 64:27 */
8ec6e075
SS		 1193 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1194 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1195 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1196 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1197 /* 88 - 2560x1080@30Hz 64:27 */
8ec6e075
SS		 1198 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1199 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1200 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1201 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1202 /* 89 - 2560x1080@50Hz 64:27 */
8ec6e075
SS		 1203 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1204 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1205 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1206 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1207 /* 90 - 2560x1080@60Hz 64:27 */
8ec6e075
SS		 1208 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1209 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1210 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1211 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1212 /* 91 - 2560x1080@100Hz 64:27 */
8ec6e075
SS		 1213 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1214 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1215 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1216 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1217 /* 92 - 2560x1080@120Hz 64:27 */
8ec6e075
SS		 1218 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1219 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1220 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1221 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1222 /* 93 - 3840x2160@24Hz 16:9 */
8ec6e075
SS		 1223 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1224 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1225 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1226 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1227 /* 94 - 3840x2160@25Hz 16:9 */
8ec6e075
SS		 1228 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1229 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1230 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1231 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1232 /* 95 - 3840x2160@30Hz 16:9 */
8ec6e075
SS		 1233 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1234 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1235 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1236 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1237 /* 96 - 3840x2160@50Hz 16:9 */
8ec6e075
SS		 1238 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1239 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1240 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1241 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1242 /* 97 - 3840x2160@60Hz 16:9 */
8ec6e075
SS		 1243 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1244 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1245 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1246 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1247 /* 98 - 4096x2160@24Hz 256:135 */
8ec6e075
SS		 1248 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1249 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1250 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1251 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1252 /* 99 - 4096x2160@25Hz 256:135 */
8ec6e075
SS		 1253 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1254 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1255 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1256 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1257 /* 100 - 4096x2160@30Hz 256:135 */
8ec6e075
SS		 1258 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1259 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1260 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1261 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1262 /* 101 - 4096x2160@50Hz 256:135 */
8ec6e075
SS		 1263 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1264 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1265 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1266 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1267 /* 102 - 4096x2160@60Hz 256:135 */
8ec6e075
SS		 1268 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1269 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1270 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1271 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1272 /* 103 - 3840x2160@24Hz 64:27 */
8ec6e075
SS		 1273 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1274 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1275 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1276 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1277 /* 104 - 3840x2160@25Hz 64:27 */
8ec6e075
SS		 1278 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1279 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1281 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1282 /* 105 - 3840x2160@30Hz 64:27 */
8ec6e075
SS		 1283 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1284 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1285 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1286 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1287 /* 106 - 3840x2160@50Hz 64:27 */
8ec6e075
SS		 1288 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1289 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1290 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1291 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1292 /* 107 - 3840x2160@60Hz 64:27 */
8ec6e075
SS		 1293 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1294 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1295 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1296 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1297 /* 108 - 1280x720@48Hz 16:9 */
1298 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1299 2280, 2500, 0, 720, 725, 730, 750, 0,
1300 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1301 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1302 /* 109 - 1280x720@48Hz 64:27 */
1303 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1304 2280, 2500, 0, 720, 725, 730, 750, 0,
1305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1306 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1307 /* 110 - 1680x720@48Hz 64:27 */
1308 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490,
1309 2530, 2750, 0, 720, 725, 730, 750, 0,
1310 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1311 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1312 /* 111 - 1920x1080@48Hz 16:9 */
1313 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1314 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1315 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1316 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1317 /* 112 - 1920x1080@48Hz 64:27 */
1318 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1319 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1320 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1321 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1322 /* 113 - 2560x1080@48Hz 64:27 */
1323 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558,
1324 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1325 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1326 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1327 /* 114 - 3840x2160@48Hz 16:9 */
1328 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1329 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1330 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1331 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1332 /* 115 - 4096x2160@48Hz 256:135 */
1333 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116,
1334 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1335 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1336 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
978f6b06
VS		 1337 /* 116 - 3840x2160@48Hz 64:27 */
1338 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1339 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1340 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1341 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1342 /* 117 - 3840x2160@100Hz 16:9 */
1343 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1344 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1345 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1346 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1347 /* 118 - 3840x2160@120Hz 16:9 */
1348 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1349 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1350 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1351 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1352 /* 119 - 3840x2160@100Hz 64:27 */
1353 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1354 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1355 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1356 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1357 /* 120 - 3840x2160@120Hz 64:27 */
1358 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1359 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1360 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1361 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1362 /* 121 - 5120x2160@24Hz 64:27 */
1363 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116,
1364 7204, 7500, 0, 2160, 2168, 2178, 2200, 0,
1365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1366 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1367 /* 122 - 5120x2160@25Hz 64:27 */
1368 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816,
1369 6904, 7200, 0, 2160, 2168, 2178, 2200, 0,
1370 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1371 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1372 /* 123 - 5120x2160@30Hz 64:27 */
1373 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784,
1374 5872, 6000, 0, 2160, 2168, 2178, 2200, 0,
1375 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1376 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1377 /* 124 - 5120x2160@48Hz 64:27 */
1378 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866,
1379 5954, 6250, 0, 2160, 2168, 2178, 2475, 0,
1380 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1381 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1382 /* 125 - 5120x2160@50Hz 64:27 */
1383 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216,
1384 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1386 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1387 /* 126 - 5120x2160@60Hz 64:27 */
1388 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284,
1389 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1390 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1391 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1392 /* 127 - 5120x2160@100Hz 64:27 */
1393 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216,
1394 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1395 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1396 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
a6b21831
TR		 1397};
1398
f7655d42
VS		 1399/*
1400 * From CEA/CTA-861 spec.
1401 *
1402 * Do not access directly, instead always use cea_mode_for_vic().
1403 */
1404static const struct drm_display_mode edid_cea_modes_193[] = {
1405 /* 193 - 5120x2160@120Hz 64:27 */
1406 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284,
1407 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1408 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1409 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1410 /* 194 - 7680x4320@24Hz 16:9 */
1411 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1412 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1413 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1414 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1415 /* 195 - 7680x4320@25Hz 16:9 */
1416 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1417 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1418 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1419 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1420 /* 196 - 7680x4320@30Hz 16:9 */
1421 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1422 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1423 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1424 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1425 /* 197 - 7680x4320@48Hz 16:9 */
1426 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1427 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1428 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1429 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1430 /* 198 - 7680x4320@50Hz 16:9 */
1431 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1432 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1433 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1434 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1435 /* 199 - 7680x4320@60Hz 16:9 */
1436 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1437 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1438 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1439 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1440 /* 200 - 7680x4320@100Hz 16:9 */
1441 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1442 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1443 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1444 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1445 /* 201 - 7680x4320@120Hz 16:9 */
1446 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1447 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1448 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1449 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1450 /* 202 - 7680x4320@24Hz 64:27 */
1451 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1452 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1454 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1455 /* 203 - 7680x4320@25Hz 64:27 */
1456 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1457 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1458 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1459 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1460 /* 204 - 7680x4320@30Hz 64:27 */
1461 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1462 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1463 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1464 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1465 /* 205 - 7680x4320@48Hz 64:27 */
1466 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1467 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1468 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1469 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1470 /* 206 - 7680x4320@50Hz 64:27 */
1471 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1472 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1473 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1474 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1475 /* 207 - 7680x4320@60Hz 64:27 */
1476 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1477 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1478 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1479 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1480 /* 208 - 7680x4320@100Hz 64:27 */
1481 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1482 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1483 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1484 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1485 /* 209 - 7680x4320@120Hz 64:27 */
1486 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1487 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1488 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1489 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1490 /* 210 - 10240x4320@24Hz 64:27 */
1491 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732,
1492 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1493 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1494 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1495 /* 211 - 10240x4320@25Hz 64:27 */
1496 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732,
1497 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1498 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1499 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1500 /* 212 - 10240x4320@30Hz 64:27 */
1501 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528,
1502 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1503 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1504 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1505 /* 213 - 10240x4320@48Hz 64:27 */
1506 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732,
1507 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1508 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1509 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1510 /* 214 - 10240x4320@50Hz 64:27 */
1511 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732,
1512 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1513 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1514 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1515 /* 215 - 10240x4320@60Hz 64:27 */
1516 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528,
1517 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1518 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1519 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1520 /* 216 - 10240x4320@100Hz 64:27 */
1521 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432,
1522 12608, 13200, 0, 4320, 4336, 4356, 4500, 0,
1523 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1524 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1525 /* 217 - 10240x4320@120Hz 64:27 */
1526 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528,
1527 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1528 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1529 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1530 /* 218 - 4096x2160@100Hz 256:135 */
1531 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896,
1532 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1533 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1534 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
f7655d42
VS		 1535 /* 219 - 4096x2160@120Hz 256:135 */
1536 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184,
1537 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1538 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1539 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
f7655d42
VS		 1540};
1541
7ebe1963 1542/*
d9278b4c 1543 * HDMI 1.4 4k modes. Index using the VIC.
7ebe1963
LD		 1544 */
1545static const struct drm_display_mode edid_4k_modes[] = {
d9278b4c
JN		 1546 /* 0 - dummy, VICs start at 1 */
1547 { },
7ebe1963
LD		 1548 /* 1 - 3840x2160@30Hz */
1549 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1550 3840, 4016, 4104, 4400, 0,
1551 2160, 2168, 2178, 2250, 0,
1552 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1553 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
7ebe1963
LD		 1554 /* 2 - 3840x2160@25Hz */
1555 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1556 3840, 4896, 4984, 5280, 0,
1557 2160, 2168, 2178, 2250, 0,
1558 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1559 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
7ebe1963
LD		 1560 /* 3 - 3840x2160@24Hz */
1561 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1562 3840, 5116, 5204, 5500, 0,
1563 2160, 2168, 2178, 2250, 0,
1564 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1565 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
7ebe1963
LD		 1566 /* 4 - 4096x2160@24Hz (SMPTE) */
1567 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1568 4096, 5116, 5204, 5500, 0,
1569 2160, 2168, 2178, 2250, 0,
1570 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1571 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
7ebe1963
LD		 1572};
1573
61e57a8d 1574/*** DDC fetch and block validation ***/
f453ba04 1575
e4ccf9a7
JN		 1576/*
1577 * The opaque EDID type, internal to drm_edid.c.
1578 */
1579struct drm_edid {
1580 /* Size allocated for edid */
1581 size_t size;
1582 const struct edid *edid;
1583};
1584
18e3c1d5
JN		 1585static int edid_hfeeodb_extension_block_count(const struct edid *edid);
1586
1587static int edid_hfeeodb_block_count(const struct edid *edid)
1588{
1589 int eeodb = edid_hfeeodb_extension_block_count(edid);
1590
1591 return eeodb ? eeodb + 1 : 0;
1592}
1593
f1e4c916
JN		 1594static int edid_extension_block_count(const struct edid *edid)
1595{
1596 return edid->extensions;
1597}
1598
1599static int edid_block_count(const struct edid *edid)
1600{
1601 return edid_extension_block_count(edid) + 1;
1602}
1603
1604static int edid_size_by_blocks(int num_blocks)
1605{
1606 return num_blocks * EDID_LENGTH;
1607}
1608
1609static int edid_size(const struct edid *edid)
1610{
1611 return edid_size_by_blocks(edid_block_count(edid));
1612}
1613
1614static const void *edid_block_data(const struct edid *edid, int index)
1615{
1616 BUILD_BUG_ON(sizeof(*edid) != EDID_LENGTH);
1617
1618 return edid + index;
1619}
1620
1621static const void *edid_extension_block_data(const struct edid *edid, int index)
1622{
1623 return edid_block_data(edid, index + 1);
1624}
1625
b16c9e6c
JN		 1626/* EDID block count indicated in EDID, may exceed allocated size */
1627static int __drm_edid_block_count(const struct drm_edid *drm_edid)
d9307f27
JN		 1628{
1629 int num_blocks;
1630
1631 /* Starting point */
1632 num_blocks = edid_block_count(drm_edid->edid);
1633
b1dee952
JN		 1634 /* HF-EEODB override */
1635 if (drm_edid->size >= edid_size_by_blocks(2)) {
1636 int eeodb;
1637
1638 /*
1639 * Note: HF-EEODB may specify a smaller extension count than the
1640 * regular one. Unlike in buffer allocation, here we can use it.
1641 */
1642 eeodb = edid_hfeeodb_block_count(drm_edid->edid);
1643 if (eeodb)
1644 num_blocks = eeodb;
1645 }
1646
d9307f27
JN		 1647 return num_blocks;
1648}
1649
b16c9e6c
JN		 1650/* EDID block count, limited by allocated size */
1651static int drm_edid_block_count(const struct drm_edid *drm_edid)
1652{
1653 /* Limit by allocated size */
1654 return min(__drm_edid_block_count(drm_edid),
1655 (int)drm_edid->size / EDID_LENGTH);
1656}
1657
1658/* EDID extension block count, limited by allocated size */
d9307f27
JN		 1659static int drm_edid_extension_block_count(const struct drm_edid *drm_edid)
1660{
1661 return drm_edid_block_count(drm_edid) - 1;
1662}
1663
1664static const void *drm_edid_block_data(const struct drm_edid *drm_edid, int index)
1665{
1666 return edid_block_data(drm_edid->edid, index);
1667}
1668
1669static const void *drm_edid_extension_block_data(const struct drm_edid *drm_edid,
1670 int index)
1671{
1672 return edid_extension_block_data(drm_edid->edid, index);
1673}
1674
22a27e05
JN		 1675/*
1676 * Initializer helper for legacy interfaces, where we have no choice but to
1677 * trust edid size. Not for general purpose use.
1678 */
1679static const struct drm_edid *drm_edid_legacy_init(struct drm_edid *drm_edid,
1680 const struct edid *edid)
1681{
1682 if (!edid)
1683 return NULL;
1684
1685 memset(drm_edid, 0, sizeof(*drm_edid));
1686
1687 drm_edid->edid = edid;
1688 drm_edid->size = edid_size(edid);
1689
1690 return drm_edid;
1691}
1692
94afc538
JN		 1693/*
1694 * EDID base and extension block iterator.
1695 *
1696 * struct drm_edid_iter iter;
1697 * const u8 *block;
1698 *
bbded689 1699 * drm_edid_iter_begin(drm_edid, &iter);
94afc538
JN		 1700 * drm_edid_iter_for_each(block, &iter) {
1701 * // do stuff with block
1702 * }
1703 * drm_edid_iter_end(&iter);
1704 */
1705struct drm_edid_iter {
bbded689 1706 const struct drm_edid *drm_edid;
94afc538
JN		 1707
1708 /* Current block index. */
1709 int index;
1710};
1711
bbded689 1712static void drm_edid_iter_begin(const struct drm_edid *drm_edid,
94afc538
JN		 1713 struct drm_edid_iter *iter)
1714{
1715 memset(iter, 0, sizeof(*iter));
1716
bbded689 1717 iter->drm_edid = drm_edid;
94afc538
JN		 1718}
1719
1720static const void *__drm_edid_iter_next(struct drm_edid_iter *iter)
1721{
1722 const void *block = NULL;
1723
bbded689 1724 if (!iter->drm_edid)
94afc538
JN		 1725 return NULL;
1726
d9307f27
JN		 1727 if (iter->index < drm_edid_block_count(iter->drm_edid))
1728 block = drm_edid_block_data(iter->drm_edid, iter->index++);
94afc538
JN		 1729
1730 return block;
1731}
1732
1733#define drm_edid_iter_for_each(__block, __iter) \
1734 while (((__block) = __drm_edid_iter_next(__iter)))
1735
1736static void drm_edid_iter_end(struct drm_edid_iter *iter)
1737{
1738 memset(iter, 0, sizeof(*iter));
1739}
1740
083ae056
AJ		 1741static const u8 edid_header[] = {
1742 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1743};
f453ba04 1744
0a612bbd
JN		 1745static void edid_header_fix(void *edid)
1746{
1747 memcpy(edid, edid_header, sizeof(edid_header));
1748}
1749
db6cf833
TR		 1750/**
1751 * drm_edid_header_is_valid - sanity check the header of the base EDID block
5d96fc9c 1752 * @_edid: pointer to raw base EDID block
db6cf833
TR		 1753 *
1754 * Sanity check the header of the base EDID block.
1755 *
1756 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
051963d4 1757 */
6d987ddd 1758int drm_edid_header_is_valid(const void *_edid)
051963d4 1759{
6d987ddd 1760 const struct edid *edid = _edid;
051963d4
TR		 1761 int i, score = 0;
1762
6d987ddd
JN		 1763 for (i = 0; i < sizeof(edid_header); i++) {
1764 if (edid->header[i] == edid_header[i])
051963d4 1765 score++;
6d987ddd 1766 }
051963d4
TR		 1767
1768 return score;
1769}
1770EXPORT_SYMBOL(drm_edid_header_is_valid);
1771
47819ba2
AJ		 1772static int edid_fixup __read_mostly = 6;
1773module_param_named(edid_fixup, edid_fixup, int, 0400);
1774MODULE_PARM_DESC(edid_fixup,
1775 "Minimum number of valid EDID header bytes (0-8, default 6)");
051963d4 1776
70e49ebe 1777static int edid_block_compute_checksum(const void *_block)
c465bbc8 1778{
70e49ebe 1779 const u8 *block = _block;
c465bbc8 1780 int i;
e11f5bd8
JFZ		 1781 u8 csum = 0, crc = 0;
1782
1783 for (i = 0; i < EDID_LENGTH - 1; i++)
70e49ebe 1784 csum += block[i];
c465bbc8 1785
e11f5bd8
JFZ		 1786 crc = 0x100 - csum;
1787
1788 return crc;
1789}
1790
70e49ebe 1791static int edid_block_get_checksum(const void *_block)
e11f5bd8 1792{
70e49ebe
JN		 1793 const struct edid *block = _block;
1794
1795 return block->checksum;
c465bbc8
SB		 1796}
1797
4ba0f53c
JN		 1798static int edid_block_tag(const void *_block)
1799{
1800 const u8 *block = _block;
1801
1802 return block[0];
1803}
1804
8baccb27 1805static bool edid_block_is_zero(const void *edid)
d6885d65 1806{
8baccb27 1807 return !memchr_inv(edid, 0, EDID_LENGTH);
d6885d65
SB		 1808}
1809
536faa45
SL		 1810/**
1811 * drm_edid_are_equal - compare two edid blobs.
1812 * @edid1: pointer to first blob
1813 * @edid2: pointer to second blob
1814 * This helper can be used during probing to determine if
1815 * edid had changed.
1816 */
1817bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2)
1818{
1819 int edid1_len, edid2_len;
1820 bool edid1_present = edid1 != NULL;
1821 bool edid2_present = edid2 != NULL;
1822
1823 if (edid1_present != edid2_present)
1824 return false;
1825
1826 if (edid1) {
f1e4c916
JN		 1827 edid1_len = edid_size(edid1);
1828 edid2_len = edid_size(edid2);
536faa45
SL		 1829
1830 if (edid1_len != edid2_len)
1831 return false;
1832
1833 if (memcmp(edid1, edid2, edid1_len))
1834 return false;
1835 }
1836
1837 return true;
1838}
1839EXPORT_SYMBOL(drm_edid_are_equal);
1840
1f221284
JN		 1841enum edid_block_status {
1842 EDID_BLOCK_OK = 0,
2deaf1c2 1843 EDID_BLOCK_READ_FAIL,
1f221284 1844 EDID_BLOCK_NULL,
49dc0558 1845 EDID_BLOCK_ZERO,
1f221284
JN		 1846 EDID_BLOCK_HEADER_CORRUPT,
1847 EDID_BLOCK_HEADER_REPAIR,
1848 EDID_BLOCK_HEADER_FIXED,
1849 EDID_BLOCK_CHECKSUM,
1850 EDID_BLOCK_VERSION,
1851};
1852
1853static enum edid_block_status edid_block_check(const void *_block,
1854 bool is_base_block)
1855{
1856 const struct edid *block = _block;
1857
1858 if (!block)
1859 return EDID_BLOCK_NULL;
1860
1861 if (is_base_block) {
1862 int score = drm_edid_header_is_valid(block);
1863
49dc0558
JN		 1864 if (score < clamp(edid_fixup, 0, 8)) {
1865 if (edid_block_is_zero(block))
1866 return EDID_BLOCK_ZERO;
1867 else
1868 return EDID_BLOCK_HEADER_CORRUPT;
1869 }
1f221284
JN		 1870
1871 if (score < 8)
1872 return EDID_BLOCK_HEADER_REPAIR;
1873 }
1874
49dc0558
JN		 1875 if (edid_block_compute_checksum(block) != edid_block_get_checksum(block)) {
1876 if (edid_block_is_zero(block))
1877 return EDID_BLOCK_ZERO;
1878 else
1879 return EDID_BLOCK_CHECKSUM;
1880 }
1f221284
JN		 1881
1882 if (is_base_block) {
1883 if (block->version != 1)
1884 return EDID_BLOCK_VERSION;
1885 }
1886
1887 return EDID_BLOCK_OK;
1888}
1889
1890static bool edid_block_status_valid(enum edid_block_status status, int tag)
1891{
1892 return status == EDID_BLOCK_OK ||
1893 status == EDID_BLOCK_HEADER_FIXED ||
1894 (status == EDID_BLOCK_CHECKSUM && tag == CEA_EXT);
1895}
1896
23e38d7b
JN		 1897static bool edid_block_valid(const void *block, bool base)
1898{
1899 return edid_block_status_valid(edid_block_check(block, base),
1900 edid_block_tag(block));
1901}
1902
cee2ce1a
JN		 1903static void edid_block_status_print(enum edid_block_status status,
1904 const struct edid *block,
1905 int block_num)
1906{
1907 switch (status) {
1908 case EDID_BLOCK_OK:
1909 break;
2deaf1c2
JN		 1910 case EDID_BLOCK_READ_FAIL:
1911 pr_debug("EDID block %d read failed\n", block_num);
1912 break;
cee2ce1a
JN		 1913 case EDID_BLOCK_NULL:
1914 pr_debug("EDID block %d pointer is NULL\n", block_num);
1915 break;
1916 case EDID_BLOCK_ZERO:
1917 pr_notice("EDID block %d is all zeroes\n", block_num);
1918 break;
1919 case EDID_BLOCK_HEADER_CORRUPT:
1920 pr_notice("EDID has corrupt header\n");
1921 break;
1922 case EDID_BLOCK_HEADER_REPAIR:
1923 pr_debug("EDID corrupt header needs repair\n");
1924 break;
1925 case EDID_BLOCK_HEADER_FIXED:
1926 pr_debug("EDID corrupt header fixed\n");
1927 break;
1928 case EDID_BLOCK_CHECKSUM:
1929 if (edid_block_status_valid(status, edid_block_tag(block))) {
1930 pr_debug("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d, ignoring\n",
1931 block_num, edid_block_tag(block),
1932 edid_block_compute_checksum(block));
1933 } else {
1934 pr_notice("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d\n",
1935 block_num, edid_block_tag(block),
1936 edid_block_compute_checksum(block));
1937 }
1938 break;
1939 case EDID_BLOCK_VERSION:
1940 pr_notice("EDID has major version %d, instead of 1\n",
1941 block->version);
1942 break;
1943 default:
1944 WARN(1, "EDID block %d unknown edid block status code %d\n",
1945 block_num, status);
1946 break;
1947 }
1948}
1949
9c7345de
JN		 1950static void edid_block_dump(const char *level, const void *block, int block_num)
1951{
1952 enum edid_block_status status;
1953 char prefix[20];
1954
1955 status = edid_block_check(block, block_num == 0);
1956 if (status == EDID_BLOCK_ZERO)
1957 sprintf(prefix, "\t[%02x] ZERO ", block_num);
1958 else if (!edid_block_status_valid(status, edid_block_tag(block)))
1959 sprintf(prefix, "\t[%02x] BAD ", block_num);
1960 else
1961 sprintf(prefix, "\t[%02x] GOOD ", block_num);
1962
1963 print_hex_dump(level, prefix, DUMP_PREFIX_NONE, 16, 1,
1964 block, EDID_LENGTH, false);
1965}
1966
db6cf833
TR		 1967/**
1968 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
5d96fc9c 1969 * @_block: pointer to raw EDID block
1f221284 1970 * @block_num: type of block to validate (0 for base, extension otherwise)
db6cf833 1971 * @print_bad_edid: if true, dump bad EDID blocks to the console
6ba2bd3d 1972 * @edid_corrupt: if true, the header or checksum is invalid
db6cf833
TR		 1973 *
1974 * Validate a base or extension EDID block and optionally dump bad blocks to
1975 * the console.
1976 *
1977 * Return: True if the block is valid, false otherwise.
f453ba04 1978 */
1f221284 1979bool drm_edid_block_valid(u8 *_block, int block_num, bool print_bad_edid,
6ba2bd3d 1980 bool *edid_corrupt)
f453ba04 1981{
1f221284
JN		 1982 struct edid *block = (struct edid *)_block;
1983 enum edid_block_status status;
1984 bool is_base_block = block_num == 0;
1985 bool valid;
f453ba04 1986
1f221284 1987 if (WARN_ON(!block))
fe2ef780
SWK		 1988 return false;
1989
1f221284
JN		 1990 status = edid_block_check(block, is_base_block);
1991 if (status == EDID_BLOCK_HEADER_REPAIR) {
e1e7bc48 1992 DRM_DEBUG_KMS("Fixing EDID header, your hardware may be failing\n");
1f221284
JN		 1993 edid_header_fix(block);
1994
1995 /* Retry with fixed header, update status if that worked. */
1996 status = edid_block_check(block, is_base_block);
1997 if (status == EDID_BLOCK_OK)
1998 status = EDID_BLOCK_HEADER_FIXED;
61e57a8d 1999 }
f453ba04 2000
1f221284
JN		 2001 if (edid_corrupt) {
2002 /*
2003 * Unknown major version isn't corrupt but we can't use it. Only
2004 * the base block can reset edid_corrupt to false.
2005 */
2006 if (is_base_block &&
2007 (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION))
2008 *edid_corrupt = false;
2009 else if (status != EDID_BLOCK_OK)
ac6f2e29 2010 *edid_corrupt = true;
f453ba04
DA		 2011 }
2012
cee2ce1a
JN		 2013 edid_block_status_print(status, block, block_num);
2014
1f221284
JN		 2015 /* Determine whether we can use this block with this status. */
2016 valid = edid_block_status_valid(status, edid_block_tag(block));
2017
cee2ce1a
JN		 2018 if (!valid && print_bad_edid && status != EDID_BLOCK_ZERO) {
2019 pr_notice("Raw EDID:\n");
9c7345de 2020 edid_block_dump(KERN_NOTICE, block, block_num);
f453ba04 2021 }
1f221284
JN		 2022
2023 return valid;
f453ba04 2024}
da0df92b 2025EXPORT_SYMBOL(drm_edid_block_valid);
61e57a8d
AJ		 2026
2027/**
2028 * drm_edid_is_valid - sanity check EDID data
2029 * @edid: EDID data
2030 *
2031 * Sanity-check an entire EDID record (including extensions)
db6cf833
TR		 2032 *
2033 * Return: True if the EDID data is valid, false otherwise.
61e57a8d
AJ		 2034 */
2035bool drm_edid_is_valid(struct edid *edid)
2036{
2037 int i;
61e57a8d
AJ		 2038
2039 if (!edid)
2040 return false;
2041
f1e4c916
JN		 2042 for (i = 0; i < edid_block_count(edid); i++) {
2043 void *block = (void *)edid_block_data(edid, i);
2044
2045 if (!drm_edid_block_valid(block, i, true, NULL))
61e57a8d 2046 return false;
f1e4c916 2047 }
61e57a8d
AJ		 2048
2049 return true;
2050}
3c537889 2051EXPORT_SYMBOL(drm_edid_is_valid);
f453ba04 2052
6c9b3db7
JN		 2053/**
2054 * drm_edid_valid - sanity check EDID data
2055 * @drm_edid: EDID data
2056 *
2057 * Sanity check an EDID. Cross check block count against allocated size and
2058 * checksum the blocks.
2059 *
2060 * Return: True if the EDID data is valid, false otherwise.
2061 */
2062bool drm_edid_valid(const struct drm_edid *drm_edid)
2063{
2064 int i;
2065
2066 if (!drm_edid)
2067 return false;
2068
2069 if (edid_size_by_blocks(__drm_edid_block_count(drm_edid)) != drm_edid->size)
2070 return false;
2071
2072 for (i = 0; i < drm_edid_block_count(drm_edid); i++) {
2073 const void *block = drm_edid_block_data(drm_edid, i);
2074
2075 if (!edid_block_valid(block, i == 0))
2076 return false;
2077 }
2078
2079 return true;
2080}
2081EXPORT_SYMBOL(drm_edid_valid);
2082
89f4b4c5 2083static struct edid *edid_filter_invalid_blocks(struct edid *edid,
407d63b3 2084 size_t *alloc_size)
4ec53461 2085{
89f4b4c5
JN		 2086 struct edid *new;
2087 int i, valid_blocks = 0;
4ec53461 2088
18e3c1d5
JN		 2089 /*
2090 * Note: If the EDID uses HF-EEODB, but has invalid blocks, we'll revert
2091 * back to regular extension count here. We don't want to start
2092 * modifying the HF-EEODB extension too.
2093 */
89f4b4c5
JN		 2094 for (i = 0; i < edid_block_count(edid); i++) {
2095 const void *src_block = edid_block_data(edid, i);
407d63b3 2096
89f4b4c5
JN		 2097 if (edid_block_valid(src_block, i == 0)) {
2098 void *dst_block = (void *)edid_block_data(edid, valid_blocks);
4ec53461 2099
89f4b4c5
JN		 2100 memmove(dst_block, src_block, EDID_LENGTH);
2101 valid_blocks++;
2102 }
2103 }
4ec53461 2104
89f4b4c5
JN		 2105 /* We already trusted the base block to be valid here... */
2106 if (WARN_ON(!valid_blocks)) {
2107 kfree(edid);
2108 return NULL;
4ec53461
JN		 2109 }
2110
89f4b4c5
JN		 2111 edid->extensions = valid_blocks - 1;
2112 edid->checksum = edid_block_compute_checksum(edid);
4ec53461 2113
89f4b4c5
JN		 2114 *alloc_size = edid_size_by_blocks(valid_blocks);
2115
2116 new = krealloc(edid, *alloc_size, GFP_KERNEL);
2117 if (!new)
2118 kfree(edid);
4ec53461
JN		 2119
2120 return new;
2121}
2122
61e57a8d
AJ		 2123#define DDC_SEGMENT_ADDR 0x30
2124/**
db6cf833 2125 * drm_do_probe_ddc_edid() - get EDID information via I2C
7c58e87e 2126 * @data: I2C device adapter
fc66811c
DV		 2127 * @buf: EDID data buffer to be filled
2128 * @block: 128 byte EDID block to start fetching from
2129 * @len: EDID data buffer length to fetch
2130 *
db6cf833 2131 * Try to fetch EDID information by calling I2C driver functions.
61e57a8d 2132 *
db6cf833 2133 * Return: 0 on success or -1 on failure.
61e57a8d
AJ		 2134 */
2135static int
18df89fe 2136drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
61e57a8d 2137{
18df89fe 2138 struct i2c_adapter *adapter = data;
61e57a8d 2139 unsigned char start = block * EDID_LENGTH;
cd004b3f
S		 2140 unsigned char segment = block >> 1;
2141 unsigned char xfers = segment ? 3 : 2;
4819d2e4
CW		 2142 int ret, retries = 5;
2143
db6cf833
TR		 2144 /*
2145 * The core I2C driver will automatically retry the transfer if the
4819d2e4
CW		 2146 * adapter reports EAGAIN. However, we find that bit-banging transfers
2147 * are susceptible to errors under a heavily loaded machine and
2148 * generate spurious NAKs and timeouts. Retrying the transfer
2149 * of the individual block a few times seems to overcome this.
2150 */
2151 do {
2152 struct i2c_msg msgs[] = {
2153 {
cd004b3f
S		 2154 .addr = DDC_SEGMENT_ADDR,
2155 .flags = 0,
2156 .len = 1,
2157 .buf = &segment,
2158 }, {
4819d2e4
CW		 2159 .addr = DDC_ADDR,
2160 .flags = 0,
2161 .len = 1,
2162 .buf = &start,
2163 }, {
2164 .addr = DDC_ADDR,
2165 .flags = I2C_M_RD,
2166 .len = len,
2167 .buf = buf,
2168 }
2169 };
cd004b3f 2170
db6cf833
TR		 2171 /*
2172 * Avoid sending the segment addr to not upset non-compliant
2173 * DDC monitors.
2174 */
cd004b3f
S		 2175 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
2176
9292f37e
ED		 2177 if (ret == -ENXIO) {
2178 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
2179 adapter->name);
2180 break;
2181 }
cd004b3f 2182 } while (ret != xfers && --retries);
4819d2e4 2183
cd004b3f 2184 return ret == xfers ? 0 : -1;
61e57a8d
AJ		 2185}
2186
14544d09 2187static void connector_bad_edid(struct drm_connector *connector,
63cae081 2188 const struct edid *edid, int num_blocks)
14544d09
CW		 2189{
2190 int i;
97794170
DA		 2191 u8 last_block;
2192
2193 /*
2194 * 0x7e in the EDID is the number of extension blocks. The EDID
2195 * is 1 (base block) + num_ext_blocks big. That means we can think
2196 * of 0x7e in the EDID of the _index_ of the last block in the
2197 * combined chunk of memory.
2198 */
63cae081 2199 last_block = edid->extensions;
e11f5bd8
JFZ		 2200
2201 /* Calculate real checksum for the last edid extension block data */
97794170
DA		 2202 if (last_block < num_blocks)
2203 connector->real_edid_checksum =
63cae081 2204 edid_block_compute_checksum(edid + last_block);
14544d09 2205
f0a8f533 2206 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
14544d09
CW		 2207 return;
2208
66d17ecd
JN		 2209 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID is invalid:\n",
2210 connector->base.id, connector->name);
63cae081
JN		 2211 for (i = 0; i < num_blocks; i++)
2212 edid_block_dump(KERN_DEBUG, edid + i, i);
14544d09
CW		 2213}
2214
56a2b7f2 2215/* Get override or firmware EDID */
794aca0e 2216static const struct drm_edid *drm_edid_override_get(struct drm_connector *connector)
56a2b7f2 2217{
794aca0e 2218 const struct drm_edid *override = NULL;
56a2b7f2 2219
90b575f5
JN		 2220 mutex_lock(&connector->edid_override_mutex);
2221
2222 if (connector->edid_override)
794aca0e 2223 override = drm_edid_dup(connector->edid_override);
90b575f5
JN		 2224
2225 mutex_unlock(&connector->edid_override_mutex);
56a2b7f2
JN		 2226
2227 if (!override)
a05992d5 2228 override = drm_edid_load_firmware(connector);
56a2b7f2
JN		 2229
2230 return IS_ERR(override) ? NULL : override;
2231}
2232
91ec9ab4
JN		 2233/* For debugfs edid_override implementation */
2234int drm_edid_override_show(struct drm_connector *connector, struct seq_file *m)
2235{
90b575f5 2236 const struct drm_edid *drm_edid;
91ec9ab4 2237
90b575f5
JN		 2238 mutex_lock(&connector->edid_override_mutex);
2239
2240 drm_edid = connector->edid_override;
2241 if (drm_edid)
2242 seq_write(m, drm_edid->edid, drm_edid->size);
2243
2244 mutex_unlock(&connector->edid_override_mutex);
91ec9ab4
JN		 2245
2246 return 0;
2247}
2248
6aa145bc
JN		 2249/* For debugfs edid_override implementation */
2250int drm_edid_override_set(struct drm_connector *connector, const void *edid,
2251 size_t size)
2252{
90b575f5 2253 const struct drm_edid *drm_edid;
6aa145bc 2254
90b575f5
JN		 2255 drm_edid = drm_edid_alloc(edid, size);
2256 if (!drm_edid_valid(drm_edid)) {
2257 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override invalid\n",
2258 connector->base.id, connector->name);
2259 drm_edid_free(drm_edid);
6aa145bc 2260 return -EINVAL;
90b575f5 2261 }
6aa145bc 2262
2c9332de
JN		 2263 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override set\n",
2264 connector->base.id, connector->name);
2265
90b575f5 2266 mutex_lock(&connector->edid_override_mutex);
6aa145bc 2267
90b575f5
JN		 2268 drm_edid_free(connector->edid_override);
2269 connector->edid_override = drm_edid;
2270
2271 mutex_unlock(&connector->edid_override_mutex);
2272
2273 return 0;
6aa145bc
JN		 2274}
2275
2276/* For debugfs edid_override implementation */
2277int drm_edid_override_reset(struct drm_connector *connector)
2278{
2c9332de
JN		 2279 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override reset\n",
2280 connector->base.id, connector->name);
2281
90b575f5
JN		 2282 mutex_lock(&connector->edid_override_mutex);
2283
2284 drm_edid_free(connector->edid_override);
2285 connector->edid_override = NULL;
2286
2287 mutex_unlock(&connector->edid_override_mutex);
2288
2289 return 0;
6aa145bc
JN		 2290}
2291
48eaeb76 2292/**
019b9387 2293 * drm_edid_override_connector_update - add modes from override/firmware EDID
48eaeb76
JN		 2294 * @connector: connector we're probing
2295 *
2296 * Add modes from the override/firmware EDID, if available. Only to be used from
2297 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
2298 * failed during drm_get_edid() and caused the override/firmware EDID to be
2299 * skipped.
2300 *
2301 * Return: The number of modes added or 0 if we couldn't find any.
2302 */
019b9387 2303int drm_edid_override_connector_update(struct drm_connector *connector)
48eaeb76 2304{
794aca0e 2305 const struct drm_edid *override;
48eaeb76
JN		 2306 int num_modes = 0;
2307
794aca0e 2308 override = drm_edid_override_get(connector);
48eaeb76 2309 if (override) {
794aca0e
JN		 2310 num_modes = drm_edid_connector_update(connector, override);
2311
2312 drm_edid_free(override);
48eaeb76 2313
e1e7bc48
JN		 2314 drm_dbg_kms(connector->dev,
2315 "[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
2316 connector->base.id, connector->name, num_modes);
48eaeb76
JN		 2317 }
2318
2319 return num_modes;
2320}
019b9387 2321EXPORT_SYMBOL(drm_edid_override_connector_update);
48eaeb76 2322
89fb7536
JN		 2323typedef int read_block_fn(void *context, u8 *buf, unsigned int block, size_t len);
2324
2deaf1c2
JN		 2325static enum edid_block_status edid_block_read(void *block, unsigned int block_num,
2326 read_block_fn read_block,
2327 void *context)
2328{
2329 enum edid_block_status status;
2330 bool is_base_block = block_num == 0;
2331 int try;
2332
2333 for (try = 0; try < 4; try++) {
2334 if (read_block(context, block, block_num, EDID_LENGTH))
2335 return EDID_BLOCK_READ_FAIL;
2336
2337 status = edid_block_check(block, is_base_block);
2338 if (status == EDID_BLOCK_HEADER_REPAIR) {
2339 edid_header_fix(block);
2340
2341 /* Retry with fixed header, update status if that worked. */
2342 status = edid_block_check(block, is_base_block);
2343 if (status == EDID_BLOCK_OK)
2344 status = EDID_BLOCK_HEADER_FIXED;
2345 }
2346
2347 if (edid_block_status_valid(status, edid_block_tag(block)))
2348 break;
2349
2350 /* Fail early for unrepairable base block all zeros. */
2351 if (try == 0 && is_base_block && status == EDID_BLOCK_ZERO)
2352 break;
2353 }
2354
2355 return status;
2356}
2357
6537f79a
JN		 2358static struct edid *_drm_do_get_edid(struct drm_connector *connector,
2359 read_block_fn read_block, void *context,
2360 size_t *size)
61e57a8d 2361{
c12561ce 2362 enum edid_block_status status;
18e3c1d5 2363 int i, num_blocks, invalid_blocks = 0;
794aca0e 2364 const struct drm_edid *override;
b3eb97b6 2365 struct edid *edid, *new;
407d63b3 2366 size_t alloc_size = EDID_LENGTH;
53fd40a9 2367
794aca0e
JN		 2368 override = drm_edid_override_get(connector);
2369 if (override) {
2370 alloc_size = override->size;
2371 edid = kmemdup(override->edid, alloc_size, GFP_KERNEL);
2372 drm_edid_free(override);
2373 if (!edid)
2374 return NULL;
1c788f69 2375 goto ok;
794aca0e 2376 }
61e57a8d 2377
407d63b3 2378 edid = kmalloc(alloc_size, GFP_KERNEL);
e7bd95a7 2379 if (!edid)
61e57a8d 2380 return NULL;
61e57a8d 2381
c12561ce
JN		 2382 status = edid_block_read(edid, 0, read_block, context);
2383
2384 edid_block_status_print(status, edid, 0);
2385
2386 if (status == EDID_BLOCK_READ_FAIL)
1c788f69 2387 goto fail;
c12561ce
JN		 2388
2389 /* FIXME: Clarify what a corrupt EDID actually means. */
2390 if (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION)
2391 connector->edid_corrupt = false;
2392 else
2393 connector->edid_corrupt = true;
2394
2395 if (!edid_block_status_valid(status, edid_block_tag(edid))) {
2396 if (status == EDID_BLOCK_ZERO)
2397 connector->null_edid_counter++;
2398
2399 connector_bad_edid(connector, edid, 1);
1c788f69 2400 goto fail;
c12561ce
JN		 2401 }
2402
f1e4c916 2403 if (!edid_extension_block_count(edid))
1c788f69 2404 goto ok;
61e57a8d 2405
407d63b3
JN		 2406 alloc_size = edid_size(edid);
2407 new = krealloc(edid, alloc_size, GFP_KERNEL);
61e57a8d 2408 if (!new)
1c788f69 2409 goto fail;
f14f3686 2410 edid = new;
61e57a8d 2411
18e3c1d5
JN		 2412 num_blocks = edid_block_count(edid);
2413 for (i = 1; i < num_blocks; i++) {
f1e4c916 2414 void *block = (void *)edid_block_data(edid, i);
a28187cc 2415
f1e4c916 2416 status = edid_block_read(block, i, read_block, context);
d3da3f40 2417
f1e4c916 2418 edid_block_status_print(status, block, i);
f934ec8c 2419
d3da3f40
JN		 2420 if (!edid_block_status_valid(status, edid_block_tag(block))) {
2421 if (status == EDID_BLOCK_READ_FAIL)
1c788f69 2422 goto fail;
ccc97def 2423 invalid_blocks++;
18e3c1d5
JN		 2424 } else if (i == 1) {
2425 /*
2426 * If the first EDID extension is a CTA extension, and
2427 * the first Data Block is HF-EEODB, override the
2428 * extension block count.
2429 *
2430 * Note: HF-EEODB could specify a smaller extension
2431 * count too, but we can't risk allocating a smaller
2432 * amount.
2433 */
2434 int eeodb = edid_hfeeodb_block_count(edid);
2435
2436 if (eeodb > num_blocks) {
2437 num_blocks = eeodb;
2438 alloc_size = edid_size_by_blocks(num_blocks);
2439 new = krealloc(edid, alloc_size, GFP_KERNEL);
2440 if (!new)
2441 goto fail;
2442 edid = new;
2443 }
d3da3f40 2444 }
0ea75e23
ST		 2445 }
2446
ccc97def 2447 if (invalid_blocks) {
18e3c1d5 2448 connector_bad_edid(connector, edid, num_blocks);
14544d09 2449
89f4b4c5 2450 edid = edid_filter_invalid_blocks(edid, &alloc_size);
61e57a8d
AJ		 2451 }
2452
1c788f69 2453ok:
6537f79a
JN		 2454 if (size)
2455 *size = alloc_size;
2456
e9a9e076 2457 return edid;
61e57a8d 2458
1c788f69 2459fail:
f14f3686 2460 kfree(edid);
61e57a8d
AJ		 2461 return NULL;
2462}
6537f79a
JN		 2463
2464/**
2465 * drm_do_get_edid - get EDID data using a custom EDID block read function
2466 * @connector: connector we're probing
2467 * @read_block: EDID block read function
2468 * @context: private data passed to the block read function
2469 *
2470 * When the I2C adapter connected to the DDC bus is hidden behind a device that
2471 * exposes a different interface to read EDID blocks this function can be used
2472 * to get EDID data using a custom block read function.
2473 *
2474 * As in the general case the DDC bus is accessible by the kernel at the I2C
2475 * level, drivers must make all reasonable efforts to expose it as an I2C
2476 * adapter and use drm_get_edid() instead of abusing this function.
2477 *
2478 * The EDID may be overridden using debugfs override_edid or firmware EDID
a05992d5 2479 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
6537f79a
JN		 2480 * order. Having either of them bypasses actual EDID reads.
2481 *
2482 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2483 */
2484struct edid *drm_do_get_edid(struct drm_connector *connector,
2485 read_block_fn read_block,
2486 void *context)
2487{
2488 return _drm_do_get_edid(connector, read_block, context, NULL);
2489}
18df89fe 2490EXPORT_SYMBOL_GPL(drm_do_get_edid);
61e57a8d 2491
3d1ab66e
JN		 2492/**
2493 * drm_edid_raw - Get a pointer to the raw EDID data.
2494 * @drm_edid: drm_edid container
2495 *
2496 * Get a pointer to the raw EDID data.
2497 *
2498 * This is for transition only. Avoid using this like the plague.
2499 *
2500 * Return: Pointer to raw EDID data.
2501 */
2502const struct edid *drm_edid_raw(const struct drm_edid *drm_edid)
2503{
2504 if (!drm_edid || !drm_edid->size)
2505 return NULL;
2506
2507 /*
2508 * Do not return pointers where relying on EDID extension count would
2509 * lead to buffer overflow.
2510 */
2511 if (WARN_ON(edid_size(drm_edid->edid) > drm_edid->size))
2512 return NULL;
2513
2514 return drm_edid->edid;
2515}
2516EXPORT_SYMBOL(drm_edid_raw);
2517
6537f79a
JN		 2518/* Allocate struct drm_edid container *without* duplicating the edid data */
2519static const struct drm_edid *_drm_edid_alloc(const void *edid, size_t size)
2520{
2521 struct drm_edid *drm_edid;
2522
2523 if (!edid || !size || size < EDID_LENGTH)
2524 return NULL;
2525
2526 drm_edid = kzalloc(sizeof(*drm_edid), GFP_KERNEL);
2527 if (drm_edid) {
2528 drm_edid->edid = edid;
2529 drm_edid->size = size;
2530 }
2531
2532 return drm_edid;
2533}
2534
2535/**
2536 * drm_edid_alloc - Allocate a new drm_edid container
2537 * @edid: Pointer to raw EDID data
2538 * @size: Size of memory allocated for EDID
2539 *
2540 * Allocate a new drm_edid container. Do not calculate edid size from edid, pass
2541 * the actual size that has been allocated for the data. There is no validation
2542 * of the raw EDID data against the size, but at least the EDID base block must
2543 * fit in the buffer.
2544 *
2545 * The returned pointer must be freed using drm_edid_free().
2546 *
2547 * Return: drm_edid container, or NULL on errors
2548 */
2549const struct drm_edid *drm_edid_alloc(const void *edid, size_t size)
2550{
2551 const struct drm_edid *drm_edid;
2552
2553 if (!edid || !size || size < EDID_LENGTH)
2554 return NULL;
2555
2556 edid = kmemdup(edid, size, GFP_KERNEL);
2557 if (!edid)
2558 return NULL;
2559
2560 drm_edid = _drm_edid_alloc(edid, size);
2561 if (!drm_edid)
2562 kfree(edid);
2563
2564 return drm_edid;
2565}
2566EXPORT_SYMBOL(drm_edid_alloc);
2567
2568/**
2569 * drm_edid_dup - Duplicate a drm_edid container
2570 * @drm_edid: EDID to duplicate
2571 *
2572 * The returned pointer must be freed using drm_edid_free().
2573 *
2574 * Returns: drm_edid container copy, or NULL on errors
2575 */
2576const struct drm_edid *drm_edid_dup(const struct drm_edid *drm_edid)
2577{
2578 if (!drm_edid)
2579 return NULL;
2580
2581 return drm_edid_alloc(drm_edid->edid, drm_edid->size);
2582}
2583EXPORT_SYMBOL(drm_edid_dup);
2584
2585/**
2586 * drm_edid_free - Free the drm_edid container
2587 * @drm_edid: EDID to free
2588 */
2589void drm_edid_free(const struct drm_edid *drm_edid)
2590{
2591 if (!drm_edid)
2592 return;
2593
2594 kfree(drm_edid->edid);
2595 kfree(drm_edid);
2596}
2597EXPORT_SYMBOL(drm_edid_free);
2598
61e57a8d 2599/**
db6cf833
TR		 2600 * drm_probe_ddc() - probe DDC presence
2601 * @adapter: I2C adapter to probe
fc66811c 2602 *
db6cf833 2603 * Return: True on success, false on failure.
61e57a8d 2604 */
fbff4690 2605bool
61e57a8d
AJ		 2606drm_probe_ddc(struct i2c_adapter *adapter)
2607{
2608 unsigned char out;
2609
2610 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
2611}
fbff4690 2612EXPORT_SYMBOL(drm_probe_ddc);
61e57a8d
AJ		 2613
2614/**
2615 * drm_get_edid - get EDID data, if available
2616 * @connector: connector we're probing
db6cf833 2617 * @adapter: I2C adapter to use for DDC
61e57a8d 2618 *
db6cf833 2619 * Poke the given I2C channel to grab EDID data if possible. If found,
61e57a8d
AJ		 2620 * attach it to the connector.
2621 *
db6cf833 2622 * Return: Pointer to valid EDID or NULL if we couldn't find any.
61e57a8d
AJ		 2623 */
2624struct edid *drm_get_edid(struct drm_connector *connector,
2625 struct i2c_adapter *adapter)
2626{
5186421c
SL		 2627 struct edid *edid;
2628
15f080f0
JN		 2629 if (connector->force == DRM_FORCE_OFF)
2630 return NULL;
2631
2632 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
18df89fe 2633 return NULL;
61e57a8d 2634
6537f79a 2635 edid = _drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter, NULL);
5186421c
SL		 2636 drm_connector_update_edid_property(connector, edid);
2637 return edid;
61e57a8d
AJ		 2638}
2639EXPORT_SYMBOL(drm_get_edid);
2640
6537f79a
JN		 2641/**
2642 * drm_edid_read_custom - Read EDID data using given EDID block read function
2643 * @connector: Connector to use
2644 * @read_block: EDID block read function
2645 * @context: Private data passed to the block read function
2646 *
2647 * When the I2C adapter connected to the DDC bus is hidden behind a device that
2648 * exposes a different interface to read EDID blocks this function can be used
2649 * to get EDID data using a custom block read function.
2650 *
2651 * As in the general case the DDC bus is accessible by the kernel at the I2C
2652 * level, drivers must make all reasonable efforts to expose it as an I2C
2653 * adapter and use drm_edid_read() or drm_edid_read_ddc() instead of abusing
2654 * this function.
2655 *
2656 * The EDID may be overridden using debugfs override_edid or firmware EDID
a05992d5 2657 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
6537f79a
JN		 2658 * order. Having either of them bypasses actual EDID reads.
2659 *
2660 * The returned pointer must be freed using drm_edid_free().
2661 *
2662 * Return: Pointer to EDID, or NULL if probe/read failed.
2663 */
2664const struct drm_edid *drm_edid_read_custom(struct drm_connector *connector,
2665 read_block_fn read_block,
2666 void *context)
2667{
2668 const struct drm_edid *drm_edid;
2669 struct edid *edid;
2670 size_t size = 0;
2671
2672 edid = _drm_do_get_edid(connector, read_block, context, &size);
2673 if (!edid)
2674 return NULL;
2675
2676 /* Sanity check for now */
2677 drm_WARN_ON(connector->dev, !size);
2678
2679 drm_edid = _drm_edid_alloc(edid, size);
2680 if (!drm_edid)
2681 kfree(edid);
2682
2683 return drm_edid;
2684}
2685EXPORT_SYMBOL(drm_edid_read_custom);
2686
2687/**
2688 * drm_edid_read_ddc - Read EDID data using given I2C adapter
2689 * @connector: Connector to use
2690 * @adapter: I2C adapter to use for DDC
2691 *
2692 * Read EDID using the given I2C adapter.
2693 *
2694 * The EDID may be overridden using debugfs override_edid or firmware EDID
a05992d5 2695 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
6537f79a
JN		 2696 * order. Having either of them bypasses actual EDID reads.
2697 *
2698 * Prefer initializing connector->ddc with drm_connector_init_with_ddc() and
2699 * using drm_edid_read() instead of this function.
2700 *
2701 * The returned pointer must be freed using drm_edid_free().
2702 *
2703 * Return: Pointer to EDID, or NULL if probe/read failed.
2704 */
2705const struct drm_edid *drm_edid_read_ddc(struct drm_connector *connector,
2706 struct i2c_adapter *adapter)
2707{
2708 const struct drm_edid *drm_edid;
2709
2710 if (connector->force == DRM_FORCE_OFF)
2711 return NULL;
2712
2713 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2714 return NULL;
2715
2716 drm_edid = drm_edid_read_custom(connector, drm_do_probe_ddc_edid, adapter);
2717
2718 /* Note: Do *not* call connector updates here. */
2719
2720 return drm_edid;
2721}
2722EXPORT_SYMBOL(drm_edid_read_ddc);
2723
2724/**
2725 * drm_edid_read - Read EDID data using connector's I2C adapter
2726 * @connector: Connector to use
2727 *
2728 * Read EDID using the connector's I2C adapter.
2729 *
2730 * The EDID may be overridden using debugfs override_edid or firmware EDID
a05992d5 2731 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
6537f79a
JN		 2732 * order. Having either of them bypasses actual EDID reads.
2733 *
2734 * The returned pointer must be freed using drm_edid_free().
2735 *
2736 * Return: Pointer to EDID, or NULL if probe/read failed.
2737 */
2738const struct drm_edid *drm_edid_read(struct drm_connector *connector)
2739{
2740 if (drm_WARN_ON(connector->dev, !connector->ddc))
2741 return NULL;
2742
2743 return drm_edid_read_ddc(connector, connector->ddc);
2744}
2745EXPORT_SYMBOL(drm_edid_read);
2746
d9f91a10
DA		 2747static u32 edid_extract_panel_id(const struct edid *edid)
2748{
2749 /*
e8de4d55
DA		 2750 * We represent the ID as a 32-bit number so it can easily be compared
2751 * with "==".
d9f91a10
DA		 2752 *
2753 * NOTE that we deal with endianness differently for the top half
2754 * of this ID than for the bottom half. The bottom half (the product
2755 * id) gets decoded as little endian by the EDID_PRODUCT_ID because
2756 * that's how everyone seems to interpret it. The top half (the mfg_id)
2757 * gets stored as big endian because that makes
2758 * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier
2759 * to write (it's easier to extract the ASCII). It doesn't really
2760 * matter, though, as long as the number here is unique.
2761 */
2762 return (u32)edid->mfg_id[0] << 24 |
2763 (u32)edid->mfg_id[1] << 16 |
2764 (u32)EDID_PRODUCT_ID(edid);
2765}
2766
2767/**
2768 * drm_edid_get_panel_id - Get a panel's ID through DDC
2769 * @adapter: I2C adapter to use for DDC
2770 *
2771 * This function reads the first block of the EDID of a panel and (assuming
2772 * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value
2773 * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's
2774 * supposed to be different for each different modem of panel.
2775 *
2776 * This function is intended to be used during early probing on devices where
2777 * more than one panel might be present. Because of its intended use it must
2778 * assume that the EDID of the panel is correct, at least as far as the ID
2779 * is concerned (in other words, we don't process any overrides here).
2780 *
2781 * NOTE: it's expected that this function and drm_do_get_edid() will both
2782 * be read the EDID, but there is no caching between them. Since we're only
2783 * reading the first block, hopefully this extra overhead won't be too big.
2784 *
2785 * Return: A 32-bit ID that should be different for each make/model of panel.
2786 * See the functions drm_edid_encode_panel_id() and
2787 * drm_edid_decode_panel_id() for some details on the structure of this
2788 * ID.
2789 */
2790
2791u32 drm_edid_get_panel_id(struct i2c_adapter *adapter)
2792{
2deaf1c2
JN		 2793 enum edid_block_status status;
2794 void *base_block;
2795 u32 panel_id = 0;
d9f91a10
DA		 2796
2797 /*
2798 * There are no manufacturer IDs of 0, so if there is a problem reading
2799 * the EDID then we'll just return 0.
2800 */
2deaf1c2 2801
4d8457fe 2802 base_block = kzalloc(EDID_LENGTH, GFP_KERNEL);
2deaf1c2 2803 if (!base_block)
d9f91a10
DA		 2804 return 0;
2805
2deaf1c2
JN		 2806 status = edid_block_read(base_block, 0, drm_do_probe_ddc_edid, adapter);
2807
2808 edid_block_status_print(status, base_block, 0);
2809
2810 if (edid_block_status_valid(status, edid_block_tag(base_block)))
2811 panel_id = edid_extract_panel_id(base_block);
69c7717c
DA		 2812 else
2813 edid_block_dump(KERN_NOTICE, base_block, 0);
2deaf1c2
JN		 2814
2815 kfree(base_block);
d9f91a10
DA		 2816
2817 return panel_id;
2818}
2819EXPORT_SYMBOL(drm_edid_get_panel_id);
2820
5cb8eaa2
LW		 2821/**
2822 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
2823 * @connector: connector we're probing
2824 * @adapter: I2C adapter to use for DDC
2825 *
2826 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
2827 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
2828 * switch DDC to the GPU which is retrieving EDID.
2829 *
2830 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2831 */
2832struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
2833 struct i2c_adapter *adapter)
2834{
36b73b05
TZ		 2835 struct drm_device *dev = connector->dev;
2836 struct pci_dev *pdev = to_pci_dev(dev->dev);
5cb8eaa2
LW		 2837 struct edid *edid;
2838
36b73b05
TZ		 2839 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev)))
2840 return NULL;
2841
5cb8eaa2
LW		 2842 vga_switcheroo_lock_ddc(pdev);
2843 edid = drm_get_edid(connector, adapter);
2844 vga_switcheroo_unlock_ddc(pdev);
2845
2846 return edid;
2847}
2848EXPORT_SYMBOL(drm_get_edid_switcheroo);
2849
6c46f644
JN		 2850/**
2851 * drm_edid_read_switcheroo - get EDID data for a vga_switcheroo output
2852 * @connector: connector we're probing
2853 * @adapter: I2C adapter to use for DDC
2854 *
2855 * Wrapper around drm_edid_read_ddc() for laptops with dual GPUs using one set
2856 * of outputs. The wrapper adds the requisite vga_switcheroo calls to
2857 * temporarily switch DDC to the GPU which is retrieving EDID.
2858 *
2859 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2860 */
2861const struct drm_edid *drm_edid_read_switcheroo(struct drm_connector *connector,
2862 struct i2c_adapter *adapter)
2863{
2864 struct drm_device *dev = connector->dev;
2865 struct pci_dev *pdev = to_pci_dev(dev->dev);
2866 const struct drm_edid *drm_edid;
2867
2868 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev)))
2869 return NULL;
2870
2871 vga_switcheroo_lock_ddc(pdev);
2872 drm_edid = drm_edid_read_ddc(connector, adapter);
2873 vga_switcheroo_unlock_ddc(pdev);
2874
2875 return drm_edid;
2876}
2877EXPORT_SYMBOL(drm_edid_read_switcheroo);
2878
51f8da59
JN		 2879/**
2880 * drm_edid_duplicate - duplicate an EDID and the extensions
2881 * @edid: EDID to duplicate
2882 *
db6cf833 2883 * Return: Pointer to duplicated EDID or NULL on allocation failure.
51f8da59
JN		 2884 */
2885struct edid *drm_edid_duplicate(const struct edid *edid)
2886{
d60d2bcc
JN		 2887 if (!edid)
2888 return NULL;
2889
f1e4c916 2890 return kmemdup(edid, edid_size(edid), GFP_KERNEL);
51f8da59
JN		 2891}
2892EXPORT_SYMBOL(drm_edid_duplicate);
2893
61e57a8d
AJ		 2894/*** EDID parsing ***/
2895
f453ba04
DA		 2896/**
2897 * edid_get_quirks - return quirk flags for a given EDID
e42192b4 2898 * @drm_edid: EDID to process
f453ba04
DA		 2899 *
2900 * This tells subsequent routines what fixes they need to apply.
2901 */
e42192b4 2902static u32 edid_get_quirks(const struct drm_edid *drm_edid)
f453ba04 2903{
e42192b4 2904 u32 panel_id = edid_extract_panel_id(drm_edid->edid);
23c4cfbd 2905 const struct edid_quirk *quirk;
f453ba04
DA		 2906 int i;
2907
2908 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
2909 quirk = &edid_quirk_list[i];
e8de4d55 2910 if (quirk->panel_id == panel_id)
f453ba04
DA		 2911 return quirk->quirks;
2912 }
2913
2914 return 0;
2915}
2916
2917#define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
339d202c 2918#define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
f453ba04 2919
17edb8e1
JN		 2920/*
2921 * Walk the mode list for connector, clearing the preferred status on existing
2922 * modes and setting it anew for the right mode ala quirks.
f453ba04 2923 */
4959b693 2924static void edid_fixup_preferred(struct drm_connector *connector)
f453ba04 2925{
4959b693 2926 const struct drm_display_info *info = &connector->display_info;
f453ba04 2927 struct drm_display_mode *t, *cur_mode, *preferred_mode;
f890607b 2928 int target_refresh = 0;
339d202c 2929 int cur_vrefresh, preferred_vrefresh;
f453ba04
DA		 2930
2931 if (list_empty(&connector->probed_modes))
2932 return;
2933
4959b693 2934 if (info->quirks & EDID_QUIRK_PREFER_LARGE_60)
f453ba04 2935 target_refresh = 60;
4959b693 2936 if (info->quirks & EDID_QUIRK_PREFER_LARGE_75)
f453ba04
DA		 2937 target_refresh = 75;
2938
2939 preferred_mode = list_first_entry(&connector->probed_modes,
2940 struct drm_display_mode, head);
2941
2942 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
2943 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
2944
2945 if (cur_mode == preferred_mode)
2946 continue;
2947
2948 /* Largest mode is preferred */
2949 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
2950 preferred_mode = cur_mode;
2951
0425662f
VS		 2952 cur_vrefresh = drm_mode_vrefresh(cur_mode);
2953 preferred_vrefresh = drm_mode_vrefresh(preferred_mode);
f453ba04
DA		 2954 /* At a given size, try to get closest to target refresh */
2955 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
339d202c
AD		 2956 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
2957 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
f453ba04
DA		 2958 preferred_mode = cur_mode;
2959 }
2960 }
2961
2962 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
2963}
2964
f6e252ba
AJ		 2965static bool
2966mode_is_rb(const struct drm_display_mode *mode)
2967{
2968 return (mode->htotal - mode->hdisplay == 160) &&
2969 (mode->hsync_end - mode->hdisplay == 80) &&
2970 (mode->hsync_end - mode->hsync_start == 32) &&
2971 (mode->vsync_start - mode->vdisplay == 3);
2972}
2973
33c7531d
AJ		 2974/*
2975 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
2976 * @dev: Device to duplicate against
2977 * @hsize: Mode width
2978 * @vsize: Mode height
2979 * @fresh: Mode refresh rate
f6e252ba 2980 * @rb: Mode reduced-blanking-ness
33c7531d
AJ		 2981 *
2982 * Walk the DMT mode list looking for a match for the given parameters.
db6cf833
TR		 2983 *
2984 * Return: A newly allocated copy of the mode, or NULL if not found.
33c7531d 2985 */
1d42bbc8 2986struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
f6e252ba
AJ		 2987 int hsize, int vsize, int fresh,
2988 bool rb)
559ee21d 2989{
07a5e632 2990 int i;
559ee21d 2991
a6b21831 2992 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
b1f559ec 2993 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
948de842 2994
f8b46a05
AJ		 2995 if (hsize != ptr->hdisplay)
2996 continue;
2997 if (vsize != ptr->vdisplay)
2998 continue;
2999 if (fresh != drm_mode_vrefresh(ptr))
3000 continue;
f6e252ba
AJ		 3001 if (rb != mode_is_rb(ptr))
3002 continue;
f8b46a05
AJ		 3003
3004 return drm_mode_duplicate(dev, ptr);
559ee21d 3005 }
f8b46a05
AJ		 3006
3007 return NULL;
559ee21d 3008}
1d42bbc8 3009EXPORT_SYMBOL(drm_mode_find_dmt);
23425cae 3010
e379814b 3011static bool is_display_descriptor(const struct detailed_timing *descriptor, u8 type)
a7a131ac 3012{
e379814b
JN		 3013 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
3014 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.pad1) != 2);
3015 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.type) != 3);
3016
3017 return descriptor->pixel_clock == 0 &&
3018 descriptor->data.other_data.pad1 == 0 &&
3019 descriptor->data.other_data.type == type;
a7a131ac
VS		 3020}
3021
a9b1f15f 3022static bool is_detailed_timing_descriptor(const struct detailed_timing *descriptor)
f447dd1f 3023{
a9b1f15f
JN		 3024 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
3025
3026 return descriptor->pixel_clock != 0;
f447dd1f
VS		 3027}
3028
4194442d 3029typedef void detailed_cb(const struct detailed_timing *timing, void *closure);
d1ff6409 3030
4d76a221 3031static void
eed628f1 3032cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
4d76a221 3033{
7304b981 3034 int i, n;
4966b2a9 3035 u8 d = ext[0x02];
eed628f1 3036 const u8 *det_base = ext + d;
4d76a221 3037
7304b981
VS		 3038 if (d < 4 || d > 127)
3039 return;
3040
4966b2a9 3041 n = (127 - d) / 18;
4d76a221 3042 for (i = 0; i < n; i++)
eed628f1 3043 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
4d76a221
AJ		 3044}
3045
cbba98f8 3046static void
eed628f1 3047vtb_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
cbba98f8
AJ		 3048{
3049 unsigned int i, n = min((int)ext[0x02], 6);
eed628f1 3050 const u8 *det_base = ext + 5;
cbba98f8
AJ		 3051
3052 if (ext[0x01] != 1)
3053 return; /* unknown version */
3054
3055 for (i = 0; i < n; i++)
eed628f1 3056 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
cbba98f8
AJ		 3057}
3058
45aa2336
JN		 3059static void drm_for_each_detailed_block(const struct drm_edid *drm_edid,
3060 detailed_cb *cb, void *closure)
d1ff6409 3061{
ab1747cc
JN		 3062 struct drm_edid_iter edid_iter;
3063 const u8 *ext;
d1ff6409 3064 int i;
d1ff6409 3065
45aa2336 3066 if (!drm_edid)
d1ff6409
AJ		 3067 return;
3068
3069 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
45aa2336 3070 cb(&drm_edid->edid->detailed_timings[i], closure);
d1ff6409 3071
bbded689 3072 drm_edid_iter_begin(drm_edid, &edid_iter);
ab1747cc 3073 drm_edid_iter_for_each(ext, &edid_iter) {
4d76a221
AJ		 3074 switch (*ext) {
3075 case CEA_EXT:
3076 cea_for_each_detailed_block(ext, cb, closure);
3077 break;
cbba98f8
AJ		 3078 case VTB_EXT:
3079 vtb_for_each_detailed_block(ext, cb, closure);
3080 break;
4d76a221
AJ		 3081 default:
3082 break;
3083 }
3084 }
ab1747cc 3085 drm_edid_iter_end(&edid_iter);
d1ff6409
AJ		 3086}
3087
3088static void
4194442d 3089is_rb(const struct detailed_timing *descriptor, void *data)
d1ff6409 3090{
90fd588f 3091 bool *res = data;
a7a131ac 3092
90fd588f 3093 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
a7a131ac
VS		 3094 return;
3095
90fd588f
JN		 3096 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3097 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.cvt.flags) != 15);
3098
3099 if (descriptor->data.other_data.data.range.flags == DRM_EDID_CVT_SUPPORT_FLAG &&
afd4429e 3100 descriptor->data.other_data.data.range.formula.cvt.flags & DRM_EDID_CVT_FLAGS_REDUCED_BLANKING)
90fd588f 3101 *res = true;
d1ff6409
AJ		 3102}
3103
3104/* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
3105static bool
874d98ee 3106drm_monitor_supports_rb(const struct drm_edid *drm_edid)
d1ff6409 3107{
874d98ee 3108 if (drm_edid->edid->revision >= 4) {
b196a498 3109 bool ret = false;
948de842 3110
45aa2336 3111 drm_for_each_detailed_block(drm_edid, is_rb, &ret);
d1ff6409
AJ		 3112 return ret;
3113 }
3114
7218779e 3115 return drm_edid_is_digital(drm_edid);
d1ff6409
AJ		 3116}
3117
7a374350 3118static void
4194442d 3119find_gtf2(const struct detailed_timing *descriptor, void *data)
7a374350 3120{
4194442d 3121 const struct detailed_timing **res = data;
a7a131ac 3122
c8a4beba 3123 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
a7a131ac
VS		 3124 return;
3125
c8a4beba
JN		 3126 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3127
afd4429e 3128 if (descriptor->data.other_data.data.range.flags == DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG)
c8a4beba 3129 *res = descriptor;
7a374350
AJ		 3130}
3131
3132/* Secondary GTF curve kicks in above some break frequency */
3133static int
67d87fac 3134drm_gtf2_hbreak(const struct drm_edid *drm_edid)
7a374350 3135{
4194442d 3136 const struct detailed_timing *descriptor = NULL;
c8a4beba 3137
45aa2336 3138 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
948de842 3139
c8a4beba
JN		 3140 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12);
3141
3142 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.hfreq_start_khz * 2 : 0;
7a374350
AJ		 3143}
3144
3145static int
67d87fac 3146drm_gtf2_2c(const struct drm_edid *drm_edid)
7a374350 3147{
4194442d 3148 const struct detailed_timing *descriptor = NULL;
c8a4beba 3149
45aa2336 3150 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
c8a4beba
JN		 3151
3152 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.c) != 13);
948de842 3153
c8a4beba 3154 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.c : 0;
7a374350
AJ		 3155}
3156
3157static int
67d87fac 3158drm_gtf2_m(const struct drm_edid *drm_edid)
7a374350 3159{
4194442d 3160 const struct detailed_timing *descriptor = NULL;
948de842 3161
45aa2336 3162 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
c8a4beba
JN		 3163
3164 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.m) != 14);
3165
3166 return descriptor ? le16_to_cpu(descriptor->data.other_data.data.range.formula.gtf2.m) : 0;
7a374350
AJ		 3167}
3168
3169static int
67d87fac 3170drm_gtf2_k(const struct drm_edid *drm_edid)
7a374350 3171{
4194442d 3172 const struct detailed_timing *descriptor = NULL;
c8a4beba 3173
45aa2336 3174 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
948de842 3175
c8a4beba
JN		 3176 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.k) != 16);
3177
3178 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.k : 0;
7a374350
AJ		 3179}
3180
3181static int
67d87fac 3182drm_gtf2_2j(const struct drm_edid *drm_edid)
7a374350 3183{
4194442d 3184 const struct detailed_timing *descriptor = NULL;
c8a4beba 3185
45aa2336 3186 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
c8a4beba
JN		 3187
3188 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.j) != 17);
948de842 3189
c8a4beba 3190 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.j : 0;
7a374350
AJ		 3191}
3192
bf72b5ef
VS		 3193static void
3194get_timing_level(const struct detailed_timing *descriptor, void *data)
3195{
3196 int *res = data;
3197
3198 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3199 return;
3200
3201 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3202
3203 switch (descriptor->data.other_data.data.range.flags) {
3204 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG:
3205 *res = LEVEL_GTF;
3206 break;
3207 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG:
3208 *res = LEVEL_GTF2;
3209 break;
3210 case DRM_EDID_CVT_SUPPORT_FLAG:
3211 *res = LEVEL_CVT;
3212 break;
3213 default:
3214 break;
3215 }
3216}
3217
17edb8e1 3218/* Get standard timing level (CVT/GTF/DMT). */
67d87fac 3219static int standard_timing_level(const struct drm_edid *drm_edid)
7a374350 3220{
67d87fac
JN		 3221 const struct edid *edid = drm_edid->edid;
3222
bf72b5ef
VS		 3223 if (edid->revision >= 4) {
3224 /*
3225 * If the range descriptor doesn't
3226 * indicate otherwise default to CVT
3227 */
3228 int ret = LEVEL_CVT;
3229
3230 drm_for_each_detailed_block(drm_edid, get_timing_level, &ret);
3231
3232 return ret;
3233 } else if (edid->revision >= 3 && drm_gtf2_hbreak(drm_edid)) {
3234 return LEVEL_GTF2;
3235 } else if (edid->revision >= 2) {
3236 return LEVEL_GTF;
3237 } else {
3238 return LEVEL_DMT;
7a374350 3239 }
7a374350
AJ		 3240}
3241
23425cae
AJ		 3242/*
3243 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
3244 * monitors fill with ascii space (0x20) instead.
3245 */
3246static int
3247bad_std_timing(u8 a, u8 b)
3248{
3249 return (a == 0x00 && b == 0x00) ||
3250 (a == 0x01 && b == 0x01) ||
3251 (a == 0x20 && b == 0x20);
3252}
3253
58911c24
VS		 3254static int drm_mode_hsync(const struct drm_display_mode *mode)
3255{
3256 if (mode->htotal <= 0)
3257 return 0;
3258
3259 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal);
3260}
3261
86101bb7
VS		 3262static struct drm_display_mode *
3263drm_gtf2_mode(struct drm_device *dev,
3264 const struct drm_edid *drm_edid,
3265 int hsize, int vsize, int vrefresh_rate)
3266{
3267 struct drm_display_mode *mode;
3268
3269 /*
3270 * This is potentially wrong if there's ever a monitor with
3271 * more than one ranges section, each claiming a different
3272 * secondary GTF curve. Please don't do that.
3273 */
3274 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
3275 if (!mode)
3276 return NULL;
3277
3278 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(drm_edid)) {
3279 drm_mode_destroy(dev, mode);
3280 mode = drm_gtf_mode_complex(dev, hsize, vsize,
3281 vrefresh_rate, 0, 0,
3282 drm_gtf2_m(drm_edid),
3283 drm_gtf2_2c(drm_edid),
3284 drm_gtf2_k(drm_edid),
3285 drm_gtf2_2j(drm_edid));
3286 }
3287
3288 return mode;
3289}
3290
17edb8e1 3291/*
f453ba04 3292 * Take the standard timing params (in this case width, aspect, and refresh)
5c61259e 3293 * and convert them into a real mode using CVT/GTF/DMT.
f453ba04 3294 */
67d87fac
JN		 3295static struct drm_display_mode *drm_mode_std(struct drm_connector *connector,
3296 const struct drm_edid *drm_edid,
3297 const struct std_timing *t)
f453ba04 3298{
7ca6adb3
AJ		 3299 struct drm_device *dev = connector->dev;
3300 struct drm_display_mode *m, *mode = NULL;
5c61259e
ZY		 3301 int hsize, vsize;
3302 int vrefresh_rate;
0454beab
MD		 3303 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
3304 >> EDID_TIMING_ASPECT_SHIFT;
5c61259e
ZY		 3305 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
3306 >> EDID_TIMING_VFREQ_SHIFT;
67d87fac 3307 int timing_level = standard_timing_level(drm_edid);
5c61259e 3308
23425cae
AJ		 3309 if (bad_std_timing(t->hsize, t->vfreq_aspect))
3310 return NULL;
3311
5c61259e
ZY		 3312 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
3313 hsize = t->hsize * 8 + 248;
3314 /* vrefresh_rate = vfreq + 60 */
3315 vrefresh_rate = vfreq + 60;
3316 /* the vdisplay is calculated based on the aspect ratio */
f066a17d 3317 if (aspect_ratio == 0) {
67d87fac 3318 if (drm_edid->edid->revision < 3)
f066a17d
AJ		 3319 vsize = hsize;
3320 else
3321 vsize = (hsize * 10) / 16;
3322 } else if (aspect_ratio == 1)
f453ba04 3323 vsize = (hsize * 3) / 4;
0454beab 3324 else if (aspect_ratio == 2)
f453ba04
DA		 3325 vsize = (hsize * 4) / 5;
3326 else
3327 vsize = (hsize * 9) / 16;
a0910c8e
AJ		 3328
3329 /* HDTV hack, part 1 */
3330 if (vrefresh_rate == 60 &&
3331 ((hsize == 1360 && vsize == 765) ||
3332 (hsize == 1368 && vsize == 769))) {
3333 hsize = 1366;
3334 vsize = 768;
3335 }
3336
7ca6adb3
AJ		 3337 /*
3338 * If this connector already has a mode for this size and refresh
3339 * rate (because it came from detailed or CVT info), use that
3340 * instead. This way we don't have to guess at interlace or
3341 * reduced blanking.
3342 */
522032da 3343 list_for_each_entry(m, &connector->probed_modes, head)
7ca6adb3
AJ		 3344 if (m->hdisplay == hsize && m->vdisplay == vsize &&
3345 drm_mode_vrefresh(m) == vrefresh_rate)
3346 return NULL;
3347
a0910c8e
AJ		 3348 /* HDTV hack, part 2 */
3349 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
3350 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
d50ba256 3351 false);
a5ef6567
JM		 3352 if (!mode)
3353 return NULL;
559ee21d 3354 mode->hdisplay = 1366;
a4967de6
AJ		 3355 mode->hsync_start = mode->hsync_start - 1;
3356 mode->hsync_end = mode->hsync_end - 1;
559ee21d
ZY		 3357 return mode;
3358 }
a0910c8e 3359
559ee21d 3360 /* check whether it can be found in default mode table */
874d98ee 3361 if (drm_monitor_supports_rb(drm_edid)) {
f6e252ba
AJ		 3362 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
3363 true);
3364 if (mode)
3365 return mode;
3366 }
3367 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
559ee21d
ZY		 3368 if (mode)
3369 return mode;
3370
f6e252ba 3371 /* okay, generate it */
5c61259e
ZY		 3372 switch (timing_level) {
3373 case LEVEL_DMT:
5c61259e
ZY		 3374 break;
3375 case LEVEL_GTF:
3376 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
3377 break;
7a374350 3378 case LEVEL_GTF2:
86101bb7 3379 mode = drm_gtf2_mode(dev, drm_edid, hsize, vsize, vrefresh_rate);
7a374350 3380 break;
5c61259e 3381 case LEVEL_CVT:
d50ba256
DA		 3382 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
3383 false);
5c61259e
ZY		 3384 break;
3385 }
f453ba04
DA		 3386 return mode;
3387}
3388
b58db2c6
AJ		 3389/*
3390 * EDID is delightfully ambiguous about how interlaced modes are to be
3391 * encoded. Our internal representation is of frame height, but some
3392 * HDTV detailed timings are encoded as field height.
3393 *
3394 * The format list here is from CEA, in frame size. Technically we
3395 * should be checking refresh rate too. Whatever.
3396 */
3397static void
3398drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
fcfb2ea1 3399 const struct detailed_pixel_timing *pt)
b58db2c6
AJ		 3400{
3401 int i;
3402 static const struct {
3403 int w, h;
3404 } cea_interlaced[] = {
3405 { 1920, 1080 },
3406 { 720, 480 },
3407 { 1440, 480 },
3408 { 2880, 480 },
3409 { 720, 576 },
3410 { 1440, 576 },
3411 { 2880, 576 },
3412 };
b58db2c6
AJ		 3413
3414 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
3415 return;
3416
3c581411 3417 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
b58db2c6
AJ		 3418 if ((mode->hdisplay == cea_interlaced[i].w) &&
3419 (mode->vdisplay == cea_interlaced[i].h / 2)) {
3420 mode->vdisplay *= 2;
3421 mode->vsync_start *= 2;
3422 mode->vsync_end *= 2;
3423 mode->vtotal *= 2;
3424 mode->vtotal |= 1;
3425 }
3426 }
3427
3428 mode->flags |= DRM_MODE_FLAG_INTERLACE;
3429}
3430
17edb8e1
JN		 3431/*
3432 * Create a new mode from an EDID detailed timing section. An EDID detailed
3433 * timing block contains enough info for us to create and return a new struct
3434 * drm_display_mode.
f453ba04 3435 */
e1e7bc48 3436static struct drm_display_mode *drm_mode_detailed(struct drm_connector *connector,
f0d080ff 3437 const struct drm_edid *drm_edid,
4959b693 3438 const struct detailed_timing *timing)
f453ba04 3439{
4959b693 3440 const struct drm_display_info *info = &connector->display_info;
e1e7bc48 3441 struct drm_device *dev = connector->dev;
f453ba04 3442 struct drm_display_mode *mode;
fcfb2ea1 3443 const struct detailed_pixel_timing *pt = &timing->data.pixel_data;
0454beab
MD		 3444 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
3445 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
3446 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
3447 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
e14cbee4
MD		 3448 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
3449 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
16dad1d7 3450 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
e14cbee4 3451 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
f453ba04 3452
fc438966 3453 /* ignore tiny modes */
0454beab 3454 if (hactive < 64 || vactive < 64)
fc438966
AJ		 3455 return NULL;
3456
0454beab 3457 if (pt->misc & DRM_EDID_PT_STEREO) {
e1e7bc48
JN		 3458 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Stereo mode not supported\n",
3459 connector->base.id, connector->name);
f453ba04
DA		 3460 return NULL;
3461 }
50b6f2c8
JN		 3462 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
3463 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Composite sync not supported\n",
3464 connector->base.id, connector->name);
3465 }
f453ba04 3466
fcb45611
ZY		 3467 /* it is incorrect if hsync/vsync width is zero */
3468 if (!hsync_pulse_width || !vsync_pulse_width) {
e1e7bc48
JN		 3469 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Incorrect Detailed timing. Wrong Hsync/Vsync pulse width\n",
3470 connector->base.id, connector->name);
fcb45611
ZY		 3471 return NULL;
3472 }
bc42aabc 3473
4959b693 3474 if (info->quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
bc42aabc
AJ		 3475 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
3476 if (!mode)
3477 return NULL;
3478
3479 goto set_size;
3480 }
3481
f453ba04
DA		 3482 mode = drm_mode_create(dev);
3483 if (!mode)
3484 return NULL;
3485
4959b693 3486 if (info->quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
faacff8e
JN		 3487 mode->clock = 1088 * 10;
3488 else
3489 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
0454beab
MD		 3490
3491 mode->hdisplay = hactive;
3492 mode->hsync_start = mode->hdisplay + hsync_offset;
3493 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
3494 mode->htotal = mode->hdisplay + hblank;
3495
3496 mode->vdisplay = vactive;
3497 mode->vsync_start = mode->vdisplay + vsync_offset;
3498 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
3499 mode->vtotal = mode->vdisplay + vblank;
f453ba04 3500
2682768b
VS		 3501 /* Some EDIDs have bogus h/vsync_end values */
3502 if (mode->hsync_end > mode->htotal) {
3503 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] reducing hsync_end %d->%d\n",
3504 connector->base.id, connector->name,
3505 mode->hsync_end, mode->htotal);
3506 mode->hsync_end = mode->htotal;
3507 }
3508 if (mode->vsync_end > mode->vtotal) {
3509 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] reducing vsync_end %d->%d\n",
3510 connector->base.id, connector->name,
3511 mode->vsync_end, mode->vtotal);
3512 mode->vsync_end = mode->vtotal;
3513 }
7064fef5 3514
b58db2c6 3515 drm_mode_do_interlace_quirk(mode, pt);
f453ba04 3516
4959b693 3517 if (info->quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
faacff8e
JN		 3518 mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC;
3519 } else {
50b6f2c8
JN		 3520 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
3521 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
3522 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
3523 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
f453ba04
DA		 3524 }
3525
bc42aabc 3526set_size:
e14cbee4
MD		 3527 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
3528 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
f453ba04 3529
4959b693 3530 if (info->quirks & EDID_QUIRK_DETAILED_IN_CM) {
f453ba04
DA		 3531 mode->width_mm *= 10;
3532 mode->height_mm *= 10;
3533 }
3534
4959b693 3535 if (info->quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
f0d080ff
JN		 3536 mode->width_mm = drm_edid->edid->width_cm * 10;
3537 mode->height_mm = drm_edid->edid->height_cm * 10;
f453ba04
DA		 3538 }
3539
bc42aabc
AJ		 3540 mode->type = DRM_MODE_TYPE_DRIVER;
3541 drm_mode_set_name(mode);
3542
f453ba04
DA		 3543 return mode;
3544}
3545
b17e52ef 3546static bool
b1f559ec 3547mode_in_hsync_range(const struct drm_display_mode *mode,
c14e7241 3548 const struct edid *edid, const u8 *t)
b17e52ef
AJ		 3549{
3550 int hsync, hmin, hmax;
3551
3552 hmin = t[7];
3553 if (edid->revision >= 4)
3554 hmin += ((t[4] & 0x04) ? 255 : 0);
3555 hmax = t[8];
3556 if (edid->revision >= 4)
3557 hmax += ((t[4] & 0x08) ? 255 : 0);
07a5e632 3558 hsync = drm_mode_hsync(mode);
07a5e632 3559
b17e52ef
AJ		 3560 return (hsync <= hmax && hsync >= hmin);
3561}
3562
3563static bool
b1f559ec 3564mode_in_vsync_range(const struct drm_display_mode *mode,
c14e7241 3565 const struct edid *edid, const u8 *t)
b17e52ef
AJ		 3566{
3567 int vsync, vmin, vmax;
3568
3569 vmin = t[5];
3570 if (edid->revision >= 4)
3571 vmin += ((t[4] & 0x01) ? 255 : 0);
3572 vmax = t[6];
3573 if (edid->revision >= 4)
3574 vmax += ((t[4] & 0x02) ? 255 : 0);
3575 vsync = drm_mode_vrefresh(mode);
3576
3577 return (vsync <= vmax && vsync >= vmin);
3578}
3579
3580static u32
c14e7241 3581range_pixel_clock(const struct edid *edid, const u8 *t)
b17e52ef
AJ		 3582{
3583 /* unspecified */
3584 if (t[9] == 0 || t[9] == 255)
3585 return 0;
3586
3587 /* 1.4 with CVT support gives us real precision, yay */
afd4429e 3588 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG)
b17e52ef
AJ		 3589 return (t[9] * 10000) - ((t[12] >> 2) * 250);
3590
3591 /* 1.3 is pathetic, so fuzz up a bit */
3592 return t[9] * 10000 + 5001;
3593}
3594
874d98ee
JN		 3595static bool mode_in_range(const struct drm_display_mode *mode,
3596 const struct drm_edid *drm_edid,
3597 const struct detailed_timing *timing)
b17e52ef 3598{
874d98ee 3599 const struct edid *edid = drm_edid->edid;
b17e52ef 3600 u32 max_clock;
fcfb2ea1 3601 const u8 *t = (const u8 *)timing;
b17e52ef
AJ		 3602
3603 if (!mode_in_hsync_range(mode, edid, t))
07a5e632
AJ		 3604 return false;
3605
b17e52ef 3606 if (!mode_in_vsync_range(mode, edid, t))
07a5e632
AJ		 3607 return false;
3608
b17e52ef 3609 if ((max_clock = range_pixel_clock(edid, t)))
07a5e632
AJ		 3610 if (mode->clock > max_clock)
3611 return false;
b17e52ef
AJ		 3612
3613 /* 1.4 max horizontal check */
afd4429e 3614 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG)
b17e52ef
AJ		 3615 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
3616 return false;
3617
874d98ee 3618 if (mode_is_rb(mode) && !drm_monitor_supports_rb(drm_edid))
b17e52ef 3619 return false;
07a5e632
AJ		 3620
3621 return true;
3622}
3623
7b668ebe
TI		 3624static bool valid_inferred_mode(const struct drm_connector *connector,
3625 const struct drm_display_mode *mode)
3626{
85f8fcd6 3627 const struct drm_display_mode *m;
7b668ebe
TI		 3628 bool ok = false;
3629
3630 list_for_each_entry(m, &connector->probed_modes, head) {
3631 if (mode->hdisplay == m->hdisplay &&
3632 mode->vdisplay == m->vdisplay &&
3633 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
3634 return false; /* duplicated */
3635 if (mode->hdisplay <= m->hdisplay &&
3636 mode->vdisplay <= m->vdisplay)
3637 ok = true;
3638 }
3639 return ok;
3640}
3641
084c7a7c
JN		 3642static int drm_dmt_modes_for_range(struct drm_connector *connector,
3643 const struct drm_edid *drm_edid,
3644 const struct detailed_timing *timing)
07a5e632
AJ		 3645{
3646 int i, modes = 0;
3647 struct drm_display_mode *newmode;
3648 struct drm_device *dev = connector->dev;
3649
a6b21831 3650 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
874d98ee 3651 if (mode_in_range(drm_dmt_modes + i, drm_edid, timing) &&
7b668ebe 3652 valid_inferred_mode(connector, drm_dmt_modes + i)) {
07a5e632
AJ		 3653 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
3654 if (newmode) {
3655 drm_mode_probed_add(connector, newmode);
3656 modes++;
3657 }
3658 }
3659 }
3660
3661 return modes;
3662}
3663
c09dedb7
TI		 3664/* fix up 1366x768 mode from 1368x768;
3665 * GFT/CVT can't express 1366 width which isn't dividable by 8
3666 */
969218fe 3667void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
c09dedb7
TI		 3668{
3669 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
3670 mode->hdisplay = 1366;
3671 mode->hsync_start--;
3672 mode->hsync_end--;
3673 drm_mode_set_name(mode);
3674 }
3675}
3676
a77f7c89
JN		 3677static int drm_gtf_modes_for_range(struct drm_connector *connector,
3678 const struct drm_edid *drm_edid,
3679 const struct detailed_timing *timing)
b309bd37
AJ		 3680{
3681 int i, modes = 0;
3682 struct drm_display_mode *newmode;
3683 struct drm_device *dev = connector->dev;
3684
a6b21831 3685 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
b309bd37 3686 const struct minimode *m = &extra_modes[i];
948de842 3687
b309bd37 3688 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
fc48f169
TI		 3689 if (!newmode)
3690 return modes;
b309bd37 3691
969218fe 3692 drm_mode_fixup_1366x768(newmode);
874d98ee 3693 if (!mode_in_range(newmode, drm_edid, timing) ||
7b668ebe 3694 !valid_inferred_mode(connector, newmode)) {
b309bd37
AJ		 3695 drm_mode_destroy(dev, newmode);
3696 continue;
3697 }
3698
3699 drm_mode_probed_add(connector, newmode);
3700 modes++;
3701 }
3702
3703 return modes;
3704}
3705
9ed15f91
VS		 3706static int drm_gtf2_modes_for_range(struct drm_connector *connector,
3707 const struct drm_edid *drm_edid,
3708 const struct detailed_timing *timing)
3709{
3710 int i, modes = 0;
3711 struct drm_display_mode *newmode;
3712 struct drm_device *dev = connector->dev;
3713
3714 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3715 const struct minimode *m = &extra_modes[i];
3716
3717 newmode = drm_gtf2_mode(dev, drm_edid, m->w, m->h, m->r);
3718 if (!newmode)
3719 return modes;
3720
3721 drm_mode_fixup_1366x768(newmode);
3722 if (!mode_in_range(newmode, drm_edid, timing) ||
3723 !valid_inferred_mode(connector, newmode)) {
3724 drm_mode_destroy(dev, newmode);
3725 continue;
3726 }
3727
3728 drm_mode_probed_add(connector, newmode);
3729 modes++;
3730 }
3731
3732 return modes;
3733}
3734
7428bfbd
JN		 3735static int drm_cvt_modes_for_range(struct drm_connector *connector,
3736 const struct drm_edid *drm_edid,
3737 const struct detailed_timing *timing)
b309bd37
AJ		 3738{
3739 int i, modes = 0;
3740 struct drm_display_mode *newmode;
3741 struct drm_device *dev = connector->dev;
874d98ee 3742 bool rb = drm_monitor_supports_rb(drm_edid);
b309bd37 3743
a6b21831 3744 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
b309bd37 3745 const struct minimode *m = &extra_modes[i];
948de842 3746
b309bd37 3747 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
fc48f169
TI		 3748 if (!newmode)
3749 return modes;
b309bd37 3750
969218fe 3751 drm_mode_fixup_1366x768(newmode);
874d98ee 3752 if (!mode_in_range(newmode, drm_edid, timing) ||
7b668ebe 3753 !valid_inferred_mode(connector, newmode)) {
b309bd37
AJ		 3754 drm_mode_destroy(dev, newmode);
3755 continue;
3756 }
3757
3758 drm_mode_probed_add(connector, newmode);
3759 modes++;
3760 }
3761
3762 return modes;
3763}
3764
13931579 3765static void
4194442d 3766do_inferred_modes(const struct detailed_timing *timing, void *c)
9340d8cf 3767{
13931579 3768 struct detailed_mode_closure *closure = c;
fcfb2ea1
JN		 3769 const struct detailed_non_pixel *data = &timing->data.other_data;
3770 const struct detailed_data_monitor_range *range = &data->data.range;
9340d8cf 3771
e379814b 3772 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
cb21aafe
AJ		 3773 return;
3774
3775 closure->modes += drm_dmt_modes_for_range(closure->connector,
084c7a7c 3776 closure->drm_edid,
cb21aafe 3777 timing);
4d23f484 3778
dd3abfe4 3779 if (closure->drm_edid->edid->revision < 2)
b309bd37
AJ		 3780 return; /* GTF not defined yet */
3781
3782 switch (range->flags) {
9ed15f91
VS		 3783 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG:
3784 closure->modes += drm_gtf2_modes_for_range(closure->connector,
3785 closure->drm_edid,
3786 timing);
3787 break;
afd4429e 3788 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG:
b309bd37 3789 closure->modes += drm_gtf_modes_for_range(closure->connector,
a77f7c89 3790 closure->drm_edid,
b309bd37
AJ		 3791 timing);
3792 break;
afd4429e 3793 case DRM_EDID_CVT_SUPPORT_FLAG:
dd3abfe4 3794 if (closure->drm_edid->edid->revision < 4)
b309bd37
AJ		 3795 break;
3796
3797 closure->modes += drm_cvt_modes_for_range(closure->connector,
7428bfbd 3798 closure->drm_edid,
b309bd37
AJ		 3799 timing);
3800 break;
afd4429e 3801 case DRM_EDID_RANGE_LIMITS_ONLY_FLAG:
b309bd37
AJ		 3802 default:
3803 break;
3804 }
13931579 3805}
69da3015 3806
40f71f5b
JN		 3807static int add_inferred_modes(struct drm_connector *connector,
3808 const struct drm_edid *drm_edid)
13931579
AJ		 3809{
3810 struct detailed_mode_closure closure = {
d456ea2e 3811 .connector = connector,
dd0f4470 3812 .drm_edid = drm_edid,
13931579 3813 };
9340d8cf 3814
dd3abfe4 3815 if (drm_edid->edid->revision >= 1)
45aa2336 3816 drm_for_each_detailed_block(drm_edid, do_inferred_modes, &closure);
9340d8cf 3817
13931579 3818 return closure.modes;
9340d8cf
AJ		 3819}
3820
2255be14 3821static int
fcfb2ea1 3822drm_est3_modes(struct drm_connector *connector, const struct detailed_timing *timing)
2255be14
AJ		 3823{
3824 int i, j, m, modes = 0;
3825 struct drm_display_mode *mode;
fcfb2ea1 3826 const u8 *est = ((const u8 *)timing) + 6;
2255be14
AJ		 3827
3828 for (i = 0; i < 6; i++) {
891a7469 3829 for (j = 7; j >= 0; j--) {
2255be14 3830 m = (i * 8) + (7 - j);
3c581411 3831 if (m >= ARRAY_SIZE(est3_modes))
2255be14
AJ		 3832 break;
3833 if (est[i] & (1 << j)) {
1d42bbc8
DA		 3834 mode = drm_mode_find_dmt(connector->dev,
3835 est3_modes[m].w,
3836 est3_modes[m].h,
f6e252ba
AJ		 3837 est3_modes[m].r,
3838 est3_modes[m].rb);
2255be14
AJ		 3839 if (mode) {
3840 drm_mode_probed_add(connector, mode);
3841 modes++;
3842 }
3843 }
3844 }
3845 }
3846
3847 return modes;
3848}
3849
13931579 3850static void
4194442d 3851do_established_modes(const struct detailed_timing *timing, void *c)
9cf00977 3852{
13931579 3853 struct detailed_mode_closure *closure = c;
9cf00977 3854
e379814b 3855 if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS))
a7a131ac
VS		 3856 return;
3857
3858 closure->modes += drm_est3_modes(closure->connector, timing);
13931579 3859}
9cf00977 3860
17edb8e1
JN		 3861/*
3862 * Get established modes from EDID and add them. Each EDID block contains a
3863 * bitmap of the supported "established modes" list (defined above). Tease them
3864 * out and add them to the global modes list.
13931579 3865 */
40f71f5b
JN		 3866static int add_established_modes(struct drm_connector *connector,
3867 const struct drm_edid *drm_edid)
13931579
AJ		 3868{
3869 struct drm_device *dev = connector->dev;
40f71f5b 3870 const struct edid *edid = drm_edid->edid;
13931579
AJ		 3871 unsigned long est_bits = edid->established_timings.t1 |
3872 (edid->established_timings.t2 << 8) |
3873 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
3874 int i, modes = 0;
3875 struct detailed_mode_closure closure = {
d456ea2e 3876 .connector = connector,
dd0f4470 3877 .drm_edid = drm_edid,
13931579 3878 };
9cf00977 3879
13931579
AJ		 3880 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
3881 if (est_bits & (1<<i)) {
3882 struct drm_display_mode *newmode;
948de842 3883
13931579
AJ		 3884 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
3885 if (newmode) {
3886 drm_mode_probed_add(connector, newmode);
3887 modes++;
3888 }
3889 }
9cf00977
AJ		 3890 }
3891
dd3abfe4 3892 if (edid->revision >= 1)
45aa2336 3893 drm_for_each_detailed_block(drm_edid, do_established_modes,
eed628f1 3894 &closure);
13931579
AJ		 3895
3896 return modes + closure.modes;
3897}
3898
3899static void
4194442d 3900do_standard_modes(const struct detailed_timing *timing, void *c)
13931579
AJ		 3901{
3902 struct detailed_mode_closure *closure = c;
fcfb2ea1 3903 const struct detailed_non_pixel *data = &timing->data.other_data;
13931579 3904 struct drm_connector *connector = closure->connector;
a7a131ac 3905 int i;
13931579 3906
e379814b 3907 if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES))
a7a131ac 3908 return;
9cf00977 3909
a7a131ac 3910 for (i = 0; i < 6; i++) {
fcfb2ea1 3911 const struct std_timing *std = &data->data.timings[i];
a7a131ac
VS		 3912 struct drm_display_mode *newmode;
3913
67d87fac 3914 newmode = drm_mode_std(connector, closure->drm_edid, std);
a7a131ac
VS		 3915 if (newmode) {
3916 drm_mode_probed_add(connector, newmode);
3917 closure->modes++;
9cf00977 3918 }
9cf00977 3919 }
9cf00977
AJ		 3920}
3921
17edb8e1
JN		 3922/*
3923 * Get standard modes from EDID and add them. Standard modes can be calculated
3924 * using the appropriate standard (DMT, GTF, or CVT). Grab them from EDID and
3925 * add them to the list.
f453ba04 3926 */
40f71f5b
JN		 3927static int add_standard_modes(struct drm_connector *connector,
3928 const struct drm_edid *drm_edid)
f453ba04 3929{
9cf00977 3930 int i, modes = 0;
13931579 3931 struct detailed_mode_closure closure = {
d456ea2e 3932 .connector = connector,
dd0f4470 3933 .drm_edid = drm_edid,
13931579
AJ		 3934 };
3935
3936 for (i = 0; i < EDID_STD_TIMINGS; i++) {
3937 struct drm_display_mode *newmode;
3938
67d87fac 3939 newmode = drm_mode_std(connector, drm_edid,
40f71f5b 3940 &drm_edid->edid->standard_timings[i]);
13931579
AJ		 3941 if (newmode) {
3942 drm_mode_probed_add(connector, newmode);
3943 modes++;
3944 }
3945 }
3946
dd3abfe4 3947 if (drm_edid->edid->revision >= 1)
45aa2336 3948 drm_for_each_detailed_block(drm_edid, do_standard_modes,
13931579
AJ		 3949 &closure);
3950
3951 /* XXX should also look for standard codes in VTB blocks */
3952
3953 return modes + closure.modes;
3954}
f453ba04 3955
13931579 3956static int drm_cvt_modes(struct drm_connector *connector,
fcfb2ea1 3957 const struct detailed_timing *timing)
13931579
AJ		 3958{
3959 int i, j, modes = 0;
3960 struct drm_display_mode *newmode;
3961 struct drm_device *dev = connector->dev;
fcfb2ea1 3962 const struct cvt_timing *cvt;
bce1eb50 3963 static const int rates[] = { 60, 85, 75, 60, 50 };
13931579 3964 const u8 empty[3] = { 0, 0, 0 };
a327f6b8 3965
13931579 3966 for (i = 0; i < 4; i++) {
3f649ab7 3967 int width, height;
948de842 3968
13931579 3969 cvt = &(timing->data.other_data.data.cvt[i]);
f453ba04 3970
13931579 3971 if (!memcmp(cvt->code, empty, 3))
9cf00977 3972 continue;
f453ba04 3973
13931579
AJ		 3974 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
3975 switch (cvt->code[1] & 0x0c) {
d652d5f1
LT		 3976 /* default - because compiler doesn't see that we've enumerated all cases */
3977 default:
13931579
AJ		 3978 case 0x00:
3979 width = height * 4 / 3;
3980 break;
3981 case 0x04:
3982 width = height * 16 / 9;
3983 break;
3984 case 0x08:
3985 width = height * 16 / 10;
3986 break;
3987 case 0x0c:
3988 width = height * 15 / 9;
3989 break;
3990 }
3991
3992 for (j = 1; j < 5; j++) {
3993 if (cvt->code[2] & (1 << j)) {
3994 newmode = drm_cvt_mode(dev, width, height,
3995 rates[j], j == 0,
3996 false, false);
3997 if (newmode) {
3998 drm_mode_probed_add(connector, newmode);
3999 modes++;
4000 }
4001 }
4002 }
f453ba04
DA		 4003 }
4004
4005 return modes;
4006}
9cf00977 4007
13931579 4008static void
4194442d 4009do_cvt_mode(const struct detailed_timing *timing, void *c)
882f0219 4010{
13931579 4011 struct detailed_mode_closure *closure = c;
882f0219 4012
e379814b 4013 if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE))
a7a131ac
VS		 4014 return;
4015
4016 closure->modes += drm_cvt_modes(closure->connector, timing);
13931579 4017}
882f0219 4018
13931579 4019static int
40f71f5b 4020add_cvt_modes(struct drm_connector *connector, const struct drm_edid *drm_edid)
4d23f484 4021{
13931579 4022 struct detailed_mode_closure closure = {
d456ea2e 4023 .connector = connector,
dd0f4470 4024 .drm_edid = drm_edid,
13931579 4025 };
882f0219 4026
dd3abfe4 4027 if (drm_edid->edid->revision >= 3)
45aa2336 4028 drm_for_each_detailed_block(drm_edid, do_cvt_mode, &closure);
882f0219 4029
13931579 4030 /* XXX should also look for CVT codes in VTB blocks */
882f0219 4031
13931579
AJ		 4032 return closure.modes;
4033}
4034
e1e7bc48
JN		 4035static void fixup_detailed_cea_mode_clock(struct drm_connector *connector,
4036 struct drm_display_mode *mode);
fa3a7340 4037
13931579 4038static void
4194442d 4039do_detailed_mode(const struct detailed_timing *timing, void *c)
13931579
AJ		 4040{
4041 struct detailed_mode_closure *closure = c;
4042 struct drm_display_mode *newmode;
4043
a9b1f15f 4044 if (!is_detailed_timing_descriptor(timing))
f447dd1f
VS		 4045 return;
4046
e1e7bc48 4047 newmode = drm_mode_detailed(closure->connector,
4959b693 4048 closure->drm_edid, timing);
f447dd1f
VS		 4049 if (!newmode)
4050 return;
13931579 4051
f447dd1f
VS		 4052 if (closure->preferred)
4053 newmode->type |= DRM_MODE_TYPE_PREFERRED;
13931579 4054
f447dd1f
VS		 4055 /*
4056 * Detailed modes are limited to 10kHz pixel clock resolution,
4057 * so fix up anything that looks like CEA/HDMI mode, but the clock
4058 * is just slightly off.
4059 */
e1e7bc48 4060 fixup_detailed_cea_mode_clock(closure->connector, newmode);
fa3a7340 4061
f447dd1f
VS		 4062 drm_mode_probed_add(closure->connector, newmode);
4063 closure->modes++;
4064 closure->preferred = false;
13931579 4065}
882f0219 4066
13931579
AJ		 4067/*
4068 * add_detailed_modes - Add modes from detailed timings
4069 * @connector: attached connector
40f71f5b 4070 * @drm_edid: EDID block to scan
13931579 4071 */
40f71f5b 4072static int add_detailed_modes(struct drm_connector *connector,
4959b693 4073 const struct drm_edid *drm_edid)
13931579
AJ		 4074{
4075 struct detailed_mode_closure closure = {
d456ea2e 4076 .connector = connector,
dd0f4470 4077 .drm_edid = drm_edid,
13931579
AJ		 4078 };
4079
dd3abfe4 4080 if (drm_edid->edid->revision >= 4)
f72f9529
VS		 4081 closure.preferred = true; /* first detailed timing is always preferred */
4082 else
13931579 4083 closure.preferred =
f72f9529 4084 drm_edid->edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING;
13931579 4085
45aa2336 4086 drm_for_each_detailed_block(drm_edid, do_detailed_mode, &closure);
13931579
AJ		 4087
4088 return closure.modes;
882f0219 4089}
f453ba04 4090
9d72b7e2
JN		 4091/* CTA-861-H Table 60 - CTA Tag Codes */
4092#define CTA_DB_AUDIO 1
4093#define CTA_DB_VIDEO 2
4094#define CTA_DB_VENDOR 3
4095#define CTA_DB_SPEAKER 4
4096#define CTA_DB_EXTENDED_TAG 7
4097
4098/* CTA-861-H Table 62 - CTA Extended Tag Codes */
4099#define CTA_EXT_DB_VIDEO_CAP 0
4100#define CTA_EXT_DB_VENDOR 1
4101#define CTA_EXT_DB_HDR_STATIC_METADATA 6
4102#define CTA_EXT_DB_420_VIDEO_DATA 14
4103#define CTA_EXT_DB_420_VIDEO_CAP_MAP 15
18e3c1d5 4104#define CTA_EXT_DB_HF_EEODB 0x78
9d72b7e2
JN		 4105#define CTA_EXT_DB_HF_SCDB 0x79
4106
8fe9790d 4107#define EDID_BASIC_AUDIO (1 << 6)
a988bc72
LPC		 4108#define EDID_CEA_YCRCB444 (1 << 5)
4109#define EDID_CEA_YCRCB422 (1 << 4)
b1edd6a6 4110#define EDID_CEA_VCDB_QS (1 << 6)
8fe9790d 4111
d4e4a31d 4112/*
8fe9790d 4113 * Search EDID for CEA extension block.
d9ba1b4c
JN		 4114 *
4115 * FIXME: Prefer not returning pointers to raw EDID data.
f23c20c8 4116 */
d9ba1b4c 4117const u8 *drm_find_edid_extension(const struct drm_edid *drm_edid,
4cc4f09e 4118 int ext_id, int *ext_index)
f23c20c8 4119{
43d16d84 4120 const u8 *edid_ext = NULL;
8fe9790d 4121 int i;
f23c20c8
ML		 4122
4123 /* No EDID or EDID extensions */
d9307f27 4124 if (!drm_edid || !drm_edid_extension_block_count(drm_edid))
8fe9790d 4125 return NULL;
f23c20c8 4126
f23c20c8 4127 /* Find CEA extension */
d9307f27
JN		 4128 for (i = *ext_index; i < drm_edid_extension_block_count(drm_edid); i++) {
4129 edid_ext = drm_edid_extension_block_data(drm_edid, i);
4ba0f53c 4130 if (edid_block_tag(edid_ext) == ext_id)
f23c20c8
ML		 4131 break;
4132 }
4133
d9307f27 4134 if (i >= drm_edid_extension_block_count(drm_edid))
8fe9790d
ZW		 4135 return NULL;
4136
8873cfa3
VS		 4137 *ext_index = i + 1;
4138
8fe9790d
ZW		 4139 return edid_ext;
4140}
4141
6ff1c19f 4142/* Return true if the EDID has a CTA extension or a DisplayID CTA data block */
40f71f5b 4143static bool drm_edid_has_cta_extension(const struct drm_edid *drm_edid)
e28ad544 4144{
43d16d84 4145 const struct displayid_block *block;
1ba63caf 4146 struct displayid_iter iter;
1ba63caf 4147 int ext_index = 0;
6ff1c19f 4148 bool found = false;
e28ad544
AR		 4149
4150 /* Look for a top level CEA extension block */
d9ba1b4c 4151 if (drm_find_edid_extension(drm_edid, CEA_EXT, &ext_index))
6ff1c19f 4152 return true;
e28ad544
AR		 4153
4154 /* CEA blocks can also be found embedded in a DisplayID block */
d9ba1b4c 4155 displayid_iter_edid_begin(drm_edid, &iter);
1ba63caf
JN		 4156 displayid_iter_for_each(block, &iter) {
4157 if (block->tag == DATA_BLOCK_CTA) {
6ff1c19f 4158 found = true;
1ba63caf 4159 break;
e28ad544
AR		 4160 }
4161 }
1ba63caf 4162 displayid_iter_end(&iter);
e28ad544 4163
6ff1c19f 4164 return found;
e28ad544
AR		 4165}
4166
e1cf35b9 4167static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic)
7befe621 4168{
9212f8ee
VS		 4169 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127);
4170 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219);
4171
8c1b2bd9
VS		 4172 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1))
4173 return &edid_cea_modes_1[vic - 1];
f7655d42
VS		 4174 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193))
4175 return &edid_cea_modes_193[vic - 193];
7befe621
VS		 4176 return NULL;
4177}
4178
4179static u8 cea_num_vics(void)
4180{
f7655d42 4181 return 193 + ARRAY_SIZE(edid_cea_modes_193);
7befe621
VS		 4182}
4183
4184static u8 cea_next_vic(u8 vic)
4185{
8c1b2bd9 4186 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1))
f7655d42
VS		 4187 vic = 193;
4188 return vic;
7befe621
VS		 4189}
4190
e6e79209
VS		 4191/*
4192 * Calculate the alternate clock for the CEA mode
4193 * (60Hz vs. 59.94Hz etc.)
4194 */
4195static unsigned int
4196cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
4197{
4198 unsigned int clock = cea_mode->clock;
4199
0425662f 4200 if (drm_mode_vrefresh(cea_mode) % 6 != 0)
e6e79209
VS		 4201 return clock;
4202
4203 /*
4204 * edid_cea_modes contains the 59.94Hz
4205 * variant for 240 and 480 line modes,
4206 * and the 60Hz variant otherwise.
4207 */
4208 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
9afd808c 4209 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
e6e79209 4210 else
9afd808c 4211 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
e6e79209
VS		 4212
4213 return clock;
4214}
4215
c45a4e46
VS		 4216static bool
4217cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
4218{
4219 /*
4220 * For certain VICs the spec allows the vertical
4221 * front porch to vary by one or two lines.
4222 *
4223 * cea_modes[] stores the variant with the shortest
4224 * vertical front porch. We can adjust the mode to
4225 * get the other variants by simply increasing the
4226 * vertical front porch length.
4227 */
7befe621
VS		 4228 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 ||
4229 cea_mode_for_vic(9)->vtotal != 262 ||
4230 cea_mode_for_vic(12)->vtotal != 262 ||
4231 cea_mode_for_vic(13)->vtotal != 262 ||
4232 cea_mode_for_vic(23)->vtotal != 312 ||
4233 cea_mode_for_vic(24)->vtotal != 312 ||
4234 cea_mode_for_vic(27)->vtotal != 312 ||
4235 cea_mode_for_vic(28)->vtotal != 312);
c45a4e46
VS		 4236
4237 if (((vic == 8 || vic == 9 ||
4238 vic == 12 || vic == 13) && mode->vtotal < 263) ||
4239 ((vic == 23 || vic == 24 ||
4240 vic == 27 || vic == 28) && mode->vtotal < 314)) {
4241 mode->vsync_start++;
4242 mode->vsync_end++;
4243 mode->vtotal++;
4244
4245 return true;
4246 }
4247
4248 return false;
4249}
4250
4c6bcf44
VS		 4251static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
4252 unsigned int clock_tolerance)
4253{
357768cc 4254 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 4255 u8 vic;
4c6bcf44
VS		 4256
4257 if (!to_match->clock)
4258 return 0;
4259
357768cc
VS		 4260 if (to_match->picture_aspect_ratio)
4261 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4262
7befe621 4263 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
563c4a75 4264 struct drm_display_mode cea_mode;
4c6bcf44
VS		 4265 unsigned int clock1, clock2;
4266
563c4a75
VS		 4267 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
4268
4c6bcf44 4269 /* Check both 60Hz and 59.94Hz */
c45a4e46
VS		 4270 clock1 = cea_mode.clock;
4271 clock2 = cea_mode_alternate_clock(&cea_mode);
4c6bcf44
VS		 4272
4273 if (abs(to_match->clock - clock1) > clock_tolerance &&
4274 abs(to_match->clock - clock2) > clock_tolerance)
4275 continue;
4276
c45a4e46 4277 do {
357768cc 4278 if (drm_mode_match(to_match, &cea_mode, match_flags))
c45a4e46
VS		 4279 return vic;
4280 } while (cea_mode_alternate_timings(vic, &cea_mode));
4c6bcf44
VS		 4281 }
4282
4283 return 0;
4284}
4285
18316c8c
TR		 4286/**
4287 * drm_match_cea_mode - look for a CEA mode matching given mode
4288 * @to_match: display mode
4289 *
db6cf833 4290 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
18316c8c 4291 * mode.
a4799037 4292 */
18316c8c 4293u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
a4799037 4294{
357768cc 4295 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 4296 u8 vic;
a4799037 4297
a90b590e
VS		 4298 if (!to_match->clock)
4299 return 0;
4300
357768cc
VS		 4301 if (to_match->picture_aspect_ratio)
4302 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4303
7befe621 4304 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
563c4a75 4305 struct drm_display_mode cea_mode;
a90b590e
VS		 4306 unsigned int clock1, clock2;
4307
563c4a75
VS		 4308 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
4309
a90b590e 4310 /* Check both 60Hz and 59.94Hz */
c45a4e46
VS		 4311 clock1 = cea_mode.clock;
4312 clock2 = cea_mode_alternate_clock(&cea_mode);
a4799037 4313
c45a4e46
VS		 4314 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
4315 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
4316 continue;
4317
4318 do {
357768cc 4319 if (drm_mode_match(to_match, &cea_mode, match_flags))
c45a4e46
VS		 4320 return vic;
4321 } while (cea_mode_alternate_timings(vic, &cea_mode));
a4799037 4322 }
c45a4e46 4323
a4799037
SM		 4324 return 0;
4325}
4326EXPORT_SYMBOL(drm_match_cea_mode);
4327
d9278b4c
JN		 4328static bool drm_valid_cea_vic(u8 vic)
4329{
7befe621 4330 return cea_mode_for_vic(vic) != NULL;
d9278b4c
JN		 4331}
4332
28c03a44 4333static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
0967e6a5 4334{
7befe621
VS		 4335 const struct drm_display_mode *mode = cea_mode_for_vic(video_code);
4336
4337 if (mode)
4338 return mode->picture_aspect_ratio;
4339
4340 return HDMI_PICTURE_ASPECT_NONE;
0967e6a5 4341}
0967e6a5 4342
d2b43473
WL		 4343static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code)
4344{
4345 return edid_4k_modes[video_code].picture_aspect_ratio;
4346}
4347
3f2f6533
LD		 4348/*
4349 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
4350 * specific block).
3f2f6533
LD		 4351 */
4352static unsigned int
4353hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
4354{
3f2f6533
LD		 4355 return cea_mode_alternate_clock(hdmi_mode);
4356}
4357
4c6bcf44
VS		 4358static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
4359 unsigned int clock_tolerance)
4360{
357768cc 4361 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 4362 u8 vic;
4c6bcf44
VS		 4363
4364 if (!to_match->clock)
4365 return 0;
4366
d2b43473
WL		 4367 if (to_match->picture_aspect_ratio)
4368 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4369
d9278b4c
JN		 4370 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
4371 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4c6bcf44
VS		 4372 unsigned int clock1, clock2;
4373
4374 /* Make sure to also match alternate clocks */
4375 clock1 = hdmi_mode->clock;
4376 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
4377
4378 if (abs(to_match->clock - clock1) > clock_tolerance &&
4379 abs(to_match->clock - clock2) > clock_tolerance)
4380 continue;
4381
357768cc 4382 if (drm_mode_match(to_match, hdmi_mode, match_flags))
d9278b4c 4383 return vic;
4c6bcf44
VS		 4384 }
4385
4386 return 0;
4387}
4388
3f2f6533
LD		 4389/*
4390 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
4391 * @to_match: display mode
4392 *
4393 * An HDMI mode is one defined in the HDMI vendor specific block.
4394 *
4395 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
4396 */
4397static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
4398{
357768cc 4399 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 4400 u8 vic;
3f2f6533
LD		 4401
4402 if (!to_match->clock)
4403 return 0;
4404
d2b43473
WL		 4405 if (to_match->picture_aspect_ratio)
4406 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4407
d9278b4c
JN		 4408 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
4409 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3f2f6533
LD		 4410 unsigned int clock1, clock2;
4411
4412 /* Make sure to also match alternate clocks */
4413 clock1 = hdmi_mode->clock;
4414 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
4415
4416 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
4417 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
357768cc 4418 drm_mode_match(to_match, hdmi_mode, match_flags))
d9278b4c 4419 return vic;
3f2f6533
LD		 4420 }
4421 return 0;
4422}
4423
d9278b4c
JN		 4424static bool drm_valid_hdmi_vic(u8 vic)
4425{
4426 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
4427}
4428
40f71f5b
JN		 4429static int add_alternate_cea_modes(struct drm_connector *connector,
4430 const struct drm_edid *drm_edid)
e6e79209
VS		 4431{
4432 struct drm_device *dev = connector->dev;
4433 struct drm_display_mode *mode, *tmp;
4434 LIST_HEAD(list);
4435 int modes = 0;
4436
6ff1c19f 4437 /* Don't add CTA modes if the CTA extension block is missing */
40f71f5b 4438 if (!drm_edid_has_cta_extension(drm_edid))
e6e79209
VS		 4439 return 0;
4440
4441 /*
4442 * Go through all probed modes and create a new mode
4443 * with the alternate clock for certain CEA modes.
4444 */
4445 list_for_each_entry(mode, &connector->probed_modes, head) {
3f2f6533 4446 const struct drm_display_mode *cea_mode = NULL;
e6e79209 4447 struct drm_display_mode *newmode;
d9278b4c 4448 u8 vic = drm_match_cea_mode(mode);
e6e79209
VS		 4449 unsigned int clock1, clock2;
4450
d9278b4c 4451 if (drm_valid_cea_vic(vic)) {
7befe621 4452 cea_mode = cea_mode_for_vic(vic);
3f2f6533
LD		 4453 clock2 = cea_mode_alternate_clock(cea_mode);
4454 } else {
d9278b4c
JN		 4455 vic = drm_match_hdmi_mode(mode);
4456 if (drm_valid_hdmi_vic(vic)) {
4457 cea_mode = &edid_4k_modes[vic];
3f2f6533
LD		 4458 clock2 = hdmi_mode_alternate_clock(cea_mode);
4459 }
4460 }
e6e79209 4461
3f2f6533
LD		 4462 if (!cea_mode)
4463 continue;
e6e79209
VS		 4464
4465 clock1 = cea_mode->clock;
e6e79209
VS		 4466
4467 if (clock1 == clock2)
4468 continue;
4469
4470 if (mode->clock != clock1 && mode->clock != clock2)
4471 continue;
4472
4473 newmode = drm_mode_duplicate(dev, cea_mode);
4474 if (!newmode)
4475 continue;
4476
27130212
DL		 4477 /* Carry over the stereo flags */
4478 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
4479
e6e79209
VS		 4480 /*
4481 * The current mode could be either variant. Make
4482 * sure to pick the "other" clock for the new mode.
4483 */
4484 if (mode->clock != clock1)
4485 newmode->clock = clock1;
4486 else
4487 newmode->clock = clock2;
4488
4489 list_add_tail(&newmode->head, &list);
4490 }
4491
4492 list_for_each_entry_safe(mode, tmp, &list, head) {
4493 list_del(&mode->head);
4494 drm_mode_probed_add(connector, mode);
4495 modes++;
4496 }
4497
4498 return modes;
4499}
a4799037 4500
8ec6e075
SS		 4501static u8 svd_to_vic(u8 svd)
4502{
4503 /* 0-6 bit vic, 7th bit native mode indicator */
4504 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
4505 return svd & 127;
4506
4507 return svd;
4508}
4509
6a40a75f
JN		 4510/*
4511 * Return a display mode for the 0-based vic_index'th VIC across all CTA VDBs in
4512 * the EDID, or NULL on errors.
4513 */
aff04ace 4514static struct drm_display_mode *
6a40a75f 4515drm_display_mode_from_vic_index(struct drm_connector *connector, int vic_index)
54ac76f8 4516{
6a40a75f 4517 const struct drm_display_info *info = &connector->display_info;
54ac76f8 4518 struct drm_device *dev = connector->dev;
54ac76f8 4519
6a40a75f 4520 if (!info->vics || vic_index >= info->vics_len || !info->vics[vic_index])
aff04ace
TW		 4521 return NULL;
4522
6a40a75f 4523 return drm_display_mode_from_cea_vic(dev, info->vics[vic_index]);
aff04ace
TW		 4524}
4525
832d4f2f
SS		 4526/*
4527 * do_y420vdb_modes - Parse YCBCR 420 only modes
4528 * @connector: connector corresponding to the HDMI sink
4529 * @svds: start of the data block of CEA YCBCR 420 VDB
4530 * @len: length of the CEA YCBCR 420 VDB
4531 *
4532 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
4533 * which contains modes which can be supported in YCBCR 420
4534 * output format only.
4535 */
4536static int do_y420vdb_modes(struct drm_connector *connector,
4537 const u8 *svds, u8 svds_len)
4538{
832d4f2f 4539 struct drm_device *dev = connector->dev;
c54e2e23 4540 int modes = 0, i;
832d4f2f
SS		 4541
4542 for (i = 0; i < svds_len; i++) {
4543 u8 vic = svd_to_vic(svds[i]);
4544 struct drm_display_mode *newmode;
4545
4546 if (!drm_valid_cea_vic(vic))
4547 continue;
4548
7befe621 4549 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
832d4f2f
SS		 4550 if (!newmode)
4551 break;
832d4f2f
SS		 4552 drm_mode_probed_add(connector, newmode);
4553 modes++;
4554 }
4555
832d4f2f
SS		 4556 return modes;
4557}
4558
7af655bc
VS		 4559/**
4560 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC
4561 * @dev: DRM device
8d7d8c0a 4562 * @video_code: CEA VIC of the mode
7af655bc
VS		 4563 *
4564 * Creates a new mode matching the specified CEA VIC.
4565 *
4566 * Returns: A new drm_display_mode on success or NULL on failure
4567 */
4568struct drm_display_mode *
4569drm_display_mode_from_cea_vic(struct drm_device *dev,
4570 u8 video_code)
4571{
4572 const struct drm_display_mode *cea_mode;
4573 struct drm_display_mode *newmode;
4574
4575 cea_mode = cea_mode_for_vic(video_code);
4576 if (!cea_mode)
4577 return NULL;
4578
4579 newmode = drm_mode_duplicate(dev, cea_mode);
4580 if (!newmode)
4581 return NULL;
4582
4583 return newmode;
4584}
4585EXPORT_SYMBOL(drm_display_mode_from_cea_vic);
4586
6a40a75f
JN		 4587/* Add modes based on VICs parsed in parse_cta_vdb() */
4588static int add_cta_vdb_modes(struct drm_connector *connector)
aff04ace 4589{
6a40a75f 4590 const struct drm_display_info *info = &connector->display_info;
aff04ace
TW		 4591 int i, modes = 0;
4592
6a40a75f
JN		 4593 if (!info->vics)
4594 return 0;
4595
4596 for (i = 0; i < info->vics_len; i++) {
aff04ace 4597 struct drm_display_mode *mode;
948de842 4598
6a40a75f 4599 mode = drm_display_mode_from_vic_index(connector, i);
aff04ace
TW		 4600 if (mode) {
4601 drm_mode_probed_add(connector, mode);
4602 modes++;
54ac76f8
CS		 4603 }
4604 }
4605
4606 return modes;
4607}
4608
c858cfca
DL		 4609struct stereo_mandatory_mode {
4610 int width, height, vrefresh;
4611 unsigned int flags;
4612};
4613
4614static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
f7e121b7
DL		 4615 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4616 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
c858cfca
DL		 4617 { 1920, 1080, 50,
4618 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
4619 { 1920, 1080, 60,
4620 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
f7e121b7
DL		 4621 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4622 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
4623 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4624 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
c858cfca
DL		 4625};
4626
4627static bool
4628stereo_match_mandatory(const struct drm_display_mode *mode,
4629 const struct stereo_mandatory_mode *stereo_mode)
4630{
4631 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
4632
4633 return mode->hdisplay == stereo_mode->width &&
4634 mode->vdisplay == stereo_mode->height &&
4635 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
4636 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
4637}
4638
c858cfca
DL		 4639static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
4640{
4641 struct drm_device *dev = connector->dev;
4642 const struct drm_display_mode *mode;
4643 struct list_head stereo_modes;
f7e121b7 4644 int modes = 0, i;
c858cfca
DL		 4645
4646 INIT_LIST_HEAD(&stereo_modes);
4647
4648 list_for_each_entry(mode, &connector->probed_modes, head) {
f7e121b7
DL		 4649 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
4650 const struct stereo_mandatory_mode *mandatory;
c858cfca
DL		 4651 struct drm_display_mode *new_mode;
4652
f7e121b7
DL		 4653 if (!stereo_match_mandatory(mode,
4654 &stereo_mandatory_modes[i]))
4655 continue;
c858cfca 4656
f7e121b7 4657 mandatory = &stereo_mandatory_modes[i];
c858cfca
DL		 4658 new_mode = drm_mode_duplicate(dev, mode);
4659 if (!new_mode)
4660 continue;
4661
f7e121b7 4662 new_mode->flags |= mandatory->flags;
c858cfca
DL		 4663 list_add_tail(&new_mode->head, &stereo_modes);
4664 modes++;
f7e121b7 4665 }
c858cfca
DL		 4666 }
4667
4668 list_splice_tail(&stereo_modes, &connector->probed_modes);
4669
4670 return modes;
4671}
4672
1deee8d7
DL		 4673static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
4674{
4675 struct drm_device *dev = connector->dev;
4676 struct drm_display_mode *newmode;
4677
d9278b4c 4678 if (!drm_valid_hdmi_vic(vic)) {
e1e7bc48
JN		 4679 drm_err(connector->dev, "[CONNECTOR:%d:%s] Unknown HDMI VIC: %d\n",
4680 connector->base.id, connector->name, vic);
1deee8d7
DL		 4681 return 0;
4682 }
4683
4684 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
4685 if (!newmode)
4686 return 0;
4687
4688 drm_mode_probed_add(connector, newmode);
4689
4690 return 1;
4691}
4692
fbf46025 4693static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
6a40a75f 4694 int vic_index)
fbf46025 4695{
fbf46025
TW		 4696 struct drm_display_mode *newmode;
4697 int modes = 0;
fbf46025
TW		 4698
4699 if (structure & (1 << 0)) {
6a40a75f 4700 newmode = drm_display_mode_from_vic_index(connector, vic_index);
fbf46025
TW		 4701 if (newmode) {
4702 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
4703 drm_mode_probed_add(connector, newmode);
4704 modes++;
4705 }
4706 }
4707 if (structure & (1 << 6)) {
6a40a75f 4708 newmode = drm_display_mode_from_vic_index(connector, vic_index);
fbf46025
TW		 4709 if (newmode) {
4710 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4711 drm_mode_probed_add(connector, newmode);
4712 modes++;
4713 }
4714 }
4715 if (structure & (1 << 8)) {
6a40a75f 4716 newmode = drm_display_mode_from_vic_index(connector, vic_index);
fbf46025 4717 if (newmode) {
89570eeb 4718 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
fbf46025
TW		 4719 drm_mode_probed_add(connector, newmode);
4720 modes++;
4721 }
4722 }
4723
4724 return modes;
4725}
4726
1ee3e217
JN		 4727static bool hdmi_vsdb_latency_present(const u8 *db)
4728{
4729 return db[8] & BIT(7);
4730}
4731
4732static bool hdmi_vsdb_i_latency_present(const u8 *db)
4733{
4734 return hdmi_vsdb_latency_present(db) && db[8] & BIT(6);
4735}
4736
cba83c1f
JN		 4737static int hdmi_vsdb_latency_length(const u8 *db)
4738{
4739 if (hdmi_vsdb_i_latency_present(db))
4740 return 4;
4741 else if (hdmi_vsdb_latency_present(db))
4742 return 2;
4743 else
4744 return 0;
4745}
4746
7ebe1963
LD		 4747/*
4748 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
4749 * @connector: connector corresponding to the HDMI sink
4750 * @db: start of the CEA vendor specific block
4751 * @len: length of the CEA block payload, ie. one can access up to db[len]
4752 *
c858cfca
DL		 4753 * Parses the HDMI VSDB looking for modes to add to @connector. This function
4754 * also adds the stereo 3d modes when applicable.
7ebe1963
LD		 4755 */
4756static int
6a40a75f 4757do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len)
7ebe1963 4758{
0e5083aa 4759 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
fbf46025
TW		 4760 u8 vic_len, hdmi_3d_len = 0;
4761 u16 mask;
4762 u16 structure_all;
7ebe1963
LD		 4763
4764 if (len < 8)
4765 goto out;
4766
4767 /* no HDMI_Video_Present */
4768 if (!(db[8] & (1 << 5)))
4769 goto out;
4770
cba83c1f 4771 offset += hdmi_vsdb_latency_length(db);
7ebe1963
LD		 4772
4773 /* the declared length is not long enough for the 2 first bytes
4774 * of additional video format capabilities */
c858cfca 4775 if (len < (8 + offset + 2))
7ebe1963
LD		 4776 goto out;
4777
c858cfca
DL		 4778 /* 3D_Present */
4779 offset++;
fbf46025 4780 if (db[8 + offset] & (1 << 7)) {
c858cfca
DL		 4781 modes += add_hdmi_mandatory_stereo_modes(connector);
4782
fbf46025
TW		 4783 /* 3D_Multi_present */
4784 multi_present = (db[8 + offset] & 0x60) >> 5;
4785 }
4786
c858cfca 4787 offset++;
7ebe1963 4788 vic_len = db[8 + offset] >> 5;
fbf46025 4789 hdmi_3d_len = db[8 + offset] & 0x1f;
7ebe1963
LD		 4790
4791 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
7ebe1963
LD		 4792 u8 vic;
4793
4794 vic = db[9 + offset + i];
1deee8d7 4795 modes += add_hdmi_mode(connector, vic);
7ebe1963 4796 }
fbf46025
TW		 4797 offset += 1 + vic_len;
4798
0e5083aa
TW		 4799 if (multi_present == 1)
4800 multi_len = 2;
4801 else if (multi_present == 2)
4802 multi_len = 4;
4803 else
4804 multi_len = 0;
fbf46025 4805
0e5083aa 4806 if (len < (8 + offset + hdmi_3d_len - 1))
fbf46025
TW		 4807 goto out;
4808
0e5083aa 4809 if (hdmi_3d_len < multi_len)
fbf46025
TW		 4810 goto out;
4811
0e5083aa
TW		 4812 if (multi_present == 1 || multi_present == 2) {
4813 /* 3D_Structure_ALL */
4814 structure_all = (db[8 + offset] << 8) | db[9 + offset];
fbf46025 4815
0e5083aa
TW		 4816 /* check if 3D_MASK is present */
4817 if (multi_present == 2)
4818 mask = (db[10 + offset] << 8) | db[11 + offset];
4819 else
4820 mask = 0xffff;
4821
4822 for (i = 0; i < 16; i++) {
4823 if (mask & (1 << i))
4824 modes += add_3d_struct_modes(connector,
6a40a75f 4825 structure_all, i);
0e5083aa
TW		 4826 }
4827 }
4828
4829 offset += multi_len;
4830
4831 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
4832 int vic_index;
4833 struct drm_display_mode *newmode = NULL;
4834 unsigned int newflag = 0;
4835 bool detail_present;
4836
4837 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
4838
4839 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
4840 break;
4841
4842 /* 2D_VIC_order_X */
4843 vic_index = db[8 + offset + i] >> 4;
4844
4845 /* 3D_Structure_X */
4846 switch (db[8 + offset + i] & 0x0f) {
4847 case 0:
4848 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
4849 break;
4850 case 6:
4851 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4852 break;
4853 case 8:
4854 /* 3D_Detail_X */
4855 if ((db[9 + offset + i] >> 4) == 1)
4856 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4857 break;
4858 }
4859
4860 if (newflag != 0) {
4861 newmode = drm_display_mode_from_vic_index(connector,
0e5083aa
TW		 4862 vic_index);
4863
4864 if (newmode) {
4865 newmode->flags |= newflag;
4866 drm_mode_probed_add(connector, newmode);
4867 modes++;
4868 }
4869 }
4870
4871 if (detail_present)
4872 i++;
fbf46025 4873 }
7ebe1963
LD		 4874
4875out:
4876 return modes;
4877}
4878
9e50b9d5
VS		 4879static int
4880cea_revision(const u8 *cea)
4881{
5036c0d0
VS		 4882 /*
4883 * FIXME is this correct for the DispID variant?
4884 * The DispID spec doesn't really specify whether
4885 * this is the revision of the CEA extension or
4886 * the DispID CEA data block. And the only value
4887 * given as an example is 0.
4888 */
9e50b9d5
VS		 4889 return cea[1];
4890}
4891
aba58254
JN		 4892/*
4893 * CTA Data Block iterator.
4894 *
4895 * Iterate through all CTA Data Blocks in both EDID CTA Extensions and DisplayID
4896 * CTA Data Blocks.
4897 *
4898 * struct cea_db *db:
4899 * struct cea_db_iter iter;
4900 *
4901 * cea_db_iter_edid_begin(edid, &iter);
4902 * cea_db_iter_for_each(db, &iter) {
4903 * // do stuff with db
4904 * }
4905 * cea_db_iter_end(&iter);
4906 */
4907struct cea_db_iter {
4908 struct drm_edid_iter edid_iter;
4909 struct displayid_iter displayid_iter;
4910
4911 /* Current Data Block Collection. */
4912 const u8 *collection;
4913
4914 /* Current Data Block index in current collection. */
4915 int index;
4916
4917 /* End index in current collection. */
4918 int end;
4919};
4920
4921/* CTA-861-H section 7.4 CTA Data BLock Collection */
4922struct cea_db {
4923 u8 tag_length;
4924 u8 data[];
4925} __packed;
4926
49a62a29 4927static int cea_db_tag(const struct cea_db *db)
aba58254 4928{
aba58254
JN		 4929 return db->tag_length >> 5;
4930}
4931
4932static int cea_db_payload_len(const void *_db)
4933{
4934 /* FIXME: Transition to passing struct cea_db * everywhere. */
4935 const struct cea_db *db = _db;
4936
4937 return db->tag_length & 0x1f;
4938}
4939
4940static const void *cea_db_data(const struct cea_db *db)
4941{
4942 return db->data;
4943}
4944
a9ec4fd0
JN		 4945static bool cea_db_is_extended_tag(const struct cea_db *db, int tag)
4946{
4947 return cea_db_tag(db) == CTA_DB_EXTENDED_TAG &&
4948 cea_db_payload_len(db) >= 1 &&
4949 db->data[0] == tag;
4950}
4951
4952static bool cea_db_is_vendor(const struct cea_db *db, int vendor_oui)
4953{
4954 const u8 *data = cea_db_data(db);
4955
4956 return cea_db_tag(db) == CTA_DB_VENDOR &&
4957 cea_db_payload_len(db) >= 3 &&
4958 oui(data[2], data[1], data[0]) == vendor_oui;
4959}
4960
5e87b2e5
JN		 4961static void cea_db_iter_edid_begin(const struct drm_edid *drm_edid,
4962 struct cea_db_iter *iter)
aba58254
JN		 4963{
4964 memset(iter, 0, sizeof(*iter));
4965
bbded689 4966 drm_edid_iter_begin(drm_edid, &iter->edid_iter);
d9ba1b4c 4967 displayid_iter_edid_begin(drm_edid, &iter->displayid_iter);
aba58254
JN		 4968}
4969
4970static const struct cea_db *
4971__cea_db_iter_current_block(const struct cea_db_iter *iter)
4972{
4973 const struct cea_db *db;
4974
4975 if (!iter->collection)
4976 return NULL;
4977
4978 db = (const struct cea_db *)&iter->collection[iter->index];
4979
4980 if (iter->index + sizeof(*db) <= iter->end &&
4981 iter->index + sizeof(*db) + cea_db_payload_len(db) <= iter->end)
4982 return db;
4983
4984 return NULL;
4985}
4986
11a8d095
JN		 4987/*
4988 * References:
4989 * - CTA-861-H section 7.3.3 CTA Extension Version 3
4990 */
4991static int cea_db_collection_size(const u8 *cta)
4992{
4993 u8 d = cta[2];
4994
4995 if (d < 4 || d > 127)
4996 return 0;
4997
4998 return d - 4;
4999}
5000
aba58254
JN		 5001/*
5002 * References:
5003 * - VESA E-EDID v1.4
5004 * - CTA-861-H section 7.3.3 CTA Extension Version 3
5005 */
5006static const void *__cea_db_iter_edid_next(struct cea_db_iter *iter)
5007{
5008 const u8 *ext;
5009
5010 drm_edid_iter_for_each(ext, &iter->edid_iter) {
11a8d095
JN		 5011 int size;
5012
aba58254
JN		 5013 /* Only support CTA Extension revision 3+ */
5014 if (ext[0] != CEA_EXT || cea_revision(ext) < 3)
5015 continue;
5016
11a8d095
JN		 5017 size = cea_db_collection_size(ext);
5018 if (!size)
aba58254
JN		 5019 continue;
5020
11a8d095
JN		 5021 iter->index = 4;
5022 iter->end = iter->index + size;
5023
aba58254
JN		 5024 return ext;
5025 }
5026
5027 return NULL;
5028}
5029
5030/*
5031 * References:
5032 * - DisplayID v1.3 Appendix C: CEA Data Block within a DisplayID Data Block
5033 * - DisplayID v2.0 section 4.10 CTA DisplayID Data Block
5034 *
5035 * Note that the above do not specify any connection between DisplayID Data
5036 * Block revision and CTA Extension versions.
5037 */
5038static const void *__cea_db_iter_displayid_next(struct cea_db_iter *iter)
5039{
5040 const struct displayid_block *block;
5041
5042 displayid_iter_for_each(block, &iter->displayid_iter) {
5043 if (block->tag != DATA_BLOCK_CTA)
5044 continue;
5045
5046 /*
5047 * The displayid iterator has already verified the block bounds
5048 * in displayid_iter_block().
5049 */
5050 iter->index = sizeof(*block);
5051 iter->end = iter->index + block->num_bytes;
5052
5053 return block;
5054 }
5055
5056 return NULL;
5057}
5058
5059static const struct cea_db *__cea_db_iter_next(struct cea_db_iter *iter)
5060{
5061 const struct cea_db *db;
5062
5063 if (iter->collection) {
5064 /* Current collection should always be valid. */
5065 db = __cea_db_iter_current_block(iter);
5066 if (WARN_ON(!db)) {
5067 iter->collection = NULL;
5068 return NULL;
5069 }
5070
5071 /* Next block in CTA Data Block Collection */
5072 iter->index += sizeof(*db) + cea_db_payload_len(db);
5073
5074 db = __cea_db_iter_current_block(iter);
5075 if (db)
5076 return db;
5077 }
5078
5079 for (;;) {
5080 /*
5081 * Find the next CTA Data Block Collection. First iterate all
5082 * the EDID CTA Extensions, then all the DisplayID CTA blocks.
5083 *
5084 * Per DisplayID v1.3 Appendix B: DisplayID as an EDID
5085 * Extension, it's recommended that DisplayID extensions are
5086 * exposed after all of the CTA Extensions.
5087 */
5088 iter->collection = __cea_db_iter_edid_next(iter);
5089 if (!iter->collection)
5090 iter->collection = __cea_db_iter_displayid_next(iter);
5091
5092 if (!iter->collection)
5093 return NULL;
5094
5095 db = __cea_db_iter_current_block(iter);
5096 if (db)
5097 return db;
5098 }
5099}
5100
5101#define cea_db_iter_for_each(__db, __iter) \
5102 while (((__db) = __cea_db_iter_next(__iter)))
5103
5104static void cea_db_iter_end(struct cea_db_iter *iter)
5105{
5106 displayid_iter_end(&iter->displayid_iter);
5107 drm_edid_iter_end(&iter->edid_iter);
5108
5109 memset(iter, 0, sizeof(*iter));
5110}
5111
49a62a29 5112static bool cea_db_is_hdmi_vsdb(const struct cea_db *db)
7ebe1963 5113{
a9ec4fd0
JN		 5114 return cea_db_is_vendor(db, HDMI_IEEE_OUI) &&
5115 cea_db_payload_len(db) >= 5;
7ebe1963
LD		 5116}
5117
49a62a29 5118static bool cea_db_is_hdmi_forum_vsdb(const struct cea_db *db)
50dd1bd1 5119{
a9ec4fd0
JN		 5120 return cea_db_is_vendor(db, HDMI_FORUM_IEEE_OUI) &&
5121 cea_db_payload_len(db) >= 7;
50dd1bd1
TR		 5122}
5123
18e3c1d5
JN		 5124static bool cea_db_is_hdmi_forum_eeodb(const void *db)
5125{
5126 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_EEODB) &&
5127 cea_db_payload_len(db) >= 2;
5128}
5129
49a62a29 5130static bool cea_db_is_microsoft_vsdb(const struct cea_db *db)
2869f599 5131{
a9ec4fd0
JN		 5132 return cea_db_is_vendor(db, MICROSOFT_IEEE_OUI) &&
5133 cea_db_payload_len(db) == 21;
2869f599
PZ		 5134}
5135
49a62a29 5136static bool cea_db_is_vcdb(const struct cea_db *db)
1581b2df 5137{
a9ec4fd0
JN		 5138 return cea_db_is_extended_tag(db, CTA_EXT_DB_VIDEO_CAP) &&
5139 cea_db_payload_len(db) == 2;
1581b2df
VS		 5140}
5141
49a62a29 5142static bool cea_db_is_hdmi_forum_scdb(const struct cea_db *db)
115fcf58 5143{
a9ec4fd0
JN		 5144 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_SCDB) &&
5145 cea_db_payload_len(db) >= 7;
115fcf58
LS		 5146}
5147
49a62a29 5148static bool cea_db_is_y420cmdb(const struct cea_db *db)
832d4f2f 5149{
a9ec4fd0 5150 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_CAP_MAP);
832d4f2f
SS		 5151}
5152
49a62a29 5153static bool cea_db_is_y420vdb(const struct cea_db *db)
832d4f2f 5154{
a9ec4fd0
JN		 5155 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_DATA);
5156}
832d4f2f 5157
49a62a29 5158static bool cea_db_is_hdmi_hdr_metadata_block(const struct cea_db *db)
a9ec4fd0
JN		 5159{
5160 return cea_db_is_extended_tag(db, CTA_EXT_DB_HDR_STATIC_METADATA) &&
5161 cea_db_payload_len(db) >= 3;
832d4f2f
SS		 5162}
5163
18e3c1d5
JN		 5164/*
5165 * Get the HF-EEODB override extension block count from EDID.
5166 *
5167 * The passed in EDID may be partially read, as long as it has at least two
5168 * blocks (base block and one extension block) if EDID extension count is > 0.
5169 *
5170 * Note that this is *not* how you should parse CTA Data Blocks in general; this
5171 * is only to handle partially read EDIDs. Normally, use the CTA Data Block
5172 * iterators instead.
5173 *
5174 * References:
5175 * - HDMI 2.1 section 10.3.6 HDMI Forum EDID Extension Override Data Block
5176 */
5177static int edid_hfeeodb_extension_block_count(const struct edid *edid)
5178{
5179 const u8 *cta;
5180
5181 /* No extensions according to base block, no HF-EEODB. */
5182 if (!edid_extension_block_count(edid))
5183 return 0;
5184
5185 /* HF-EEODB is always in the first EDID extension block only */
5186 cta = edid_extension_block_data(edid, 0);
5187 if (edid_block_tag(cta) != CEA_EXT || cea_revision(cta) < 3)
5188 return 0;
5189
5190 /* Need to have the data block collection, and at least 3 bytes. */
5191 if (cea_db_collection_size(cta) < 3)
5192 return 0;
5193
5194 /*
5195 * Sinks that include the HF-EEODB in their E-EDID shall include one and
5196 * only one instance of the HF-EEODB in the E-EDID, occupying bytes 4
5197 * through 6 of Block 1 of the E-EDID.
5198 */
5199 if (!cea_db_is_hdmi_forum_eeodb(&cta[4]))
5200 return 0;
5201
5202 return cta[4 + 2];
5203}
5204
61e05fdc
JN		 5205/*
5206 * CTA-861 YCbCr 4:2:0 Capability Map Data Block (CTA Y420CMDB)
5207 *
5208 * Y420CMDB contains a bitmap which gives the index of CTA modes from CTA VDB,
5209 * which can support YCBCR 420 sampling output also (apart from RGB/YCBCR444
5210 * etc). For example, if the bit 0 in bitmap is set, first mode in VDB can
5211 * support YCBCR420 output too.
5212 */
5213static void parse_cta_y420cmdb(struct drm_connector *connector,
5214 const struct cea_db *db, u64 *y420cmdb_map)
832d4f2f
SS		 5215{
5216 struct drm_display_info *info = &connector->display_info;
61e05fdc
JN		 5217 int i, map_len = cea_db_payload_len(db) - 1;
5218 const u8 *data = cea_db_data(db) + 1;
832d4f2f
SS		 5219 u64 map = 0;
5220
5221 if (map_len == 0) {
5222 /* All CEA modes support ycbcr420 sampling also.*/
61e05fdc
JN		 5223 map = U64_MAX;
5224 goto out;
832d4f2f
SS		 5225 }
5226
5227 /*
5228 * This map indicates which of the existing CEA block modes
5229 * from VDB can support YCBCR420 output too. So if bit=0 is
5230 * set, first mode from VDB can support YCBCR420 output too.
5231 * We will parse and keep this map, before parsing VDB itself
5232 * to avoid going through the same block again and again.
5233 *
5234 * Spec is not clear about max possible size of this block.
5235 * Clamping max bitmap block size at 8 bytes. Every byte can
5236 * address 8 CEA modes, in this way this map can address
5237 * 8*8 = first 64 SVDs.
5238 */
5239 if (WARN_ON_ONCE(map_len > 8))
5240 map_len = 8;
5241
61e05fdc
JN		 5242 for (i = 0; i < map_len; i++)
5243 map |= (u64)data[i] << (8 * i);
832d4f2f 5244
61e05fdc 5245out:
832d4f2f 5246 if (map)
c03d0b52 5247 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
832d4f2f 5248
61e05fdc 5249 *y420cmdb_map = map;
832d4f2f
SS		 5250}
5251
40f71f5b
JN		 5252static int add_cea_modes(struct drm_connector *connector,
5253 const struct drm_edid *drm_edid)
54ac76f8 5254{
537d9ed2
JN		 5255 const struct cea_db *db;
5256 struct cea_db_iter iter;
6a40a75f
JN		 5257 int modes;
5258
5259 /* CTA VDB block VICs parsed earlier */
5260 modes = add_cta_vdb_modes(connector);
54ac76f8 5261
5e87b2e5 5262 cea_db_iter_edid_begin(drm_edid, &iter);
537d9ed2 5263 cea_db_iter_for_each(db, &iter) {
6a40a75f
JN		 5264 if (cea_db_is_hdmi_vsdb(db)) {
5265 modes += do_hdmi_vsdb_modes(connector, (const u8 *)db,
5266 cea_db_payload_len(db));
537d9ed2
JN		 5267 } else if (cea_db_is_y420vdb(db)) {
5268 const u8 *vdb420 = cea_db_data(db) + 1;
5269
5270 /* Add 4:2:0(only) modes present in EDID */
5271 modes += do_y420vdb_modes(connector, vdb420,
5272 cea_db_payload_len(db) - 1);
54ac76f8 5273 }
537d9ed2
JN		 5274 }
5275 cea_db_iter_end(&iter);
c858cfca 5276
54ac76f8
CS		 5277 return modes;
5278}
5279
e1e7bc48
JN		 5280static void fixup_detailed_cea_mode_clock(struct drm_connector *connector,
5281 struct drm_display_mode *mode)
fa3a7340
VS		 5282{
5283 const struct drm_display_mode *cea_mode;
5284 int clock1, clock2, clock;
d9278b4c 5285 u8 vic;
fa3a7340
VS		 5286 const char *type;
5287
4c6bcf44
VS		 5288 /*
5289 * allow 5kHz clock difference either way to account for
5290 * the 10kHz clock resolution limit of detailed timings.
5291 */
d9278b4c
JN		 5292 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
5293 if (drm_valid_cea_vic(vic)) {
fa3a7340 5294 type = "CEA";
7befe621 5295 cea_mode = cea_mode_for_vic(vic);
fa3a7340
VS		 5296 clock1 = cea_mode->clock;
5297 clock2 = cea_mode_alternate_clock(cea_mode);
5298 } else {
d9278b4c
JN		 5299 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
5300 if (drm_valid_hdmi_vic(vic)) {
fa3a7340 5301 type = "HDMI";
d9278b4c 5302 cea_mode = &edid_4k_modes[vic];
fa3a7340
VS		 5303 clock1 = cea_mode->clock;
5304 clock2 = hdmi_mode_alternate_clock(cea_mode);
5305 } else {
5306 return;
5307 }
5308 }
5309
5310 /* pick whichever is closest */
5311 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
5312 clock = clock1;
5313 else
5314 clock = clock2;
5315
5316 if (mode->clock == clock)
5317 return;
5318
e1e7bc48
JN		 5319 drm_dbg_kms(connector->dev,
5320 "[CONNECTOR:%d:%s] detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
5321 connector->base.id, connector->name,
5322 type, vic, mode->clock, clock);
fa3a7340
VS		 5323 mode->clock = clock;
5324}
5325
82068ede
JH		 5326static void drm_calculate_luminance_range(struct drm_connector *connector)
5327{
5328 struct hdr_static_metadata *hdr_metadata = &connector->hdr_sink_metadata.hdmi_type1;
5329 struct drm_luminance_range_info *luminance_range =
5330 &connector->display_info.luminance_range;
5331 static const u8 pre_computed_values[] = {
5332 50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69,
5333 71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98
5334 };
5335 u32 max_avg, min_cll, max, min, q, r;
5336
5337 if (!(hdr_metadata->metadata_type & BIT(HDMI_STATIC_METADATA_TYPE1)))
5338 return;
5339
5340 max_avg = hdr_metadata->max_fall;
5341 min_cll = hdr_metadata->min_cll;
5342
5343 /*
5344 * From the specification (CTA-861-G), for calculating the maximum
5345 * luminance we need to use:
5346 * Luminance = 50*2**(CV/32)
5347 * Where CV is a one-byte value.
5348 * For calculating this expression we may need float point precision;
5349 * to avoid this complexity level, we take advantage that CV is divided
5350 * by a constant. From the Euclids division algorithm, we know that CV
5351 * can be written as: CV = 32*q + r. Next, we replace CV in the
5352 * Luminance expression and get 50*(2**q)*(2**(r/32)), hence we just
5353 * need to pre-compute the value of r/32. For pre-computing the values
5354 * We just used the following Ruby line:
5355 * (0...32).each {|cv| puts (50*2**(cv/32.0)).round}
5356 * The results of the above expressions can be verified at
5357 * pre_computed_values.
5358 */
5359 q = max_avg >> 5;
5360 r = max_avg % 32;
5361 max = (1 << q) * pre_computed_values[r];
5362
5363 /* min luminance: maxLum * (CV/255)^2 / 100 */
5364 q = DIV_ROUND_CLOSEST(min_cll, 255);
5365 min = max * DIV_ROUND_CLOSEST((q * q), 100);
5366
5367 luminance_range->min_luminance = min;
5368 luminance_range->max_luminance = max;
5369}
5370
e85959d6
US		 5371static uint8_t eotf_supported(const u8 *edid_ext)
5372{
5373 return edid_ext[2] &
5374 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
5375 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
b5e3eed1
VS		 5376 BIT(HDMI_EOTF_SMPTE_ST2084) |
5377 BIT(HDMI_EOTF_BT_2100_HLG));
e85959d6
US		 5378}
5379
5380static uint8_t hdr_metadata_type(const u8 *edid_ext)
5381{
5382 return edid_ext[3] &
5383 BIT(HDMI_STATIC_METADATA_TYPE1);
5384}
5385
5386static void
5387drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
5388{
5389 u16 len;
5390
5391 len = cea_db_payload_len(db);
5392
5393 connector->hdr_sink_metadata.hdmi_type1.eotf =
5394 eotf_supported(db);
5395 connector->hdr_sink_metadata.hdmi_type1.metadata_type =
5396 hdr_metadata_type(db);
5397
5398 if (len >= 4)
5399 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4];
5400 if (len >= 5)
5401 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5];
82068ede 5402 if (len >= 6) {
e85959d6 5403 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6];
82068ede
JH		 5404
5405 /* Calculate only when all values are available */
5406 drm_calculate_luminance_range(connector);
5407 }
e85959d6
US		 5408}
5409
1ee3e217 5410/* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */
76adaa34 5411static void
23ebf8b9 5412drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
76adaa34 5413{
8504072a 5414 u8 len = cea_db_payload_len(db);
76adaa34 5415
f7da7785
JN		 5416 if (len >= 6 && (db[6] & (1 << 7)))
5417 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
1ee3e217
JN		 5418
5419 if (len >= 10 && hdmi_vsdb_latency_present(db)) {
5420 connector->latency_present[0] = true;
8504072a 5421 connector->video_latency[0] = db[9];
8504072a 5422 connector->audio_latency[0] = db[10];
1ee3e217
JN		 5423 }
5424
5425 if (len >= 12 && hdmi_vsdb_i_latency_present(db)) {
5426 connector->latency_present[1] = true;
8504072a 5427 connector->video_latency[1] = db[11];
8504072a 5428 connector->audio_latency[1] = db[12];
1ee3e217 5429 }
76adaa34 5430
e1e7bc48
JN		 5431 drm_dbg_kms(connector->dev,
5432 "[CONNECTOR:%d:%s] HDMI: latency present %d %d, video latency %d %d, audio latency %d %d\n",
5433 connector->base.id, connector->name,
5434 connector->latency_present[0], connector->latency_present[1],
5435 connector->video_latency[0], connector->video_latency[1],
5436 connector->audio_latency[0], connector->audio_latency[1]);
76adaa34
WF		 5437}
5438
5439static void
4194442d 5440monitor_name(const struct detailed_timing *timing, void *data)
76adaa34 5441{
4194442d
JN		 5442 const char **res = data;
5443
5444 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME))
a7a131ac
VS		 5445 return;
5446
4194442d 5447 *res = timing->data.other_data.data.str.str;
14f77fdd
VS		 5448}
5449
2c54f87c 5450static int get_monitor_name(const struct drm_edid *drm_edid, char name[13])
59f7c0fa 5451{
4194442d 5452 const char *edid_name = NULL;
59f7c0fa
JB		 5453 int mnl;
5454
2c54f87c 5455 if (!drm_edid || !name)
59f7c0fa
JB		 5456 return 0;
5457
45aa2336 5458 drm_for_each_detailed_block(drm_edid, monitor_name, &edid_name);
59f7c0fa
JB		 5459 for (mnl = 0; edid_name && mnl < 13; mnl++) {
5460 if (edid_name[mnl] == 0x0a)
5461 break;
5462
5463 name[mnl] = edid_name[mnl];
5464 }
5465
5466 return mnl;
5467}
5468
5469/**
5470 * drm_edid_get_monitor_name - fetch the monitor name from the edid
5471 * @edid: monitor EDID information
5472 * @name: pointer to a character array to hold the name of the monitor
5473 * @bufsize: The size of the name buffer (should be at least 14 chars.)
5474 *
5475 */
f4e558ec 5476void drm_edid_get_monitor_name(const struct edid *edid, char *name, int bufsize)
59f7c0fa 5477{
2c54f87c 5478 int name_length = 0;
4d23f484 5479
59f7c0fa
JB		 5480 if (bufsize <= 0)
5481 return;
5482
2c54f87c
JN		 5483 if (edid) {
5484 char buf[13];
5485 struct drm_edid drm_edid = {
5486 .edid = edid,
5487 .size = edid_size(edid),
5488 };
5489
5490 name_length = min(get_monitor_name(&drm_edid, buf), bufsize - 1);
5491 memcpy(name, buf, name_length);
5492 }
5493
59f7c0fa
JB		 5494 name[name_length] = '\0';
5495}
5496EXPORT_SYMBOL(drm_edid_get_monitor_name);
5497
42750d39
JN		 5498static void clear_eld(struct drm_connector *connector)
5499{
5500 memset(connector->eld, 0, sizeof(connector->eld));
5501
5502 connector->latency_present[0] = false;
5503 connector->latency_present[1] = false;
5504 connector->video_latency[0] = 0;
5505 connector->audio_latency[0] = 0;
5506 connector->video_latency[1] = 0;
5507 connector->audio_latency[1] = 0;
5508}
5509
79436a1c 5510/*
76adaa34
WF		 5511 * drm_edid_to_eld - build ELD from EDID
5512 * @connector: connector corresponding to the HDMI/DP sink
a2f9790d 5513 * @drm_edid: EDID to parse
76adaa34 5514 *
db6cf833 5515 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
1d1c3665 5516 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
76adaa34 5517 */
f4e558ec 5518static void drm_edid_to_eld(struct drm_connector *connector,
a2f9790d 5519 const struct drm_edid *drm_edid)
76adaa34 5520{
58304630 5521 const struct drm_display_info *info = &connector->display_info;
37852141
JN		 5522 const struct cea_db *db;
5523 struct cea_db_iter iter;
76adaa34 5524 uint8_t *eld = connector->eld;
7c018782 5525 int total_sad_count = 0;
76adaa34 5526 int mnl;
76adaa34 5527
a2f9790d 5528 if (!drm_edid)
e9bd0b84
JN		 5529 return;
5530
2c54f87c 5531 mnl = get_monitor_name(drm_edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
e1e7bc48
JN		 5532 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD monitor %s\n",
5533 connector->base.id, connector->name,
5534 &eld[DRM_ELD_MONITOR_NAME_STRING]);
59f7c0fa 5535
58304630 5536 eld[DRM_ELD_CEA_EDID_VER_MNL] = info->cea_rev << DRM_ELD_CEA_EDID_VER_SHIFT;
f7da7785 5537 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
76adaa34 5538
f7da7785 5539 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
76adaa34 5540
a2f9790d
JN		 5541 eld[DRM_ELD_MANUFACTURER_NAME0] = drm_edid->edid->mfg_id[0];
5542 eld[DRM_ELD_MANUFACTURER_NAME1] = drm_edid->edid->mfg_id[1];
5543 eld[DRM_ELD_PRODUCT_CODE0] = drm_edid->edid->prod_code[0];
5544 eld[DRM_ELD_PRODUCT_CODE1] = drm_edid->edid->prod_code[1];
76adaa34 5545
5e87b2e5 5546 cea_db_iter_edid_begin(drm_edid, &iter);
37852141
JN		 5547 cea_db_iter_for_each(db, &iter) {
5548 const u8 *data = cea_db_data(db);
5549 int len = cea_db_payload_len(db);
deec222e 5550 int sad_count;
9e50b9d5 5551
37852141
JN		 5552 switch (cea_db_tag(db)) {
5553 case CTA_DB_AUDIO:
5554 /* Audio Data Block, contains SADs */
5555 sad_count = min(len / 3, 15 - total_sad_count);
5556 if (sad_count >= 1)
5557 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
5558 data, sad_count * 3);
5559 total_sad_count += sad_count;
5560 break;
5561 case CTA_DB_SPEAKER:
5562 /* Speaker Allocation Data Block */
5563 if (len >= 1)
5564 eld[DRM_ELD_SPEAKER] = data[0];
5565 break;
5566 case CTA_DB_VENDOR:
5567 /* HDMI Vendor-Specific Data Block */
5568 if (cea_db_is_hdmi_vsdb(db))
5569 drm_parse_hdmi_vsdb_audio(connector, (const u8 *)db);
5570 break;
5571 default:
5572 break;
76adaa34 5573 }
9e50b9d5 5574 }
37852141
JN		 5575 cea_db_iter_end(&iter);
5576
f7da7785 5577 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
76adaa34 5578
1d1c3665
JN		 5579 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5580 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5581 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
5582 else
5583 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
76adaa34 5584
938fd8aa
JN		 5585 eld[DRM_ELD_BASELINE_ELD_LEN] =
5586 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
5587
e1e7bc48
JN		 5588 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD size %d, SAD count %d\n",
5589 connector->base.id, connector->name,
5590 drm_eld_size(eld), total_sad_count);
76adaa34 5591}
76adaa34 5592
bba4b647 5593static int _drm_edid_to_sad(const struct drm_edid *drm_edid,
e8d0b2c0 5594 struct cea_sad **psads)
fe214163 5595{
b07debc2
JN		 5596 const struct cea_db *db;
5597 struct cea_db_iter iter;
fe214163 5598 int count = 0;
fe214163 5599
5e87b2e5 5600 cea_db_iter_edid_begin(drm_edid, &iter);
b07debc2 5601 cea_db_iter_for_each(db, &iter) {
9d72b7e2 5602 if (cea_db_tag(db) == CTA_DB_AUDIO) {
e8d0b2c0 5603 struct cea_sad *sads;
fe214163 5604 int j;
948de842 5605
b07debc2 5606 count = cea_db_payload_len(db) / 3; /* SAD is 3B */
e8d0b2c0
JN		 5607 sads = kcalloc(count, sizeof(*sads), GFP_KERNEL);
5608 *psads = sads;
5609 if (!sads)
fe214163
RM		 5610 return -ENOMEM;
5611 for (j = 0; j < count; j++) {
b07debc2 5612 const u8 *sad = &db->data[j * 3];
fe214163 5613
e8d0b2c0
JN		 5614 sads[j].format = (sad[0] & 0x78) >> 3;
5615 sads[j].channels = sad[0] & 0x7;
5616 sads[j].freq = sad[1] & 0x7F;
5617 sads[j].byte2 = sad[2];
fe214163
RM		 5618 }
5619 break;
5620 }
5621 }
b07debc2
JN		 5622 cea_db_iter_end(&iter);
5623
5624 DRM_DEBUG_KMS("Found %d Short Audio Descriptors\n", count);
fe214163
RM		 5625
5626 return count;
5627}
bba4b647
JN		 5628
5629/**
5630 * drm_edid_to_sad - extracts SADs from EDID
5631 * @edid: EDID to parse
5632 * @sads: pointer that will be set to the extracted SADs
5633 *
5634 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
5635 *
5636 * Note: The returned pointer needs to be freed using kfree().
5637 *
5638 * Return: The number of found SADs or negative number on error.
5639 */
5640int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads)
5641{
5642 struct drm_edid drm_edid;
5643
5644 return _drm_edid_to_sad(drm_edid_legacy_init(&drm_edid, edid), sads);
5645}
fe214163
RM		 5646EXPORT_SYMBOL(drm_edid_to_sad);
5647
02703451
JN		 5648static int _drm_edid_to_speaker_allocation(const struct drm_edid *drm_edid,
5649 u8 **sadb)
d105f476 5650{
ed317307
JN		 5651 const struct cea_db *db;
5652 struct cea_db_iter iter;
d105f476 5653 int count = 0;
d105f476 5654
5e87b2e5 5655 cea_db_iter_edid_begin(drm_edid, &iter);
ed317307
JN		 5656 cea_db_iter_for_each(db, &iter) {
5657 if (cea_db_tag(db) == CTA_DB_SPEAKER &&
5658 cea_db_payload_len(db) == 3) {
5659 *sadb = kmemdup(db->data, cea_db_payload_len(db),
5660 GFP_KERNEL);
5661 if (!*sadb)
5662 return -ENOMEM;
5663 count = cea_db_payload_len(db);
5664 break;
d105f476
AD		 5665 }
5666 }
ed317307
JN		 5667 cea_db_iter_end(&iter);
5668
5669 DRM_DEBUG_KMS("Found %d Speaker Allocation Data Blocks\n", count);
d105f476
AD		 5670
5671 return count;
5672}
02703451
JN		 5673
5674/**
5675 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
5676 * @edid: EDID to parse
5677 * @sadb: pointer to the speaker block
5678 *
5679 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
5680 *
5681 * Note: The returned pointer needs to be freed using kfree().
5682 *
5683 * Return: The number of found Speaker Allocation Blocks or negative number on
5684 * error.
5685 */
5686int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb)
5687{
5688 struct drm_edid drm_edid;
5689
5690 return _drm_edid_to_speaker_allocation(drm_edid_legacy_init(&drm_edid, edid),
5691 sadb);
5692}
d105f476
AD		 5693EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
5694
76adaa34 5695/**
db6cf833 5696 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
76adaa34
WF		 5697 * @connector: connector associated with the HDMI/DP sink
5698 * @mode: the display mode
db6cf833
TR		 5699 *
5700 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
5701 * the sink doesn't support audio or video.
76adaa34
WF		 5702 */
5703int drm_av_sync_delay(struct drm_connector *connector,
3a818d35 5704 const struct drm_display_mode *mode)
76adaa34
WF		 5705{
5706 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
5707 int a, v;
5708
5709 if (!connector->latency_present[0])
5710 return 0;
5711 if (!connector->latency_present[1])
5712 i = 0;
5713
5714 a = connector->audio_latency[i];
5715 v = connector->video_latency[i];
5716
5717 /*
5718 * HDMI/DP sink doesn't support audio or video?
5719 */
5720 if (a == 255 || v == 255)
5721 return 0;
5722
5723 /*
5724 * Convert raw EDID values to millisecond.
5725 * Treat unknown latency as 0ms.
5726 */
5727 if (a)
5728 a = min(2 * (a - 1), 500);
5729 if (v)
5730 v = min(2 * (v - 1), 500);
5731
5732 return max(v - a, 0);
5733}
5734EXPORT_SYMBOL(drm_av_sync_delay);
5735
3176d092 5736static bool _drm_detect_hdmi_monitor(const struct drm_edid *drm_edid)
8fe9790d 5737{
4ce08703
JN		 5738 const struct cea_db *db;
5739 struct cea_db_iter iter;
5740 bool hdmi = false;
f23c20c8
ML		 5741
5742 /*
5743 * Because HDMI identifier is in Vendor Specific Block,
5744 * search it from all data blocks of CEA extension.
5745 */
5e87b2e5 5746 cea_db_iter_edid_begin(drm_edid, &iter);
4ce08703
JN		 5747 cea_db_iter_for_each(db, &iter) {
5748 if (cea_db_is_hdmi_vsdb(db)) {
5749 hdmi = true;
5750 break;
5751 }
f23c20c8 5752 }
4ce08703 5753 cea_db_iter_end(&iter);
f23c20c8 5754
4ce08703 5755 return hdmi;
f23c20c8 5756}
3176d092
JN		 5757
5758/**
5759 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
5760 * @edid: monitor EDID information
5761 *
5762 * Parse the CEA extension according to CEA-861-B.
5763 *
5764 * Drivers that have added the modes parsed from EDID to drm_display_info
5765 * should use &drm_display_info.is_hdmi instead of calling this function.
5766 *
5767 * Return: True if the monitor is HDMI, false if not or unknown.
5768 */
5769bool drm_detect_hdmi_monitor(const struct edid *edid)
5770{
5771 struct drm_edid drm_edid;
5772
5773 return _drm_detect_hdmi_monitor(drm_edid_legacy_init(&drm_edid, edid));
5774}
f23c20c8
ML		 5775EXPORT_SYMBOL(drm_detect_hdmi_monitor);
5776
0c057877 5777static bool _drm_detect_monitor_audio(const struct drm_edid *drm_edid)
8fe9790d 5778{
705bec3e 5779 struct drm_edid_iter edid_iter;
9975af04
JN		 5780 const struct cea_db *db;
5781 struct cea_db_iter iter;
43d16d84 5782 const u8 *edid_ext;
8fe9790d 5783 bool has_audio = false;
8fe9790d 5784
bbded689 5785 drm_edid_iter_begin(drm_edid, &edid_iter);
705bec3e
JN		 5786 drm_edid_iter_for_each(edid_ext, &edid_iter) {
5787 if (edid_ext[0] == CEA_EXT) {
5788 has_audio = edid_ext[3] & EDID_BASIC_AUDIO;
5789 if (has_audio)
5790 break;
5791 }
5792 }
5793 drm_edid_iter_end(&edid_iter);
8fe9790d
ZW		 5794
5795 if (has_audio) {
5796 DRM_DEBUG_KMS("Monitor has basic audio support\n");
5797 goto end;
5798 }
5799
5e87b2e5 5800 cea_db_iter_edid_begin(drm_edid, &iter);
9975af04
JN		 5801 cea_db_iter_for_each(db, &iter) {
5802 if (cea_db_tag(db) == CTA_DB_AUDIO) {
5803 const u8 *data = cea_db_data(db);
5804 int i;
8fe9790d 5805
9975af04 5806 for (i = 0; i < cea_db_payload_len(db); i += 3)
8fe9790d 5807 DRM_DEBUG_KMS("CEA audio format %d\n",
9975af04
JN		 5808 (data[i] >> 3) & 0xf);
5809 has_audio = true;
5810 break;
8fe9790d
ZW		 5811 }
5812 }
9975af04
JN		 5813 cea_db_iter_end(&iter);
5814
8fe9790d
ZW		 5815end:
5816 return has_audio;
5817}
0c057877
JN		 5818
5819/**
5820 * drm_detect_monitor_audio - check monitor audio capability
5821 * @edid: EDID block to scan
5822 *
5823 * Monitor should have CEA extension block.
5824 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
5825 * audio' only. If there is any audio extension block and supported
5826 * audio format, assume at least 'basic audio' support, even if 'basic
5827 * audio' is not defined in EDID.
5828 *
5829 * Return: True if the monitor supports audio, false otherwise.
5830 */
5831bool drm_detect_monitor_audio(const struct edid *edid)
5832{
5833 struct drm_edid drm_edid;
5834
5835 return _drm_detect_monitor_audio(drm_edid_legacy_init(&drm_edid, edid));
5836}
8fe9790d
ZW		 5837EXPORT_SYMBOL(drm_detect_monitor_audio);
5838
b1edd6a6 5839
c8127cf0
VS		 5840/**
5841 * drm_default_rgb_quant_range - default RGB quantization range
5842 * @mode: display mode
5843 *
5844 * Determine the default RGB quantization range for the mode,
5845 * as specified in CEA-861.
5846 *
5847 * Return: The default RGB quantization range for the mode
5848 */
5849enum hdmi_quantization_range
5850drm_default_rgb_quant_range(const struct drm_display_mode *mode)
5851{
5852 /* All CEA modes other than VIC 1 use limited quantization range. */
5853 return drm_match_cea_mode(mode) > 1 ?
5854 HDMI_QUANTIZATION_RANGE_LIMITED :
5855 HDMI_QUANTIZATION_RANGE_FULL;
5856}
5857EXPORT_SYMBOL(drm_default_rgb_quant_range);
5858
c3292ab5
JN		 5859/* CTA-861 Video Data Block (CTA VDB) */
5860static void parse_cta_vdb(struct drm_connector *connector, const struct cea_db *db)
5861{
5862 struct drm_display_info *info = &connector->display_info;
5863 int i, vic_index, len = cea_db_payload_len(db);
5864 const u8 *svds = cea_db_data(db);
5865 u8 *vics;
5866
5867 if (!len)
5868 return;
5869
5870 /* Gracefully handle multiple VDBs, however unlikely that is */
5871 vics = krealloc(info->vics, info->vics_len + len, GFP_KERNEL);
5872 if (!vics)
5873 return;
5874
5875 vic_index = info->vics_len;
5876 info->vics_len += len;
5877 info->vics = vics;
5878
5879 for (i = 0; i < len; i++) {
5880 u8 vic = svd_to_vic(svds[i]);
5881
5882 if (!drm_valid_cea_vic(vic))
5883 vic = 0;
5884
5885 info->vics[vic_index++] = vic;
5886 }
5887}
5888
61e05fdc
JN		 5889/*
5890 * Update y420_cmdb_modes based on previously parsed CTA VDB and Y420CMDB.
5891 *
5892 * Translate the y420cmdb_map based on VIC indexes to y420_cmdb_modes indexed
5893 * using the VICs themselves.
5894 */
5895static void update_cta_y420cmdb(struct drm_connector *connector, u64 y420cmdb_map)
5896{
5897 struct drm_display_info *info = &connector->display_info;
5898 struct drm_hdmi_info *hdmi = &info->hdmi;
5899 int i, len = min_t(int, info->vics_len, BITS_PER_TYPE(y420cmdb_map));
5900
5901 for (i = 0; i < len; i++) {
5902 u8 vic = info->vics[i];
5903
5904 if (vic && y420cmdb_map & BIT_ULL(i))
5905 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
5906 }
5907}
5908
4ed29f39
JN		 5909static bool cta_vdb_has_vic(const struct drm_connector *connector, u8 vic)
5910{
5911 const struct drm_display_info *info = &connector->display_info;
5912 int i;
5913
5914 if (!vic || !info->vics)
5915 return false;
5916
5917 for (i = 0; i < info->vics_len; i++) {
5918 if (info->vics[i] == vic)
5919 return true;
5920 }
5921
5922 return false;
5923}
5924
c54e2e23
JN		 5925/* CTA-861-H YCbCr 4:2:0 Video Data Block (CTA Y420VDB) */
5926static void parse_cta_y420vdb(struct drm_connector *connector,
5927 const struct cea_db *db)
5928{
5929 struct drm_display_info *info = &connector->display_info;
5930 struct drm_hdmi_info *hdmi = &info->hdmi;
5931 const u8 *svds = cea_db_data(db) + 1;
5932 int i;
5933
5934 for (i = 0; i < cea_db_payload_len(db) - 1; i++) {
5935 u8 vic = svd_to_vic(svds[i]);
5936
5937 if (!drm_valid_cea_vic(vic))
5938 continue;
5939
5940 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
5941 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
5942 }
5943}
5944
1581b2df
VS		 5945static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
5946{
5947 struct drm_display_info *info = &connector->display_info;
5948
e1e7bc48
JN		 5949 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] CEA VCDB 0x%02x\n",
5950 connector->base.id, connector->name, db[2]);
1581b2df
VS		 5951
5952 if (db[2] & EDID_CEA_VCDB_QS)
5953 info->rgb_quant_range_selectable = true;
5954}
5955
4499d488
SS		 5956static
5957void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane)
5958{
5959 switch (max_frl_rate) {
5960 case 1:
5961 *max_lanes = 3;
5962 *max_rate_per_lane = 3;
5963 break;
5964 case 2:
5965 *max_lanes = 3;
5966 *max_rate_per_lane = 6;
5967 break;
5968 case 3:
5969 *max_lanes = 4;
5970 *max_rate_per_lane = 6;
5971 break;
5972 case 4:
5973 *max_lanes = 4;
5974 *max_rate_per_lane = 8;
5975 break;
5976 case 5:
5977 *max_lanes = 4;
5978 *max_rate_per_lane = 10;
5979 break;
5980 case 6:
5981 *max_lanes = 4;
5982 *max_rate_per_lane = 12;
5983 break;
5984 case 0:
5985 default:
5986 *max_lanes = 0;
5987 *max_rate_per_lane = 0;
5988 }
5989}
5990
e6a9a2c3
SS		 5991static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
5992 const u8 *db)
5993{
5994 u8 dc_mask;
5995 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
5996
5997 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
9068e02f 5998 hdmi->y420_dc_modes = dc_mask;
e6a9a2c3
SS		 5999}
6000
5e706c4d
AN		 6001static void drm_parse_dsc_info(struct drm_hdmi_dsc_cap *hdmi_dsc,
6002 const u8 *hf_scds)
6003{
5e706c4d
AN		 6004 hdmi_dsc->v_1p2 = hf_scds[11] & DRM_EDID_DSC_1P2;
6005
6006 if (!hdmi_dsc->v_1p2)
6007 return;
6008
6009 hdmi_dsc->native_420 = hf_scds[11] & DRM_EDID_DSC_NATIVE_420;
6010 hdmi_dsc->all_bpp = hf_scds[11] & DRM_EDID_DSC_ALL_BPP;
6011
6012 if (hf_scds[11] & DRM_EDID_DSC_16BPC)
6013 hdmi_dsc->bpc_supported = 16;
6014 else if (hf_scds[11] & DRM_EDID_DSC_12BPC)
6015 hdmi_dsc->bpc_supported = 12;
6016 else if (hf_scds[11] & DRM_EDID_DSC_10BPC)
6017 hdmi_dsc->bpc_supported = 10;
6018 else
6019 /* Supports min 8 BPC if DSC 1.2 is supported*/
6020 hdmi_dsc->bpc_supported = 8;
6021
a07e6f56
AN		 6022 if (cea_db_payload_len(hf_scds) >= 12 && hf_scds[12]) {
6023 u8 dsc_max_slices;
6024 u8 dsc_max_frl_rate;
5e706c4d 6025
a07e6f56
AN		 6026 dsc_max_frl_rate = (hf_scds[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4;
6027 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes,
6028 &hdmi_dsc->max_frl_rate_per_lane);
5e706c4d 6029
a07e6f56
AN		 6030 dsc_max_slices = hf_scds[12] & DRM_EDID_DSC_MAX_SLICES;
6031
6032 switch (dsc_max_slices) {
6033 case 1:
6034 hdmi_dsc->max_slices = 1;
6035 hdmi_dsc->clk_per_slice = 340;
6036 break;
6037 case 2:
6038 hdmi_dsc->max_slices = 2;
6039 hdmi_dsc->clk_per_slice = 340;
6040 break;
6041 case 3:
6042 hdmi_dsc->max_slices = 4;
6043 hdmi_dsc->clk_per_slice = 340;
6044 break;
6045 case 4:
6046 hdmi_dsc->max_slices = 8;
6047 hdmi_dsc->clk_per_slice = 340;
6048 break;
6049 case 5:
6050 hdmi_dsc->max_slices = 8;
6051 hdmi_dsc->clk_per_slice = 400;
6052 break;
6053 case 6:
6054 hdmi_dsc->max_slices = 12;
6055 hdmi_dsc->clk_per_slice = 400;
6056 break;
6057 case 7:
6058 hdmi_dsc->max_slices = 16;
6059 hdmi_dsc->clk_per_slice = 400;
6060 break;
6061 case 0:
6062 default:
6063 hdmi_dsc->max_slices = 0;
6064 hdmi_dsc->clk_per_slice = 0;
6065 }
5e706c4d 6066 }
a07e6f56
AN		 6067
6068 if (cea_db_payload_len(hf_scds) >= 13 && hf_scds[13])
6069 hdmi_dsc->total_chunk_kbytes = hf_scds[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES;
5e706c4d
AN		 6070}
6071
d8cb49d2
JN		 6072/* Sink Capability Data Structure */
6073static void drm_parse_hdmi_forum_scds(struct drm_connector *connector,
6074 const u8 *hf_scds)
afa1c763 6075{
26c2ff77
JN		 6076 struct drm_display_info *info = &connector->display_info;
6077 struct drm_hdmi_info *hdmi = &info->hdmi;
a07e6f56 6078 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap;
5e931c88
AN		 6079 int max_tmds_clock = 0;
6080 u8 max_frl_rate = 0;
6081 bool dsc_support = false;
afa1c763 6082
26c2ff77 6083 info->has_hdmi_infoframe = true;
f1781e9b 6084
d8cb49d2 6085 if (hf_scds[6] & 0x80) {
afa1c763 6086 hdmi->scdc.supported = true;
d8cb49d2 6087 if (hf_scds[6] & 0x40)
afa1c763
SS		 6088 hdmi->scdc.read_request = true;
6089 }
62c58af3
SS		 6090
6091 /*
6092 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
6093 * And as per the spec, three factors confirm this:
6094 * * Availability of a HF-VSDB block in EDID (check)
6095 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
6096 * * SCDC support available (let's check)
6097 * Lets check it out.
6098 */
6099
d8cb49d2 6100 if (hf_scds[5]) {
62c58af3
SS		 6101 struct drm_scdc *scdc = &hdmi->scdc;
6102
5e931c88
AN		 6103 /* max clock is 5000 KHz times block value */
6104 max_tmds_clock = hf_scds[5] * 5000;
6105
62c58af3 6106 if (max_tmds_clock > 340000) {
26c2ff77 6107 info->max_tmds_clock = max_tmds_clock;
62c58af3
SS		 6108 }
6109
6110 if (scdc->supported) {
6111 scdc->scrambling.supported = true;
6112
dbe2d2bf 6113 /* Few sinks support scrambling for clocks < 340M */
d8cb49d2 6114 if ((hf_scds[6] & 0x8))
62c58af3
SS		 6115 scdc->scrambling.low_rates = true;
6116 }
6117 }
e6a9a2c3 6118
d8cb49d2 6119 if (hf_scds[7]) {
d8cb49d2 6120 max_frl_rate = (hf_scds[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4;
4499d488
SS		 6121 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes,
6122 &hdmi->max_frl_rate_per_lane);
6123 }
6124
d8cb49d2 6125 drm_parse_ycbcr420_deep_color_info(connector, hf_scds);
a07e6f56 6126
5e931c88 6127 if (cea_db_payload_len(hf_scds) >= 11 && hf_scds[11]) {
a07e6f56 6128 drm_parse_dsc_info(hdmi_dsc, hf_scds);
5e931c88
AN		 6129 dsc_support = true;
6130 }
6131
6132 drm_dbg_kms(connector->dev,
66d17ecd
JN		 6133 "[CONNECTOR:%d:%s] HF-VSDB: max TMDS clock: %d KHz, HDMI 2.1 support: %s, DSC 1.2 support: %s\n",
6134 connector->base.id, connector->name,
5e931c88 6135 max_tmds_clock, str_yes_no(max_frl_rate), str_yes_no(dsc_support));
afa1c763
SS		 6136}
6137
1cea146a
VS		 6138static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
6139 const u8 *hdmi)
d0c94692 6140{
1826750f 6141 struct drm_display_info *info = &connector->display_info;
d0c94692
MK		 6142 unsigned int dc_bpc = 0;
6143
1cea146a
VS		 6144 /* HDMI supports at least 8 bpc */
6145 info->bpc = 8;
d0c94692 6146
1cea146a
VS		 6147 if (cea_db_payload_len(hdmi) < 6)
6148 return;
6149
6150 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
6151 dc_bpc = 10;
4adc33f3 6152 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_30;
e1e7bc48
JN		 6153 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 30.\n",
6154 connector->base.id, connector->name);
1cea146a
VS		 6155 }
6156
6157 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
6158 dc_bpc = 12;
4adc33f3 6159 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_36;
e1e7bc48
JN		 6160 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 36.\n",
6161 connector->base.id, connector->name);
1cea146a
VS		 6162 }
6163
6164 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
6165 dc_bpc = 16;
4adc33f3 6166 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_48;
e1e7bc48
JN		 6167 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 48.\n",
6168 connector->base.id, connector->name);
1cea146a
VS		 6169 }
6170
6171 if (dc_bpc == 0) {
e1e7bc48
JN		 6172 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] No deep color support on this HDMI sink.\n",
6173 connector->base.id, connector->name);
1cea146a
VS		 6174 return;
6175 }
6176
e1e7bc48
JN		 6177 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Assigning HDMI sink color depth as %d bpc.\n",
6178 connector->base.id, connector->name, dc_bpc);
1cea146a 6179 info->bpc = dc_bpc;
d0c94692 6180
1cea146a
VS		 6181 /* YCRCB444 is optional according to spec. */
6182 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
4adc33f3 6183 info->edid_hdmi_ycbcr444_dc_modes = info->edid_hdmi_rgb444_dc_modes;
e1e7bc48
JN		 6184 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does YCRCB444 in deep color.\n",
6185 connector->base.id, connector->name);
1cea146a 6186 }
d0c94692 6187
1cea146a
VS		 6188 /*
6189 * Spec says that if any deep color mode is supported at all,
6190 * then deep color 36 bit must be supported.
6191 */
6192 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
e1e7bc48
JN		 6193 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink should do DC_36, but does not!\n",
6194 connector->base.id, connector->name);
1cea146a
VS		 6195 }
6196}
d0c94692 6197
919d320f 6198/* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */
23ebf8b9
VS		 6199static void
6200drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
6201{
6202 struct drm_display_info *info = &connector->display_info;
6203 u8 len = cea_db_payload_len(db);
6204
a92d083d
LP		 6205 info->is_hdmi = true;
6206
82b599ec
JN		 6207 info->source_physical_address = (db[4] << 8) | db[5];
6208
23ebf8b9
VS		 6209 if (len >= 6)
6210 info->dvi_dual = db[6] & 1;
6211 if (len >= 7)
6212 info->max_tmds_clock = db[7] * 5000;
6213
919d320f
JN		 6214 /*
6215 * Try to infer whether the sink supports HDMI infoframes.
6216 *
6217 * HDMI infoframe support was first added in HDMI 1.4. Assume the sink
6218 * supports infoframes if HDMI_Video_present is set.
6219 */
6220 if (len >= 8 && db[8] & BIT(5))
6221 info->has_hdmi_infoframe = true;
6222
e1e7bc48
JN		 6223 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI: DVI dual %d, max TMDS clock %d kHz\n",
6224 connector->base.id, connector->name,
6225 info->dvi_dual, info->max_tmds_clock);
23ebf8b9
VS		 6226
6227 drm_parse_hdmi_deep_color_info(connector, db);
6228}
6229
2869f599
PZ		 6230/*
6231 * See EDID extension for head-mounted and specialized monitors, specified at:
6232 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/specialized-monitors-edid-extension
6233 */
6234static void drm_parse_microsoft_vsdb(struct drm_connector *connector,
6235 const u8 *db)
6236{
6237 struct drm_display_info *info = &connector->display_info;
6238 u8 version = db[4];
6239 bool desktop_usage = db[5] & BIT(6);
6240
6241 /* Version 1 and 2 for HMDs, version 3 flags desktop usage explicitly */
6242 if (version == 1 || version == 2 || (version == 3 && !desktop_usage))
6243 info->non_desktop = true;
6244
66d17ecd
JN		 6245 drm_dbg_kms(connector->dev,
6246 "[CONNECTOR:%d:%s] HMD or specialized display VSDB version %u: 0x%02x\n",
6247 connector->base.id, connector->name, version, db[5]);
2869f599
PZ		 6248}
6249
1cea146a 6250static void drm_parse_cea_ext(struct drm_connector *connector,
e42192b4 6251 const struct drm_edid *drm_edid)
1cea146a
VS		 6252{
6253 struct drm_display_info *info = &connector->display_info;
8db73897 6254 struct drm_edid_iter edid_iter;
dfc03125
JN		 6255 const struct cea_db *db;
6256 struct cea_db_iter iter;
1cea146a 6257 const u8 *edid_ext;
61e05fdc 6258 u64 y420cmdb_map = 0;
d0c94692 6259
bbded689 6260 drm_edid_iter_begin(drm_edid, &edid_iter);
8db73897
JN		 6261 drm_edid_iter_for_each(edid_ext, &edid_iter) {
6262 if (edid_ext[0] != CEA_EXT)
6263 continue;
d0c94692 6264
8db73897
JN		 6265 if (!info->cea_rev)
6266 info->cea_rev = edid_ext[1];
d0c94692 6267
8db73897 6268 if (info->cea_rev != edid_ext[1])
e1e7bc48
JN		 6269 drm_dbg_kms(connector->dev,
6270 "[CONNECTOR:%d:%s] CEA extension version mismatch %u != %u\n",
6271 connector->base.id, connector->name,
6272 info->cea_rev, edid_ext[1]);
7344bad7 6273
8db73897
JN		 6274 /* The existence of a CTA extension should imply RGB support */
6275 info->color_formats = DRM_COLOR_FORMAT_RGB444;
7344bad7
JN		 6276 if (edid_ext[3] & EDID_CEA_YCRCB444)
6277 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
6278 if (edid_ext[3] & EDID_CEA_YCRCB422)
6279 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
0374ffa5
JN		 6280 if (edid_ext[3] & EDID_BASIC_AUDIO)
6281 info->has_audio = true;
6282
7344bad7 6283 }
8db73897 6284 drm_edid_iter_end(&edid_iter);
1cea146a 6285
5e87b2e5 6286 cea_db_iter_edid_begin(drm_edid, &iter);
dfc03125
JN		 6287 cea_db_iter_for_each(db, &iter) {
6288 /* FIXME: convert parsers to use struct cea_db */
6289 const u8 *data = (const u8 *)db;
1cea146a 6290
23ebf8b9 6291 if (cea_db_is_hdmi_vsdb(db))
dfc03125 6292 drm_parse_hdmi_vsdb_video(connector, data);
be982415
JN		 6293 else if (cea_db_is_hdmi_forum_vsdb(db) ||
6294 cea_db_is_hdmi_forum_scdb(db))
dfc03125 6295 drm_parse_hdmi_forum_scds(connector, data);
be982415 6296 else if (cea_db_is_microsoft_vsdb(db))
dfc03125 6297 drm_parse_microsoft_vsdb(connector, data);
be982415 6298 else if (cea_db_is_y420cmdb(db))
61e05fdc 6299 parse_cta_y420cmdb(connector, db, &y420cmdb_map);
c54e2e23
JN		 6300 else if (cea_db_is_y420vdb(db))
6301 parse_cta_y420vdb(connector, db);
be982415 6302 else if (cea_db_is_vcdb(db))
dfc03125 6303 drm_parse_vcdb(connector, data);
be982415 6304 else if (cea_db_is_hdmi_hdr_metadata_block(db))
dfc03125 6305 drm_parse_hdr_metadata_block(connector, data);
c3292ab5
JN		 6306 else if (cea_db_tag(db) == CTA_DB_VIDEO)
6307 parse_cta_vdb(connector, db);
0374ffa5
JN		 6308 else if (cea_db_tag(db) == CTA_DB_AUDIO)
6309 info->has_audio = true;
1cea146a 6310 }
dfc03125 6311 cea_db_iter_end(&iter);
61e05fdc
JN		 6312
6313 if (y420cmdb_map)
6314 update_cta_y420cmdb(connector, y420cmdb_map);
d0c94692
MK		 6315}
6316
a1d11d1e 6317static
c7943bb3 6318void get_monitor_range(const struct detailed_timing *timing, void *c)
a1d11d1e 6319{
c7943bb3
VS		 6320 struct detailed_mode_closure *closure = c;
6321 struct drm_display_info *info = &closure->connector->display_info;
6322 struct drm_monitor_range_info *monitor_range = &info->monitor_range;
a1d11d1e
MN		 6323 const struct detailed_non_pixel *data = &timing->data.other_data;
6324 const struct detailed_data_monitor_range *range = &data->data.range;
c7943bb3 6325 const struct edid *edid = closure->drm_edid->edid;
a1d11d1e 6326
e379814b 6327 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
a1d11d1e
MN		 6328 return;
6329
6330 /*
67d7469a
VS		 6331 * These limits are used to determine the VRR refresh
6332 * rate range. Only the "range limits only" variant
6333 * of the range descriptor seems to guarantee that
6334 * any and all timings are accepted by the sink, as
6335 * opposed to just timings conforming to the indicated
6336 * formula (GTF/GTF2/CVT). Thus other variants of the
6337 * range descriptor are not accepted here.
a1d11d1e
MN		 6338 */
6339 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG)
6340 return;
6341
6342 monitor_range->min_vfreq = range->min_vfreq;
6343 monitor_range->max_vfreq = range->max_vfreq;
c7943bb3
VS		 6344
6345 if (edid->revision >= 4) {
6346 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ)
6347 monitor_range->min_vfreq += 255;
6348 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MAX_VFREQ)
6349 monitor_range->max_vfreq += 255;
6350 }
a1d11d1e
MN		 6351}
6352
e42192b4
JN		 6353static void drm_get_monitor_range(struct drm_connector *connector,
6354 const struct drm_edid *drm_edid)
a1d11d1e 6355{
c7943bb3
VS		 6356 const struct drm_display_info *info = &connector->display_info;
6357 struct detailed_mode_closure closure = {
6358 .connector = connector,
6359 .drm_edid = drm_edid,
6360 };
a1d11d1e 6361
dd3abfe4 6362 if (drm_edid->edid->revision < 4)
ca2582c6
VS		 6363 return;
6364
6365 if (!(drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ))
a1d11d1e
MN		 6366 return;
6367
c7943bb3 6368 drm_for_each_detailed_block(drm_edid, get_monitor_range, &closure);
a1d11d1e 6369
e1e7bc48
JN		 6370 drm_dbg_kms(connector->dev,
6371 "[CONNECTOR:%d:%s] Supported Monitor Refresh rate range is %d Hz - %d Hz\n",
6372 connector->base.id, connector->name,
6373 info->monitor_range.min_vfreq, info->monitor_range.max_vfreq);
a1d11d1e
MN		 6374}
6375
18a9cbbe
JN		 6376static void drm_parse_vesa_mso_data(struct drm_connector *connector,
6377 const struct displayid_block *block)
6378{
6379 struct displayid_vesa_vendor_specific_block *vesa =
6380 (struct displayid_vesa_vendor_specific_block *)block;
6381 struct drm_display_info *info = &connector->display_info;
6382
6383 if (block->num_bytes < 3) {
66d17ecd
JN		 6384 drm_dbg_kms(connector->dev,
6385 "[CONNECTOR:%d:%s] Unexpected vendor block size %u\n",
6386 connector->base.id, connector->name, block->num_bytes);
18a9cbbe
JN		 6387 return;
6388 }
6389
6390 if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI)
6391 return;
6392
6393 if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
66d17ecd
JN		 6394 drm_dbg_kms(connector->dev,
6395 "[CONNECTOR:%d:%s] Unexpected VESA vendor block size\n",
6396 connector->base.id, connector->name);
18a9cbbe
JN		 6397 return;
6398 }
6399
6400 switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
6401 default:
66d17ecd
JN		 6402 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved MSO mode value\n",
6403 connector->base.id, connector->name);
18a9cbbe
JN		 6404 fallthrough;
6405 case 0:
6406 info->mso_stream_count = 0;
6407 break;
6408 case 1:
6409 info->mso_stream_count = 2; /* 2 or 4 links */
6410 break;
6411 case 2:
6412 info->mso_stream_count = 4; /* 4 links */
6413 break;
6414 }
6415
6416 if (!info->mso_stream_count) {
6417 info->mso_pixel_overlap = 0;
6418 return;
6419 }
6420
6421 info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
6422 if (info->mso_pixel_overlap > 8) {
66d17ecd
JN		 6423 drm_dbg_kms(connector->dev,
6424 "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n",
6425 connector->base.id, connector->name,
18a9cbbe
JN		 6426 info->mso_pixel_overlap);
6427 info->mso_pixel_overlap = 8;
6428 }
6429
66d17ecd
JN		 6430 drm_dbg_kms(connector->dev,
6431 "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n",
6432 connector->base.id, connector->name,
18a9cbbe
JN		 6433 info->mso_stream_count, info->mso_pixel_overlap);
6434}
6435
e42192b4
JN		 6436static void drm_update_mso(struct drm_connector *connector,
6437 const struct drm_edid *drm_edid)
18a9cbbe
JN		 6438{
6439 const struct displayid_block *block;
6440 struct displayid_iter iter;
6441
d9ba1b4c 6442 displayid_iter_edid_begin(drm_edid, &iter);
18a9cbbe
JN		 6443 displayid_iter_for_each(block, &iter) {
6444 if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC)
6445 drm_parse_vesa_mso_data(connector, block);
6446 }
6447 displayid_iter_end(&iter);
6448}
6449
170178fe
KP		 6450/* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
6451 * all of the values which would have been set from EDID
6452 */
02b16fbc 6453static void drm_reset_display_info(struct drm_connector *connector)
170178fe
KP		 6454{
6455 struct drm_display_info *info = &connector->display_info;
6456
6457 info->width_mm = 0;
6458 info->height_mm = 0;
6459
6460 info->bpc = 0;
6461 info->color_formats = 0;
6462 info->cea_rev = 0;
6463 info->max_tmds_clock = 0;
6464 info->dvi_dual = false;
a92d083d 6465 info->is_hdmi = false;
0374ffa5 6466 info->has_audio = false;
170178fe 6467 info->has_hdmi_infoframe = false;
1581b2df 6468 info->rgb_quant_range_selectable = false;
1f6b8eef 6469 memset(&info->hdmi, 0, sizeof(info->hdmi));
170178fe 6470
70c0b80d
MR		 6471 info->edid_hdmi_rgb444_dc_modes = 0;
6472 info->edid_hdmi_ycbcr444_dc_modes = 0;
6473
170178fe 6474 info->non_desktop = 0;
a1d11d1e 6475 memset(&info->monitor_range, 0, sizeof(info->monitor_range));
82068ede 6476 memset(&info->luminance_range, 0, sizeof(info->luminance_range));
18a9cbbe
JN		 6477
6478 info->mso_stream_count = 0;
6479 info->mso_pixel_overlap = 0;
aa193f7e 6480 info->max_dsc_bpp = 0;
c3292ab5
JN		 6481
6482 kfree(info->vics);
6483 info->vics = NULL;
6484 info->vics_len = 0;
783dedc5
JN		 6485
6486 info->quirks = 0;
82b599ec
JN		 6487
6488 info->source_physical_address = CEC_PHYS_ADDR_INVALID;
170178fe 6489}
170178fe 6490
217a8c63
JN		 6491static void update_displayid_info(struct drm_connector *connector,
6492 const struct drm_edid *drm_edid)
6493{
6494 struct drm_display_info *info = &connector->display_info;
6495 const struct displayid_block *block;
6496 struct displayid_iter iter;
6497
6498 displayid_iter_edid_begin(drm_edid, &iter);
6499 displayid_iter_for_each(block, &iter) {
6500 if (displayid_version(&iter) == DISPLAY_ID_STRUCTURE_VER_20 &&
6501 (displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_VR ||
6502 displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_AR))
6503 info->non_desktop = true;
6504
6505 /*
6506 * We're only interested in the base section here, no need to
6507 * iterate further.
6508 */
6509 break;
6510 }
6511 displayid_iter_end(&iter);
6512}
6513
783dedc5
JN		 6514static void update_display_info(struct drm_connector *connector,
6515 const struct drm_edid *drm_edid)
3b11228b 6516{
1826750f 6517 struct drm_display_info *info = &connector->display_info;
45ea02d1 6518 const struct edid *edid;
ebec9a7b 6519
1f6b8eef 6520 drm_reset_display_info(connector);
45ea02d1
JN		 6521 clear_eld(connector);
6522
6523 if (!drm_edid)
6524 return;
6525
6526 edid = drm_edid->edid;
1f6b8eef 6527
783dedc5
JN		 6528 info->quirks = edid_get_quirks(drm_edid);
6529
3b11228b
JB		 6530 info->width_mm = edid->width_cm * 10;
6531 info->height_mm = edid->height_cm * 10;
6532
e42192b4 6533 drm_get_monitor_range(connector, drm_edid);
a1d11d1e 6534
a988bc72 6535 if (edid->revision < 3)
ce99534e 6536 goto out;
3b11228b 6537
7218779e 6538 if (!drm_edid_is_digital(drm_edid))
ce99534e 6539 goto out;
3b11228b 6540
ecbd4912 6541 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
e42192b4 6542 drm_parse_cea_ext(connector, drm_edid);
d0c94692 6543
217a8c63
JN		 6544 update_displayid_info(connector, drm_edid);
6545
210a021d
MK		 6546 /*
6547 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
6548 *
6549 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
6550 * tells us to assume 8 bpc color depth if the EDID doesn't have
6551 * extensions which tell otherwise.
6552 */
3bde449f
VS		 6553 if (info->bpc == 0 && edid->revision == 3 &&
6554 edid->input & DRM_EDID_DIGITAL_DFP_1_X) {
210a021d 6555 info->bpc = 8;
e1e7bc48
JN		 6556 drm_dbg_kms(connector->dev,
6557 "[CONNECTOR:%d:%s] Assigning DFP sink color depth as %d bpc.\n",
6558 connector->base.id, connector->name, info->bpc);
210a021d
MK		 6559 }
6560
a988bc72
LPC		 6561 /* Only defined for 1.4 with digital displays */
6562 if (edid->revision < 4)
ce99534e 6563 goto out;
a988bc72 6564
3b11228b
JB		 6565 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
6566 case DRM_EDID_DIGITAL_DEPTH_6:
6567 info->bpc = 6;
6568 break;
6569 case DRM_EDID_DIGITAL_DEPTH_8:
6570 info->bpc = 8;
6571 break;
6572 case DRM_EDID_DIGITAL_DEPTH_10:
6573 info->bpc = 10;
6574 break;
6575 case DRM_EDID_DIGITAL_DEPTH_12:
6576 info->bpc = 12;
6577 break;
6578 case DRM_EDID_DIGITAL_DEPTH_14:
6579 info->bpc = 14;
6580 break;
6581 case DRM_EDID_DIGITAL_DEPTH_16:
6582 info->bpc = 16;
6583 break;
6584 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
6585 default:
6586 info->bpc = 0;
6587 break;
6588 }
da05a5a7 6589
e1e7bc48
JN		 6590 drm_dbg_kms(connector->dev,
6591 "[CONNECTOR:%d:%s] Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
6592 connector->base.id, connector->name, info->bpc);
d0c94692 6593
ee58808d 6594 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
c03d0b52 6595 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
ee58808d 6596 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
c03d0b52 6597 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
18a9cbbe 6598
e42192b4 6599 drm_update_mso(connector, drm_edid);
18a9cbbe 6600
ce99534e 6601out:
783dedc5 6602 if (info->quirks & EDID_QUIRK_NON_DESKTOP) {
66d17ecd
JN		 6603 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Non-desktop display%s\n",
6604 connector->base.id, connector->name,
ce99534e
JN		 6605 info->non_desktop ? " (redundant quirk)" : "");
6606 info->non_desktop = true;
6607 }
6608
783dedc5 6609 if (info->quirks & EDID_QUIRK_CAP_DSC_15BPP)
aa193f7e 6610 info->max_dsc_bpp = 15;
45ea02d1 6611
43bde505
JN		 6612 if (info->quirks & EDID_QUIRK_FORCE_6BPC)
6613 info->bpc = 6;
6614
6615 if (info->quirks & EDID_QUIRK_FORCE_8BPC)
6616 info->bpc = 8;
6617
6618 if (info->quirks & EDID_QUIRK_FORCE_10BPC)
6619 info->bpc = 10;
6620
6621 if (info->quirks & EDID_QUIRK_FORCE_12BPC)
6622 info->bpc = 12;
6623
45ea02d1
JN		 6624 /* Depends on info->cea_rev set by drm_parse_cea_ext() above */
6625 drm_edid_to_eld(connector, drm_edid);
3b11228b
JB		 6626}
6627
a39ed680 6628static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
80ecb5d7
YB		 6629 struct displayid_detailed_timings_1 *timings,
6630 bool type_7)
a39ed680
DA		 6631{
6632 struct drm_display_mode *mode;
6633 unsigned pixel_clock = (timings->pixel_clock[0] |
6634 (timings->pixel_clock[1] << 8) |
6292b8ef 6635 (timings->pixel_clock[2] << 16)) + 1;
a39ed680
DA		 6636 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
6637 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
6638 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
6639 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
6640 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
6641 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
6642 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
6643 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
6644 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
6645 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
948de842 6646
a39ed680
DA		 6647 mode = drm_mode_create(dev);
6648 if (!mode)
6649 return NULL;
6650
80ecb5d7
YB		 6651 /* resolution is kHz for type VII, and 10 kHz for type I */
6652 mode->clock = type_7 ? pixel_clock : pixel_clock * 10;
a39ed680
DA		 6653 mode->hdisplay = hactive;
6654 mode->hsync_start = mode->hdisplay + hsync;
6655 mode->hsync_end = mode->hsync_start + hsync_width;
6656 mode->htotal = mode->hdisplay + hblank;
6657
6658 mode->vdisplay = vactive;
6659 mode->vsync_start = mode->vdisplay + vsync;
6660 mode->vsync_end = mode->vsync_start + vsync_width;
6661 mode->vtotal = mode->vdisplay + vblank;
6662
6663 mode->flags = 0;
6664 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
6665 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
6666 mode->type = DRM_MODE_TYPE_DRIVER;
6667
6668 if (timings->flags & 0x80)
6669 mode->type |= DRM_MODE_TYPE_PREFERRED;
a39ed680
DA		 6670 drm_mode_set_name(mode);
6671
6672 return mode;
6673}
6674
6675static int add_displayid_detailed_1_modes(struct drm_connector *connector,
43d16d84 6676 const struct displayid_block *block)
a39ed680
DA		 6677{
6678 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
6679 int i;
6680 int num_timings;
6681 struct drm_display_mode *newmode;
6682 int num_modes = 0;
80ecb5d7 6683 bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING;
a39ed680
DA		 6684 /* blocks must be multiple of 20 bytes length */
6685 if (block->num_bytes % 20)
6686 return 0;
6687
6688 num_timings = block->num_bytes / 20;
6689 for (i = 0; i < num_timings; i++) {
6690 struct displayid_detailed_timings_1 *timings = &det->timings[i];
6691
80ecb5d7 6692 newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7);
a39ed680
DA		 6693 if (!newmode)
6694 continue;
6695
6696 drm_mode_probed_add(connector, newmode);
6697 num_modes++;
6698 }
6699 return num_modes;
6700}
6701
6702static int add_displayid_detailed_modes(struct drm_connector *connector,
40f71f5b 6703 const struct drm_edid *drm_edid)
a39ed680 6704{
43d16d84 6705 const struct displayid_block *block;
5ef88dc5 6706 struct displayid_iter iter;
a39ed680
DA		 6707 int num_modes = 0;
6708
d9ba1b4c 6709 displayid_iter_edid_begin(drm_edid, &iter);
5ef88dc5 6710 displayid_iter_for_each(block, &iter) {
80ecb5d7
YB		 6711 if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING ||
6712 block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING)
5ef88dc5 6713 num_modes += add_displayid_detailed_1_modes(connector, block);
a39ed680 6714 }
5ef88dc5 6715 displayid_iter_end(&iter);
7f261afd 6716
a39ed680
DA		 6717 return num_modes;
6718}
6719
e8b1f0d4
JN		 6720static int _drm_edid_connector_add_modes(struct drm_connector *connector,
6721 const struct drm_edid *drm_edid)
f453ba04 6722{
43bde505 6723 const struct drm_display_info *info = &connector->display_info;
f453ba04 6724 int num_modes = 0;
f453ba04 6725
45ea02d1
JN		 6726 if (!drm_edid)
6727 return 0;
58304630 6728
c867df70
AJ		 6729 /*
6730 * EDID spec says modes should be preferred in this order:
6731 * - preferred detailed mode
6732 * - other detailed modes from base block
6733 * - detailed modes from extension blocks
6734 * - CVT 3-byte code modes
6735 * - standard timing codes
6736 * - established timing codes
6737 * - modes inferred from GTF or CVT range information
6738 *
13931579 6739 * We get this pretty much right.
c867df70
AJ		 6740 *
6741 * XXX order for additional mode types in extension blocks?
6742 */
4959b693 6743 num_modes += add_detailed_modes(connector, drm_edid);
40f71f5b
JN		 6744 num_modes += add_cvt_modes(connector, drm_edid);
6745 num_modes += add_standard_modes(connector, drm_edid);
6746 num_modes += add_established_modes(connector, drm_edid);
6747 num_modes += add_cea_modes(connector, drm_edid);
6748 num_modes += add_alternate_cea_modes(connector, drm_edid);
6749 num_modes += add_displayid_detailed_modes(connector, drm_edid);
afd4429e 6750 if (drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ)
40f71f5b 6751 num_modes += add_inferred_modes(connector, drm_edid);
f453ba04 6752
783dedc5 6753 if (info->quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
4959b693 6754 edid_fixup_preferred(connector);
f453ba04 6755
f453ba04
DA		 6756 return num_modes;
6757}
f40ab034 6758
a819451e
JN		 6759static void _drm_update_tile_info(struct drm_connector *connector,
6760 const struct drm_edid *drm_edid);
02b16fbc 6761
b71c0aaa 6762static int _drm_edid_connector_property_update(struct drm_connector *connector,
a819451e 6763 const struct drm_edid *drm_edid)
02b16fbc
JN		 6764{
6765 struct drm_device *dev = connector->dev;
02b16fbc 6766 int ret;
02b16fbc 6767
02b16fbc 6768 if (connector->edid_blob_ptr) {
a819451e
JN		 6769 const struct edid *old_edid = connector->edid_blob_ptr->data;
6770
02b16fbc 6771 if (old_edid) {
a819451e 6772 if (!drm_edid_are_equal(drm_edid ? drm_edid->edid : NULL, old_edid)) {
f999b37e
JN		 6773 connector->epoch_counter++;
6774 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID changed, epoch counter %llu\n",
6775 connector->base.id, connector->name,
6776 connector->epoch_counter);
02b16fbc
JN		 6777 }
6778 }
6779 }
6780
02b16fbc
JN		 6781 ret = drm_property_replace_global_blob(dev,
6782 &connector->edid_blob_ptr,
a819451e
JN		 6783 drm_edid ? drm_edid->size : 0,
6784 drm_edid ? drm_edid->edid : NULL,
02b16fbc
JN		 6785 &connector->base,
6786 dev->mode_config.edid_property);
f999b37e
JN		 6787 if (ret) {
6788 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID property update failed (%d)\n",
6789 connector->base.id, connector->name, ret);
6790 goto out;
6791 }
6792
6793 ret = drm_object_property_set_value(&connector->base,
6794 dev->mode_config.non_desktop_property,
6795 connector->display_info.non_desktop);
6796 if (ret) {
6797 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Non-desktop property update failed (%d)\n",
6798 connector->base.id, connector->name, ret);
6799 goto out;
6800 }
6801
6802 ret = drm_connector_set_tile_property(connector);
6803 if (ret) {
6804 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Tile property update failed (%d)\n",
6805 connector->base.id, connector->name, ret);
6806 goto out;
6807 }
6808
6809out:
6810 return ret;
02b16fbc 6811}
a819451e 6812
b71c0aaa
JN		 6813/**
6814 * drm_edid_connector_update - Update connector information from EDID
6815 * @connector: Connector
6816 * @drm_edid: EDID
6817 *
c533b516
JN		 6818 * Update the connector display info, ELD, HDR metadata, relevant properties,
6819 * etc. from the passed in EDID.
b71c0aaa
JN		 6820 *
6821 * If EDID is NULL, reset the information.
6822 *
c533b516
JN		 6823 * Must be called before calling drm_edid_connector_add_modes().
6824 *
6825 * Return: 0 on success, negative error on errors.
b71c0aaa
JN		 6826 */
6827int drm_edid_connector_update(struct drm_connector *connector,
6828 const struct drm_edid *drm_edid)
6829{
c533b516
JN		 6830 update_display_info(connector, drm_edid);
6831
6832 _drm_update_tile_info(connector, drm_edid);
6833
6834 return _drm_edid_connector_property_update(connector, drm_edid);
6835}
6836EXPORT_SYMBOL(drm_edid_connector_update);
6837
6838/**
6839 * drm_edid_connector_add_modes - Update probed modes from the EDID property
6840 * @connector: Connector
6841 *
6842 * Add the modes from the previously updated EDID property to the connector
6843 * probed modes list.
6844 *
6845 * drm_edid_connector_update() must have been called before this to update the
6846 * EDID property.
6847 *
6848 * Return: The number of modes added, or 0 if we couldn't find any.
6849 */
6850int drm_edid_connector_add_modes(struct drm_connector *connector)
6851{
6852 const struct drm_edid *drm_edid = NULL;
b71c0aaa
JN		 6853 int count;
6854
c533b516
JN		 6855 if (connector->edid_blob_ptr)
6856 drm_edid = drm_edid_alloc(connector->edid_blob_ptr->data,
6857 connector->edid_blob_ptr->length);
e8b1f0d4
JN		 6858
6859 count = _drm_edid_connector_add_modes(connector, drm_edid);
b71c0aaa 6860
c533b516 6861 drm_edid_free(drm_edid);
b71c0aaa
JN		 6862
6863 return count;
6864}
c533b516 6865EXPORT_SYMBOL(drm_edid_connector_add_modes);
b71c0aaa 6866
a819451e
JN		 6867/**
6868 * drm_connector_update_edid_property - update the edid property of a connector
6869 * @connector: drm connector
6870 * @edid: new value of the edid property
6871 *
6872 * This function creates a new blob modeset object and assigns its id to the
6873 * connector's edid property.
6874 * Since we also parse tile information from EDID's displayID block, we also
6875 * set the connector's tile property here. See drm_connector_set_tile_property()
6876 * for more details.
6877 *
b71c0aaa
JN		 6878 * This function is deprecated. Use drm_edid_connector_update() instead.
6879 *
a819451e
JN		 6880 * Returns:
6881 * Zero on success, negative errno on failure.
6882 */
6883int drm_connector_update_edid_property(struct drm_connector *connector,
6884 const struct edid *edid)
6885{
6886 struct drm_edid drm_edid;
6887
b494d628 6888 return drm_edid_connector_update(connector, drm_edid_legacy_init(&drm_edid, edid));
a819451e 6889}
02b16fbc
JN		 6890EXPORT_SYMBOL(drm_connector_update_edid_property);
6891
f40ab034
JN		 6892/**
6893 * drm_add_edid_modes - add modes from EDID data, if available
6894 * @connector: connector we're probing
6895 * @edid: EDID data
6896 *
6897 * Add the specified modes to the connector's mode list. Also fills out the
6898 * &drm_display_info structure and ELD in @connector with any information which
6899 * can be derived from the edid.
6900 *
c533b516 6901 * This function is deprecated. Use drm_edid_connector_add_modes() instead.
b71c0aaa 6902 *
f40ab034
JN		 6903 * Return: The number of modes added or 0 if we couldn't find any.
6904 */
6905int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
6906{
e8b1f0d4
JN		 6907 struct drm_edid _drm_edid;
6908 const struct drm_edid *drm_edid;
22a27e05 6909
f40ab034 6910 if (edid && !drm_edid_is_valid(edid)) {
66d17ecd
JN		 6911 drm_warn(connector->dev, "[CONNECTOR:%d:%s] EDID invalid.\n",
6912 connector->base.id, connector->name);
f40ab034
JN		 6913 edid = NULL;
6914 }
6915
e8b1f0d4
JN		 6916 drm_edid = drm_edid_legacy_init(&_drm_edid, edid);
6917
6918 update_display_info(connector, drm_edid);
6919
6920 return _drm_edid_connector_add_modes(connector, drm_edid);
f40ab034 6921}
f453ba04 6922EXPORT_SYMBOL(drm_add_edid_modes);
f0fda0a4
ZY		 6923
6924/**
6925 * drm_add_modes_noedid - add modes for the connectors without EDID
6926 * @connector: connector we're probing
6927 * @hdisplay: the horizontal display limit
6928 * @vdisplay: the vertical display limit
6929 *
6930 * Add the specified modes to the connector's mode list. Only when the
6931 * hdisplay/vdisplay is not beyond the given limit, it will be added.
6932 *
db6cf833 6933 * Return: The number of modes added or 0 if we couldn't find any.
f0fda0a4
ZY		 6934 */
6935int drm_add_modes_noedid(struct drm_connector *connector,
6936 int hdisplay, int vdisplay)
6937{
6938 int i, count, num_modes = 0;
b1f559ec 6939 struct drm_display_mode *mode;
f0fda0a4
ZY		 6940 struct drm_device *dev = connector->dev;
6941
fbb40b28 6942 count = ARRAY_SIZE(drm_dmt_modes);
f0fda0a4
ZY		 6943 if (hdisplay < 0)
6944 hdisplay = 0;
6945 if (vdisplay < 0)
6946 vdisplay = 0;
6947
6948 for (i = 0; i < count; i++) {
b1f559ec 6949 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
948de842 6950
f0fda0a4
ZY		 6951 if (hdisplay && vdisplay) {
6952 /*
6953 * Only when two are valid, they will be used to check
6954 * whether the mode should be added to the mode list of
6955 * the connector.
6956 */
6957 if (ptr->hdisplay > hdisplay ||
6958 ptr->vdisplay > vdisplay)
6959 continue;
6960 }
f985dedb
AJ		 6961 if (drm_mode_vrefresh(ptr) > 61)
6962 continue;
f0fda0a4
ZY		 6963 mode = drm_mode_duplicate(dev, ptr);
6964 if (mode) {
6965 drm_mode_probed_add(connector, mode);
6966 num_modes++;
6967 }
6968 }
6969 return num_modes;
6970}
6971EXPORT_SYMBOL(drm_add_modes_noedid);
10a85120 6972
db6cf833
TR		 6973/**
6974 * drm_set_preferred_mode - Sets the preferred mode of a connector
6975 * @connector: connector whose mode list should be processed
6976 * @hpref: horizontal resolution of preferred mode
6977 * @vpref: vertical resolution of preferred mode
6978 *
6979 * Marks a mode as preferred if it matches the resolution specified by @hpref
6980 * and @vpref.
6981 */
3cf70daf
GH		 6982void drm_set_preferred_mode(struct drm_connector *connector,
6983 int hpref, int vpref)
6984{
6985 struct drm_display_mode *mode;
6986
6987 list_for_each_entry(mode, &connector->probed_modes, head) {
db6cf833 6988 if (mode->hdisplay == hpref &&
9d3de138 6989 mode->vdisplay == vpref)
3cf70daf
GH		 6990 mode->type |= DRM_MODE_TYPE_PREFERRED;
6991 }
6992}
6993EXPORT_SYMBOL(drm_set_preferred_mode);
6994
192a3aa0 6995static bool is_hdmi2_sink(const struct drm_connector *connector)
13d0add3
VS		 6996{
6997 /*
6998 * FIXME: sil-sii8620 doesn't have a connector around when
6999 * we need one, so we have to be prepared for a NULL connector.
7000 */
7001 if (!connector)
7002 return true;
7003
7004 return connector->display_info.hdmi.scdc.supported ||
c03d0b52 7005 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR420;
13d0add3
VS		 7006}
7007
192a3aa0 7008static u8 drm_mode_hdmi_vic(const struct drm_connector *connector,
949561eb
VS		 7009 const struct drm_display_mode *mode)
7010{
7011 bool has_hdmi_infoframe = connector ?
7012 connector->display_info.has_hdmi_infoframe : false;
7013
7014 if (!has_hdmi_infoframe)
7015 return 0;
7016
7017 /* No HDMI VIC when signalling 3D video format */
7018 if (mode->flags & DRM_MODE_FLAG_3D_MASK)
7019 return 0;
7020
7021 return drm_match_hdmi_mode(mode);
7022}
7023
192a3aa0 7024static u8 drm_mode_cea_vic(const struct drm_connector *connector,
cfd6f8c3
VS		 7025 const struct drm_display_mode *mode)
7026{
cfd6f8c3
VS		 7027 /*
7028 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
7029 * we should send its VIC in vendor infoframes, else send the
7030 * VIC in AVI infoframes. Lets check if this mode is present in
7031 * HDMI 1.4b 4K modes
7032 */
949561eb 7033 if (drm_mode_hdmi_vic(connector, mode))
cfd6f8c3
VS		 7034 return 0;
7035
1cbc1f0d
JN		 7036 return drm_match_cea_mode(mode);
7037}
cfd6f8c3 7038
1cbc1f0d
JN		 7039/*
7040 * Avoid sending VICs defined in HDMI 2.0 in AVI infoframes to sinks that
7041 * conform to HDMI 1.4.
7042 *
7043 * HDMI 1.4 (CTA-861-D) VIC range: [1..64]
7044 * HDMI 2.0 (CTA-861-F) VIC range: [1..107]
4ed29f39
JN		 7045 *
7046 * If the sink lists the VIC in CTA VDB, assume it's fine, regardless of HDMI
7047 * version.
1cbc1f0d
JN		 7048 */
7049static u8 vic_for_avi_infoframe(const struct drm_connector *connector, u8 vic)
7050{
4ed29f39
JN		 7051 if (!is_hdmi2_sink(connector) && vic > 64 &&
7052 !cta_vdb_has_vic(connector, vic))
cfd6f8c3
VS		 7053 return 0;
7054
7055 return vic;
7056}
7057
10a85120
TR		 7058/**
7059 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
7060 * data from a DRM display mode
7061 * @frame: HDMI AVI infoframe
13d0add3 7062 * @connector: the connector
10a85120
TR		 7063 * @mode: DRM display mode
7064 *
db6cf833 7065 * Return: 0 on success or a negative error code on failure.
10a85120
TR		 7066 */
7067int
7068drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
192a3aa0 7069 const struct drm_connector *connector,
13d0add3 7070 const struct drm_display_mode *mode)
10a85120 7071{
a9c266c2 7072 enum hdmi_picture_aspect picture_aspect;
d2b43473 7073 u8 vic, hdmi_vic;
10a85120
TR		 7074
7075 if (!frame || !mode)
7076 return -EINVAL;
7077
5ee0caf1 7078 hdmi_avi_infoframe_init(frame);
10a85120 7079
bf02db99
DL		 7080 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
7081 frame->pixel_repeat = 1;
7082
d2b43473
WL		 7083 vic = drm_mode_cea_vic(connector, mode);
7084 hdmi_vic = drm_mode_hdmi_vic(connector, mode);
0c1f528c 7085
10a85120 7086 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
0967e6a5 7087
50525c33
SL		 7088 /*
7089 * As some drivers don't support atomic, we can't use connector state.
7090 * So just initialize the frame with default values, just the same way
7091 * as it's done with other properties here.
7092 */
7093 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
7094 frame->itc = 0;
7095
69ab6d35
VK		 7096 /*
7097 * Populate picture aspect ratio from either
d2b43473 7098 * user input (if specified) or from the CEA/HDMI mode lists.
69ab6d35 7099 */
a9c266c2 7100 picture_aspect = mode->picture_aspect_ratio;
d2b43473
WL		 7101 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) {
7102 if (vic)
7103 picture_aspect = drm_get_cea_aspect_ratio(vic);
7104 else if (hdmi_vic)
7105 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic);
7106 }
0967e6a5 7107
a9c266c2
VS		 7108 /*
7109 * The infoframe can't convey anything but none, 4:3
7110 * and 16:9, so if the user has asked for anything else
7111 * we can only satisfy it by specifying the right VIC.
7112 */
7113 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
d2b43473
WL		 7114 if (vic) {
7115 if (picture_aspect != drm_get_cea_aspect_ratio(vic))
7116 return -EINVAL;
7117 } else if (hdmi_vic) {
7118 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic))
7119 return -EINVAL;
7120 } else {
a9c266c2 7121 return -EINVAL;
d2b43473
WL		 7122 }
7123
a9c266c2
VS		 7124 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
7125 }
7126
1cbc1f0d 7127 frame->video_code = vic_for_avi_infoframe(connector, vic);
a9c266c2 7128 frame->picture_aspect = picture_aspect;
10a85120 7129 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
24d01805 7130 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
10a85120
TR		 7131
7132 return 0;
7133}
7134EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
83dd0008 7135
a2ce26f8
VS		 7136/**
7137 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
7138 * quantization range information
7139 * @frame: HDMI AVI infoframe
13d0add3 7140 * @connector: the connector
779c4c28 7141 * @mode: DRM display mode
a2ce26f8 7142 * @rgb_quant_range: RGB quantization range (Q)
a2ce26f8
VS		 7143 */
7144void
7145drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
192a3aa0 7146 const struct drm_connector *connector,
779c4c28 7147 const struct drm_display_mode *mode,
1581b2df 7148 enum hdmi_quantization_range rgb_quant_range)
a2ce26f8 7149{
1581b2df
VS		 7150 const struct drm_display_info *info = &connector->display_info;
7151
a2ce26f8
VS		 7152 /*
7153 * CEA-861:
7154 * "A Source shall not send a non-zero Q value that does not correspond
7155 * to the default RGB Quantization Range for the transmitted Picture
7156 * unless the Sink indicates support for the Q bit in a Video
7157 * Capabilities Data Block."
779c4c28
VS		 7158 *
7159 * HDMI 2.0 recommends sending non-zero Q when it does match the
7160 * default RGB quantization range for the mode, even when QS=0.
a2ce26f8 7161 */
1581b2df 7162 if (info->rgb_quant_range_selectable ||
779c4c28 7163 rgb_quant_range == drm_default_rgb_quant_range(mode))
a2ce26f8
VS		 7164 frame->quantization_range = rgb_quant_range;
7165 else
7166 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
fcc8a22c
VS		 7167
7168 /*
7169 * CEA-861-F:
7170 * "When transmitting any RGB colorimetry, the Source should set the
7171 * YQ-field to match the RGB Quantization Range being transmitted
7172 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
7173 * set YQ=1) and the Sink shall ignore the YQ-field."
9271c0ca
VS		 7174 *
7175 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
7176 * by non-zero YQ when receiving RGB. There doesn't seem to be any
7177 * good way to tell which version of CEA-861 the sink supports, so
7178 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
96c92551 7179 * on CEA-861-F.
fcc8a22c 7180 */
13d0add3 7181 if (!is_hdmi2_sink(connector) ||
9271c0ca 7182 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
fcc8a22c
VS		 7183 frame->ycc_quantization_range =
7184 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
7185 else
7186 frame->ycc_quantization_range =
7187 HDMI_YCC_QUANTIZATION_RANGE_FULL;
a2ce26f8
VS		 7188}
7189EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
7190
4eed4a0a
DL		 7191static enum hdmi_3d_structure
7192s3d_structure_from_display_mode(const struct drm_display_mode *mode)
7193{
7194 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
7195
7196 switch (layout) {
7197 case DRM_MODE_FLAG_3D_FRAME_PACKING:
7198 return HDMI_3D_STRUCTURE_FRAME_PACKING;
7199 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
7200 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
7201 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
7202 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
7203 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
7204 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
7205 case DRM_MODE_FLAG_3D_L_DEPTH:
7206 return HDMI_3D_STRUCTURE_L_DEPTH;
7207 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
7208 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
7209 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
7210 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
7211 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
7212 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
7213 default:
7214 return HDMI_3D_STRUCTURE_INVALID;
7215 }
7216}
7217
83dd0008
LD		 7218/**
7219 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
7220 * data from a DRM display mode
7221 * @frame: HDMI vendor infoframe
f1781e9b 7222 * @connector: the connector
83dd0008
LD		 7223 * @mode: DRM display mode
7224 *
7225 * Note that there's is a need to send HDMI vendor infoframes only when using a
7226 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
7227 * function will return -EINVAL, error that can be safely ignored.
7228 *
db6cf833 7229 * Return: 0 on success or a negative error code on failure.
83dd0008
LD		 7230 */
7231int
7232drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
192a3aa0 7233 const struct drm_connector *connector,
83dd0008
LD		 7234 const struct drm_display_mode *mode)
7235{
f1781e9b
VS		 7236 /*
7237 * FIXME: sil-sii8620 doesn't have a connector around when
7238 * we need one, so we have to be prepared for a NULL connector.
7239 */
7240 bool has_hdmi_infoframe = connector ?
7241 connector->display_info.has_hdmi_infoframe : false;
83dd0008 7242 int err;
83dd0008
LD		 7243
7244 if (!frame || !mode)
7245 return -EINVAL;
7246
f1781e9b
VS		 7247 if (!has_hdmi_infoframe)
7248 return -EINVAL;
7249
949561eb
VS		 7250 err = hdmi_vendor_infoframe_init(frame);
7251 if (err < 0)
7252 return err;
4eed4a0a 7253
f1781e9b
VS		 7254 /*
7255 * Even if it's not absolutely necessary to send the infoframe
7256 * (ie.vic==0 and s3d_struct==0) we will still send it if we
7257 * know that the sink can handle it. This is based on a
7258 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
0ae865ef 7259 * have trouble realizing that they should switch from 3D to 2D
f1781e9b
VS		 7260 * mode if the source simply stops sending the infoframe when
7261 * it wants to switch from 3D to 2D.
7262 */
949561eb 7263 frame->vic = drm_mode_hdmi_vic(connector, mode);
f1781e9b 7264 frame->s3d_struct = s3d_structure_from_display_mode(mode);
83dd0008
LD		 7265
7266 return 0;
7267}
7268EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
40d9b043 7269
7f261afd
VS		 7270static void drm_parse_tiled_block(struct drm_connector *connector,
7271 const struct displayid_block *block)
5e546cd5 7272{
092c367a 7273 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
5e546cd5
DA		 7274 u16 w, h;
7275 u8 tile_v_loc, tile_h_loc;
7276 u8 num_v_tile, num_h_tile;
7277 struct drm_tile_group *tg;
7278
7279 w = tile->tile_size[0] | tile->tile_size[1] << 8;
7280 h = tile->tile_size[2] | tile->tile_size[3] << 8;
7281
7282 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
7283 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
7284 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
7285 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
7286
7287 connector->has_tile = true;
7288 if (tile->tile_cap & 0x80)
7289 connector->tile_is_single_monitor = true;
7290
7291 connector->num_h_tile = num_h_tile + 1;
7292 connector->num_v_tile = num_v_tile + 1;
7293 connector->tile_h_loc = tile_h_loc;
7294 connector->tile_v_loc = tile_v_loc;
7295 connector->tile_h_size = w + 1;
7296 connector->tile_v_size = h + 1;
7297
e1e7bc48
JN		 7298 drm_dbg_kms(connector->dev,
7299 "[CONNECTOR:%d:%s] tile cap 0x%x, size %dx%d, num tiles %dx%d, location %dx%d, vend %c%c%c",
7300 connector->base.id, connector->name,
7301 tile->tile_cap,
7302 connector->tile_h_size, connector->tile_v_size,
7303 connector->num_h_tile, connector->num_v_tile,
7304 connector->tile_h_loc, connector->tile_v_loc,
7305 tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
5e546cd5
DA		 7306
7307 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
392f9fcb 7308 if (!tg)
5e546cd5 7309 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
5e546cd5 7310 if (!tg)
7f261afd 7311 return;
5e546cd5
DA		 7312
7313 if (connector->tile_group != tg) {
7314 /* if we haven't got a pointer,
7315 take the reference, drop ref to old tile group */
392f9fcb 7316 if (connector->tile_group)
5e546cd5 7317 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5e546cd5 7318 connector->tile_group = tg;
392f9fcb 7319 } else {
5e546cd5
DA		 7320 /* if same tile group, then release the ref we just took. */
7321 drm_mode_put_tile_group(connector->dev, tg);
392f9fcb 7322 }
5e546cd5
DA		 7323}
7324
c5a486af
JN		 7325static bool displayid_is_tiled_block(const struct displayid_iter *iter,
7326 const struct displayid_block *block)
7327{
7328 return (displayid_version(iter) == DISPLAY_ID_STRUCTURE_VER_12 &&
7329 block->tag == DATA_BLOCK_TILED_DISPLAY) ||
7330 (displayid_version(iter) == DISPLAY_ID_STRUCTURE_VER_20 &&
7331 block->tag == DATA_BLOCK_2_TILED_DISPLAY_TOPOLOGY);
7332}
7333
c7b2dee4
JN		 7334static void _drm_update_tile_info(struct drm_connector *connector,
7335 const struct drm_edid *drm_edid)
40d9b043 7336{
bfd4e192
JN		 7337 const struct displayid_block *block;
7338 struct displayid_iter iter;
36881184 7339
40d9b043 7340 connector->has_tile = false;
7f261afd 7341
d9ba1b4c 7342 displayid_iter_edid_begin(drm_edid, &iter);
bfd4e192 7343 displayid_iter_for_each(block, &iter) {
c5a486af 7344 if (displayid_is_tiled_block(&iter, block))
bfd4e192 7345 drm_parse_tiled_block(connector, block);
40d9b043 7346 }
bfd4e192 7347 displayid_iter_end(&iter);
40d9b043 7348
7f261afd 7349 if (!connector->has_tile && connector->tile_group) {
40d9b043
DA		 7350 drm_mode_put_tile_group(connector->dev, connector->tile_group);
7351 connector->tile_group = NULL;
7352 }
40d9b043 7353}
7218779e
JN		 7354
7355/**
7356 * drm_edid_is_digital - is digital?
7357 * @drm_edid: The EDID
7358 *
7359 * Return true if input is digital.
7360 */
7361bool drm_edid_is_digital(const struct drm_edid *drm_edid)
7362{
7363 return drm_edid && drm_edid->edid &&
7364 drm_edid->edid->input & DRM_EDID_INPUT_DIGITAL;
7365}
7366EXPORT_SYMBOL(drm_edid_is_digital);
Linux 6.x block layer and io_uring tree(s)