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drm/edid: refactor _drm_edid_connector_update() and rename
[linux-2.6-block.git] / drivers / gpu / drm / drm_edid.c
CommitLineData
f453ba04
DA		 1/*
2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
61e57a8d 5 * Copyright 2010 Red Hat, Inc.
f453ba04
DA		 6 *
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
8 * FB layer.
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 */
9c79edec 30
18a9cbbe 31#include <linux/bitfield.h>
10a85120 32#include <linux/hdmi.h>
f453ba04 33#include <linux/i2c.h>
9c79edec 34#include <linux/kernel.h>
47819ba2 35#include <linux/module.h>
36b73b05 36#include <linux/pci.h>
9c79edec 37#include <linux/slab.h>
5cb8eaa2 38#include <linux/vga_switcheroo.h>
9c79edec
JN		 39
40#include <drm/drm_displayid.h>
41#include <drm/drm_drv.h>
760285e7 42#include <drm/drm_edid.h>
9338203c 43#include <drm/drm_encoder.h>
9c79edec 44#include <drm/drm_print.h>
f453ba04 45
969218fe
TI		 46#include "drm_crtc_internal.h"
47
37eab1fe
JN		 48static int oui(u8 first, u8 second, u8 third)
49{
50 return (first << 16) | (second << 8) | third;
51}
52
d1ff6409
AJ		 53#define EDID_EST_TIMINGS 16
54#define EDID_STD_TIMINGS 8
55#define EDID_DETAILED_TIMINGS 4
f453ba04
DA		 56
57/*
58 * EDID blocks out in the wild have a variety of bugs, try to collect
59 * them here (note that userspace may work around broken monitors first,
60 * but fixes should make their way here so that the kernel "just works"
61 * on as many displays as possible).
62 */
63
64/* First detailed mode wrong, use largest 60Hz mode */
65#define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
66/* Reported 135MHz pixel clock is too high, needs adjustment */
67#define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
68/* Prefer the largest mode at 75 Hz */
69#define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
70/* Detail timing is in cm not mm */
71#define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
72/* Detailed timing descriptors have bogus size values, so just take the
73 * maximum size and use that.
74 */
75#define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
f453ba04
DA		 76/* use +hsync +vsync for detailed mode */
77#define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
bc42aabc
AJ		 78/* Force reduced-blanking timings for detailed modes */
79#define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
49d45a31
RM		 80/* Force 8bpc */
81#define EDID_QUIRK_FORCE_8BPC (1 << 8)
bc5b9641
MK		 82/* Force 12bpc */
83#define EDID_QUIRK_FORCE_12BPC (1 << 9)
e10aec65
MK		 84/* Force 6bpc */
85#define EDID_QUIRK_FORCE_6BPC (1 << 10)
e345da82
MK		 86/* Force 10bpc */
87#define EDID_QUIRK_FORCE_10BPC (1 << 11)
66660d4c
DA		 88/* Non desktop display (i.e. HMD) */
89#define EDID_QUIRK_NON_DESKTOP (1 << 12)
aa193f7e
HM		 90/* Cap the DSC target bitrate to 15bpp */
91#define EDID_QUIRK_CAP_DSC_15BPP (1 << 13)
3c537889 92
2869f599
PZ		 93#define MICROSOFT_IEEE_OUI 0xca125c
94
13931579
AJ		 95struct detailed_mode_closure {
96 struct drm_connector *connector;
dd0f4470 97 const struct drm_edid *drm_edid;
13931579 98 bool preferred;
13931579
AJ		 99 int modes;
100};
f453ba04 101
5c61259e
ZY		 102#define LEVEL_DMT 0
103#define LEVEL_GTF 1
7a374350
AJ		 104#define LEVEL_GTF2 2
105#define LEVEL_CVT 3
5c61259e 106
7d1be0a0 107#define EDID_QUIRK(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _quirks) \
e8de4d55 108{ \
7d1be0a0
DA		 109 .panel_id = drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, \
110 product_id), \
e8de4d55
DA		 111 .quirks = _quirks \
112}
113
23c4cfbd 114static const struct edid_quirk {
e8de4d55 115 u32 panel_id;
f453ba04
DA		 116 u32 quirks;
117} edid_quirk_list[] = {
118 /* Acer AL1706 */
7d1be0a0 119 EDID_QUIRK('A', 'C', 'R', 44358, EDID_QUIRK_PREFER_LARGE_60),
f453ba04 120 /* Acer F51 */
7d1be0a0 121 EDID_QUIRK('A', 'P', 'I', 0x7602, EDID_QUIRK_PREFER_LARGE_60),
f453ba04 122
e10aec65 123 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
7d1be0a0 124 EDID_QUIRK('A', 'E', 'O', 0, EDID_QUIRK_FORCE_6BPC),
e10aec65 125
0711a43b 126 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
7d1be0a0 127 EDID_QUIRK('B', 'O', 'E', 0x78b, EDID_QUIRK_FORCE_6BPC),
0711a43b 128
06998a75 129 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
7d1be0a0 130 EDID_QUIRK('C', 'P', 'T', 0x17df, EDID_QUIRK_FORCE_6BPC),
06998a75 131
25da7504 132 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
7d1be0a0 133 EDID_QUIRK('S', 'D', 'C', 0x3652, EDID_QUIRK_FORCE_6BPC),
25da7504 134
922dceff 135 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
7d1be0a0 136 EDID_QUIRK('B', 'O', 'E', 0x0771, EDID_QUIRK_FORCE_6BPC),
922dceff 137
f453ba04 138 /* Belinea 10 15 55 */
7d1be0a0
DA		 139 EDID_QUIRK('M', 'A', 'X', 1516, EDID_QUIRK_PREFER_LARGE_60),
140 EDID_QUIRK('M', 'A', 'X', 0x77e, EDID_QUIRK_PREFER_LARGE_60),
f453ba04
DA		 141
142 /* Envision Peripherals, Inc. EN-7100e */
7d1be0a0 143 EDID_QUIRK('E', 'P', 'I', 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH),
ba1163de 144 /* Envision EN2028 */
7d1be0a0 145 EDID_QUIRK('E', 'P', 'I', 8232, EDID_QUIRK_PREFER_LARGE_60),
f453ba04
DA		 146
147 /* Funai Electronics PM36B */
7d1be0a0 148 EDID_QUIRK('F', 'C', 'M', 13600, EDID_QUIRK_PREFER_LARGE_75 |
e8de4d55 149 EDID_QUIRK_DETAILED_IN_CM),
f453ba04 150
aa193f7e
HM		 151 /* LG 27GP950 */
152 EDID_QUIRK('G', 'S', 'M', 0x5bbf, EDID_QUIRK_CAP_DSC_15BPP),
153
154 /* LG 27GN950 */
155 EDID_QUIRK('G', 'S', 'M', 0x5b9a, EDID_QUIRK_CAP_DSC_15BPP),
156
e345da82 157 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
7d1be0a0 158 EDID_QUIRK('L', 'G', 'D', 764, EDID_QUIRK_FORCE_10BPC),
e345da82 159
f453ba04 160 /* LG Philips LCD LP154W01-A5 */
7d1be0a0
DA		 161 EDID_QUIRK('L', 'P', 'L', 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
162 EDID_QUIRK('L', 'P', 'L', 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
f453ba04 163
f453ba04 164 /* Samsung SyncMaster 205BW. Note: irony */
7d1be0a0 165 EDID_QUIRK('S', 'A', 'M', 541, EDID_QUIRK_DETAILED_SYNC_PP),
f453ba04 166 /* Samsung SyncMaster 22[5-6]BW */
7d1be0a0
DA		 167 EDID_QUIRK('S', 'A', 'M', 596, EDID_QUIRK_PREFER_LARGE_60),
168 EDID_QUIRK('S', 'A', 'M', 638, EDID_QUIRK_PREFER_LARGE_60),
bc42aabc 169
bc5b9641 170 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
7d1be0a0 171 EDID_QUIRK('S', 'N', 'Y', 0x2541, EDID_QUIRK_FORCE_12BPC),
bc5b9641 172
bc42aabc 173 /* ViewSonic VA2026w */
7d1be0a0 174 EDID_QUIRK('V', 'S', 'C', 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING),
118bdbd8
AD		 175
176 /* Medion MD 30217 PG */
7d1be0a0 177 EDID_QUIRK('M', 'E', 'D', 0x7b8, EDID_QUIRK_PREFER_LARGE_75),
49d45a31 178
11bcf5f7 179 /* Lenovo G50 */
7d1be0a0 180 EDID_QUIRK('S', 'D', 'C', 18514, EDID_QUIRK_FORCE_6BPC),
11bcf5f7 181
49d45a31 182 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
7d1be0a0 183 EDID_QUIRK('S', 'E', 'C', 0xd033, EDID_QUIRK_FORCE_8BPC),
36fc5797
TV		 184
185 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
7d1be0a0 186 EDID_QUIRK('E', 'T', 'R', 13896, EDID_QUIRK_FORCE_8BPC),
acb1d8ee 187
30d62d44 188 /* Valve Index Headset */
7d1be0a0
DA		 189 EDID_QUIRK('V', 'L', 'V', 0x91a8, EDID_QUIRK_NON_DESKTOP),
190 EDID_QUIRK('V', 'L', 'V', 0x91b0, EDID_QUIRK_NON_DESKTOP),
191 EDID_QUIRK('V', 'L', 'V', 0x91b1, EDID_QUIRK_NON_DESKTOP),
192 EDID_QUIRK('V', 'L', 'V', 0x91b2, EDID_QUIRK_NON_DESKTOP),
193 EDID_QUIRK('V', 'L', 'V', 0x91b3, EDID_QUIRK_NON_DESKTOP),
194 EDID_QUIRK('V', 'L', 'V', 0x91b4, EDID_QUIRK_NON_DESKTOP),
195 EDID_QUIRK('V', 'L', 'V', 0x91b5, EDID_QUIRK_NON_DESKTOP),
196 EDID_QUIRK('V', 'L', 'V', 0x91b6, EDID_QUIRK_NON_DESKTOP),
197 EDID_QUIRK('V', 'L', 'V', 0x91b7, EDID_QUIRK_NON_DESKTOP),
198 EDID_QUIRK('V', 'L', 'V', 0x91b8, EDID_QUIRK_NON_DESKTOP),
199 EDID_QUIRK('V', 'L', 'V', 0x91b9, EDID_QUIRK_NON_DESKTOP),
200 EDID_QUIRK('V', 'L', 'V', 0x91ba, EDID_QUIRK_NON_DESKTOP),
201 EDID_QUIRK('V', 'L', 'V', 0x91bb, EDID_QUIRK_NON_DESKTOP),
202 EDID_QUIRK('V', 'L', 'V', 0x91bc, EDID_QUIRK_NON_DESKTOP),
203 EDID_QUIRK('V', 'L', 'V', 0x91bd, EDID_QUIRK_NON_DESKTOP),
204 EDID_QUIRK('V', 'L', 'V', 0x91be, EDID_QUIRK_NON_DESKTOP),
205 EDID_QUIRK('V', 'L', 'V', 0x91bf, EDID_QUIRK_NON_DESKTOP),
30d62d44 206
6931317c 207 /* HTC Vive and Vive Pro VR Headsets */
7d1be0a0
DA		 208 EDID_QUIRK('H', 'V', 'R', 0xaa01, EDID_QUIRK_NON_DESKTOP),
209 EDID_QUIRK('H', 'V', 'R', 0xaa02, EDID_QUIRK_NON_DESKTOP),
b3b12ea3 210
5a3f6108 211 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */
7d1be0a0
DA		 212 EDID_QUIRK('O', 'V', 'R', 0x0001, EDID_QUIRK_NON_DESKTOP),
213 EDID_QUIRK('O', 'V', 'R', 0x0003, EDID_QUIRK_NON_DESKTOP),
214 EDID_QUIRK('O', 'V', 'R', 0x0004, EDID_QUIRK_NON_DESKTOP),
215 EDID_QUIRK('O', 'V', 'R', 0x0012, EDID_QUIRK_NON_DESKTOP),
90eda8fc
PZ		 216
217 /* Windows Mixed Reality Headsets */
7d1be0a0 218 EDID_QUIRK('A', 'C', 'R', 0x7fce, EDID_QUIRK_NON_DESKTOP),
7d1be0a0 219 EDID_QUIRK('L', 'E', 'N', 0x0408, EDID_QUIRK_NON_DESKTOP),
7d1be0a0
DA		 220 EDID_QUIRK('F', 'U', 'J', 0x1970, EDID_QUIRK_NON_DESKTOP),
221 EDID_QUIRK('D', 'E', 'L', 0x7fce, EDID_QUIRK_NON_DESKTOP),
222 EDID_QUIRK('S', 'E', 'C', 0x144a, EDID_QUIRK_NON_DESKTOP),
223 EDID_QUIRK('A', 'U', 'S', 0xc102, EDID_QUIRK_NON_DESKTOP),
ccffc9eb
PZ		 224
225 /* Sony PlayStation VR Headset */
7d1be0a0 226 EDID_QUIRK('S', 'N', 'Y', 0x0704, EDID_QUIRK_NON_DESKTOP),
29054230
RP		 227
228 /* Sensics VR Headsets */
7d1be0a0 229 EDID_QUIRK('S', 'E', 'N', 0x1019, EDID_QUIRK_NON_DESKTOP),
29054230
RP		 230
231 /* OSVR HDK and HDK2 VR Headsets */
7d1be0a0 232 EDID_QUIRK('S', 'V', 'R', 0x1019, EDID_QUIRK_NON_DESKTOP),
f453ba04
DA		 233};
234
a6b21831
TR		 235/*
236 * Autogenerated from the DMT spec.
237 * This table is copied from xfree86/modes/xf86EdidModes.c.
238 */
239static const struct drm_display_mode drm_dmt_modes[] = {
24b856b1 240 /* 0x01 - 640x350@85Hz */
a6b21831
TR		 241 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
242 736, 832, 0, 350, 382, 385, 445, 0,
243 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 244 /* 0x02 - 640x400@85Hz */
a6b21831
TR		 245 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
246 736, 832, 0, 400, 401, 404, 445, 0,
247 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 248 /* 0x03 - 720x400@85Hz */
a6b21831
TR		 249 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
250 828, 936, 0, 400, 401, 404, 446, 0,
251 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 252 /* 0x04 - 640x480@60Hz */
a6b21831 253 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
fcf22d05 254 752, 800, 0, 480, 490, 492, 525, 0,
a6b21831 255 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 256 /* 0x05 - 640x480@72Hz */
a6b21831
TR		 257 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
258 704, 832, 0, 480, 489, 492, 520, 0,
259 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 260 /* 0x06 - 640x480@75Hz */
a6b21831
TR		 261 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
262 720, 840, 0, 480, 481, 484, 500, 0,
263 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 264 /* 0x07 - 640x480@85Hz */
a6b21831
TR		 265 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
266 752, 832, 0, 480, 481, 484, 509, 0,
267 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 268 /* 0x08 - 800x600@56Hz */
a6b21831
TR		 269 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
270 896, 1024, 0, 600, 601, 603, 625, 0,
271 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 272 /* 0x09 - 800x600@60Hz */
a6b21831
TR		 273 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
274 968, 1056, 0, 600, 601, 605, 628, 0,
275 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 276 /* 0x0a - 800x600@72Hz */
a6b21831
TR		 277 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
278 976, 1040, 0, 600, 637, 643, 666, 0,
279 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 280 /* 0x0b - 800x600@75Hz */
a6b21831
TR		 281 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
282 896, 1056, 0, 600, 601, 604, 625, 0,
283 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 284 /* 0x0c - 800x600@85Hz */
a6b21831
TR		 285 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
286 896, 1048, 0, 600, 601, 604, 631, 0,
287 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 288 /* 0x0d - 800x600@120Hz RB */
a6b21831
TR		 289 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
290 880, 960, 0, 600, 603, 607, 636, 0,
291 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 292 /* 0x0e - 848x480@60Hz */
a6b21831
TR		 293 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
294 976, 1088, 0, 480, 486, 494, 517, 0,
295 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 296 /* 0x0f - 1024x768@43Hz, interlace */
a6b21831 297 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
735b100f 298 1208, 1264, 0, 768, 768, 776, 817, 0,
a6b21831 299 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
fcf22d05 300 DRM_MODE_FLAG_INTERLACE) },
24b856b1 301 /* 0x10 - 1024x768@60Hz */
a6b21831
TR		 302 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
303 1184, 1344, 0, 768, 771, 777, 806, 0,
304 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 305 /* 0x11 - 1024x768@70Hz */
a6b21831
TR		 306 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
307 1184, 1328, 0, 768, 771, 777, 806, 0,
308 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 309 /* 0x12 - 1024x768@75Hz */
a6b21831
TR		 310 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
311 1136, 1312, 0, 768, 769, 772, 800, 0,
312 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 313 /* 0x13 - 1024x768@85Hz */
a6b21831
TR		 314 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
315 1168, 1376, 0, 768, 769, 772, 808, 0,
316 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 317 /* 0x14 - 1024x768@120Hz RB */
a6b21831
TR		 318 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
319 1104, 1184, 0, 768, 771, 775, 813, 0,
320 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 321 /* 0x15 - 1152x864@75Hz */
a6b21831
TR		 322 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
323 1344, 1600, 0, 864, 865, 868, 900, 0,
324 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
bfcd74d2
VS		 325 /* 0x55 - 1280x720@60Hz */
326 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
327 1430, 1650, 0, 720, 725, 730, 750, 0,
328 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 329 /* 0x16 - 1280x768@60Hz RB */
a6b21831
TR		 330 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
331 1360, 1440, 0, 768, 771, 778, 790, 0,
332 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 333 /* 0x17 - 1280x768@60Hz */
a6b21831
TR		 334 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
335 1472, 1664, 0, 768, 771, 778, 798, 0,
336 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 337 /* 0x18 - 1280x768@75Hz */
a6b21831
TR		 338 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
339 1488, 1696, 0, 768, 771, 778, 805, 0,
fcf22d05 340 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 341 /* 0x19 - 1280x768@85Hz */
a6b21831
TR		 342 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
343 1496, 1712, 0, 768, 771, 778, 809, 0,
344 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 345 /* 0x1a - 1280x768@120Hz RB */
a6b21831
TR		 346 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
347 1360, 1440, 0, 768, 771, 778, 813, 0,
348 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 349 /* 0x1b - 1280x800@60Hz RB */
a6b21831
TR		 350 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
351 1360, 1440, 0, 800, 803, 809, 823, 0,
352 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 353 /* 0x1c - 1280x800@60Hz */
a6b21831
TR		 354 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
355 1480, 1680, 0, 800, 803, 809, 831, 0,
fcf22d05 356 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 357 /* 0x1d - 1280x800@75Hz */
a6b21831
TR		 358 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
359 1488, 1696, 0, 800, 803, 809, 838, 0,
360 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 361 /* 0x1e - 1280x800@85Hz */
a6b21831
TR		 362 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
363 1496, 1712, 0, 800, 803, 809, 843, 0,
364 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 365 /* 0x1f - 1280x800@120Hz RB */
a6b21831
TR		 366 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
367 1360, 1440, 0, 800, 803, 809, 847, 0,
368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 369 /* 0x20 - 1280x960@60Hz */
a6b21831
TR		 370 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
371 1488, 1800, 0, 960, 961, 964, 1000, 0,
372 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 373 /* 0x21 - 1280x960@85Hz */
a6b21831
TR		 374 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
375 1504, 1728, 0, 960, 961, 964, 1011, 0,
376 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 377 /* 0x22 - 1280x960@120Hz RB */
a6b21831
TR		 378 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
379 1360, 1440, 0, 960, 963, 967, 1017, 0,
380 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 381 /* 0x23 - 1280x1024@60Hz */
a6b21831
TR		 382 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
383 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
384 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 385 /* 0x24 - 1280x1024@75Hz */
a6b21831
TR		 386 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
387 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
388 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 389 /* 0x25 - 1280x1024@85Hz */
a6b21831
TR		 390 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
391 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
392 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 393 /* 0x26 - 1280x1024@120Hz RB */
a6b21831
TR		 394 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
395 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
396 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 397 /* 0x27 - 1360x768@60Hz */
a6b21831
TR		 398 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
399 1536, 1792, 0, 768, 771, 777, 795, 0,
400 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 401 /* 0x28 - 1360x768@120Hz RB */
a6b21831
TR		 402 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
403 1440, 1520, 0, 768, 771, 776, 813, 0,
404 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 405 /* 0x51 - 1366x768@60Hz */
406 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
407 1579, 1792, 0, 768, 771, 774, 798, 0,
408 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
409 /* 0x56 - 1366x768@60Hz */
410 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
411 1436, 1500, 0, 768, 769, 772, 800, 0,
412 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 413 /* 0x29 - 1400x1050@60Hz RB */
a6b21831
TR		 414 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
415 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
416 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 417 /* 0x2a - 1400x1050@60Hz */
a6b21831
TR		 418 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
419 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
420 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 421 /* 0x2b - 1400x1050@75Hz */
a6b21831
TR		 422 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
423 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
424 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 425 /* 0x2c - 1400x1050@85Hz */
a6b21831
TR		 426 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
427 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
428 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 429 /* 0x2d - 1400x1050@120Hz RB */
a6b21831
TR		 430 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
431 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
432 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 433 /* 0x2e - 1440x900@60Hz RB */
a6b21831
TR		 434 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
435 1520, 1600, 0, 900, 903, 909, 926, 0,
436 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 437 /* 0x2f - 1440x900@60Hz */
a6b21831
TR		 438 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
439 1672, 1904, 0, 900, 903, 909, 934, 0,
440 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 441 /* 0x30 - 1440x900@75Hz */
a6b21831
TR		 442 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
443 1688, 1936, 0, 900, 903, 909, 942, 0,
444 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 445 /* 0x31 - 1440x900@85Hz */
a6b21831
TR		 446 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
447 1696, 1952, 0, 900, 903, 909, 948, 0,
448 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 449 /* 0x32 - 1440x900@120Hz RB */
a6b21831
TR		 450 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
451 1520, 1600, 0, 900, 903, 909, 953, 0,
452 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 453 /* 0x53 - 1600x900@60Hz */
454 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
455 1704, 1800, 0, 900, 901, 904, 1000, 0,
456 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 457 /* 0x33 - 1600x1200@60Hz */
a6b21831
TR		 458 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
459 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
460 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 461 /* 0x34 - 1600x1200@65Hz */
a6b21831
TR		 462 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
463 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
464 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 465 /* 0x35 - 1600x1200@70Hz */
a6b21831
TR		 466 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
467 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
468 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 469 /* 0x36 - 1600x1200@75Hz */
a6b21831
TR		 470 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
471 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
472 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 473 /* 0x37 - 1600x1200@85Hz */
a6b21831
TR		 474 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
475 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
476 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 477 /* 0x38 - 1600x1200@120Hz RB */
a6b21831
TR		 478 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
479 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
480 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 481 /* 0x39 - 1680x1050@60Hz RB */
a6b21831
TR		 482 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
483 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
484 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 485 /* 0x3a - 1680x1050@60Hz */
a6b21831
TR		 486 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
487 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
488 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 489 /* 0x3b - 1680x1050@75Hz */
a6b21831
TR		 490 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
491 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
492 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 493 /* 0x3c - 1680x1050@85Hz */
a6b21831
TR		 494 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
495 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
496 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 497 /* 0x3d - 1680x1050@120Hz RB */
a6b21831
TR		 498 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
499 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
500 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 501 /* 0x3e - 1792x1344@60Hz */
a6b21831
TR		 502 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
503 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
504 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 505 /* 0x3f - 1792x1344@75Hz */
a6b21831
TR		 506 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
507 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
508 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 509 /* 0x40 - 1792x1344@120Hz RB */
a6b21831
TR		 510 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
511 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
512 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 513 /* 0x41 - 1856x1392@60Hz */
a6b21831
TR		 514 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
515 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
516 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 517 /* 0x42 - 1856x1392@75Hz */
a6b21831 518 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
fcf22d05 519 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
a6b21831 520 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 521 /* 0x43 - 1856x1392@120Hz RB */
a6b21831
TR		 522 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
523 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
524 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 525 /* 0x52 - 1920x1080@60Hz */
526 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
527 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
528 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 529 /* 0x44 - 1920x1200@60Hz RB */
a6b21831
TR		 530 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
531 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
532 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 533 /* 0x45 - 1920x1200@60Hz */
a6b21831
TR		 534 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
535 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
536 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 537 /* 0x46 - 1920x1200@75Hz */
a6b21831
TR		 538 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
539 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
540 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 541 /* 0x47 - 1920x1200@85Hz */
a6b21831
TR		 542 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
543 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
544 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 545 /* 0x48 - 1920x1200@120Hz RB */
a6b21831
TR		 546 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
547 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
548 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 549 /* 0x49 - 1920x1440@60Hz */
a6b21831
TR		 550 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
551 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
552 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 553 /* 0x4a - 1920x1440@75Hz */
a6b21831
TR		 554 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
555 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
556 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 557 /* 0x4b - 1920x1440@120Hz RB */
a6b21831
TR		 558 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
559 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
560 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 561 /* 0x54 - 2048x1152@60Hz */
562 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
563 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
564 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 565 /* 0x4c - 2560x1600@60Hz RB */
a6b21831
TR		 566 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
567 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
568 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 569 /* 0x4d - 2560x1600@60Hz */
a6b21831
TR		 570 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
571 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
572 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 573 /* 0x4e - 2560x1600@75Hz */
a6b21831
TR		 574 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
575 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
576 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 577 /* 0x4f - 2560x1600@85Hz */
a6b21831
TR		 578 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
579 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
580 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 581 /* 0x50 - 2560x1600@120Hz RB */
a6b21831
TR		 582 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
583 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
584 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 585 /* 0x57 - 4096x2160@60Hz RB */
586 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
587 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
588 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
589 /* 0x58 - 4096x2160@59.94Hz RB */
590 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
591 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
592 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
a6b21831
TR		 593};
594
e7bfa5c4
VS		 595/*
596 * These more or less come from the DMT spec. The 720x400 modes are
597 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
598 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
599 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
600 * mode.
601 *
602 * The DMT modes have been fact-checked; the rest are mild guesses.
603 */
a6b21831
TR		 604static const struct drm_display_mode edid_est_modes[] = {
605 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
606 968, 1056, 0, 600, 601, 605, 628, 0,
607 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
608 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
609 896, 1024, 0, 600, 601, 603, 625, 0,
610 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
611 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
612 720, 840, 0, 480, 481, 484, 500, 0,
613 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
614 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
87707cfd 615 704, 832, 0, 480, 489, 492, 520, 0,
a6b21831
TR		 616 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
617 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
618 768, 864, 0, 480, 483, 486, 525, 0,
619 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
87707cfd 620 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
a6b21831
TR		 621 752, 800, 0, 480, 490, 492, 525, 0,
622 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
623 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
624 846, 900, 0, 400, 421, 423, 449, 0,
625 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
626 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
627 846, 900, 0, 400, 412, 414, 449, 0,
628 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
629 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
630 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
631 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
87707cfd 632 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
a6b21831
TR		 633 1136, 1312, 0, 768, 769, 772, 800, 0,
634 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
635 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
636 1184, 1328, 0, 768, 771, 777, 806, 0,
637 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
638 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
639 1184, 1344, 0, 768, 771, 777, 806, 0,
640 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
641 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
642 1208, 1264, 0, 768, 768, 776, 817, 0,
643 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
644 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
645 928, 1152, 0, 624, 625, 628, 667, 0,
646 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
647 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
648 896, 1056, 0, 600, 601, 604, 625, 0,
649 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
650 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
651 976, 1040, 0, 600, 637, 643, 666, 0,
652 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
653 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
654 1344, 1600, 0, 864, 865, 868, 900, 0,
655 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
656};
657
658struct minimode {
659 short w;
660 short h;
661 short r;
662 short rb;
663};
664
665static const struct minimode est3_modes[] = {
666 /* byte 6 */
667 { 640, 350, 85, 0 },
668 { 640, 400, 85, 0 },
669 { 720, 400, 85, 0 },
670 { 640, 480, 85, 0 },
671 { 848, 480, 60, 0 },
672 { 800, 600, 85, 0 },
673 { 1024, 768, 85, 0 },
674 { 1152, 864, 75, 0 },
675 /* byte 7 */
676 { 1280, 768, 60, 1 },
677 { 1280, 768, 60, 0 },
678 { 1280, 768, 75, 0 },
679 { 1280, 768, 85, 0 },
680 { 1280, 960, 60, 0 },
681 { 1280, 960, 85, 0 },
682 { 1280, 1024, 60, 0 },
683 { 1280, 1024, 85, 0 },
684 /* byte 8 */
685 { 1360, 768, 60, 0 },
686 { 1440, 900, 60, 1 },
687 { 1440, 900, 60, 0 },
688 { 1440, 900, 75, 0 },
689 { 1440, 900, 85, 0 },
690 { 1400, 1050, 60, 1 },
691 { 1400, 1050, 60, 0 },
692 { 1400, 1050, 75, 0 },
693 /* byte 9 */
694 { 1400, 1050, 85, 0 },
695 { 1680, 1050, 60, 1 },
696 { 1680, 1050, 60, 0 },
697 { 1680, 1050, 75, 0 },
698 { 1680, 1050, 85, 0 },
699 { 1600, 1200, 60, 0 },
700 { 1600, 1200, 65, 0 },
701 { 1600, 1200, 70, 0 },
702 /* byte 10 */
703 { 1600, 1200, 75, 0 },
704 { 1600, 1200, 85, 0 },
705 { 1792, 1344, 60, 0 },
c068b32a 706 { 1792, 1344, 75, 0 },
a6b21831
TR		 707 { 1856, 1392, 60, 0 },
708 { 1856, 1392, 75, 0 },
709 { 1920, 1200, 60, 1 },
710 { 1920, 1200, 60, 0 },
711 /* byte 11 */
712 { 1920, 1200, 75, 0 },
713 { 1920, 1200, 85, 0 },
714 { 1920, 1440, 60, 0 },
715 { 1920, 1440, 75, 0 },
716};
717
718static const struct minimode extra_modes[] = {
719 { 1024, 576, 60, 0 },
720 { 1366, 768, 60, 0 },
721 { 1600, 900, 60, 0 },
722 { 1680, 945, 60, 0 },
723 { 1920, 1080, 60, 0 },
724 { 2048, 1152, 60, 0 },
725 { 2048, 1536, 60, 0 },
726};
727
728/*
7befe621 729 * From CEA/CTA-861 spec.
d9278b4c 730 *
7befe621 731 * Do not access directly, instead always use cea_mode_for_vic().
a6b21831 732 */
8c1b2bd9 733static const struct drm_display_mode edid_cea_modes_1[] = {
78691960 734 /* 1 - 640x480@60Hz 4:3 */
a6b21831
TR		 735 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
736 752, 800, 0, 480, 490, 492, 525, 0,
ee7925bb 737 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 738 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 739 /* 2 - 720x480@60Hz 4:3 */
a6b21831
TR		 740 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
741 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 742 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 743 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 744 /* 3 - 720x480@60Hz 16:9 */
a6b21831
TR		 745 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
746 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 747 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 748 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 749 /* 4 - 1280x720@60Hz 16:9 */
a6b21831
TR		 750 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
751 1430, 1650, 0, 720, 725, 730, 750, 0,
ee7925bb 752 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 753 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 754 /* 5 - 1920x1080i@60Hz 16:9 */
a6b21831
TR		 755 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
756 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
757 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 758 DRM_MODE_FLAG_INTERLACE),
0425662f 759 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 760 /* 6 - 720(1440)x480i@60Hz 4:3 */
fb01d280
CT		 761 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
762 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 763 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 764 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 765 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 766 /* 7 - 720(1440)x480i@60Hz 16:9 */
fb01d280
CT		 767 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
768 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 769 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 770 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 771 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 772 /* 8 - 720(1440)x240@60Hz 4:3 */
fb01d280
CT		 773 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
774 801, 858, 0, 240, 244, 247, 262, 0,
a6b21831 775 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 776 DRM_MODE_FLAG_DBLCLK),
0425662f 777 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 778 /* 9 - 720(1440)x240@60Hz 16:9 */
fb01d280
CT		 779 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
780 801, 858, 0, 240, 244, 247, 262, 0,
a6b21831 781 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 782 DRM_MODE_FLAG_DBLCLK),
0425662f 783 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 784 /* 10 - 2880x480i@60Hz 4:3 */
a6b21831
TR		 785 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
786 3204, 3432, 0, 480, 488, 494, 525, 0,
787 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 788 DRM_MODE_FLAG_INTERLACE),
0425662f 789 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 790 /* 11 - 2880x480i@60Hz 16:9 */
a6b21831
TR		 791 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
792 3204, 3432, 0, 480, 488, 494, 525, 0,
793 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 794 DRM_MODE_FLAG_INTERLACE),
0425662f 795 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 796 /* 12 - 2880x240@60Hz 4:3 */
a6b21831
TR		 797 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
798 3204, 3432, 0, 240, 244, 247, 262, 0,
ee7925bb 799 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 800 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 801 /* 13 - 2880x240@60Hz 16:9 */
a6b21831
TR		 802 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
803 3204, 3432, 0, 240, 244, 247, 262, 0,
ee7925bb 804 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 805 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 806 /* 14 - 1440x480@60Hz 4:3 */
a6b21831
TR		 807 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
808 1596, 1716, 0, 480, 489, 495, 525, 0,
ee7925bb 809 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 810 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 811 /* 15 - 1440x480@60Hz 16:9 */
a6b21831
TR		 812 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
813 1596, 1716, 0, 480, 489, 495, 525, 0,
ee7925bb 814 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 815 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 816 /* 16 - 1920x1080@60Hz 16:9 */
a6b21831
TR		 817 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
818 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 819 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 820 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 821 /* 17 - 720x576@50Hz 4:3 */
a6b21831
TR		 822 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
823 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 824 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 825 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 826 /* 18 - 720x576@50Hz 16:9 */
a6b21831
TR		 827 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
828 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 829 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 830 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 831 /* 19 - 1280x720@50Hz 16:9 */
a6b21831
TR		 832 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
833 1760, 1980, 0, 720, 725, 730, 750, 0,
ee7925bb 834 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 835 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 836 /* 20 - 1920x1080i@50Hz 16:9 */
a6b21831
TR		 837 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
838 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
839 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 840 DRM_MODE_FLAG_INTERLACE),
0425662f 841 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 842 /* 21 - 720(1440)x576i@50Hz 4:3 */
fb01d280
CT		 843 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
844 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 845 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 846 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 847 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 848 /* 22 - 720(1440)x576i@50Hz 16:9 */
fb01d280
CT		 849 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
850 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 851 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 852 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 853 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 854 /* 23 - 720(1440)x288@50Hz 4:3 */
fb01d280
CT		 855 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
856 795, 864, 0, 288, 290, 293, 312, 0,
a6b21831 857 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 858 DRM_MODE_FLAG_DBLCLK),
0425662f 859 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 860 /* 24 - 720(1440)x288@50Hz 16:9 */
fb01d280
CT		 861 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
862 795, 864, 0, 288, 290, 293, 312, 0,
a6b21831 863 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 864 DRM_MODE_FLAG_DBLCLK),
0425662f 865 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 866 /* 25 - 2880x576i@50Hz 4:3 */
a6b21831
TR		 867 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
868 3180, 3456, 0, 576, 580, 586, 625, 0,
869 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 870 DRM_MODE_FLAG_INTERLACE),
0425662f 871 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 872 /* 26 - 2880x576i@50Hz 16:9 */
a6b21831
TR		 873 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
874 3180, 3456, 0, 576, 580, 586, 625, 0,
875 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 876 DRM_MODE_FLAG_INTERLACE),
0425662f 877 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 878 /* 27 - 2880x288@50Hz 4:3 */
a6b21831
TR		 879 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
880 3180, 3456, 0, 288, 290, 293, 312, 0,
ee7925bb 881 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 882 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 883 /* 28 - 2880x288@50Hz 16:9 */
a6b21831
TR		 884 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
885 3180, 3456, 0, 288, 290, 293, 312, 0,
ee7925bb 886 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 887 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 888 /* 29 - 1440x576@50Hz 4:3 */
a6b21831
TR		 889 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
890 1592, 1728, 0, 576, 581, 586, 625, 0,
ee7925bb 891 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 892 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 893 /* 30 - 1440x576@50Hz 16:9 */
a6b21831
TR		 894 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
895 1592, 1728, 0, 576, 581, 586, 625, 0,
ee7925bb 896 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 897 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 898 /* 31 - 1920x1080@50Hz 16:9 */
a6b21831
TR		 899 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
900 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 901 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 902 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 903 /* 32 - 1920x1080@24Hz 16:9 */
a6b21831
TR		 904 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
905 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 906 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 907 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 908 /* 33 - 1920x1080@25Hz 16:9 */
a6b21831
TR		 909 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
910 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 911 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 912 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 913 /* 34 - 1920x1080@30Hz 16:9 */
a6b21831
TR		 914 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
915 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 916 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 917 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 918 /* 35 - 2880x480@60Hz 4:3 */
a6b21831
TR		 919 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
920 3192, 3432, 0, 480, 489, 495, 525, 0,
ee7925bb 921 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 922 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 923 /* 36 - 2880x480@60Hz 16:9 */
a6b21831
TR		 924 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
925 3192, 3432, 0, 480, 489, 495, 525, 0,
ee7925bb 926 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 927 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 928 /* 37 - 2880x576@50Hz 4:3 */
a6b21831
TR		 929 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
930 3184, 3456, 0, 576, 581, 586, 625, 0,
ee7925bb 931 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 932 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 933 /* 38 - 2880x576@50Hz 16:9 */
a6b21831
TR		 934 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
935 3184, 3456, 0, 576, 581, 586, 625, 0,
ee7925bb 936 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 937 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 938 /* 39 - 1920x1080i@50Hz 16:9 */
a6b21831
TR		 939 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
940 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
941 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 942 DRM_MODE_FLAG_INTERLACE),
0425662f 943 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 944 /* 40 - 1920x1080i@100Hz 16:9 */
a6b21831
TR		 945 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
946 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
947 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 948 DRM_MODE_FLAG_INTERLACE),
0425662f 949 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 950 /* 41 - 1280x720@100Hz 16:9 */
a6b21831
TR		 951 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
952 1760, 1980, 0, 720, 725, 730, 750, 0,
ee7925bb 953 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 954 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 955 /* 42 - 720x576@100Hz 4:3 */
a6b21831
TR		 956 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
957 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 958 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 959 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 960 /* 43 - 720x576@100Hz 16:9 */
a6b21831
TR		 961 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
962 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 963 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 964 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 965 /* 44 - 720(1440)x576i@100Hz 4:3 */
fb01d280
CT		 966 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
967 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 968 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 969 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 970 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 971 /* 45 - 720(1440)x576i@100Hz 16:9 */
fb01d280
CT		 972 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
973 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 974 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 975 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 976 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 977 /* 46 - 1920x1080i@120Hz 16:9 */
a6b21831
TR		 978 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
979 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
980 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 981 DRM_MODE_FLAG_INTERLACE),
0425662f 982 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 983 /* 47 - 1280x720@120Hz 16:9 */
a6b21831
TR		 984 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
985 1430, 1650, 0, 720, 725, 730, 750, 0,
ee7925bb 986 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 987 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 988 /* 48 - 720x480@120Hz 4:3 */
a6b21831
TR		 989 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
990 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 991 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 992 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 993 /* 49 - 720x480@120Hz 16:9 */
a6b21831
TR		 994 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
995 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 996 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 997 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 998 /* 50 - 720(1440)x480i@120Hz 4:3 */
fb01d280
CT		 999 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
1000 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 1001 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1002 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1003 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1004 /* 51 - 720(1440)x480i@120Hz 16:9 */
fb01d280
CT		 1005 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
1006 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 1007 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1008 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1009 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1010 /* 52 - 720x576@200Hz 4:3 */
a6b21831
TR		 1011 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1012 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 1013 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 1014 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1015 /* 53 - 720x576@200Hz 16:9 */
a6b21831
TR		 1016 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1017 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 1018 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 1019 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1020 /* 54 - 720(1440)x576i@200Hz 4:3 */
fb01d280
CT		 1021 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1022 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 1023 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1024 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1025 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1026 /* 55 - 720(1440)x576i@200Hz 16:9 */
fb01d280
CT		 1027 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1028 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 1029 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1030 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1031 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1032 /* 56 - 720x480@240Hz 4:3 */
a6b21831
TR		 1033 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1034 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 1035 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 1036 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1037 /* 57 - 720x480@240Hz 16:9 */
a6b21831
TR		 1038 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1039 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 1040 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 1041 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1042 /* 58 - 720(1440)x480i@240Hz 4:3 */
fb01d280
CT		 1043 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1044 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 1045 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1046 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1047 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1048 /* 59 - 720(1440)x480i@240Hz 16:9 */
fb01d280
CT		 1049 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1050 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 1051 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1052 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1053 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1054 /* 60 - 1280x720@24Hz 16:9 */
a6b21831
TR		 1055 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1056 3080, 3300, 0, 720, 725, 730, 750, 0,
ee7925bb 1057 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1058 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1059 /* 61 - 1280x720@25Hz 16:9 */
a6b21831
TR		 1060 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1061 3740, 3960, 0, 720, 725, 730, 750, 0,
ee7925bb 1062 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1063 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1064 /* 62 - 1280x720@30Hz 16:9 */
a6b21831
TR		 1065 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1066 3080, 3300, 0, 720, 725, 730, 750, 0,
ee7925bb 1067 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1068 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1069 /* 63 - 1920x1080@120Hz 16:9 */
a6b21831
TR		 1070 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1071 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 1072 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1073 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1074 /* 64 - 1920x1080@100Hz 16:9 */
a6b21831 1075 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
8f0e4907 1076 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 1077 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1078 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1079 /* 65 - 1280x720@24Hz 64:27 */
8ec6e075
SS		 1080 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1081 3080, 3300, 0, 720, 725, 730, 750, 0,
1082 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1083 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1084 /* 66 - 1280x720@25Hz 64:27 */
8ec6e075
SS		 1085 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1086 3740, 3960, 0, 720, 725, 730, 750, 0,
1087 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1088 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1089 /* 67 - 1280x720@30Hz 64:27 */
8ec6e075
SS		 1090 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1091 3080, 3300, 0, 720, 725, 730, 750, 0,
1092 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1093 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1094 /* 68 - 1280x720@50Hz 64:27 */
8ec6e075
SS		 1095 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1096 1760, 1980, 0, 720, 725, 730, 750, 0,
1097 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1098 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1099 /* 69 - 1280x720@60Hz 64:27 */
8ec6e075
SS		 1100 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1101 1430, 1650, 0, 720, 725, 730, 750, 0,
1102 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1103 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1104 /* 70 - 1280x720@100Hz 64:27 */
8ec6e075
SS		 1105 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1106 1760, 1980, 0, 720, 725, 730, 750, 0,
1107 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1108 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1109 /* 71 - 1280x720@120Hz 64:27 */
8ec6e075
SS		 1110 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1111 1430, 1650, 0, 720, 725, 730, 750, 0,
1112 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1113 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1114 /* 72 - 1920x1080@24Hz 64:27 */
8ec6e075
SS		 1115 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1116 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1117 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1118 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1119 /* 73 - 1920x1080@25Hz 64:27 */
8ec6e075
SS		 1120 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1121 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1122 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1123 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1124 /* 74 - 1920x1080@30Hz 64:27 */
8ec6e075
SS		 1125 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1126 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1127 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1128 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1129 /* 75 - 1920x1080@50Hz 64:27 */
8ec6e075
SS		 1130 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1131 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1132 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1133 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1134 /* 76 - 1920x1080@60Hz 64:27 */
8ec6e075
SS		 1135 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1136 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1137 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1138 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1139 /* 77 - 1920x1080@100Hz 64:27 */
8ec6e075
SS		 1140 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1141 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1142 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1143 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1144 /* 78 - 1920x1080@120Hz 64:27 */
8ec6e075
SS		 1145 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1146 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1147 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1148 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1149 /* 79 - 1680x720@24Hz 64:27 */
8ec6e075
SS		 1150 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1151 3080, 3300, 0, 720, 725, 730, 750, 0,
1152 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1153 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1154 /* 80 - 1680x720@25Hz 64:27 */
8ec6e075
SS		 1155 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1156 2948, 3168, 0, 720, 725, 730, 750, 0,
1157 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1158 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1159 /* 81 - 1680x720@30Hz 64:27 */
8ec6e075
SS		 1160 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1161 2420, 2640, 0, 720, 725, 730, 750, 0,
1162 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1163 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1164 /* 82 - 1680x720@50Hz 64:27 */
8ec6e075
SS		 1165 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1166 1980, 2200, 0, 720, 725, 730, 750, 0,
1167 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1168 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1169 /* 83 - 1680x720@60Hz 64:27 */
8ec6e075
SS		 1170 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1171 1980, 2200, 0, 720, 725, 730, 750, 0,
1172 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1173 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1174 /* 84 - 1680x720@100Hz 64:27 */
8ec6e075
SS		 1175 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1176 1780, 2000, 0, 720, 725, 730, 825, 0,
1177 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1178 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1179 /* 85 - 1680x720@120Hz 64:27 */
8ec6e075
SS		 1180 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1181 1780, 2000, 0, 720, 725, 730, 825, 0,
1182 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1183 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1184 /* 86 - 2560x1080@24Hz 64:27 */
8ec6e075
SS		 1185 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1186 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1187 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1188 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1189 /* 87 - 2560x1080@25Hz 64:27 */
8ec6e075
SS		 1190 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1191 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1192 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1193 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1194 /* 88 - 2560x1080@30Hz 64:27 */
8ec6e075
SS		 1195 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1196 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1197 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1198 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1199 /* 89 - 2560x1080@50Hz 64:27 */
8ec6e075
SS		 1200 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1201 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1202 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1203 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1204 /* 90 - 2560x1080@60Hz 64:27 */
8ec6e075
SS		 1205 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1206 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1207 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1208 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1209 /* 91 - 2560x1080@100Hz 64:27 */
8ec6e075
SS		 1210 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1211 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1212 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1213 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1214 /* 92 - 2560x1080@120Hz 64:27 */
8ec6e075
SS		 1215 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1216 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1217 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1218 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1219 /* 93 - 3840x2160@24Hz 16:9 */
8ec6e075
SS		 1220 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1221 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1222 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1223 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1224 /* 94 - 3840x2160@25Hz 16:9 */
8ec6e075
SS		 1225 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1226 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1227 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1228 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1229 /* 95 - 3840x2160@30Hz 16:9 */
8ec6e075
SS		 1230 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1231 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1232 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1233 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1234 /* 96 - 3840x2160@50Hz 16:9 */
8ec6e075
SS		 1235 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1236 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1237 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1238 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1239 /* 97 - 3840x2160@60Hz 16:9 */
8ec6e075
SS		 1240 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1241 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1242 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1243 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1244 /* 98 - 4096x2160@24Hz 256:135 */
8ec6e075
SS		 1245 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1246 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1247 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1248 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1249 /* 99 - 4096x2160@25Hz 256:135 */
8ec6e075
SS		 1250 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1251 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1252 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1253 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1254 /* 100 - 4096x2160@30Hz 256:135 */
8ec6e075
SS		 1255 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1256 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1257 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1258 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1259 /* 101 - 4096x2160@50Hz 256:135 */
8ec6e075
SS		 1260 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1261 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1262 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1263 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1264 /* 102 - 4096x2160@60Hz 256:135 */
8ec6e075
SS		 1265 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1266 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1267 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1268 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1269 /* 103 - 3840x2160@24Hz 64:27 */
8ec6e075
SS		 1270 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1271 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1273 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1274 /* 104 - 3840x2160@25Hz 64:27 */
8ec6e075
SS		 1275 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1276 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1277 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1278 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1279 /* 105 - 3840x2160@30Hz 64:27 */
8ec6e075
SS		 1280 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1281 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1282 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1283 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1284 /* 106 - 3840x2160@50Hz 64:27 */
8ec6e075
SS		 1285 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1286 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1287 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1288 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1289 /* 107 - 3840x2160@60Hz 64:27 */
8ec6e075
SS		 1290 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1291 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1292 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1293 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1294 /* 108 - 1280x720@48Hz 16:9 */
1295 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1296 2280, 2500, 0, 720, 725, 730, 750, 0,
1297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1298 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1299 /* 109 - 1280x720@48Hz 64:27 */
1300 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1301 2280, 2500, 0, 720, 725, 730, 750, 0,
1302 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1303 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1304 /* 110 - 1680x720@48Hz 64:27 */
1305 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490,
1306 2530, 2750, 0, 720, 725, 730, 750, 0,
1307 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1308 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1309 /* 111 - 1920x1080@48Hz 16:9 */
1310 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1311 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1312 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1313 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1314 /* 112 - 1920x1080@48Hz 64:27 */
1315 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1316 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1318 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1319 /* 113 - 2560x1080@48Hz 64:27 */
1320 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558,
1321 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1322 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1323 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1324 /* 114 - 3840x2160@48Hz 16:9 */
1325 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1326 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1327 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1328 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1329 /* 115 - 4096x2160@48Hz 256:135 */
1330 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116,
1331 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1332 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1333 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
978f6b06
VS		 1334 /* 116 - 3840x2160@48Hz 64:27 */
1335 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1336 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1337 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1338 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1339 /* 117 - 3840x2160@100Hz 16:9 */
1340 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1341 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1342 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1343 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1344 /* 118 - 3840x2160@120Hz 16:9 */
1345 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1346 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1347 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1348 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1349 /* 119 - 3840x2160@100Hz 64:27 */
1350 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1351 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1352 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1353 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1354 /* 120 - 3840x2160@120Hz 64:27 */
1355 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1356 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1357 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1358 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1359 /* 121 - 5120x2160@24Hz 64:27 */
1360 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116,
1361 7204, 7500, 0, 2160, 2168, 2178, 2200, 0,
1362 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1363 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1364 /* 122 - 5120x2160@25Hz 64:27 */
1365 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816,
1366 6904, 7200, 0, 2160, 2168, 2178, 2200, 0,
1367 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1368 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1369 /* 123 - 5120x2160@30Hz 64:27 */
1370 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784,
1371 5872, 6000, 0, 2160, 2168, 2178, 2200, 0,
1372 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1373 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1374 /* 124 - 5120x2160@48Hz 64:27 */
1375 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866,
1376 5954, 6250, 0, 2160, 2168, 2178, 2475, 0,
1377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1378 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1379 /* 125 - 5120x2160@50Hz 64:27 */
1380 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216,
1381 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1382 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1383 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1384 /* 126 - 5120x2160@60Hz 64:27 */
1385 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284,
1386 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1387 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1388 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1389 /* 127 - 5120x2160@100Hz 64:27 */
1390 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216,
1391 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1392 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1393 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
a6b21831
TR		 1394};
1395
f7655d42
VS		 1396/*
1397 * From CEA/CTA-861 spec.
1398 *
1399 * Do not access directly, instead always use cea_mode_for_vic().
1400 */
1401static const struct drm_display_mode edid_cea_modes_193[] = {
1402 /* 193 - 5120x2160@120Hz 64:27 */
1403 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284,
1404 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1405 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1406 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1407 /* 194 - 7680x4320@24Hz 16:9 */
1408 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1409 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1410 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1411 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1412 /* 195 - 7680x4320@25Hz 16:9 */
1413 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1414 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1415 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1416 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1417 /* 196 - 7680x4320@30Hz 16:9 */
1418 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1419 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1420 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1421 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1422 /* 197 - 7680x4320@48Hz 16:9 */
1423 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1424 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1425 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1426 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1427 /* 198 - 7680x4320@50Hz 16:9 */
1428 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1429 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1430 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1431 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1432 /* 199 - 7680x4320@60Hz 16:9 */
1433 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1434 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1435 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1436 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1437 /* 200 - 7680x4320@100Hz 16:9 */
1438 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1439 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1440 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1441 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1442 /* 201 - 7680x4320@120Hz 16:9 */
1443 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1444 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1445 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1446 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1447 /* 202 - 7680x4320@24Hz 64:27 */
1448 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1449 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1450 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1451 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1452 /* 203 - 7680x4320@25Hz 64:27 */
1453 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1454 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1455 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1456 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1457 /* 204 - 7680x4320@30Hz 64:27 */
1458 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1459 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1460 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1461 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1462 /* 205 - 7680x4320@48Hz 64:27 */
1463 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1464 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1466 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1467 /* 206 - 7680x4320@50Hz 64:27 */
1468 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1469 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1470 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1471 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1472 /* 207 - 7680x4320@60Hz 64:27 */
1473 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1474 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1475 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1476 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1477 /* 208 - 7680x4320@100Hz 64:27 */
1478 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1479 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1480 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1481 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1482 /* 209 - 7680x4320@120Hz 64:27 */
1483 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1484 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1485 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1486 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1487 /* 210 - 10240x4320@24Hz 64:27 */
1488 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732,
1489 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1490 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1491 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1492 /* 211 - 10240x4320@25Hz 64:27 */
1493 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732,
1494 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1495 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1496 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1497 /* 212 - 10240x4320@30Hz 64:27 */
1498 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528,
1499 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1500 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1501 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1502 /* 213 - 10240x4320@48Hz 64:27 */
1503 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732,
1504 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1505 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1506 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1507 /* 214 - 10240x4320@50Hz 64:27 */
1508 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732,
1509 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1510 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1511 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1512 /* 215 - 10240x4320@60Hz 64:27 */
1513 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528,
1514 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1515 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1516 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1517 /* 216 - 10240x4320@100Hz 64:27 */
1518 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432,
1519 12608, 13200, 0, 4320, 4336, 4356, 4500, 0,
1520 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1521 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1522 /* 217 - 10240x4320@120Hz 64:27 */
1523 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528,
1524 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1525 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1526 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1527 /* 218 - 4096x2160@100Hz 256:135 */
1528 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896,
1529 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1530 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1531 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
f7655d42
VS		 1532 /* 219 - 4096x2160@120Hz 256:135 */
1533 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184,
1534 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1535 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1536 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
f7655d42
VS		 1537};
1538
7ebe1963 1539/*
d9278b4c 1540 * HDMI 1.4 4k modes. Index using the VIC.
7ebe1963
LD		 1541 */
1542static const struct drm_display_mode edid_4k_modes[] = {
d9278b4c
JN		 1543 /* 0 - dummy, VICs start at 1 */
1544 { },
7ebe1963
LD		 1545 /* 1 - 3840x2160@30Hz */
1546 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1547 3840, 4016, 4104, 4400, 0,
1548 2160, 2168, 2178, 2250, 0,
1549 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1550 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
7ebe1963
LD		 1551 /* 2 - 3840x2160@25Hz */
1552 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1553 3840, 4896, 4984, 5280, 0,
1554 2160, 2168, 2178, 2250, 0,
1555 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1556 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
7ebe1963
LD		 1557 /* 3 - 3840x2160@24Hz */
1558 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1559 3840, 5116, 5204, 5500, 0,
1560 2160, 2168, 2178, 2250, 0,
1561 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1562 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
7ebe1963
LD		 1563 /* 4 - 4096x2160@24Hz (SMPTE) */
1564 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1565 4096, 5116, 5204, 5500, 0,
1566 2160, 2168, 2178, 2250, 0,
1567 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1568 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
7ebe1963
LD		 1569};
1570
61e57a8d 1571/*** DDC fetch and block validation ***/
f453ba04 1572
e4ccf9a7
JN		 1573/*
1574 * The opaque EDID type, internal to drm_edid.c.
1575 */
1576struct drm_edid {
1577 /* Size allocated for edid */
1578 size_t size;
1579 const struct edid *edid;
1580};
1581
18e3c1d5
JN		 1582static int edid_hfeeodb_extension_block_count(const struct edid *edid);
1583
1584static int edid_hfeeodb_block_count(const struct edid *edid)
1585{
1586 int eeodb = edid_hfeeodb_extension_block_count(edid);
1587
1588 return eeodb ? eeodb + 1 : 0;
1589}
1590
f1e4c916
JN		 1591static int edid_extension_block_count(const struct edid *edid)
1592{
1593 return edid->extensions;
1594}
1595
1596static int edid_block_count(const struct edid *edid)
1597{
1598 return edid_extension_block_count(edid) + 1;
1599}
1600
1601static int edid_size_by_blocks(int num_blocks)
1602{
1603 return num_blocks * EDID_LENGTH;
1604}
1605
1606static int edid_size(const struct edid *edid)
1607{
1608 return edid_size_by_blocks(edid_block_count(edid));
1609}
1610
1611static const void *edid_block_data(const struct edid *edid, int index)
1612{
1613 BUILD_BUG_ON(sizeof(*edid) != EDID_LENGTH);
1614
1615 return edid + index;
1616}
1617
1618static const void *edid_extension_block_data(const struct edid *edid, int index)
1619{
1620 return edid_block_data(edid, index + 1);
1621}
1622
b16c9e6c
JN		 1623/* EDID block count indicated in EDID, may exceed allocated size */
1624static int __drm_edid_block_count(const struct drm_edid *drm_edid)
d9307f27
JN		 1625{
1626 int num_blocks;
1627
1628 /* Starting point */
1629 num_blocks = edid_block_count(drm_edid->edid);
1630
b1dee952
JN		 1631 /* HF-EEODB override */
1632 if (drm_edid->size >= edid_size_by_blocks(2)) {
1633 int eeodb;
1634
1635 /*
1636 * Note: HF-EEODB may specify a smaller extension count than the
1637 * regular one. Unlike in buffer allocation, here we can use it.
1638 */
1639 eeodb = edid_hfeeodb_block_count(drm_edid->edid);
1640 if (eeodb)
1641 num_blocks = eeodb;
1642 }
1643
d9307f27
JN		 1644 return num_blocks;
1645}
1646
b16c9e6c
JN		 1647/* EDID block count, limited by allocated size */
1648static int drm_edid_block_count(const struct drm_edid *drm_edid)
1649{
1650 /* Limit by allocated size */
1651 return min(__drm_edid_block_count(drm_edid),
1652 (int)drm_edid->size / EDID_LENGTH);
1653}
1654
1655/* EDID extension block count, limited by allocated size */
d9307f27
JN		 1656static int drm_edid_extension_block_count(const struct drm_edid *drm_edid)
1657{
1658 return drm_edid_block_count(drm_edid) - 1;
1659}
1660
1661static const void *drm_edid_block_data(const struct drm_edid *drm_edid, int index)
1662{
1663 return edid_block_data(drm_edid->edid, index);
1664}
1665
1666static const void *drm_edid_extension_block_data(const struct drm_edid *drm_edid,
1667 int index)
1668{
1669 return edid_extension_block_data(drm_edid->edid, index);
1670}
1671
22a27e05
JN		 1672/*
1673 * Initializer helper for legacy interfaces, where we have no choice but to
1674 * trust edid size. Not for general purpose use.
1675 */
1676static const struct drm_edid *drm_edid_legacy_init(struct drm_edid *drm_edid,
1677 const struct edid *edid)
1678{
1679 if (!edid)
1680 return NULL;
1681
1682 memset(drm_edid, 0, sizeof(*drm_edid));
1683
1684 drm_edid->edid = edid;
1685 drm_edid->size = edid_size(edid);
1686
1687 return drm_edid;
1688}
1689
94afc538
JN		 1690/*
1691 * EDID base and extension block iterator.
1692 *
1693 * struct drm_edid_iter iter;
1694 * const u8 *block;
1695 *
bbded689 1696 * drm_edid_iter_begin(drm_edid, &iter);
94afc538
JN		 1697 * drm_edid_iter_for_each(block, &iter) {
1698 * // do stuff with block
1699 * }
1700 * drm_edid_iter_end(&iter);
1701 */
1702struct drm_edid_iter {
bbded689 1703 const struct drm_edid *drm_edid;
94afc538
JN		 1704
1705 /* Current block index. */
1706 int index;
1707};
1708
bbded689 1709static void drm_edid_iter_begin(const struct drm_edid *drm_edid,
94afc538
JN		 1710 struct drm_edid_iter *iter)
1711{
1712 memset(iter, 0, sizeof(*iter));
1713
bbded689 1714 iter->drm_edid = drm_edid;
94afc538
JN		 1715}
1716
1717static const void *__drm_edid_iter_next(struct drm_edid_iter *iter)
1718{
1719 const void *block = NULL;
1720
bbded689 1721 if (!iter->drm_edid)
94afc538
JN		 1722 return NULL;
1723
d9307f27
JN		 1724 if (iter->index < drm_edid_block_count(iter->drm_edid))
1725 block = drm_edid_block_data(iter->drm_edid, iter->index++);
94afc538
JN		 1726
1727 return block;
1728}
1729
1730#define drm_edid_iter_for_each(__block, __iter) \
1731 while (((__block) = __drm_edid_iter_next(__iter)))
1732
1733static void drm_edid_iter_end(struct drm_edid_iter *iter)
1734{
1735 memset(iter, 0, sizeof(*iter));
1736}
1737
083ae056
AJ		 1738static const u8 edid_header[] = {
1739 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1740};
f453ba04 1741
0a612bbd
JN		 1742static void edid_header_fix(void *edid)
1743{
1744 memcpy(edid, edid_header, sizeof(edid_header));
1745}
1746
db6cf833
TR		 1747/**
1748 * drm_edid_header_is_valid - sanity check the header of the base EDID block
5d96fc9c 1749 * @_edid: pointer to raw base EDID block
db6cf833
TR		 1750 *
1751 * Sanity check the header of the base EDID block.
1752 *
1753 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
051963d4 1754 */
6d987ddd 1755int drm_edid_header_is_valid(const void *_edid)
051963d4 1756{
6d987ddd 1757 const struct edid *edid = _edid;
051963d4
TR		 1758 int i, score = 0;
1759
6d987ddd
JN		 1760 for (i = 0; i < sizeof(edid_header); i++) {
1761 if (edid->header[i] == edid_header[i])
051963d4 1762 score++;
6d987ddd 1763 }
051963d4
TR		 1764
1765 return score;
1766}
1767EXPORT_SYMBOL(drm_edid_header_is_valid);
1768
47819ba2
AJ		 1769static int edid_fixup __read_mostly = 6;
1770module_param_named(edid_fixup, edid_fixup, int, 0400);
1771MODULE_PARM_DESC(edid_fixup,
1772 "Minimum number of valid EDID header bytes (0-8, default 6)");
051963d4 1773
70e49ebe 1774static int edid_block_compute_checksum(const void *_block)
c465bbc8 1775{
70e49ebe 1776 const u8 *block = _block;
c465bbc8 1777 int i;
e11f5bd8
JFZ		 1778 u8 csum = 0, crc = 0;
1779
1780 for (i = 0; i < EDID_LENGTH - 1; i++)
70e49ebe 1781 csum += block[i];
c465bbc8 1782
e11f5bd8
JFZ		 1783 crc = 0x100 - csum;
1784
1785 return crc;
1786}
1787
70e49ebe 1788static int edid_block_get_checksum(const void *_block)
e11f5bd8 1789{
70e49ebe
JN		 1790 const struct edid *block = _block;
1791
1792 return block->checksum;
c465bbc8
SB		 1793}
1794
4ba0f53c
JN		 1795static int edid_block_tag(const void *_block)
1796{
1797 const u8 *block = _block;
1798
1799 return block[0];
1800}
1801
8baccb27 1802static bool edid_block_is_zero(const void *edid)
d6885d65 1803{
8baccb27 1804 return !memchr_inv(edid, 0, EDID_LENGTH);
d6885d65
SB		 1805}
1806
536faa45
SL		 1807/**
1808 * drm_edid_are_equal - compare two edid blobs.
1809 * @edid1: pointer to first blob
1810 * @edid2: pointer to second blob
1811 * This helper can be used during probing to determine if
1812 * edid had changed.
1813 */
1814bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2)
1815{
1816 int edid1_len, edid2_len;
1817 bool edid1_present = edid1 != NULL;
1818 bool edid2_present = edid2 != NULL;
1819
1820 if (edid1_present != edid2_present)
1821 return false;
1822
1823 if (edid1) {
f1e4c916
JN		 1824 edid1_len = edid_size(edid1);
1825 edid2_len = edid_size(edid2);
536faa45
SL		 1826
1827 if (edid1_len != edid2_len)
1828 return false;
1829
1830 if (memcmp(edid1, edid2, edid1_len))
1831 return false;
1832 }
1833
1834 return true;
1835}
1836EXPORT_SYMBOL(drm_edid_are_equal);
1837
1f221284
JN		 1838enum edid_block_status {
1839 EDID_BLOCK_OK = 0,
2deaf1c2 1840 EDID_BLOCK_READ_FAIL,
1f221284 1841 EDID_BLOCK_NULL,
49dc0558 1842 EDID_BLOCK_ZERO,
1f221284
JN		 1843 EDID_BLOCK_HEADER_CORRUPT,
1844 EDID_BLOCK_HEADER_REPAIR,
1845 EDID_BLOCK_HEADER_FIXED,
1846 EDID_BLOCK_CHECKSUM,
1847 EDID_BLOCK_VERSION,
1848};
1849
1850static enum edid_block_status edid_block_check(const void *_block,
1851 bool is_base_block)
1852{
1853 const struct edid *block = _block;
1854
1855 if (!block)
1856 return EDID_BLOCK_NULL;
1857
1858 if (is_base_block) {
1859 int score = drm_edid_header_is_valid(block);
1860
49dc0558
JN		 1861 if (score < clamp(edid_fixup, 0, 8)) {
1862 if (edid_block_is_zero(block))
1863 return EDID_BLOCK_ZERO;
1864 else
1865 return EDID_BLOCK_HEADER_CORRUPT;
1866 }
1f221284
JN		 1867
1868 if (score < 8)
1869 return EDID_BLOCK_HEADER_REPAIR;
1870 }
1871
49dc0558
JN		 1872 if (edid_block_compute_checksum(block) != edid_block_get_checksum(block)) {
1873 if (edid_block_is_zero(block))
1874 return EDID_BLOCK_ZERO;
1875 else
1876 return EDID_BLOCK_CHECKSUM;
1877 }
1f221284
JN		 1878
1879 if (is_base_block) {
1880 if (block->version != 1)
1881 return EDID_BLOCK_VERSION;
1882 }
1883
1884 return EDID_BLOCK_OK;
1885}
1886
1887static bool edid_block_status_valid(enum edid_block_status status, int tag)
1888{
1889 return status == EDID_BLOCK_OK ||
1890 status == EDID_BLOCK_HEADER_FIXED ||
1891 (status == EDID_BLOCK_CHECKSUM && tag == CEA_EXT);
1892}
1893
23e38d7b
JN		 1894static bool edid_block_valid(const void *block, bool base)
1895{
1896 return edid_block_status_valid(edid_block_check(block, base),
1897 edid_block_tag(block));
1898}
1899
cee2ce1a
JN		 1900static void edid_block_status_print(enum edid_block_status status,
1901 const struct edid *block,
1902 int block_num)
1903{
1904 switch (status) {
1905 case EDID_BLOCK_OK:
1906 break;
2deaf1c2
JN		 1907 case EDID_BLOCK_READ_FAIL:
1908 pr_debug("EDID block %d read failed\n", block_num);
1909 break;
cee2ce1a
JN		 1910 case EDID_BLOCK_NULL:
1911 pr_debug("EDID block %d pointer is NULL\n", block_num);
1912 break;
1913 case EDID_BLOCK_ZERO:
1914 pr_notice("EDID block %d is all zeroes\n", block_num);
1915 break;
1916 case EDID_BLOCK_HEADER_CORRUPT:
1917 pr_notice("EDID has corrupt header\n");
1918 break;
1919 case EDID_BLOCK_HEADER_REPAIR:
1920 pr_debug("EDID corrupt header needs repair\n");
1921 break;
1922 case EDID_BLOCK_HEADER_FIXED:
1923 pr_debug("EDID corrupt header fixed\n");
1924 break;
1925 case EDID_BLOCK_CHECKSUM:
1926 if (edid_block_status_valid(status, edid_block_tag(block))) {
1927 pr_debug("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d, ignoring\n",
1928 block_num, edid_block_tag(block),
1929 edid_block_compute_checksum(block));
1930 } else {
1931 pr_notice("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d\n",
1932 block_num, edid_block_tag(block),
1933 edid_block_compute_checksum(block));
1934 }
1935 break;
1936 case EDID_BLOCK_VERSION:
1937 pr_notice("EDID has major version %d, instead of 1\n",
1938 block->version);
1939 break;
1940 default:
1941 WARN(1, "EDID block %d unknown edid block status code %d\n",
1942 block_num, status);
1943 break;
1944 }
1945}
1946
9c7345de
JN		 1947static void edid_block_dump(const char *level, const void *block, int block_num)
1948{
1949 enum edid_block_status status;
1950 char prefix[20];
1951
1952 status = edid_block_check(block, block_num == 0);
1953 if (status == EDID_BLOCK_ZERO)
1954 sprintf(prefix, "\t[%02x] ZERO ", block_num);
1955 else if (!edid_block_status_valid(status, edid_block_tag(block)))
1956 sprintf(prefix, "\t[%02x] BAD ", block_num);
1957 else
1958 sprintf(prefix, "\t[%02x] GOOD ", block_num);
1959
1960 print_hex_dump(level, prefix, DUMP_PREFIX_NONE, 16, 1,
1961 block, EDID_LENGTH, false);
1962}
1963
db6cf833
TR		 1964/**
1965 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
5d96fc9c 1966 * @_block: pointer to raw EDID block
1f221284 1967 * @block_num: type of block to validate (0 for base, extension otherwise)
db6cf833 1968 * @print_bad_edid: if true, dump bad EDID blocks to the console
6ba2bd3d 1969 * @edid_corrupt: if true, the header or checksum is invalid
db6cf833
TR		 1970 *
1971 * Validate a base or extension EDID block and optionally dump bad blocks to
1972 * the console.
1973 *
1974 * Return: True if the block is valid, false otherwise.
f453ba04 1975 */
1f221284 1976bool drm_edid_block_valid(u8 *_block, int block_num, bool print_bad_edid,
6ba2bd3d 1977 bool *edid_corrupt)
f453ba04 1978{
1f221284
JN		 1979 struct edid *block = (struct edid *)_block;
1980 enum edid_block_status status;
1981 bool is_base_block = block_num == 0;
1982 bool valid;
f453ba04 1983
1f221284 1984 if (WARN_ON(!block))
fe2ef780
SWK		 1985 return false;
1986
1f221284
JN		 1987 status = edid_block_check(block, is_base_block);
1988 if (status == EDID_BLOCK_HEADER_REPAIR) {
e1e7bc48 1989 DRM_DEBUG_KMS("Fixing EDID header, your hardware may be failing\n");
1f221284
JN		 1990 edid_header_fix(block);
1991
1992 /* Retry with fixed header, update status if that worked. */
1993 status = edid_block_check(block, is_base_block);
1994 if (status == EDID_BLOCK_OK)
1995 status = EDID_BLOCK_HEADER_FIXED;
61e57a8d 1996 }
f453ba04 1997
1f221284
JN		 1998 if (edid_corrupt) {
1999 /*
2000 * Unknown major version isn't corrupt but we can't use it. Only
2001 * the base block can reset edid_corrupt to false.
2002 */
2003 if (is_base_block &&
2004 (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION))
2005 *edid_corrupt = false;
2006 else if (status != EDID_BLOCK_OK)
ac6f2e29 2007 *edid_corrupt = true;
f453ba04
DA		 2008 }
2009
cee2ce1a
JN		 2010 edid_block_status_print(status, block, block_num);
2011
1f221284
JN		 2012 /* Determine whether we can use this block with this status. */
2013 valid = edid_block_status_valid(status, edid_block_tag(block));
2014
cee2ce1a
JN		 2015 if (!valid && print_bad_edid && status != EDID_BLOCK_ZERO) {
2016 pr_notice("Raw EDID:\n");
9c7345de 2017 edid_block_dump(KERN_NOTICE, block, block_num);
f453ba04 2018 }
1f221284
JN		 2019
2020 return valid;
f453ba04 2021}
da0df92b 2022EXPORT_SYMBOL(drm_edid_block_valid);
61e57a8d
AJ		 2023
2024/**
2025 * drm_edid_is_valid - sanity check EDID data
2026 * @edid: EDID data
2027 *
2028 * Sanity-check an entire EDID record (including extensions)
db6cf833
TR		 2029 *
2030 * Return: True if the EDID data is valid, false otherwise.
61e57a8d
AJ		 2031 */
2032bool drm_edid_is_valid(struct edid *edid)
2033{
2034 int i;
61e57a8d
AJ		 2035
2036 if (!edid)
2037 return false;
2038
f1e4c916
JN		 2039 for (i = 0; i < edid_block_count(edid); i++) {
2040 void *block = (void *)edid_block_data(edid, i);
2041
2042 if (!drm_edid_block_valid(block, i, true, NULL))
61e57a8d 2043 return false;
f1e4c916 2044 }
61e57a8d
AJ		 2045
2046 return true;
2047}
3c537889 2048EXPORT_SYMBOL(drm_edid_is_valid);
f453ba04 2049
6c9b3db7
JN		 2050/**
2051 * drm_edid_valid - sanity check EDID data
2052 * @drm_edid: EDID data
2053 *
2054 * Sanity check an EDID. Cross check block count against allocated size and
2055 * checksum the blocks.
2056 *
2057 * Return: True if the EDID data is valid, false otherwise.
2058 */
2059bool drm_edid_valid(const struct drm_edid *drm_edid)
2060{
2061 int i;
2062
2063 if (!drm_edid)
2064 return false;
2065
2066 if (edid_size_by_blocks(__drm_edid_block_count(drm_edid)) != drm_edid->size)
2067 return false;
2068
2069 for (i = 0; i < drm_edid_block_count(drm_edid); i++) {
2070 const void *block = drm_edid_block_data(drm_edid, i);
2071
2072 if (!edid_block_valid(block, i == 0))
2073 return false;
2074 }
2075
2076 return true;
2077}
2078EXPORT_SYMBOL(drm_edid_valid);
2079
89f4b4c5 2080static struct edid *edid_filter_invalid_blocks(struct edid *edid,
407d63b3 2081 size_t *alloc_size)
4ec53461 2082{
89f4b4c5
JN		 2083 struct edid *new;
2084 int i, valid_blocks = 0;
4ec53461 2085
18e3c1d5
JN		 2086 /*
2087 * Note: If the EDID uses HF-EEODB, but has invalid blocks, we'll revert
2088 * back to regular extension count here. We don't want to start
2089 * modifying the HF-EEODB extension too.
2090 */
89f4b4c5
JN		 2091 for (i = 0; i < edid_block_count(edid); i++) {
2092 const void *src_block = edid_block_data(edid, i);
407d63b3 2093
89f4b4c5
JN		 2094 if (edid_block_valid(src_block, i == 0)) {
2095 void *dst_block = (void *)edid_block_data(edid, valid_blocks);
4ec53461 2096
89f4b4c5
JN		 2097 memmove(dst_block, src_block, EDID_LENGTH);
2098 valid_blocks++;
2099 }
2100 }
4ec53461 2101
89f4b4c5
JN		 2102 /* We already trusted the base block to be valid here... */
2103 if (WARN_ON(!valid_blocks)) {
2104 kfree(edid);
2105 return NULL;
4ec53461
JN		 2106 }
2107
89f4b4c5
JN		 2108 edid->extensions = valid_blocks - 1;
2109 edid->checksum = edid_block_compute_checksum(edid);
4ec53461 2110
89f4b4c5
JN		 2111 *alloc_size = edid_size_by_blocks(valid_blocks);
2112
2113 new = krealloc(edid, *alloc_size, GFP_KERNEL);
2114 if (!new)
2115 kfree(edid);
4ec53461
JN		 2116
2117 return new;
2118}
2119
61e57a8d
AJ		 2120#define DDC_SEGMENT_ADDR 0x30
2121/**
db6cf833 2122 * drm_do_probe_ddc_edid() - get EDID information via I2C
7c58e87e 2123 * @data: I2C device adapter
fc66811c
DV		 2124 * @buf: EDID data buffer to be filled
2125 * @block: 128 byte EDID block to start fetching from
2126 * @len: EDID data buffer length to fetch
2127 *
db6cf833 2128 * Try to fetch EDID information by calling I2C driver functions.
61e57a8d 2129 *
db6cf833 2130 * Return: 0 on success or -1 on failure.
61e57a8d
AJ		 2131 */
2132static int
18df89fe 2133drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
61e57a8d 2134{
18df89fe 2135 struct i2c_adapter *adapter = data;
61e57a8d 2136 unsigned char start = block * EDID_LENGTH;
cd004b3f
S		 2137 unsigned char segment = block >> 1;
2138 unsigned char xfers = segment ? 3 : 2;
4819d2e4
CW		 2139 int ret, retries = 5;
2140
db6cf833
TR		 2141 /*
2142 * The core I2C driver will automatically retry the transfer if the
4819d2e4
CW		 2143 * adapter reports EAGAIN. However, we find that bit-banging transfers
2144 * are susceptible to errors under a heavily loaded machine and
2145 * generate spurious NAKs and timeouts. Retrying the transfer
2146 * of the individual block a few times seems to overcome this.
2147 */
2148 do {
2149 struct i2c_msg msgs[] = {
2150 {
cd004b3f
S		 2151 .addr = DDC_SEGMENT_ADDR,
2152 .flags = 0,
2153 .len = 1,
2154 .buf = &segment,
2155 }, {
4819d2e4
CW		 2156 .addr = DDC_ADDR,
2157 .flags = 0,
2158 .len = 1,
2159 .buf = &start,
2160 }, {
2161 .addr = DDC_ADDR,
2162 .flags = I2C_M_RD,
2163 .len = len,
2164 .buf = buf,
2165 }
2166 };
cd004b3f 2167
db6cf833
TR		 2168 /*
2169 * Avoid sending the segment addr to not upset non-compliant
2170 * DDC monitors.
2171 */
cd004b3f
S		 2172 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
2173
9292f37e
ED		 2174 if (ret == -ENXIO) {
2175 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
2176 adapter->name);
2177 break;
2178 }
cd004b3f 2179 } while (ret != xfers && --retries);
4819d2e4 2180
cd004b3f 2181 return ret == xfers ? 0 : -1;
61e57a8d
AJ		 2182}
2183
14544d09 2184static void connector_bad_edid(struct drm_connector *connector,
63cae081 2185 const struct edid *edid, int num_blocks)
14544d09
CW		 2186{
2187 int i;
97794170
DA		 2188 u8 last_block;
2189
2190 /*
2191 * 0x7e in the EDID is the number of extension blocks. The EDID
2192 * is 1 (base block) + num_ext_blocks big. That means we can think
2193 * of 0x7e in the EDID of the _index_ of the last block in the
2194 * combined chunk of memory.
2195 */
63cae081 2196 last_block = edid->extensions;
e11f5bd8
JFZ		 2197
2198 /* Calculate real checksum for the last edid extension block data */
97794170
DA		 2199 if (last_block < num_blocks)
2200 connector->real_edid_checksum =
63cae081 2201 edid_block_compute_checksum(edid + last_block);
14544d09 2202
f0a8f533 2203 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
14544d09
CW		 2204 return;
2205
66d17ecd
JN		 2206 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID is invalid:\n",
2207 connector->base.id, connector->name);
63cae081
JN		 2208 for (i = 0; i < num_blocks; i++)
2209 edid_block_dump(KERN_DEBUG, edid + i, i);
14544d09
CW		 2210}
2211
56a2b7f2 2212/* Get override or firmware EDID */
794aca0e 2213static const struct drm_edid *drm_edid_override_get(struct drm_connector *connector)
56a2b7f2 2214{
794aca0e 2215 const struct drm_edid *override = NULL;
56a2b7f2 2216
90b575f5
JN		 2217 mutex_lock(&connector->edid_override_mutex);
2218
2219 if (connector->edid_override)
794aca0e 2220 override = drm_edid_dup(connector->edid_override);
90b575f5
JN		 2221
2222 mutex_unlock(&connector->edid_override_mutex);
56a2b7f2
JN		 2223
2224 if (!override)
a05992d5 2225 override = drm_edid_load_firmware(connector);
56a2b7f2
JN		 2226
2227 return IS_ERR(override) ? NULL : override;
2228}
2229
91ec9ab4
JN		 2230/* For debugfs edid_override implementation */
2231int drm_edid_override_show(struct drm_connector *connector, struct seq_file *m)
2232{
90b575f5 2233 const struct drm_edid *drm_edid;
91ec9ab4 2234
90b575f5
JN		 2235 mutex_lock(&connector->edid_override_mutex);
2236
2237 drm_edid = connector->edid_override;
2238 if (drm_edid)
2239 seq_write(m, drm_edid->edid, drm_edid->size);
2240
2241 mutex_unlock(&connector->edid_override_mutex);
91ec9ab4
JN		 2242
2243 return 0;
2244}
2245
6aa145bc
JN		 2246/* For debugfs edid_override implementation */
2247int drm_edid_override_set(struct drm_connector *connector, const void *edid,
2248 size_t size)
2249{
90b575f5 2250 const struct drm_edid *drm_edid;
6aa145bc 2251
90b575f5
JN		 2252 drm_edid = drm_edid_alloc(edid, size);
2253 if (!drm_edid_valid(drm_edid)) {
2254 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override invalid\n",
2255 connector->base.id, connector->name);
2256 drm_edid_free(drm_edid);
6aa145bc 2257 return -EINVAL;
90b575f5 2258 }
6aa145bc 2259
2c9332de
JN		 2260 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override set\n",
2261 connector->base.id, connector->name);
2262
90b575f5 2263 mutex_lock(&connector->edid_override_mutex);
6aa145bc 2264
90b575f5
JN		 2265 drm_edid_free(connector->edid_override);
2266 connector->edid_override = drm_edid;
2267
2268 mutex_unlock(&connector->edid_override_mutex);
2269
2270 return 0;
6aa145bc
JN		 2271}
2272
2273/* For debugfs edid_override implementation */
2274int drm_edid_override_reset(struct drm_connector *connector)
2275{
2c9332de
JN		 2276 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override reset\n",
2277 connector->base.id, connector->name);
2278
90b575f5
JN		 2279 mutex_lock(&connector->edid_override_mutex);
2280
2281 drm_edid_free(connector->edid_override);
2282 connector->edid_override = NULL;
2283
2284 mutex_unlock(&connector->edid_override_mutex);
2285
2286 return 0;
6aa145bc
JN		 2287}
2288
48eaeb76 2289/**
019b9387 2290 * drm_edid_override_connector_update - add modes from override/firmware EDID
48eaeb76
JN		 2291 * @connector: connector we're probing
2292 *
2293 * Add modes from the override/firmware EDID, if available. Only to be used from
2294 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
2295 * failed during drm_get_edid() and caused the override/firmware EDID to be
2296 * skipped.
2297 *
2298 * Return: The number of modes added or 0 if we couldn't find any.
2299 */
019b9387 2300int drm_edid_override_connector_update(struct drm_connector *connector)
48eaeb76 2301{
794aca0e 2302 const struct drm_edid *override;
48eaeb76
JN		 2303 int num_modes = 0;
2304
794aca0e 2305 override = drm_edid_override_get(connector);
48eaeb76 2306 if (override) {
794aca0e
JN		 2307 num_modes = drm_edid_connector_update(connector, override);
2308
2309 drm_edid_free(override);
48eaeb76 2310
e1e7bc48
JN		 2311 drm_dbg_kms(connector->dev,
2312 "[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
2313 connector->base.id, connector->name, num_modes);
48eaeb76
JN		 2314 }
2315
2316 return num_modes;
2317}
019b9387 2318EXPORT_SYMBOL(drm_edid_override_connector_update);
48eaeb76 2319
89fb7536
JN		 2320typedef int read_block_fn(void *context, u8 *buf, unsigned int block, size_t len);
2321
2deaf1c2
JN		 2322static enum edid_block_status edid_block_read(void *block, unsigned int block_num,
2323 read_block_fn read_block,
2324 void *context)
2325{
2326 enum edid_block_status status;
2327 bool is_base_block = block_num == 0;
2328 int try;
2329
2330 for (try = 0; try < 4; try++) {
2331 if (read_block(context, block, block_num, EDID_LENGTH))
2332 return EDID_BLOCK_READ_FAIL;
2333
2334 status = edid_block_check(block, is_base_block);
2335 if (status == EDID_BLOCK_HEADER_REPAIR) {
2336 edid_header_fix(block);
2337
2338 /* Retry with fixed header, update status if that worked. */
2339 status = edid_block_check(block, is_base_block);
2340 if (status == EDID_BLOCK_OK)
2341 status = EDID_BLOCK_HEADER_FIXED;
2342 }
2343
2344 if (edid_block_status_valid(status, edid_block_tag(block)))
2345 break;
2346
2347 /* Fail early for unrepairable base block all zeros. */
2348 if (try == 0 && is_base_block && status == EDID_BLOCK_ZERO)
2349 break;
2350 }
2351
2352 return status;
2353}
2354
6537f79a
JN		 2355static struct edid *_drm_do_get_edid(struct drm_connector *connector,
2356 read_block_fn read_block, void *context,
2357 size_t *size)
61e57a8d 2358{
c12561ce 2359 enum edid_block_status status;
18e3c1d5 2360 int i, num_blocks, invalid_blocks = 0;
794aca0e 2361 const struct drm_edid *override;
b3eb97b6 2362 struct edid *edid, *new;
407d63b3 2363 size_t alloc_size = EDID_LENGTH;
53fd40a9 2364
794aca0e
JN		 2365 override = drm_edid_override_get(connector);
2366 if (override) {
2367 alloc_size = override->size;
2368 edid = kmemdup(override->edid, alloc_size, GFP_KERNEL);
2369 drm_edid_free(override);
2370 if (!edid)
2371 return NULL;
1c788f69 2372 goto ok;
794aca0e 2373 }
61e57a8d 2374
407d63b3 2375 edid = kmalloc(alloc_size, GFP_KERNEL);
e7bd95a7 2376 if (!edid)
61e57a8d 2377 return NULL;
61e57a8d 2378
c12561ce
JN		 2379 status = edid_block_read(edid, 0, read_block, context);
2380
2381 edid_block_status_print(status, edid, 0);
2382
2383 if (status == EDID_BLOCK_READ_FAIL)
1c788f69 2384 goto fail;
c12561ce
JN		 2385
2386 /* FIXME: Clarify what a corrupt EDID actually means. */
2387 if (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION)
2388 connector->edid_corrupt = false;
2389 else
2390 connector->edid_corrupt = true;
2391
2392 if (!edid_block_status_valid(status, edid_block_tag(edid))) {
2393 if (status == EDID_BLOCK_ZERO)
2394 connector->null_edid_counter++;
2395
2396 connector_bad_edid(connector, edid, 1);
1c788f69 2397 goto fail;
c12561ce
JN		 2398 }
2399
f1e4c916 2400 if (!edid_extension_block_count(edid))
1c788f69 2401 goto ok;
61e57a8d 2402
407d63b3
JN		 2403 alloc_size = edid_size(edid);
2404 new = krealloc(edid, alloc_size, GFP_KERNEL);
61e57a8d 2405 if (!new)
1c788f69 2406 goto fail;
f14f3686 2407 edid = new;
61e57a8d 2408
18e3c1d5
JN		 2409 num_blocks = edid_block_count(edid);
2410 for (i = 1; i < num_blocks; i++) {
f1e4c916 2411 void *block = (void *)edid_block_data(edid, i);
a28187cc 2412
f1e4c916 2413 status = edid_block_read(block, i, read_block, context);
d3da3f40 2414
f1e4c916 2415 edid_block_status_print(status, block, i);
f934ec8c 2416
d3da3f40
JN		 2417 if (!edid_block_status_valid(status, edid_block_tag(block))) {
2418 if (status == EDID_BLOCK_READ_FAIL)
1c788f69 2419 goto fail;
ccc97def 2420 invalid_blocks++;
18e3c1d5
JN		 2421 } else if (i == 1) {
2422 /*
2423 * If the first EDID extension is a CTA extension, and
2424 * the first Data Block is HF-EEODB, override the
2425 * extension block count.
2426 *
2427 * Note: HF-EEODB could specify a smaller extension
2428 * count too, but we can't risk allocating a smaller
2429 * amount.
2430 */
2431 int eeodb = edid_hfeeodb_block_count(edid);
2432
2433 if (eeodb > num_blocks) {
2434 num_blocks = eeodb;
2435 alloc_size = edid_size_by_blocks(num_blocks);
2436 new = krealloc(edid, alloc_size, GFP_KERNEL);
2437 if (!new)
2438 goto fail;
2439 edid = new;
2440 }
d3da3f40 2441 }
0ea75e23
ST		 2442 }
2443
ccc97def 2444 if (invalid_blocks) {
18e3c1d5 2445 connector_bad_edid(connector, edid, num_blocks);
14544d09 2446
89f4b4c5 2447 edid = edid_filter_invalid_blocks(edid, &alloc_size);
61e57a8d
AJ		 2448 }
2449
1c788f69 2450ok:
6537f79a
JN		 2451 if (size)
2452 *size = alloc_size;
2453
e9a9e076 2454 return edid;
61e57a8d 2455
1c788f69 2456fail:
f14f3686 2457 kfree(edid);
61e57a8d
AJ		 2458 return NULL;
2459}
6537f79a
JN		 2460
2461/**
2462 * drm_do_get_edid - get EDID data using a custom EDID block read function
2463 * @connector: connector we're probing
2464 * @read_block: EDID block read function
2465 * @context: private data passed to the block read function
2466 *
2467 * When the I2C adapter connected to the DDC bus is hidden behind a device that
2468 * exposes a different interface to read EDID blocks this function can be used
2469 * to get EDID data using a custom block read function.
2470 *
2471 * As in the general case the DDC bus is accessible by the kernel at the I2C
2472 * level, drivers must make all reasonable efforts to expose it as an I2C
2473 * adapter and use drm_get_edid() instead of abusing this function.
2474 *
2475 * The EDID may be overridden using debugfs override_edid or firmware EDID
a05992d5 2476 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
6537f79a
JN		 2477 * order. Having either of them bypasses actual EDID reads.
2478 *
2479 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2480 */
2481struct edid *drm_do_get_edid(struct drm_connector *connector,
2482 read_block_fn read_block,
2483 void *context)
2484{
2485 return _drm_do_get_edid(connector, read_block, context, NULL);
2486}
18df89fe 2487EXPORT_SYMBOL_GPL(drm_do_get_edid);
61e57a8d 2488
3d1ab66e
JN		 2489/**
2490 * drm_edid_raw - Get a pointer to the raw EDID data.
2491 * @drm_edid: drm_edid container
2492 *
2493 * Get a pointer to the raw EDID data.
2494 *
2495 * This is for transition only. Avoid using this like the plague.
2496 *
2497 * Return: Pointer to raw EDID data.
2498 */
2499const struct edid *drm_edid_raw(const struct drm_edid *drm_edid)
2500{
2501 if (!drm_edid || !drm_edid->size)
2502 return NULL;
2503
2504 /*
2505 * Do not return pointers where relying on EDID extension count would
2506 * lead to buffer overflow.
2507 */
2508 if (WARN_ON(edid_size(drm_edid->edid) > drm_edid->size))
2509 return NULL;
2510
2511 return drm_edid->edid;
2512}
2513EXPORT_SYMBOL(drm_edid_raw);
2514
6537f79a
JN		 2515/* Allocate struct drm_edid container *without* duplicating the edid data */
2516static const struct drm_edid *_drm_edid_alloc(const void *edid, size_t size)
2517{
2518 struct drm_edid *drm_edid;
2519
2520 if (!edid || !size || size < EDID_LENGTH)
2521 return NULL;
2522
2523 drm_edid = kzalloc(sizeof(*drm_edid), GFP_KERNEL);
2524 if (drm_edid) {
2525 drm_edid->edid = edid;
2526 drm_edid->size = size;
2527 }
2528
2529 return drm_edid;
2530}
2531
2532/**
2533 * drm_edid_alloc - Allocate a new drm_edid container
2534 * @edid: Pointer to raw EDID data
2535 * @size: Size of memory allocated for EDID
2536 *
2537 * Allocate a new drm_edid container. Do not calculate edid size from edid, pass
2538 * the actual size that has been allocated for the data. There is no validation
2539 * of the raw EDID data against the size, but at least the EDID base block must
2540 * fit in the buffer.
2541 *
2542 * The returned pointer must be freed using drm_edid_free().
2543 *
2544 * Return: drm_edid container, or NULL on errors
2545 */
2546const struct drm_edid *drm_edid_alloc(const void *edid, size_t size)
2547{
2548 const struct drm_edid *drm_edid;
2549
2550 if (!edid || !size || size < EDID_LENGTH)
2551 return NULL;
2552
2553 edid = kmemdup(edid, size, GFP_KERNEL);
2554 if (!edid)
2555 return NULL;
2556
2557 drm_edid = _drm_edid_alloc(edid, size);
2558 if (!drm_edid)
2559 kfree(edid);
2560
2561 return drm_edid;
2562}
2563EXPORT_SYMBOL(drm_edid_alloc);
2564
2565/**
2566 * drm_edid_dup - Duplicate a drm_edid container
2567 * @drm_edid: EDID to duplicate
2568 *
2569 * The returned pointer must be freed using drm_edid_free().
2570 *
2571 * Returns: drm_edid container copy, or NULL on errors
2572 */
2573const struct drm_edid *drm_edid_dup(const struct drm_edid *drm_edid)
2574{
2575 if (!drm_edid)
2576 return NULL;
2577
2578 return drm_edid_alloc(drm_edid->edid, drm_edid->size);
2579}
2580EXPORT_SYMBOL(drm_edid_dup);
2581
2582/**
2583 * drm_edid_free - Free the drm_edid container
2584 * @drm_edid: EDID to free
2585 */
2586void drm_edid_free(const struct drm_edid *drm_edid)
2587{
2588 if (!drm_edid)
2589 return;
2590
2591 kfree(drm_edid->edid);
2592 kfree(drm_edid);
2593}
2594EXPORT_SYMBOL(drm_edid_free);
2595
61e57a8d 2596/**
db6cf833
TR		 2597 * drm_probe_ddc() - probe DDC presence
2598 * @adapter: I2C adapter to probe
fc66811c 2599 *
db6cf833 2600 * Return: True on success, false on failure.
61e57a8d 2601 */
fbff4690 2602bool
61e57a8d
AJ		 2603drm_probe_ddc(struct i2c_adapter *adapter)
2604{
2605 unsigned char out;
2606
2607 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
2608}
fbff4690 2609EXPORT_SYMBOL(drm_probe_ddc);
61e57a8d
AJ		 2610
2611/**
2612 * drm_get_edid - get EDID data, if available
2613 * @connector: connector we're probing
db6cf833 2614 * @adapter: I2C adapter to use for DDC
61e57a8d 2615 *
db6cf833 2616 * Poke the given I2C channel to grab EDID data if possible. If found,
61e57a8d
AJ		 2617 * attach it to the connector.
2618 *
db6cf833 2619 * Return: Pointer to valid EDID or NULL if we couldn't find any.
61e57a8d
AJ		 2620 */
2621struct edid *drm_get_edid(struct drm_connector *connector,
2622 struct i2c_adapter *adapter)
2623{
5186421c
SL		 2624 struct edid *edid;
2625
15f080f0
JN		 2626 if (connector->force == DRM_FORCE_OFF)
2627 return NULL;
2628
2629 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
18df89fe 2630 return NULL;
61e57a8d 2631
6537f79a 2632 edid = _drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter, NULL);
5186421c
SL		 2633 drm_connector_update_edid_property(connector, edid);
2634 return edid;
61e57a8d
AJ		 2635}
2636EXPORT_SYMBOL(drm_get_edid);
2637
6537f79a
JN		 2638/**
2639 * drm_edid_read_custom - Read EDID data using given EDID block read function
2640 * @connector: Connector to use
2641 * @read_block: EDID block read function
2642 * @context: Private data passed to the block read function
2643 *
2644 * When the I2C adapter connected to the DDC bus is hidden behind a device that
2645 * exposes a different interface to read EDID blocks this function can be used
2646 * to get EDID data using a custom block read function.
2647 *
2648 * As in the general case the DDC bus is accessible by the kernel at the I2C
2649 * level, drivers must make all reasonable efforts to expose it as an I2C
2650 * adapter and use drm_edid_read() or drm_edid_read_ddc() instead of abusing
2651 * this function.
2652 *
2653 * The EDID may be overridden using debugfs override_edid or firmware EDID
a05992d5 2654 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
6537f79a
JN		 2655 * order. Having either of them bypasses actual EDID reads.
2656 *
2657 * The returned pointer must be freed using drm_edid_free().
2658 *
2659 * Return: Pointer to EDID, or NULL if probe/read failed.
2660 */
2661const struct drm_edid *drm_edid_read_custom(struct drm_connector *connector,
2662 read_block_fn read_block,
2663 void *context)
2664{
2665 const struct drm_edid *drm_edid;
2666 struct edid *edid;
2667 size_t size = 0;
2668
2669 edid = _drm_do_get_edid(connector, read_block, context, &size);
2670 if (!edid)
2671 return NULL;
2672
2673 /* Sanity check for now */
2674 drm_WARN_ON(connector->dev, !size);
2675
2676 drm_edid = _drm_edid_alloc(edid, size);
2677 if (!drm_edid)
2678 kfree(edid);
2679
2680 return drm_edid;
2681}
2682EXPORT_SYMBOL(drm_edid_read_custom);
2683
2684/**
2685 * drm_edid_read_ddc - Read EDID data using given I2C adapter
2686 * @connector: Connector to use
2687 * @adapter: I2C adapter to use for DDC
2688 *
2689 * Read EDID using the given I2C adapter.
2690 *
2691 * The EDID may be overridden using debugfs override_edid or firmware EDID
a05992d5 2692 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
6537f79a
JN		 2693 * order. Having either of them bypasses actual EDID reads.
2694 *
2695 * Prefer initializing connector->ddc with drm_connector_init_with_ddc() and
2696 * using drm_edid_read() instead of this function.
2697 *
2698 * The returned pointer must be freed using drm_edid_free().
2699 *
2700 * Return: Pointer to EDID, or NULL if probe/read failed.
2701 */
2702const struct drm_edid *drm_edid_read_ddc(struct drm_connector *connector,
2703 struct i2c_adapter *adapter)
2704{
2705 const struct drm_edid *drm_edid;
2706
2707 if (connector->force == DRM_FORCE_OFF)
2708 return NULL;
2709
2710 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2711 return NULL;
2712
2713 drm_edid = drm_edid_read_custom(connector, drm_do_probe_ddc_edid, adapter);
2714
2715 /* Note: Do *not* call connector updates here. */
2716
2717 return drm_edid;
2718}
2719EXPORT_SYMBOL(drm_edid_read_ddc);
2720
2721/**
2722 * drm_edid_read - Read EDID data using connector's I2C adapter
2723 * @connector: Connector to use
2724 *
2725 * Read EDID using the connector's I2C adapter.
2726 *
2727 * The EDID may be overridden using debugfs override_edid or firmware EDID
a05992d5 2728 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
6537f79a
JN		 2729 * order. Having either of them bypasses actual EDID reads.
2730 *
2731 * The returned pointer must be freed using drm_edid_free().
2732 *
2733 * Return: Pointer to EDID, or NULL if probe/read failed.
2734 */
2735const struct drm_edid *drm_edid_read(struct drm_connector *connector)
2736{
2737 if (drm_WARN_ON(connector->dev, !connector->ddc))
2738 return NULL;
2739
2740 return drm_edid_read_ddc(connector, connector->ddc);
2741}
2742EXPORT_SYMBOL(drm_edid_read);
2743
d9f91a10
DA		 2744static u32 edid_extract_panel_id(const struct edid *edid)
2745{
2746 /*
e8de4d55
DA		 2747 * We represent the ID as a 32-bit number so it can easily be compared
2748 * with "==".
d9f91a10
DA		 2749 *
2750 * NOTE that we deal with endianness differently for the top half
2751 * of this ID than for the bottom half. The bottom half (the product
2752 * id) gets decoded as little endian by the EDID_PRODUCT_ID because
2753 * that's how everyone seems to interpret it. The top half (the mfg_id)
2754 * gets stored as big endian because that makes
2755 * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier
2756 * to write (it's easier to extract the ASCII). It doesn't really
2757 * matter, though, as long as the number here is unique.
2758 */
2759 return (u32)edid->mfg_id[0] << 24 |
2760 (u32)edid->mfg_id[1] << 16 |
2761 (u32)EDID_PRODUCT_ID(edid);
2762}
2763
2764/**
2765 * drm_edid_get_panel_id - Get a panel's ID through DDC
2766 * @adapter: I2C adapter to use for DDC
2767 *
2768 * This function reads the first block of the EDID of a panel and (assuming
2769 * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value
2770 * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's
2771 * supposed to be different for each different modem of panel.
2772 *
2773 * This function is intended to be used during early probing on devices where
2774 * more than one panel might be present. Because of its intended use it must
2775 * assume that the EDID of the panel is correct, at least as far as the ID
2776 * is concerned (in other words, we don't process any overrides here).
2777 *
2778 * NOTE: it's expected that this function and drm_do_get_edid() will both
2779 * be read the EDID, but there is no caching between them. Since we're only
2780 * reading the first block, hopefully this extra overhead won't be too big.
2781 *
2782 * Return: A 32-bit ID that should be different for each make/model of panel.
2783 * See the functions drm_edid_encode_panel_id() and
2784 * drm_edid_decode_panel_id() for some details on the structure of this
2785 * ID.
2786 */
2787
2788u32 drm_edid_get_panel_id(struct i2c_adapter *adapter)
2789{
2deaf1c2
JN		 2790 enum edid_block_status status;
2791 void *base_block;
2792 u32 panel_id = 0;
d9f91a10
DA		 2793
2794 /*
2795 * There are no manufacturer IDs of 0, so if there is a problem reading
2796 * the EDID then we'll just return 0.
2797 */
2deaf1c2
JN		 2798
2799 base_block = kmalloc(EDID_LENGTH, GFP_KERNEL);
2800 if (!base_block)
d9f91a10
DA		 2801 return 0;
2802
2deaf1c2
JN		 2803 status = edid_block_read(base_block, 0, drm_do_probe_ddc_edid, adapter);
2804
2805 edid_block_status_print(status, base_block, 0);
2806
2807 if (edid_block_status_valid(status, edid_block_tag(base_block)))
2808 panel_id = edid_extract_panel_id(base_block);
69c7717c
DA		 2809 else
2810 edid_block_dump(KERN_NOTICE, base_block, 0);
2deaf1c2
JN		 2811
2812 kfree(base_block);
d9f91a10
DA		 2813
2814 return panel_id;
2815}
2816EXPORT_SYMBOL(drm_edid_get_panel_id);
2817
5cb8eaa2
LW		 2818/**
2819 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
2820 * @connector: connector we're probing
2821 * @adapter: I2C adapter to use for DDC
2822 *
2823 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
2824 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
2825 * switch DDC to the GPU which is retrieving EDID.
2826 *
2827 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2828 */
2829struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
2830 struct i2c_adapter *adapter)
2831{
36b73b05
TZ		 2832 struct drm_device *dev = connector->dev;
2833 struct pci_dev *pdev = to_pci_dev(dev->dev);
5cb8eaa2
LW		 2834 struct edid *edid;
2835
36b73b05
TZ		 2836 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev)))
2837 return NULL;
2838
5cb8eaa2
LW		 2839 vga_switcheroo_lock_ddc(pdev);
2840 edid = drm_get_edid(connector, adapter);
2841 vga_switcheroo_unlock_ddc(pdev);
2842
2843 return edid;
2844}
2845EXPORT_SYMBOL(drm_get_edid_switcheroo);
2846
51f8da59
JN		 2847/**
2848 * drm_edid_duplicate - duplicate an EDID and the extensions
2849 * @edid: EDID to duplicate
2850 *
db6cf833 2851 * Return: Pointer to duplicated EDID or NULL on allocation failure.
51f8da59
JN		 2852 */
2853struct edid *drm_edid_duplicate(const struct edid *edid)
2854{
f1e4c916 2855 return kmemdup(edid, edid_size(edid), GFP_KERNEL);
51f8da59
JN		 2856}
2857EXPORT_SYMBOL(drm_edid_duplicate);
2858
61e57a8d
AJ		 2859/*** EDID parsing ***/
2860
f453ba04
DA		 2861/**
2862 * edid_get_quirks - return quirk flags for a given EDID
e42192b4 2863 * @drm_edid: EDID to process
f453ba04
DA		 2864 *
2865 * This tells subsequent routines what fixes they need to apply.
2866 */
e42192b4 2867static u32 edid_get_quirks(const struct drm_edid *drm_edid)
f453ba04 2868{
e42192b4 2869 u32 panel_id = edid_extract_panel_id(drm_edid->edid);
23c4cfbd 2870 const struct edid_quirk *quirk;
f453ba04
DA		 2871 int i;
2872
2873 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
2874 quirk = &edid_quirk_list[i];
e8de4d55 2875 if (quirk->panel_id == panel_id)
f453ba04
DA		 2876 return quirk->quirks;
2877 }
2878
2879 return 0;
2880}
2881
2882#define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
339d202c 2883#define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
f453ba04 2884
17edb8e1
JN		 2885/*
2886 * Walk the mode list for connector, clearing the preferred status on existing
2887 * modes and setting it anew for the right mode ala quirks.
f453ba04 2888 */
4959b693 2889static void edid_fixup_preferred(struct drm_connector *connector)
f453ba04 2890{
4959b693 2891 const struct drm_display_info *info = &connector->display_info;
f453ba04 2892 struct drm_display_mode *t, *cur_mode, *preferred_mode;
f890607b 2893 int target_refresh = 0;
339d202c 2894 int cur_vrefresh, preferred_vrefresh;
f453ba04
DA		 2895
2896 if (list_empty(&connector->probed_modes))
2897 return;
2898
4959b693 2899 if (info->quirks & EDID_QUIRK_PREFER_LARGE_60)
f453ba04 2900 target_refresh = 60;
4959b693 2901 if (info->quirks & EDID_QUIRK_PREFER_LARGE_75)
f453ba04
DA		 2902 target_refresh = 75;
2903
2904 preferred_mode = list_first_entry(&connector->probed_modes,
2905 struct drm_display_mode, head);
2906
2907 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
2908 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
2909
2910 if (cur_mode == preferred_mode)
2911 continue;
2912
2913 /* Largest mode is preferred */
2914 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
2915 preferred_mode = cur_mode;
2916
0425662f
VS		 2917 cur_vrefresh = drm_mode_vrefresh(cur_mode);
2918 preferred_vrefresh = drm_mode_vrefresh(preferred_mode);
f453ba04
DA		 2919 /* At a given size, try to get closest to target refresh */
2920 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
339d202c
AD		 2921 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
2922 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
f453ba04
DA		 2923 preferred_mode = cur_mode;
2924 }
2925 }
2926
2927 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
2928}
2929
f6e252ba
AJ		 2930static bool
2931mode_is_rb(const struct drm_display_mode *mode)
2932{
2933 return (mode->htotal - mode->hdisplay == 160) &&
2934 (mode->hsync_end - mode->hdisplay == 80) &&
2935 (mode->hsync_end - mode->hsync_start == 32) &&
2936 (mode->vsync_start - mode->vdisplay == 3);
2937}
2938
33c7531d
AJ		 2939/*
2940 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
2941 * @dev: Device to duplicate against
2942 * @hsize: Mode width
2943 * @vsize: Mode height
2944 * @fresh: Mode refresh rate
f6e252ba 2945 * @rb: Mode reduced-blanking-ness
33c7531d
AJ		 2946 *
2947 * Walk the DMT mode list looking for a match for the given parameters.
db6cf833
TR		 2948 *
2949 * Return: A newly allocated copy of the mode, or NULL if not found.
33c7531d 2950 */
1d42bbc8 2951struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
f6e252ba
AJ		 2952 int hsize, int vsize, int fresh,
2953 bool rb)
559ee21d 2954{
07a5e632 2955 int i;
559ee21d 2956
a6b21831 2957 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
b1f559ec 2958 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
948de842 2959
f8b46a05
AJ		 2960 if (hsize != ptr->hdisplay)
2961 continue;
2962 if (vsize != ptr->vdisplay)
2963 continue;
2964 if (fresh != drm_mode_vrefresh(ptr))
2965 continue;
f6e252ba
AJ		 2966 if (rb != mode_is_rb(ptr))
2967 continue;
f8b46a05
AJ		 2968
2969 return drm_mode_duplicate(dev, ptr);
559ee21d 2970 }
f8b46a05
AJ		 2971
2972 return NULL;
559ee21d 2973}
1d42bbc8 2974EXPORT_SYMBOL(drm_mode_find_dmt);
23425cae 2975
e379814b 2976static bool is_display_descriptor(const struct detailed_timing *descriptor, u8 type)
a7a131ac 2977{
e379814b
JN		 2978 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
2979 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.pad1) != 2);
2980 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.type) != 3);
2981
2982 return descriptor->pixel_clock == 0 &&
2983 descriptor->data.other_data.pad1 == 0 &&
2984 descriptor->data.other_data.type == type;
a7a131ac
VS		 2985}
2986
a9b1f15f 2987static bool is_detailed_timing_descriptor(const struct detailed_timing *descriptor)
f447dd1f 2988{
a9b1f15f
JN		 2989 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
2990
2991 return descriptor->pixel_clock != 0;
f447dd1f
VS		 2992}
2993
4194442d 2994typedef void detailed_cb(const struct detailed_timing *timing, void *closure);
d1ff6409 2995
4d76a221 2996static void
eed628f1 2997cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
4d76a221 2998{
7304b981 2999 int i, n;
4966b2a9 3000 u8 d = ext[0x02];
eed628f1 3001 const u8 *det_base = ext + d;
4d76a221 3002
7304b981
VS		 3003 if (d < 4 || d > 127)
3004 return;
3005
4966b2a9 3006 n = (127 - d) / 18;
4d76a221 3007 for (i = 0; i < n; i++)
eed628f1 3008 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
4d76a221
AJ		 3009}
3010
cbba98f8 3011static void
eed628f1 3012vtb_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
cbba98f8
AJ		 3013{
3014 unsigned int i, n = min((int)ext[0x02], 6);
eed628f1 3015 const u8 *det_base = ext + 5;
cbba98f8
AJ		 3016
3017 if (ext[0x01] != 1)
3018 return; /* unknown version */
3019
3020 for (i = 0; i < n; i++)
eed628f1 3021 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
cbba98f8
AJ		 3022}
3023
45aa2336
JN		 3024static void drm_for_each_detailed_block(const struct drm_edid *drm_edid,
3025 detailed_cb *cb, void *closure)
d1ff6409 3026{
ab1747cc
JN		 3027 struct drm_edid_iter edid_iter;
3028 const u8 *ext;
d1ff6409 3029 int i;
d1ff6409 3030
45aa2336 3031 if (!drm_edid)
d1ff6409
AJ		 3032 return;
3033
3034 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
45aa2336 3035 cb(&drm_edid->edid->detailed_timings[i], closure);
d1ff6409 3036
bbded689 3037 drm_edid_iter_begin(drm_edid, &edid_iter);
ab1747cc 3038 drm_edid_iter_for_each(ext, &edid_iter) {
4d76a221
AJ		 3039 switch (*ext) {
3040 case CEA_EXT:
3041 cea_for_each_detailed_block(ext, cb, closure);
3042 break;
cbba98f8
AJ		 3043 case VTB_EXT:
3044 vtb_for_each_detailed_block(ext, cb, closure);
3045 break;
4d76a221
AJ		 3046 default:
3047 break;
3048 }
3049 }
ab1747cc 3050 drm_edid_iter_end(&edid_iter);
d1ff6409
AJ		 3051}
3052
3053static void
4194442d 3054is_rb(const struct detailed_timing *descriptor, void *data)
d1ff6409 3055{
90fd588f 3056 bool *res = data;
a7a131ac 3057
90fd588f 3058 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
a7a131ac
VS		 3059 return;
3060
90fd588f
JN		 3061 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3062 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.cvt.flags) != 15);
3063
3064 if (descriptor->data.other_data.data.range.flags == DRM_EDID_CVT_SUPPORT_FLAG &&
afd4429e 3065 descriptor->data.other_data.data.range.formula.cvt.flags & DRM_EDID_CVT_FLAGS_REDUCED_BLANKING)
90fd588f 3066 *res = true;
d1ff6409
AJ		 3067}
3068
3069/* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
3070static bool
874d98ee 3071drm_monitor_supports_rb(const struct drm_edid *drm_edid)
d1ff6409 3072{
874d98ee 3073 if (drm_edid->edid->revision >= 4) {
b196a498 3074 bool ret = false;
948de842 3075
45aa2336 3076 drm_for_each_detailed_block(drm_edid, is_rb, &ret);
d1ff6409
AJ		 3077 return ret;
3078 }
3079
874d98ee 3080 return ((drm_edid->edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
d1ff6409
AJ		 3081}
3082
7a374350 3083static void
4194442d 3084find_gtf2(const struct detailed_timing *descriptor, void *data)
7a374350 3085{
4194442d 3086 const struct detailed_timing **res = data;
a7a131ac 3087
c8a4beba 3088 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
a7a131ac
VS		 3089 return;
3090
c8a4beba
JN		 3091 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3092
afd4429e 3093 if (descriptor->data.other_data.data.range.flags == DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG)
c8a4beba 3094 *res = descriptor;
7a374350
AJ		 3095}
3096
3097/* Secondary GTF curve kicks in above some break frequency */
3098static int
67d87fac 3099drm_gtf2_hbreak(const struct drm_edid *drm_edid)
7a374350 3100{
4194442d 3101 const struct detailed_timing *descriptor = NULL;
c8a4beba 3102
45aa2336 3103 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
948de842 3104
c8a4beba
JN		 3105 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12);
3106
3107 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.hfreq_start_khz * 2 : 0;
7a374350
AJ		 3108}
3109
3110static int
67d87fac 3111drm_gtf2_2c(const struct drm_edid *drm_edid)
7a374350 3112{
4194442d 3113 const struct detailed_timing *descriptor = NULL;
c8a4beba 3114
45aa2336 3115 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
c8a4beba
JN		 3116
3117 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.c) != 13);
948de842 3118
c8a4beba 3119 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.c : 0;
7a374350
AJ		 3120}
3121
3122static int
67d87fac 3123drm_gtf2_m(const struct drm_edid *drm_edid)
7a374350 3124{
4194442d 3125 const struct detailed_timing *descriptor = NULL;
948de842 3126
45aa2336 3127 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
c8a4beba
JN		 3128
3129 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.m) != 14);
3130
3131 return descriptor ? le16_to_cpu(descriptor->data.other_data.data.range.formula.gtf2.m) : 0;
7a374350
AJ		 3132}
3133
3134static int
67d87fac 3135drm_gtf2_k(const struct drm_edid *drm_edid)
7a374350 3136{
4194442d 3137 const struct detailed_timing *descriptor = NULL;
c8a4beba 3138
45aa2336 3139 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
948de842 3140
c8a4beba
JN		 3141 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.k) != 16);
3142
3143 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.k : 0;
7a374350
AJ		 3144}
3145
3146static int
67d87fac 3147drm_gtf2_2j(const struct drm_edid *drm_edid)
7a374350 3148{
4194442d 3149 const struct detailed_timing *descriptor = NULL;
c8a4beba 3150
45aa2336 3151 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
c8a4beba
JN		 3152
3153 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.j) != 17);
948de842 3154
c8a4beba 3155 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.j : 0;
7a374350
AJ		 3156}
3157
bf72b5ef
VS		 3158static void
3159get_timing_level(const struct detailed_timing *descriptor, void *data)
3160{
3161 int *res = data;
3162
3163 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3164 return;
3165
3166 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3167
3168 switch (descriptor->data.other_data.data.range.flags) {
3169 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG:
3170 *res = LEVEL_GTF;
3171 break;
3172 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG:
3173 *res = LEVEL_GTF2;
3174 break;
3175 case DRM_EDID_CVT_SUPPORT_FLAG:
3176 *res = LEVEL_CVT;
3177 break;
3178 default:
3179 break;
3180 }
3181}
3182
17edb8e1 3183/* Get standard timing level (CVT/GTF/DMT). */
67d87fac 3184static int standard_timing_level(const struct drm_edid *drm_edid)
7a374350 3185{
67d87fac
JN		 3186 const struct edid *edid = drm_edid->edid;
3187
bf72b5ef
VS		 3188 if (edid->revision >= 4) {
3189 /*
3190 * If the range descriptor doesn't
3191 * indicate otherwise default to CVT
3192 */
3193 int ret = LEVEL_CVT;
3194
3195 drm_for_each_detailed_block(drm_edid, get_timing_level, &ret);
3196
3197 return ret;
3198 } else if (edid->revision >= 3 && drm_gtf2_hbreak(drm_edid)) {
3199 return LEVEL_GTF2;
3200 } else if (edid->revision >= 2) {
3201 return LEVEL_GTF;
3202 } else {
3203 return LEVEL_DMT;
7a374350 3204 }
7a374350
AJ		 3205}
3206
23425cae
AJ		 3207/*
3208 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
3209 * monitors fill with ascii space (0x20) instead.
3210 */
3211static int
3212bad_std_timing(u8 a, u8 b)
3213{
3214 return (a == 0x00 && b == 0x00) ||
3215 (a == 0x01 && b == 0x01) ||
3216 (a == 0x20 && b == 0x20);
3217}
3218
58911c24
VS		 3219static int drm_mode_hsync(const struct drm_display_mode *mode)
3220{
3221 if (mode->htotal <= 0)
3222 return 0;
3223
3224 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal);
3225}
3226
86101bb7
VS		 3227static struct drm_display_mode *
3228drm_gtf2_mode(struct drm_device *dev,
3229 const struct drm_edid *drm_edid,
3230 int hsize, int vsize, int vrefresh_rate)
3231{
3232 struct drm_display_mode *mode;
3233
3234 /*
3235 * This is potentially wrong if there's ever a monitor with
3236 * more than one ranges section, each claiming a different
3237 * secondary GTF curve. Please don't do that.
3238 */
3239 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
3240 if (!mode)
3241 return NULL;
3242
3243 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(drm_edid)) {
3244 drm_mode_destroy(dev, mode);
3245 mode = drm_gtf_mode_complex(dev, hsize, vsize,
3246 vrefresh_rate, 0, 0,
3247 drm_gtf2_m(drm_edid),
3248 drm_gtf2_2c(drm_edid),
3249 drm_gtf2_k(drm_edid),
3250 drm_gtf2_2j(drm_edid));
3251 }
3252
3253 return mode;
3254}
3255
17edb8e1 3256/*
f453ba04 3257 * Take the standard timing params (in this case width, aspect, and refresh)
5c61259e 3258 * and convert them into a real mode using CVT/GTF/DMT.
f453ba04 3259 */
67d87fac
JN		 3260static struct drm_display_mode *drm_mode_std(struct drm_connector *connector,
3261 const struct drm_edid *drm_edid,
3262 const struct std_timing *t)
f453ba04 3263{
7ca6adb3
AJ		 3264 struct drm_device *dev = connector->dev;
3265 struct drm_display_mode *m, *mode = NULL;
5c61259e
ZY		 3266 int hsize, vsize;
3267 int vrefresh_rate;
0454beab
MD		 3268 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
3269 >> EDID_TIMING_ASPECT_SHIFT;
5c61259e
ZY		 3270 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
3271 >> EDID_TIMING_VFREQ_SHIFT;
67d87fac 3272 int timing_level = standard_timing_level(drm_edid);
5c61259e 3273
23425cae
AJ		 3274 if (bad_std_timing(t->hsize, t->vfreq_aspect))
3275 return NULL;
3276
5c61259e
ZY		 3277 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
3278 hsize = t->hsize * 8 + 248;
3279 /* vrefresh_rate = vfreq + 60 */
3280 vrefresh_rate = vfreq + 60;
3281 /* the vdisplay is calculated based on the aspect ratio */
f066a17d 3282 if (aspect_ratio == 0) {
67d87fac 3283 if (drm_edid->edid->revision < 3)
f066a17d
AJ		 3284 vsize = hsize;
3285 else
3286 vsize = (hsize * 10) / 16;
3287 } else if (aspect_ratio == 1)
f453ba04 3288 vsize = (hsize * 3) / 4;
0454beab 3289 else if (aspect_ratio == 2)
f453ba04
DA		 3290 vsize = (hsize * 4) / 5;
3291 else
3292 vsize = (hsize * 9) / 16;
a0910c8e
AJ		 3293
3294 /* HDTV hack, part 1 */
3295 if (vrefresh_rate == 60 &&
3296 ((hsize == 1360 && vsize == 765) ||
3297 (hsize == 1368 && vsize == 769))) {
3298 hsize = 1366;
3299 vsize = 768;
3300 }
3301
7ca6adb3
AJ		 3302 /*
3303 * If this connector already has a mode for this size and refresh
3304 * rate (because it came from detailed or CVT info), use that
3305 * instead. This way we don't have to guess at interlace or
3306 * reduced blanking.
3307 */
522032da 3308 list_for_each_entry(m, &connector->probed_modes, head)
7ca6adb3
AJ		 3309 if (m->hdisplay == hsize && m->vdisplay == vsize &&
3310 drm_mode_vrefresh(m) == vrefresh_rate)
3311 return NULL;
3312
a0910c8e
AJ		 3313 /* HDTV hack, part 2 */
3314 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
3315 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
d50ba256 3316 false);
a5ef6567
JM		 3317 if (!mode)
3318 return NULL;
559ee21d 3319 mode->hdisplay = 1366;
a4967de6
AJ		 3320 mode->hsync_start = mode->hsync_start - 1;
3321 mode->hsync_end = mode->hsync_end - 1;
559ee21d
ZY		 3322 return mode;
3323 }
a0910c8e 3324
559ee21d 3325 /* check whether it can be found in default mode table */
874d98ee 3326 if (drm_monitor_supports_rb(drm_edid)) {
f6e252ba
AJ		 3327 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
3328 true);
3329 if (mode)
3330 return mode;
3331 }
3332 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
559ee21d
ZY		 3333 if (mode)
3334 return mode;
3335
f6e252ba 3336 /* okay, generate it */
5c61259e
ZY		 3337 switch (timing_level) {
3338 case LEVEL_DMT:
5c61259e
ZY		 3339 break;
3340 case LEVEL_GTF:
3341 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
3342 break;
7a374350 3343 case LEVEL_GTF2:
86101bb7 3344 mode = drm_gtf2_mode(dev, drm_edid, hsize, vsize, vrefresh_rate);
7a374350 3345 break;
5c61259e 3346 case LEVEL_CVT:
d50ba256
DA		 3347 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
3348 false);
5c61259e
ZY		 3349 break;
3350 }
f453ba04
DA		 3351 return mode;
3352}
3353
b58db2c6
AJ		 3354/*
3355 * EDID is delightfully ambiguous about how interlaced modes are to be
3356 * encoded. Our internal representation is of frame height, but some
3357 * HDTV detailed timings are encoded as field height.
3358 *
3359 * The format list here is from CEA, in frame size. Technically we
3360 * should be checking refresh rate too. Whatever.
3361 */
3362static void
3363drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
fcfb2ea1 3364 const struct detailed_pixel_timing *pt)
b58db2c6
AJ		 3365{
3366 int i;
3367 static const struct {
3368 int w, h;
3369 } cea_interlaced[] = {
3370 { 1920, 1080 },
3371 { 720, 480 },
3372 { 1440, 480 },
3373 { 2880, 480 },
3374 { 720, 576 },
3375 { 1440, 576 },
3376 { 2880, 576 },
3377 };
b58db2c6
AJ		 3378
3379 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
3380 return;
3381
3c581411 3382 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
b58db2c6
AJ		 3383 if ((mode->hdisplay == cea_interlaced[i].w) &&
3384 (mode->vdisplay == cea_interlaced[i].h / 2)) {
3385 mode->vdisplay *= 2;
3386 mode->vsync_start *= 2;
3387 mode->vsync_end *= 2;
3388 mode->vtotal *= 2;
3389 mode->vtotal |= 1;
3390 }
3391 }
3392
3393 mode->flags |= DRM_MODE_FLAG_INTERLACE;
3394}
3395
17edb8e1
JN		 3396/*
3397 * Create a new mode from an EDID detailed timing section. An EDID detailed
3398 * timing block contains enough info for us to create and return a new struct
3399 * drm_display_mode.
f453ba04 3400 */
e1e7bc48 3401static struct drm_display_mode *drm_mode_detailed(struct drm_connector *connector,
f0d080ff 3402 const struct drm_edid *drm_edid,
4959b693 3403 const struct detailed_timing *timing)
f453ba04 3404{
4959b693 3405 const struct drm_display_info *info = &connector->display_info;
e1e7bc48 3406 struct drm_device *dev = connector->dev;
f453ba04 3407 struct drm_display_mode *mode;
fcfb2ea1 3408 const struct detailed_pixel_timing *pt = &timing->data.pixel_data;
0454beab
MD		 3409 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
3410 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
3411 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
3412 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
e14cbee4
MD		 3413 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
3414 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
16dad1d7 3415 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
e14cbee4 3416 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
f453ba04 3417
fc438966 3418 /* ignore tiny modes */
0454beab 3419 if (hactive < 64 || vactive < 64)
fc438966
AJ		 3420 return NULL;
3421
0454beab 3422 if (pt->misc & DRM_EDID_PT_STEREO) {
e1e7bc48
JN		 3423 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Stereo mode not supported\n",
3424 connector->base.id, connector->name);
f453ba04
DA		 3425 return NULL;
3426 }
0454beab 3427 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
e1e7bc48
JN		 3428 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Composite sync not supported\n",
3429 connector->base.id, connector->name);
f453ba04
DA		 3430 }
3431
fcb45611
ZY		 3432 /* it is incorrect if hsync/vsync width is zero */
3433 if (!hsync_pulse_width || !vsync_pulse_width) {
e1e7bc48
JN		 3434 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Incorrect Detailed timing. Wrong Hsync/Vsync pulse width\n",
3435 connector->base.id, connector->name);
fcb45611
ZY		 3436 return NULL;
3437 }
bc42aabc 3438
4959b693 3439 if (info->quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
bc42aabc
AJ		 3440 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
3441 if (!mode)
3442 return NULL;
3443
3444 goto set_size;
3445 }
3446
f453ba04
DA		 3447 mode = drm_mode_create(dev);
3448 if (!mode)
3449 return NULL;
3450
4959b693 3451 if (info->quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
faacff8e
JN		 3452 mode->clock = 1088 * 10;
3453 else
3454 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
0454beab
MD		 3455
3456 mode->hdisplay = hactive;
3457 mode->hsync_start = mode->hdisplay + hsync_offset;
3458 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
3459 mode->htotal = mode->hdisplay + hblank;
3460
3461 mode->vdisplay = vactive;
3462 mode->vsync_start = mode->vdisplay + vsync_offset;
3463 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
3464 mode->vtotal = mode->vdisplay + vblank;
f453ba04 3465
7064fef5
JB		 3466 /* Some EDIDs have bogus h/vtotal values */
3467 if (mode->hsync_end > mode->htotal)
3468 mode->htotal = mode->hsync_end + 1;
3469 if (mode->vsync_end > mode->vtotal)
3470 mode->vtotal = mode->vsync_end + 1;
3471
b58db2c6 3472 drm_mode_do_interlace_quirk(mode, pt);
f453ba04 3473
4959b693 3474 if (info->quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
faacff8e
JN		 3475 mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC;
3476 } else {
3477 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
3478 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
3479 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
3480 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
f453ba04
DA		 3481 }
3482
bc42aabc 3483set_size:
e14cbee4
MD		 3484 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
3485 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
f453ba04 3486
4959b693 3487 if (info->quirks & EDID_QUIRK_DETAILED_IN_CM) {
f453ba04
DA		 3488 mode->width_mm *= 10;
3489 mode->height_mm *= 10;
3490 }
3491
4959b693 3492 if (info->quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
f0d080ff
JN		 3493 mode->width_mm = drm_edid->edid->width_cm * 10;
3494 mode->height_mm = drm_edid->edid->height_cm * 10;
f453ba04
DA		 3495 }
3496
bc42aabc
AJ		 3497 mode->type = DRM_MODE_TYPE_DRIVER;
3498 drm_mode_set_name(mode);
3499
f453ba04
DA		 3500 return mode;
3501}
3502
b17e52ef 3503static bool
b1f559ec 3504mode_in_hsync_range(const struct drm_display_mode *mode,
c14e7241 3505 const struct edid *edid, const u8 *t)
b17e52ef
AJ		 3506{
3507 int hsync, hmin, hmax;
3508
3509 hmin = t[7];
3510 if (edid->revision >= 4)
3511 hmin += ((t[4] & 0x04) ? 255 : 0);
3512 hmax = t[8];
3513 if (edid->revision >= 4)
3514 hmax += ((t[4] & 0x08) ? 255 : 0);
07a5e632 3515 hsync = drm_mode_hsync(mode);
07a5e632 3516
b17e52ef
AJ		 3517 return (hsync <= hmax && hsync >= hmin);
3518}
3519
3520static bool
b1f559ec 3521mode_in_vsync_range(const struct drm_display_mode *mode,
c14e7241 3522 const struct edid *edid, const u8 *t)
b17e52ef
AJ		 3523{
3524 int vsync, vmin, vmax;
3525
3526 vmin = t[5];
3527 if (edid->revision >= 4)
3528 vmin += ((t[4] & 0x01) ? 255 : 0);
3529 vmax = t[6];
3530 if (edid->revision >= 4)
3531 vmax += ((t[4] & 0x02) ? 255 : 0);
3532 vsync = drm_mode_vrefresh(mode);
3533
3534 return (vsync <= vmax && vsync >= vmin);
3535}
3536
3537static u32
c14e7241 3538range_pixel_clock(const struct edid *edid, const u8 *t)
b17e52ef
AJ		 3539{
3540 /* unspecified */
3541 if (t[9] == 0 || t[9] == 255)
3542 return 0;
3543
3544 /* 1.4 with CVT support gives us real precision, yay */
afd4429e 3545 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG)
b17e52ef
AJ		 3546 return (t[9] * 10000) - ((t[12] >> 2) * 250);
3547
3548 /* 1.3 is pathetic, so fuzz up a bit */
3549 return t[9] * 10000 + 5001;
3550}
3551
874d98ee
JN		 3552static bool mode_in_range(const struct drm_display_mode *mode,
3553 const struct drm_edid *drm_edid,
3554 const struct detailed_timing *timing)
b17e52ef 3555{
874d98ee 3556 const struct edid *edid = drm_edid->edid;
b17e52ef 3557 u32 max_clock;
fcfb2ea1 3558 const u8 *t = (const u8 *)timing;
b17e52ef
AJ		 3559
3560 if (!mode_in_hsync_range(mode, edid, t))
07a5e632
AJ		 3561 return false;
3562
b17e52ef 3563 if (!mode_in_vsync_range(mode, edid, t))
07a5e632
AJ		 3564 return false;
3565
b17e52ef 3566 if ((max_clock = range_pixel_clock(edid, t)))
07a5e632
AJ		 3567 if (mode->clock > max_clock)
3568 return false;
b17e52ef
AJ		 3569
3570 /* 1.4 max horizontal check */
afd4429e 3571 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG)
b17e52ef
AJ		 3572 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
3573 return false;
3574
874d98ee 3575 if (mode_is_rb(mode) && !drm_monitor_supports_rb(drm_edid))
b17e52ef 3576 return false;
07a5e632
AJ		 3577
3578 return true;
3579}
3580
7b668ebe
TI		 3581static bool valid_inferred_mode(const struct drm_connector *connector,
3582 const struct drm_display_mode *mode)
3583{
85f8fcd6 3584 const struct drm_display_mode *m;
7b668ebe
TI		 3585 bool ok = false;
3586
3587 list_for_each_entry(m, &connector->probed_modes, head) {
3588 if (mode->hdisplay == m->hdisplay &&
3589 mode->vdisplay == m->vdisplay &&
3590 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
3591 return false; /* duplicated */
3592 if (mode->hdisplay <= m->hdisplay &&
3593 mode->vdisplay <= m->vdisplay)
3594 ok = true;
3595 }
3596 return ok;
3597}
3598
084c7a7c
JN		 3599static int drm_dmt_modes_for_range(struct drm_connector *connector,
3600 const struct drm_edid *drm_edid,
3601 const struct detailed_timing *timing)
07a5e632
AJ		 3602{
3603 int i, modes = 0;
3604 struct drm_display_mode *newmode;
3605 struct drm_device *dev = connector->dev;
3606
a6b21831 3607 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
874d98ee 3608 if (mode_in_range(drm_dmt_modes + i, drm_edid, timing) &&
7b668ebe 3609 valid_inferred_mode(connector, drm_dmt_modes + i)) {
07a5e632
AJ		 3610 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
3611 if (newmode) {
3612 drm_mode_probed_add(connector, newmode);
3613 modes++;
3614 }
3615 }
3616 }
3617
3618 return modes;
3619}
3620
c09dedb7
TI		 3621/* fix up 1366x768 mode from 1368x768;
3622 * GFT/CVT can't express 1366 width which isn't dividable by 8
3623 */
969218fe 3624void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
c09dedb7
TI		 3625{
3626 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
3627 mode->hdisplay = 1366;
3628 mode->hsync_start--;
3629 mode->hsync_end--;
3630 drm_mode_set_name(mode);
3631 }
3632}
3633
a77f7c89
JN		 3634static int drm_gtf_modes_for_range(struct drm_connector *connector,
3635 const struct drm_edid *drm_edid,
3636 const struct detailed_timing *timing)
b309bd37
AJ		 3637{
3638 int i, modes = 0;
3639 struct drm_display_mode *newmode;
3640 struct drm_device *dev = connector->dev;
3641
a6b21831 3642 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
b309bd37 3643 const struct minimode *m = &extra_modes[i];
948de842 3644
b309bd37 3645 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
fc48f169
TI		 3646 if (!newmode)
3647 return modes;
b309bd37 3648
969218fe 3649 drm_mode_fixup_1366x768(newmode);
874d98ee 3650 if (!mode_in_range(newmode, drm_edid, timing) ||
7b668ebe 3651 !valid_inferred_mode(connector, newmode)) {
b309bd37
AJ		 3652 drm_mode_destroy(dev, newmode);
3653 continue;
3654 }
3655
3656 drm_mode_probed_add(connector, newmode);
3657 modes++;
3658 }
3659
3660 return modes;
3661}
3662
9ed15f91
VS		 3663static int drm_gtf2_modes_for_range(struct drm_connector *connector,
3664 const struct drm_edid *drm_edid,
3665 const struct detailed_timing *timing)
3666{
3667 int i, modes = 0;
3668 struct drm_display_mode *newmode;
3669 struct drm_device *dev = connector->dev;
3670
3671 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3672 const struct minimode *m = &extra_modes[i];
3673
3674 newmode = drm_gtf2_mode(dev, drm_edid, m->w, m->h, m->r);
3675 if (!newmode)
3676 return modes;
3677
3678 drm_mode_fixup_1366x768(newmode);
3679 if (!mode_in_range(newmode, drm_edid, timing) ||
3680 !valid_inferred_mode(connector, newmode)) {
3681 drm_mode_destroy(dev, newmode);
3682 continue;
3683 }
3684
3685 drm_mode_probed_add(connector, newmode);
3686 modes++;
3687 }
3688
3689 return modes;
3690}
3691
7428bfbd
JN		 3692static int drm_cvt_modes_for_range(struct drm_connector *connector,
3693 const struct drm_edid *drm_edid,
3694 const struct detailed_timing *timing)
b309bd37
AJ		 3695{
3696 int i, modes = 0;
3697 struct drm_display_mode *newmode;
3698 struct drm_device *dev = connector->dev;
874d98ee 3699 bool rb = drm_monitor_supports_rb(drm_edid);
b309bd37 3700
a6b21831 3701 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
b309bd37 3702 const struct minimode *m = &extra_modes[i];
948de842 3703
b309bd37 3704 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
fc48f169
TI		 3705 if (!newmode)
3706 return modes;
b309bd37 3707
969218fe 3708 drm_mode_fixup_1366x768(newmode);
874d98ee 3709 if (!mode_in_range(newmode, drm_edid, timing) ||
7b668ebe 3710 !valid_inferred_mode(connector, newmode)) {
b309bd37
AJ		 3711 drm_mode_destroy(dev, newmode);
3712 continue;
3713 }
3714
3715 drm_mode_probed_add(connector, newmode);
3716 modes++;
3717 }
3718
3719 return modes;
3720}
3721
13931579 3722static void
4194442d 3723do_inferred_modes(const struct detailed_timing *timing, void *c)
9340d8cf 3724{
13931579 3725 struct detailed_mode_closure *closure = c;
fcfb2ea1
JN		 3726 const struct detailed_non_pixel *data = &timing->data.other_data;
3727 const struct detailed_data_monitor_range *range = &data->data.range;
9340d8cf 3728
e379814b 3729 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
cb21aafe
AJ		 3730 return;
3731
3732 closure->modes += drm_dmt_modes_for_range(closure->connector,
084c7a7c 3733 closure->drm_edid,
cb21aafe 3734 timing);
4d23f484 3735
dd3abfe4 3736 if (closure->drm_edid->edid->revision < 2)
b309bd37
AJ		 3737 return; /* GTF not defined yet */
3738
3739 switch (range->flags) {
9ed15f91
VS		 3740 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG:
3741 closure->modes += drm_gtf2_modes_for_range(closure->connector,
3742 closure->drm_edid,
3743 timing);
3744 break;
afd4429e 3745 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG:
b309bd37 3746 closure->modes += drm_gtf_modes_for_range(closure->connector,
a77f7c89 3747 closure->drm_edid,
b309bd37
AJ		 3748 timing);
3749 break;
afd4429e 3750 case DRM_EDID_CVT_SUPPORT_FLAG:
dd3abfe4 3751 if (closure->drm_edid->edid->revision < 4)
b309bd37
AJ		 3752 break;
3753
3754 closure->modes += drm_cvt_modes_for_range(closure->connector,
7428bfbd 3755 closure->drm_edid,
b309bd37
AJ		 3756 timing);
3757 break;
afd4429e 3758 case DRM_EDID_RANGE_LIMITS_ONLY_FLAG:
b309bd37
AJ		 3759 default:
3760 break;
3761 }
13931579 3762}
69da3015 3763
40f71f5b
JN		 3764static int add_inferred_modes(struct drm_connector *connector,
3765 const struct drm_edid *drm_edid)
13931579
AJ		 3766{
3767 struct detailed_mode_closure closure = {
d456ea2e 3768 .connector = connector,
dd0f4470 3769 .drm_edid = drm_edid,
13931579 3770 };
9340d8cf 3771
dd3abfe4 3772 if (drm_edid->edid->revision >= 1)
45aa2336 3773 drm_for_each_detailed_block(drm_edid, do_inferred_modes, &closure);
9340d8cf 3774
13931579 3775 return closure.modes;
9340d8cf
AJ		 3776}
3777
2255be14 3778static int
fcfb2ea1 3779drm_est3_modes(struct drm_connector *connector, const struct detailed_timing *timing)
2255be14
AJ		 3780{
3781 int i, j, m, modes = 0;
3782 struct drm_display_mode *mode;
fcfb2ea1 3783 const u8 *est = ((const u8 *)timing) + 6;
2255be14
AJ		 3784
3785 for (i = 0; i < 6; i++) {
891a7469 3786 for (j = 7; j >= 0; j--) {
2255be14 3787 m = (i * 8) + (7 - j);
3c581411 3788 if (m >= ARRAY_SIZE(est3_modes))
2255be14
AJ		 3789 break;
3790 if (est[i] & (1 << j)) {
1d42bbc8
DA		 3791 mode = drm_mode_find_dmt(connector->dev,
3792 est3_modes[m].w,
3793 est3_modes[m].h,
f6e252ba
AJ		 3794 est3_modes[m].r,
3795 est3_modes[m].rb);
2255be14
AJ		 3796 if (mode) {
3797 drm_mode_probed_add(connector, mode);
3798 modes++;
3799 }
3800 }
3801 }
3802 }
3803
3804 return modes;
3805}
3806
13931579 3807static void
4194442d 3808do_established_modes(const struct detailed_timing *timing, void *c)
9cf00977 3809{
13931579 3810 struct detailed_mode_closure *closure = c;
9cf00977 3811
e379814b 3812 if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS))
a7a131ac
VS		 3813 return;
3814
3815 closure->modes += drm_est3_modes(closure->connector, timing);
13931579 3816}
9cf00977 3817
17edb8e1
JN		 3818/*
3819 * Get established modes from EDID and add them. Each EDID block contains a
3820 * bitmap of the supported "established modes" list (defined above). Tease them
3821 * out and add them to the global modes list.
13931579 3822 */
40f71f5b
JN		 3823static int add_established_modes(struct drm_connector *connector,
3824 const struct drm_edid *drm_edid)
13931579
AJ		 3825{
3826 struct drm_device *dev = connector->dev;
40f71f5b 3827 const struct edid *edid = drm_edid->edid;
13931579
AJ		 3828 unsigned long est_bits = edid->established_timings.t1 |
3829 (edid->established_timings.t2 << 8) |
3830 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
3831 int i, modes = 0;
3832 struct detailed_mode_closure closure = {
d456ea2e 3833 .connector = connector,
dd0f4470 3834 .drm_edid = drm_edid,
13931579 3835 };
9cf00977 3836
13931579
AJ		 3837 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
3838 if (est_bits & (1<<i)) {
3839 struct drm_display_mode *newmode;
948de842 3840
13931579
AJ		 3841 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
3842 if (newmode) {
3843 drm_mode_probed_add(connector, newmode);
3844 modes++;
3845 }
3846 }
9cf00977
AJ		 3847 }
3848
dd3abfe4 3849 if (edid->revision >= 1)
45aa2336 3850 drm_for_each_detailed_block(drm_edid, do_established_modes,
eed628f1 3851 &closure);
13931579
AJ		 3852
3853 return modes + closure.modes;
3854}
3855
3856static void
4194442d 3857do_standard_modes(const struct detailed_timing *timing, void *c)
13931579
AJ		 3858{
3859 struct detailed_mode_closure *closure = c;
fcfb2ea1 3860 const struct detailed_non_pixel *data = &timing->data.other_data;
13931579 3861 struct drm_connector *connector = closure->connector;
a7a131ac 3862 int i;
13931579 3863
e379814b 3864 if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES))
a7a131ac 3865 return;
9cf00977 3866
a7a131ac 3867 for (i = 0; i < 6; i++) {
fcfb2ea1 3868 const struct std_timing *std = &data->data.timings[i];
a7a131ac
VS		 3869 struct drm_display_mode *newmode;
3870
67d87fac 3871 newmode = drm_mode_std(connector, closure->drm_edid, std);
a7a131ac
VS		 3872 if (newmode) {
3873 drm_mode_probed_add(connector, newmode);
3874 closure->modes++;
9cf00977 3875 }
9cf00977 3876 }
9cf00977
AJ		 3877}
3878
17edb8e1
JN		 3879/*
3880 * Get standard modes from EDID and add them. Standard modes can be calculated
3881 * using the appropriate standard (DMT, GTF, or CVT). Grab them from EDID and
3882 * add them to the list.
f453ba04 3883 */
40f71f5b
JN		 3884static int add_standard_modes(struct drm_connector *connector,
3885 const struct drm_edid *drm_edid)
f453ba04 3886{
9cf00977 3887 int i, modes = 0;
13931579 3888 struct detailed_mode_closure closure = {
d456ea2e 3889 .connector = connector,
dd0f4470 3890 .drm_edid = drm_edid,
13931579
AJ		 3891 };
3892
3893 for (i = 0; i < EDID_STD_TIMINGS; i++) {
3894 struct drm_display_mode *newmode;
3895
67d87fac 3896 newmode = drm_mode_std(connector, drm_edid,
40f71f5b 3897 &drm_edid->edid->standard_timings[i]);
13931579
AJ		 3898 if (newmode) {
3899 drm_mode_probed_add(connector, newmode);
3900 modes++;
3901 }
3902 }
3903
dd3abfe4 3904 if (drm_edid->edid->revision >= 1)
45aa2336 3905 drm_for_each_detailed_block(drm_edid, do_standard_modes,
13931579
AJ		 3906 &closure);
3907
3908 /* XXX should also look for standard codes in VTB blocks */
3909
3910 return modes + closure.modes;
3911}
f453ba04 3912
13931579 3913static int drm_cvt_modes(struct drm_connector *connector,
fcfb2ea1 3914 const struct detailed_timing *timing)
13931579
AJ		 3915{
3916 int i, j, modes = 0;
3917 struct drm_display_mode *newmode;
3918 struct drm_device *dev = connector->dev;
fcfb2ea1 3919 const struct cvt_timing *cvt;
13931579
AJ		 3920 const int rates[] = { 60, 85, 75, 60, 50 };
3921 const u8 empty[3] = { 0, 0, 0 };
a327f6b8 3922
13931579 3923 for (i = 0; i < 4; i++) {
3f649ab7 3924 int width, height;
948de842 3925
13931579 3926 cvt = &(timing->data.other_data.data.cvt[i]);
f453ba04 3927
13931579 3928 if (!memcmp(cvt->code, empty, 3))
9cf00977 3929 continue;
f453ba04 3930
13931579
AJ		 3931 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
3932 switch (cvt->code[1] & 0x0c) {
d652d5f1
LT		 3933 /* default - because compiler doesn't see that we've enumerated all cases */
3934 default:
13931579
AJ		 3935 case 0x00:
3936 width = height * 4 / 3;
3937 break;
3938 case 0x04:
3939 width = height * 16 / 9;
3940 break;
3941 case 0x08:
3942 width = height * 16 / 10;
3943 break;
3944 case 0x0c:
3945 width = height * 15 / 9;
3946 break;
3947 }
3948
3949 for (j = 1; j < 5; j++) {
3950 if (cvt->code[2] & (1 << j)) {
3951 newmode = drm_cvt_mode(dev, width, height,
3952 rates[j], j == 0,
3953 false, false);
3954 if (newmode) {
3955 drm_mode_probed_add(connector, newmode);
3956 modes++;
3957 }
3958 }
3959 }
f453ba04
DA		 3960 }
3961
3962 return modes;
3963}
9cf00977 3964
13931579 3965static void
4194442d 3966do_cvt_mode(const struct detailed_timing *timing, void *c)
882f0219 3967{
13931579 3968 struct detailed_mode_closure *closure = c;
882f0219 3969
e379814b 3970 if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE))
a7a131ac
VS		 3971 return;
3972
3973 closure->modes += drm_cvt_modes(closure->connector, timing);
13931579 3974}
882f0219 3975
13931579 3976static int
40f71f5b 3977add_cvt_modes(struct drm_connector *connector, const struct drm_edid *drm_edid)
4d23f484 3978{
13931579 3979 struct detailed_mode_closure closure = {
d456ea2e 3980 .connector = connector,
dd0f4470 3981 .drm_edid = drm_edid,
13931579 3982 };
882f0219 3983
dd3abfe4 3984 if (drm_edid->edid->revision >= 3)
45aa2336 3985 drm_for_each_detailed_block(drm_edid, do_cvt_mode, &closure);
882f0219 3986
13931579 3987 /* XXX should also look for CVT codes in VTB blocks */
882f0219 3988
13931579
AJ		 3989 return closure.modes;
3990}
3991
e1e7bc48
JN		 3992static void fixup_detailed_cea_mode_clock(struct drm_connector *connector,
3993 struct drm_display_mode *mode);
fa3a7340 3994
13931579 3995static void
4194442d 3996do_detailed_mode(const struct detailed_timing *timing, void *c)
13931579
AJ		 3997{
3998 struct detailed_mode_closure *closure = c;
3999 struct drm_display_mode *newmode;
4000
a9b1f15f 4001 if (!is_detailed_timing_descriptor(timing))
f447dd1f
VS		 4002 return;
4003
e1e7bc48 4004 newmode = drm_mode_detailed(closure->connector,
4959b693 4005 closure->drm_edid, timing);
f447dd1f
VS		 4006 if (!newmode)
4007 return;
13931579 4008
f447dd1f
VS		 4009 if (closure->preferred)
4010 newmode->type |= DRM_MODE_TYPE_PREFERRED;
13931579 4011
f447dd1f
VS		 4012 /*
4013 * Detailed modes are limited to 10kHz pixel clock resolution,
4014 * so fix up anything that looks like CEA/HDMI mode, but the clock
4015 * is just slightly off.
4016 */
e1e7bc48 4017 fixup_detailed_cea_mode_clock(closure->connector, newmode);
fa3a7340 4018
f447dd1f
VS		 4019 drm_mode_probed_add(closure->connector, newmode);
4020 closure->modes++;
4021 closure->preferred = false;
13931579 4022}
882f0219 4023
13931579
AJ		 4024/*
4025 * add_detailed_modes - Add modes from detailed timings
4026 * @connector: attached connector
40f71f5b 4027 * @drm_edid: EDID block to scan
13931579 4028 */
40f71f5b 4029static int add_detailed_modes(struct drm_connector *connector,
4959b693 4030 const struct drm_edid *drm_edid)
13931579
AJ		 4031{
4032 struct detailed_mode_closure closure = {
d456ea2e 4033 .connector = connector,
dd0f4470 4034 .drm_edid = drm_edid,
13931579
AJ		 4035 };
4036
dd3abfe4 4037 if (drm_edid->edid->revision >= 4)
f72f9529
VS		 4038 closure.preferred = true; /* first detailed timing is always preferred */
4039 else
13931579 4040 closure.preferred =
f72f9529 4041 drm_edid->edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING;
13931579 4042
45aa2336 4043 drm_for_each_detailed_block(drm_edid, do_detailed_mode, &closure);
13931579
AJ		 4044
4045 return closure.modes;
882f0219 4046}
f453ba04 4047
9d72b7e2
JN		 4048/* CTA-861-H Table 60 - CTA Tag Codes */
4049#define CTA_DB_AUDIO 1
4050#define CTA_DB_VIDEO 2
4051#define CTA_DB_VENDOR 3
4052#define CTA_DB_SPEAKER 4
4053#define CTA_DB_EXTENDED_TAG 7
4054
4055/* CTA-861-H Table 62 - CTA Extended Tag Codes */
4056#define CTA_EXT_DB_VIDEO_CAP 0
4057#define CTA_EXT_DB_VENDOR 1
4058#define CTA_EXT_DB_HDR_STATIC_METADATA 6
4059#define CTA_EXT_DB_420_VIDEO_DATA 14
4060#define CTA_EXT_DB_420_VIDEO_CAP_MAP 15
18e3c1d5 4061#define CTA_EXT_DB_HF_EEODB 0x78
9d72b7e2
JN		 4062#define CTA_EXT_DB_HF_SCDB 0x79
4063
8fe9790d 4064#define EDID_BASIC_AUDIO (1 << 6)
a988bc72
LPC		 4065#define EDID_CEA_YCRCB444 (1 << 5)
4066#define EDID_CEA_YCRCB422 (1 << 4)
b1edd6a6 4067#define EDID_CEA_VCDB_QS (1 << 6)
8fe9790d 4068
d4e4a31d 4069/*
8fe9790d 4070 * Search EDID for CEA extension block.
d9ba1b4c
JN		 4071 *
4072 * FIXME: Prefer not returning pointers to raw EDID data.
f23c20c8 4073 */
d9ba1b4c 4074const u8 *drm_find_edid_extension(const struct drm_edid *drm_edid,
4cc4f09e 4075 int ext_id, int *ext_index)
f23c20c8 4076{
43d16d84 4077 const u8 *edid_ext = NULL;
8fe9790d 4078 int i;
f23c20c8
ML		 4079
4080 /* No EDID or EDID extensions */
d9307f27 4081 if (!drm_edid || !drm_edid_extension_block_count(drm_edid))
8fe9790d 4082 return NULL;
f23c20c8 4083
f23c20c8 4084 /* Find CEA extension */
d9307f27
JN		 4085 for (i = *ext_index; i < drm_edid_extension_block_count(drm_edid); i++) {
4086 edid_ext = drm_edid_extension_block_data(drm_edid, i);
4ba0f53c 4087 if (edid_block_tag(edid_ext) == ext_id)
f23c20c8
ML		 4088 break;
4089 }
4090
d9307f27 4091 if (i >= drm_edid_extension_block_count(drm_edid))
8fe9790d
ZW		 4092 return NULL;
4093
8873cfa3
VS		 4094 *ext_index = i + 1;
4095
8fe9790d
ZW		 4096 return edid_ext;
4097}
4098
6ff1c19f 4099/* Return true if the EDID has a CTA extension or a DisplayID CTA data block */
40f71f5b 4100static bool drm_edid_has_cta_extension(const struct drm_edid *drm_edid)
e28ad544 4101{
43d16d84 4102 const struct displayid_block *block;
1ba63caf 4103 struct displayid_iter iter;
1ba63caf 4104 int ext_index = 0;
6ff1c19f 4105 bool found = false;
e28ad544
AR		 4106
4107 /* Look for a top level CEA extension block */
d9ba1b4c 4108 if (drm_find_edid_extension(drm_edid, CEA_EXT, &ext_index))
6ff1c19f 4109 return true;
e28ad544
AR		 4110
4111 /* CEA blocks can also be found embedded in a DisplayID block */
d9ba1b4c 4112 displayid_iter_edid_begin(drm_edid, &iter);
1ba63caf
JN		 4113 displayid_iter_for_each(block, &iter) {
4114 if (block->tag == DATA_BLOCK_CTA) {
6ff1c19f 4115 found = true;
1ba63caf 4116 break;
e28ad544
AR		 4117 }
4118 }
1ba63caf 4119 displayid_iter_end(&iter);
e28ad544 4120
6ff1c19f 4121 return found;
e28ad544
AR		 4122}
4123
e1cf35b9 4124static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic)
7befe621 4125{
9212f8ee
VS		 4126 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127);
4127 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219);
4128
8c1b2bd9
VS		 4129 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1))
4130 return &edid_cea_modes_1[vic - 1];
f7655d42
VS		 4131 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193))
4132 return &edid_cea_modes_193[vic - 193];
7befe621
VS		 4133 return NULL;
4134}
4135
4136static u8 cea_num_vics(void)
4137{
f7655d42 4138 return 193 + ARRAY_SIZE(edid_cea_modes_193);
7befe621
VS		 4139}
4140
4141static u8 cea_next_vic(u8 vic)
4142{
8c1b2bd9 4143 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1))
f7655d42
VS		 4144 vic = 193;
4145 return vic;
7befe621
VS		 4146}
4147
e6e79209
VS		 4148/*
4149 * Calculate the alternate clock for the CEA mode
4150 * (60Hz vs. 59.94Hz etc.)
4151 */
4152static unsigned int
4153cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
4154{
4155 unsigned int clock = cea_mode->clock;
4156
0425662f 4157 if (drm_mode_vrefresh(cea_mode) % 6 != 0)
e6e79209
VS		 4158 return clock;
4159
4160 /*
4161 * edid_cea_modes contains the 59.94Hz
4162 * variant for 240 and 480 line modes,
4163 * and the 60Hz variant otherwise.
4164 */
4165 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
9afd808c 4166 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
e6e79209 4167 else
9afd808c 4168 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
e6e79209
VS		 4169
4170 return clock;
4171}
4172
c45a4e46
VS		 4173static bool
4174cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
4175{
4176 /*
4177 * For certain VICs the spec allows the vertical
4178 * front porch to vary by one or two lines.
4179 *
4180 * cea_modes[] stores the variant with the shortest
4181 * vertical front porch. We can adjust the mode to
4182 * get the other variants by simply increasing the
4183 * vertical front porch length.
4184 */
7befe621
VS		 4185 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 ||
4186 cea_mode_for_vic(9)->vtotal != 262 ||
4187 cea_mode_for_vic(12)->vtotal != 262 ||
4188 cea_mode_for_vic(13)->vtotal != 262 ||
4189 cea_mode_for_vic(23)->vtotal != 312 ||
4190 cea_mode_for_vic(24)->vtotal != 312 ||
4191 cea_mode_for_vic(27)->vtotal != 312 ||
4192 cea_mode_for_vic(28)->vtotal != 312);
c45a4e46
VS		 4193
4194 if (((vic == 8 || vic == 9 ||
4195 vic == 12 || vic == 13) && mode->vtotal < 263) ||
4196 ((vic == 23 || vic == 24 ||
4197 vic == 27 || vic == 28) && mode->vtotal < 314)) {
4198 mode->vsync_start++;
4199 mode->vsync_end++;
4200 mode->vtotal++;
4201
4202 return true;
4203 }
4204
4205 return false;
4206}
4207
4c6bcf44
VS		 4208static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
4209 unsigned int clock_tolerance)
4210{
357768cc 4211 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 4212 u8 vic;
4c6bcf44
VS		 4213
4214 if (!to_match->clock)
4215 return 0;
4216
357768cc
VS		 4217 if (to_match->picture_aspect_ratio)
4218 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4219
7befe621 4220 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
563c4a75 4221 struct drm_display_mode cea_mode;
4c6bcf44
VS		 4222 unsigned int clock1, clock2;
4223
563c4a75
VS		 4224 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
4225
4c6bcf44 4226 /* Check both 60Hz and 59.94Hz */
c45a4e46
VS		 4227 clock1 = cea_mode.clock;
4228 clock2 = cea_mode_alternate_clock(&cea_mode);
4c6bcf44
VS		 4229
4230 if (abs(to_match->clock - clock1) > clock_tolerance &&
4231 abs(to_match->clock - clock2) > clock_tolerance)
4232 continue;
4233
c45a4e46 4234 do {
357768cc 4235 if (drm_mode_match(to_match, &cea_mode, match_flags))
c45a4e46
VS		 4236 return vic;
4237 } while (cea_mode_alternate_timings(vic, &cea_mode));
4c6bcf44
VS		 4238 }
4239
4240 return 0;
4241}
4242
18316c8c
TR		 4243/**
4244 * drm_match_cea_mode - look for a CEA mode matching given mode
4245 * @to_match: display mode
4246 *
db6cf833 4247 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
18316c8c 4248 * mode.
a4799037 4249 */
18316c8c 4250u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
a4799037 4251{
357768cc 4252 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 4253 u8 vic;
a4799037 4254
a90b590e
VS		 4255 if (!to_match->clock)
4256 return 0;
4257
357768cc
VS		 4258 if (to_match->picture_aspect_ratio)
4259 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4260
7befe621 4261 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
563c4a75 4262 struct drm_display_mode cea_mode;
a90b590e
VS		 4263 unsigned int clock1, clock2;
4264
563c4a75
VS		 4265 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
4266
a90b590e 4267 /* Check both 60Hz and 59.94Hz */
c45a4e46
VS		 4268 clock1 = cea_mode.clock;
4269 clock2 = cea_mode_alternate_clock(&cea_mode);
a4799037 4270
c45a4e46
VS		 4271 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
4272 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
4273 continue;
4274
4275 do {
357768cc 4276 if (drm_mode_match(to_match, &cea_mode, match_flags))
c45a4e46
VS		 4277 return vic;
4278 } while (cea_mode_alternate_timings(vic, &cea_mode));
a4799037 4279 }
c45a4e46 4280
a4799037
SM		 4281 return 0;
4282}
4283EXPORT_SYMBOL(drm_match_cea_mode);
4284
d9278b4c
JN		 4285static bool drm_valid_cea_vic(u8 vic)
4286{
7befe621 4287 return cea_mode_for_vic(vic) != NULL;
d9278b4c
JN		 4288}
4289
28c03a44 4290static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
0967e6a5 4291{
7befe621
VS		 4292 const struct drm_display_mode *mode = cea_mode_for_vic(video_code);
4293
4294 if (mode)
4295 return mode->picture_aspect_ratio;
4296
4297 return HDMI_PICTURE_ASPECT_NONE;
0967e6a5 4298}
0967e6a5 4299
d2b43473
WL		 4300static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code)
4301{
4302 return edid_4k_modes[video_code].picture_aspect_ratio;
4303}
4304
3f2f6533
LD		 4305/*
4306 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
4307 * specific block).
3f2f6533
LD		 4308 */
4309static unsigned int
4310hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
4311{
3f2f6533
LD		 4312 return cea_mode_alternate_clock(hdmi_mode);
4313}
4314
4c6bcf44
VS		 4315static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
4316 unsigned int clock_tolerance)
4317{
357768cc 4318 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 4319 u8 vic;
4c6bcf44
VS		 4320
4321 if (!to_match->clock)
4322 return 0;
4323
d2b43473
WL		 4324 if (to_match->picture_aspect_ratio)
4325 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4326
d9278b4c
JN		 4327 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
4328 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4c6bcf44
VS		 4329 unsigned int clock1, clock2;
4330
4331 /* Make sure to also match alternate clocks */
4332 clock1 = hdmi_mode->clock;
4333 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
4334
4335 if (abs(to_match->clock - clock1) > clock_tolerance &&
4336 abs(to_match->clock - clock2) > clock_tolerance)
4337 continue;
4338
357768cc 4339 if (drm_mode_match(to_match, hdmi_mode, match_flags))
d9278b4c 4340 return vic;
4c6bcf44
VS		 4341 }
4342
4343 return 0;
4344}
4345
3f2f6533
LD		 4346/*
4347 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
4348 * @to_match: display mode
4349 *
4350 * An HDMI mode is one defined in the HDMI vendor specific block.
4351 *
4352 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
4353 */
4354static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
4355{
357768cc 4356 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 4357 u8 vic;
3f2f6533
LD		 4358
4359 if (!to_match->clock)
4360 return 0;
4361
d2b43473
WL		 4362 if (to_match->picture_aspect_ratio)
4363 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4364
d9278b4c
JN		 4365 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
4366 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3f2f6533
LD		 4367 unsigned int clock1, clock2;
4368
4369 /* Make sure to also match alternate clocks */
4370 clock1 = hdmi_mode->clock;
4371 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
4372
4373 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
4374 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
357768cc 4375 drm_mode_match(to_match, hdmi_mode, match_flags))
d9278b4c 4376 return vic;
3f2f6533
LD		 4377 }
4378 return 0;
4379}
4380
d9278b4c
JN		 4381static bool drm_valid_hdmi_vic(u8 vic)
4382{
4383 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
4384}
4385
40f71f5b
JN		 4386static int add_alternate_cea_modes(struct drm_connector *connector,
4387 const struct drm_edid *drm_edid)
e6e79209
VS		 4388{
4389 struct drm_device *dev = connector->dev;
4390 struct drm_display_mode *mode, *tmp;
4391 LIST_HEAD(list);
4392 int modes = 0;
4393
6ff1c19f 4394 /* Don't add CTA modes if the CTA extension block is missing */
40f71f5b 4395 if (!drm_edid_has_cta_extension(drm_edid))
e6e79209
VS		 4396 return 0;
4397
4398 /*
4399 * Go through all probed modes and create a new mode
4400 * with the alternate clock for certain CEA modes.
4401 */
4402 list_for_each_entry(mode, &connector->probed_modes, head) {
3f2f6533 4403 const struct drm_display_mode *cea_mode = NULL;
e6e79209 4404 struct drm_display_mode *newmode;
d9278b4c 4405 u8 vic = drm_match_cea_mode(mode);
e6e79209
VS		 4406 unsigned int clock1, clock2;
4407
d9278b4c 4408 if (drm_valid_cea_vic(vic)) {
7befe621 4409 cea_mode = cea_mode_for_vic(vic);
3f2f6533
LD		 4410 clock2 = cea_mode_alternate_clock(cea_mode);
4411 } else {
d9278b4c
JN		 4412 vic = drm_match_hdmi_mode(mode);
4413 if (drm_valid_hdmi_vic(vic)) {
4414 cea_mode = &edid_4k_modes[vic];
3f2f6533
LD		 4415 clock2 = hdmi_mode_alternate_clock(cea_mode);
4416 }
4417 }
e6e79209 4418
3f2f6533
LD		 4419 if (!cea_mode)
4420 continue;
e6e79209
VS		 4421
4422 clock1 = cea_mode->clock;
e6e79209
VS		 4423
4424 if (clock1 == clock2)
4425 continue;
4426
4427 if (mode->clock != clock1 && mode->clock != clock2)
4428 continue;
4429
4430 newmode = drm_mode_duplicate(dev, cea_mode);
4431 if (!newmode)
4432 continue;
4433
27130212
DL		 4434 /* Carry over the stereo flags */
4435 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
4436
e6e79209
VS		 4437 /*
4438 * The current mode could be either variant. Make
4439 * sure to pick the "other" clock for the new mode.
4440 */
4441 if (mode->clock != clock1)
4442 newmode->clock = clock1;
4443 else
4444 newmode->clock = clock2;
4445
4446 list_add_tail(&newmode->head, &list);
4447 }
4448
4449 list_for_each_entry_safe(mode, tmp, &list, head) {
4450 list_del(&mode->head);
4451 drm_mode_probed_add(connector, mode);
4452 modes++;
4453 }
4454
4455 return modes;
4456}
a4799037 4457
8ec6e075
SS		 4458static u8 svd_to_vic(u8 svd)
4459{
4460 /* 0-6 bit vic, 7th bit native mode indicator */
4461 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
4462 return svd & 127;
4463
4464 return svd;
4465}
4466
6a40a75f
JN		 4467/*
4468 * Return a display mode for the 0-based vic_index'th VIC across all CTA VDBs in
4469 * the EDID, or NULL on errors.
4470 */
aff04ace 4471static struct drm_display_mode *
6a40a75f 4472drm_display_mode_from_vic_index(struct drm_connector *connector, int vic_index)
54ac76f8 4473{
6a40a75f 4474 const struct drm_display_info *info = &connector->display_info;
54ac76f8 4475 struct drm_device *dev = connector->dev;
54ac76f8 4476
6a40a75f 4477 if (!info->vics || vic_index >= info->vics_len || !info->vics[vic_index])
aff04ace
TW		 4478 return NULL;
4479
6a40a75f 4480 return drm_display_mode_from_cea_vic(dev, info->vics[vic_index]);
aff04ace
TW		 4481}
4482
832d4f2f
SS		 4483/*
4484 * do_y420vdb_modes - Parse YCBCR 420 only modes
4485 * @connector: connector corresponding to the HDMI sink
4486 * @svds: start of the data block of CEA YCBCR 420 VDB
4487 * @len: length of the CEA YCBCR 420 VDB
4488 *
4489 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
4490 * which contains modes which can be supported in YCBCR 420
4491 * output format only.
4492 */
4493static int do_y420vdb_modes(struct drm_connector *connector,
4494 const u8 *svds, u8 svds_len)
4495{
832d4f2f 4496 struct drm_device *dev = connector->dev;
c54e2e23 4497 int modes = 0, i;
832d4f2f
SS		 4498
4499 for (i = 0; i < svds_len; i++) {
4500 u8 vic = svd_to_vic(svds[i]);
4501 struct drm_display_mode *newmode;
4502
4503 if (!drm_valid_cea_vic(vic))
4504 continue;
4505
7befe621 4506 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
832d4f2f
SS		 4507 if (!newmode)
4508 break;
832d4f2f
SS		 4509 drm_mode_probed_add(connector, newmode);
4510 modes++;
4511 }
4512
832d4f2f
SS		 4513 return modes;
4514}
4515
7af655bc
VS		 4516/**
4517 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC
4518 * @dev: DRM device
8d7d8c0a 4519 * @video_code: CEA VIC of the mode
7af655bc
VS		 4520 *
4521 * Creates a new mode matching the specified CEA VIC.
4522 *
4523 * Returns: A new drm_display_mode on success or NULL on failure
4524 */
4525struct drm_display_mode *
4526drm_display_mode_from_cea_vic(struct drm_device *dev,
4527 u8 video_code)
4528{
4529 const struct drm_display_mode *cea_mode;
4530 struct drm_display_mode *newmode;
4531
4532 cea_mode = cea_mode_for_vic(video_code);
4533 if (!cea_mode)
4534 return NULL;
4535
4536 newmode = drm_mode_duplicate(dev, cea_mode);
4537 if (!newmode)
4538 return NULL;
4539
4540 return newmode;
4541}
4542EXPORT_SYMBOL(drm_display_mode_from_cea_vic);
4543
6a40a75f
JN		 4544/* Add modes based on VICs parsed in parse_cta_vdb() */
4545static int add_cta_vdb_modes(struct drm_connector *connector)
aff04ace 4546{
6a40a75f 4547 const struct drm_display_info *info = &connector->display_info;
aff04ace
TW		 4548 int i, modes = 0;
4549
6a40a75f
JN		 4550 if (!info->vics)
4551 return 0;
4552
4553 for (i = 0; i < info->vics_len; i++) {
aff04ace 4554 struct drm_display_mode *mode;
948de842 4555
6a40a75f 4556 mode = drm_display_mode_from_vic_index(connector, i);
aff04ace
TW		 4557 if (mode) {
4558 drm_mode_probed_add(connector, mode);
4559 modes++;
54ac76f8
CS		 4560 }
4561 }
4562
4563 return modes;
4564}
4565
c858cfca
DL		 4566struct stereo_mandatory_mode {
4567 int width, height, vrefresh;
4568 unsigned int flags;
4569};
4570
4571static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
f7e121b7
DL		 4572 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4573 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
c858cfca
DL		 4574 { 1920, 1080, 50,
4575 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
4576 { 1920, 1080, 60,
4577 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
f7e121b7
DL		 4578 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4579 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
4580 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4581 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
c858cfca
DL		 4582};
4583
4584static bool
4585stereo_match_mandatory(const struct drm_display_mode *mode,
4586 const struct stereo_mandatory_mode *stereo_mode)
4587{
4588 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
4589
4590 return mode->hdisplay == stereo_mode->width &&
4591 mode->vdisplay == stereo_mode->height &&
4592 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
4593 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
4594}
4595
c858cfca
DL		 4596static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
4597{
4598 struct drm_device *dev = connector->dev;
4599 const struct drm_display_mode *mode;
4600 struct list_head stereo_modes;
f7e121b7 4601 int modes = 0, i;
c858cfca
DL		 4602
4603 INIT_LIST_HEAD(&stereo_modes);
4604
4605 list_for_each_entry(mode, &connector->probed_modes, head) {
f7e121b7
DL		 4606 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
4607 const struct stereo_mandatory_mode *mandatory;
c858cfca
DL		 4608 struct drm_display_mode *new_mode;
4609
f7e121b7
DL		 4610 if (!stereo_match_mandatory(mode,
4611 &stereo_mandatory_modes[i]))
4612 continue;
c858cfca 4613
f7e121b7 4614 mandatory = &stereo_mandatory_modes[i];
c858cfca
DL		 4615 new_mode = drm_mode_duplicate(dev, mode);
4616 if (!new_mode)
4617 continue;
4618
f7e121b7 4619 new_mode->flags |= mandatory->flags;
c858cfca
DL		 4620 list_add_tail(&new_mode->head, &stereo_modes);
4621 modes++;
f7e121b7 4622 }
c858cfca
DL		 4623 }
4624
4625 list_splice_tail(&stereo_modes, &connector->probed_modes);
4626
4627 return modes;
4628}
4629
1deee8d7
DL		 4630static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
4631{
4632 struct drm_device *dev = connector->dev;
4633 struct drm_display_mode *newmode;
4634
d9278b4c 4635 if (!drm_valid_hdmi_vic(vic)) {
e1e7bc48
JN		 4636 drm_err(connector->dev, "[CONNECTOR:%d:%s] Unknown HDMI VIC: %d\n",
4637 connector->base.id, connector->name, vic);
1deee8d7
DL		 4638 return 0;
4639 }
4640
4641 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
4642 if (!newmode)
4643 return 0;
4644
4645 drm_mode_probed_add(connector, newmode);
4646
4647 return 1;
4648}
4649
fbf46025 4650static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
6a40a75f 4651 int vic_index)
fbf46025 4652{
fbf46025
TW		 4653 struct drm_display_mode *newmode;
4654 int modes = 0;
fbf46025
TW		 4655
4656 if (structure & (1 << 0)) {
6a40a75f 4657 newmode = drm_display_mode_from_vic_index(connector, vic_index);
fbf46025
TW		 4658 if (newmode) {
4659 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
4660 drm_mode_probed_add(connector, newmode);
4661 modes++;
4662 }
4663 }
4664 if (structure & (1 << 6)) {
6a40a75f 4665 newmode = drm_display_mode_from_vic_index(connector, vic_index);
fbf46025
TW		 4666 if (newmode) {
4667 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4668 drm_mode_probed_add(connector, newmode);
4669 modes++;
4670 }
4671 }
4672 if (structure & (1 << 8)) {
6a40a75f 4673 newmode = drm_display_mode_from_vic_index(connector, vic_index);
fbf46025 4674 if (newmode) {
89570eeb 4675 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
fbf46025
TW		 4676 drm_mode_probed_add(connector, newmode);
4677 modes++;
4678 }
4679 }
4680
4681 return modes;
4682}
4683
1ee3e217
JN		 4684static bool hdmi_vsdb_latency_present(const u8 *db)
4685{
4686 return db[8] & BIT(7);
4687}
4688
4689static bool hdmi_vsdb_i_latency_present(const u8 *db)
4690{
4691 return hdmi_vsdb_latency_present(db) && db[8] & BIT(6);
4692}
4693
cba83c1f
JN		 4694static int hdmi_vsdb_latency_length(const u8 *db)
4695{
4696 if (hdmi_vsdb_i_latency_present(db))
4697 return 4;
4698 else if (hdmi_vsdb_latency_present(db))
4699 return 2;
4700 else
4701 return 0;
4702}
4703
7ebe1963
LD		 4704/*
4705 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
4706 * @connector: connector corresponding to the HDMI sink
4707 * @db: start of the CEA vendor specific block
4708 * @len: length of the CEA block payload, ie. one can access up to db[len]
4709 *
c858cfca
DL		 4710 * Parses the HDMI VSDB looking for modes to add to @connector. This function
4711 * also adds the stereo 3d modes when applicable.
7ebe1963
LD		 4712 */
4713static int
6a40a75f 4714do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len)
7ebe1963 4715{
0e5083aa 4716 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
fbf46025
TW		 4717 u8 vic_len, hdmi_3d_len = 0;
4718 u16 mask;
4719 u16 structure_all;
7ebe1963
LD		 4720
4721 if (len < 8)
4722 goto out;
4723
4724 /* no HDMI_Video_Present */
4725 if (!(db[8] & (1 << 5)))
4726 goto out;
4727
cba83c1f 4728 offset += hdmi_vsdb_latency_length(db);
7ebe1963
LD		 4729
4730 /* the declared length is not long enough for the 2 first bytes
4731 * of additional video format capabilities */
c858cfca 4732 if (len < (8 + offset + 2))
7ebe1963
LD		 4733 goto out;
4734
c858cfca
DL		 4735 /* 3D_Present */
4736 offset++;
fbf46025 4737 if (db[8 + offset] & (1 << 7)) {
c858cfca
DL		 4738 modes += add_hdmi_mandatory_stereo_modes(connector);
4739
fbf46025
TW		 4740 /* 3D_Multi_present */
4741 multi_present = (db[8 + offset] & 0x60) >> 5;
4742 }
4743
c858cfca 4744 offset++;
7ebe1963 4745 vic_len = db[8 + offset] >> 5;
fbf46025 4746 hdmi_3d_len = db[8 + offset] & 0x1f;
7ebe1963
LD		 4747
4748 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
7ebe1963
LD		 4749 u8 vic;
4750
4751 vic = db[9 + offset + i];
1deee8d7 4752 modes += add_hdmi_mode(connector, vic);
7ebe1963 4753 }
fbf46025
TW		 4754 offset += 1 + vic_len;
4755
0e5083aa
TW		 4756 if (multi_present == 1)
4757 multi_len = 2;
4758 else if (multi_present == 2)
4759 multi_len = 4;
4760 else
4761 multi_len = 0;
fbf46025 4762
0e5083aa 4763 if (len < (8 + offset + hdmi_3d_len - 1))
fbf46025
TW		 4764 goto out;
4765
0e5083aa 4766 if (hdmi_3d_len < multi_len)
fbf46025
TW		 4767 goto out;
4768
0e5083aa
TW		 4769 if (multi_present == 1 || multi_present == 2) {
4770 /* 3D_Structure_ALL */
4771 structure_all = (db[8 + offset] << 8) | db[9 + offset];
fbf46025 4772
0e5083aa
TW		 4773 /* check if 3D_MASK is present */
4774 if (multi_present == 2)
4775 mask = (db[10 + offset] << 8) | db[11 + offset];
4776 else
4777 mask = 0xffff;
4778
4779 for (i = 0; i < 16; i++) {
4780 if (mask & (1 << i))
4781 modes += add_3d_struct_modes(connector,
6a40a75f 4782 structure_all, i);
0e5083aa
TW		 4783 }
4784 }
4785
4786 offset += multi_len;
4787
4788 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
4789 int vic_index;
4790 struct drm_display_mode *newmode = NULL;
4791 unsigned int newflag = 0;
4792 bool detail_present;
4793
4794 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
4795
4796 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
4797 break;
4798
4799 /* 2D_VIC_order_X */
4800 vic_index = db[8 + offset + i] >> 4;
4801
4802 /* 3D_Structure_X */
4803 switch (db[8 + offset + i] & 0x0f) {
4804 case 0:
4805 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
4806 break;
4807 case 6:
4808 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4809 break;
4810 case 8:
4811 /* 3D_Detail_X */
4812 if ((db[9 + offset + i] >> 4) == 1)
4813 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4814 break;
4815 }
4816
4817 if (newflag != 0) {
4818 newmode = drm_display_mode_from_vic_index(connector,
0e5083aa
TW		 4819 vic_index);
4820
4821 if (newmode) {
4822 newmode->flags |= newflag;
4823 drm_mode_probed_add(connector, newmode);
4824 modes++;
4825 }
4826 }
4827
4828 if (detail_present)
4829 i++;
fbf46025 4830 }
7ebe1963
LD		 4831
4832out:
4833 return modes;
4834}
4835
9e50b9d5
VS		 4836static int
4837cea_revision(const u8 *cea)
4838{
5036c0d0
VS		 4839 /*
4840 * FIXME is this correct for the DispID variant?
4841 * The DispID spec doesn't really specify whether
4842 * this is the revision of the CEA extension or
4843 * the DispID CEA data block. And the only value
4844 * given as an example is 0.
4845 */
9e50b9d5
VS		 4846 return cea[1];
4847}
4848
aba58254
JN		 4849/*
4850 * CTA Data Block iterator.
4851 *
4852 * Iterate through all CTA Data Blocks in both EDID CTA Extensions and DisplayID
4853 * CTA Data Blocks.
4854 *
4855 * struct cea_db *db:
4856 * struct cea_db_iter iter;
4857 *
4858 * cea_db_iter_edid_begin(edid, &iter);
4859 * cea_db_iter_for_each(db, &iter) {
4860 * // do stuff with db
4861 * }
4862 * cea_db_iter_end(&iter);
4863 */
4864struct cea_db_iter {
4865 struct drm_edid_iter edid_iter;
4866 struct displayid_iter displayid_iter;
4867
4868 /* Current Data Block Collection. */
4869 const u8 *collection;
4870
4871 /* Current Data Block index in current collection. */
4872 int index;
4873
4874 /* End index in current collection. */
4875 int end;
4876};
4877
4878/* CTA-861-H section 7.4 CTA Data BLock Collection */
4879struct cea_db {
4880 u8 tag_length;
4881 u8 data[];
4882} __packed;
4883
49a62a29 4884static int cea_db_tag(const struct cea_db *db)
aba58254 4885{
aba58254
JN		 4886 return db->tag_length >> 5;
4887}
4888
4889static int cea_db_payload_len(const void *_db)
4890{
4891 /* FIXME: Transition to passing struct cea_db * everywhere. */
4892 const struct cea_db *db = _db;
4893
4894 return db->tag_length & 0x1f;
4895}
4896
4897static const void *cea_db_data(const struct cea_db *db)
4898{
4899 return db->data;
4900}
4901
a9ec4fd0
JN		 4902static bool cea_db_is_extended_tag(const struct cea_db *db, int tag)
4903{
4904 return cea_db_tag(db) == CTA_DB_EXTENDED_TAG &&
4905 cea_db_payload_len(db) >= 1 &&
4906 db->data[0] == tag;
4907}
4908
4909static bool cea_db_is_vendor(const struct cea_db *db, int vendor_oui)
4910{
4911 const u8 *data = cea_db_data(db);
4912
4913 return cea_db_tag(db) == CTA_DB_VENDOR &&
4914 cea_db_payload_len(db) >= 3 &&
4915 oui(data[2], data[1], data[0]) == vendor_oui;
4916}
4917
5e87b2e5
JN		 4918static void cea_db_iter_edid_begin(const struct drm_edid *drm_edid,
4919 struct cea_db_iter *iter)
aba58254
JN		 4920{
4921 memset(iter, 0, sizeof(*iter));
4922
bbded689 4923 drm_edid_iter_begin(drm_edid, &iter->edid_iter);
d9ba1b4c 4924 displayid_iter_edid_begin(drm_edid, &iter->displayid_iter);
aba58254
JN		 4925}
4926
4927static const struct cea_db *
4928__cea_db_iter_current_block(const struct cea_db_iter *iter)
4929{
4930 const struct cea_db *db;
4931
4932 if (!iter->collection)
4933 return NULL;
4934
4935 db = (const struct cea_db *)&iter->collection[iter->index];
4936
4937 if (iter->index + sizeof(*db) <= iter->end &&
4938 iter->index + sizeof(*db) + cea_db_payload_len(db) <= iter->end)
4939 return db;
4940
4941 return NULL;
4942}
4943
11a8d095
JN		 4944/*
4945 * References:
4946 * - CTA-861-H section 7.3.3 CTA Extension Version 3
4947 */
4948static int cea_db_collection_size(const u8 *cta)
4949{
4950 u8 d = cta[2];
4951
4952 if (d < 4 || d > 127)
4953 return 0;
4954
4955 return d - 4;
4956}
4957
aba58254
JN		 4958/*
4959 * References:
4960 * - VESA E-EDID v1.4
4961 * - CTA-861-H section 7.3.3 CTA Extension Version 3
4962 */
4963static const void *__cea_db_iter_edid_next(struct cea_db_iter *iter)
4964{
4965 const u8 *ext;
4966
4967 drm_edid_iter_for_each(ext, &iter->edid_iter) {
11a8d095
JN		 4968 int size;
4969
aba58254
JN		 4970 /* Only support CTA Extension revision 3+ */
4971 if (ext[0] != CEA_EXT || cea_revision(ext) < 3)
4972 continue;
4973
11a8d095
JN		 4974 size = cea_db_collection_size(ext);
4975 if (!size)
aba58254
JN		 4976 continue;
4977
11a8d095
JN		 4978 iter->index = 4;
4979 iter->end = iter->index + size;
4980
aba58254
JN		 4981 return ext;
4982 }
4983
4984 return NULL;
4985}
4986
4987/*
4988 * References:
4989 * - DisplayID v1.3 Appendix C: CEA Data Block within a DisplayID Data Block
4990 * - DisplayID v2.0 section 4.10 CTA DisplayID Data Block
4991 *
4992 * Note that the above do not specify any connection between DisplayID Data
4993 * Block revision and CTA Extension versions.
4994 */
4995static const void *__cea_db_iter_displayid_next(struct cea_db_iter *iter)
4996{
4997 const struct displayid_block *block;
4998
4999 displayid_iter_for_each(block, &iter->displayid_iter) {
5000 if (block->tag != DATA_BLOCK_CTA)
5001 continue;
5002
5003 /*
5004 * The displayid iterator has already verified the block bounds
5005 * in displayid_iter_block().
5006 */
5007 iter->index = sizeof(*block);
5008 iter->end = iter->index + block->num_bytes;
5009
5010 return block;
5011 }
5012
5013 return NULL;
5014}
5015
5016static const struct cea_db *__cea_db_iter_next(struct cea_db_iter *iter)
5017{
5018 const struct cea_db *db;
5019
5020 if (iter->collection) {
5021 /* Current collection should always be valid. */
5022 db = __cea_db_iter_current_block(iter);
5023 if (WARN_ON(!db)) {
5024 iter->collection = NULL;
5025 return NULL;
5026 }
5027
5028 /* Next block in CTA Data Block Collection */
5029 iter->index += sizeof(*db) + cea_db_payload_len(db);
5030
5031 db = __cea_db_iter_current_block(iter);
5032 if (db)
5033 return db;
5034 }
5035
5036 for (;;) {
5037 /*
5038 * Find the next CTA Data Block Collection. First iterate all
5039 * the EDID CTA Extensions, then all the DisplayID CTA blocks.
5040 *
5041 * Per DisplayID v1.3 Appendix B: DisplayID as an EDID
5042 * Extension, it's recommended that DisplayID extensions are
5043 * exposed after all of the CTA Extensions.
5044 */
5045 iter->collection = __cea_db_iter_edid_next(iter);
5046 if (!iter->collection)
5047 iter->collection = __cea_db_iter_displayid_next(iter);
5048
5049 if (!iter->collection)
5050 return NULL;
5051
5052 db = __cea_db_iter_current_block(iter);
5053 if (db)
5054 return db;
5055 }
5056}
5057
5058#define cea_db_iter_for_each(__db, __iter) \
5059 while (((__db) = __cea_db_iter_next(__iter)))
5060
5061static void cea_db_iter_end(struct cea_db_iter *iter)
5062{
5063 displayid_iter_end(&iter->displayid_iter);
5064 drm_edid_iter_end(&iter->edid_iter);
5065
5066 memset(iter, 0, sizeof(*iter));
5067}
5068
49a62a29 5069static bool cea_db_is_hdmi_vsdb(const struct cea_db *db)
7ebe1963 5070{
a9ec4fd0
JN		 5071 return cea_db_is_vendor(db, HDMI_IEEE_OUI) &&
5072 cea_db_payload_len(db) >= 5;
7ebe1963
LD		 5073}
5074
49a62a29 5075static bool cea_db_is_hdmi_forum_vsdb(const struct cea_db *db)
50dd1bd1 5076{
a9ec4fd0
JN		 5077 return cea_db_is_vendor(db, HDMI_FORUM_IEEE_OUI) &&
5078 cea_db_payload_len(db) >= 7;
50dd1bd1
TR		 5079}
5080
18e3c1d5
JN		 5081static bool cea_db_is_hdmi_forum_eeodb(const void *db)
5082{
5083 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_EEODB) &&
5084 cea_db_payload_len(db) >= 2;
5085}
5086
49a62a29 5087static bool cea_db_is_microsoft_vsdb(const struct cea_db *db)
2869f599 5088{
a9ec4fd0
JN		 5089 return cea_db_is_vendor(db, MICROSOFT_IEEE_OUI) &&
5090 cea_db_payload_len(db) == 21;
2869f599
PZ		 5091}
5092
49a62a29 5093static bool cea_db_is_vcdb(const struct cea_db *db)
1581b2df 5094{
a9ec4fd0
JN		 5095 return cea_db_is_extended_tag(db, CTA_EXT_DB_VIDEO_CAP) &&
5096 cea_db_payload_len(db) == 2;
1581b2df
VS		 5097}
5098
49a62a29 5099static bool cea_db_is_hdmi_forum_scdb(const struct cea_db *db)
115fcf58 5100{
a9ec4fd0
JN		 5101 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_SCDB) &&
5102 cea_db_payload_len(db) >= 7;
115fcf58
LS		 5103}
5104
49a62a29 5105static bool cea_db_is_y420cmdb(const struct cea_db *db)
832d4f2f 5106{
a9ec4fd0 5107 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_CAP_MAP);
832d4f2f
SS		 5108}
5109
49a62a29 5110static bool cea_db_is_y420vdb(const struct cea_db *db)
832d4f2f 5111{
a9ec4fd0
JN		 5112 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_DATA);
5113}
832d4f2f 5114
49a62a29 5115static bool cea_db_is_hdmi_hdr_metadata_block(const struct cea_db *db)
a9ec4fd0
JN		 5116{
5117 return cea_db_is_extended_tag(db, CTA_EXT_DB_HDR_STATIC_METADATA) &&
5118 cea_db_payload_len(db) >= 3;
832d4f2f
SS		 5119}
5120
18e3c1d5
JN		 5121/*
5122 * Get the HF-EEODB override extension block count from EDID.
5123 *
5124 * The passed in EDID may be partially read, as long as it has at least two
5125 * blocks (base block and one extension block) if EDID extension count is > 0.
5126 *
5127 * Note that this is *not* how you should parse CTA Data Blocks in general; this
5128 * is only to handle partially read EDIDs. Normally, use the CTA Data Block
5129 * iterators instead.
5130 *
5131 * References:
5132 * - HDMI 2.1 section 10.3.6 HDMI Forum EDID Extension Override Data Block
5133 */
5134static int edid_hfeeodb_extension_block_count(const struct edid *edid)
5135{
5136 const u8 *cta;
5137
5138 /* No extensions according to base block, no HF-EEODB. */
5139 if (!edid_extension_block_count(edid))
5140 return 0;
5141
5142 /* HF-EEODB is always in the first EDID extension block only */
5143 cta = edid_extension_block_data(edid, 0);
5144 if (edid_block_tag(cta) != CEA_EXT || cea_revision(cta) < 3)
5145 return 0;
5146
5147 /* Need to have the data block collection, and at least 3 bytes. */
5148 if (cea_db_collection_size(cta) < 3)
5149 return 0;
5150
5151 /*
5152 * Sinks that include the HF-EEODB in their E-EDID shall include one and
5153 * only one instance of the HF-EEODB in the E-EDID, occupying bytes 4
5154 * through 6 of Block 1 of the E-EDID.
5155 */
5156 if (!cea_db_is_hdmi_forum_eeodb(&cta[4]))
5157 return 0;
5158
5159 return cta[4 + 2];
5160}
5161
61e05fdc
JN		 5162/*
5163 * CTA-861 YCbCr 4:2:0 Capability Map Data Block (CTA Y420CMDB)
5164 *
5165 * Y420CMDB contains a bitmap which gives the index of CTA modes from CTA VDB,
5166 * which can support YCBCR 420 sampling output also (apart from RGB/YCBCR444
5167 * etc). For example, if the bit 0 in bitmap is set, first mode in VDB can
5168 * support YCBCR420 output too.
5169 */
5170static void parse_cta_y420cmdb(struct drm_connector *connector,
5171 const struct cea_db *db, u64 *y420cmdb_map)
832d4f2f
SS		 5172{
5173 struct drm_display_info *info = &connector->display_info;
61e05fdc
JN		 5174 int i, map_len = cea_db_payload_len(db) - 1;
5175 const u8 *data = cea_db_data(db) + 1;
832d4f2f
SS		 5176 u64 map = 0;
5177
5178 if (map_len == 0) {
5179 /* All CEA modes support ycbcr420 sampling also.*/
61e05fdc
JN		 5180 map = U64_MAX;
5181 goto out;
832d4f2f
SS		 5182 }
5183
5184 /*
5185 * This map indicates which of the existing CEA block modes
5186 * from VDB can support YCBCR420 output too. So if bit=0 is
5187 * set, first mode from VDB can support YCBCR420 output too.
5188 * We will parse and keep this map, before parsing VDB itself
5189 * to avoid going through the same block again and again.
5190 *
5191 * Spec is not clear about max possible size of this block.
5192 * Clamping max bitmap block size at 8 bytes. Every byte can
5193 * address 8 CEA modes, in this way this map can address
5194 * 8*8 = first 64 SVDs.
5195 */
5196 if (WARN_ON_ONCE(map_len > 8))
5197 map_len = 8;
5198
61e05fdc
JN		 5199 for (i = 0; i < map_len; i++)
5200 map |= (u64)data[i] << (8 * i);
832d4f2f 5201
61e05fdc 5202out:
832d4f2f 5203 if (map)
c03d0b52 5204 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
832d4f2f 5205
61e05fdc 5206 *y420cmdb_map = map;
832d4f2f
SS		 5207}
5208
40f71f5b
JN		 5209static int add_cea_modes(struct drm_connector *connector,
5210 const struct drm_edid *drm_edid)
54ac76f8 5211{
537d9ed2
JN		 5212 const struct cea_db *db;
5213 struct cea_db_iter iter;
6a40a75f
JN		 5214 int modes;
5215
5216 /* CTA VDB block VICs parsed earlier */
5217 modes = add_cta_vdb_modes(connector);
54ac76f8 5218
5e87b2e5 5219 cea_db_iter_edid_begin(drm_edid, &iter);
537d9ed2 5220 cea_db_iter_for_each(db, &iter) {
6a40a75f
JN		 5221 if (cea_db_is_hdmi_vsdb(db)) {
5222 modes += do_hdmi_vsdb_modes(connector, (const u8 *)db,
5223 cea_db_payload_len(db));
537d9ed2
JN		 5224 } else if (cea_db_is_y420vdb(db)) {
5225 const u8 *vdb420 = cea_db_data(db) + 1;
5226
5227 /* Add 4:2:0(only) modes present in EDID */
5228 modes += do_y420vdb_modes(connector, vdb420,
5229 cea_db_payload_len(db) - 1);
54ac76f8 5230 }
537d9ed2
JN		 5231 }
5232 cea_db_iter_end(&iter);
c858cfca 5233
54ac76f8
CS		 5234 return modes;
5235}
5236
e1e7bc48
JN		 5237static void fixup_detailed_cea_mode_clock(struct drm_connector *connector,
5238 struct drm_display_mode *mode)
fa3a7340
VS		 5239{
5240 const struct drm_display_mode *cea_mode;
5241 int clock1, clock2, clock;
d9278b4c 5242 u8 vic;
fa3a7340
VS		 5243 const char *type;
5244
4c6bcf44
VS		 5245 /*
5246 * allow 5kHz clock difference either way to account for
5247 * the 10kHz clock resolution limit of detailed timings.
5248 */
d9278b4c
JN		 5249 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
5250 if (drm_valid_cea_vic(vic)) {
fa3a7340 5251 type = "CEA";
7befe621 5252 cea_mode = cea_mode_for_vic(vic);
fa3a7340
VS		 5253 clock1 = cea_mode->clock;
5254 clock2 = cea_mode_alternate_clock(cea_mode);
5255 } else {
d9278b4c
JN		 5256 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
5257 if (drm_valid_hdmi_vic(vic)) {
fa3a7340 5258 type = "HDMI";
d9278b4c 5259 cea_mode = &edid_4k_modes[vic];
fa3a7340
VS		 5260 clock1 = cea_mode->clock;
5261 clock2 = hdmi_mode_alternate_clock(cea_mode);
5262 } else {
5263 return;
5264 }
5265 }
5266
5267 /* pick whichever is closest */
5268 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
5269 clock = clock1;
5270 else
5271 clock = clock2;
5272
5273 if (mode->clock == clock)
5274 return;
5275
e1e7bc48
JN		 5276 drm_dbg_kms(connector->dev,
5277 "[CONNECTOR:%d:%s] detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
5278 connector->base.id, connector->name,
5279 type, vic, mode->clock, clock);
fa3a7340
VS		 5280 mode->clock = clock;
5281}
5282
82068ede
JH		 5283static void drm_calculate_luminance_range(struct drm_connector *connector)
5284{
5285 struct hdr_static_metadata *hdr_metadata = &connector->hdr_sink_metadata.hdmi_type1;
5286 struct drm_luminance_range_info *luminance_range =
5287 &connector->display_info.luminance_range;
5288 static const u8 pre_computed_values[] = {
5289 50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69,
5290 71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98
5291 };
5292 u32 max_avg, min_cll, max, min, q, r;
5293
5294 if (!(hdr_metadata->metadata_type & BIT(HDMI_STATIC_METADATA_TYPE1)))
5295 return;
5296
5297 max_avg = hdr_metadata->max_fall;
5298 min_cll = hdr_metadata->min_cll;
5299
5300 /*
5301 * From the specification (CTA-861-G), for calculating the maximum
5302 * luminance we need to use:
5303 * Luminance = 50*2**(CV/32)
5304 * Where CV is a one-byte value.
5305 * For calculating this expression we may need float point precision;
5306 * to avoid this complexity level, we take advantage that CV is divided
5307 * by a constant. From the Euclids division algorithm, we know that CV
5308 * can be written as: CV = 32*q + r. Next, we replace CV in the
5309 * Luminance expression and get 50*(2**q)*(2**(r/32)), hence we just
5310 * need to pre-compute the value of r/32. For pre-computing the values
5311 * We just used the following Ruby line:
5312 * (0...32).each {|cv| puts (50*2**(cv/32.0)).round}
5313 * The results of the above expressions can be verified at
5314 * pre_computed_values.
5315 */
5316 q = max_avg >> 5;
5317 r = max_avg % 32;
5318 max = (1 << q) * pre_computed_values[r];
5319
5320 /* min luminance: maxLum * (CV/255)^2 / 100 */
5321 q = DIV_ROUND_CLOSEST(min_cll, 255);
5322 min = max * DIV_ROUND_CLOSEST((q * q), 100);
5323
5324 luminance_range->min_luminance = min;
5325 luminance_range->max_luminance = max;
5326}
5327
e85959d6
US		 5328static uint8_t eotf_supported(const u8 *edid_ext)
5329{
5330 return edid_ext[2] &
5331 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
5332 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
b5e3eed1
VS		 5333 BIT(HDMI_EOTF_SMPTE_ST2084) |
5334 BIT(HDMI_EOTF_BT_2100_HLG));
e85959d6
US		 5335}
5336
5337static uint8_t hdr_metadata_type(const u8 *edid_ext)
5338{
5339 return edid_ext[3] &
5340 BIT(HDMI_STATIC_METADATA_TYPE1);
5341}
5342
5343static void
5344drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
5345{
5346 u16 len;
5347
5348 len = cea_db_payload_len(db);
5349
5350 connector->hdr_sink_metadata.hdmi_type1.eotf =
5351 eotf_supported(db);
5352 connector->hdr_sink_metadata.hdmi_type1.metadata_type =
5353 hdr_metadata_type(db);
5354
5355 if (len >= 4)
5356 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4];
5357 if (len >= 5)
5358 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5];
82068ede 5359 if (len >= 6) {
e85959d6 5360 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6];
82068ede
JH		 5361
5362 /* Calculate only when all values are available */
5363 drm_calculate_luminance_range(connector);
5364 }
e85959d6
US		 5365}
5366
1ee3e217 5367/* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */
76adaa34 5368static void
23ebf8b9 5369drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
76adaa34 5370{
8504072a 5371 u8 len = cea_db_payload_len(db);
76adaa34 5372
f7da7785
JN		 5373 if (len >= 6 && (db[6] & (1 << 7)))
5374 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
1ee3e217
JN		 5375
5376 if (len >= 10 && hdmi_vsdb_latency_present(db)) {
5377 connector->latency_present[0] = true;
8504072a 5378 connector->video_latency[0] = db[9];
8504072a 5379 connector->audio_latency[0] = db[10];
1ee3e217
JN		 5380 }
5381
5382 if (len >= 12 && hdmi_vsdb_i_latency_present(db)) {
5383 connector->latency_present[1] = true;
8504072a 5384 connector->video_latency[1] = db[11];
8504072a 5385 connector->audio_latency[1] = db[12];
1ee3e217 5386 }
76adaa34 5387
e1e7bc48
JN		 5388 drm_dbg_kms(connector->dev,
5389 "[CONNECTOR:%d:%s] HDMI: latency present %d %d, video latency %d %d, audio latency %d %d\n",
5390 connector->base.id, connector->name,
5391 connector->latency_present[0], connector->latency_present[1],
5392 connector->video_latency[0], connector->video_latency[1],
5393 connector->audio_latency[0], connector->audio_latency[1]);
76adaa34
WF		 5394}
5395
5396static void
4194442d 5397monitor_name(const struct detailed_timing *timing, void *data)
76adaa34 5398{
4194442d
JN		 5399 const char **res = data;
5400
5401 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME))
a7a131ac
VS		 5402 return;
5403
4194442d 5404 *res = timing->data.other_data.data.str.str;
14f77fdd
VS		 5405}
5406
2c54f87c 5407static int get_monitor_name(const struct drm_edid *drm_edid, char name[13])
59f7c0fa 5408{
4194442d 5409 const char *edid_name = NULL;
59f7c0fa
JB		 5410 int mnl;
5411
2c54f87c 5412 if (!drm_edid || !name)
59f7c0fa
JB		 5413 return 0;
5414
45aa2336 5415 drm_for_each_detailed_block(drm_edid, monitor_name, &edid_name);
59f7c0fa
JB		 5416 for (mnl = 0; edid_name && mnl < 13; mnl++) {
5417 if (edid_name[mnl] == 0x0a)
5418 break;
5419
5420 name[mnl] = edid_name[mnl];
5421 }
5422
5423 return mnl;
5424}
5425
5426/**
5427 * drm_edid_get_monitor_name - fetch the monitor name from the edid
5428 * @edid: monitor EDID information
5429 * @name: pointer to a character array to hold the name of the monitor
5430 * @bufsize: The size of the name buffer (should be at least 14 chars.)
5431 *
5432 */
f4e558ec 5433void drm_edid_get_monitor_name(const struct edid *edid, char *name, int bufsize)
59f7c0fa 5434{
2c54f87c 5435 int name_length = 0;
4d23f484 5436
59f7c0fa
JB		 5437 if (bufsize <= 0)
5438 return;
5439
2c54f87c
JN		 5440 if (edid) {
5441 char buf[13];
5442 struct drm_edid drm_edid = {
5443 .edid = edid,
5444 .size = edid_size(edid),
5445 };
5446
5447 name_length = min(get_monitor_name(&drm_edid, buf), bufsize - 1);
5448 memcpy(name, buf, name_length);
5449 }
5450
59f7c0fa
JB		 5451 name[name_length] = '\0';
5452}
5453EXPORT_SYMBOL(drm_edid_get_monitor_name);
5454
42750d39
JN		 5455static void clear_eld(struct drm_connector *connector)
5456{
5457 memset(connector->eld, 0, sizeof(connector->eld));
5458
5459 connector->latency_present[0] = false;
5460 connector->latency_present[1] = false;
5461 connector->video_latency[0] = 0;
5462 connector->audio_latency[0] = 0;
5463 connector->video_latency[1] = 0;
5464 connector->audio_latency[1] = 0;
5465}
5466
79436a1c 5467/*
76adaa34
WF		 5468 * drm_edid_to_eld - build ELD from EDID
5469 * @connector: connector corresponding to the HDMI/DP sink
a2f9790d 5470 * @drm_edid: EDID to parse
76adaa34 5471 *
db6cf833 5472 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
1d1c3665 5473 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
76adaa34 5474 */
f4e558ec 5475static void drm_edid_to_eld(struct drm_connector *connector,
a2f9790d 5476 const struct drm_edid *drm_edid)
76adaa34 5477{
58304630 5478 const struct drm_display_info *info = &connector->display_info;
37852141
JN		 5479 const struct cea_db *db;
5480 struct cea_db_iter iter;
76adaa34 5481 uint8_t *eld = connector->eld;
7c018782 5482 int total_sad_count = 0;
76adaa34 5483 int mnl;
76adaa34 5484
a2f9790d 5485 if (!drm_edid)
e9bd0b84
JN		 5486 return;
5487
2c54f87c 5488 mnl = get_monitor_name(drm_edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
e1e7bc48
JN		 5489 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD monitor %s\n",
5490 connector->base.id, connector->name,
5491 &eld[DRM_ELD_MONITOR_NAME_STRING]);
59f7c0fa 5492
58304630 5493 eld[DRM_ELD_CEA_EDID_VER_MNL] = info->cea_rev << DRM_ELD_CEA_EDID_VER_SHIFT;
f7da7785 5494 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
76adaa34 5495
f7da7785 5496 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
76adaa34 5497
a2f9790d
JN		 5498 eld[DRM_ELD_MANUFACTURER_NAME0] = drm_edid->edid->mfg_id[0];
5499 eld[DRM_ELD_MANUFACTURER_NAME1] = drm_edid->edid->mfg_id[1];
5500 eld[DRM_ELD_PRODUCT_CODE0] = drm_edid->edid->prod_code[0];
5501 eld[DRM_ELD_PRODUCT_CODE1] = drm_edid->edid->prod_code[1];
76adaa34 5502
5e87b2e5 5503 cea_db_iter_edid_begin(drm_edid, &iter);
37852141
JN		 5504 cea_db_iter_for_each(db, &iter) {
5505 const u8 *data = cea_db_data(db);
5506 int len = cea_db_payload_len(db);
deec222e 5507 int sad_count;
9e50b9d5 5508
37852141
JN		 5509 switch (cea_db_tag(db)) {
5510 case CTA_DB_AUDIO:
5511 /* Audio Data Block, contains SADs */
5512 sad_count = min(len / 3, 15 - total_sad_count);
5513 if (sad_count >= 1)
5514 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
5515 data, sad_count * 3);
5516 total_sad_count += sad_count;
5517 break;
5518 case CTA_DB_SPEAKER:
5519 /* Speaker Allocation Data Block */
5520 if (len >= 1)
5521 eld[DRM_ELD_SPEAKER] = data[0];
5522 break;
5523 case CTA_DB_VENDOR:
5524 /* HDMI Vendor-Specific Data Block */
5525 if (cea_db_is_hdmi_vsdb(db))
5526 drm_parse_hdmi_vsdb_audio(connector, (const u8 *)db);
5527 break;
5528 default:
5529 break;
76adaa34 5530 }
9e50b9d5 5531 }
37852141
JN		 5532 cea_db_iter_end(&iter);
5533
f7da7785 5534 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
76adaa34 5535
1d1c3665
JN		 5536 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5537 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5538 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
5539 else
5540 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
76adaa34 5541
938fd8aa
JN		 5542 eld[DRM_ELD_BASELINE_ELD_LEN] =
5543 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
5544
e1e7bc48
JN		 5545 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD size %d, SAD count %d\n",
5546 connector->base.id, connector->name,
5547 drm_eld_size(eld), total_sad_count);
76adaa34 5548}
76adaa34 5549
bba4b647
JN		 5550static int _drm_edid_to_sad(const struct drm_edid *drm_edid,
5551 struct cea_sad **sads)
fe214163 5552{
b07debc2
JN		 5553 const struct cea_db *db;
5554 struct cea_db_iter iter;
fe214163 5555 int count = 0;
fe214163 5556
5e87b2e5 5557 cea_db_iter_edid_begin(drm_edid, &iter);
b07debc2 5558 cea_db_iter_for_each(db, &iter) {
9d72b7e2 5559 if (cea_db_tag(db) == CTA_DB_AUDIO) {
fe214163 5560 int j;
948de842 5561
b07debc2 5562 count = cea_db_payload_len(db) / 3; /* SAD is 3B */
fe214163
RM		 5563 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
5564 if (!*sads)
5565 return -ENOMEM;
5566 for (j = 0; j < count; j++) {
b07debc2 5567 const u8 *sad = &db->data[j * 3];
fe214163
RM		 5568
5569 (*sads)[j].format = (sad[0] & 0x78) >> 3;
5570 (*sads)[j].channels = sad[0] & 0x7;
5571 (*sads)[j].freq = sad[1] & 0x7F;
5572 (*sads)[j].byte2 = sad[2];
5573 }
5574 break;
5575 }
5576 }
b07debc2
JN		 5577 cea_db_iter_end(&iter);
5578
5579 DRM_DEBUG_KMS("Found %d Short Audio Descriptors\n", count);
fe214163
RM		 5580
5581 return count;
5582}
bba4b647
JN		 5583
5584/**
5585 * drm_edid_to_sad - extracts SADs from EDID
5586 * @edid: EDID to parse
5587 * @sads: pointer that will be set to the extracted SADs
5588 *
5589 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
5590 *
5591 * Note: The returned pointer needs to be freed using kfree().
5592 *
5593 * Return: The number of found SADs or negative number on error.
5594 */
5595int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads)
5596{
5597 struct drm_edid drm_edid;
5598
5599 return _drm_edid_to_sad(drm_edid_legacy_init(&drm_edid, edid), sads);
5600}
fe214163
RM		 5601EXPORT_SYMBOL(drm_edid_to_sad);
5602
02703451
JN		 5603static int _drm_edid_to_speaker_allocation(const struct drm_edid *drm_edid,
5604 u8 **sadb)
d105f476 5605{
ed317307
JN		 5606 const struct cea_db *db;
5607 struct cea_db_iter iter;
d105f476 5608 int count = 0;
d105f476 5609
5e87b2e5 5610 cea_db_iter_edid_begin(drm_edid, &iter);
ed317307
JN		 5611 cea_db_iter_for_each(db, &iter) {
5612 if (cea_db_tag(db) == CTA_DB_SPEAKER &&
5613 cea_db_payload_len(db) == 3) {
5614 *sadb = kmemdup(db->data, cea_db_payload_len(db),
5615 GFP_KERNEL);
5616 if (!*sadb)
5617 return -ENOMEM;
5618 count = cea_db_payload_len(db);
5619 break;
d105f476
AD		 5620 }
5621 }
ed317307
JN		 5622 cea_db_iter_end(&iter);
5623
5624 DRM_DEBUG_KMS("Found %d Speaker Allocation Data Blocks\n", count);
d105f476
AD		 5625
5626 return count;
5627}
02703451
JN		 5628
5629/**
5630 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
5631 * @edid: EDID to parse
5632 * @sadb: pointer to the speaker block
5633 *
5634 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
5635 *
5636 * Note: The returned pointer needs to be freed using kfree().
5637 *
5638 * Return: The number of found Speaker Allocation Blocks or negative number on
5639 * error.
5640 */
5641int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb)
5642{
5643 struct drm_edid drm_edid;
5644
5645 return _drm_edid_to_speaker_allocation(drm_edid_legacy_init(&drm_edid, edid),
5646 sadb);
5647}
d105f476
AD		 5648EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
5649
76adaa34 5650/**
db6cf833 5651 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
76adaa34
WF		 5652 * @connector: connector associated with the HDMI/DP sink
5653 * @mode: the display mode
db6cf833
TR		 5654 *
5655 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
5656 * the sink doesn't support audio or video.
76adaa34
WF		 5657 */
5658int drm_av_sync_delay(struct drm_connector *connector,
3a818d35 5659 const struct drm_display_mode *mode)
76adaa34
WF		 5660{
5661 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
5662 int a, v;
5663
5664 if (!connector->latency_present[0])
5665 return 0;
5666 if (!connector->latency_present[1])
5667 i = 0;
5668
5669 a = connector->audio_latency[i];
5670 v = connector->video_latency[i];
5671
5672 /*
5673 * HDMI/DP sink doesn't support audio or video?
5674 */
5675 if (a == 255 || v == 255)
5676 return 0;
5677
5678 /*
5679 * Convert raw EDID values to millisecond.
5680 * Treat unknown latency as 0ms.
5681 */
5682 if (a)
5683 a = min(2 * (a - 1), 500);
5684 if (v)
5685 v = min(2 * (v - 1), 500);
5686
5687 return max(v - a, 0);
5688}
5689EXPORT_SYMBOL(drm_av_sync_delay);
5690
3176d092 5691static bool _drm_detect_hdmi_monitor(const struct drm_edid *drm_edid)
8fe9790d 5692{
4ce08703
JN		 5693 const struct cea_db *db;
5694 struct cea_db_iter iter;
5695 bool hdmi = false;
f23c20c8
ML		 5696
5697 /*
5698 * Because HDMI identifier is in Vendor Specific Block,
5699 * search it from all data blocks of CEA extension.
5700 */
5e87b2e5 5701 cea_db_iter_edid_begin(drm_edid, &iter);
4ce08703
JN		 5702 cea_db_iter_for_each(db, &iter) {
5703 if (cea_db_is_hdmi_vsdb(db)) {
5704 hdmi = true;
5705 break;
5706 }
f23c20c8 5707 }
4ce08703 5708 cea_db_iter_end(&iter);
f23c20c8 5709
4ce08703 5710 return hdmi;
f23c20c8 5711}
3176d092
JN		 5712
5713/**
5714 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
5715 * @edid: monitor EDID information
5716 *
5717 * Parse the CEA extension according to CEA-861-B.
5718 *
5719 * Drivers that have added the modes parsed from EDID to drm_display_info
5720 * should use &drm_display_info.is_hdmi instead of calling this function.
5721 *
5722 * Return: True if the monitor is HDMI, false if not or unknown.
5723 */
5724bool drm_detect_hdmi_monitor(const struct edid *edid)
5725{
5726 struct drm_edid drm_edid;
5727
5728 return _drm_detect_hdmi_monitor(drm_edid_legacy_init(&drm_edid, edid));
5729}
f23c20c8
ML		 5730EXPORT_SYMBOL(drm_detect_hdmi_monitor);
5731
0c057877 5732static bool _drm_detect_monitor_audio(const struct drm_edid *drm_edid)
8fe9790d 5733{
705bec3e 5734 struct drm_edid_iter edid_iter;
9975af04
JN		 5735 const struct cea_db *db;
5736 struct cea_db_iter iter;
43d16d84 5737 const u8 *edid_ext;
8fe9790d 5738 bool has_audio = false;
8fe9790d 5739
bbded689 5740 drm_edid_iter_begin(drm_edid, &edid_iter);
705bec3e
JN		 5741 drm_edid_iter_for_each(edid_ext, &edid_iter) {
5742 if (edid_ext[0] == CEA_EXT) {
5743 has_audio = edid_ext[3] & EDID_BASIC_AUDIO;
5744 if (has_audio)
5745 break;
5746 }
5747 }
5748 drm_edid_iter_end(&edid_iter);
8fe9790d
ZW		 5749
5750 if (has_audio) {
5751 DRM_DEBUG_KMS("Monitor has basic audio support\n");
5752 goto end;
5753 }
5754
5e87b2e5 5755 cea_db_iter_edid_begin(drm_edid, &iter);
9975af04
JN		 5756 cea_db_iter_for_each(db, &iter) {
5757 if (cea_db_tag(db) == CTA_DB_AUDIO) {
5758 const u8 *data = cea_db_data(db);
5759 int i;
8fe9790d 5760
9975af04 5761 for (i = 0; i < cea_db_payload_len(db); i += 3)
8fe9790d 5762 DRM_DEBUG_KMS("CEA audio format %d\n",
9975af04
JN		 5763 (data[i] >> 3) & 0xf);
5764 has_audio = true;
5765 break;
8fe9790d
ZW		 5766 }
5767 }
9975af04
JN		 5768 cea_db_iter_end(&iter);
5769
8fe9790d
ZW		 5770end:
5771 return has_audio;
5772}
0c057877
JN		 5773
5774/**
5775 * drm_detect_monitor_audio - check monitor audio capability
5776 * @edid: EDID block to scan
5777 *
5778 * Monitor should have CEA extension block.
5779 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
5780 * audio' only. If there is any audio extension block and supported
5781 * audio format, assume at least 'basic audio' support, even if 'basic
5782 * audio' is not defined in EDID.
5783 *
5784 * Return: True if the monitor supports audio, false otherwise.
5785 */
5786bool drm_detect_monitor_audio(const struct edid *edid)
5787{
5788 struct drm_edid drm_edid;
5789
5790 return _drm_detect_monitor_audio(drm_edid_legacy_init(&drm_edid, edid));
5791}
8fe9790d
ZW		 5792EXPORT_SYMBOL(drm_detect_monitor_audio);
5793
b1edd6a6 5794
c8127cf0
VS		 5795/**
5796 * drm_default_rgb_quant_range - default RGB quantization range
5797 * @mode: display mode
5798 *
5799 * Determine the default RGB quantization range for the mode,
5800 * as specified in CEA-861.
5801 *
5802 * Return: The default RGB quantization range for the mode
5803 */
5804enum hdmi_quantization_range
5805drm_default_rgb_quant_range(const struct drm_display_mode *mode)
5806{
5807 /* All CEA modes other than VIC 1 use limited quantization range. */
5808 return drm_match_cea_mode(mode) > 1 ?
5809 HDMI_QUANTIZATION_RANGE_LIMITED :
5810 HDMI_QUANTIZATION_RANGE_FULL;
5811}
5812EXPORT_SYMBOL(drm_default_rgb_quant_range);
5813
c3292ab5
JN		 5814/* CTA-861 Video Data Block (CTA VDB) */
5815static void parse_cta_vdb(struct drm_connector *connector, const struct cea_db *db)
5816{
5817 struct drm_display_info *info = &connector->display_info;
5818 int i, vic_index, len = cea_db_payload_len(db);
5819 const u8 *svds = cea_db_data(db);
5820 u8 *vics;
5821
5822 if (!len)
5823 return;
5824
5825 /* Gracefully handle multiple VDBs, however unlikely that is */
5826 vics = krealloc(info->vics, info->vics_len + len, GFP_KERNEL);
5827 if (!vics)
5828 return;
5829
5830 vic_index = info->vics_len;
5831 info->vics_len += len;
5832 info->vics = vics;
5833
5834 for (i = 0; i < len; i++) {
5835 u8 vic = svd_to_vic(svds[i]);
5836
5837 if (!drm_valid_cea_vic(vic))
5838 vic = 0;
5839
5840 info->vics[vic_index++] = vic;
5841 }
5842}
5843
61e05fdc
JN		 5844/*
5845 * Update y420_cmdb_modes based on previously parsed CTA VDB and Y420CMDB.
5846 *
5847 * Translate the y420cmdb_map based on VIC indexes to y420_cmdb_modes indexed
5848 * using the VICs themselves.
5849 */
5850static void update_cta_y420cmdb(struct drm_connector *connector, u64 y420cmdb_map)
5851{
5852 struct drm_display_info *info = &connector->display_info;
5853 struct drm_hdmi_info *hdmi = &info->hdmi;
5854 int i, len = min_t(int, info->vics_len, BITS_PER_TYPE(y420cmdb_map));
5855
5856 for (i = 0; i < len; i++) {
5857 u8 vic = info->vics[i];
5858
5859 if (vic && y420cmdb_map & BIT_ULL(i))
5860 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
5861 }
5862}
5863
4ed29f39
JN		 5864static bool cta_vdb_has_vic(const struct drm_connector *connector, u8 vic)
5865{
5866 const struct drm_display_info *info = &connector->display_info;
5867 int i;
5868
5869 if (!vic || !info->vics)
5870 return false;
5871
5872 for (i = 0; i < info->vics_len; i++) {
5873 if (info->vics[i] == vic)
5874 return true;
5875 }
5876
5877 return false;
5878}
5879
c54e2e23
JN		 5880/* CTA-861-H YCbCr 4:2:0 Video Data Block (CTA Y420VDB) */
5881static void parse_cta_y420vdb(struct drm_connector *connector,
5882 const struct cea_db *db)
5883{
5884 struct drm_display_info *info = &connector->display_info;
5885 struct drm_hdmi_info *hdmi = &info->hdmi;
5886 const u8 *svds = cea_db_data(db) + 1;
5887 int i;
5888
5889 for (i = 0; i < cea_db_payload_len(db) - 1; i++) {
5890 u8 vic = svd_to_vic(svds[i]);
5891
5892 if (!drm_valid_cea_vic(vic))
5893 continue;
5894
5895 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
5896 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
5897 }
5898}
5899
1581b2df
VS		 5900static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
5901{
5902 struct drm_display_info *info = &connector->display_info;
5903
e1e7bc48
JN		 5904 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] CEA VCDB 0x%02x\n",
5905 connector->base.id, connector->name, db[2]);
1581b2df
VS		 5906
5907 if (db[2] & EDID_CEA_VCDB_QS)
5908 info->rgb_quant_range_selectable = true;
5909}
5910
4499d488
SS		 5911static
5912void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane)
5913{
5914 switch (max_frl_rate) {
5915 case 1:
5916 *max_lanes = 3;
5917 *max_rate_per_lane = 3;
5918 break;
5919 case 2:
5920 *max_lanes = 3;
5921 *max_rate_per_lane = 6;
5922 break;
5923 case 3:
5924 *max_lanes = 4;
5925 *max_rate_per_lane = 6;
5926 break;
5927 case 4:
5928 *max_lanes = 4;
5929 *max_rate_per_lane = 8;
5930 break;
5931 case 5:
5932 *max_lanes = 4;
5933 *max_rate_per_lane = 10;
5934 break;
5935 case 6:
5936 *max_lanes = 4;
5937 *max_rate_per_lane = 12;
5938 break;
5939 case 0:
5940 default:
5941 *max_lanes = 0;
5942 *max_rate_per_lane = 0;
5943 }
5944}
5945
e6a9a2c3
SS		 5946static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
5947 const u8 *db)
5948{
5949 u8 dc_mask;
5950 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
5951
5952 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
9068e02f 5953 hdmi->y420_dc_modes = dc_mask;
e6a9a2c3
SS		 5954}
5955
5e706c4d
AN		 5956static void drm_parse_dsc_info(struct drm_hdmi_dsc_cap *hdmi_dsc,
5957 const u8 *hf_scds)
5958{
5e706c4d
AN		 5959 hdmi_dsc->v_1p2 = hf_scds[11] & DRM_EDID_DSC_1P2;
5960
5961 if (!hdmi_dsc->v_1p2)
5962 return;
5963
5964 hdmi_dsc->native_420 = hf_scds[11] & DRM_EDID_DSC_NATIVE_420;
5965 hdmi_dsc->all_bpp = hf_scds[11] & DRM_EDID_DSC_ALL_BPP;
5966
5967 if (hf_scds[11] & DRM_EDID_DSC_16BPC)
5968 hdmi_dsc->bpc_supported = 16;
5969 else if (hf_scds[11] & DRM_EDID_DSC_12BPC)
5970 hdmi_dsc->bpc_supported = 12;
5971 else if (hf_scds[11] & DRM_EDID_DSC_10BPC)
5972 hdmi_dsc->bpc_supported = 10;
5973 else
5974 /* Supports min 8 BPC if DSC 1.2 is supported*/
5975 hdmi_dsc->bpc_supported = 8;
5976
a07e6f56
AN		 5977 if (cea_db_payload_len(hf_scds) >= 12 && hf_scds[12]) {
5978 u8 dsc_max_slices;
5979 u8 dsc_max_frl_rate;
5e706c4d 5980
a07e6f56
AN		 5981 dsc_max_frl_rate = (hf_scds[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4;
5982 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes,
5983 &hdmi_dsc->max_frl_rate_per_lane);
5e706c4d 5984
a07e6f56
AN		 5985 dsc_max_slices = hf_scds[12] & DRM_EDID_DSC_MAX_SLICES;
5986
5987 switch (dsc_max_slices) {
5988 case 1:
5989 hdmi_dsc->max_slices = 1;
5990 hdmi_dsc->clk_per_slice = 340;
5991 break;
5992 case 2:
5993 hdmi_dsc->max_slices = 2;
5994 hdmi_dsc->clk_per_slice = 340;
5995 break;
5996 case 3:
5997 hdmi_dsc->max_slices = 4;
5998 hdmi_dsc->clk_per_slice = 340;
5999 break;
6000 case 4:
6001 hdmi_dsc->max_slices = 8;
6002 hdmi_dsc->clk_per_slice = 340;
6003 break;
6004 case 5:
6005 hdmi_dsc->max_slices = 8;
6006 hdmi_dsc->clk_per_slice = 400;
6007 break;
6008 case 6:
6009 hdmi_dsc->max_slices = 12;
6010 hdmi_dsc->clk_per_slice = 400;
6011 break;
6012 case 7:
6013 hdmi_dsc->max_slices = 16;
6014 hdmi_dsc->clk_per_slice = 400;
6015 break;
6016 case 0:
6017 default:
6018 hdmi_dsc->max_slices = 0;
6019 hdmi_dsc->clk_per_slice = 0;
6020 }
5e706c4d 6021 }
a07e6f56
AN		 6022
6023 if (cea_db_payload_len(hf_scds) >= 13 && hf_scds[13])
6024 hdmi_dsc->total_chunk_kbytes = hf_scds[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES;
5e706c4d
AN		 6025}
6026
d8cb49d2
JN		 6027/* Sink Capability Data Structure */
6028static void drm_parse_hdmi_forum_scds(struct drm_connector *connector,
6029 const u8 *hf_scds)
afa1c763 6030{
26c2ff77
JN		 6031 struct drm_display_info *info = &connector->display_info;
6032 struct drm_hdmi_info *hdmi = &info->hdmi;
a07e6f56 6033 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap;
5e931c88
AN		 6034 int max_tmds_clock = 0;
6035 u8 max_frl_rate = 0;
6036 bool dsc_support = false;
afa1c763 6037
26c2ff77 6038 info->has_hdmi_infoframe = true;
f1781e9b 6039
d8cb49d2 6040 if (hf_scds[6] & 0x80) {
afa1c763 6041 hdmi->scdc.supported = true;
d8cb49d2 6042 if (hf_scds[6] & 0x40)
afa1c763
SS		 6043 hdmi->scdc.read_request = true;
6044 }
62c58af3
SS		 6045
6046 /*
6047 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
6048 * And as per the spec, three factors confirm this:
6049 * * Availability of a HF-VSDB block in EDID (check)
6050 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
6051 * * SCDC support available (let's check)
6052 * Lets check it out.
6053 */
6054
d8cb49d2 6055 if (hf_scds[5]) {
62c58af3
SS		 6056 struct drm_scdc *scdc = &hdmi->scdc;
6057
5e931c88
AN		 6058 /* max clock is 5000 KHz times block value */
6059 max_tmds_clock = hf_scds[5] * 5000;
6060
62c58af3 6061 if (max_tmds_clock > 340000) {
26c2ff77 6062 info->max_tmds_clock = max_tmds_clock;
62c58af3
SS		 6063 }
6064
6065 if (scdc->supported) {
6066 scdc->scrambling.supported = true;
6067
dbe2d2bf 6068 /* Few sinks support scrambling for clocks < 340M */
d8cb49d2 6069 if ((hf_scds[6] & 0x8))
62c58af3
SS		 6070 scdc->scrambling.low_rates = true;
6071 }
6072 }
e6a9a2c3 6073
d8cb49d2 6074 if (hf_scds[7]) {
d8cb49d2 6075 max_frl_rate = (hf_scds[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4;
4499d488
SS		 6076 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes,
6077 &hdmi->max_frl_rate_per_lane);
6078 }
6079
d8cb49d2 6080 drm_parse_ycbcr420_deep_color_info(connector, hf_scds);
a07e6f56 6081
5e931c88 6082 if (cea_db_payload_len(hf_scds) >= 11 && hf_scds[11]) {
a07e6f56 6083 drm_parse_dsc_info(hdmi_dsc, hf_scds);
5e931c88
AN		 6084 dsc_support = true;
6085 }
6086
6087 drm_dbg_kms(connector->dev,
66d17ecd
JN		 6088 "[CONNECTOR:%d:%s] HF-VSDB: max TMDS clock: %d KHz, HDMI 2.1 support: %s, DSC 1.2 support: %s\n",
6089 connector->base.id, connector->name,
5e931c88 6090 max_tmds_clock, str_yes_no(max_frl_rate), str_yes_no(dsc_support));
afa1c763
SS		 6091}
6092
1cea146a
VS		 6093static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
6094 const u8 *hdmi)
d0c94692 6095{
1826750f 6096 struct drm_display_info *info = &connector->display_info;
d0c94692
MK		 6097 unsigned int dc_bpc = 0;
6098
1cea146a
VS		 6099 /* HDMI supports at least 8 bpc */
6100 info->bpc = 8;
d0c94692 6101
1cea146a
VS		 6102 if (cea_db_payload_len(hdmi) < 6)
6103 return;
6104
6105 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
6106 dc_bpc = 10;
4adc33f3 6107 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_30;
e1e7bc48
JN		 6108 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 30.\n",
6109 connector->base.id, connector->name);
1cea146a
VS		 6110 }
6111
6112 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
6113 dc_bpc = 12;
4adc33f3 6114 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_36;
e1e7bc48
JN		 6115 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 36.\n",
6116 connector->base.id, connector->name);
1cea146a
VS		 6117 }
6118
6119 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
6120 dc_bpc = 16;
4adc33f3 6121 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_48;
e1e7bc48
JN		 6122 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 48.\n",
6123 connector->base.id, connector->name);
1cea146a
VS		 6124 }
6125
6126 if (dc_bpc == 0) {
e1e7bc48
JN		 6127 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] No deep color support on this HDMI sink.\n",
6128 connector->base.id, connector->name);
1cea146a
VS		 6129 return;
6130 }
6131
e1e7bc48
JN		 6132 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Assigning HDMI sink color depth as %d bpc.\n",
6133 connector->base.id, connector->name, dc_bpc);
1cea146a 6134 info->bpc = dc_bpc;
d0c94692 6135
1cea146a
VS		 6136 /* YCRCB444 is optional according to spec. */
6137 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
4adc33f3 6138 info->edid_hdmi_ycbcr444_dc_modes = info->edid_hdmi_rgb444_dc_modes;
e1e7bc48
JN		 6139 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does YCRCB444 in deep color.\n",
6140 connector->base.id, connector->name);
1cea146a 6141 }
d0c94692 6142
1cea146a
VS		 6143 /*
6144 * Spec says that if any deep color mode is supported at all,
6145 * then deep color 36 bit must be supported.
6146 */
6147 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
e1e7bc48
JN		 6148 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink should do DC_36, but does not!\n",
6149 connector->base.id, connector->name);
1cea146a
VS		 6150 }
6151}
d0c94692 6152
919d320f 6153/* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */
23ebf8b9
VS		 6154static void
6155drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
6156{
6157 struct drm_display_info *info = &connector->display_info;
6158 u8 len = cea_db_payload_len(db);
6159
a92d083d
LP		 6160 info->is_hdmi = true;
6161
23ebf8b9
VS		 6162 if (len >= 6)
6163 info->dvi_dual = db[6] & 1;
6164 if (len >= 7)
6165 info->max_tmds_clock = db[7] * 5000;
6166
919d320f
JN		 6167 /*
6168 * Try to infer whether the sink supports HDMI infoframes.
6169 *
6170 * HDMI infoframe support was first added in HDMI 1.4. Assume the sink
6171 * supports infoframes if HDMI_Video_present is set.
6172 */
6173 if (len >= 8 && db[8] & BIT(5))
6174 info->has_hdmi_infoframe = true;
6175
e1e7bc48
JN		 6176 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI: DVI dual %d, max TMDS clock %d kHz\n",
6177 connector->base.id, connector->name,
6178 info->dvi_dual, info->max_tmds_clock);
23ebf8b9
VS		 6179
6180 drm_parse_hdmi_deep_color_info(connector, db);
6181}
6182
2869f599
PZ		 6183/*
6184 * See EDID extension for head-mounted and specialized monitors, specified at:
6185 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/specialized-monitors-edid-extension
6186 */
6187static void drm_parse_microsoft_vsdb(struct drm_connector *connector,
6188 const u8 *db)
6189{
6190 struct drm_display_info *info = &connector->display_info;
6191 u8 version = db[4];
6192 bool desktop_usage = db[5] & BIT(6);
6193
6194 /* Version 1 and 2 for HMDs, version 3 flags desktop usage explicitly */
6195 if (version == 1 || version == 2 || (version == 3 && !desktop_usage))
6196 info->non_desktop = true;
6197
66d17ecd
JN		 6198 drm_dbg_kms(connector->dev,
6199 "[CONNECTOR:%d:%s] HMD or specialized display VSDB version %u: 0x%02x\n",
6200 connector->base.id, connector->name, version, db[5]);
2869f599
PZ		 6201}
6202
1cea146a 6203static void drm_parse_cea_ext(struct drm_connector *connector,
e42192b4 6204 const struct drm_edid *drm_edid)
1cea146a
VS		 6205{
6206 struct drm_display_info *info = &connector->display_info;
8db73897 6207 struct drm_edid_iter edid_iter;
dfc03125
JN		 6208 const struct cea_db *db;
6209 struct cea_db_iter iter;
1cea146a 6210 const u8 *edid_ext;
61e05fdc 6211 u64 y420cmdb_map = 0;
d0c94692 6212
bbded689 6213 drm_edid_iter_begin(drm_edid, &edid_iter);
8db73897
JN		 6214 drm_edid_iter_for_each(edid_ext, &edid_iter) {
6215 if (edid_ext[0] != CEA_EXT)
6216 continue;
d0c94692 6217
8db73897
JN		 6218 if (!info->cea_rev)
6219 info->cea_rev = edid_ext[1];
d0c94692 6220
8db73897 6221 if (info->cea_rev != edid_ext[1])
e1e7bc48
JN		 6222 drm_dbg_kms(connector->dev,
6223 "[CONNECTOR:%d:%s] CEA extension version mismatch %u != %u\n",
6224 connector->base.id, connector->name,
6225 info->cea_rev, edid_ext[1]);
7344bad7 6226
8db73897
JN		 6227 /* The existence of a CTA extension should imply RGB support */
6228 info->color_formats = DRM_COLOR_FORMAT_RGB444;
7344bad7
JN		 6229 if (edid_ext[3] & EDID_CEA_YCRCB444)
6230 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
6231 if (edid_ext[3] & EDID_CEA_YCRCB422)
6232 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
6233 }
8db73897 6234 drm_edid_iter_end(&edid_iter);
1cea146a 6235
5e87b2e5 6236 cea_db_iter_edid_begin(drm_edid, &iter);
dfc03125
JN		 6237 cea_db_iter_for_each(db, &iter) {
6238 /* FIXME: convert parsers to use struct cea_db */
6239 const u8 *data = (const u8 *)db;
1cea146a 6240
23ebf8b9 6241 if (cea_db_is_hdmi_vsdb(db))
dfc03125 6242 drm_parse_hdmi_vsdb_video(connector, data);
be982415
JN		 6243 else if (cea_db_is_hdmi_forum_vsdb(db) ||
6244 cea_db_is_hdmi_forum_scdb(db))
dfc03125 6245 drm_parse_hdmi_forum_scds(connector, data);
be982415 6246 else if (cea_db_is_microsoft_vsdb(db))
dfc03125 6247 drm_parse_microsoft_vsdb(connector, data);
be982415 6248 else if (cea_db_is_y420cmdb(db))
61e05fdc 6249 parse_cta_y420cmdb(connector, db, &y420cmdb_map);
c54e2e23
JN		 6250 else if (cea_db_is_y420vdb(db))
6251 parse_cta_y420vdb(connector, db);
be982415 6252 else if (cea_db_is_vcdb(db))
dfc03125 6253 drm_parse_vcdb(connector, data);
be982415 6254 else if (cea_db_is_hdmi_hdr_metadata_block(db))
dfc03125 6255 drm_parse_hdr_metadata_block(connector, data);
c3292ab5
JN		 6256 else if (cea_db_tag(db) == CTA_DB_VIDEO)
6257 parse_cta_vdb(connector, db);
1cea146a 6258 }
dfc03125 6259 cea_db_iter_end(&iter);
61e05fdc
JN		 6260
6261 if (y420cmdb_map)
6262 update_cta_y420cmdb(connector, y420cmdb_map);
d0c94692
MK		 6263}
6264
a1d11d1e 6265static
c7943bb3 6266void get_monitor_range(const struct detailed_timing *timing, void *c)
a1d11d1e 6267{
c7943bb3
VS		 6268 struct detailed_mode_closure *closure = c;
6269 struct drm_display_info *info = &closure->connector->display_info;
6270 struct drm_monitor_range_info *monitor_range = &info->monitor_range;
a1d11d1e
MN		 6271 const struct detailed_non_pixel *data = &timing->data.other_data;
6272 const struct detailed_data_monitor_range *range = &data->data.range;
c7943bb3 6273 const struct edid *edid = closure->drm_edid->edid;
a1d11d1e 6274
e379814b 6275 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
a1d11d1e
MN		 6276 return;
6277
6278 /*
67d7469a
VS		 6279 * These limits are used to determine the VRR refresh
6280 * rate range. Only the "range limits only" variant
6281 * of the range descriptor seems to guarantee that
6282 * any and all timings are accepted by the sink, as
6283 * opposed to just timings conforming to the indicated
6284 * formula (GTF/GTF2/CVT). Thus other variants of the
6285 * range descriptor are not accepted here.
a1d11d1e
MN		 6286 */
6287 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG)
6288 return;
6289
6290 monitor_range->min_vfreq = range->min_vfreq;
6291 monitor_range->max_vfreq = range->max_vfreq;
c7943bb3
VS		 6292
6293 if (edid->revision >= 4) {
6294 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ)
6295 monitor_range->min_vfreq += 255;
6296 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MAX_VFREQ)
6297 monitor_range->max_vfreq += 255;
6298 }
a1d11d1e
MN		 6299}
6300
e42192b4
JN		 6301static void drm_get_monitor_range(struct drm_connector *connector,
6302 const struct drm_edid *drm_edid)
a1d11d1e 6303{
c7943bb3
VS		 6304 const struct drm_display_info *info = &connector->display_info;
6305 struct detailed_mode_closure closure = {
6306 .connector = connector,
6307 .drm_edid = drm_edid,
6308 };
a1d11d1e 6309
dd3abfe4 6310 if (drm_edid->edid->revision < 4)
ca2582c6
VS		 6311 return;
6312
6313 if (!(drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ))
a1d11d1e
MN		 6314 return;
6315
c7943bb3 6316 drm_for_each_detailed_block(drm_edid, get_monitor_range, &closure);
a1d11d1e 6317
e1e7bc48
JN		 6318 drm_dbg_kms(connector->dev,
6319 "[CONNECTOR:%d:%s] Supported Monitor Refresh rate range is %d Hz - %d Hz\n",
6320 connector->base.id, connector->name,
6321 info->monitor_range.min_vfreq, info->monitor_range.max_vfreq);
a1d11d1e
MN		 6322}
6323
18a9cbbe
JN		 6324static void drm_parse_vesa_mso_data(struct drm_connector *connector,
6325 const struct displayid_block *block)
6326{
6327 struct displayid_vesa_vendor_specific_block *vesa =
6328 (struct displayid_vesa_vendor_specific_block *)block;
6329 struct drm_display_info *info = &connector->display_info;
6330
6331 if (block->num_bytes < 3) {
66d17ecd
JN		 6332 drm_dbg_kms(connector->dev,
6333 "[CONNECTOR:%d:%s] Unexpected vendor block size %u\n",
6334 connector->base.id, connector->name, block->num_bytes);
18a9cbbe
JN		 6335 return;
6336 }
6337
6338 if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI)
6339 return;
6340
6341 if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
66d17ecd
JN		 6342 drm_dbg_kms(connector->dev,
6343 "[CONNECTOR:%d:%s] Unexpected VESA vendor block size\n",
6344 connector->base.id, connector->name);
18a9cbbe
JN		 6345 return;
6346 }
6347
6348 switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
6349 default:
66d17ecd
JN		 6350 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved MSO mode value\n",
6351 connector->base.id, connector->name);
18a9cbbe
JN		 6352 fallthrough;
6353 case 0:
6354 info->mso_stream_count = 0;
6355 break;
6356 case 1:
6357 info->mso_stream_count = 2; /* 2 or 4 links */
6358 break;
6359 case 2:
6360 info->mso_stream_count = 4; /* 4 links */
6361 break;
6362 }
6363
6364 if (!info->mso_stream_count) {
6365 info->mso_pixel_overlap = 0;
6366 return;
6367 }
6368
6369 info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
6370 if (info->mso_pixel_overlap > 8) {
66d17ecd
JN		 6371 drm_dbg_kms(connector->dev,
6372 "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n",
6373 connector->base.id, connector->name,
18a9cbbe
JN		 6374 info->mso_pixel_overlap);
6375 info->mso_pixel_overlap = 8;
6376 }
6377
66d17ecd
JN		 6378 drm_dbg_kms(connector->dev,
6379 "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n",
6380 connector->base.id, connector->name,
18a9cbbe
JN		 6381 info->mso_stream_count, info->mso_pixel_overlap);
6382}
6383
e42192b4
JN		 6384static void drm_update_mso(struct drm_connector *connector,
6385 const struct drm_edid *drm_edid)
18a9cbbe
JN		 6386{
6387 const struct displayid_block *block;
6388 struct displayid_iter iter;
6389
d9ba1b4c 6390 displayid_iter_edid_begin(drm_edid, &iter);
18a9cbbe
JN		 6391 displayid_iter_for_each(block, &iter) {
6392 if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC)
6393 drm_parse_vesa_mso_data(connector, block);
6394 }
6395 displayid_iter_end(&iter);
6396}
6397
170178fe
KP		 6398/* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
6399 * all of the values which would have been set from EDID
6400 */
02b16fbc 6401static void drm_reset_display_info(struct drm_connector *connector)
170178fe
KP		 6402{
6403 struct drm_display_info *info = &connector->display_info;
6404
6405 info->width_mm = 0;
6406 info->height_mm = 0;
6407
6408 info->bpc = 0;
6409 info->color_formats = 0;
6410 info->cea_rev = 0;
6411 info->max_tmds_clock = 0;
6412 info->dvi_dual = false;
a92d083d 6413 info->is_hdmi = false;
170178fe 6414 info->has_hdmi_infoframe = false;
1581b2df 6415 info->rgb_quant_range_selectable = false;
1f6b8eef 6416 memset(&info->hdmi, 0, sizeof(info->hdmi));
170178fe 6417
70c0b80d
MR		 6418 info->edid_hdmi_rgb444_dc_modes = 0;
6419 info->edid_hdmi_ycbcr444_dc_modes = 0;
6420
170178fe 6421 info->non_desktop = 0;
a1d11d1e 6422 memset(&info->monitor_range, 0, sizeof(info->monitor_range));
82068ede 6423 memset(&info->luminance_range, 0, sizeof(info->luminance_range));
18a9cbbe
JN		 6424
6425 info->mso_stream_count = 0;
6426 info->mso_pixel_overlap = 0;
aa193f7e 6427 info->max_dsc_bpp = 0;
c3292ab5
JN		 6428
6429 kfree(info->vics);
6430 info->vics = NULL;
6431 info->vics_len = 0;
783dedc5
JN		 6432
6433 info->quirks = 0;
170178fe 6434}
170178fe 6435
783dedc5
JN		 6436static void update_display_info(struct drm_connector *connector,
6437 const struct drm_edid *drm_edid)
3b11228b 6438{
1826750f 6439 struct drm_display_info *info = &connector->display_info;
45ea02d1 6440 const struct edid *edid;
ebec9a7b 6441
1f6b8eef 6442 drm_reset_display_info(connector);
45ea02d1
JN		 6443 clear_eld(connector);
6444
6445 if (!drm_edid)
6446 return;
6447
6448 edid = drm_edid->edid;
1f6b8eef 6449
783dedc5
JN		 6450 info->quirks = edid_get_quirks(drm_edid);
6451
3b11228b
JB		 6452 info->width_mm = edid->width_cm * 10;
6453 info->height_mm = edid->height_cm * 10;
6454
e42192b4 6455 drm_get_monitor_range(connector, drm_edid);
a1d11d1e 6456
a988bc72 6457 if (edid->revision < 3)
ce99534e 6458 goto out;
3b11228b
JB		 6459
6460 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
ce99534e 6461 goto out;
3b11228b 6462
ecbd4912 6463 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
e42192b4 6464 drm_parse_cea_ext(connector, drm_edid);
d0c94692 6465
210a021d
MK		 6466 /*
6467 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
6468 *
6469 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
6470 * tells us to assume 8 bpc color depth if the EDID doesn't have
6471 * extensions which tell otherwise.
6472 */
3bde449f
VS		 6473 if (info->bpc == 0 && edid->revision == 3 &&
6474 edid->input & DRM_EDID_DIGITAL_DFP_1_X) {
210a021d 6475 info->bpc = 8;
e1e7bc48
JN		 6476 drm_dbg_kms(connector->dev,
6477 "[CONNECTOR:%d:%s] Assigning DFP sink color depth as %d bpc.\n",
6478 connector->base.id, connector->name, info->bpc);
210a021d
MK		 6479 }
6480
a988bc72
LPC		 6481 /* Only defined for 1.4 with digital displays */
6482 if (edid->revision < 4)
ce99534e 6483 goto out;
a988bc72 6484
3b11228b
JB		 6485 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
6486 case DRM_EDID_DIGITAL_DEPTH_6:
6487 info->bpc = 6;
6488 break;
6489 case DRM_EDID_DIGITAL_DEPTH_8:
6490 info->bpc = 8;
6491 break;
6492 case DRM_EDID_DIGITAL_DEPTH_10:
6493 info->bpc = 10;
6494 break;
6495 case DRM_EDID_DIGITAL_DEPTH_12:
6496 info->bpc = 12;
6497 break;
6498 case DRM_EDID_DIGITAL_DEPTH_14:
6499 info->bpc = 14;
6500 break;
6501 case DRM_EDID_DIGITAL_DEPTH_16:
6502 info->bpc = 16;
6503 break;
6504 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
6505 default:
6506 info->bpc = 0;
6507 break;
6508 }
da05a5a7 6509
e1e7bc48
JN		 6510 drm_dbg_kms(connector->dev,
6511 "[CONNECTOR:%d:%s] Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
6512 connector->base.id, connector->name, info->bpc);
d0c94692 6513
ee58808d 6514 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
c03d0b52 6515 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
ee58808d 6516 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
c03d0b52 6517 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
18a9cbbe 6518
e42192b4 6519 drm_update_mso(connector, drm_edid);
18a9cbbe 6520
ce99534e 6521out:
783dedc5 6522 if (info->quirks & EDID_QUIRK_NON_DESKTOP) {
66d17ecd
JN		 6523 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Non-desktop display%s\n",
6524 connector->base.id, connector->name,
ce99534e
JN		 6525 info->non_desktop ? " (redundant quirk)" : "");
6526 info->non_desktop = true;
6527 }
6528
783dedc5 6529 if (info->quirks & EDID_QUIRK_CAP_DSC_15BPP)
aa193f7e 6530 info->max_dsc_bpp = 15;
45ea02d1 6531
43bde505
JN		 6532 if (info->quirks & EDID_QUIRK_FORCE_6BPC)
6533 info->bpc = 6;
6534
6535 if (info->quirks & EDID_QUIRK_FORCE_8BPC)
6536 info->bpc = 8;
6537
6538 if (info->quirks & EDID_QUIRK_FORCE_10BPC)
6539 info->bpc = 10;
6540
6541 if (info->quirks & EDID_QUIRK_FORCE_12BPC)
6542 info->bpc = 12;
6543
45ea02d1
JN		 6544 /* Depends on info->cea_rev set by drm_parse_cea_ext() above */
6545 drm_edid_to_eld(connector, drm_edid);
3b11228b
JB		 6546}
6547
a39ed680 6548static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
80ecb5d7
YB		 6549 struct displayid_detailed_timings_1 *timings,
6550 bool type_7)
a39ed680
DA		 6551{
6552 struct drm_display_mode *mode;
6553 unsigned pixel_clock = (timings->pixel_clock[0] |
6554 (timings->pixel_clock[1] << 8) |
6292b8ef 6555 (timings->pixel_clock[2] << 16)) + 1;
a39ed680
DA		 6556 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
6557 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
6558 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
6559 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
6560 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
6561 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
6562 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
6563 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
6564 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
6565 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
948de842 6566
a39ed680
DA		 6567 mode = drm_mode_create(dev);
6568 if (!mode)
6569 return NULL;
6570
80ecb5d7
YB		 6571 /* resolution is kHz for type VII, and 10 kHz for type I */
6572 mode->clock = type_7 ? pixel_clock : pixel_clock * 10;
a39ed680
DA		 6573 mode->hdisplay = hactive;
6574 mode->hsync_start = mode->hdisplay + hsync;
6575 mode->hsync_end = mode->hsync_start + hsync_width;
6576 mode->htotal = mode->hdisplay + hblank;
6577
6578 mode->vdisplay = vactive;
6579 mode->vsync_start = mode->vdisplay + vsync;
6580 mode->vsync_end = mode->vsync_start + vsync_width;
6581 mode->vtotal = mode->vdisplay + vblank;
6582
6583 mode->flags = 0;
6584 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
6585 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
6586 mode->type = DRM_MODE_TYPE_DRIVER;
6587
6588 if (timings->flags & 0x80)
6589 mode->type |= DRM_MODE_TYPE_PREFERRED;
a39ed680
DA		 6590 drm_mode_set_name(mode);
6591
6592 return mode;
6593}
6594
6595static int add_displayid_detailed_1_modes(struct drm_connector *connector,
43d16d84 6596 const struct displayid_block *block)
a39ed680
DA		 6597{
6598 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
6599 int i;
6600 int num_timings;
6601 struct drm_display_mode *newmode;
6602 int num_modes = 0;
80ecb5d7 6603 bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING;
a39ed680
DA		 6604 /* blocks must be multiple of 20 bytes length */
6605 if (block->num_bytes % 20)
6606 return 0;
6607
6608 num_timings = block->num_bytes / 20;
6609 for (i = 0; i < num_timings; i++) {
6610 struct displayid_detailed_timings_1 *timings = &det->timings[i];
6611
80ecb5d7 6612 newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7);
a39ed680
DA		 6613 if (!newmode)
6614 continue;
6615
6616 drm_mode_probed_add(connector, newmode);
6617 num_modes++;
6618 }
6619 return num_modes;
6620}
6621
6622static int add_displayid_detailed_modes(struct drm_connector *connector,
40f71f5b 6623 const struct drm_edid *drm_edid)
a39ed680 6624{
43d16d84 6625 const struct displayid_block *block;
5ef88dc5 6626 struct displayid_iter iter;
a39ed680
DA		 6627 int num_modes = 0;
6628
d9ba1b4c 6629 displayid_iter_edid_begin(drm_edid, &iter);
5ef88dc5 6630 displayid_iter_for_each(block, &iter) {
80ecb5d7
YB		 6631 if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING ||
6632 block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING)
5ef88dc5 6633 num_modes += add_displayid_detailed_1_modes(connector, block);
a39ed680 6634 }
5ef88dc5 6635 displayid_iter_end(&iter);
7f261afd 6636
a39ed680
DA		 6637 return num_modes;
6638}
6639
e8b1f0d4
JN		 6640static int _drm_edid_connector_add_modes(struct drm_connector *connector,
6641 const struct drm_edid *drm_edid)
f453ba04 6642{
43bde505 6643 const struct drm_display_info *info = &connector->display_info;
f453ba04 6644 int num_modes = 0;
f453ba04 6645
45ea02d1
JN		 6646 if (!drm_edid)
6647 return 0;
58304630 6648
c867df70
AJ		 6649 /*
6650 * EDID spec says modes should be preferred in this order:
6651 * - preferred detailed mode
6652 * - other detailed modes from base block
6653 * - detailed modes from extension blocks
6654 * - CVT 3-byte code modes
6655 * - standard timing codes
6656 * - established timing codes
6657 * - modes inferred from GTF or CVT range information
6658 *
13931579 6659 * We get this pretty much right.
c867df70
AJ		 6660 *
6661 * XXX order for additional mode types in extension blocks?
6662 */
4959b693 6663 num_modes += add_detailed_modes(connector, drm_edid);
40f71f5b
JN		 6664 num_modes += add_cvt_modes(connector, drm_edid);
6665 num_modes += add_standard_modes(connector, drm_edid);
6666 num_modes += add_established_modes(connector, drm_edid);
6667 num_modes += add_cea_modes(connector, drm_edid);
6668 num_modes += add_alternate_cea_modes(connector, drm_edid);
6669 num_modes += add_displayid_detailed_modes(connector, drm_edid);
afd4429e 6670 if (drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ)
40f71f5b 6671 num_modes += add_inferred_modes(connector, drm_edid);
f453ba04 6672
783dedc5 6673 if (info->quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
4959b693 6674 edid_fixup_preferred(connector);
f453ba04 6675
f453ba04
DA		 6676 return num_modes;
6677}
f40ab034 6678
a819451e
JN		 6679static void _drm_update_tile_info(struct drm_connector *connector,
6680 const struct drm_edid *drm_edid);
02b16fbc 6681
b71c0aaa 6682static int _drm_edid_connector_property_update(struct drm_connector *connector,
a819451e 6683 const struct drm_edid *drm_edid)
02b16fbc
JN		 6684{
6685 struct drm_device *dev = connector->dev;
02b16fbc 6686 int ret;
02b16fbc 6687
02b16fbc 6688 if (connector->edid_blob_ptr) {
a819451e
JN		 6689 const struct edid *old_edid = connector->edid_blob_ptr->data;
6690
02b16fbc 6691 if (old_edid) {
a819451e 6692 if (!drm_edid_are_equal(drm_edid ? drm_edid->edid : NULL, old_edid)) {
f999b37e
JN		 6693 connector->epoch_counter++;
6694 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID changed, epoch counter %llu\n",
6695 connector->base.id, connector->name,
6696 connector->epoch_counter);
02b16fbc
JN		 6697 }
6698 }
6699 }
6700
02b16fbc
JN		 6701 ret = drm_property_replace_global_blob(dev,
6702 &connector->edid_blob_ptr,
a819451e
JN		 6703 drm_edid ? drm_edid->size : 0,
6704 drm_edid ? drm_edid->edid : NULL,
02b16fbc
JN		 6705 &connector->base,
6706 dev->mode_config.edid_property);
f999b37e
JN		 6707 if (ret) {
6708 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID property update failed (%d)\n",
6709 connector->base.id, connector->name, ret);
6710 goto out;
6711 }
6712
6713 ret = drm_object_property_set_value(&connector->base,
6714 dev->mode_config.non_desktop_property,
6715 connector->display_info.non_desktop);
6716 if (ret) {
6717 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Non-desktop property update failed (%d)\n",
6718 connector->base.id, connector->name, ret);
6719 goto out;
6720 }
6721
6722 ret = drm_connector_set_tile_property(connector);
6723 if (ret) {
6724 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Tile property update failed (%d)\n",
6725 connector->base.id, connector->name, ret);
6726 goto out;
6727 }
6728
6729out:
6730 return ret;
02b16fbc 6731}
a819451e 6732
b71c0aaa
JN		 6733/**
6734 * drm_edid_connector_update - Update connector information from EDID
6735 * @connector: Connector
6736 * @drm_edid: EDID
6737 *
6738 * Update the connector mode list, display info, ELD, HDR metadata, relevant
6739 * properties, etc. from the passed in EDID.
6740 *
6741 * If EDID is NULL, reset the information.
6742 *
6743 * Return: The number of modes added or 0 if we couldn't find any.
6744 */
6745int drm_edid_connector_update(struct drm_connector *connector,
6746 const struct drm_edid *drm_edid)
6747{
6748 int count;
6749
e8b1f0d4
JN		 6750 update_display_info(connector, drm_edid);
6751
6752 count = _drm_edid_connector_add_modes(connector, drm_edid);
b71c0aaa
JN		 6753
6754 _drm_update_tile_info(connector, drm_edid);
6755
6756 /* Note: Ignore errors for now. */
6757 _drm_edid_connector_property_update(connector, drm_edid);
6758
6759 return count;
6760}
6761EXPORT_SYMBOL(drm_edid_connector_update);
6762
6763static int _drm_connector_update_edid_property(struct drm_connector *connector,
6764 const struct drm_edid *drm_edid)
6765{
b71c0aaa
JN		 6766 /*
6767 * Set the display info, using edid if available, otherwise resetting
6768 * the values to defaults. This duplicates the work done in
6769 * drm_add_edid_modes, but that function is not consistently called
6770 * before this one in all drivers and the computation is cheap enough
6771 * that it seems better to duplicate it rather than attempt to ensure
6772 * some arbitrary ordering of calls.
6773 */
45ea02d1 6774 update_display_info(connector, drm_edid);
b71c0aaa
JN		 6775
6776 _drm_update_tile_info(connector, drm_edid);
6777
6778 return _drm_edid_connector_property_update(connector, drm_edid);
6779}
6780
a819451e
JN		 6781/**
6782 * drm_connector_update_edid_property - update the edid property of a connector
6783 * @connector: drm connector
6784 * @edid: new value of the edid property
6785 *
6786 * This function creates a new blob modeset object and assigns its id to the
6787 * connector's edid property.
6788 * Since we also parse tile information from EDID's displayID block, we also
6789 * set the connector's tile property here. See drm_connector_set_tile_property()
6790 * for more details.
6791 *
b71c0aaa
JN		 6792 * This function is deprecated. Use drm_edid_connector_update() instead.
6793 *
a819451e
JN		 6794 * Returns:
6795 * Zero on success, negative errno on failure.
6796 */
6797int drm_connector_update_edid_property(struct drm_connector *connector,
6798 const struct edid *edid)
6799{
6800 struct drm_edid drm_edid;
6801
6802 return _drm_connector_update_edid_property(connector,
6803 drm_edid_legacy_init(&drm_edid, edid));
6804}
02b16fbc
JN		 6805EXPORT_SYMBOL(drm_connector_update_edid_property);
6806
f40ab034
JN		 6807/**
6808 * drm_add_edid_modes - add modes from EDID data, if available
6809 * @connector: connector we're probing
6810 * @edid: EDID data
6811 *
6812 * Add the specified modes to the connector's mode list. Also fills out the
6813 * &drm_display_info structure and ELD in @connector with any information which
6814 * can be derived from the edid.
6815 *
b71c0aaa
JN		 6816 * This function is deprecated. Use drm_edid_connector_update() instead.
6817 *
f40ab034
JN		 6818 * Return: The number of modes added or 0 if we couldn't find any.
6819 */
6820int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
6821{
e8b1f0d4
JN		 6822 struct drm_edid _drm_edid;
6823 const struct drm_edid *drm_edid;
22a27e05 6824
f40ab034 6825 if (edid && !drm_edid_is_valid(edid)) {
66d17ecd
JN		 6826 drm_warn(connector->dev, "[CONNECTOR:%d:%s] EDID invalid.\n",
6827 connector->base.id, connector->name);
f40ab034
JN		 6828 edid = NULL;
6829 }
6830
e8b1f0d4
JN		 6831 drm_edid = drm_edid_legacy_init(&_drm_edid, edid);
6832
6833 update_display_info(connector, drm_edid);
6834
6835 return _drm_edid_connector_add_modes(connector, drm_edid);
f40ab034 6836}
f453ba04 6837EXPORT_SYMBOL(drm_add_edid_modes);
f0fda0a4
ZY		 6838
6839/**
6840 * drm_add_modes_noedid - add modes for the connectors without EDID
6841 * @connector: connector we're probing
6842 * @hdisplay: the horizontal display limit
6843 * @vdisplay: the vertical display limit
6844 *
6845 * Add the specified modes to the connector's mode list. Only when the
6846 * hdisplay/vdisplay is not beyond the given limit, it will be added.
6847 *
db6cf833 6848 * Return: The number of modes added or 0 if we couldn't find any.
f0fda0a4
ZY		 6849 */
6850int drm_add_modes_noedid(struct drm_connector *connector,
6851 int hdisplay, int vdisplay)
6852{
6853 int i, count, num_modes = 0;
b1f559ec 6854 struct drm_display_mode *mode;
f0fda0a4
ZY		 6855 struct drm_device *dev = connector->dev;
6856
fbb40b28 6857 count = ARRAY_SIZE(drm_dmt_modes);
f0fda0a4
ZY		 6858 if (hdisplay < 0)
6859 hdisplay = 0;
6860 if (vdisplay < 0)
6861 vdisplay = 0;
6862
6863 for (i = 0; i < count; i++) {
b1f559ec 6864 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
948de842 6865
f0fda0a4
ZY		 6866 if (hdisplay && vdisplay) {
6867 /*
6868 * Only when two are valid, they will be used to check
6869 * whether the mode should be added to the mode list of
6870 * the connector.
6871 */
6872 if (ptr->hdisplay > hdisplay ||
6873 ptr->vdisplay > vdisplay)
6874 continue;
6875 }
f985dedb
AJ		 6876 if (drm_mode_vrefresh(ptr) > 61)
6877 continue;
f0fda0a4
ZY		 6878 mode = drm_mode_duplicate(dev, ptr);
6879 if (mode) {
6880 drm_mode_probed_add(connector, mode);
6881 num_modes++;
6882 }
6883 }
6884 return num_modes;
6885}
6886EXPORT_SYMBOL(drm_add_modes_noedid);
10a85120 6887
db6cf833
TR		 6888/**
6889 * drm_set_preferred_mode - Sets the preferred mode of a connector
6890 * @connector: connector whose mode list should be processed
6891 * @hpref: horizontal resolution of preferred mode
6892 * @vpref: vertical resolution of preferred mode
6893 *
6894 * Marks a mode as preferred if it matches the resolution specified by @hpref
6895 * and @vpref.
6896 */
3cf70daf
GH		 6897void drm_set_preferred_mode(struct drm_connector *connector,
6898 int hpref, int vpref)
6899{
6900 struct drm_display_mode *mode;
6901
6902 list_for_each_entry(mode, &connector->probed_modes, head) {
db6cf833 6903 if (mode->hdisplay == hpref &&
9d3de138 6904 mode->vdisplay == vpref)
3cf70daf
GH		 6905 mode->type |= DRM_MODE_TYPE_PREFERRED;
6906 }
6907}
6908EXPORT_SYMBOL(drm_set_preferred_mode);
6909
192a3aa0 6910static bool is_hdmi2_sink(const struct drm_connector *connector)
13d0add3
VS		 6911{
6912 /*
6913 * FIXME: sil-sii8620 doesn't have a connector around when
6914 * we need one, so we have to be prepared for a NULL connector.
6915 */
6916 if (!connector)
6917 return true;
6918
6919 return connector->display_info.hdmi.scdc.supported ||
c03d0b52 6920 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR420;
13d0add3
VS		 6921}
6922
192a3aa0 6923static u8 drm_mode_hdmi_vic(const struct drm_connector *connector,
949561eb
VS		 6924 const struct drm_display_mode *mode)
6925{
6926 bool has_hdmi_infoframe = connector ?
6927 connector->display_info.has_hdmi_infoframe : false;
6928
6929 if (!has_hdmi_infoframe)
6930 return 0;
6931
6932 /* No HDMI VIC when signalling 3D video format */
6933 if (mode->flags & DRM_MODE_FLAG_3D_MASK)
6934 return 0;
6935
6936 return drm_match_hdmi_mode(mode);
6937}
6938
192a3aa0 6939static u8 drm_mode_cea_vic(const struct drm_connector *connector,
cfd6f8c3
VS		 6940 const struct drm_display_mode *mode)
6941{
cfd6f8c3
VS		 6942 /*
6943 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
6944 * we should send its VIC in vendor infoframes, else send the
6945 * VIC in AVI infoframes. Lets check if this mode is present in
6946 * HDMI 1.4b 4K modes
6947 */
949561eb 6948 if (drm_mode_hdmi_vic(connector, mode))
cfd6f8c3
VS		 6949 return 0;
6950
1cbc1f0d
JN		 6951 return drm_match_cea_mode(mode);
6952}
cfd6f8c3 6953
1cbc1f0d
JN		 6954/*
6955 * Avoid sending VICs defined in HDMI 2.0 in AVI infoframes to sinks that
6956 * conform to HDMI 1.4.
6957 *
6958 * HDMI 1.4 (CTA-861-D) VIC range: [1..64]
6959 * HDMI 2.0 (CTA-861-F) VIC range: [1..107]
4ed29f39
JN		 6960 *
6961 * If the sink lists the VIC in CTA VDB, assume it's fine, regardless of HDMI
6962 * version.
1cbc1f0d
JN		 6963 */
6964static u8 vic_for_avi_infoframe(const struct drm_connector *connector, u8 vic)
6965{
4ed29f39
JN		 6966 if (!is_hdmi2_sink(connector) && vic > 64 &&
6967 !cta_vdb_has_vic(connector, vic))
cfd6f8c3
VS		 6968 return 0;
6969
6970 return vic;
6971}
6972
10a85120
TR		 6973/**
6974 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
6975 * data from a DRM display mode
6976 * @frame: HDMI AVI infoframe
13d0add3 6977 * @connector: the connector
10a85120
TR		 6978 * @mode: DRM display mode
6979 *
db6cf833 6980 * Return: 0 on success or a negative error code on failure.
10a85120
TR		 6981 */
6982int
6983drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
192a3aa0 6984 const struct drm_connector *connector,
13d0add3 6985 const struct drm_display_mode *mode)
10a85120 6986{
a9c266c2 6987 enum hdmi_picture_aspect picture_aspect;
d2b43473 6988 u8 vic, hdmi_vic;
10a85120
TR		 6989
6990 if (!frame || !mode)
6991 return -EINVAL;
6992
5ee0caf1 6993 hdmi_avi_infoframe_init(frame);
10a85120 6994
bf02db99
DL		 6995 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
6996 frame->pixel_repeat = 1;
6997
d2b43473
WL		 6998 vic = drm_mode_cea_vic(connector, mode);
6999 hdmi_vic = drm_mode_hdmi_vic(connector, mode);
0c1f528c 7000
10a85120 7001 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
0967e6a5 7002
50525c33
SL		 7003 /*
7004 * As some drivers don't support atomic, we can't use connector state.
7005 * So just initialize the frame with default values, just the same way
7006 * as it's done with other properties here.
7007 */
7008 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
7009 frame->itc = 0;
7010
69ab6d35
VK		 7011 /*
7012 * Populate picture aspect ratio from either
d2b43473 7013 * user input (if specified) or from the CEA/HDMI mode lists.
69ab6d35 7014 */
a9c266c2 7015 picture_aspect = mode->picture_aspect_ratio;
d2b43473
WL		 7016 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) {
7017 if (vic)
7018 picture_aspect = drm_get_cea_aspect_ratio(vic);
7019 else if (hdmi_vic)
7020 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic);
7021 }
0967e6a5 7022
a9c266c2
VS		 7023 /*
7024 * The infoframe can't convey anything but none, 4:3
7025 * and 16:9, so if the user has asked for anything else
7026 * we can only satisfy it by specifying the right VIC.
7027 */
7028 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
d2b43473
WL		 7029 if (vic) {
7030 if (picture_aspect != drm_get_cea_aspect_ratio(vic))
7031 return -EINVAL;
7032 } else if (hdmi_vic) {
7033 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic))
7034 return -EINVAL;
7035 } else {
a9c266c2 7036 return -EINVAL;
d2b43473
WL		 7037 }
7038
a9c266c2
VS		 7039 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
7040 }
7041
1cbc1f0d 7042 frame->video_code = vic_for_avi_infoframe(connector, vic);
a9c266c2 7043 frame->picture_aspect = picture_aspect;
10a85120 7044 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
24d01805 7045 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
10a85120
TR		 7046
7047 return 0;
7048}
7049EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
83dd0008 7050
a2ce26f8
VS		 7051/**
7052 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
7053 * quantization range information
7054 * @frame: HDMI AVI infoframe
13d0add3 7055 * @connector: the connector
779c4c28 7056 * @mode: DRM display mode
a2ce26f8 7057 * @rgb_quant_range: RGB quantization range (Q)
a2ce26f8
VS		 7058 */
7059void
7060drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
192a3aa0 7061 const struct drm_connector *connector,
779c4c28 7062 const struct drm_display_mode *mode,
1581b2df 7063 enum hdmi_quantization_range rgb_quant_range)
a2ce26f8 7064{
1581b2df
VS		 7065 const struct drm_display_info *info = &connector->display_info;
7066
a2ce26f8
VS		 7067 /*
7068 * CEA-861:
7069 * "A Source shall not send a non-zero Q value that does not correspond
7070 * to the default RGB Quantization Range for the transmitted Picture
7071 * unless the Sink indicates support for the Q bit in a Video
7072 * Capabilities Data Block."
779c4c28
VS		 7073 *
7074 * HDMI 2.0 recommends sending non-zero Q when it does match the
7075 * default RGB quantization range for the mode, even when QS=0.
a2ce26f8 7076 */
1581b2df 7077 if (info->rgb_quant_range_selectable ||
779c4c28 7078 rgb_quant_range == drm_default_rgb_quant_range(mode))
a2ce26f8
VS		 7079 frame->quantization_range = rgb_quant_range;
7080 else
7081 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
fcc8a22c
VS		 7082
7083 /*
7084 * CEA-861-F:
7085 * "When transmitting any RGB colorimetry, the Source should set the
7086 * YQ-field to match the RGB Quantization Range being transmitted
7087 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
7088 * set YQ=1) and the Sink shall ignore the YQ-field."
9271c0ca
VS		 7089 *
7090 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
7091 * by non-zero YQ when receiving RGB. There doesn't seem to be any
7092 * good way to tell which version of CEA-861 the sink supports, so
7093 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
96c92551 7094 * on CEA-861-F.
fcc8a22c 7095 */
13d0add3 7096 if (!is_hdmi2_sink(connector) ||
9271c0ca 7097 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
fcc8a22c
VS		 7098 frame->ycc_quantization_range =
7099 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
7100 else
7101 frame->ycc_quantization_range =
7102 HDMI_YCC_QUANTIZATION_RANGE_FULL;
a2ce26f8
VS		 7103}
7104EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
7105
4eed4a0a
DL		 7106static enum hdmi_3d_structure
7107s3d_structure_from_display_mode(const struct drm_display_mode *mode)
7108{
7109 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
7110
7111 switch (layout) {
7112 case DRM_MODE_FLAG_3D_FRAME_PACKING:
7113 return HDMI_3D_STRUCTURE_FRAME_PACKING;
7114 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
7115 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
7116 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
7117 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
7118 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
7119 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
7120 case DRM_MODE_FLAG_3D_L_DEPTH:
7121 return HDMI_3D_STRUCTURE_L_DEPTH;
7122 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
7123 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
7124 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
7125 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
7126 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
7127 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
7128 default:
7129 return HDMI_3D_STRUCTURE_INVALID;
7130 }
7131}
7132
83dd0008
LD		 7133/**
7134 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
7135 * data from a DRM display mode
7136 * @frame: HDMI vendor infoframe
f1781e9b 7137 * @connector: the connector
83dd0008
LD		 7138 * @mode: DRM display mode
7139 *
7140 * Note that there's is a need to send HDMI vendor infoframes only when using a
7141 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
7142 * function will return -EINVAL, error that can be safely ignored.
7143 *
db6cf833 7144 * Return: 0 on success or a negative error code on failure.
83dd0008
LD		 7145 */
7146int
7147drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
192a3aa0 7148 const struct drm_connector *connector,
83dd0008
LD		 7149 const struct drm_display_mode *mode)
7150{
f1781e9b
VS		 7151 /*
7152 * FIXME: sil-sii8620 doesn't have a connector around when
7153 * we need one, so we have to be prepared for a NULL connector.
7154 */
7155 bool has_hdmi_infoframe = connector ?
7156 connector->display_info.has_hdmi_infoframe : false;
83dd0008 7157 int err;
83dd0008
LD		 7158
7159 if (!frame || !mode)
7160 return -EINVAL;
7161
f1781e9b
VS		 7162 if (!has_hdmi_infoframe)
7163 return -EINVAL;
7164
949561eb
VS		 7165 err = hdmi_vendor_infoframe_init(frame);
7166 if (err < 0)
7167 return err;
4eed4a0a 7168
f1781e9b
VS		 7169 /*
7170 * Even if it's not absolutely necessary to send the infoframe
7171 * (ie.vic==0 and s3d_struct==0) we will still send it if we
7172 * know that the sink can handle it. This is based on a
7173 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
0ae865ef 7174 * have trouble realizing that they should switch from 3D to 2D
f1781e9b
VS		 7175 * mode if the source simply stops sending the infoframe when
7176 * it wants to switch from 3D to 2D.
7177 */
949561eb 7178 frame->vic = drm_mode_hdmi_vic(connector, mode);
f1781e9b 7179 frame->s3d_struct = s3d_structure_from_display_mode(mode);
83dd0008
LD		 7180
7181 return 0;
7182}
7183EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
40d9b043 7184
7f261afd
VS		 7185static void drm_parse_tiled_block(struct drm_connector *connector,
7186 const struct displayid_block *block)
5e546cd5 7187{
092c367a 7188 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
5e546cd5
DA		 7189 u16 w, h;
7190 u8 tile_v_loc, tile_h_loc;
7191 u8 num_v_tile, num_h_tile;
7192 struct drm_tile_group *tg;
7193
7194 w = tile->tile_size[0] | tile->tile_size[1] << 8;
7195 h = tile->tile_size[2] | tile->tile_size[3] << 8;
7196
7197 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
7198 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
7199 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
7200 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
7201
7202 connector->has_tile = true;
7203 if (tile->tile_cap & 0x80)
7204 connector->tile_is_single_monitor = true;
7205
7206 connector->num_h_tile = num_h_tile + 1;
7207 connector->num_v_tile = num_v_tile + 1;
7208 connector->tile_h_loc = tile_h_loc;
7209 connector->tile_v_loc = tile_v_loc;
7210 connector->tile_h_size = w + 1;
7211 connector->tile_v_size = h + 1;
7212
e1e7bc48
JN		 7213 drm_dbg_kms(connector->dev,
7214 "[CONNECTOR:%d:%s] tile cap 0x%x, size %dx%d, num tiles %dx%d, location %dx%d, vend %c%c%c",
7215 connector->base.id, connector->name,
7216 tile->tile_cap,
7217 connector->tile_h_size, connector->tile_v_size,
7218 connector->num_h_tile, connector->num_v_tile,
7219 connector->tile_h_loc, connector->tile_v_loc,
7220 tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
5e546cd5
DA		 7221
7222 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
392f9fcb 7223 if (!tg)
5e546cd5 7224 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
5e546cd5 7225 if (!tg)
7f261afd 7226 return;
5e546cd5
DA		 7227
7228 if (connector->tile_group != tg) {
7229 /* if we haven't got a pointer,
7230 take the reference, drop ref to old tile group */
392f9fcb 7231 if (connector->tile_group)
5e546cd5 7232 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5e546cd5 7233 connector->tile_group = tg;
392f9fcb 7234 } else {
5e546cd5
DA		 7235 /* if same tile group, then release the ref we just took. */
7236 drm_mode_put_tile_group(connector->dev, tg);
392f9fcb 7237 }
5e546cd5
DA		 7238}
7239
c7b2dee4
JN		 7240static void _drm_update_tile_info(struct drm_connector *connector,
7241 const struct drm_edid *drm_edid)
40d9b043 7242{
bfd4e192
JN		 7243 const struct displayid_block *block;
7244 struct displayid_iter iter;
36881184 7245
40d9b043 7246 connector->has_tile = false;
7f261afd 7247
d9ba1b4c 7248 displayid_iter_edid_begin(drm_edid, &iter);
bfd4e192
JN		 7249 displayid_iter_for_each(block, &iter) {
7250 if (block->tag == DATA_BLOCK_TILED_DISPLAY)
7251 drm_parse_tiled_block(connector, block);
40d9b043 7252 }
bfd4e192 7253 displayid_iter_end(&iter);
40d9b043 7254
7f261afd 7255 if (!connector->has_tile && connector->tile_group) {
40d9b043
DA		 7256 drm_mode_put_tile_group(connector->dev, connector->tile_group);
7257 connector->tile_group = NULL;
7258 }
40d9b043 7259}
Linux 6.x block layer and io_uring tree(s)