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drm:pl111: Add of_node_put() when breaking out of for_each_available_child_of_node()
[linux-2.6-block.git] / drivers / gpu / drm / drm_edid.c
CommitLineData
f453ba04
DA		 1/*
2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
61e57a8d 5 * Copyright 2010 Red Hat, Inc.
f453ba04
DA		 6 *
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
8 * FB layer.
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 */
9c79edec 30
18a9cbbe 31#include <linux/bitfield.h>
10a85120 32#include <linux/hdmi.h>
f453ba04 33#include <linux/i2c.h>
9c79edec 34#include <linux/kernel.h>
47819ba2 35#include <linux/module.h>
36b73b05 36#include <linux/pci.h>
9c79edec 37#include <linux/slab.h>
5cb8eaa2 38#include <linux/vga_switcheroo.h>
9c79edec
JN		 39
40#include <drm/drm_displayid.h>
41#include <drm/drm_drv.h>
760285e7 42#include <drm/drm_edid.h>
9338203c 43#include <drm/drm_encoder.h>
9c79edec 44#include <drm/drm_print.h>
f453ba04 45
969218fe
TI		 46#include "drm_crtc_internal.h"
47
37eab1fe
JN		 48static int oui(u8 first, u8 second, u8 third)
49{
50 return (first << 16) | (second << 8) | third;
51}
52
d1ff6409
AJ		 53#define EDID_EST_TIMINGS 16
54#define EDID_STD_TIMINGS 8
55#define EDID_DETAILED_TIMINGS 4
f453ba04
DA		 56
57/*
58 * EDID blocks out in the wild have a variety of bugs, try to collect
59 * them here (note that userspace may work around broken monitors first,
60 * but fixes should make their way here so that the kernel "just works"
61 * on as many displays as possible).
62 */
63
64/* First detailed mode wrong, use largest 60Hz mode */
65#define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
66/* Reported 135MHz pixel clock is too high, needs adjustment */
67#define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
68/* Prefer the largest mode at 75 Hz */
69#define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
70/* Detail timing is in cm not mm */
71#define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
72/* Detailed timing descriptors have bogus size values, so just take the
73 * maximum size and use that.
74 */
75#define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
f453ba04
DA		 76/* use +hsync +vsync for detailed mode */
77#define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
bc42aabc
AJ		 78/* Force reduced-blanking timings for detailed modes */
79#define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
49d45a31
RM		 80/* Force 8bpc */
81#define EDID_QUIRK_FORCE_8BPC (1 << 8)
bc5b9641
MK		 82/* Force 12bpc */
83#define EDID_QUIRK_FORCE_12BPC (1 << 9)
e10aec65
MK		 84/* Force 6bpc */
85#define EDID_QUIRK_FORCE_6BPC (1 << 10)
e345da82
MK		 86/* Force 10bpc */
87#define EDID_QUIRK_FORCE_10BPC (1 << 11)
66660d4c
DA		 88/* Non desktop display (i.e. HMD) */
89#define EDID_QUIRK_NON_DESKTOP (1 << 12)
3c537889 90
2869f599
PZ		 91#define MICROSOFT_IEEE_OUI 0xca125c
92
13931579
AJ		 93struct detailed_mode_closure {
94 struct drm_connector *connector;
dd0f4470 95 const struct drm_edid *drm_edid;
13931579
AJ		 96 bool preferred;
97 u32 quirks;
98 int modes;
99};
f453ba04 100
5c61259e
ZY		 101#define LEVEL_DMT 0
102#define LEVEL_GTF 1
7a374350
AJ		 103#define LEVEL_GTF2 2
104#define LEVEL_CVT 3
5c61259e 105
7d1be0a0 106#define EDID_QUIRK(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _quirks) \
e8de4d55 107{ \
7d1be0a0
DA		 108 .panel_id = drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, \
109 product_id), \
e8de4d55
DA		 110 .quirks = _quirks \
111}
112
23c4cfbd 113static const struct edid_quirk {
e8de4d55 114 u32 panel_id;
f453ba04
DA		 115 u32 quirks;
116} edid_quirk_list[] = {
117 /* Acer AL1706 */
7d1be0a0 118 EDID_QUIRK('A', 'C', 'R', 44358, EDID_QUIRK_PREFER_LARGE_60),
f453ba04 119 /* Acer F51 */
7d1be0a0 120 EDID_QUIRK('A', 'P', 'I', 0x7602, EDID_QUIRK_PREFER_LARGE_60),
f453ba04 121
e10aec65 122 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
7d1be0a0 123 EDID_QUIRK('A', 'E', 'O', 0, EDID_QUIRK_FORCE_6BPC),
e10aec65 124
0711a43b 125 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
7d1be0a0 126 EDID_QUIRK('B', 'O', 'E', 0x78b, EDID_QUIRK_FORCE_6BPC),
0711a43b 127
06998a75 128 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
7d1be0a0 129 EDID_QUIRK('C', 'P', 'T', 0x17df, EDID_QUIRK_FORCE_6BPC),
06998a75 130
25da7504 131 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
7d1be0a0 132 EDID_QUIRK('S', 'D', 'C', 0x3652, EDID_QUIRK_FORCE_6BPC),
25da7504 133
922dceff 134 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
7d1be0a0 135 EDID_QUIRK('B', 'O', 'E', 0x0771, EDID_QUIRK_FORCE_6BPC),
922dceff 136
f453ba04 137 /* Belinea 10 15 55 */
7d1be0a0
DA		 138 EDID_QUIRK('M', 'A', 'X', 1516, EDID_QUIRK_PREFER_LARGE_60),
139 EDID_QUIRK('M', 'A', 'X', 0x77e, EDID_QUIRK_PREFER_LARGE_60),
f453ba04
DA		 140
141 /* Envision Peripherals, Inc. EN-7100e */
7d1be0a0 142 EDID_QUIRK('E', 'P', 'I', 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH),
ba1163de 143 /* Envision EN2028 */
7d1be0a0 144 EDID_QUIRK('E', 'P', 'I', 8232, EDID_QUIRK_PREFER_LARGE_60),
f453ba04
DA		 145
146 /* Funai Electronics PM36B */
7d1be0a0 147 EDID_QUIRK('F', 'C', 'M', 13600, EDID_QUIRK_PREFER_LARGE_75 |
e8de4d55 148 EDID_QUIRK_DETAILED_IN_CM),
f453ba04 149
e345da82 150 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
7d1be0a0 151 EDID_QUIRK('L', 'G', 'D', 764, EDID_QUIRK_FORCE_10BPC),
e345da82 152
f453ba04 153 /* LG Philips LCD LP154W01-A5 */
7d1be0a0
DA		 154 EDID_QUIRK('L', 'P', 'L', 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
155 EDID_QUIRK('L', 'P', 'L', 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
f453ba04 156
f453ba04 157 /* Samsung SyncMaster 205BW. Note: irony */
7d1be0a0 158 EDID_QUIRK('S', 'A', 'M', 541, EDID_QUIRK_DETAILED_SYNC_PP),
f453ba04 159 /* Samsung SyncMaster 22[5-6]BW */
7d1be0a0
DA		 160 EDID_QUIRK('S', 'A', 'M', 596, EDID_QUIRK_PREFER_LARGE_60),
161 EDID_QUIRK('S', 'A', 'M', 638, EDID_QUIRK_PREFER_LARGE_60),
bc42aabc 162
bc5b9641 163 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
7d1be0a0 164 EDID_QUIRK('S', 'N', 'Y', 0x2541, EDID_QUIRK_FORCE_12BPC),
bc5b9641 165
bc42aabc 166 /* ViewSonic VA2026w */
7d1be0a0 167 EDID_QUIRK('V', 'S', 'C', 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING),
118bdbd8
AD		 168
169 /* Medion MD 30217 PG */
7d1be0a0 170 EDID_QUIRK('M', 'E', 'D', 0x7b8, EDID_QUIRK_PREFER_LARGE_75),
49d45a31 171
11bcf5f7 172 /* Lenovo G50 */
7d1be0a0 173 EDID_QUIRK('S', 'D', 'C', 18514, EDID_QUIRK_FORCE_6BPC),
11bcf5f7 174
49d45a31 175 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
7d1be0a0 176 EDID_QUIRK('S', 'E', 'C', 0xd033, EDID_QUIRK_FORCE_8BPC),
36fc5797
TV		 177
178 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
7d1be0a0 179 EDID_QUIRK('E', 'T', 'R', 13896, EDID_QUIRK_FORCE_8BPC),
acb1d8ee 180
30d62d44 181 /* Valve Index Headset */
7d1be0a0
DA		 182 EDID_QUIRK('V', 'L', 'V', 0x91a8, EDID_QUIRK_NON_DESKTOP),
183 EDID_QUIRK('V', 'L', 'V', 0x91b0, EDID_QUIRK_NON_DESKTOP),
184 EDID_QUIRK('V', 'L', 'V', 0x91b1, EDID_QUIRK_NON_DESKTOP),
185 EDID_QUIRK('V', 'L', 'V', 0x91b2, EDID_QUIRK_NON_DESKTOP),
186 EDID_QUIRK('V', 'L', 'V', 0x91b3, EDID_QUIRK_NON_DESKTOP),
187 EDID_QUIRK('V', 'L', 'V', 0x91b4, EDID_QUIRK_NON_DESKTOP),
188 EDID_QUIRK('V', 'L', 'V', 0x91b5, EDID_QUIRK_NON_DESKTOP),
189 EDID_QUIRK('V', 'L', 'V', 0x91b6, EDID_QUIRK_NON_DESKTOP),
190 EDID_QUIRK('V', 'L', 'V', 0x91b7, EDID_QUIRK_NON_DESKTOP),
191 EDID_QUIRK('V', 'L', 'V', 0x91b8, EDID_QUIRK_NON_DESKTOP),
192 EDID_QUIRK('V', 'L', 'V', 0x91b9, EDID_QUIRK_NON_DESKTOP),
193 EDID_QUIRK('V', 'L', 'V', 0x91ba, EDID_QUIRK_NON_DESKTOP),
194 EDID_QUIRK('V', 'L', 'V', 0x91bb, EDID_QUIRK_NON_DESKTOP),
195 EDID_QUIRK('V', 'L', 'V', 0x91bc, EDID_QUIRK_NON_DESKTOP),
196 EDID_QUIRK('V', 'L', 'V', 0x91bd, EDID_QUIRK_NON_DESKTOP),
197 EDID_QUIRK('V', 'L', 'V', 0x91be, EDID_QUIRK_NON_DESKTOP),
198 EDID_QUIRK('V', 'L', 'V', 0x91bf, EDID_QUIRK_NON_DESKTOP),
30d62d44 199
6931317c 200 /* HTC Vive and Vive Pro VR Headsets */
7d1be0a0
DA		 201 EDID_QUIRK('H', 'V', 'R', 0xaa01, EDID_QUIRK_NON_DESKTOP),
202 EDID_QUIRK('H', 'V', 'R', 0xaa02, EDID_QUIRK_NON_DESKTOP),
b3b12ea3 203
5a3f6108 204 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */
7d1be0a0
DA		 205 EDID_QUIRK('O', 'V', 'R', 0x0001, EDID_QUIRK_NON_DESKTOP),
206 EDID_QUIRK('O', 'V', 'R', 0x0003, EDID_QUIRK_NON_DESKTOP),
207 EDID_QUIRK('O', 'V', 'R', 0x0004, EDID_QUIRK_NON_DESKTOP),
208 EDID_QUIRK('O', 'V', 'R', 0x0012, EDID_QUIRK_NON_DESKTOP),
90eda8fc
PZ		 209
210 /* Windows Mixed Reality Headsets */
7d1be0a0 211 EDID_QUIRK('A', 'C', 'R', 0x7fce, EDID_QUIRK_NON_DESKTOP),
7d1be0a0 212 EDID_QUIRK('L', 'E', 'N', 0x0408, EDID_QUIRK_NON_DESKTOP),
7d1be0a0
DA		 213 EDID_QUIRK('F', 'U', 'J', 0x1970, EDID_QUIRK_NON_DESKTOP),
214 EDID_QUIRK('D', 'E', 'L', 0x7fce, EDID_QUIRK_NON_DESKTOP),
215 EDID_QUIRK('S', 'E', 'C', 0x144a, EDID_QUIRK_NON_DESKTOP),
216 EDID_QUIRK('A', 'U', 'S', 0xc102, EDID_QUIRK_NON_DESKTOP),
ccffc9eb
PZ		 217
218 /* Sony PlayStation VR Headset */
7d1be0a0 219 EDID_QUIRK('S', 'N', 'Y', 0x0704, EDID_QUIRK_NON_DESKTOP),
29054230
RP		 220
221 /* Sensics VR Headsets */
7d1be0a0 222 EDID_QUIRK('S', 'E', 'N', 0x1019, EDID_QUIRK_NON_DESKTOP),
29054230
RP		 223
224 /* OSVR HDK and HDK2 VR Headsets */
7d1be0a0 225 EDID_QUIRK('S', 'V', 'R', 0x1019, EDID_QUIRK_NON_DESKTOP),
f453ba04
DA		 226};
227
a6b21831
TR		 228/*
229 * Autogenerated from the DMT spec.
230 * This table is copied from xfree86/modes/xf86EdidModes.c.
231 */
232static const struct drm_display_mode drm_dmt_modes[] = {
24b856b1 233 /* 0x01 - 640x350@85Hz */
a6b21831
TR		 234 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
235 736, 832, 0, 350, 382, 385, 445, 0,
236 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 237 /* 0x02 - 640x400@85Hz */
a6b21831
TR		 238 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
239 736, 832, 0, 400, 401, 404, 445, 0,
240 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 241 /* 0x03 - 720x400@85Hz */
a6b21831
TR		 242 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
243 828, 936, 0, 400, 401, 404, 446, 0,
244 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 245 /* 0x04 - 640x480@60Hz */
a6b21831 246 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
fcf22d05 247 752, 800, 0, 480, 490, 492, 525, 0,
a6b21831 248 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 249 /* 0x05 - 640x480@72Hz */
a6b21831
TR		 250 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
251 704, 832, 0, 480, 489, 492, 520, 0,
252 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 253 /* 0x06 - 640x480@75Hz */
a6b21831
TR		 254 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
255 720, 840, 0, 480, 481, 484, 500, 0,
256 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 257 /* 0x07 - 640x480@85Hz */
a6b21831
TR		 258 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
259 752, 832, 0, 480, 481, 484, 509, 0,
260 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 261 /* 0x08 - 800x600@56Hz */
a6b21831
TR		 262 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
263 896, 1024, 0, 600, 601, 603, 625, 0,
264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 265 /* 0x09 - 800x600@60Hz */
a6b21831
TR		 266 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
267 968, 1056, 0, 600, 601, 605, 628, 0,
268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 269 /* 0x0a - 800x600@72Hz */
a6b21831
TR		 270 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
271 976, 1040, 0, 600, 637, 643, 666, 0,
272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 273 /* 0x0b - 800x600@75Hz */
a6b21831
TR		 274 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
275 896, 1056, 0, 600, 601, 604, 625, 0,
276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 277 /* 0x0c - 800x600@85Hz */
a6b21831
TR		 278 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
279 896, 1048, 0, 600, 601, 604, 631, 0,
280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 281 /* 0x0d - 800x600@120Hz RB */
a6b21831
TR		 282 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
283 880, 960, 0, 600, 603, 607, 636, 0,
284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 285 /* 0x0e - 848x480@60Hz */
a6b21831
TR		 286 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
287 976, 1088, 0, 480, 486, 494, 517, 0,
288 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 289 /* 0x0f - 1024x768@43Hz, interlace */
a6b21831 290 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
735b100f 291 1208, 1264, 0, 768, 768, 776, 817, 0,
a6b21831 292 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
fcf22d05 293 DRM_MODE_FLAG_INTERLACE) },
24b856b1 294 /* 0x10 - 1024x768@60Hz */
a6b21831
TR		 295 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
296 1184, 1344, 0, 768, 771, 777, 806, 0,
297 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 298 /* 0x11 - 1024x768@70Hz */
a6b21831
TR		 299 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
300 1184, 1328, 0, 768, 771, 777, 806, 0,
301 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 302 /* 0x12 - 1024x768@75Hz */
a6b21831
TR		 303 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
304 1136, 1312, 0, 768, 769, 772, 800, 0,
305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 306 /* 0x13 - 1024x768@85Hz */
a6b21831
TR		 307 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
308 1168, 1376, 0, 768, 769, 772, 808, 0,
309 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 310 /* 0x14 - 1024x768@120Hz RB */
a6b21831
TR		 311 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
312 1104, 1184, 0, 768, 771, 775, 813, 0,
313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 314 /* 0x15 - 1152x864@75Hz */
a6b21831
TR		 315 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
316 1344, 1600, 0, 864, 865, 868, 900, 0,
317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
bfcd74d2
VS		 318 /* 0x55 - 1280x720@60Hz */
319 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
320 1430, 1650, 0, 720, 725, 730, 750, 0,
321 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 322 /* 0x16 - 1280x768@60Hz RB */
a6b21831
TR		 323 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
324 1360, 1440, 0, 768, 771, 778, 790, 0,
325 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 326 /* 0x17 - 1280x768@60Hz */
a6b21831
TR		 327 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
328 1472, 1664, 0, 768, 771, 778, 798, 0,
329 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 330 /* 0x18 - 1280x768@75Hz */
a6b21831
TR		 331 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
332 1488, 1696, 0, 768, 771, 778, 805, 0,
fcf22d05 333 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 334 /* 0x19 - 1280x768@85Hz */
a6b21831
TR		 335 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
336 1496, 1712, 0, 768, 771, 778, 809, 0,
337 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 338 /* 0x1a - 1280x768@120Hz RB */
a6b21831
TR		 339 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
340 1360, 1440, 0, 768, 771, 778, 813, 0,
341 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 342 /* 0x1b - 1280x800@60Hz RB */
a6b21831
TR		 343 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
344 1360, 1440, 0, 800, 803, 809, 823, 0,
345 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 346 /* 0x1c - 1280x800@60Hz */
a6b21831
TR		 347 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
348 1480, 1680, 0, 800, 803, 809, 831, 0,
fcf22d05 349 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 350 /* 0x1d - 1280x800@75Hz */
a6b21831
TR		 351 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
352 1488, 1696, 0, 800, 803, 809, 838, 0,
353 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 354 /* 0x1e - 1280x800@85Hz */
a6b21831
TR		 355 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
356 1496, 1712, 0, 800, 803, 809, 843, 0,
357 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 358 /* 0x1f - 1280x800@120Hz RB */
a6b21831
TR		 359 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
360 1360, 1440, 0, 800, 803, 809, 847, 0,
361 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 362 /* 0x20 - 1280x960@60Hz */
a6b21831
TR		 363 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
364 1488, 1800, 0, 960, 961, 964, 1000, 0,
365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 366 /* 0x21 - 1280x960@85Hz */
a6b21831
TR		 367 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
368 1504, 1728, 0, 960, 961, 964, 1011, 0,
369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 370 /* 0x22 - 1280x960@120Hz RB */
a6b21831
TR		 371 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
372 1360, 1440, 0, 960, 963, 967, 1017, 0,
373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 374 /* 0x23 - 1280x1024@60Hz */
a6b21831
TR		 375 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
376 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 378 /* 0x24 - 1280x1024@75Hz */
a6b21831
TR		 379 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
380 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
381 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 382 /* 0x25 - 1280x1024@85Hz */
a6b21831
TR		 383 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
384 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 386 /* 0x26 - 1280x1024@120Hz RB */
a6b21831
TR		 387 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
388 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 390 /* 0x27 - 1360x768@60Hz */
a6b21831
TR		 391 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
392 1536, 1792, 0, 768, 771, 777, 795, 0,
393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 394 /* 0x28 - 1360x768@120Hz RB */
a6b21831
TR		 395 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
396 1440, 1520, 0, 768, 771, 776, 813, 0,
397 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 398 /* 0x51 - 1366x768@60Hz */
399 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
400 1579, 1792, 0, 768, 771, 774, 798, 0,
401 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
402 /* 0x56 - 1366x768@60Hz */
403 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
404 1436, 1500, 0, 768, 769, 772, 800, 0,
405 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 406 /* 0x29 - 1400x1050@60Hz RB */
a6b21831
TR		 407 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
408 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
409 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 410 /* 0x2a - 1400x1050@60Hz */
a6b21831
TR		 411 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
412 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
413 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 414 /* 0x2b - 1400x1050@75Hz */
a6b21831
TR		 415 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
416 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
417 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 418 /* 0x2c - 1400x1050@85Hz */
a6b21831
TR		 419 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
420 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
421 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 422 /* 0x2d - 1400x1050@120Hz RB */
a6b21831
TR		 423 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
424 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
425 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 426 /* 0x2e - 1440x900@60Hz RB */
a6b21831
TR		 427 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
428 1520, 1600, 0, 900, 903, 909, 926, 0,
429 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 430 /* 0x2f - 1440x900@60Hz */
a6b21831
TR		 431 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
432 1672, 1904, 0, 900, 903, 909, 934, 0,
433 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 434 /* 0x30 - 1440x900@75Hz */
a6b21831
TR		 435 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
436 1688, 1936, 0, 900, 903, 909, 942, 0,
437 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 438 /* 0x31 - 1440x900@85Hz */
a6b21831
TR		 439 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
440 1696, 1952, 0, 900, 903, 909, 948, 0,
441 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 442 /* 0x32 - 1440x900@120Hz RB */
a6b21831
TR		 443 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
444 1520, 1600, 0, 900, 903, 909, 953, 0,
445 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 446 /* 0x53 - 1600x900@60Hz */
447 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
448 1704, 1800, 0, 900, 901, 904, 1000, 0,
449 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 450 /* 0x33 - 1600x1200@60Hz */
a6b21831
TR		 451 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
452 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 454 /* 0x34 - 1600x1200@65Hz */
a6b21831
TR		 455 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
456 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 458 /* 0x35 - 1600x1200@70Hz */
a6b21831
TR		 459 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
460 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 462 /* 0x36 - 1600x1200@75Hz */
a6b21831
TR		 463 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
464 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 466 /* 0x37 - 1600x1200@85Hz */
a6b21831
TR		 467 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
468 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 470 /* 0x38 - 1600x1200@120Hz RB */
a6b21831
TR		 471 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
472 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
473 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 474 /* 0x39 - 1680x1050@60Hz RB */
a6b21831
TR		 475 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
476 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
477 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 478 /* 0x3a - 1680x1050@60Hz */
a6b21831
TR		 479 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
480 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
481 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 482 /* 0x3b - 1680x1050@75Hz */
a6b21831
TR		 483 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
484 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
485 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 486 /* 0x3c - 1680x1050@85Hz */
a6b21831
TR		 487 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
488 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
489 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 490 /* 0x3d - 1680x1050@120Hz RB */
a6b21831
TR		 491 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
492 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
493 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 494 /* 0x3e - 1792x1344@60Hz */
a6b21831
TR		 495 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
496 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
497 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 498 /* 0x3f - 1792x1344@75Hz */
a6b21831
TR		 499 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
500 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
501 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 502 /* 0x40 - 1792x1344@120Hz RB */
a6b21831
TR		 503 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
504 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
505 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 506 /* 0x41 - 1856x1392@60Hz */
a6b21831
TR		 507 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
508 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
509 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 510 /* 0x42 - 1856x1392@75Hz */
a6b21831 511 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
fcf22d05 512 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
a6b21831 513 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 514 /* 0x43 - 1856x1392@120Hz RB */
a6b21831
TR		 515 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
516 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
517 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 518 /* 0x52 - 1920x1080@60Hz */
519 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
520 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
521 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 522 /* 0x44 - 1920x1200@60Hz RB */
a6b21831
TR		 523 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
524 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
525 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 526 /* 0x45 - 1920x1200@60Hz */
a6b21831
TR		 527 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
528 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
529 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 530 /* 0x46 - 1920x1200@75Hz */
a6b21831
TR		 531 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
532 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
533 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 534 /* 0x47 - 1920x1200@85Hz */
a6b21831
TR		 535 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
536 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
537 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 538 /* 0x48 - 1920x1200@120Hz RB */
a6b21831
TR		 539 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
540 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
541 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 542 /* 0x49 - 1920x1440@60Hz */
a6b21831
TR		 543 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
544 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
545 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 546 /* 0x4a - 1920x1440@75Hz */
a6b21831
TR		 547 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
548 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
549 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 550 /* 0x4b - 1920x1440@120Hz RB */
a6b21831
TR		 551 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
552 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
553 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 554 /* 0x54 - 2048x1152@60Hz */
555 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
556 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
557 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 558 /* 0x4c - 2560x1600@60Hz RB */
a6b21831
TR		 559 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
560 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
561 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 562 /* 0x4d - 2560x1600@60Hz */
a6b21831
TR		 563 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
564 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
565 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 566 /* 0x4e - 2560x1600@75Hz */
a6b21831
TR		 567 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
568 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
569 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 570 /* 0x4f - 2560x1600@85Hz */
a6b21831
TR		 571 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
572 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
573 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 574 /* 0x50 - 2560x1600@120Hz RB */
a6b21831
TR		 575 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
576 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
577 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 578 /* 0x57 - 4096x2160@60Hz RB */
579 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
580 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
581 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
582 /* 0x58 - 4096x2160@59.94Hz RB */
583 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
584 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
585 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
a6b21831
TR		 586};
587
e7bfa5c4
VS		 588/*
589 * These more or less come from the DMT spec. The 720x400 modes are
590 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
591 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
592 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
593 * mode.
594 *
595 * The DMT modes have been fact-checked; the rest are mild guesses.
596 */
a6b21831
TR		 597static const struct drm_display_mode edid_est_modes[] = {
598 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
599 968, 1056, 0, 600, 601, 605, 628, 0,
600 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
601 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
602 896, 1024, 0, 600, 601, 603, 625, 0,
603 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
604 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
605 720, 840, 0, 480, 481, 484, 500, 0,
606 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
607 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
87707cfd 608 704, 832, 0, 480, 489, 492, 520, 0,
a6b21831
TR		 609 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
610 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
611 768, 864, 0, 480, 483, 486, 525, 0,
612 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
87707cfd 613 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
a6b21831
TR		 614 752, 800, 0, 480, 490, 492, 525, 0,
615 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
616 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
617 846, 900, 0, 400, 421, 423, 449, 0,
618 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
619 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
620 846, 900, 0, 400, 412, 414, 449, 0,
621 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
622 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
623 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
624 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
87707cfd 625 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
a6b21831
TR		 626 1136, 1312, 0, 768, 769, 772, 800, 0,
627 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
628 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
629 1184, 1328, 0, 768, 771, 777, 806, 0,
630 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
631 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
632 1184, 1344, 0, 768, 771, 777, 806, 0,
633 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
634 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
635 1208, 1264, 0, 768, 768, 776, 817, 0,
636 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
637 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
638 928, 1152, 0, 624, 625, 628, 667, 0,
639 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
640 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
641 896, 1056, 0, 600, 601, 604, 625, 0,
642 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
643 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
644 976, 1040, 0, 600, 637, 643, 666, 0,
645 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
646 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
647 1344, 1600, 0, 864, 865, 868, 900, 0,
648 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
649};
650
651struct minimode {
652 short w;
653 short h;
654 short r;
655 short rb;
656};
657
658static const struct minimode est3_modes[] = {
659 /* byte 6 */
660 { 640, 350, 85, 0 },
661 { 640, 400, 85, 0 },
662 { 720, 400, 85, 0 },
663 { 640, 480, 85, 0 },
664 { 848, 480, 60, 0 },
665 { 800, 600, 85, 0 },
666 { 1024, 768, 85, 0 },
667 { 1152, 864, 75, 0 },
668 /* byte 7 */
669 { 1280, 768, 60, 1 },
670 { 1280, 768, 60, 0 },
671 { 1280, 768, 75, 0 },
672 { 1280, 768, 85, 0 },
673 { 1280, 960, 60, 0 },
674 { 1280, 960, 85, 0 },
675 { 1280, 1024, 60, 0 },
676 { 1280, 1024, 85, 0 },
677 /* byte 8 */
678 { 1360, 768, 60, 0 },
679 { 1440, 900, 60, 1 },
680 { 1440, 900, 60, 0 },
681 { 1440, 900, 75, 0 },
682 { 1440, 900, 85, 0 },
683 { 1400, 1050, 60, 1 },
684 { 1400, 1050, 60, 0 },
685 { 1400, 1050, 75, 0 },
686 /* byte 9 */
687 { 1400, 1050, 85, 0 },
688 { 1680, 1050, 60, 1 },
689 { 1680, 1050, 60, 0 },
690 { 1680, 1050, 75, 0 },
691 { 1680, 1050, 85, 0 },
692 { 1600, 1200, 60, 0 },
693 { 1600, 1200, 65, 0 },
694 { 1600, 1200, 70, 0 },
695 /* byte 10 */
696 { 1600, 1200, 75, 0 },
697 { 1600, 1200, 85, 0 },
698 { 1792, 1344, 60, 0 },
c068b32a 699 { 1792, 1344, 75, 0 },
a6b21831
TR		 700 { 1856, 1392, 60, 0 },
701 { 1856, 1392, 75, 0 },
702 { 1920, 1200, 60, 1 },
703 { 1920, 1200, 60, 0 },
704 /* byte 11 */
705 { 1920, 1200, 75, 0 },
706 { 1920, 1200, 85, 0 },
707 { 1920, 1440, 60, 0 },
708 { 1920, 1440, 75, 0 },
709};
710
711static const struct minimode extra_modes[] = {
712 { 1024, 576, 60, 0 },
713 { 1366, 768, 60, 0 },
714 { 1600, 900, 60, 0 },
715 { 1680, 945, 60, 0 },
716 { 1920, 1080, 60, 0 },
717 { 2048, 1152, 60, 0 },
718 { 2048, 1536, 60, 0 },
719};
720
721/*
7befe621 722 * From CEA/CTA-861 spec.
d9278b4c 723 *
7befe621 724 * Do not access directly, instead always use cea_mode_for_vic().
a6b21831 725 */
8c1b2bd9 726static const struct drm_display_mode edid_cea_modes_1[] = {
78691960 727 /* 1 - 640x480@60Hz 4:3 */
a6b21831
TR		 728 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
729 752, 800, 0, 480, 490, 492, 525, 0,
ee7925bb 730 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 731 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 732 /* 2 - 720x480@60Hz 4:3 */
a6b21831
TR		 733 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
734 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 735 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 736 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 737 /* 3 - 720x480@60Hz 16:9 */
a6b21831
TR		 738 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
739 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 740 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 741 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 742 /* 4 - 1280x720@60Hz 16:9 */
a6b21831
TR		 743 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
744 1430, 1650, 0, 720, 725, 730, 750, 0,
ee7925bb 745 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 746 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 747 /* 5 - 1920x1080i@60Hz 16:9 */
a6b21831
TR		 748 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
749 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
750 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 751 DRM_MODE_FLAG_INTERLACE),
0425662f 752 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 753 /* 6 - 720(1440)x480i@60Hz 4:3 */
fb01d280
CT		 754 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
755 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 756 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 757 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 758 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 759 /* 7 - 720(1440)x480i@60Hz 16:9 */
fb01d280
CT		 760 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
761 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 762 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 763 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 764 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 765 /* 8 - 720(1440)x240@60Hz 4:3 */
fb01d280
CT		 766 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
767 801, 858, 0, 240, 244, 247, 262, 0,
a6b21831 768 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 769 DRM_MODE_FLAG_DBLCLK),
0425662f 770 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 771 /* 9 - 720(1440)x240@60Hz 16:9 */
fb01d280
CT		 772 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
773 801, 858, 0, 240, 244, 247, 262, 0,
a6b21831 774 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 775 DRM_MODE_FLAG_DBLCLK),
0425662f 776 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 777 /* 10 - 2880x480i@60Hz 4:3 */
a6b21831
TR		 778 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
779 3204, 3432, 0, 480, 488, 494, 525, 0,
780 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 781 DRM_MODE_FLAG_INTERLACE),
0425662f 782 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 783 /* 11 - 2880x480i@60Hz 16:9 */
a6b21831
TR		 784 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
785 3204, 3432, 0, 480, 488, 494, 525, 0,
786 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 787 DRM_MODE_FLAG_INTERLACE),
0425662f 788 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 789 /* 12 - 2880x240@60Hz 4:3 */
a6b21831
TR		 790 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
791 3204, 3432, 0, 240, 244, 247, 262, 0,
ee7925bb 792 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 793 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 794 /* 13 - 2880x240@60Hz 16:9 */
a6b21831
TR		 795 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
796 3204, 3432, 0, 240, 244, 247, 262, 0,
ee7925bb 797 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 798 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 799 /* 14 - 1440x480@60Hz 4:3 */
a6b21831
TR		 800 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
801 1596, 1716, 0, 480, 489, 495, 525, 0,
ee7925bb 802 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 803 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 804 /* 15 - 1440x480@60Hz 16:9 */
a6b21831
TR		 805 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
806 1596, 1716, 0, 480, 489, 495, 525, 0,
ee7925bb 807 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 808 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 809 /* 16 - 1920x1080@60Hz 16:9 */
a6b21831
TR		 810 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
811 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 812 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 813 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 814 /* 17 - 720x576@50Hz 4:3 */
a6b21831
TR		 815 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
816 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 817 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 818 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 819 /* 18 - 720x576@50Hz 16:9 */
a6b21831
TR		 820 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
821 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 822 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 823 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 824 /* 19 - 1280x720@50Hz 16:9 */
a6b21831
TR		 825 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
826 1760, 1980, 0, 720, 725, 730, 750, 0,
ee7925bb 827 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 828 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 829 /* 20 - 1920x1080i@50Hz 16:9 */
a6b21831
TR		 830 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
831 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
832 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 833 DRM_MODE_FLAG_INTERLACE),
0425662f 834 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 835 /* 21 - 720(1440)x576i@50Hz 4:3 */
fb01d280
CT		 836 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
837 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 838 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 839 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 840 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 841 /* 22 - 720(1440)x576i@50Hz 16:9 */
fb01d280
CT		 842 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
843 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 844 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 845 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 846 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 847 /* 23 - 720(1440)x288@50Hz 4:3 */
fb01d280
CT		 848 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
849 795, 864, 0, 288, 290, 293, 312, 0,
a6b21831 850 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 851 DRM_MODE_FLAG_DBLCLK),
0425662f 852 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 853 /* 24 - 720(1440)x288@50Hz 16:9 */
fb01d280
CT		 854 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
855 795, 864, 0, 288, 290, 293, 312, 0,
a6b21831 856 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 857 DRM_MODE_FLAG_DBLCLK),
0425662f 858 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 859 /* 25 - 2880x576i@50Hz 4:3 */
a6b21831
TR		 860 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
861 3180, 3456, 0, 576, 580, 586, 625, 0,
862 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 863 DRM_MODE_FLAG_INTERLACE),
0425662f 864 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 865 /* 26 - 2880x576i@50Hz 16:9 */
a6b21831
TR		 866 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
867 3180, 3456, 0, 576, 580, 586, 625, 0,
868 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 869 DRM_MODE_FLAG_INTERLACE),
0425662f 870 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 871 /* 27 - 2880x288@50Hz 4:3 */
a6b21831
TR		 872 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
873 3180, 3456, 0, 288, 290, 293, 312, 0,
ee7925bb 874 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 875 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 876 /* 28 - 2880x288@50Hz 16:9 */
a6b21831
TR		 877 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
878 3180, 3456, 0, 288, 290, 293, 312, 0,
ee7925bb 879 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 880 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 881 /* 29 - 1440x576@50Hz 4:3 */
a6b21831
TR		 882 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
883 1592, 1728, 0, 576, 581, 586, 625, 0,
ee7925bb 884 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 885 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 886 /* 30 - 1440x576@50Hz 16:9 */
a6b21831
TR		 887 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
888 1592, 1728, 0, 576, 581, 586, 625, 0,
ee7925bb 889 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 890 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 891 /* 31 - 1920x1080@50Hz 16:9 */
a6b21831
TR		 892 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
893 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 894 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 895 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 896 /* 32 - 1920x1080@24Hz 16:9 */
a6b21831
TR		 897 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
898 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 899 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 900 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 901 /* 33 - 1920x1080@25Hz 16:9 */
a6b21831
TR		 902 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
903 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 904 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 905 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 906 /* 34 - 1920x1080@30Hz 16:9 */
a6b21831
TR		 907 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
908 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 909 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 910 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 911 /* 35 - 2880x480@60Hz 4:3 */
a6b21831
TR		 912 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
913 3192, 3432, 0, 480, 489, 495, 525, 0,
ee7925bb 914 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 915 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 916 /* 36 - 2880x480@60Hz 16:9 */
a6b21831
TR		 917 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
918 3192, 3432, 0, 480, 489, 495, 525, 0,
ee7925bb 919 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 920 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 921 /* 37 - 2880x576@50Hz 4:3 */
a6b21831
TR		 922 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
923 3184, 3456, 0, 576, 581, 586, 625, 0,
ee7925bb 924 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 925 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 926 /* 38 - 2880x576@50Hz 16:9 */
a6b21831
TR		 927 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
928 3184, 3456, 0, 576, 581, 586, 625, 0,
ee7925bb 929 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 930 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 931 /* 39 - 1920x1080i@50Hz 16:9 */
a6b21831
TR		 932 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
933 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
934 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 935 DRM_MODE_FLAG_INTERLACE),
0425662f 936 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 937 /* 40 - 1920x1080i@100Hz 16:9 */
a6b21831
TR		 938 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
939 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
940 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 941 DRM_MODE_FLAG_INTERLACE),
0425662f 942 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 943 /* 41 - 1280x720@100Hz 16:9 */
a6b21831
TR		 944 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
945 1760, 1980, 0, 720, 725, 730, 750, 0,
ee7925bb 946 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 947 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 948 /* 42 - 720x576@100Hz 4:3 */
a6b21831
TR		 949 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
950 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 951 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 952 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 953 /* 43 - 720x576@100Hz 16:9 */
a6b21831
TR		 954 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
955 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 956 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 957 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 958 /* 44 - 720(1440)x576i@100Hz 4:3 */
fb01d280
CT		 959 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
960 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 961 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 962 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 963 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 964 /* 45 - 720(1440)x576i@100Hz 16:9 */
fb01d280
CT		 965 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
966 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 967 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 968 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 969 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 970 /* 46 - 1920x1080i@120Hz 16:9 */
a6b21831
TR		 971 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
972 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
973 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 974 DRM_MODE_FLAG_INTERLACE),
0425662f 975 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 976 /* 47 - 1280x720@120Hz 16:9 */
a6b21831
TR		 977 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
978 1430, 1650, 0, 720, 725, 730, 750, 0,
ee7925bb 979 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 980 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 981 /* 48 - 720x480@120Hz 4:3 */
a6b21831
TR		 982 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
983 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 984 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 985 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 986 /* 49 - 720x480@120Hz 16:9 */
a6b21831
TR		 987 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
988 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 989 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 990 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 991 /* 50 - 720(1440)x480i@120Hz 4:3 */
fb01d280
CT		 992 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
993 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 994 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 995 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 996 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 997 /* 51 - 720(1440)x480i@120Hz 16:9 */
fb01d280
CT		 998 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
999 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 1000 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1001 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1002 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1003 /* 52 - 720x576@200Hz 4:3 */
a6b21831
TR		 1004 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1005 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 1006 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 1007 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1008 /* 53 - 720x576@200Hz 16:9 */
a6b21831
TR		 1009 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1010 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 1011 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 1012 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1013 /* 54 - 720(1440)x576i@200Hz 4:3 */
fb01d280
CT		 1014 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1015 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 1016 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1017 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1018 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1019 /* 55 - 720(1440)x576i@200Hz 16:9 */
fb01d280
CT		 1020 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1021 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 1022 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1023 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1024 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1025 /* 56 - 720x480@240Hz 4:3 */
a6b21831
TR		 1026 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1027 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 1028 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 1029 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1030 /* 57 - 720x480@240Hz 16:9 */
a6b21831
TR		 1031 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1032 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 1033 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 1034 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1035 /* 58 - 720(1440)x480i@240Hz 4:3 */
fb01d280
CT		 1036 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1037 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 1038 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1039 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1040 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1041 /* 59 - 720(1440)x480i@240Hz 16:9 */
fb01d280
CT		 1042 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1043 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 1044 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1045 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1046 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1047 /* 60 - 1280x720@24Hz 16:9 */
a6b21831
TR		 1048 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1049 3080, 3300, 0, 720, 725, 730, 750, 0,
ee7925bb 1050 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1051 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1052 /* 61 - 1280x720@25Hz 16:9 */
a6b21831
TR		 1053 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1054 3740, 3960, 0, 720, 725, 730, 750, 0,
ee7925bb 1055 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1056 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1057 /* 62 - 1280x720@30Hz 16:9 */
a6b21831
TR		 1058 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1059 3080, 3300, 0, 720, 725, 730, 750, 0,
ee7925bb 1060 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1061 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1062 /* 63 - 1920x1080@120Hz 16:9 */
a6b21831
TR		 1063 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1064 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 1065 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1066 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1067 /* 64 - 1920x1080@100Hz 16:9 */
a6b21831 1068 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
8f0e4907 1069 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 1070 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1071 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1072 /* 65 - 1280x720@24Hz 64:27 */
8ec6e075
SS		 1073 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1074 3080, 3300, 0, 720, 725, 730, 750, 0,
1075 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1076 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1077 /* 66 - 1280x720@25Hz 64:27 */
8ec6e075
SS		 1078 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1079 3740, 3960, 0, 720, 725, 730, 750, 0,
1080 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1081 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1082 /* 67 - 1280x720@30Hz 64:27 */
8ec6e075
SS		 1083 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1084 3080, 3300, 0, 720, 725, 730, 750, 0,
1085 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1086 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1087 /* 68 - 1280x720@50Hz 64:27 */
8ec6e075
SS		 1088 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1089 1760, 1980, 0, 720, 725, 730, 750, 0,
1090 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1091 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1092 /* 69 - 1280x720@60Hz 64:27 */
8ec6e075
SS		 1093 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1094 1430, 1650, 0, 720, 725, 730, 750, 0,
1095 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1096 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1097 /* 70 - 1280x720@100Hz 64:27 */
8ec6e075
SS		 1098 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1099 1760, 1980, 0, 720, 725, 730, 750, 0,
1100 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1101 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1102 /* 71 - 1280x720@120Hz 64:27 */
8ec6e075
SS		 1103 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1104 1430, 1650, 0, 720, 725, 730, 750, 0,
1105 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1106 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1107 /* 72 - 1920x1080@24Hz 64:27 */
8ec6e075
SS		 1108 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1109 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1110 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1111 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1112 /* 73 - 1920x1080@25Hz 64:27 */
8ec6e075
SS		 1113 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1114 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1115 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1116 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1117 /* 74 - 1920x1080@30Hz 64:27 */
8ec6e075
SS		 1118 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1119 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1120 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1121 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1122 /* 75 - 1920x1080@50Hz 64:27 */
8ec6e075
SS		 1123 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1124 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1125 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1126 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1127 /* 76 - 1920x1080@60Hz 64:27 */
8ec6e075
SS		 1128 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1129 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1130 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1131 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1132 /* 77 - 1920x1080@100Hz 64:27 */
8ec6e075
SS		 1133 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1134 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1135 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1136 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1137 /* 78 - 1920x1080@120Hz 64:27 */
8ec6e075
SS		 1138 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1139 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1140 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1141 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1142 /* 79 - 1680x720@24Hz 64:27 */
8ec6e075
SS		 1143 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1144 3080, 3300, 0, 720, 725, 730, 750, 0,
1145 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1146 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1147 /* 80 - 1680x720@25Hz 64:27 */
8ec6e075
SS		 1148 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1149 2948, 3168, 0, 720, 725, 730, 750, 0,
1150 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1151 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1152 /* 81 - 1680x720@30Hz 64:27 */
8ec6e075
SS		 1153 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1154 2420, 2640, 0, 720, 725, 730, 750, 0,
1155 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1156 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1157 /* 82 - 1680x720@50Hz 64:27 */
8ec6e075
SS		 1158 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1159 1980, 2200, 0, 720, 725, 730, 750, 0,
1160 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1161 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1162 /* 83 - 1680x720@60Hz 64:27 */
8ec6e075
SS		 1163 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1164 1980, 2200, 0, 720, 725, 730, 750, 0,
1165 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1166 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1167 /* 84 - 1680x720@100Hz 64:27 */
8ec6e075
SS		 1168 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1169 1780, 2000, 0, 720, 725, 730, 825, 0,
1170 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1171 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1172 /* 85 - 1680x720@120Hz 64:27 */
8ec6e075
SS		 1173 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1174 1780, 2000, 0, 720, 725, 730, 825, 0,
1175 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1176 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1177 /* 86 - 2560x1080@24Hz 64:27 */
8ec6e075
SS		 1178 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1179 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1180 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1181 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1182 /* 87 - 2560x1080@25Hz 64:27 */
8ec6e075
SS		 1183 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1184 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1185 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1186 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1187 /* 88 - 2560x1080@30Hz 64:27 */
8ec6e075
SS		 1188 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1189 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1190 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1191 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1192 /* 89 - 2560x1080@50Hz 64:27 */
8ec6e075
SS		 1193 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1194 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1195 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1196 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1197 /* 90 - 2560x1080@60Hz 64:27 */
8ec6e075
SS		 1198 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1199 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1200 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1201 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1202 /* 91 - 2560x1080@100Hz 64:27 */
8ec6e075
SS		 1203 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1204 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1205 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1206 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1207 /* 92 - 2560x1080@120Hz 64:27 */
8ec6e075
SS		 1208 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1209 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1210 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1211 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1212 /* 93 - 3840x2160@24Hz 16:9 */
8ec6e075
SS		 1213 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1214 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1215 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1216 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1217 /* 94 - 3840x2160@25Hz 16:9 */
8ec6e075
SS		 1218 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1219 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1220 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1221 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1222 /* 95 - 3840x2160@30Hz 16:9 */
8ec6e075
SS		 1223 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1224 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1225 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1226 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1227 /* 96 - 3840x2160@50Hz 16:9 */
8ec6e075
SS		 1228 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1229 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1230 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1231 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1232 /* 97 - 3840x2160@60Hz 16:9 */
8ec6e075
SS		 1233 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1234 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1235 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1236 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1237 /* 98 - 4096x2160@24Hz 256:135 */
8ec6e075
SS		 1238 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1239 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1240 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1241 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1242 /* 99 - 4096x2160@25Hz 256:135 */
8ec6e075
SS		 1243 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1244 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1245 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1246 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1247 /* 100 - 4096x2160@30Hz 256:135 */
8ec6e075
SS		 1248 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1249 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1250 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1251 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1252 /* 101 - 4096x2160@50Hz 256:135 */
8ec6e075
SS		 1253 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1254 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1255 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1256 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1257 /* 102 - 4096x2160@60Hz 256:135 */
8ec6e075
SS		 1258 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1259 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1260 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1261 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1262 /* 103 - 3840x2160@24Hz 64:27 */
8ec6e075
SS		 1263 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1264 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1265 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1266 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1267 /* 104 - 3840x2160@25Hz 64:27 */
8ec6e075
SS		 1268 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1269 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1270 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1271 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1272 /* 105 - 3840x2160@30Hz 64:27 */
8ec6e075
SS		 1273 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1274 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1275 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1276 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1277 /* 106 - 3840x2160@50Hz 64:27 */
8ec6e075
SS		 1278 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1279 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1281 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1282 /* 107 - 3840x2160@60Hz 64:27 */
8ec6e075
SS		 1283 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1284 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1285 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1286 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1287 /* 108 - 1280x720@48Hz 16:9 */
1288 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1289 2280, 2500, 0, 720, 725, 730, 750, 0,
1290 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1291 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1292 /* 109 - 1280x720@48Hz 64:27 */
1293 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1294 2280, 2500, 0, 720, 725, 730, 750, 0,
1295 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1296 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1297 /* 110 - 1680x720@48Hz 64:27 */
1298 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490,
1299 2530, 2750, 0, 720, 725, 730, 750, 0,
1300 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1301 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1302 /* 111 - 1920x1080@48Hz 16:9 */
1303 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1304 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1306 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1307 /* 112 - 1920x1080@48Hz 64:27 */
1308 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1309 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1310 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1311 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1312 /* 113 - 2560x1080@48Hz 64:27 */
1313 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558,
1314 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1315 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1316 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1317 /* 114 - 3840x2160@48Hz 16:9 */
1318 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1319 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1320 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1321 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1322 /* 115 - 4096x2160@48Hz 256:135 */
1323 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116,
1324 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1325 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1326 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
978f6b06
VS		 1327 /* 116 - 3840x2160@48Hz 64:27 */
1328 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1329 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1330 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1331 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1332 /* 117 - 3840x2160@100Hz 16:9 */
1333 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1334 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1335 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1336 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1337 /* 118 - 3840x2160@120Hz 16:9 */
1338 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1339 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1340 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1341 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1342 /* 119 - 3840x2160@100Hz 64:27 */
1343 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1344 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1345 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1346 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1347 /* 120 - 3840x2160@120Hz 64:27 */
1348 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1349 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1350 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1351 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1352 /* 121 - 5120x2160@24Hz 64:27 */
1353 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116,
1354 7204, 7500, 0, 2160, 2168, 2178, 2200, 0,
1355 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1356 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1357 /* 122 - 5120x2160@25Hz 64:27 */
1358 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816,
1359 6904, 7200, 0, 2160, 2168, 2178, 2200, 0,
1360 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1361 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1362 /* 123 - 5120x2160@30Hz 64:27 */
1363 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784,
1364 5872, 6000, 0, 2160, 2168, 2178, 2200, 0,
1365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1366 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1367 /* 124 - 5120x2160@48Hz 64:27 */
1368 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866,
1369 5954, 6250, 0, 2160, 2168, 2178, 2475, 0,
1370 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1371 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1372 /* 125 - 5120x2160@50Hz 64:27 */
1373 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216,
1374 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1375 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1376 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1377 /* 126 - 5120x2160@60Hz 64:27 */
1378 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284,
1379 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1380 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1381 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1382 /* 127 - 5120x2160@100Hz 64:27 */
1383 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216,
1384 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1386 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
a6b21831
TR		 1387};
1388
f7655d42
VS		 1389/*
1390 * From CEA/CTA-861 spec.
1391 *
1392 * Do not access directly, instead always use cea_mode_for_vic().
1393 */
1394static const struct drm_display_mode edid_cea_modes_193[] = {
1395 /* 193 - 5120x2160@120Hz 64:27 */
1396 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284,
1397 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1398 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1399 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1400 /* 194 - 7680x4320@24Hz 16:9 */
1401 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1402 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1403 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1404 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1405 /* 195 - 7680x4320@25Hz 16:9 */
1406 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1407 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1408 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1409 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1410 /* 196 - 7680x4320@30Hz 16:9 */
1411 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1412 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1413 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1414 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1415 /* 197 - 7680x4320@48Hz 16:9 */
1416 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1417 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1418 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1419 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1420 /* 198 - 7680x4320@50Hz 16:9 */
1421 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1422 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1423 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1424 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1425 /* 199 - 7680x4320@60Hz 16:9 */
1426 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1427 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1428 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1429 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1430 /* 200 - 7680x4320@100Hz 16:9 */
1431 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1432 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1433 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1434 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1435 /* 201 - 7680x4320@120Hz 16:9 */
1436 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1437 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1438 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1439 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1440 /* 202 - 7680x4320@24Hz 64:27 */
1441 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1442 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1443 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1444 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1445 /* 203 - 7680x4320@25Hz 64:27 */
1446 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1447 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1448 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1449 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1450 /* 204 - 7680x4320@30Hz 64:27 */
1451 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1452 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1454 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1455 /* 205 - 7680x4320@48Hz 64:27 */
1456 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1457 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1458 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1459 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1460 /* 206 - 7680x4320@50Hz 64:27 */
1461 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1462 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1463 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1464 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1465 /* 207 - 7680x4320@60Hz 64:27 */
1466 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1467 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1468 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1469 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1470 /* 208 - 7680x4320@100Hz 64:27 */
1471 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1472 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1473 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1474 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1475 /* 209 - 7680x4320@120Hz 64:27 */
1476 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1477 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1478 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1479 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1480 /* 210 - 10240x4320@24Hz 64:27 */
1481 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732,
1482 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1483 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1484 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1485 /* 211 - 10240x4320@25Hz 64:27 */
1486 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732,
1487 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1488 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1489 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1490 /* 212 - 10240x4320@30Hz 64:27 */
1491 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528,
1492 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1493 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1494 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1495 /* 213 - 10240x4320@48Hz 64:27 */
1496 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732,
1497 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1498 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1499 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1500 /* 214 - 10240x4320@50Hz 64:27 */
1501 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732,
1502 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1503 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1504 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1505 /* 215 - 10240x4320@60Hz 64:27 */
1506 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528,
1507 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1508 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1509 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1510 /* 216 - 10240x4320@100Hz 64:27 */
1511 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432,
1512 12608, 13200, 0, 4320, 4336, 4356, 4500, 0,
1513 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1514 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1515 /* 217 - 10240x4320@120Hz 64:27 */
1516 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528,
1517 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1518 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1519 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1520 /* 218 - 4096x2160@100Hz 256:135 */
1521 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896,
1522 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1523 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1524 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
f7655d42
VS		 1525 /* 219 - 4096x2160@120Hz 256:135 */
1526 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184,
1527 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1528 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1529 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
f7655d42
VS		 1530};
1531
7ebe1963 1532/*
d9278b4c 1533 * HDMI 1.4 4k modes. Index using the VIC.
7ebe1963
LD		 1534 */
1535static const struct drm_display_mode edid_4k_modes[] = {
d9278b4c
JN		 1536 /* 0 - dummy, VICs start at 1 */
1537 { },
7ebe1963
LD		 1538 /* 1 - 3840x2160@30Hz */
1539 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1540 3840, 4016, 4104, 4400, 0,
1541 2160, 2168, 2178, 2250, 0,
1542 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1543 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
7ebe1963
LD		 1544 /* 2 - 3840x2160@25Hz */
1545 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1546 3840, 4896, 4984, 5280, 0,
1547 2160, 2168, 2178, 2250, 0,
1548 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1549 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
7ebe1963
LD		 1550 /* 3 - 3840x2160@24Hz */
1551 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1552 3840, 5116, 5204, 5500, 0,
1553 2160, 2168, 2178, 2250, 0,
1554 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1555 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
7ebe1963
LD		 1556 /* 4 - 4096x2160@24Hz (SMPTE) */
1557 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1558 4096, 5116, 5204, 5500, 0,
1559 2160, 2168, 2178, 2250, 0,
1560 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1561 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
7ebe1963
LD		 1562};
1563
61e57a8d 1564/*** DDC fetch and block validation ***/
f453ba04 1565
e4ccf9a7
JN		 1566/*
1567 * The opaque EDID type, internal to drm_edid.c.
1568 */
1569struct drm_edid {
1570 /* Size allocated for edid */
1571 size_t size;
1572 const struct edid *edid;
1573};
1574
d0edd3c1
JN		 1575static bool version_greater(const struct drm_edid *drm_edid,
1576 u8 version, u8 revision)
1577{
1578 const struct edid *edid = drm_edid->edid;
1579
1580 return edid->version > version ||
1581 (edid->version == version && edid->revision > revision);
1582}
1583
18e3c1d5
JN		 1584static int edid_hfeeodb_extension_block_count(const struct edid *edid);
1585
1586static int edid_hfeeodb_block_count(const struct edid *edid)
1587{
1588 int eeodb = edid_hfeeodb_extension_block_count(edid);
1589
1590 return eeodb ? eeodb + 1 : 0;
1591}
1592
f1e4c916
JN		 1593static int edid_extension_block_count(const struct edid *edid)
1594{
1595 return edid->extensions;
1596}
1597
1598static int edid_block_count(const struct edid *edid)
1599{
1600 return edid_extension_block_count(edid) + 1;
1601}
1602
1603static int edid_size_by_blocks(int num_blocks)
1604{
1605 return num_blocks * EDID_LENGTH;
1606}
1607
1608static int edid_size(const struct edid *edid)
1609{
1610 return edid_size_by_blocks(edid_block_count(edid));
1611}
1612
1613static const void *edid_block_data(const struct edid *edid, int index)
1614{
1615 BUILD_BUG_ON(sizeof(*edid) != EDID_LENGTH);
1616
1617 return edid + index;
1618}
1619
1620static const void *edid_extension_block_data(const struct edid *edid, int index)
1621{
1622 return edid_block_data(edid, index + 1);
1623}
1624
d9307f27
JN		 1625static int drm_edid_block_count(const struct drm_edid *drm_edid)
1626{
1627 int num_blocks;
1628
1629 /* Starting point */
1630 num_blocks = edid_block_count(drm_edid->edid);
1631
b1dee952
JN		 1632 /* HF-EEODB override */
1633 if (drm_edid->size >= edid_size_by_blocks(2)) {
1634 int eeodb;
1635
1636 /*
1637 * Note: HF-EEODB may specify a smaller extension count than the
1638 * regular one. Unlike in buffer allocation, here we can use it.
1639 */
1640 eeodb = edid_hfeeodb_block_count(drm_edid->edid);
1641 if (eeodb)
1642 num_blocks = eeodb;
1643 }
1644
d9307f27
JN		 1645 /* Limit by allocated size */
1646 num_blocks = min(num_blocks, (int)drm_edid->size / EDID_LENGTH);
1647
1648 return num_blocks;
1649}
1650
1651static int drm_edid_extension_block_count(const struct drm_edid *drm_edid)
1652{
1653 return drm_edid_block_count(drm_edid) - 1;
1654}
1655
1656static const void *drm_edid_block_data(const struct drm_edid *drm_edid, int index)
1657{
1658 return edid_block_data(drm_edid->edid, index);
1659}
1660
1661static const void *drm_edid_extension_block_data(const struct drm_edid *drm_edid,
1662 int index)
1663{
1664 return edid_extension_block_data(drm_edid->edid, index);
1665}
1666
22a27e05
JN		 1667/*
1668 * Initializer helper for legacy interfaces, where we have no choice but to
1669 * trust edid size. Not for general purpose use.
1670 */
1671static const struct drm_edid *drm_edid_legacy_init(struct drm_edid *drm_edid,
1672 const struct edid *edid)
1673{
1674 if (!edid)
1675 return NULL;
1676
1677 memset(drm_edid, 0, sizeof(*drm_edid));
1678
1679 drm_edid->edid = edid;
1680 drm_edid->size = edid_size(edid);
1681
1682 return drm_edid;
1683}
1684
94afc538
JN		 1685/*
1686 * EDID base and extension block iterator.
1687 *
1688 * struct drm_edid_iter iter;
1689 * const u8 *block;
1690 *
bbded689 1691 * drm_edid_iter_begin(drm_edid, &iter);
94afc538
JN		 1692 * drm_edid_iter_for_each(block, &iter) {
1693 * // do stuff with block
1694 * }
1695 * drm_edid_iter_end(&iter);
1696 */
1697struct drm_edid_iter {
bbded689 1698 const struct drm_edid *drm_edid;
94afc538
JN		 1699
1700 /* Current block index. */
1701 int index;
1702};
1703
bbded689 1704static void drm_edid_iter_begin(const struct drm_edid *drm_edid,
94afc538
JN		 1705 struct drm_edid_iter *iter)
1706{
1707 memset(iter, 0, sizeof(*iter));
1708
bbded689 1709 iter->drm_edid = drm_edid;
94afc538
JN		 1710}
1711
1712static const void *__drm_edid_iter_next(struct drm_edid_iter *iter)
1713{
1714 const void *block = NULL;
1715
bbded689 1716 if (!iter->drm_edid)
94afc538
JN		 1717 return NULL;
1718
d9307f27
JN		 1719 if (iter->index < drm_edid_block_count(iter->drm_edid))
1720 block = drm_edid_block_data(iter->drm_edid, iter->index++);
94afc538
JN		 1721
1722 return block;
1723}
1724
1725#define drm_edid_iter_for_each(__block, __iter) \
1726 while (((__block) = __drm_edid_iter_next(__iter)))
1727
1728static void drm_edid_iter_end(struct drm_edid_iter *iter)
1729{
1730 memset(iter, 0, sizeof(*iter));
1731}
1732
083ae056
AJ		 1733static const u8 edid_header[] = {
1734 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1735};
f453ba04 1736
0a612bbd
JN		 1737static void edid_header_fix(void *edid)
1738{
1739 memcpy(edid, edid_header, sizeof(edid_header));
1740}
1741
db6cf833
TR		 1742/**
1743 * drm_edid_header_is_valid - sanity check the header of the base EDID block
5d96fc9c 1744 * @_edid: pointer to raw base EDID block
db6cf833
TR		 1745 *
1746 * Sanity check the header of the base EDID block.
1747 *
1748 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
051963d4 1749 */
6d987ddd 1750int drm_edid_header_is_valid(const void *_edid)
051963d4 1751{
6d987ddd 1752 const struct edid *edid = _edid;
051963d4
TR		 1753 int i, score = 0;
1754
6d987ddd
JN		 1755 for (i = 0; i < sizeof(edid_header); i++) {
1756 if (edid->header[i] == edid_header[i])
051963d4 1757 score++;
6d987ddd 1758 }
051963d4
TR		 1759
1760 return score;
1761}
1762EXPORT_SYMBOL(drm_edid_header_is_valid);
1763
47819ba2
AJ		 1764static int edid_fixup __read_mostly = 6;
1765module_param_named(edid_fixup, edid_fixup, int, 0400);
1766MODULE_PARM_DESC(edid_fixup,
1767 "Minimum number of valid EDID header bytes (0-8, default 6)");
051963d4 1768
70e49ebe 1769static int edid_block_compute_checksum(const void *_block)
c465bbc8 1770{
70e49ebe 1771 const u8 *block = _block;
c465bbc8 1772 int i;
e11f5bd8
JFZ		 1773 u8 csum = 0, crc = 0;
1774
1775 for (i = 0; i < EDID_LENGTH - 1; i++)
70e49ebe 1776 csum += block[i];
c465bbc8 1777
e11f5bd8
JFZ		 1778 crc = 0x100 - csum;
1779
1780 return crc;
1781}
1782
70e49ebe 1783static int edid_block_get_checksum(const void *_block)
e11f5bd8 1784{
70e49ebe
JN		 1785 const struct edid *block = _block;
1786
1787 return block->checksum;
c465bbc8
SB		 1788}
1789
4ba0f53c
JN		 1790static int edid_block_tag(const void *_block)
1791{
1792 const u8 *block = _block;
1793
1794 return block[0];
1795}
1796
8baccb27 1797static bool edid_block_is_zero(const void *edid)
d6885d65 1798{
8baccb27 1799 return !memchr_inv(edid, 0, EDID_LENGTH);
d6885d65
SB		 1800}
1801
536faa45
SL		 1802/**
1803 * drm_edid_are_equal - compare two edid blobs.
1804 * @edid1: pointer to first blob
1805 * @edid2: pointer to second blob
1806 * This helper can be used during probing to determine if
1807 * edid had changed.
1808 */
1809bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2)
1810{
1811 int edid1_len, edid2_len;
1812 bool edid1_present = edid1 != NULL;
1813 bool edid2_present = edid2 != NULL;
1814
1815 if (edid1_present != edid2_present)
1816 return false;
1817
1818 if (edid1) {
f1e4c916
JN		 1819 edid1_len = edid_size(edid1);
1820 edid2_len = edid_size(edid2);
536faa45
SL		 1821
1822 if (edid1_len != edid2_len)
1823 return false;
1824
1825 if (memcmp(edid1, edid2, edid1_len))
1826 return false;
1827 }
1828
1829 return true;
1830}
1831EXPORT_SYMBOL(drm_edid_are_equal);
1832
1f221284
JN		 1833enum edid_block_status {
1834 EDID_BLOCK_OK = 0,
2deaf1c2 1835 EDID_BLOCK_READ_FAIL,
1f221284 1836 EDID_BLOCK_NULL,
49dc0558 1837 EDID_BLOCK_ZERO,
1f221284
JN		 1838 EDID_BLOCK_HEADER_CORRUPT,
1839 EDID_BLOCK_HEADER_REPAIR,
1840 EDID_BLOCK_HEADER_FIXED,
1841 EDID_BLOCK_CHECKSUM,
1842 EDID_BLOCK_VERSION,
1843};
1844
1845static enum edid_block_status edid_block_check(const void *_block,
1846 bool is_base_block)
1847{
1848 const struct edid *block = _block;
1849
1850 if (!block)
1851 return EDID_BLOCK_NULL;
1852
1853 if (is_base_block) {
1854 int score = drm_edid_header_is_valid(block);
1855
49dc0558
JN		 1856 if (score < clamp(edid_fixup, 0, 8)) {
1857 if (edid_block_is_zero(block))
1858 return EDID_BLOCK_ZERO;
1859 else
1860 return EDID_BLOCK_HEADER_CORRUPT;
1861 }
1f221284
JN		 1862
1863 if (score < 8)
1864 return EDID_BLOCK_HEADER_REPAIR;
1865 }
1866
49dc0558
JN		 1867 if (edid_block_compute_checksum(block) != edid_block_get_checksum(block)) {
1868 if (edid_block_is_zero(block))
1869 return EDID_BLOCK_ZERO;
1870 else
1871 return EDID_BLOCK_CHECKSUM;
1872 }
1f221284
JN		 1873
1874 if (is_base_block) {
1875 if (block->version != 1)
1876 return EDID_BLOCK_VERSION;
1877 }
1878
1879 return EDID_BLOCK_OK;
1880}
1881
1882static bool edid_block_status_valid(enum edid_block_status status, int tag)
1883{
1884 return status == EDID_BLOCK_OK ||
1885 status == EDID_BLOCK_HEADER_FIXED ||
1886 (status == EDID_BLOCK_CHECKSUM && tag == CEA_EXT);
1887}
1888
23e38d7b
JN		 1889static bool edid_block_valid(const void *block, bool base)
1890{
1891 return edid_block_status_valid(edid_block_check(block, base),
1892 edid_block_tag(block));
1893}
1894
cee2ce1a
JN		 1895static void edid_block_status_print(enum edid_block_status status,
1896 const struct edid *block,
1897 int block_num)
1898{
1899 switch (status) {
1900 case EDID_BLOCK_OK:
1901 break;
2deaf1c2
JN		 1902 case EDID_BLOCK_READ_FAIL:
1903 pr_debug("EDID block %d read failed\n", block_num);
1904 break;
cee2ce1a
JN		 1905 case EDID_BLOCK_NULL:
1906 pr_debug("EDID block %d pointer is NULL\n", block_num);
1907 break;
1908 case EDID_BLOCK_ZERO:
1909 pr_notice("EDID block %d is all zeroes\n", block_num);
1910 break;
1911 case EDID_BLOCK_HEADER_CORRUPT:
1912 pr_notice("EDID has corrupt header\n");
1913 break;
1914 case EDID_BLOCK_HEADER_REPAIR:
1915 pr_debug("EDID corrupt header needs repair\n");
1916 break;
1917 case EDID_BLOCK_HEADER_FIXED:
1918 pr_debug("EDID corrupt header fixed\n");
1919 break;
1920 case EDID_BLOCK_CHECKSUM:
1921 if (edid_block_status_valid(status, edid_block_tag(block))) {
1922 pr_debug("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d, ignoring\n",
1923 block_num, edid_block_tag(block),
1924 edid_block_compute_checksum(block));
1925 } else {
1926 pr_notice("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d\n",
1927 block_num, edid_block_tag(block),
1928 edid_block_compute_checksum(block));
1929 }
1930 break;
1931 case EDID_BLOCK_VERSION:
1932 pr_notice("EDID has major version %d, instead of 1\n",
1933 block->version);
1934 break;
1935 default:
1936 WARN(1, "EDID block %d unknown edid block status code %d\n",
1937 block_num, status);
1938 break;
1939 }
1940}
1941
9c7345de
JN		 1942static void edid_block_dump(const char *level, const void *block, int block_num)
1943{
1944 enum edid_block_status status;
1945 char prefix[20];
1946
1947 status = edid_block_check(block, block_num == 0);
1948 if (status == EDID_BLOCK_ZERO)
1949 sprintf(prefix, "\t[%02x] ZERO ", block_num);
1950 else if (!edid_block_status_valid(status, edid_block_tag(block)))
1951 sprintf(prefix, "\t[%02x] BAD ", block_num);
1952 else
1953 sprintf(prefix, "\t[%02x] GOOD ", block_num);
1954
1955 print_hex_dump(level, prefix, DUMP_PREFIX_NONE, 16, 1,
1956 block, EDID_LENGTH, false);
1957}
1958
db6cf833
TR		 1959/**
1960 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
5d96fc9c 1961 * @_block: pointer to raw EDID block
1f221284 1962 * @block_num: type of block to validate (0 for base, extension otherwise)
db6cf833 1963 * @print_bad_edid: if true, dump bad EDID blocks to the console
6ba2bd3d 1964 * @edid_corrupt: if true, the header or checksum is invalid
db6cf833
TR		 1965 *
1966 * Validate a base or extension EDID block and optionally dump bad blocks to
1967 * the console.
1968 *
1969 * Return: True if the block is valid, false otherwise.
f453ba04 1970 */
1f221284 1971bool drm_edid_block_valid(u8 *_block, int block_num, bool print_bad_edid,
6ba2bd3d 1972 bool *edid_corrupt)
f453ba04 1973{
1f221284
JN		 1974 struct edid *block = (struct edid *)_block;
1975 enum edid_block_status status;
1976 bool is_base_block = block_num == 0;
1977 bool valid;
f453ba04 1978
1f221284 1979 if (WARN_ON(!block))
fe2ef780
SWK		 1980 return false;
1981
1f221284
JN		 1982 status = edid_block_check(block, is_base_block);
1983 if (status == EDID_BLOCK_HEADER_REPAIR) {
1984 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1985 edid_header_fix(block);
1986
1987 /* Retry with fixed header, update status if that worked. */
1988 status = edid_block_check(block, is_base_block);
1989 if (status == EDID_BLOCK_OK)
1990 status = EDID_BLOCK_HEADER_FIXED;
61e57a8d 1991 }
f453ba04 1992
1f221284
JN		 1993 if (edid_corrupt) {
1994 /*
1995 * Unknown major version isn't corrupt but we can't use it. Only
1996 * the base block can reset edid_corrupt to false.
1997 */
1998 if (is_base_block &&
1999 (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION))
2000 *edid_corrupt = false;
2001 else if (status != EDID_BLOCK_OK)
ac6f2e29 2002 *edid_corrupt = true;
f453ba04
DA		 2003 }
2004
cee2ce1a
JN		 2005 edid_block_status_print(status, block, block_num);
2006
1f221284
JN		 2007 /* Determine whether we can use this block with this status. */
2008 valid = edid_block_status_valid(status, edid_block_tag(block));
2009
cee2ce1a
JN		 2010 if (!valid && print_bad_edid && status != EDID_BLOCK_ZERO) {
2011 pr_notice("Raw EDID:\n");
9c7345de 2012 edid_block_dump(KERN_NOTICE, block, block_num);
f453ba04 2013 }
1f221284
JN		 2014
2015 return valid;
f453ba04 2016}
da0df92b 2017EXPORT_SYMBOL(drm_edid_block_valid);
61e57a8d
AJ		 2018
2019/**
2020 * drm_edid_is_valid - sanity check EDID data
2021 * @edid: EDID data
2022 *
2023 * Sanity-check an entire EDID record (including extensions)
db6cf833
TR		 2024 *
2025 * Return: True if the EDID data is valid, false otherwise.
61e57a8d
AJ		 2026 */
2027bool drm_edid_is_valid(struct edid *edid)
2028{
2029 int i;
61e57a8d
AJ		 2030
2031 if (!edid)
2032 return false;
2033
f1e4c916
JN		 2034 for (i = 0; i < edid_block_count(edid); i++) {
2035 void *block = (void *)edid_block_data(edid, i);
2036
2037 if (!drm_edid_block_valid(block, i, true, NULL))
61e57a8d 2038 return false;
f1e4c916 2039 }
61e57a8d
AJ		 2040
2041 return true;
2042}
3c537889 2043EXPORT_SYMBOL(drm_edid_is_valid);
f453ba04 2044
89f4b4c5 2045static struct edid *edid_filter_invalid_blocks(struct edid *edid,
407d63b3 2046 size_t *alloc_size)
4ec53461 2047{
89f4b4c5
JN		 2048 struct edid *new;
2049 int i, valid_blocks = 0;
4ec53461 2050
18e3c1d5
JN		 2051 /*
2052 * Note: If the EDID uses HF-EEODB, but has invalid blocks, we'll revert
2053 * back to regular extension count here. We don't want to start
2054 * modifying the HF-EEODB extension too.
2055 */
89f4b4c5
JN		 2056 for (i = 0; i < edid_block_count(edid); i++) {
2057 const void *src_block = edid_block_data(edid, i);
407d63b3 2058
89f4b4c5
JN		 2059 if (edid_block_valid(src_block, i == 0)) {
2060 void *dst_block = (void *)edid_block_data(edid, valid_blocks);
4ec53461 2061
89f4b4c5
JN		 2062 memmove(dst_block, src_block, EDID_LENGTH);
2063 valid_blocks++;
2064 }
2065 }
4ec53461 2066
89f4b4c5
JN		 2067 /* We already trusted the base block to be valid here... */
2068 if (WARN_ON(!valid_blocks)) {
2069 kfree(edid);
2070 return NULL;
4ec53461
JN		 2071 }
2072
89f4b4c5
JN		 2073 edid->extensions = valid_blocks - 1;
2074 edid->checksum = edid_block_compute_checksum(edid);
4ec53461 2075
89f4b4c5
JN		 2076 *alloc_size = edid_size_by_blocks(valid_blocks);
2077
2078 new = krealloc(edid, *alloc_size, GFP_KERNEL);
2079 if (!new)
2080 kfree(edid);
4ec53461
JN		 2081
2082 return new;
2083}
2084
61e57a8d
AJ		 2085#define DDC_SEGMENT_ADDR 0x30
2086/**
db6cf833 2087 * drm_do_probe_ddc_edid() - get EDID information via I2C
7c58e87e 2088 * @data: I2C device adapter
fc66811c
DV		 2089 * @buf: EDID data buffer to be filled
2090 * @block: 128 byte EDID block to start fetching from
2091 * @len: EDID data buffer length to fetch
2092 *
db6cf833 2093 * Try to fetch EDID information by calling I2C driver functions.
61e57a8d 2094 *
db6cf833 2095 * Return: 0 on success or -1 on failure.
61e57a8d
AJ		 2096 */
2097static int
18df89fe 2098drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
61e57a8d 2099{
18df89fe 2100 struct i2c_adapter *adapter = data;
61e57a8d 2101 unsigned char start = block * EDID_LENGTH;
cd004b3f
S		 2102 unsigned char segment = block >> 1;
2103 unsigned char xfers = segment ? 3 : 2;
4819d2e4
CW		 2104 int ret, retries = 5;
2105
db6cf833
TR		 2106 /*
2107 * The core I2C driver will automatically retry the transfer if the
4819d2e4
CW		 2108 * adapter reports EAGAIN. However, we find that bit-banging transfers
2109 * are susceptible to errors under a heavily loaded machine and
2110 * generate spurious NAKs and timeouts. Retrying the transfer
2111 * of the individual block a few times seems to overcome this.
2112 */
2113 do {
2114 struct i2c_msg msgs[] = {
2115 {
cd004b3f
S		 2116 .addr = DDC_SEGMENT_ADDR,
2117 .flags = 0,
2118 .len = 1,
2119 .buf = &segment,
2120 }, {
4819d2e4
CW		 2121 .addr = DDC_ADDR,
2122 .flags = 0,
2123 .len = 1,
2124 .buf = &start,
2125 }, {
2126 .addr = DDC_ADDR,
2127 .flags = I2C_M_RD,
2128 .len = len,
2129 .buf = buf,
2130 }
2131 };
cd004b3f 2132
db6cf833
TR		 2133 /*
2134 * Avoid sending the segment addr to not upset non-compliant
2135 * DDC monitors.
2136 */
cd004b3f
S		 2137 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
2138
9292f37e
ED		 2139 if (ret == -ENXIO) {
2140 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
2141 adapter->name);
2142 break;
2143 }
cd004b3f 2144 } while (ret != xfers && --retries);
4819d2e4 2145
cd004b3f 2146 return ret == xfers ? 0 : -1;
61e57a8d
AJ		 2147}
2148
14544d09 2149static void connector_bad_edid(struct drm_connector *connector,
63cae081 2150 const struct edid *edid, int num_blocks)
14544d09
CW		 2151{
2152 int i;
97794170
DA		 2153 u8 last_block;
2154
2155 /*
2156 * 0x7e in the EDID is the number of extension blocks. The EDID
2157 * is 1 (base block) + num_ext_blocks big. That means we can think
2158 * of 0x7e in the EDID of the _index_ of the last block in the
2159 * combined chunk of memory.
2160 */
63cae081 2161 last_block = edid->extensions;
e11f5bd8
JFZ		 2162
2163 /* Calculate real checksum for the last edid extension block data */
97794170
DA		 2164 if (last_block < num_blocks)
2165 connector->real_edid_checksum =
63cae081 2166 edid_block_compute_checksum(edid + last_block);
14544d09 2167
f0a8f533 2168 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
14544d09
CW		 2169 return;
2170
fa3bfa35 2171 drm_dbg_kms(connector->dev, "%s: EDID is invalid:\n", connector->name);
63cae081
JN		 2172 for (i = 0; i < num_blocks; i++)
2173 edid_block_dump(KERN_DEBUG, edid + i, i);
14544d09
CW		 2174}
2175
56a2b7f2 2176/* Get override or firmware EDID */
407d63b3
JN		 2177static struct edid *drm_get_override_edid(struct drm_connector *connector,
2178 size_t *alloc_size)
56a2b7f2
JN		 2179{
2180 struct edid *override = NULL;
2181
2182 if (connector->override_edid)
2183 override = drm_edid_duplicate(connector->edid_blob_ptr->data);
2184
2185 if (!override)
2186 override = drm_load_edid_firmware(connector);
2187
407d63b3
JN		 2188 /* FIXME: Get alloc size from deeper down the stack */
2189 if (!IS_ERR_OR_NULL(override) && alloc_size)
2190 *alloc_size = edid_size(override);
2191
56a2b7f2
JN		 2192 return IS_ERR(override) ? NULL : override;
2193}
2194
6aa145bc
JN		 2195/* For debugfs edid_override implementation */
2196int drm_edid_override_set(struct drm_connector *connector, const void *edid,
2197 size_t size)
2198{
2199 int ret;
2200
2201 if (size < EDID_LENGTH || edid_size(edid) > size)
2202 return -EINVAL;
2203
2204 connector->override_edid = false;
2205
2206 ret = drm_connector_update_edid_property(connector, edid);
2207 if (!ret)
2208 connector->override_edid = true;
2209
2210 return ret;
2211}
2212
2213/* For debugfs edid_override implementation */
2214int drm_edid_override_reset(struct drm_connector *connector)
2215{
2216 connector->override_edid = false;
2217
2218 return drm_connector_update_edid_property(connector, NULL);
2219}
2220
48eaeb76
JN		 2221/**
2222 * drm_add_override_edid_modes - add modes from override/firmware EDID
2223 * @connector: connector we're probing
2224 *
2225 * Add modes from the override/firmware EDID, if available. Only to be used from
2226 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
2227 * failed during drm_get_edid() and caused the override/firmware EDID to be
2228 * skipped.
2229 *
2230 * Return: The number of modes added or 0 if we couldn't find any.
2231 */
2232int drm_add_override_edid_modes(struct drm_connector *connector)
2233{
2234 struct edid *override;
2235 int num_modes = 0;
2236
407d63b3 2237 override = drm_get_override_edid(connector, NULL);
48eaeb76
JN		 2238 if (override) {
2239 drm_connector_update_edid_property(connector, override);
2240 num_modes = drm_add_edid_modes(connector, override);
2241 kfree(override);
2242
2243 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
2244 connector->base.id, connector->name, num_modes);
2245 }
2246
2247 return num_modes;
2248}
2249EXPORT_SYMBOL(drm_add_override_edid_modes);
2250
89fb7536
JN		 2251typedef int read_block_fn(void *context, u8 *buf, unsigned int block, size_t len);
2252
2deaf1c2
JN		 2253static enum edid_block_status edid_block_read(void *block, unsigned int block_num,
2254 read_block_fn read_block,
2255 void *context)
2256{
2257 enum edid_block_status status;
2258 bool is_base_block = block_num == 0;
2259 int try;
2260
2261 for (try = 0; try < 4; try++) {
2262 if (read_block(context, block, block_num, EDID_LENGTH))
2263 return EDID_BLOCK_READ_FAIL;
2264
2265 status = edid_block_check(block, is_base_block);
2266 if (status == EDID_BLOCK_HEADER_REPAIR) {
2267 edid_header_fix(block);
2268
2269 /* Retry with fixed header, update status if that worked. */
2270 status = edid_block_check(block, is_base_block);
2271 if (status == EDID_BLOCK_OK)
2272 status = EDID_BLOCK_HEADER_FIXED;
2273 }
2274
2275 if (edid_block_status_valid(status, edid_block_tag(block)))
2276 break;
2277
2278 /* Fail early for unrepairable base block all zeros. */
2279 if (try == 0 && is_base_block && status == EDID_BLOCK_ZERO)
2280 break;
2281 }
2282
2283 return status;
2284}
2285
6537f79a
JN		 2286static struct edid *_drm_do_get_edid(struct drm_connector *connector,
2287 read_block_fn read_block, void *context,
2288 size_t *size)
61e57a8d 2289{
c12561ce 2290 enum edid_block_status status;
18e3c1d5 2291 int i, num_blocks, invalid_blocks = 0;
b3eb97b6 2292 struct edid *edid, *new;
407d63b3 2293 size_t alloc_size = EDID_LENGTH;
53fd40a9 2294
407d63b3 2295 edid = drm_get_override_edid(connector, &alloc_size);
b3eb97b6 2296 if (edid)
1c788f69 2297 goto ok;
61e57a8d 2298
407d63b3 2299 edid = kmalloc(alloc_size, GFP_KERNEL);
e7bd95a7 2300 if (!edid)
61e57a8d 2301 return NULL;
61e57a8d 2302
c12561ce
JN		 2303 status = edid_block_read(edid, 0, read_block, context);
2304
2305 edid_block_status_print(status, edid, 0);
2306
2307 if (status == EDID_BLOCK_READ_FAIL)
1c788f69 2308 goto fail;
c12561ce
JN		 2309
2310 /* FIXME: Clarify what a corrupt EDID actually means. */
2311 if (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION)
2312 connector->edid_corrupt = false;
2313 else
2314 connector->edid_corrupt = true;
2315
2316 if (!edid_block_status_valid(status, edid_block_tag(edid))) {
2317 if (status == EDID_BLOCK_ZERO)
2318 connector->null_edid_counter++;
2319
2320 connector_bad_edid(connector, edid, 1);
1c788f69 2321 goto fail;
c12561ce
JN		 2322 }
2323
f1e4c916 2324 if (!edid_extension_block_count(edid))
1c788f69 2325 goto ok;
61e57a8d 2326
407d63b3
JN		 2327 alloc_size = edid_size(edid);
2328 new = krealloc(edid, alloc_size, GFP_KERNEL);
61e57a8d 2329 if (!new)
1c788f69 2330 goto fail;
f14f3686 2331 edid = new;
61e57a8d 2332
18e3c1d5
JN		 2333 num_blocks = edid_block_count(edid);
2334 for (i = 1; i < num_blocks; i++) {
f1e4c916 2335 void *block = (void *)edid_block_data(edid, i);
a28187cc 2336
f1e4c916 2337 status = edid_block_read(block, i, read_block, context);
d3da3f40 2338
f1e4c916 2339 edid_block_status_print(status, block, i);
f934ec8c 2340
d3da3f40
JN		 2341 if (!edid_block_status_valid(status, edid_block_tag(block))) {
2342 if (status == EDID_BLOCK_READ_FAIL)
1c788f69 2343 goto fail;
ccc97def 2344 invalid_blocks++;
18e3c1d5
JN		 2345 } else if (i == 1) {
2346 /*
2347 * If the first EDID extension is a CTA extension, and
2348 * the first Data Block is HF-EEODB, override the
2349 * extension block count.
2350 *
2351 * Note: HF-EEODB could specify a smaller extension
2352 * count too, but we can't risk allocating a smaller
2353 * amount.
2354 */
2355 int eeodb = edid_hfeeodb_block_count(edid);
2356
2357 if (eeodb > num_blocks) {
2358 num_blocks = eeodb;
2359 alloc_size = edid_size_by_blocks(num_blocks);
2360 new = krealloc(edid, alloc_size, GFP_KERNEL);
2361 if (!new)
2362 goto fail;
2363 edid = new;
2364 }
d3da3f40 2365 }
0ea75e23
ST		 2366 }
2367
ccc97def 2368 if (invalid_blocks) {
18e3c1d5 2369 connector_bad_edid(connector, edid, num_blocks);
14544d09 2370
89f4b4c5 2371 edid = edid_filter_invalid_blocks(edid, &alloc_size);
61e57a8d
AJ		 2372 }
2373
1c788f69 2374ok:
6537f79a
JN		 2375 if (size)
2376 *size = alloc_size;
2377
e9a9e076 2378 return edid;
61e57a8d 2379
1c788f69 2380fail:
f14f3686 2381 kfree(edid);
61e57a8d
AJ		 2382 return NULL;
2383}
6537f79a
JN		 2384
2385/**
2386 * drm_do_get_edid - get EDID data using a custom EDID block read function
2387 * @connector: connector we're probing
2388 * @read_block: EDID block read function
2389 * @context: private data passed to the block read function
2390 *
2391 * When the I2C adapter connected to the DDC bus is hidden behind a device that
2392 * exposes a different interface to read EDID blocks this function can be used
2393 * to get EDID data using a custom block read function.
2394 *
2395 * As in the general case the DDC bus is accessible by the kernel at the I2C
2396 * level, drivers must make all reasonable efforts to expose it as an I2C
2397 * adapter and use drm_get_edid() instead of abusing this function.
2398 *
2399 * The EDID may be overridden using debugfs override_edid or firmware EDID
2400 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
2401 * order. Having either of them bypasses actual EDID reads.
2402 *
2403 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2404 */
2405struct edid *drm_do_get_edid(struct drm_connector *connector,
2406 read_block_fn read_block,
2407 void *context)
2408{
2409 return _drm_do_get_edid(connector, read_block, context, NULL);
2410}
18df89fe 2411EXPORT_SYMBOL_GPL(drm_do_get_edid);
61e57a8d 2412
3d1ab66e
JN		 2413/**
2414 * drm_edid_raw - Get a pointer to the raw EDID data.
2415 * @drm_edid: drm_edid container
2416 *
2417 * Get a pointer to the raw EDID data.
2418 *
2419 * This is for transition only. Avoid using this like the plague.
2420 *
2421 * Return: Pointer to raw EDID data.
2422 */
2423const struct edid *drm_edid_raw(const struct drm_edid *drm_edid)
2424{
2425 if (!drm_edid || !drm_edid->size)
2426 return NULL;
2427
2428 /*
2429 * Do not return pointers where relying on EDID extension count would
2430 * lead to buffer overflow.
2431 */
2432 if (WARN_ON(edid_size(drm_edid->edid) > drm_edid->size))
2433 return NULL;
2434
2435 return drm_edid->edid;
2436}
2437EXPORT_SYMBOL(drm_edid_raw);
2438
6537f79a
JN		 2439/* Allocate struct drm_edid container *without* duplicating the edid data */
2440static const struct drm_edid *_drm_edid_alloc(const void *edid, size_t size)
2441{
2442 struct drm_edid *drm_edid;
2443
2444 if (!edid || !size || size < EDID_LENGTH)
2445 return NULL;
2446
2447 drm_edid = kzalloc(sizeof(*drm_edid), GFP_KERNEL);
2448 if (drm_edid) {
2449 drm_edid->edid = edid;
2450 drm_edid->size = size;
2451 }
2452
2453 return drm_edid;
2454}
2455
2456/**
2457 * drm_edid_alloc - Allocate a new drm_edid container
2458 * @edid: Pointer to raw EDID data
2459 * @size: Size of memory allocated for EDID
2460 *
2461 * Allocate a new drm_edid container. Do not calculate edid size from edid, pass
2462 * the actual size that has been allocated for the data. There is no validation
2463 * of the raw EDID data against the size, but at least the EDID base block must
2464 * fit in the buffer.
2465 *
2466 * The returned pointer must be freed using drm_edid_free().
2467 *
2468 * Return: drm_edid container, or NULL on errors
2469 */
2470const struct drm_edid *drm_edid_alloc(const void *edid, size_t size)
2471{
2472 const struct drm_edid *drm_edid;
2473
2474 if (!edid || !size || size < EDID_LENGTH)
2475 return NULL;
2476
2477 edid = kmemdup(edid, size, GFP_KERNEL);
2478 if (!edid)
2479 return NULL;
2480
2481 drm_edid = _drm_edid_alloc(edid, size);
2482 if (!drm_edid)
2483 kfree(edid);
2484
2485 return drm_edid;
2486}
2487EXPORT_SYMBOL(drm_edid_alloc);
2488
2489/**
2490 * drm_edid_dup - Duplicate a drm_edid container
2491 * @drm_edid: EDID to duplicate
2492 *
2493 * The returned pointer must be freed using drm_edid_free().
2494 *
2495 * Returns: drm_edid container copy, or NULL on errors
2496 */
2497const struct drm_edid *drm_edid_dup(const struct drm_edid *drm_edid)
2498{
2499 if (!drm_edid)
2500 return NULL;
2501
2502 return drm_edid_alloc(drm_edid->edid, drm_edid->size);
2503}
2504EXPORT_SYMBOL(drm_edid_dup);
2505
2506/**
2507 * drm_edid_free - Free the drm_edid container
2508 * @drm_edid: EDID to free
2509 */
2510void drm_edid_free(const struct drm_edid *drm_edid)
2511{
2512 if (!drm_edid)
2513 return;
2514
2515 kfree(drm_edid->edid);
2516 kfree(drm_edid);
2517}
2518EXPORT_SYMBOL(drm_edid_free);
2519
61e57a8d 2520/**
db6cf833
TR		 2521 * drm_probe_ddc() - probe DDC presence
2522 * @adapter: I2C adapter to probe
fc66811c 2523 *
db6cf833 2524 * Return: True on success, false on failure.
61e57a8d 2525 */
fbff4690 2526bool
61e57a8d
AJ		 2527drm_probe_ddc(struct i2c_adapter *adapter)
2528{
2529 unsigned char out;
2530
2531 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
2532}
fbff4690 2533EXPORT_SYMBOL(drm_probe_ddc);
61e57a8d
AJ		 2534
2535/**
2536 * drm_get_edid - get EDID data, if available
2537 * @connector: connector we're probing
db6cf833 2538 * @adapter: I2C adapter to use for DDC
61e57a8d 2539 *
db6cf833 2540 * Poke the given I2C channel to grab EDID data if possible. If found,
61e57a8d
AJ		 2541 * attach it to the connector.
2542 *
db6cf833 2543 * Return: Pointer to valid EDID or NULL if we couldn't find any.
61e57a8d
AJ		 2544 */
2545struct edid *drm_get_edid(struct drm_connector *connector,
2546 struct i2c_adapter *adapter)
2547{
5186421c
SL		 2548 struct edid *edid;
2549
15f080f0
JN		 2550 if (connector->force == DRM_FORCE_OFF)
2551 return NULL;
2552
2553 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
18df89fe 2554 return NULL;
61e57a8d 2555
6537f79a 2556 edid = _drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter, NULL);
5186421c
SL		 2557 drm_connector_update_edid_property(connector, edid);
2558 return edid;
61e57a8d
AJ		 2559}
2560EXPORT_SYMBOL(drm_get_edid);
2561
6537f79a
JN		 2562/**
2563 * drm_edid_read_custom - Read EDID data using given EDID block read function
2564 * @connector: Connector to use
2565 * @read_block: EDID block read function
2566 * @context: Private data passed to the block read function
2567 *
2568 * When the I2C adapter connected to the DDC bus is hidden behind a device that
2569 * exposes a different interface to read EDID blocks this function can be used
2570 * to get EDID data using a custom block read function.
2571 *
2572 * As in the general case the DDC bus is accessible by the kernel at the I2C
2573 * level, drivers must make all reasonable efforts to expose it as an I2C
2574 * adapter and use drm_edid_read() or drm_edid_read_ddc() instead of abusing
2575 * this function.
2576 *
2577 * The EDID may be overridden using debugfs override_edid or firmware EDID
2578 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
2579 * order. Having either of them bypasses actual EDID reads.
2580 *
2581 * The returned pointer must be freed using drm_edid_free().
2582 *
2583 * Return: Pointer to EDID, or NULL if probe/read failed.
2584 */
2585const struct drm_edid *drm_edid_read_custom(struct drm_connector *connector,
2586 read_block_fn read_block,
2587 void *context)
2588{
2589 const struct drm_edid *drm_edid;
2590 struct edid *edid;
2591 size_t size = 0;
2592
2593 edid = _drm_do_get_edid(connector, read_block, context, &size);
2594 if (!edid)
2595 return NULL;
2596
2597 /* Sanity check for now */
2598 drm_WARN_ON(connector->dev, !size);
2599
2600 drm_edid = _drm_edid_alloc(edid, size);
2601 if (!drm_edid)
2602 kfree(edid);
2603
2604 return drm_edid;
2605}
2606EXPORT_SYMBOL(drm_edid_read_custom);
2607
2608/**
2609 * drm_edid_read_ddc - Read EDID data using given I2C adapter
2610 * @connector: Connector to use
2611 * @adapter: I2C adapter to use for DDC
2612 *
2613 * Read EDID using the given I2C adapter.
2614 *
2615 * The EDID may be overridden using debugfs override_edid or firmware EDID
2616 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
2617 * order. Having either of them bypasses actual EDID reads.
2618 *
2619 * Prefer initializing connector->ddc with drm_connector_init_with_ddc() and
2620 * using drm_edid_read() instead of this function.
2621 *
2622 * The returned pointer must be freed using drm_edid_free().
2623 *
2624 * Return: Pointer to EDID, or NULL if probe/read failed.
2625 */
2626const struct drm_edid *drm_edid_read_ddc(struct drm_connector *connector,
2627 struct i2c_adapter *adapter)
2628{
2629 const struct drm_edid *drm_edid;
2630
2631 if (connector->force == DRM_FORCE_OFF)
2632 return NULL;
2633
2634 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2635 return NULL;
2636
2637 drm_edid = drm_edid_read_custom(connector, drm_do_probe_ddc_edid, adapter);
2638
2639 /* Note: Do *not* call connector updates here. */
2640
2641 return drm_edid;
2642}
2643EXPORT_SYMBOL(drm_edid_read_ddc);
2644
2645/**
2646 * drm_edid_read - Read EDID data using connector's I2C adapter
2647 * @connector: Connector to use
2648 *
2649 * Read EDID using the connector's I2C adapter.
2650 *
2651 * The EDID may be overridden using debugfs override_edid or firmware EDID
2652 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
2653 * order. Having either of them bypasses actual EDID reads.
2654 *
2655 * The returned pointer must be freed using drm_edid_free().
2656 *
2657 * Return: Pointer to EDID, or NULL if probe/read failed.
2658 */
2659const struct drm_edid *drm_edid_read(struct drm_connector *connector)
2660{
2661 if (drm_WARN_ON(connector->dev, !connector->ddc))
2662 return NULL;
2663
2664 return drm_edid_read_ddc(connector, connector->ddc);
2665}
2666EXPORT_SYMBOL(drm_edid_read);
2667
d9f91a10
DA		 2668static u32 edid_extract_panel_id(const struct edid *edid)
2669{
2670 /*
e8de4d55
DA		 2671 * We represent the ID as a 32-bit number so it can easily be compared
2672 * with "==".
d9f91a10
DA		 2673 *
2674 * NOTE that we deal with endianness differently for the top half
2675 * of this ID than for the bottom half. The bottom half (the product
2676 * id) gets decoded as little endian by the EDID_PRODUCT_ID because
2677 * that's how everyone seems to interpret it. The top half (the mfg_id)
2678 * gets stored as big endian because that makes
2679 * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier
2680 * to write (it's easier to extract the ASCII). It doesn't really
2681 * matter, though, as long as the number here is unique.
2682 */
2683 return (u32)edid->mfg_id[0] << 24 |
2684 (u32)edid->mfg_id[1] << 16 |
2685 (u32)EDID_PRODUCT_ID(edid);
2686}
2687
2688/**
2689 * drm_edid_get_panel_id - Get a panel's ID through DDC
2690 * @adapter: I2C adapter to use for DDC
2691 *
2692 * This function reads the first block of the EDID of a panel and (assuming
2693 * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value
2694 * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's
2695 * supposed to be different for each different modem of panel.
2696 *
2697 * This function is intended to be used during early probing on devices where
2698 * more than one panel might be present. Because of its intended use it must
2699 * assume that the EDID of the panel is correct, at least as far as the ID
2700 * is concerned (in other words, we don't process any overrides here).
2701 *
2702 * NOTE: it's expected that this function and drm_do_get_edid() will both
2703 * be read the EDID, but there is no caching between them. Since we're only
2704 * reading the first block, hopefully this extra overhead won't be too big.
2705 *
2706 * Return: A 32-bit ID that should be different for each make/model of panel.
2707 * See the functions drm_edid_encode_panel_id() and
2708 * drm_edid_decode_panel_id() for some details on the structure of this
2709 * ID.
2710 */
2711
2712u32 drm_edid_get_panel_id(struct i2c_adapter *adapter)
2713{
2deaf1c2
JN		 2714 enum edid_block_status status;
2715 void *base_block;
2716 u32 panel_id = 0;
d9f91a10
DA		 2717
2718 /*
2719 * There are no manufacturer IDs of 0, so if there is a problem reading
2720 * the EDID then we'll just return 0.
2721 */
2deaf1c2
JN		 2722
2723 base_block = kmalloc(EDID_LENGTH, GFP_KERNEL);
2724 if (!base_block)
d9f91a10
DA		 2725 return 0;
2726
2deaf1c2
JN		 2727 status = edid_block_read(base_block, 0, drm_do_probe_ddc_edid, adapter);
2728
2729 edid_block_status_print(status, base_block, 0);
2730
2731 if (edid_block_status_valid(status, edid_block_tag(base_block)))
2732 panel_id = edid_extract_panel_id(base_block);
2733
2734 kfree(base_block);
d9f91a10
DA		 2735
2736 return panel_id;
2737}
2738EXPORT_SYMBOL(drm_edid_get_panel_id);
2739
5cb8eaa2
LW		 2740/**
2741 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
2742 * @connector: connector we're probing
2743 * @adapter: I2C adapter to use for DDC
2744 *
2745 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
2746 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
2747 * switch DDC to the GPU which is retrieving EDID.
2748 *
2749 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2750 */
2751struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
2752 struct i2c_adapter *adapter)
2753{
36b73b05
TZ		 2754 struct drm_device *dev = connector->dev;
2755 struct pci_dev *pdev = to_pci_dev(dev->dev);
5cb8eaa2
LW		 2756 struct edid *edid;
2757
36b73b05
TZ		 2758 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev)))
2759 return NULL;
2760
5cb8eaa2
LW		 2761 vga_switcheroo_lock_ddc(pdev);
2762 edid = drm_get_edid(connector, adapter);
2763 vga_switcheroo_unlock_ddc(pdev);
2764
2765 return edid;
2766}
2767EXPORT_SYMBOL(drm_get_edid_switcheroo);
2768
51f8da59
JN		 2769/**
2770 * drm_edid_duplicate - duplicate an EDID and the extensions
2771 * @edid: EDID to duplicate
2772 *
db6cf833 2773 * Return: Pointer to duplicated EDID or NULL on allocation failure.
51f8da59
JN		 2774 */
2775struct edid *drm_edid_duplicate(const struct edid *edid)
2776{
f1e4c916 2777 return kmemdup(edid, edid_size(edid), GFP_KERNEL);
51f8da59
JN		 2778}
2779EXPORT_SYMBOL(drm_edid_duplicate);
2780
61e57a8d
AJ		 2781/*** EDID parsing ***/
2782
f453ba04
DA		 2783/**
2784 * edid_get_quirks - return quirk flags for a given EDID
e42192b4 2785 * @drm_edid: EDID to process
f453ba04
DA		 2786 *
2787 * This tells subsequent routines what fixes they need to apply.
2788 */
e42192b4 2789static u32 edid_get_quirks(const struct drm_edid *drm_edid)
f453ba04 2790{
e42192b4 2791 u32 panel_id = edid_extract_panel_id(drm_edid->edid);
23c4cfbd 2792 const struct edid_quirk *quirk;
f453ba04
DA		 2793 int i;
2794
2795 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
2796 quirk = &edid_quirk_list[i];
e8de4d55 2797 if (quirk->panel_id == panel_id)
f453ba04
DA		 2798 return quirk->quirks;
2799 }
2800
2801 return 0;
2802}
2803
2804#define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
339d202c 2805#define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
f453ba04 2806
17edb8e1
JN		 2807/*
2808 * Walk the mode list for connector, clearing the preferred status on existing
2809 * modes and setting it anew for the right mode ala quirks.
f453ba04
DA		 2810 */
2811static void edid_fixup_preferred(struct drm_connector *connector,
2812 u32 quirks)
2813{
2814 struct drm_display_mode *t, *cur_mode, *preferred_mode;
f890607b 2815 int target_refresh = 0;
339d202c 2816 int cur_vrefresh, preferred_vrefresh;
f453ba04
DA		 2817
2818 if (list_empty(&connector->probed_modes))
2819 return;
2820
2821 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
2822 target_refresh = 60;
2823 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
2824 target_refresh = 75;
2825
2826 preferred_mode = list_first_entry(&connector->probed_modes,
2827 struct drm_display_mode, head);
2828
2829 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
2830 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
2831
2832 if (cur_mode == preferred_mode)
2833 continue;
2834
2835 /* Largest mode is preferred */
2836 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
2837 preferred_mode = cur_mode;
2838
0425662f
VS		 2839 cur_vrefresh = drm_mode_vrefresh(cur_mode);
2840 preferred_vrefresh = drm_mode_vrefresh(preferred_mode);
f453ba04
DA		 2841 /* At a given size, try to get closest to target refresh */
2842 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
339d202c
AD		 2843 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
2844 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
f453ba04
DA		 2845 preferred_mode = cur_mode;
2846 }
2847 }
2848
2849 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
2850}
2851
f6e252ba
AJ		 2852static bool
2853mode_is_rb(const struct drm_display_mode *mode)
2854{
2855 return (mode->htotal - mode->hdisplay == 160) &&
2856 (mode->hsync_end - mode->hdisplay == 80) &&
2857 (mode->hsync_end - mode->hsync_start == 32) &&
2858 (mode->vsync_start - mode->vdisplay == 3);
2859}
2860
33c7531d
AJ		 2861/*
2862 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
2863 * @dev: Device to duplicate against
2864 * @hsize: Mode width
2865 * @vsize: Mode height
2866 * @fresh: Mode refresh rate
f6e252ba 2867 * @rb: Mode reduced-blanking-ness
33c7531d
AJ		 2868 *
2869 * Walk the DMT mode list looking for a match for the given parameters.
db6cf833
TR		 2870 *
2871 * Return: A newly allocated copy of the mode, or NULL if not found.
33c7531d 2872 */
1d42bbc8 2873struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
f6e252ba
AJ		 2874 int hsize, int vsize, int fresh,
2875 bool rb)
559ee21d 2876{
07a5e632 2877 int i;
559ee21d 2878
a6b21831 2879 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
b1f559ec 2880 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
948de842 2881
f8b46a05
AJ		 2882 if (hsize != ptr->hdisplay)
2883 continue;
2884 if (vsize != ptr->vdisplay)
2885 continue;
2886 if (fresh != drm_mode_vrefresh(ptr))
2887 continue;
f6e252ba
AJ		 2888 if (rb != mode_is_rb(ptr))
2889 continue;
f8b46a05
AJ		 2890
2891 return drm_mode_duplicate(dev, ptr);
559ee21d 2892 }
f8b46a05
AJ		 2893
2894 return NULL;
559ee21d 2895}
1d42bbc8 2896EXPORT_SYMBOL(drm_mode_find_dmt);
23425cae 2897
e379814b 2898static bool is_display_descriptor(const struct detailed_timing *descriptor, u8 type)
a7a131ac 2899{
e379814b
JN		 2900 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
2901 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.pad1) != 2);
2902 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.type) != 3);
2903
2904 return descriptor->pixel_clock == 0 &&
2905 descriptor->data.other_data.pad1 == 0 &&
2906 descriptor->data.other_data.type == type;
a7a131ac
VS		 2907}
2908
a9b1f15f 2909static bool is_detailed_timing_descriptor(const struct detailed_timing *descriptor)
f447dd1f 2910{
a9b1f15f
JN		 2911 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
2912
2913 return descriptor->pixel_clock != 0;
f447dd1f
VS		 2914}
2915
4194442d 2916typedef void detailed_cb(const struct detailed_timing *timing, void *closure);
d1ff6409 2917
4d76a221 2918static void
eed628f1 2919cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
4d76a221 2920{
7304b981 2921 int i, n;
4966b2a9 2922 u8 d = ext[0x02];
eed628f1 2923 const u8 *det_base = ext + d;
4d76a221 2924
7304b981
VS		 2925 if (d < 4 || d > 127)
2926 return;
2927
4966b2a9 2928 n = (127 - d) / 18;
4d76a221 2929 for (i = 0; i < n; i++)
eed628f1 2930 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
4d76a221
AJ		 2931}
2932
cbba98f8 2933static void
eed628f1 2934vtb_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
cbba98f8
AJ		 2935{
2936 unsigned int i, n = min((int)ext[0x02], 6);
eed628f1 2937 const u8 *det_base = ext + 5;
cbba98f8
AJ		 2938
2939 if (ext[0x01] != 1)
2940 return; /* unknown version */
2941
2942 for (i = 0; i < n; i++)
eed628f1 2943 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
cbba98f8
AJ		 2944}
2945
45aa2336
JN		 2946static void drm_for_each_detailed_block(const struct drm_edid *drm_edid,
2947 detailed_cb *cb, void *closure)
d1ff6409 2948{
ab1747cc
JN		 2949 struct drm_edid_iter edid_iter;
2950 const u8 *ext;
d1ff6409 2951 int i;
d1ff6409 2952
45aa2336 2953 if (!drm_edid)
d1ff6409
AJ		 2954 return;
2955
2956 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
45aa2336 2957 cb(&drm_edid->edid->detailed_timings[i], closure);
d1ff6409 2958
bbded689 2959 drm_edid_iter_begin(drm_edid, &edid_iter);
ab1747cc 2960 drm_edid_iter_for_each(ext, &edid_iter) {
4d76a221
AJ		 2961 switch (*ext) {
2962 case CEA_EXT:
2963 cea_for_each_detailed_block(ext, cb, closure);
2964 break;
cbba98f8
AJ		 2965 case VTB_EXT:
2966 vtb_for_each_detailed_block(ext, cb, closure);
2967 break;
4d76a221
AJ		 2968 default:
2969 break;
2970 }
2971 }
ab1747cc 2972 drm_edid_iter_end(&edid_iter);
d1ff6409
AJ		 2973}
2974
2975static void
4194442d 2976is_rb(const struct detailed_timing *descriptor, void *data)
d1ff6409 2977{
90fd588f 2978 bool *res = data;
a7a131ac 2979
90fd588f 2980 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
a7a131ac
VS		 2981 return;
2982
90fd588f
JN		 2983 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
2984 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.cvt.flags) != 15);
2985
2986 if (descriptor->data.other_data.data.range.flags == DRM_EDID_CVT_SUPPORT_FLAG &&
2987 descriptor->data.other_data.data.range.formula.cvt.flags & 0x10)
2988 *res = true;
d1ff6409
AJ		 2989}
2990
2991/* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
2992static bool
874d98ee 2993drm_monitor_supports_rb(const struct drm_edid *drm_edid)
d1ff6409 2994{
874d98ee 2995 if (drm_edid->edid->revision >= 4) {
b196a498 2996 bool ret = false;
948de842 2997
45aa2336 2998 drm_for_each_detailed_block(drm_edid, is_rb, &ret);
d1ff6409
AJ		 2999 return ret;
3000 }
3001
874d98ee 3002 return ((drm_edid->edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
d1ff6409
AJ		 3003}
3004
7a374350 3005static void
4194442d 3006find_gtf2(const struct detailed_timing *descriptor, void *data)
7a374350 3007{
4194442d 3008 const struct detailed_timing **res = data;
a7a131ac 3009
c8a4beba 3010 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
a7a131ac
VS		 3011 return;
3012
c8a4beba
JN		 3013 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3014
3015 if (descriptor->data.other_data.data.range.flags == 0x02)
3016 *res = descriptor;
7a374350
AJ		 3017}
3018
3019/* Secondary GTF curve kicks in above some break frequency */
3020static int
67d87fac 3021drm_gtf2_hbreak(const struct drm_edid *drm_edid)
7a374350 3022{
4194442d 3023 const struct detailed_timing *descriptor = NULL;
c8a4beba 3024
45aa2336 3025 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
948de842 3026
c8a4beba
JN		 3027 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12);
3028
3029 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.hfreq_start_khz * 2 : 0;
7a374350
AJ		 3030}
3031
3032static int
67d87fac 3033drm_gtf2_2c(const struct drm_edid *drm_edid)
7a374350 3034{
4194442d 3035 const struct detailed_timing *descriptor = NULL;
c8a4beba 3036
45aa2336 3037 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
c8a4beba
JN		 3038
3039 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.c) != 13);
948de842 3040
c8a4beba 3041 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.c : 0;
7a374350
AJ		 3042}
3043
3044static int
67d87fac 3045drm_gtf2_m(const struct drm_edid *drm_edid)
7a374350 3046{
4194442d 3047 const struct detailed_timing *descriptor = NULL;
948de842 3048
45aa2336 3049 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
c8a4beba
JN		 3050
3051 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.m) != 14);
3052
3053 return descriptor ? le16_to_cpu(descriptor->data.other_data.data.range.formula.gtf2.m) : 0;
7a374350
AJ		 3054}
3055
3056static int
67d87fac 3057drm_gtf2_k(const struct drm_edid *drm_edid)
7a374350 3058{
4194442d 3059 const struct detailed_timing *descriptor = NULL;
c8a4beba 3060
45aa2336 3061 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
948de842 3062
c8a4beba
JN		 3063 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.k) != 16);
3064
3065 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.k : 0;
7a374350
AJ		 3066}
3067
3068static int
67d87fac 3069drm_gtf2_2j(const struct drm_edid *drm_edid)
7a374350 3070{
4194442d 3071 const struct detailed_timing *descriptor = NULL;
c8a4beba 3072
45aa2336 3073 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
c8a4beba
JN		 3074
3075 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.j) != 17);
948de842 3076
c8a4beba 3077 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.j : 0;
7a374350
AJ		 3078}
3079
17edb8e1 3080/* Get standard timing level (CVT/GTF/DMT). */
67d87fac 3081static int standard_timing_level(const struct drm_edid *drm_edid)
7a374350 3082{
67d87fac
JN		 3083 const struct edid *edid = drm_edid->edid;
3084
7a374350
AJ		 3085 if (edid->revision >= 2) {
3086 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
3087 return LEVEL_CVT;
67d87fac 3088 if (drm_gtf2_hbreak(drm_edid))
7a374350 3089 return LEVEL_GTF2;
bfef04ad
LS		 3090 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
3091 return LEVEL_GTF;
7a374350
AJ		 3092 }
3093 return LEVEL_DMT;
3094}
3095
23425cae
AJ		 3096/*
3097 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
3098 * monitors fill with ascii space (0x20) instead.
3099 */
3100static int
3101bad_std_timing(u8 a, u8 b)
3102{
3103 return (a == 0x00 && b == 0x00) ||
3104 (a == 0x01 && b == 0x01) ||
3105 (a == 0x20 && b == 0x20);
3106}
3107
58911c24
VS		 3108static int drm_mode_hsync(const struct drm_display_mode *mode)
3109{
3110 if (mode->htotal <= 0)
3111 return 0;
3112
3113 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal);
3114}
3115
17edb8e1 3116/*
f453ba04 3117 * Take the standard timing params (in this case width, aspect, and refresh)
5c61259e 3118 * and convert them into a real mode using CVT/GTF/DMT.
f453ba04 3119 */
67d87fac
JN		 3120static struct drm_display_mode *drm_mode_std(struct drm_connector *connector,
3121 const struct drm_edid *drm_edid,
3122 const struct std_timing *t)
f453ba04 3123{
7ca6adb3
AJ		 3124 struct drm_device *dev = connector->dev;
3125 struct drm_display_mode *m, *mode = NULL;
5c61259e
ZY		 3126 int hsize, vsize;
3127 int vrefresh_rate;
0454beab
MD		 3128 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
3129 >> EDID_TIMING_ASPECT_SHIFT;
5c61259e
ZY		 3130 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
3131 >> EDID_TIMING_VFREQ_SHIFT;
67d87fac 3132 int timing_level = standard_timing_level(drm_edid);
5c61259e 3133
23425cae
AJ		 3134 if (bad_std_timing(t->hsize, t->vfreq_aspect))
3135 return NULL;
3136
5c61259e
ZY		 3137 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
3138 hsize = t->hsize * 8 + 248;
3139 /* vrefresh_rate = vfreq + 60 */
3140 vrefresh_rate = vfreq + 60;
3141 /* the vdisplay is calculated based on the aspect ratio */
f066a17d 3142 if (aspect_ratio == 0) {
67d87fac 3143 if (drm_edid->edid->revision < 3)
f066a17d
AJ		 3144 vsize = hsize;
3145 else
3146 vsize = (hsize * 10) / 16;
3147 } else if (aspect_ratio == 1)
f453ba04 3148 vsize = (hsize * 3) / 4;
0454beab 3149 else if (aspect_ratio == 2)
f453ba04
DA		 3150 vsize = (hsize * 4) / 5;
3151 else
3152 vsize = (hsize * 9) / 16;
a0910c8e
AJ		 3153
3154 /* HDTV hack, part 1 */
3155 if (vrefresh_rate == 60 &&
3156 ((hsize == 1360 && vsize == 765) ||
3157 (hsize == 1368 && vsize == 769))) {
3158 hsize = 1366;
3159 vsize = 768;
3160 }
3161
7ca6adb3
AJ		 3162 /*
3163 * If this connector already has a mode for this size and refresh
3164 * rate (because it came from detailed or CVT info), use that
3165 * instead. This way we don't have to guess at interlace or
3166 * reduced blanking.
3167 */
522032da 3168 list_for_each_entry(m, &connector->probed_modes, head)
7ca6adb3
AJ		 3169 if (m->hdisplay == hsize && m->vdisplay == vsize &&
3170 drm_mode_vrefresh(m) == vrefresh_rate)
3171 return NULL;
3172
a0910c8e
AJ		 3173 /* HDTV hack, part 2 */
3174 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
3175 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
d50ba256 3176 false);
a5ef6567
JM		 3177 if (!mode)
3178 return NULL;
559ee21d 3179 mode->hdisplay = 1366;
a4967de6
AJ		 3180 mode->hsync_start = mode->hsync_start - 1;
3181 mode->hsync_end = mode->hsync_end - 1;
559ee21d
ZY		 3182 return mode;
3183 }
a0910c8e 3184
559ee21d 3185 /* check whether it can be found in default mode table */
874d98ee 3186 if (drm_monitor_supports_rb(drm_edid)) {
f6e252ba
AJ		 3187 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
3188 true);
3189 if (mode)
3190 return mode;
3191 }
3192 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
559ee21d
ZY		 3193 if (mode)
3194 return mode;
3195
f6e252ba 3196 /* okay, generate it */
5c61259e
ZY		 3197 switch (timing_level) {
3198 case LEVEL_DMT:
5c61259e
ZY		 3199 break;
3200 case LEVEL_GTF:
3201 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
3202 break;
7a374350
AJ		 3203 case LEVEL_GTF2:
3204 /*
3205 * This is potentially wrong if there's ever a monitor with
3206 * more than one ranges section, each claiming a different
3207 * secondary GTF curve. Please don't do that.
3208 */
3209 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
fc48f169
TI		 3210 if (!mode)
3211 return NULL;
67d87fac 3212 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(drm_edid)) {
aefd330e 3213 drm_mode_destroy(dev, mode);
7a374350
AJ		 3214 mode = drm_gtf_mode_complex(dev, hsize, vsize,
3215 vrefresh_rate, 0, 0,
67d87fac
JN		 3216 drm_gtf2_m(drm_edid),
3217 drm_gtf2_2c(drm_edid),
3218 drm_gtf2_k(drm_edid),
3219 drm_gtf2_2j(drm_edid));
7a374350
AJ		 3220 }
3221 break;
5c61259e 3222 case LEVEL_CVT:
d50ba256
DA		 3223 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
3224 false);
5c61259e
ZY		 3225 break;
3226 }
f453ba04
DA		 3227 return mode;
3228}
3229
b58db2c6
AJ		 3230/*
3231 * EDID is delightfully ambiguous about how interlaced modes are to be
3232 * encoded. Our internal representation is of frame height, but some
3233 * HDTV detailed timings are encoded as field height.
3234 *
3235 * The format list here is from CEA, in frame size. Technically we
3236 * should be checking refresh rate too. Whatever.
3237 */
3238static void
3239drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
fcfb2ea1 3240 const struct detailed_pixel_timing *pt)
b58db2c6
AJ		 3241{
3242 int i;
3243 static const struct {
3244 int w, h;
3245 } cea_interlaced[] = {
3246 { 1920, 1080 },
3247 { 720, 480 },
3248 { 1440, 480 },
3249 { 2880, 480 },
3250 { 720, 576 },
3251 { 1440, 576 },
3252 { 2880, 576 },
3253 };
b58db2c6
AJ		 3254
3255 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
3256 return;
3257
3c581411 3258 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
b58db2c6
AJ		 3259 if ((mode->hdisplay == cea_interlaced[i].w) &&
3260 (mode->vdisplay == cea_interlaced[i].h / 2)) {
3261 mode->vdisplay *= 2;
3262 mode->vsync_start *= 2;
3263 mode->vsync_end *= 2;
3264 mode->vtotal *= 2;
3265 mode->vtotal |= 1;
3266 }
3267 }
3268
3269 mode->flags |= DRM_MODE_FLAG_INTERLACE;
3270}
3271
17edb8e1
JN		 3272/*
3273 * Create a new mode from an EDID detailed timing section. An EDID detailed
3274 * timing block contains enough info for us to create and return a new struct
3275 * drm_display_mode.
f453ba04
DA		 3276 */
3277static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
f0d080ff 3278 const struct drm_edid *drm_edid,
fcfb2ea1 3279 const struct detailed_timing *timing,
f453ba04
DA		 3280 u32 quirks)
3281{
3282 struct drm_display_mode *mode;
fcfb2ea1 3283 const struct detailed_pixel_timing *pt = &timing->data.pixel_data;
0454beab
MD		 3284 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
3285 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
3286 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
3287 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
e14cbee4
MD		 3288 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
3289 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
16dad1d7 3290 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
e14cbee4 3291 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
f453ba04 3292
fc438966 3293 /* ignore tiny modes */
0454beab 3294 if (hactive < 64 || vactive < 64)
fc438966
AJ		 3295 return NULL;
3296
0454beab 3297 if (pt->misc & DRM_EDID_PT_STEREO) {
c7d015f3 3298 DRM_DEBUG_KMS("stereo mode not supported\n");
f453ba04
DA		 3299 return NULL;
3300 }
0454beab 3301 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
c7d015f3 3302 DRM_DEBUG_KMS("composite sync not supported\n");
f453ba04
DA		 3303 }
3304
fcb45611
ZY		 3305 /* it is incorrect if hsync/vsync width is zero */
3306 if (!hsync_pulse_width || !vsync_pulse_width) {
3307 DRM_DEBUG_KMS("Incorrect Detailed timing. "
3308 "Wrong Hsync/Vsync pulse width\n");
3309 return NULL;
3310 }
bc42aabc
AJ		 3311
3312 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
3313 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
3314 if (!mode)
3315 return NULL;
3316
3317 goto set_size;
3318 }
3319
f453ba04
DA		 3320 mode = drm_mode_create(dev);
3321 if (!mode)
3322 return NULL;
3323
f453ba04 3324 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
faacff8e
JN		 3325 mode->clock = 1088 * 10;
3326 else
3327 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
0454beab
MD		 3328
3329 mode->hdisplay = hactive;
3330 mode->hsync_start = mode->hdisplay + hsync_offset;
3331 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
3332 mode->htotal = mode->hdisplay + hblank;
3333
3334 mode->vdisplay = vactive;
3335 mode->vsync_start = mode->vdisplay + vsync_offset;
3336 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
3337 mode->vtotal = mode->vdisplay + vblank;
f453ba04 3338
7064fef5
JB		 3339 /* Some EDIDs have bogus h/vtotal values */
3340 if (mode->hsync_end > mode->htotal)
3341 mode->htotal = mode->hsync_end + 1;
3342 if (mode->vsync_end > mode->vtotal)
3343 mode->vtotal = mode->vsync_end + 1;
3344
b58db2c6 3345 drm_mode_do_interlace_quirk(mode, pt);
f453ba04
DA		 3346
3347 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
faacff8e
JN		 3348 mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC;
3349 } else {
3350 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
3351 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
3352 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
3353 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
f453ba04
DA		 3354 }
3355
bc42aabc 3356set_size:
e14cbee4
MD		 3357 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
3358 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
f453ba04
DA		 3359
3360 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
3361 mode->width_mm *= 10;
3362 mode->height_mm *= 10;
3363 }
3364
3365 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
f0d080ff
JN		 3366 mode->width_mm = drm_edid->edid->width_cm * 10;
3367 mode->height_mm = drm_edid->edid->height_cm * 10;
f453ba04
DA		 3368 }
3369
bc42aabc
AJ		 3370 mode->type = DRM_MODE_TYPE_DRIVER;
3371 drm_mode_set_name(mode);
3372
f453ba04
DA		 3373 return mode;
3374}
3375
b17e52ef 3376static bool
b1f559ec 3377mode_in_hsync_range(const struct drm_display_mode *mode,
c14e7241 3378 const struct edid *edid, const u8 *t)
b17e52ef
AJ		 3379{
3380 int hsync, hmin, hmax;
3381
3382 hmin = t[7];
3383 if (edid->revision >= 4)
3384 hmin += ((t[4] & 0x04) ? 255 : 0);
3385 hmax = t[8];
3386 if (edid->revision >= 4)
3387 hmax += ((t[4] & 0x08) ? 255 : 0);
07a5e632 3388 hsync = drm_mode_hsync(mode);
07a5e632 3389
b17e52ef
AJ		 3390 return (hsync <= hmax && hsync >= hmin);
3391}
3392
3393static bool
b1f559ec 3394mode_in_vsync_range(const struct drm_display_mode *mode,
c14e7241 3395 const struct edid *edid, const u8 *t)
b17e52ef
AJ		 3396{
3397 int vsync, vmin, vmax;
3398
3399 vmin = t[5];
3400 if (edid->revision >= 4)
3401 vmin += ((t[4] & 0x01) ? 255 : 0);
3402 vmax = t[6];
3403 if (edid->revision >= 4)
3404 vmax += ((t[4] & 0x02) ? 255 : 0);
3405 vsync = drm_mode_vrefresh(mode);
3406
3407 return (vsync <= vmax && vsync >= vmin);
3408}
3409
3410static u32
c14e7241 3411range_pixel_clock(const struct edid *edid, const u8 *t)
b17e52ef
AJ		 3412{
3413 /* unspecified */
3414 if (t[9] == 0 || t[9] == 255)
3415 return 0;
3416
3417 /* 1.4 with CVT support gives us real precision, yay */
3418 if (edid->revision >= 4 && t[10] == 0x04)
3419 return (t[9] * 10000) - ((t[12] >> 2) * 250);
3420
3421 /* 1.3 is pathetic, so fuzz up a bit */
3422 return t[9] * 10000 + 5001;
3423}
3424
874d98ee
JN		 3425static bool mode_in_range(const struct drm_display_mode *mode,
3426 const struct drm_edid *drm_edid,
3427 const struct detailed_timing *timing)
b17e52ef 3428{
874d98ee 3429 const struct edid *edid = drm_edid->edid;
b17e52ef 3430 u32 max_clock;
fcfb2ea1 3431 const u8 *t = (const u8 *)timing;
b17e52ef
AJ		 3432
3433 if (!mode_in_hsync_range(mode, edid, t))
07a5e632
AJ		 3434 return false;
3435
b17e52ef 3436 if (!mode_in_vsync_range(mode, edid, t))
07a5e632
AJ		 3437 return false;
3438
b17e52ef 3439 if ((max_clock = range_pixel_clock(edid, t)))
07a5e632
AJ		 3440 if (mode->clock > max_clock)
3441 return false;
b17e52ef
AJ		 3442
3443 /* 1.4 max horizontal check */
3444 if (edid->revision >= 4 && t[10] == 0x04)
3445 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
3446 return false;
3447
874d98ee 3448 if (mode_is_rb(mode) && !drm_monitor_supports_rb(drm_edid))
b17e52ef 3449 return false;
07a5e632
AJ		 3450
3451 return true;
3452}
3453
7b668ebe
TI		 3454static bool valid_inferred_mode(const struct drm_connector *connector,
3455 const struct drm_display_mode *mode)
3456{
85f8fcd6 3457 const struct drm_display_mode *m;
7b668ebe
TI		 3458 bool ok = false;
3459
3460 list_for_each_entry(m, &connector->probed_modes, head) {
3461 if (mode->hdisplay == m->hdisplay &&
3462 mode->vdisplay == m->vdisplay &&
3463 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
3464 return false; /* duplicated */
3465 if (mode->hdisplay <= m->hdisplay &&
3466 mode->vdisplay <= m->vdisplay)
3467 ok = true;
3468 }
3469 return ok;
3470}
3471
084c7a7c
JN		 3472static int drm_dmt_modes_for_range(struct drm_connector *connector,
3473 const struct drm_edid *drm_edid,
3474 const struct detailed_timing *timing)
07a5e632
AJ		 3475{
3476 int i, modes = 0;
3477 struct drm_display_mode *newmode;
3478 struct drm_device *dev = connector->dev;
3479
a6b21831 3480 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
874d98ee 3481 if (mode_in_range(drm_dmt_modes + i, drm_edid, timing) &&
7b668ebe 3482 valid_inferred_mode(connector, drm_dmt_modes + i)) {
07a5e632
AJ		 3483 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
3484 if (newmode) {
3485 drm_mode_probed_add(connector, newmode);
3486 modes++;
3487 }
3488 }
3489 }
3490
3491 return modes;
3492}
3493
c09dedb7
TI		 3494/* fix up 1366x768 mode from 1368x768;
3495 * GFT/CVT can't express 1366 width which isn't dividable by 8
3496 */
969218fe 3497void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
c09dedb7
TI		 3498{
3499 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
3500 mode->hdisplay = 1366;
3501 mode->hsync_start--;
3502 mode->hsync_end--;
3503 drm_mode_set_name(mode);
3504 }
3505}
3506
a77f7c89
JN		 3507static int drm_gtf_modes_for_range(struct drm_connector *connector,
3508 const struct drm_edid *drm_edid,
3509 const struct detailed_timing *timing)
b309bd37
AJ		 3510{
3511 int i, modes = 0;
3512 struct drm_display_mode *newmode;
3513 struct drm_device *dev = connector->dev;
3514
a6b21831 3515 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
b309bd37 3516 const struct minimode *m = &extra_modes[i];
948de842 3517
b309bd37 3518 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
fc48f169
TI		 3519 if (!newmode)
3520 return modes;
b309bd37 3521
969218fe 3522 drm_mode_fixup_1366x768(newmode);
874d98ee 3523 if (!mode_in_range(newmode, drm_edid, timing) ||
7b668ebe 3524 !valid_inferred_mode(connector, newmode)) {
b309bd37
AJ		 3525 drm_mode_destroy(dev, newmode);
3526 continue;
3527 }
3528
3529 drm_mode_probed_add(connector, newmode);
3530 modes++;
3531 }
3532
3533 return modes;
3534}
3535
7428bfbd
JN		 3536static int drm_cvt_modes_for_range(struct drm_connector *connector,
3537 const struct drm_edid *drm_edid,
3538 const struct detailed_timing *timing)
b309bd37
AJ		 3539{
3540 int i, modes = 0;
3541 struct drm_display_mode *newmode;
3542 struct drm_device *dev = connector->dev;
874d98ee 3543 bool rb = drm_monitor_supports_rb(drm_edid);
b309bd37 3544
a6b21831 3545 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
b309bd37 3546 const struct minimode *m = &extra_modes[i];
948de842 3547
b309bd37 3548 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
fc48f169
TI		 3549 if (!newmode)
3550 return modes;
b309bd37 3551
969218fe 3552 drm_mode_fixup_1366x768(newmode);
874d98ee 3553 if (!mode_in_range(newmode, drm_edid, timing) ||
7b668ebe 3554 !valid_inferred_mode(connector, newmode)) {
b309bd37
AJ		 3555 drm_mode_destroy(dev, newmode);
3556 continue;
3557 }
3558
3559 drm_mode_probed_add(connector, newmode);
3560 modes++;
3561 }
3562
3563 return modes;
3564}
3565
13931579 3566static void
4194442d 3567do_inferred_modes(const struct detailed_timing *timing, void *c)
9340d8cf 3568{
13931579 3569 struct detailed_mode_closure *closure = c;
fcfb2ea1
JN		 3570 const struct detailed_non_pixel *data = &timing->data.other_data;
3571 const struct detailed_data_monitor_range *range = &data->data.range;
9340d8cf 3572
e379814b 3573 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
cb21aafe
AJ		 3574 return;
3575
3576 closure->modes += drm_dmt_modes_for_range(closure->connector,
084c7a7c 3577 closure->drm_edid,
cb21aafe 3578 timing);
4d23f484 3579
d0edd3c1 3580 if (!version_greater(closure->drm_edid, 1, 1))
b309bd37
AJ		 3581 return; /* GTF not defined yet */
3582
3583 switch (range->flags) {
3584 case 0x02: /* secondary gtf, XXX could do more */
3585 case 0x00: /* default gtf */
3586 closure->modes += drm_gtf_modes_for_range(closure->connector,
a77f7c89 3587 closure->drm_edid,
b309bd37
AJ		 3588 timing);
3589 break;
3590 case 0x04: /* cvt, only in 1.4+ */
d0edd3c1 3591 if (!version_greater(closure->drm_edid, 1, 3))
b309bd37
AJ		 3592 break;
3593
3594 closure->modes += drm_cvt_modes_for_range(closure->connector,
7428bfbd 3595 closure->drm_edid,
b309bd37
AJ		 3596 timing);
3597 break;
3598 case 0x01: /* just the ranges, no formula */
3599 default:
3600 break;
3601 }
13931579 3602}
69da3015 3603
40f71f5b
JN		 3604static int add_inferred_modes(struct drm_connector *connector,
3605 const struct drm_edid *drm_edid)
13931579
AJ		 3606{
3607 struct detailed_mode_closure closure = {
d456ea2e 3608 .connector = connector,
dd0f4470 3609 .drm_edid = drm_edid,
13931579 3610 };
9340d8cf 3611
d0edd3c1 3612 if (version_greater(drm_edid, 1, 0))
45aa2336 3613 drm_for_each_detailed_block(drm_edid, do_inferred_modes, &closure);
9340d8cf 3614
13931579 3615 return closure.modes;
9340d8cf
AJ		 3616}
3617
2255be14 3618static int
fcfb2ea1 3619drm_est3_modes(struct drm_connector *connector, const struct detailed_timing *timing)
2255be14
AJ		 3620{
3621 int i, j, m, modes = 0;
3622 struct drm_display_mode *mode;
fcfb2ea1 3623 const u8 *est = ((const u8 *)timing) + 6;
2255be14
AJ		 3624
3625 for (i = 0; i < 6; i++) {
891a7469 3626 for (j = 7; j >= 0; j--) {
2255be14 3627 m = (i * 8) + (7 - j);
3c581411 3628 if (m >= ARRAY_SIZE(est3_modes))
2255be14
AJ		 3629 break;
3630 if (est[i] & (1 << j)) {
1d42bbc8
DA		 3631 mode = drm_mode_find_dmt(connector->dev,
3632 est3_modes[m].w,
3633 est3_modes[m].h,
f6e252ba
AJ		 3634 est3_modes[m].r,
3635 est3_modes[m].rb);
2255be14
AJ		 3636 if (mode) {
3637 drm_mode_probed_add(connector, mode);
3638 modes++;
3639 }
3640 }
3641 }
3642 }
3643
3644 return modes;
3645}
3646
13931579 3647static void
4194442d 3648do_established_modes(const struct detailed_timing *timing, void *c)
9cf00977 3649{
13931579 3650 struct detailed_mode_closure *closure = c;
9cf00977 3651
e379814b 3652 if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS))
a7a131ac
VS		 3653 return;
3654
3655 closure->modes += drm_est3_modes(closure->connector, timing);
13931579 3656}
9cf00977 3657
17edb8e1
JN		 3658/*
3659 * Get established modes from EDID and add them. Each EDID block contains a
3660 * bitmap of the supported "established modes" list (defined above). Tease them
3661 * out and add them to the global modes list.
13931579 3662 */
40f71f5b
JN		 3663static int add_established_modes(struct drm_connector *connector,
3664 const struct drm_edid *drm_edid)
13931579
AJ		 3665{
3666 struct drm_device *dev = connector->dev;
40f71f5b 3667 const struct edid *edid = drm_edid->edid;
13931579
AJ		 3668 unsigned long est_bits = edid->established_timings.t1 |
3669 (edid->established_timings.t2 << 8) |
3670 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
3671 int i, modes = 0;
3672 struct detailed_mode_closure closure = {
d456ea2e 3673 .connector = connector,
dd0f4470 3674 .drm_edid = drm_edid,
13931579 3675 };
9cf00977 3676
13931579
AJ		 3677 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
3678 if (est_bits & (1<<i)) {
3679 struct drm_display_mode *newmode;
948de842 3680
13931579
AJ		 3681 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
3682 if (newmode) {
3683 drm_mode_probed_add(connector, newmode);
3684 modes++;
3685 }
3686 }
9cf00977
AJ		 3687 }
3688
d0edd3c1 3689 if (version_greater(drm_edid, 1, 0))
45aa2336 3690 drm_for_each_detailed_block(drm_edid, do_established_modes,
eed628f1 3691 &closure);
13931579
AJ		 3692
3693 return modes + closure.modes;
3694}
3695
3696static void
4194442d 3697do_standard_modes(const struct detailed_timing *timing, void *c)
13931579
AJ		 3698{
3699 struct detailed_mode_closure *closure = c;
fcfb2ea1 3700 const struct detailed_non_pixel *data = &timing->data.other_data;
13931579 3701 struct drm_connector *connector = closure->connector;
a7a131ac 3702 int i;
13931579 3703
e379814b 3704 if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES))
a7a131ac 3705 return;
9cf00977 3706
a7a131ac 3707 for (i = 0; i < 6; i++) {
fcfb2ea1 3708 const struct std_timing *std = &data->data.timings[i];
a7a131ac
VS		 3709 struct drm_display_mode *newmode;
3710
67d87fac 3711 newmode = drm_mode_std(connector, closure->drm_edid, std);
a7a131ac
VS		 3712 if (newmode) {
3713 drm_mode_probed_add(connector, newmode);
3714 closure->modes++;
9cf00977 3715 }
9cf00977 3716 }
9cf00977
AJ		 3717}
3718
17edb8e1
JN		 3719/*
3720 * Get standard modes from EDID and add them. Standard modes can be calculated
3721 * using the appropriate standard (DMT, GTF, or CVT). Grab them from EDID and
3722 * add them to the list.
f453ba04 3723 */
40f71f5b
JN		 3724static int add_standard_modes(struct drm_connector *connector,
3725 const struct drm_edid *drm_edid)
f453ba04 3726{
9cf00977 3727 int i, modes = 0;
13931579 3728 struct detailed_mode_closure closure = {
d456ea2e 3729 .connector = connector,
dd0f4470 3730 .drm_edid = drm_edid,
13931579
AJ		 3731 };
3732
3733 for (i = 0; i < EDID_STD_TIMINGS; i++) {
3734 struct drm_display_mode *newmode;
3735
67d87fac 3736 newmode = drm_mode_std(connector, drm_edid,
40f71f5b 3737 &drm_edid->edid->standard_timings[i]);
13931579
AJ		 3738 if (newmode) {
3739 drm_mode_probed_add(connector, newmode);
3740 modes++;
3741 }
3742 }
3743
d0edd3c1 3744 if (version_greater(drm_edid, 1, 0))
45aa2336 3745 drm_for_each_detailed_block(drm_edid, do_standard_modes,
13931579
AJ		 3746 &closure);
3747
3748 /* XXX should also look for standard codes in VTB blocks */
3749
3750 return modes + closure.modes;
3751}
f453ba04 3752
13931579 3753static int drm_cvt_modes(struct drm_connector *connector,
fcfb2ea1 3754 const struct detailed_timing *timing)
13931579
AJ		 3755{
3756 int i, j, modes = 0;
3757 struct drm_display_mode *newmode;
3758 struct drm_device *dev = connector->dev;
fcfb2ea1 3759 const struct cvt_timing *cvt;
13931579
AJ		 3760 const int rates[] = { 60, 85, 75, 60, 50 };
3761 const u8 empty[3] = { 0, 0, 0 };
a327f6b8 3762
13931579 3763 for (i = 0; i < 4; i++) {
3f649ab7 3764 int width, height;
948de842 3765
13931579 3766 cvt = &(timing->data.other_data.data.cvt[i]);
f453ba04 3767
13931579 3768 if (!memcmp(cvt->code, empty, 3))
9cf00977 3769 continue;
f453ba04 3770
13931579
AJ		 3771 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
3772 switch (cvt->code[1] & 0x0c) {
d652d5f1
LT		 3773 /* default - because compiler doesn't see that we've enumerated all cases */
3774 default:
13931579
AJ		 3775 case 0x00:
3776 width = height * 4 / 3;
3777 break;
3778 case 0x04:
3779 width = height * 16 / 9;
3780 break;
3781 case 0x08:
3782 width = height * 16 / 10;
3783 break;
3784 case 0x0c:
3785 width = height * 15 / 9;
3786 break;
3787 }
3788
3789 for (j = 1; j < 5; j++) {
3790 if (cvt->code[2] & (1 << j)) {
3791 newmode = drm_cvt_mode(dev, width, height,
3792 rates[j], j == 0,
3793 false, false);
3794 if (newmode) {
3795 drm_mode_probed_add(connector, newmode);
3796 modes++;
3797 }
3798 }
3799 }
f453ba04
DA		 3800 }
3801
3802 return modes;
3803}
9cf00977 3804
13931579 3805static void
4194442d 3806do_cvt_mode(const struct detailed_timing *timing, void *c)
882f0219 3807{
13931579 3808 struct detailed_mode_closure *closure = c;
882f0219 3809
e379814b 3810 if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE))
a7a131ac
VS		 3811 return;
3812
3813 closure->modes += drm_cvt_modes(closure->connector, timing);
13931579 3814}
882f0219 3815
13931579 3816static int
40f71f5b 3817add_cvt_modes(struct drm_connector *connector, const struct drm_edid *drm_edid)
4d23f484 3818{
13931579 3819 struct detailed_mode_closure closure = {
d456ea2e 3820 .connector = connector,
dd0f4470 3821 .drm_edid = drm_edid,
13931579 3822 };
882f0219 3823
d0edd3c1 3824 if (version_greater(drm_edid, 1, 2))
45aa2336 3825 drm_for_each_detailed_block(drm_edid, do_cvt_mode, &closure);
882f0219 3826
13931579 3827 /* XXX should also look for CVT codes in VTB blocks */
882f0219 3828
13931579
AJ		 3829 return closure.modes;
3830}
3831
fa3a7340
VS		 3832static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
3833
13931579 3834static void
4194442d 3835do_detailed_mode(const struct detailed_timing *timing, void *c)
13931579
AJ		 3836{
3837 struct detailed_mode_closure *closure = c;
3838 struct drm_display_mode *newmode;
3839
a9b1f15f 3840 if (!is_detailed_timing_descriptor(timing))
f447dd1f
VS		 3841 return;
3842
3843 newmode = drm_mode_detailed(closure->connector->dev,
f0d080ff 3844 closure->drm_edid, timing,
f447dd1f
VS		 3845 closure->quirks);
3846 if (!newmode)
3847 return;
13931579 3848
f447dd1f
VS		 3849 if (closure->preferred)
3850 newmode->type |= DRM_MODE_TYPE_PREFERRED;
13931579 3851
f447dd1f
VS		 3852 /*
3853 * Detailed modes are limited to 10kHz pixel clock resolution,
3854 * so fix up anything that looks like CEA/HDMI mode, but the clock
3855 * is just slightly off.
3856 */
3857 fixup_detailed_cea_mode_clock(newmode);
fa3a7340 3858
f447dd1f
VS		 3859 drm_mode_probed_add(closure->connector, newmode);
3860 closure->modes++;
3861 closure->preferred = false;
13931579 3862}
882f0219 3863
13931579
AJ		 3864/*
3865 * add_detailed_modes - Add modes from detailed timings
3866 * @connector: attached connector
40f71f5b 3867 * @drm_edid: EDID block to scan
13931579
AJ		 3868 * @quirks: quirks to apply
3869 */
40f71f5b
JN		 3870static int add_detailed_modes(struct drm_connector *connector,
3871 const struct drm_edid *drm_edid, u32 quirks)
13931579
AJ		 3872{
3873 struct detailed_mode_closure closure = {
d456ea2e 3874 .connector = connector,
dd0f4470 3875 .drm_edid = drm_edid,
c2925bde 3876 .preferred = true,
d456ea2e 3877 .quirks = quirks,
13931579
AJ		 3878 };
3879
d0edd3c1 3880 if (closure.preferred && !version_greater(drm_edid, 1, 3))
13931579 3881 closure.preferred =
40f71f5b 3882 (drm_edid->edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
13931579 3883
45aa2336 3884 drm_for_each_detailed_block(drm_edid, do_detailed_mode, &closure);
13931579
AJ		 3885
3886 return closure.modes;
882f0219 3887}
f453ba04 3888
9d72b7e2
JN		 3889/* CTA-861-H Table 60 - CTA Tag Codes */
3890#define CTA_DB_AUDIO 1
3891#define CTA_DB_VIDEO 2
3892#define CTA_DB_VENDOR 3
3893#define CTA_DB_SPEAKER 4
3894#define CTA_DB_EXTENDED_TAG 7
3895
3896/* CTA-861-H Table 62 - CTA Extended Tag Codes */
3897#define CTA_EXT_DB_VIDEO_CAP 0
3898#define CTA_EXT_DB_VENDOR 1
3899#define CTA_EXT_DB_HDR_STATIC_METADATA 6
3900#define CTA_EXT_DB_420_VIDEO_DATA 14
3901#define CTA_EXT_DB_420_VIDEO_CAP_MAP 15
18e3c1d5 3902#define CTA_EXT_DB_HF_EEODB 0x78
9d72b7e2
JN		 3903#define CTA_EXT_DB_HF_SCDB 0x79
3904
8fe9790d 3905#define EDID_BASIC_AUDIO (1 << 6)
a988bc72
LPC		 3906#define EDID_CEA_YCRCB444 (1 << 5)
3907#define EDID_CEA_YCRCB422 (1 << 4)
b1edd6a6 3908#define EDID_CEA_VCDB_QS (1 << 6)
8fe9790d 3909
d4e4a31d 3910/*
8fe9790d 3911 * Search EDID for CEA extension block.
d9ba1b4c
JN		 3912 *
3913 * FIXME: Prefer not returning pointers to raw EDID data.
f23c20c8 3914 */
d9ba1b4c 3915const u8 *drm_find_edid_extension(const struct drm_edid *drm_edid,
4cc4f09e 3916 int ext_id, int *ext_index)
f23c20c8 3917{
43d16d84 3918 const u8 *edid_ext = NULL;
8fe9790d 3919 int i;
f23c20c8
ML		 3920
3921 /* No EDID or EDID extensions */
d9307f27 3922 if (!drm_edid || !drm_edid_extension_block_count(drm_edid))
8fe9790d 3923 return NULL;
f23c20c8 3924
f23c20c8 3925 /* Find CEA extension */
d9307f27
JN		 3926 for (i = *ext_index; i < drm_edid_extension_block_count(drm_edid); i++) {
3927 edid_ext = drm_edid_extension_block_data(drm_edid, i);
4ba0f53c 3928 if (edid_block_tag(edid_ext) == ext_id)
f23c20c8
ML		 3929 break;
3930 }
3931
d9307f27 3932 if (i >= drm_edid_extension_block_count(drm_edid))
8fe9790d
ZW		 3933 return NULL;
3934
8873cfa3
VS		 3935 *ext_index = i + 1;
3936
8fe9790d
ZW		 3937 return edid_ext;
3938}
3939
6ff1c19f 3940/* Return true if the EDID has a CTA extension or a DisplayID CTA data block */
40f71f5b 3941static bool drm_edid_has_cta_extension(const struct drm_edid *drm_edid)
e28ad544 3942{
43d16d84 3943 const struct displayid_block *block;
1ba63caf 3944 struct displayid_iter iter;
1ba63caf 3945 int ext_index = 0;
6ff1c19f 3946 bool found = false;
e28ad544
AR		 3947
3948 /* Look for a top level CEA extension block */
d9ba1b4c 3949 if (drm_find_edid_extension(drm_edid, CEA_EXT, &ext_index))
6ff1c19f 3950 return true;
e28ad544
AR		 3951
3952 /* CEA blocks can also be found embedded in a DisplayID block */
d9ba1b4c 3953 displayid_iter_edid_begin(drm_edid, &iter);
1ba63caf
JN		 3954 displayid_iter_for_each(block, &iter) {
3955 if (block->tag == DATA_BLOCK_CTA) {
6ff1c19f 3956 found = true;
1ba63caf 3957 break;
e28ad544
AR		 3958 }
3959 }
1ba63caf 3960 displayid_iter_end(&iter);
e28ad544 3961
6ff1c19f 3962 return found;
e28ad544
AR		 3963}
3964
e1cf35b9 3965static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic)
7befe621 3966{
9212f8ee
VS		 3967 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127);
3968 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219);
3969
8c1b2bd9
VS		 3970 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1))
3971 return &edid_cea_modes_1[vic - 1];
f7655d42
VS		 3972 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193))
3973 return &edid_cea_modes_193[vic - 193];
7befe621
VS		 3974 return NULL;
3975}
3976
3977static u8 cea_num_vics(void)
3978{
f7655d42 3979 return 193 + ARRAY_SIZE(edid_cea_modes_193);
7befe621
VS		 3980}
3981
3982static u8 cea_next_vic(u8 vic)
3983{
8c1b2bd9 3984 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1))
f7655d42
VS		 3985 vic = 193;
3986 return vic;
7befe621
VS		 3987}
3988
e6e79209
VS		 3989/*
3990 * Calculate the alternate clock for the CEA mode
3991 * (60Hz vs. 59.94Hz etc.)
3992 */
3993static unsigned int
3994cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
3995{
3996 unsigned int clock = cea_mode->clock;
3997
0425662f 3998 if (drm_mode_vrefresh(cea_mode) % 6 != 0)
e6e79209
VS		 3999 return clock;
4000
4001 /*
4002 * edid_cea_modes contains the 59.94Hz
4003 * variant for 240 and 480 line modes,
4004 * and the 60Hz variant otherwise.
4005 */
4006 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
9afd808c 4007 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
e6e79209 4008 else
9afd808c 4009 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
e6e79209
VS		 4010
4011 return clock;
4012}
4013
c45a4e46
VS		 4014static bool
4015cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
4016{
4017 /*
4018 * For certain VICs the spec allows the vertical
4019 * front porch to vary by one or two lines.
4020 *
4021 * cea_modes[] stores the variant with the shortest
4022 * vertical front porch. We can adjust the mode to
4023 * get the other variants by simply increasing the
4024 * vertical front porch length.
4025 */
7befe621
VS		 4026 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 ||
4027 cea_mode_for_vic(9)->vtotal != 262 ||
4028 cea_mode_for_vic(12)->vtotal != 262 ||
4029 cea_mode_for_vic(13)->vtotal != 262 ||
4030 cea_mode_for_vic(23)->vtotal != 312 ||
4031 cea_mode_for_vic(24)->vtotal != 312 ||
4032 cea_mode_for_vic(27)->vtotal != 312 ||
4033 cea_mode_for_vic(28)->vtotal != 312);
c45a4e46
VS		 4034
4035 if (((vic == 8 || vic == 9 ||
4036 vic == 12 || vic == 13) && mode->vtotal < 263) ||
4037 ((vic == 23 || vic == 24 ||
4038 vic == 27 || vic == 28) && mode->vtotal < 314)) {
4039 mode->vsync_start++;
4040 mode->vsync_end++;
4041 mode->vtotal++;
4042
4043 return true;
4044 }
4045
4046 return false;
4047}
4048
4c6bcf44
VS		 4049static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
4050 unsigned int clock_tolerance)
4051{
357768cc 4052 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 4053 u8 vic;
4c6bcf44
VS		 4054
4055 if (!to_match->clock)
4056 return 0;
4057
357768cc
VS		 4058 if (to_match->picture_aspect_ratio)
4059 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4060
7befe621 4061 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
563c4a75 4062 struct drm_display_mode cea_mode;
4c6bcf44
VS		 4063 unsigned int clock1, clock2;
4064
563c4a75
VS		 4065 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
4066
4c6bcf44 4067 /* Check both 60Hz and 59.94Hz */
c45a4e46
VS		 4068 clock1 = cea_mode.clock;
4069 clock2 = cea_mode_alternate_clock(&cea_mode);
4c6bcf44
VS		 4070
4071 if (abs(to_match->clock - clock1) > clock_tolerance &&
4072 abs(to_match->clock - clock2) > clock_tolerance)
4073 continue;
4074
c45a4e46 4075 do {
357768cc 4076 if (drm_mode_match(to_match, &cea_mode, match_flags))
c45a4e46
VS		 4077 return vic;
4078 } while (cea_mode_alternate_timings(vic, &cea_mode));
4c6bcf44
VS		 4079 }
4080
4081 return 0;
4082}
4083
18316c8c
TR		 4084/**
4085 * drm_match_cea_mode - look for a CEA mode matching given mode
4086 * @to_match: display mode
4087 *
db6cf833 4088 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
18316c8c 4089 * mode.
a4799037 4090 */
18316c8c 4091u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
a4799037 4092{
357768cc 4093 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 4094 u8 vic;
a4799037 4095
a90b590e
VS		 4096 if (!to_match->clock)
4097 return 0;
4098
357768cc
VS		 4099 if (to_match->picture_aspect_ratio)
4100 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4101
7befe621 4102 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
563c4a75 4103 struct drm_display_mode cea_mode;
a90b590e
VS		 4104 unsigned int clock1, clock2;
4105
563c4a75
VS		 4106 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
4107
a90b590e 4108 /* Check both 60Hz and 59.94Hz */
c45a4e46
VS		 4109 clock1 = cea_mode.clock;
4110 clock2 = cea_mode_alternate_clock(&cea_mode);
a4799037 4111
c45a4e46
VS		 4112 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
4113 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
4114 continue;
4115
4116 do {
357768cc 4117 if (drm_mode_match(to_match, &cea_mode, match_flags))
c45a4e46
VS		 4118 return vic;
4119 } while (cea_mode_alternate_timings(vic, &cea_mode));
a4799037 4120 }
c45a4e46 4121
a4799037
SM		 4122 return 0;
4123}
4124EXPORT_SYMBOL(drm_match_cea_mode);
4125
d9278b4c
JN		 4126static bool drm_valid_cea_vic(u8 vic)
4127{
7befe621 4128 return cea_mode_for_vic(vic) != NULL;
d9278b4c
JN		 4129}
4130
28c03a44 4131static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
0967e6a5 4132{
7befe621
VS		 4133 const struct drm_display_mode *mode = cea_mode_for_vic(video_code);
4134
4135 if (mode)
4136 return mode->picture_aspect_ratio;
4137
4138 return HDMI_PICTURE_ASPECT_NONE;
0967e6a5 4139}
0967e6a5 4140
d2b43473
WL		 4141static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code)
4142{
4143 return edid_4k_modes[video_code].picture_aspect_ratio;
4144}
4145
3f2f6533
LD		 4146/*
4147 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
4148 * specific block).
3f2f6533
LD		 4149 */
4150static unsigned int
4151hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
4152{
3f2f6533
LD		 4153 return cea_mode_alternate_clock(hdmi_mode);
4154}
4155
4c6bcf44
VS		 4156static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
4157 unsigned int clock_tolerance)
4158{
357768cc 4159 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 4160 u8 vic;
4c6bcf44
VS		 4161
4162 if (!to_match->clock)
4163 return 0;
4164
d2b43473
WL		 4165 if (to_match->picture_aspect_ratio)
4166 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4167
d9278b4c
JN		 4168 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
4169 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4c6bcf44
VS		 4170 unsigned int clock1, clock2;
4171
4172 /* Make sure to also match alternate clocks */
4173 clock1 = hdmi_mode->clock;
4174 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
4175
4176 if (abs(to_match->clock - clock1) > clock_tolerance &&
4177 abs(to_match->clock - clock2) > clock_tolerance)
4178 continue;
4179
357768cc 4180 if (drm_mode_match(to_match, hdmi_mode, match_flags))
d9278b4c 4181 return vic;
4c6bcf44
VS		 4182 }
4183
4184 return 0;
4185}
4186
3f2f6533
LD		 4187/*
4188 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
4189 * @to_match: display mode
4190 *
4191 * An HDMI mode is one defined in the HDMI vendor specific block.
4192 *
4193 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
4194 */
4195static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
4196{
357768cc 4197 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 4198 u8 vic;
3f2f6533
LD		 4199
4200 if (!to_match->clock)
4201 return 0;
4202
d2b43473
WL		 4203 if (to_match->picture_aspect_ratio)
4204 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4205
d9278b4c
JN		 4206 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
4207 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3f2f6533
LD		 4208 unsigned int clock1, clock2;
4209
4210 /* Make sure to also match alternate clocks */
4211 clock1 = hdmi_mode->clock;
4212 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
4213
4214 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
4215 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
357768cc 4216 drm_mode_match(to_match, hdmi_mode, match_flags))
d9278b4c 4217 return vic;
3f2f6533
LD		 4218 }
4219 return 0;
4220}
4221
d9278b4c
JN		 4222static bool drm_valid_hdmi_vic(u8 vic)
4223{
4224 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
4225}
4226
40f71f5b
JN		 4227static int add_alternate_cea_modes(struct drm_connector *connector,
4228 const struct drm_edid *drm_edid)
e6e79209
VS		 4229{
4230 struct drm_device *dev = connector->dev;
4231 struct drm_display_mode *mode, *tmp;
4232 LIST_HEAD(list);
4233 int modes = 0;
4234
6ff1c19f 4235 /* Don't add CTA modes if the CTA extension block is missing */
40f71f5b 4236 if (!drm_edid_has_cta_extension(drm_edid))
e6e79209
VS		 4237 return 0;
4238
4239 /*
4240 * Go through all probed modes and create a new mode
4241 * with the alternate clock for certain CEA modes.
4242 */
4243 list_for_each_entry(mode, &connector->probed_modes, head) {
3f2f6533 4244 const struct drm_display_mode *cea_mode = NULL;
e6e79209 4245 struct drm_display_mode *newmode;
d9278b4c 4246 u8 vic = drm_match_cea_mode(mode);
e6e79209
VS		 4247 unsigned int clock1, clock2;
4248
d9278b4c 4249 if (drm_valid_cea_vic(vic)) {
7befe621 4250 cea_mode = cea_mode_for_vic(vic);
3f2f6533
LD		 4251 clock2 = cea_mode_alternate_clock(cea_mode);
4252 } else {
d9278b4c
JN		 4253 vic = drm_match_hdmi_mode(mode);
4254 if (drm_valid_hdmi_vic(vic)) {
4255 cea_mode = &edid_4k_modes[vic];
3f2f6533
LD		 4256 clock2 = hdmi_mode_alternate_clock(cea_mode);
4257 }
4258 }
e6e79209 4259
3f2f6533
LD		 4260 if (!cea_mode)
4261 continue;
e6e79209
VS		 4262
4263 clock1 = cea_mode->clock;
e6e79209
VS		 4264
4265 if (clock1 == clock2)
4266 continue;
4267
4268 if (mode->clock != clock1 && mode->clock != clock2)
4269 continue;
4270
4271 newmode = drm_mode_duplicate(dev, cea_mode);
4272 if (!newmode)
4273 continue;
4274
27130212
DL		 4275 /* Carry over the stereo flags */
4276 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
4277
e6e79209
VS		 4278 /*
4279 * The current mode could be either variant. Make
4280 * sure to pick the "other" clock for the new mode.
4281 */
4282 if (mode->clock != clock1)
4283 newmode->clock = clock1;
4284 else
4285 newmode->clock = clock2;
4286
4287 list_add_tail(&newmode->head, &list);
4288 }
4289
4290 list_for_each_entry_safe(mode, tmp, &list, head) {
4291 list_del(&mode->head);
4292 drm_mode_probed_add(connector, mode);
4293 modes++;
4294 }
4295
4296 return modes;
4297}
a4799037 4298
8ec6e075
SS		 4299static u8 svd_to_vic(u8 svd)
4300{
4301 /* 0-6 bit vic, 7th bit native mode indicator */
4302 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
4303 return svd & 127;
4304
4305 return svd;
4306}
4307
aff04ace
TW		 4308static struct drm_display_mode *
4309drm_display_mode_from_vic_index(struct drm_connector *connector,
4310 const u8 *video_db, u8 video_len,
4311 u8 video_index)
54ac76f8
CS		 4312{
4313 struct drm_device *dev = connector->dev;
aff04ace 4314 struct drm_display_mode *newmode;
d9278b4c 4315 u8 vic;
54ac76f8 4316
aff04ace
TW		 4317 if (video_db == NULL || video_index >= video_len)
4318 return NULL;
4319
4320 /* CEA modes are numbered 1..127 */
8ec6e075 4321 vic = svd_to_vic(video_db[video_index]);
d9278b4c 4322 if (!drm_valid_cea_vic(vic))
aff04ace
TW		 4323 return NULL;
4324
7befe621 4325 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
409bbf1e
DL		 4326 if (!newmode)
4327 return NULL;
4328
aff04ace
TW		 4329 return newmode;
4330}
4331
832d4f2f
SS		 4332/*
4333 * do_y420vdb_modes - Parse YCBCR 420 only modes
4334 * @connector: connector corresponding to the HDMI sink
4335 * @svds: start of the data block of CEA YCBCR 420 VDB
4336 * @len: length of the CEA YCBCR 420 VDB
4337 *
4338 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
4339 * which contains modes which can be supported in YCBCR 420
4340 * output format only.
4341 */
4342static int do_y420vdb_modes(struct drm_connector *connector,
4343 const u8 *svds, u8 svds_len)
4344{
4345 int modes = 0, i;
4346 struct drm_device *dev = connector->dev;
4347 struct drm_display_info *info = &connector->display_info;
4348 struct drm_hdmi_info *hdmi = &info->hdmi;
4349
4350 for (i = 0; i < svds_len; i++) {
4351 u8 vic = svd_to_vic(svds[i]);
4352 struct drm_display_mode *newmode;
4353
4354 if (!drm_valid_cea_vic(vic))
4355 continue;
4356
7befe621 4357 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
832d4f2f
SS		 4358 if (!newmode)
4359 break;
4360 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
4361 drm_mode_probed_add(connector, newmode);
4362 modes++;
4363 }
4364
4365 if (modes > 0)
c03d0b52 4366 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
832d4f2f
SS		 4367 return modes;
4368}
4369
4370/*
4371 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap
4372 * @connector: connector corresponding to the HDMI sink
4373 * @vic: CEA vic for the video mode to be added in the map
4374 *
4375 * Makes an entry for a videomode in the YCBCR 420 bitmap
4376 */
4377static void
4378drm_add_cmdb_modes(struct drm_connector *connector, u8 svd)
4379{
4380 u8 vic = svd_to_vic(svd);
4381 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4382
4383 if (!drm_valid_cea_vic(vic))
4384 return;
4385
4386 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
4387}
4388
7af655bc
VS		 4389/**
4390 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC
4391 * @dev: DRM device
8d7d8c0a 4392 * @video_code: CEA VIC of the mode
7af655bc
VS		 4393 *
4394 * Creates a new mode matching the specified CEA VIC.
4395 *
4396 * Returns: A new drm_display_mode on success or NULL on failure
4397 */
4398struct drm_display_mode *
4399drm_display_mode_from_cea_vic(struct drm_device *dev,
4400 u8 video_code)
4401{
4402 const struct drm_display_mode *cea_mode;
4403 struct drm_display_mode *newmode;
4404
4405 cea_mode = cea_mode_for_vic(video_code);
4406 if (!cea_mode)
4407 return NULL;
4408
4409 newmode = drm_mode_duplicate(dev, cea_mode);
4410 if (!newmode)
4411 return NULL;
4412
4413 return newmode;
4414}
4415EXPORT_SYMBOL(drm_display_mode_from_cea_vic);
4416
aff04ace
TW		 4417static int
4418do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
4419{
4420 int i, modes = 0;
832d4f2f 4421 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
aff04ace
TW		 4422
4423 for (i = 0; i < len; i++) {
4424 struct drm_display_mode *mode;
948de842 4425
aff04ace
TW		 4426 mode = drm_display_mode_from_vic_index(connector, db, len, i);
4427 if (mode) {
832d4f2f
SS		 4428 /*
4429 * YCBCR420 capability block contains a bitmap which
4430 * gives the index of CEA modes from CEA VDB, which
4431 * can support YCBCR 420 sampling output also (apart
4432 * from RGB/YCBCR444 etc).
4433 * For example, if the bit 0 in bitmap is set,
4434 * first mode in VDB can support YCBCR420 output too.
4435 * Add YCBCR420 modes only if sink is HDMI 2.0 capable.
4436 */
4437 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i))
4438 drm_add_cmdb_modes(connector, db[i]);
4439
aff04ace
TW		 4440 drm_mode_probed_add(connector, mode);
4441 modes++;
54ac76f8
CS		 4442 }
4443 }
4444
4445 return modes;
4446}
4447
c858cfca
DL		 4448struct stereo_mandatory_mode {
4449 int width, height, vrefresh;
4450 unsigned int flags;
4451};
4452
4453static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
f7e121b7
DL		 4454 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4455 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
c858cfca
DL		 4456 { 1920, 1080, 50,
4457 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
4458 { 1920, 1080, 60,
4459 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
f7e121b7
DL		 4460 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4461 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
4462 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4463 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
c858cfca
DL		 4464};
4465
4466static bool
4467stereo_match_mandatory(const struct drm_display_mode *mode,
4468 const struct stereo_mandatory_mode *stereo_mode)
4469{
4470 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
4471
4472 return mode->hdisplay == stereo_mode->width &&
4473 mode->vdisplay == stereo_mode->height &&
4474 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
4475 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
4476}
4477
c858cfca
DL		 4478static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
4479{
4480 struct drm_device *dev = connector->dev;
4481 const struct drm_display_mode *mode;
4482 struct list_head stereo_modes;
f7e121b7 4483 int modes = 0, i;
c858cfca
DL		 4484
4485 INIT_LIST_HEAD(&stereo_modes);
4486
4487 list_for_each_entry(mode, &connector->probed_modes, head) {
f7e121b7
DL		 4488 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
4489 const struct stereo_mandatory_mode *mandatory;
c858cfca
DL		 4490 struct drm_display_mode *new_mode;
4491
f7e121b7
DL		 4492 if (!stereo_match_mandatory(mode,
4493 &stereo_mandatory_modes[i]))
4494 continue;
c858cfca 4495
f7e121b7 4496 mandatory = &stereo_mandatory_modes[i];
c858cfca
DL		 4497 new_mode = drm_mode_duplicate(dev, mode);
4498 if (!new_mode)
4499 continue;
4500
f7e121b7 4501 new_mode->flags |= mandatory->flags;
c858cfca
DL		 4502 list_add_tail(&new_mode->head, &stereo_modes);
4503 modes++;
f7e121b7 4504 }
c858cfca
DL		 4505 }
4506
4507 list_splice_tail(&stereo_modes, &connector->probed_modes);
4508
4509 return modes;
4510}
4511
1deee8d7
DL		 4512static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
4513{
4514 struct drm_device *dev = connector->dev;
4515 struct drm_display_mode *newmode;
4516
d9278b4c 4517 if (!drm_valid_hdmi_vic(vic)) {
1deee8d7
DL		 4518 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
4519 return 0;
4520 }
4521
4522 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
4523 if (!newmode)
4524 return 0;
4525
4526 drm_mode_probed_add(connector, newmode);
4527
4528 return 1;
4529}
4530
fbf46025
TW		 4531static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
4532 const u8 *video_db, u8 video_len, u8 video_index)
4533{
fbf46025
TW		 4534 struct drm_display_mode *newmode;
4535 int modes = 0;
fbf46025
TW		 4536
4537 if (structure & (1 << 0)) {
aff04ace
TW		 4538 newmode = drm_display_mode_from_vic_index(connector, video_db,
4539 video_len,
4540 video_index);
fbf46025
TW		 4541 if (newmode) {
4542 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
4543 drm_mode_probed_add(connector, newmode);
4544 modes++;
4545 }
4546 }
4547 if (structure & (1 << 6)) {
aff04ace
TW		 4548 newmode = drm_display_mode_from_vic_index(connector, video_db,
4549 video_len,
4550 video_index);
fbf46025
TW		 4551 if (newmode) {
4552 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4553 drm_mode_probed_add(connector, newmode);
4554 modes++;
4555 }
4556 }
4557 if (structure & (1 << 8)) {
aff04ace
TW		 4558 newmode = drm_display_mode_from_vic_index(connector, video_db,
4559 video_len,
4560 video_index);
fbf46025 4561 if (newmode) {
89570eeb 4562 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
fbf46025
TW		 4563 drm_mode_probed_add(connector, newmode);
4564 modes++;
4565 }
4566 }
4567
4568 return modes;
4569}
4570
7ebe1963
LD		 4571/*
4572 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
4573 * @connector: connector corresponding to the HDMI sink
4574 * @db: start of the CEA vendor specific block
4575 * @len: length of the CEA block payload, ie. one can access up to db[len]
4576 *
c858cfca
DL		 4577 * Parses the HDMI VSDB looking for modes to add to @connector. This function
4578 * also adds the stereo 3d modes when applicable.
7ebe1963
LD		 4579 */
4580static int
fbf46025
TW		 4581do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
4582 const u8 *video_db, u8 video_len)
7ebe1963 4583{
f1781e9b 4584 struct drm_display_info *info = &connector->display_info;
0e5083aa 4585 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
fbf46025
TW		 4586 u8 vic_len, hdmi_3d_len = 0;
4587 u16 mask;
4588 u16 structure_all;
7ebe1963
LD		 4589
4590 if (len < 8)
4591 goto out;
4592
4593 /* no HDMI_Video_Present */
4594 if (!(db[8] & (1 << 5)))
4595 goto out;
4596
4597 /* Latency_Fields_Present */
4598 if (db[8] & (1 << 7))
4599 offset += 2;
4600
4601 /* I_Latency_Fields_Present */
4602 if (db[8] & (1 << 6))
4603 offset += 2;
4604
4605 /* the declared length is not long enough for the 2 first bytes
4606 * of additional video format capabilities */
c858cfca 4607 if (len < (8 + offset + 2))
7ebe1963
LD		 4608 goto out;
4609
c858cfca
DL		 4610 /* 3D_Present */
4611 offset++;
fbf46025 4612 if (db[8 + offset] & (1 << 7)) {
c858cfca
DL		 4613 modes += add_hdmi_mandatory_stereo_modes(connector);
4614
fbf46025
TW		 4615 /* 3D_Multi_present */
4616 multi_present = (db[8 + offset] & 0x60) >> 5;
4617 }
4618
c858cfca 4619 offset++;
7ebe1963 4620 vic_len = db[8 + offset] >> 5;
fbf46025 4621 hdmi_3d_len = db[8 + offset] & 0x1f;
7ebe1963
LD		 4622
4623 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
7ebe1963
LD		 4624 u8 vic;
4625
4626 vic = db[9 + offset + i];
1deee8d7 4627 modes += add_hdmi_mode(connector, vic);
7ebe1963 4628 }
fbf46025
TW		 4629 offset += 1 + vic_len;
4630
0e5083aa
TW		 4631 if (multi_present == 1)
4632 multi_len = 2;
4633 else if (multi_present == 2)
4634 multi_len = 4;
4635 else
4636 multi_len = 0;
fbf46025 4637
0e5083aa 4638 if (len < (8 + offset + hdmi_3d_len - 1))
fbf46025
TW		 4639 goto out;
4640
0e5083aa 4641 if (hdmi_3d_len < multi_len)
fbf46025
TW		 4642 goto out;
4643
0e5083aa
TW		 4644 if (multi_present == 1 || multi_present == 2) {
4645 /* 3D_Structure_ALL */
4646 structure_all = (db[8 + offset] << 8) | db[9 + offset];
fbf46025 4647
0e5083aa
TW		 4648 /* check if 3D_MASK is present */
4649 if (multi_present == 2)
4650 mask = (db[10 + offset] << 8) | db[11 + offset];
4651 else
4652 mask = 0xffff;
4653
4654 for (i = 0; i < 16; i++) {
4655 if (mask & (1 << i))
4656 modes += add_3d_struct_modes(connector,
4657 structure_all,
4658 video_db,
4659 video_len, i);
4660 }
4661 }
4662
4663 offset += multi_len;
4664
4665 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
4666 int vic_index;
4667 struct drm_display_mode *newmode = NULL;
4668 unsigned int newflag = 0;
4669 bool detail_present;
4670
4671 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
4672
4673 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
4674 break;
4675
4676 /* 2D_VIC_order_X */
4677 vic_index = db[8 + offset + i] >> 4;
4678
4679 /* 3D_Structure_X */
4680 switch (db[8 + offset + i] & 0x0f) {
4681 case 0:
4682 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
4683 break;
4684 case 6:
4685 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4686 break;
4687 case 8:
4688 /* 3D_Detail_X */
4689 if ((db[9 + offset + i] >> 4) == 1)
4690 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4691 break;
4692 }
4693
4694 if (newflag != 0) {
4695 newmode = drm_display_mode_from_vic_index(connector,
4696 video_db,
4697 video_len,
4698 vic_index);
4699
4700 if (newmode) {
4701 newmode->flags |= newflag;
4702 drm_mode_probed_add(connector, newmode);
4703 modes++;
4704 }
4705 }
4706
4707 if (detail_present)
4708 i++;
fbf46025 4709 }
7ebe1963
LD		 4710
4711out:
f1781e9b
VS		 4712 if (modes > 0)
4713 info->has_hdmi_infoframe = true;
7ebe1963
LD		 4714 return modes;
4715}
4716
9e50b9d5
VS		 4717static int
4718cea_revision(const u8 *cea)
4719{
5036c0d0
VS		 4720 /*
4721 * FIXME is this correct for the DispID variant?
4722 * The DispID spec doesn't really specify whether
4723 * this is the revision of the CEA extension or
4724 * the DispID CEA data block. And the only value
4725 * given as an example is 0.
4726 */
9e50b9d5
VS		 4727 return cea[1];
4728}
4729
aba58254
JN		 4730/*
4731 * CTA Data Block iterator.
4732 *
4733 * Iterate through all CTA Data Blocks in both EDID CTA Extensions and DisplayID
4734 * CTA Data Blocks.
4735 *
4736 * struct cea_db *db:
4737 * struct cea_db_iter iter;
4738 *
4739 * cea_db_iter_edid_begin(edid, &iter);
4740 * cea_db_iter_for_each(db, &iter) {
4741 * // do stuff with db
4742 * }
4743 * cea_db_iter_end(&iter);
4744 */
4745struct cea_db_iter {
4746 struct drm_edid_iter edid_iter;
4747 struct displayid_iter displayid_iter;
4748
4749 /* Current Data Block Collection. */
4750 const u8 *collection;
4751
4752 /* Current Data Block index in current collection. */
4753 int index;
4754
4755 /* End index in current collection. */
4756 int end;
4757};
4758
4759/* CTA-861-H section 7.4 CTA Data BLock Collection */
4760struct cea_db {
4761 u8 tag_length;
4762 u8 data[];
4763} __packed;
4764
49a62a29 4765static int cea_db_tag(const struct cea_db *db)
aba58254 4766{
aba58254
JN		 4767 return db->tag_length >> 5;
4768}
4769
4770static int cea_db_payload_len(const void *_db)
4771{
4772 /* FIXME: Transition to passing struct cea_db * everywhere. */
4773 const struct cea_db *db = _db;
4774
4775 return db->tag_length & 0x1f;
4776}
4777
4778static const void *cea_db_data(const struct cea_db *db)
4779{
4780 return db->data;
4781}
4782
a9ec4fd0
JN		 4783static bool cea_db_is_extended_tag(const struct cea_db *db, int tag)
4784{
4785 return cea_db_tag(db) == CTA_DB_EXTENDED_TAG &&
4786 cea_db_payload_len(db) >= 1 &&
4787 db->data[0] == tag;
4788}
4789
4790static bool cea_db_is_vendor(const struct cea_db *db, int vendor_oui)
4791{
4792 const u8 *data = cea_db_data(db);
4793
4794 return cea_db_tag(db) == CTA_DB_VENDOR &&
4795 cea_db_payload_len(db) >= 3 &&
4796 oui(data[2], data[1], data[0]) == vendor_oui;
4797}
4798
5e87b2e5
JN		 4799static void cea_db_iter_edid_begin(const struct drm_edid *drm_edid,
4800 struct cea_db_iter *iter)
aba58254
JN		 4801{
4802 memset(iter, 0, sizeof(*iter));
4803
bbded689 4804 drm_edid_iter_begin(drm_edid, &iter->edid_iter);
d9ba1b4c 4805 displayid_iter_edid_begin(drm_edid, &iter->displayid_iter);
aba58254
JN		 4806}
4807
4808static const struct cea_db *
4809__cea_db_iter_current_block(const struct cea_db_iter *iter)
4810{
4811 const struct cea_db *db;
4812
4813 if (!iter->collection)
4814 return NULL;
4815
4816 db = (const struct cea_db *)&iter->collection[iter->index];
4817
4818 if (iter->index + sizeof(*db) <= iter->end &&
4819 iter->index + sizeof(*db) + cea_db_payload_len(db) <= iter->end)
4820 return db;
4821
4822 return NULL;
4823}
4824
11a8d095
JN		 4825/*
4826 * References:
4827 * - CTA-861-H section 7.3.3 CTA Extension Version 3
4828 */
4829static int cea_db_collection_size(const u8 *cta)
4830{
4831 u8 d = cta[2];
4832
4833 if (d < 4 || d > 127)
4834 return 0;
4835
4836 return d - 4;
4837}
4838
aba58254
JN		 4839/*
4840 * References:
4841 * - VESA E-EDID v1.4
4842 * - CTA-861-H section 7.3.3 CTA Extension Version 3
4843 */
4844static const void *__cea_db_iter_edid_next(struct cea_db_iter *iter)
4845{
4846 const u8 *ext;
4847
4848 drm_edid_iter_for_each(ext, &iter->edid_iter) {
11a8d095
JN		 4849 int size;
4850
aba58254
JN		 4851 /* Only support CTA Extension revision 3+ */
4852 if (ext[0] != CEA_EXT || cea_revision(ext) < 3)
4853 continue;
4854
11a8d095
JN		 4855 size = cea_db_collection_size(ext);
4856 if (!size)
aba58254
JN		 4857 continue;
4858
11a8d095
JN		 4859 iter->index = 4;
4860 iter->end = iter->index + size;
4861
aba58254
JN		 4862 return ext;
4863 }
4864
4865 return NULL;
4866}
4867
4868/*
4869 * References:
4870 * - DisplayID v1.3 Appendix C: CEA Data Block within a DisplayID Data Block
4871 * - DisplayID v2.0 section 4.10 CTA DisplayID Data Block
4872 *
4873 * Note that the above do not specify any connection between DisplayID Data
4874 * Block revision and CTA Extension versions.
4875 */
4876static const void *__cea_db_iter_displayid_next(struct cea_db_iter *iter)
4877{
4878 const struct displayid_block *block;
4879
4880 displayid_iter_for_each(block, &iter->displayid_iter) {
4881 if (block->tag != DATA_BLOCK_CTA)
4882 continue;
4883
4884 /*
4885 * The displayid iterator has already verified the block bounds
4886 * in displayid_iter_block().
4887 */
4888 iter->index = sizeof(*block);
4889 iter->end = iter->index + block->num_bytes;
4890
4891 return block;
4892 }
4893
4894 return NULL;
4895}
4896
4897static const struct cea_db *__cea_db_iter_next(struct cea_db_iter *iter)
4898{
4899 const struct cea_db *db;
4900
4901 if (iter->collection) {
4902 /* Current collection should always be valid. */
4903 db = __cea_db_iter_current_block(iter);
4904 if (WARN_ON(!db)) {
4905 iter->collection = NULL;
4906 return NULL;
4907 }
4908
4909 /* Next block in CTA Data Block Collection */
4910 iter->index += sizeof(*db) + cea_db_payload_len(db);
4911
4912 db = __cea_db_iter_current_block(iter);
4913 if (db)
4914 return db;
4915 }
4916
4917 for (;;) {
4918 /*
4919 * Find the next CTA Data Block Collection. First iterate all
4920 * the EDID CTA Extensions, then all the DisplayID CTA blocks.
4921 *
4922 * Per DisplayID v1.3 Appendix B: DisplayID as an EDID
4923 * Extension, it's recommended that DisplayID extensions are
4924 * exposed after all of the CTA Extensions.
4925 */
4926 iter->collection = __cea_db_iter_edid_next(iter);
4927 if (!iter->collection)
4928 iter->collection = __cea_db_iter_displayid_next(iter);
4929
4930 if (!iter->collection)
4931 return NULL;
4932
4933 db = __cea_db_iter_current_block(iter);
4934 if (db)
4935 return db;
4936 }
4937}
4938
4939#define cea_db_iter_for_each(__db, __iter) \
4940 while (((__db) = __cea_db_iter_next(__iter)))
4941
4942static void cea_db_iter_end(struct cea_db_iter *iter)
4943{
4944 displayid_iter_end(&iter->displayid_iter);
4945 drm_edid_iter_end(&iter->edid_iter);
4946
4947 memset(iter, 0, sizeof(*iter));
4948}
4949
49a62a29 4950static bool cea_db_is_hdmi_vsdb(const struct cea_db *db)
7ebe1963 4951{
a9ec4fd0
JN		 4952 return cea_db_is_vendor(db, HDMI_IEEE_OUI) &&
4953 cea_db_payload_len(db) >= 5;
7ebe1963
LD		 4954}
4955
49a62a29 4956static bool cea_db_is_hdmi_forum_vsdb(const struct cea_db *db)
50dd1bd1 4957{
a9ec4fd0
JN		 4958 return cea_db_is_vendor(db, HDMI_FORUM_IEEE_OUI) &&
4959 cea_db_payload_len(db) >= 7;
50dd1bd1
TR		 4960}
4961
18e3c1d5
JN		 4962static bool cea_db_is_hdmi_forum_eeodb(const void *db)
4963{
4964 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_EEODB) &&
4965 cea_db_payload_len(db) >= 2;
4966}
4967
49a62a29 4968static bool cea_db_is_microsoft_vsdb(const struct cea_db *db)
2869f599 4969{
a9ec4fd0
JN		 4970 return cea_db_is_vendor(db, MICROSOFT_IEEE_OUI) &&
4971 cea_db_payload_len(db) == 21;
2869f599
PZ		 4972}
4973
49a62a29 4974static bool cea_db_is_vcdb(const struct cea_db *db)
1581b2df 4975{
a9ec4fd0
JN		 4976 return cea_db_is_extended_tag(db, CTA_EXT_DB_VIDEO_CAP) &&
4977 cea_db_payload_len(db) == 2;
1581b2df
VS		 4978}
4979
49a62a29 4980static bool cea_db_is_hdmi_forum_scdb(const struct cea_db *db)
115fcf58 4981{
a9ec4fd0
JN		 4982 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_SCDB) &&
4983 cea_db_payload_len(db) >= 7;
115fcf58
LS		 4984}
4985
49a62a29 4986static bool cea_db_is_y420cmdb(const struct cea_db *db)
832d4f2f 4987{
a9ec4fd0 4988 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_CAP_MAP);
832d4f2f
SS		 4989}
4990
49a62a29 4991static bool cea_db_is_y420vdb(const struct cea_db *db)
832d4f2f 4992{
a9ec4fd0
JN		 4993 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_DATA);
4994}
832d4f2f 4995
49a62a29 4996static bool cea_db_is_hdmi_hdr_metadata_block(const struct cea_db *db)
a9ec4fd0
JN		 4997{
4998 return cea_db_is_extended_tag(db, CTA_EXT_DB_HDR_STATIC_METADATA) &&
4999 cea_db_payload_len(db) >= 3;
832d4f2f
SS		 5000}
5001
18e3c1d5
JN		 5002/*
5003 * Get the HF-EEODB override extension block count from EDID.
5004 *
5005 * The passed in EDID may be partially read, as long as it has at least two
5006 * blocks (base block and one extension block) if EDID extension count is > 0.
5007 *
5008 * Note that this is *not* how you should parse CTA Data Blocks in general; this
5009 * is only to handle partially read EDIDs. Normally, use the CTA Data Block
5010 * iterators instead.
5011 *
5012 * References:
5013 * - HDMI 2.1 section 10.3.6 HDMI Forum EDID Extension Override Data Block
5014 */
5015static int edid_hfeeodb_extension_block_count(const struct edid *edid)
5016{
5017 const u8 *cta;
5018
5019 /* No extensions according to base block, no HF-EEODB. */
5020 if (!edid_extension_block_count(edid))
5021 return 0;
5022
5023 /* HF-EEODB is always in the first EDID extension block only */
5024 cta = edid_extension_block_data(edid, 0);
5025 if (edid_block_tag(cta) != CEA_EXT || cea_revision(cta) < 3)
5026 return 0;
5027
5028 /* Need to have the data block collection, and at least 3 bytes. */
5029 if (cea_db_collection_size(cta) < 3)
5030 return 0;
5031
5032 /*
5033 * Sinks that include the HF-EEODB in their E-EDID shall include one and
5034 * only one instance of the HF-EEODB in the E-EDID, occupying bytes 4
5035 * through 6 of Block 1 of the E-EDID.
5036 */
5037 if (!cea_db_is_hdmi_forum_eeodb(&cta[4]))
5038 return 0;
5039
5040 return cta[4 + 2];
5041}
5042
832d4f2f
SS		 5043static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector,
5044 const u8 *db)
5045{
5046 struct drm_display_info *info = &connector->display_info;
5047 struct drm_hdmi_info *hdmi = &info->hdmi;
5048 u8 map_len = cea_db_payload_len(db) - 1;
5049 u8 count;
5050 u64 map = 0;
5051
5052 if (map_len == 0) {
5053 /* All CEA modes support ycbcr420 sampling also.*/
5054 hdmi->y420_cmdb_map = U64_MAX;
c03d0b52 5055 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
832d4f2f
SS		 5056 return;
5057 }
5058
5059 /*
5060 * This map indicates which of the existing CEA block modes
5061 * from VDB can support YCBCR420 output too. So if bit=0 is
5062 * set, first mode from VDB can support YCBCR420 output too.
5063 * We will parse and keep this map, before parsing VDB itself
5064 * to avoid going through the same block again and again.
5065 *
5066 * Spec is not clear about max possible size of this block.
5067 * Clamping max bitmap block size at 8 bytes. Every byte can
5068 * address 8 CEA modes, in this way this map can address
5069 * 8*8 = first 64 SVDs.
5070 */
5071 if (WARN_ON_ONCE(map_len > 8))
5072 map_len = 8;
5073
5074 for (count = 0; count < map_len; count++)
5075 map |= (u64)db[2 + count] << (8 * count);
5076
5077 if (map)
c03d0b52 5078 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
832d4f2f
SS		 5079
5080 hdmi->y420_cmdb_map = map;
5081}
5082
40f71f5b
JN		 5083static int add_cea_modes(struct drm_connector *connector,
5084 const struct drm_edid *drm_edid)
54ac76f8 5085{
537d9ed2
JN		 5086 const struct cea_db *db;
5087 struct cea_db_iter iter;
54ac76f8
CS		 5088 int modes = 0;
5089
5e87b2e5 5090 cea_db_iter_edid_begin(drm_edid, &iter);
537d9ed2
JN		 5091 cea_db_iter_for_each(db, &iter) {
5092 const u8 *hdmi = NULL, *video = NULL;
5093 u8 hdmi_len = 0, video_len = 0;
5094
5095 if (cea_db_tag(db) == CTA_DB_VIDEO) {
5096 video = cea_db_data(db);
5097 video_len = cea_db_payload_len(db);
5098 modes += do_cea_modes(connector, video, video_len);
5099 } else if (cea_db_is_hdmi_vsdb(db)) {
5100 /* FIXME: Switch to use cea_db_data() */
5101 hdmi = (const u8 *)db;
5102 hdmi_len = cea_db_payload_len(db);
5103 } else if (cea_db_is_y420vdb(db)) {
5104 const u8 *vdb420 = cea_db_data(db) + 1;
5105
5106 /* Add 4:2:0(only) modes present in EDID */
5107 modes += do_y420vdb_modes(connector, vdb420,
5108 cea_db_payload_len(db) - 1);
54ac76f8 5109 }
54ac76f8 5110
537d9ed2
JN		 5111 /*
5112 * We parse the HDMI VSDB after having added the cea modes as we
5113 * will be patching their flags when the sink supports stereo
5114 * 3D.
5115 */
5116 if (hdmi)
5117 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len,
5118 video, video_len);
5119 }
5120 cea_db_iter_end(&iter);
c858cfca 5121
54ac76f8
CS		 5122 return modes;
5123}
5124
fa3a7340
VS		 5125static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
5126{
5127 const struct drm_display_mode *cea_mode;
5128 int clock1, clock2, clock;
d9278b4c 5129 u8 vic;
fa3a7340
VS		 5130 const char *type;
5131
4c6bcf44
VS		 5132 /*
5133 * allow 5kHz clock difference either way to account for
5134 * the 10kHz clock resolution limit of detailed timings.
5135 */
d9278b4c
JN		 5136 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
5137 if (drm_valid_cea_vic(vic)) {
fa3a7340 5138 type = "CEA";
7befe621 5139 cea_mode = cea_mode_for_vic(vic);
fa3a7340
VS		 5140 clock1 = cea_mode->clock;
5141 clock2 = cea_mode_alternate_clock(cea_mode);
5142 } else {
d9278b4c
JN		 5143 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
5144 if (drm_valid_hdmi_vic(vic)) {
fa3a7340 5145 type = "HDMI";
d9278b4c 5146 cea_mode = &edid_4k_modes[vic];
fa3a7340
VS		 5147 clock1 = cea_mode->clock;
5148 clock2 = hdmi_mode_alternate_clock(cea_mode);
5149 } else {
5150 return;
5151 }
5152 }
5153
5154 /* pick whichever is closest */
5155 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
5156 clock = clock1;
5157 else
5158 clock = clock2;
5159
5160 if (mode->clock == clock)
5161 return;
5162
5163 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
d9278b4c 5164 type, vic, mode->clock, clock);
fa3a7340
VS		 5165 mode->clock = clock;
5166}
5167
e85959d6
US		 5168static uint8_t eotf_supported(const u8 *edid_ext)
5169{
5170 return edid_ext[2] &
5171 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
5172 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
b5e3eed1
VS		 5173 BIT(HDMI_EOTF_SMPTE_ST2084) |
5174 BIT(HDMI_EOTF_BT_2100_HLG));
e85959d6
US		 5175}
5176
5177static uint8_t hdr_metadata_type(const u8 *edid_ext)
5178{
5179 return edid_ext[3] &
5180 BIT(HDMI_STATIC_METADATA_TYPE1);
5181}
5182
5183static void
5184drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
5185{
5186 u16 len;
5187
5188 len = cea_db_payload_len(db);
5189
5190 connector->hdr_sink_metadata.hdmi_type1.eotf =
5191 eotf_supported(db);
5192 connector->hdr_sink_metadata.hdmi_type1.metadata_type =
5193 hdr_metadata_type(db);
5194
5195 if (len >= 4)
5196 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4];
5197 if (len >= 5)
5198 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5];
5199 if (len >= 6)
5200 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6];
5201}
5202
76adaa34 5203static void
23ebf8b9 5204drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
76adaa34 5205{
8504072a 5206 u8 len = cea_db_payload_len(db);
76adaa34 5207
f7da7785
JN		 5208 if (len >= 6 && (db[6] & (1 << 7)))
5209 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
8504072a
VS		 5210 if (len >= 8) {
5211 connector->latency_present[0] = db[8] >> 7;
5212 connector->latency_present[1] = (db[8] >> 6) & 1;
5213 }
5214 if (len >= 9)
5215 connector->video_latency[0] = db[9];
5216 if (len >= 10)
5217 connector->audio_latency[0] = db[10];
5218 if (len >= 11)
5219 connector->video_latency[1] = db[11];
5220 if (len >= 12)
5221 connector->audio_latency[1] = db[12];
76adaa34 5222
23ebf8b9
VS		 5223 DRM_DEBUG_KMS("HDMI: latency present %d %d, "
5224 "video latency %d %d, "
5225 "audio latency %d %d\n",
5226 connector->latency_present[0],
5227 connector->latency_present[1],
5228 connector->video_latency[0],
5229 connector->video_latency[1],
5230 connector->audio_latency[0],
5231 connector->audio_latency[1]);
76adaa34
WF		 5232}
5233
5234static void
4194442d 5235monitor_name(const struct detailed_timing *timing, void *data)
76adaa34 5236{
4194442d
JN		 5237 const char **res = data;
5238
5239 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME))
a7a131ac
VS		 5240 return;
5241
4194442d 5242 *res = timing->data.other_data.data.str.str;
14f77fdd
VS		 5243}
5244
2c54f87c 5245static int get_monitor_name(const struct drm_edid *drm_edid, char name[13])
59f7c0fa 5246{
4194442d 5247 const char *edid_name = NULL;
59f7c0fa
JB		 5248 int mnl;
5249
2c54f87c 5250 if (!drm_edid || !name)
59f7c0fa
JB		 5251 return 0;
5252
45aa2336 5253 drm_for_each_detailed_block(drm_edid, monitor_name, &edid_name);
59f7c0fa
JB		 5254 for (mnl = 0; edid_name && mnl < 13; mnl++) {
5255 if (edid_name[mnl] == 0x0a)
5256 break;
5257
5258 name[mnl] = edid_name[mnl];
5259 }
5260
5261 return mnl;
5262}
5263
5264/**
5265 * drm_edid_get_monitor_name - fetch the monitor name from the edid
5266 * @edid: monitor EDID information
5267 * @name: pointer to a character array to hold the name of the monitor
5268 * @bufsize: The size of the name buffer (should be at least 14 chars.)
5269 *
5270 */
f4e558ec 5271void drm_edid_get_monitor_name(const struct edid *edid, char *name, int bufsize)
59f7c0fa 5272{
2c54f87c 5273 int name_length = 0;
4d23f484 5274
59f7c0fa
JB		 5275 if (bufsize <= 0)
5276 return;
5277
2c54f87c
JN		 5278 if (edid) {
5279 char buf[13];
5280 struct drm_edid drm_edid = {
5281 .edid = edid,
5282 .size = edid_size(edid),
5283 };
5284
5285 name_length = min(get_monitor_name(&drm_edid, buf), bufsize - 1);
5286 memcpy(name, buf, name_length);
5287 }
5288
59f7c0fa
JB		 5289 name[name_length] = '\0';
5290}
5291EXPORT_SYMBOL(drm_edid_get_monitor_name);
5292
42750d39
JN		 5293static void clear_eld(struct drm_connector *connector)
5294{
5295 memset(connector->eld, 0, sizeof(connector->eld));
5296
5297 connector->latency_present[0] = false;
5298 connector->latency_present[1] = false;
5299 connector->video_latency[0] = 0;
5300 connector->audio_latency[0] = 0;
5301 connector->video_latency[1] = 0;
5302 connector->audio_latency[1] = 0;
5303}
5304
79436a1c 5305/*
76adaa34
WF		 5306 * drm_edid_to_eld - build ELD from EDID
5307 * @connector: connector corresponding to the HDMI/DP sink
a2f9790d 5308 * @drm_edid: EDID to parse
76adaa34 5309 *
db6cf833 5310 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
1d1c3665 5311 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
76adaa34 5312 */
f4e558ec 5313static void drm_edid_to_eld(struct drm_connector *connector,
a2f9790d 5314 const struct drm_edid *drm_edid)
76adaa34 5315{
58304630 5316 const struct drm_display_info *info = &connector->display_info;
37852141
JN		 5317 const struct cea_db *db;
5318 struct cea_db_iter iter;
76adaa34 5319 uint8_t *eld = connector->eld;
7c018782 5320 int total_sad_count = 0;
76adaa34 5321 int mnl;
76adaa34 5322
42750d39 5323 clear_eld(connector);
85c91580 5324
a2f9790d 5325 if (!drm_edid)
e9bd0b84
JN		 5326 return;
5327
2c54f87c 5328 mnl = get_monitor_name(drm_edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
f7da7785 5329 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]);
59f7c0fa 5330
58304630 5331 eld[DRM_ELD_CEA_EDID_VER_MNL] = info->cea_rev << DRM_ELD_CEA_EDID_VER_SHIFT;
f7da7785 5332 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
76adaa34 5333
f7da7785 5334 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
76adaa34 5335
a2f9790d
JN		 5336 eld[DRM_ELD_MANUFACTURER_NAME0] = drm_edid->edid->mfg_id[0];
5337 eld[DRM_ELD_MANUFACTURER_NAME1] = drm_edid->edid->mfg_id[1];
5338 eld[DRM_ELD_PRODUCT_CODE0] = drm_edid->edid->prod_code[0];
5339 eld[DRM_ELD_PRODUCT_CODE1] = drm_edid->edid->prod_code[1];
76adaa34 5340
5e87b2e5 5341 cea_db_iter_edid_begin(drm_edid, &iter);
37852141
JN		 5342 cea_db_iter_for_each(db, &iter) {
5343 const u8 *data = cea_db_data(db);
5344 int len = cea_db_payload_len(db);
deec222e 5345 int sad_count;
9e50b9d5 5346
37852141
JN		 5347 switch (cea_db_tag(db)) {
5348 case CTA_DB_AUDIO:
5349 /* Audio Data Block, contains SADs */
5350 sad_count = min(len / 3, 15 - total_sad_count);
5351 if (sad_count >= 1)
5352 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
5353 data, sad_count * 3);
5354 total_sad_count += sad_count;
5355 break;
5356 case CTA_DB_SPEAKER:
5357 /* Speaker Allocation Data Block */
5358 if (len >= 1)
5359 eld[DRM_ELD_SPEAKER] = data[0];
5360 break;
5361 case CTA_DB_VENDOR:
5362 /* HDMI Vendor-Specific Data Block */
5363 if (cea_db_is_hdmi_vsdb(db))
5364 drm_parse_hdmi_vsdb_audio(connector, (const u8 *)db);
5365 break;
5366 default:
5367 break;
76adaa34 5368 }
9e50b9d5 5369 }
37852141
JN		 5370 cea_db_iter_end(&iter);
5371
f7da7785 5372 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
76adaa34 5373
1d1c3665
JN		 5374 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5375 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5376 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
5377 else
5378 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
76adaa34 5379
938fd8aa
JN		 5380 eld[DRM_ELD_BASELINE_ELD_LEN] =
5381 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
5382
5383 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
7c018782 5384 drm_eld_size(eld), total_sad_count);
76adaa34 5385}
76adaa34 5386
bba4b647
JN		 5387static int _drm_edid_to_sad(const struct drm_edid *drm_edid,
5388 struct cea_sad **sads)
fe214163 5389{
b07debc2
JN		 5390 const struct cea_db *db;
5391 struct cea_db_iter iter;
fe214163 5392 int count = 0;
fe214163 5393
5e87b2e5 5394 cea_db_iter_edid_begin(drm_edid, &iter);
b07debc2 5395 cea_db_iter_for_each(db, &iter) {
9d72b7e2 5396 if (cea_db_tag(db) == CTA_DB_AUDIO) {
fe214163 5397 int j;
948de842 5398
b07debc2 5399 count = cea_db_payload_len(db) / 3; /* SAD is 3B */
fe214163
RM		 5400 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
5401 if (!*sads)
5402 return -ENOMEM;
5403 for (j = 0; j < count; j++) {
b07debc2 5404 const u8 *sad = &db->data[j * 3];
fe214163
RM		 5405
5406 (*sads)[j].format = (sad[0] & 0x78) >> 3;
5407 (*sads)[j].channels = sad[0] & 0x7;
5408 (*sads)[j].freq = sad[1] & 0x7F;
5409 (*sads)[j].byte2 = sad[2];
5410 }
5411 break;
5412 }
5413 }
b07debc2
JN		 5414 cea_db_iter_end(&iter);
5415
5416 DRM_DEBUG_KMS("Found %d Short Audio Descriptors\n", count);
fe214163
RM		 5417
5418 return count;
5419}
bba4b647
JN		 5420
5421/**
5422 * drm_edid_to_sad - extracts SADs from EDID
5423 * @edid: EDID to parse
5424 * @sads: pointer that will be set to the extracted SADs
5425 *
5426 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
5427 *
5428 * Note: The returned pointer needs to be freed using kfree().
5429 *
5430 * Return: The number of found SADs or negative number on error.
5431 */
5432int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads)
5433{
5434 struct drm_edid drm_edid;
5435
5436 return _drm_edid_to_sad(drm_edid_legacy_init(&drm_edid, edid), sads);
5437}
fe214163
RM		 5438EXPORT_SYMBOL(drm_edid_to_sad);
5439
02703451
JN		 5440static int _drm_edid_to_speaker_allocation(const struct drm_edid *drm_edid,
5441 u8 **sadb)
d105f476 5442{
ed317307
JN		 5443 const struct cea_db *db;
5444 struct cea_db_iter iter;
d105f476 5445 int count = 0;
d105f476 5446
5e87b2e5 5447 cea_db_iter_edid_begin(drm_edid, &iter);
ed317307
JN		 5448 cea_db_iter_for_each(db, &iter) {
5449 if (cea_db_tag(db) == CTA_DB_SPEAKER &&
5450 cea_db_payload_len(db) == 3) {
5451 *sadb = kmemdup(db->data, cea_db_payload_len(db),
5452 GFP_KERNEL);
5453 if (!*sadb)
5454 return -ENOMEM;
5455 count = cea_db_payload_len(db);
5456 break;
d105f476
AD		 5457 }
5458 }
ed317307
JN		 5459 cea_db_iter_end(&iter);
5460
5461 DRM_DEBUG_KMS("Found %d Speaker Allocation Data Blocks\n", count);
d105f476
AD		 5462
5463 return count;
5464}
02703451
JN		 5465
5466/**
5467 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
5468 * @edid: EDID to parse
5469 * @sadb: pointer to the speaker block
5470 *
5471 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
5472 *
5473 * Note: The returned pointer needs to be freed using kfree().
5474 *
5475 * Return: The number of found Speaker Allocation Blocks or negative number on
5476 * error.
5477 */
5478int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb)
5479{
5480 struct drm_edid drm_edid;
5481
5482 return _drm_edid_to_speaker_allocation(drm_edid_legacy_init(&drm_edid, edid),
5483 sadb);
5484}
d105f476
AD		 5485EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
5486
76adaa34 5487/**
db6cf833 5488 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
76adaa34
WF		 5489 * @connector: connector associated with the HDMI/DP sink
5490 * @mode: the display mode
db6cf833
TR		 5491 *
5492 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
5493 * the sink doesn't support audio or video.
76adaa34
WF		 5494 */
5495int drm_av_sync_delay(struct drm_connector *connector,
3a818d35 5496 const struct drm_display_mode *mode)
76adaa34
WF		 5497{
5498 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
5499 int a, v;
5500
5501 if (!connector->latency_present[0])
5502 return 0;
5503 if (!connector->latency_present[1])
5504 i = 0;
5505
5506 a = connector->audio_latency[i];
5507 v = connector->video_latency[i];
5508
5509 /*
5510 * HDMI/DP sink doesn't support audio or video?
5511 */
5512 if (a == 255 || v == 255)
5513 return 0;
5514
5515 /*
5516 * Convert raw EDID values to millisecond.
5517 * Treat unknown latency as 0ms.
5518 */
5519 if (a)
5520 a = min(2 * (a - 1), 500);
5521 if (v)
5522 v = min(2 * (v - 1), 500);
5523
5524 return max(v - a, 0);
5525}
5526EXPORT_SYMBOL(drm_av_sync_delay);
5527
3176d092 5528static bool _drm_detect_hdmi_monitor(const struct drm_edid *drm_edid)
8fe9790d 5529{
4ce08703
JN		 5530 const struct cea_db *db;
5531 struct cea_db_iter iter;
5532 bool hdmi = false;
f23c20c8
ML		 5533
5534 /*
5535 * Because HDMI identifier is in Vendor Specific Block,
5536 * search it from all data blocks of CEA extension.
5537 */
5e87b2e5 5538 cea_db_iter_edid_begin(drm_edid, &iter);
4ce08703
JN		 5539 cea_db_iter_for_each(db, &iter) {
5540 if (cea_db_is_hdmi_vsdb(db)) {
5541 hdmi = true;
5542 break;
5543 }
f23c20c8 5544 }
4ce08703 5545 cea_db_iter_end(&iter);
f23c20c8 5546
4ce08703 5547 return hdmi;
f23c20c8 5548}
3176d092
JN		 5549
5550/**
5551 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
5552 * @edid: monitor EDID information
5553 *
5554 * Parse the CEA extension according to CEA-861-B.
5555 *
5556 * Drivers that have added the modes parsed from EDID to drm_display_info
5557 * should use &drm_display_info.is_hdmi instead of calling this function.
5558 *
5559 * Return: True if the monitor is HDMI, false if not or unknown.
5560 */
5561bool drm_detect_hdmi_monitor(const struct edid *edid)
5562{
5563 struct drm_edid drm_edid;
5564
5565 return _drm_detect_hdmi_monitor(drm_edid_legacy_init(&drm_edid, edid));
5566}
f23c20c8
ML		 5567EXPORT_SYMBOL(drm_detect_hdmi_monitor);
5568
0c057877 5569static bool _drm_detect_monitor_audio(const struct drm_edid *drm_edid)
8fe9790d 5570{
705bec3e 5571 struct drm_edid_iter edid_iter;
9975af04
JN		 5572 const struct cea_db *db;
5573 struct cea_db_iter iter;
43d16d84 5574 const u8 *edid_ext;
8fe9790d 5575 bool has_audio = false;
8fe9790d 5576
bbded689 5577 drm_edid_iter_begin(drm_edid, &edid_iter);
705bec3e
JN		 5578 drm_edid_iter_for_each(edid_ext, &edid_iter) {
5579 if (edid_ext[0] == CEA_EXT) {
5580 has_audio = edid_ext[3] & EDID_BASIC_AUDIO;
5581 if (has_audio)
5582 break;
5583 }
5584 }
5585 drm_edid_iter_end(&edid_iter);
8fe9790d
ZW		 5586
5587 if (has_audio) {
5588 DRM_DEBUG_KMS("Monitor has basic audio support\n");
5589 goto end;
5590 }
5591
5e87b2e5 5592 cea_db_iter_edid_begin(drm_edid, &iter);
9975af04
JN		 5593 cea_db_iter_for_each(db, &iter) {
5594 if (cea_db_tag(db) == CTA_DB_AUDIO) {
5595 const u8 *data = cea_db_data(db);
5596 int i;
8fe9790d 5597
9975af04 5598 for (i = 0; i < cea_db_payload_len(db); i += 3)
8fe9790d 5599 DRM_DEBUG_KMS("CEA audio format %d\n",
9975af04
JN		 5600 (data[i] >> 3) & 0xf);
5601 has_audio = true;
5602 break;
8fe9790d
ZW		 5603 }
5604 }
9975af04
JN		 5605 cea_db_iter_end(&iter);
5606
8fe9790d
ZW		 5607end:
5608 return has_audio;
5609}
0c057877
JN		 5610
5611/**
5612 * drm_detect_monitor_audio - check monitor audio capability
5613 * @edid: EDID block to scan
5614 *
5615 * Monitor should have CEA extension block.
5616 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
5617 * audio' only. If there is any audio extension block and supported
5618 * audio format, assume at least 'basic audio' support, even if 'basic
5619 * audio' is not defined in EDID.
5620 *
5621 * Return: True if the monitor supports audio, false otherwise.
5622 */
5623bool drm_detect_monitor_audio(const struct edid *edid)
5624{
5625 struct drm_edid drm_edid;
5626
5627 return _drm_detect_monitor_audio(drm_edid_legacy_init(&drm_edid, edid));
5628}
8fe9790d
ZW		 5629EXPORT_SYMBOL(drm_detect_monitor_audio);
5630
b1edd6a6 5631
c8127cf0
VS		 5632/**
5633 * drm_default_rgb_quant_range - default RGB quantization range
5634 * @mode: display mode
5635 *
5636 * Determine the default RGB quantization range for the mode,
5637 * as specified in CEA-861.
5638 *
5639 * Return: The default RGB quantization range for the mode
5640 */
5641enum hdmi_quantization_range
5642drm_default_rgb_quant_range(const struct drm_display_mode *mode)
5643{
5644 /* All CEA modes other than VIC 1 use limited quantization range. */
5645 return drm_match_cea_mode(mode) > 1 ?
5646 HDMI_QUANTIZATION_RANGE_LIMITED :
5647 HDMI_QUANTIZATION_RANGE_FULL;
5648}
5649EXPORT_SYMBOL(drm_default_rgb_quant_range);
5650
1581b2df
VS		 5651static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
5652{
5653 struct drm_display_info *info = &connector->display_info;
5654
5655 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]);
5656
5657 if (db[2] & EDID_CEA_VCDB_QS)
5658 info->rgb_quant_range_selectable = true;
5659}
5660
4499d488
SS		 5661static
5662void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane)
5663{
5664 switch (max_frl_rate) {
5665 case 1:
5666 *max_lanes = 3;
5667 *max_rate_per_lane = 3;
5668 break;
5669 case 2:
5670 *max_lanes = 3;
5671 *max_rate_per_lane = 6;
5672 break;
5673 case 3:
5674 *max_lanes = 4;
5675 *max_rate_per_lane = 6;
5676 break;
5677 case 4:
5678 *max_lanes = 4;
5679 *max_rate_per_lane = 8;
5680 break;
5681 case 5:
5682 *max_lanes = 4;
5683 *max_rate_per_lane = 10;
5684 break;
5685 case 6:
5686 *max_lanes = 4;
5687 *max_rate_per_lane = 12;
5688 break;
5689 case 0:
5690 default:
5691 *max_lanes = 0;
5692 *max_rate_per_lane = 0;
5693 }
5694}
5695
e6a9a2c3
SS		 5696static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
5697 const u8 *db)
5698{
5699 u8 dc_mask;
5700 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
5701
5702 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
9068e02f 5703 hdmi->y420_dc_modes = dc_mask;
e6a9a2c3
SS		 5704}
5705
d8cb49d2
JN		 5706/* Sink Capability Data Structure */
5707static void drm_parse_hdmi_forum_scds(struct drm_connector *connector,
5708 const u8 *hf_scds)
afa1c763 5709{
62c58af3
SS		 5710 struct drm_display_info *display = &connector->display_info;
5711 struct drm_hdmi_info *hdmi = &display->hdmi;
afa1c763 5712
f1781e9b
VS		 5713 display->has_hdmi_infoframe = true;
5714
d8cb49d2 5715 if (hf_scds[6] & 0x80) {
afa1c763 5716 hdmi->scdc.supported = true;
d8cb49d2 5717 if (hf_scds[6] & 0x40)
afa1c763
SS		 5718 hdmi->scdc.read_request = true;
5719 }
62c58af3
SS		 5720
5721 /*
5722 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
5723 * And as per the spec, three factors confirm this:
5724 * * Availability of a HF-VSDB block in EDID (check)
5725 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
5726 * * SCDC support available (let's check)
5727 * Lets check it out.
5728 */
5729
d8cb49d2 5730 if (hf_scds[5]) {
62c58af3 5731 /* max clock is 5000 KHz times block value */
d8cb49d2 5732 u32 max_tmds_clock = hf_scds[5] * 5000;
62c58af3
SS		 5733 struct drm_scdc *scdc = &hdmi->scdc;
5734
5735 if (max_tmds_clock > 340000) {
5736 display->max_tmds_clock = max_tmds_clock;
5737 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
5738 display->max_tmds_clock);
5739 }
5740
5741 if (scdc->supported) {
5742 scdc->scrambling.supported = true;
5743
dbe2d2bf 5744 /* Few sinks support scrambling for clocks < 340M */
d8cb49d2 5745 if ((hf_scds[6] & 0x8))
62c58af3
SS		 5746 scdc->scrambling.low_rates = true;
5747 }
5748 }
e6a9a2c3 5749
d8cb49d2 5750 if (hf_scds[7]) {
4499d488 5751 u8 max_frl_rate;
76ee7b90
AN		 5752 u8 dsc_max_frl_rate;
5753 u8 dsc_max_slices;
5754 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap;
4499d488
SS		 5755
5756 DRM_DEBUG_KMS("hdmi_21 sink detected. parsing edid\n");
d8cb49d2 5757 max_frl_rate = (hf_scds[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4;
4499d488
SS		 5758 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes,
5759 &hdmi->max_frl_rate_per_lane);
d8cb49d2 5760 hdmi_dsc->v_1p2 = hf_scds[11] & DRM_EDID_DSC_1P2;
76ee7b90
AN		 5761
5762 if (hdmi_dsc->v_1p2) {
d8cb49d2
JN		 5763 hdmi_dsc->native_420 = hf_scds[11] & DRM_EDID_DSC_NATIVE_420;
5764 hdmi_dsc->all_bpp = hf_scds[11] & DRM_EDID_DSC_ALL_BPP;
76ee7b90 5765
d8cb49d2 5766 if (hf_scds[11] & DRM_EDID_DSC_16BPC)
76ee7b90 5767 hdmi_dsc->bpc_supported = 16;
d8cb49d2 5768 else if (hf_scds[11] & DRM_EDID_DSC_12BPC)
76ee7b90 5769 hdmi_dsc->bpc_supported = 12;
d8cb49d2 5770 else if (hf_scds[11] & DRM_EDID_DSC_10BPC)
76ee7b90
AN		 5771 hdmi_dsc->bpc_supported = 10;
5772 else
5773 hdmi_dsc->bpc_supported = 0;
5774
d8cb49d2 5775 dsc_max_frl_rate = (hf_scds[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4;
76ee7b90
AN		 5776 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes,
5777 &hdmi_dsc->max_frl_rate_per_lane);
d8cb49d2 5778 hdmi_dsc->total_chunk_kbytes = hf_scds[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES;
76ee7b90 5779
d8cb49d2 5780 dsc_max_slices = hf_scds[12] & DRM_EDID_DSC_MAX_SLICES;
76ee7b90
AN		 5781 switch (dsc_max_slices) {
5782 case 1:
5783 hdmi_dsc->max_slices = 1;
5784 hdmi_dsc->clk_per_slice = 340;
5785 break;
5786 case 2:
5787 hdmi_dsc->max_slices = 2;
5788 hdmi_dsc->clk_per_slice = 340;
5789 break;
5790 case 3:
5791 hdmi_dsc->max_slices = 4;
5792 hdmi_dsc->clk_per_slice = 340;
5793 break;
5794 case 4:
5795 hdmi_dsc->max_slices = 8;
5796 hdmi_dsc->clk_per_slice = 340;
5797 break;
5798 case 5:
5799 hdmi_dsc->max_slices = 8;
5800 hdmi_dsc->clk_per_slice = 400;
5801 break;
5802 case 6:
5803 hdmi_dsc->max_slices = 12;
5804 hdmi_dsc->clk_per_slice = 400;
5805 break;
5806 case 7:
5807 hdmi_dsc->max_slices = 16;
5808 hdmi_dsc->clk_per_slice = 400;
5809 break;
5810 case 0:
5811 default:
5812 hdmi_dsc->max_slices = 0;
5813 hdmi_dsc->clk_per_slice = 0;
5814 }
5815 }
4499d488
SS		 5816 }
5817
d8cb49d2 5818 drm_parse_ycbcr420_deep_color_info(connector, hf_scds);
afa1c763
SS		 5819}
5820
1cea146a
VS		 5821static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
5822 const u8 *hdmi)
d0c94692 5823{
1826750f 5824 struct drm_display_info *info = &connector->display_info;
d0c94692
MK		 5825 unsigned int dc_bpc = 0;
5826
1cea146a
VS		 5827 /* HDMI supports at least 8 bpc */
5828 info->bpc = 8;
d0c94692 5829
1cea146a
VS		 5830 if (cea_db_payload_len(hdmi) < 6)
5831 return;
5832
5833 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
5834 dc_bpc = 10;
4adc33f3 5835 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_30;
1cea146a
VS		 5836 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
5837 connector->name);
5838 }
5839
5840 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
5841 dc_bpc = 12;
4adc33f3 5842 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_36;
1cea146a
VS		 5843 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
5844 connector->name);
5845 }
5846
5847 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
5848 dc_bpc = 16;
4adc33f3 5849 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_48;
1cea146a
VS		 5850 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
5851 connector->name);
5852 }
5853
5854 if (dc_bpc == 0) {
5855 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
5856 connector->name);
5857 return;
5858 }
5859
5860 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
5861 connector->name, dc_bpc);
5862 info->bpc = dc_bpc;
d0c94692 5863
1cea146a
VS		 5864 /* YCRCB444 is optional according to spec. */
5865 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
4adc33f3 5866 info->edid_hdmi_ycbcr444_dc_modes = info->edid_hdmi_rgb444_dc_modes;
1cea146a
VS		 5867 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
5868 connector->name);
5869 }
d0c94692 5870
1cea146a
VS		 5871 /*
5872 * Spec says that if any deep color mode is supported at all,
5873 * then deep color 36 bit must be supported.
5874 */
5875 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
5876 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
5877 connector->name);
5878 }
5879}
d0c94692 5880
23ebf8b9
VS		 5881static void
5882drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
5883{
5884 struct drm_display_info *info = &connector->display_info;
5885 u8 len = cea_db_payload_len(db);
5886
a92d083d
LP		 5887 info->is_hdmi = true;
5888
23ebf8b9
VS		 5889 if (len >= 6)
5890 info->dvi_dual = db[6] & 1;
5891 if (len >= 7)
5892 info->max_tmds_clock = db[7] * 5000;
5893
5894 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
5895 "max TMDS clock %d kHz\n",
5896 info->dvi_dual,
5897 info->max_tmds_clock);
5898
5899 drm_parse_hdmi_deep_color_info(connector, db);
5900}
5901
2869f599
PZ		 5902/*
5903 * See EDID extension for head-mounted and specialized monitors, specified at:
5904 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/specialized-monitors-edid-extension
5905 */
5906static void drm_parse_microsoft_vsdb(struct drm_connector *connector,
5907 const u8 *db)
5908{
5909 struct drm_display_info *info = &connector->display_info;
5910 u8 version = db[4];
5911 bool desktop_usage = db[5] & BIT(6);
5912
5913 /* Version 1 and 2 for HMDs, version 3 flags desktop usage explicitly */
5914 if (version == 1 || version == 2 || (version == 3 && !desktop_usage))
5915 info->non_desktop = true;
5916
5917 drm_dbg_kms(connector->dev, "HMD or specialized display VSDB version %u: 0x%02x\n",
5918 version, db[5]);
5919}
5920
1cea146a 5921static void drm_parse_cea_ext(struct drm_connector *connector,
e42192b4 5922 const struct drm_edid *drm_edid)
1cea146a
VS		 5923{
5924 struct drm_display_info *info = &connector->display_info;
8db73897 5925 struct drm_edid_iter edid_iter;
dfc03125
JN		 5926 const struct cea_db *db;
5927 struct cea_db_iter iter;
1cea146a 5928 const u8 *edid_ext;
d0c94692 5929
bbded689 5930 drm_edid_iter_begin(drm_edid, &edid_iter);
8db73897
JN		 5931 drm_edid_iter_for_each(edid_ext, &edid_iter) {
5932 if (edid_ext[0] != CEA_EXT)
5933 continue;
d0c94692 5934
8db73897
JN		 5935 if (!info->cea_rev)
5936 info->cea_rev = edid_ext[1];
d0c94692 5937
8db73897
JN		 5938 if (info->cea_rev != edid_ext[1])
5939 DRM_DEBUG_KMS("CEA extension version mismatch %u != %u\n",
5940 info->cea_rev, edid_ext[1]);
7344bad7 5941
8db73897
JN		 5942 /* The existence of a CTA extension should imply RGB support */
5943 info->color_formats = DRM_COLOR_FORMAT_RGB444;
7344bad7
JN		 5944 if (edid_ext[3] & EDID_CEA_YCRCB444)
5945 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
5946 if (edid_ext[3] & EDID_CEA_YCRCB422)
5947 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
5948 }
8db73897 5949 drm_edid_iter_end(&edid_iter);
1cea146a 5950
5e87b2e5 5951 cea_db_iter_edid_begin(drm_edid, &iter);
dfc03125
JN		 5952 cea_db_iter_for_each(db, &iter) {
5953 /* FIXME: convert parsers to use struct cea_db */
5954 const u8 *data = (const u8 *)db;
1cea146a 5955
23ebf8b9 5956 if (cea_db_is_hdmi_vsdb(db))
dfc03125 5957 drm_parse_hdmi_vsdb_video(connector, data);
be982415
JN		 5958 else if (cea_db_is_hdmi_forum_vsdb(db) ||
5959 cea_db_is_hdmi_forum_scdb(db))
dfc03125 5960 drm_parse_hdmi_forum_scds(connector, data);
be982415 5961 else if (cea_db_is_microsoft_vsdb(db))
dfc03125 5962 drm_parse_microsoft_vsdb(connector, data);
be982415 5963 else if (cea_db_is_y420cmdb(db))
dfc03125 5964 drm_parse_y420cmdb_bitmap(connector, data);
be982415 5965 else if (cea_db_is_vcdb(db))
dfc03125 5966 drm_parse_vcdb(connector, data);
be982415 5967 else if (cea_db_is_hdmi_hdr_metadata_block(db))
dfc03125 5968 drm_parse_hdr_metadata_block(connector, data);
1cea146a 5969 }
dfc03125 5970 cea_db_iter_end(&iter);
d0c94692
MK		 5971}
5972
a1d11d1e 5973static
4194442d 5974void get_monitor_range(const struct detailed_timing *timing,
a1d11d1e
MN		 5975 void *info_monitor_range)
5976{
5977 struct drm_monitor_range_info *monitor_range = info_monitor_range;
5978 const struct detailed_non_pixel *data = &timing->data.other_data;
5979 const struct detailed_data_monitor_range *range = &data->data.range;
5980
e379814b 5981 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
a1d11d1e
MN		 5982 return;
5983
5984 /*
5985 * Check for flag range limits only. If flag == 1 then
5986 * no additional timing information provided.
5987 * Default GTF, GTF Secondary curve and CVT are not
5988 * supported
5989 */
5990 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG)
5991 return;
5992
5993 monitor_range->min_vfreq = range->min_vfreq;
5994 monitor_range->max_vfreq = range->max_vfreq;
5995}
5996
e42192b4
JN		 5997static void drm_get_monitor_range(struct drm_connector *connector,
5998 const struct drm_edid *drm_edid)
a1d11d1e
MN		 5999{
6000 struct drm_display_info *info = &connector->display_info;
6001
d0edd3c1 6002 if (!version_greater(drm_edid, 1, 1))
a1d11d1e
MN		 6003 return;
6004
45aa2336 6005 drm_for_each_detailed_block(drm_edid, get_monitor_range,
a1d11d1e
MN		 6006 &info->monitor_range);
6007
6008 DRM_DEBUG_KMS("Supported Monitor Refresh rate range is %d Hz - %d Hz\n",
6009 info->monitor_range.min_vfreq,
6010 info->monitor_range.max_vfreq);
6011}
6012
18a9cbbe
JN		 6013static void drm_parse_vesa_mso_data(struct drm_connector *connector,
6014 const struct displayid_block *block)
6015{
6016 struct displayid_vesa_vendor_specific_block *vesa =
6017 (struct displayid_vesa_vendor_specific_block *)block;
6018 struct drm_display_info *info = &connector->display_info;
6019
6020 if (block->num_bytes < 3) {
6021 drm_dbg_kms(connector->dev, "Unexpected vendor block size %u\n",
6022 block->num_bytes);
6023 return;
6024 }
6025
6026 if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI)
6027 return;
6028
6029 if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
6030 drm_dbg_kms(connector->dev, "Unexpected VESA vendor block size\n");
6031 return;
6032 }
6033
6034 switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
6035 default:
6036 drm_dbg_kms(connector->dev, "Reserved MSO mode value\n");
6037 fallthrough;
6038 case 0:
6039 info->mso_stream_count = 0;
6040 break;
6041 case 1:
6042 info->mso_stream_count = 2; /* 2 or 4 links */
6043 break;
6044 case 2:
6045 info->mso_stream_count = 4; /* 4 links */
6046 break;
6047 }
6048
6049 if (!info->mso_stream_count) {
6050 info->mso_pixel_overlap = 0;
6051 return;
6052 }
6053
6054 info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
6055 if (info->mso_pixel_overlap > 8) {
6056 drm_dbg_kms(connector->dev, "Reserved MSO pixel overlap value %u\n",
6057 info->mso_pixel_overlap);
6058 info->mso_pixel_overlap = 8;
6059 }
6060
6061 drm_dbg_kms(connector->dev, "MSO stream count %u, pixel overlap %u\n",
6062 info->mso_stream_count, info->mso_pixel_overlap);
6063}
6064
e42192b4
JN		 6065static void drm_update_mso(struct drm_connector *connector,
6066 const struct drm_edid *drm_edid)
18a9cbbe
JN		 6067{
6068 const struct displayid_block *block;
6069 struct displayid_iter iter;
6070
d9ba1b4c 6071 displayid_iter_edid_begin(drm_edid, &iter);
18a9cbbe
JN		 6072 displayid_iter_for_each(block, &iter) {
6073 if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC)
6074 drm_parse_vesa_mso_data(connector, block);
6075 }
6076 displayid_iter_end(&iter);
6077}
6078
170178fe
KP		 6079/* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
6080 * all of the values which would have been set from EDID
6081 */
02b16fbc 6082static void drm_reset_display_info(struct drm_connector *connector)
170178fe
KP		 6083{
6084 struct drm_display_info *info = &connector->display_info;
6085
6086 info->width_mm = 0;
6087 info->height_mm = 0;
6088
6089 info->bpc = 0;
6090 info->color_formats = 0;
6091 info->cea_rev = 0;
6092 info->max_tmds_clock = 0;
6093 info->dvi_dual = false;
a92d083d 6094 info->is_hdmi = false;
170178fe 6095 info->has_hdmi_infoframe = false;
1581b2df 6096 info->rgb_quant_range_selectable = false;
1f6b8eef 6097 memset(&info->hdmi, 0, sizeof(info->hdmi));
170178fe 6098
70c0b80d
MR		 6099 info->edid_hdmi_rgb444_dc_modes = 0;
6100 info->edid_hdmi_ycbcr444_dc_modes = 0;
6101
170178fe 6102 info->non_desktop = 0;
a1d11d1e 6103 memset(&info->monitor_range, 0, sizeof(info->monitor_range));
18a9cbbe
JN		 6104
6105 info->mso_stream_count = 0;
6106 info->mso_pixel_overlap = 0;
170178fe 6107}
170178fe 6108
e42192b4
JN		 6109static u32 update_display_info(struct drm_connector *connector,
6110 const struct drm_edid *drm_edid)
3b11228b 6111{
1826750f 6112 struct drm_display_info *info = &connector->display_info;
e42192b4 6113 const struct edid *edid = drm_edid->edid;
ebec9a7b 6114
e42192b4 6115 u32 quirks = edid_get_quirks(drm_edid);
170178fe 6116
1f6b8eef
VS		 6117 drm_reset_display_info(connector);
6118
3b11228b
JB		 6119 info->width_mm = edid->width_cm * 10;
6120 info->height_mm = edid->height_cm * 10;
6121
e42192b4 6122 drm_get_monitor_range(connector, drm_edid);
a1d11d1e 6123
a988bc72 6124 if (edid->revision < 3)
ce99534e 6125 goto out;
3b11228b
JB		 6126
6127 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
ce99534e 6128 goto out;
3b11228b 6129
ecbd4912 6130 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
e42192b4 6131 drm_parse_cea_ext(connector, drm_edid);
d0c94692 6132
210a021d
MK		 6133 /*
6134 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
6135 *
6136 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
6137 * tells us to assume 8 bpc color depth if the EDID doesn't have
6138 * extensions which tell otherwise.
6139 */
3bde449f
VS		 6140 if (info->bpc == 0 && edid->revision == 3 &&
6141 edid->input & DRM_EDID_DIGITAL_DFP_1_X) {
210a021d
MK		 6142 info->bpc = 8;
6143 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
6144 connector->name, info->bpc);
6145 }
6146
a988bc72
LPC		 6147 /* Only defined for 1.4 with digital displays */
6148 if (edid->revision < 4)
ce99534e 6149 goto out;
a988bc72 6150
3b11228b
JB		 6151 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
6152 case DRM_EDID_DIGITAL_DEPTH_6:
6153 info->bpc = 6;
6154 break;
6155 case DRM_EDID_DIGITAL_DEPTH_8:
6156 info->bpc = 8;
6157 break;
6158 case DRM_EDID_DIGITAL_DEPTH_10:
6159 info->bpc = 10;
6160 break;
6161 case DRM_EDID_DIGITAL_DEPTH_12:
6162 info->bpc = 12;
6163 break;
6164 case DRM_EDID_DIGITAL_DEPTH_14:
6165 info->bpc = 14;
6166 break;
6167 case DRM_EDID_DIGITAL_DEPTH_16:
6168 info->bpc = 16;
6169 break;
6170 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
6171 default:
6172 info->bpc = 0;
6173 break;
6174 }
da05a5a7 6175
d0c94692 6176 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
25933820 6177 connector->name, info->bpc);
d0c94692 6178
ee58808d 6179 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
c03d0b52 6180 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
ee58808d 6181 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
c03d0b52 6182 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
18a9cbbe 6183
e42192b4 6184 drm_update_mso(connector, drm_edid);
18a9cbbe 6185
ce99534e
JN		 6186out:
6187 if (quirks & EDID_QUIRK_NON_DESKTOP) {
6188 drm_dbg_kms(connector->dev, "Non-desktop display%s\n",
6189 info->non_desktop ? " (redundant quirk)" : "");
6190 info->non_desktop = true;
6191 }
6192
170178fe 6193 return quirks;
3b11228b
JB		 6194}
6195
a39ed680 6196static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
80ecb5d7
YB		 6197 struct displayid_detailed_timings_1 *timings,
6198 bool type_7)
a39ed680
DA		 6199{
6200 struct drm_display_mode *mode;
6201 unsigned pixel_clock = (timings->pixel_clock[0] |
6202 (timings->pixel_clock[1] << 8) |
6292b8ef 6203 (timings->pixel_clock[2] << 16)) + 1;
a39ed680
DA		 6204 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
6205 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
6206 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
6207 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
6208 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
6209 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
6210 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
6211 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
6212 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
6213 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
948de842 6214
a39ed680
DA		 6215 mode = drm_mode_create(dev);
6216 if (!mode)
6217 return NULL;
6218
80ecb5d7
YB		 6219 /* resolution is kHz for type VII, and 10 kHz for type I */
6220 mode->clock = type_7 ? pixel_clock : pixel_clock * 10;
a39ed680
DA		 6221 mode->hdisplay = hactive;
6222 mode->hsync_start = mode->hdisplay + hsync;
6223 mode->hsync_end = mode->hsync_start + hsync_width;
6224 mode->htotal = mode->hdisplay + hblank;
6225
6226 mode->vdisplay = vactive;
6227 mode->vsync_start = mode->vdisplay + vsync;
6228 mode->vsync_end = mode->vsync_start + vsync_width;
6229 mode->vtotal = mode->vdisplay + vblank;
6230
6231 mode->flags = 0;
6232 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
6233 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
6234 mode->type = DRM_MODE_TYPE_DRIVER;
6235
6236 if (timings->flags & 0x80)
6237 mode->type |= DRM_MODE_TYPE_PREFERRED;
a39ed680
DA		 6238 drm_mode_set_name(mode);
6239
6240 return mode;
6241}
6242
6243static int add_displayid_detailed_1_modes(struct drm_connector *connector,
43d16d84 6244 const struct displayid_block *block)
a39ed680
DA		 6245{
6246 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
6247 int i;
6248 int num_timings;
6249 struct drm_display_mode *newmode;
6250 int num_modes = 0;
80ecb5d7 6251 bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING;
a39ed680
DA		 6252 /* blocks must be multiple of 20 bytes length */
6253 if (block->num_bytes % 20)
6254 return 0;
6255
6256 num_timings = block->num_bytes / 20;
6257 for (i = 0; i < num_timings; i++) {
6258 struct displayid_detailed_timings_1 *timings = &det->timings[i];
6259
80ecb5d7 6260 newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7);
a39ed680
DA		 6261 if (!newmode)
6262 continue;
6263
6264 drm_mode_probed_add(connector, newmode);
6265 num_modes++;
6266 }
6267 return num_modes;
6268}
6269
6270static int add_displayid_detailed_modes(struct drm_connector *connector,
40f71f5b 6271 const struct drm_edid *drm_edid)
a39ed680 6272{
43d16d84 6273 const struct displayid_block *block;
5ef88dc5 6274 struct displayid_iter iter;
a39ed680
DA		 6275 int num_modes = 0;
6276
d9ba1b4c 6277 displayid_iter_edid_begin(drm_edid, &iter);
5ef88dc5 6278 displayid_iter_for_each(block, &iter) {
80ecb5d7
YB		 6279 if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING ||
6280 block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING)
5ef88dc5 6281 num_modes += add_displayid_detailed_1_modes(connector, block);
a39ed680 6282 }
5ef88dc5 6283 displayid_iter_end(&iter);
7f261afd 6284
a39ed680
DA		 6285 return num_modes;
6286}
6287
b71c0aaa
JN		 6288static int _drm_edid_connector_update(struct drm_connector *connector,
6289 const struct drm_edid *drm_edid)
f453ba04
DA		 6290{
6291 int num_modes = 0;
6292 u32 quirks;
6293
22a27e05 6294 if (!drm_edid) {
d10f7117 6295 drm_reset_display_info(connector);
c945b8c1 6296 clear_eld(connector);
f453ba04
DA		 6297 return 0;
6298 }
f453ba04 6299
0f0f8708
SS		 6300 /*
6301 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
6302 * To avoid multiple parsing of same block, lets parse that map
6303 * from sink info, before parsing CEA modes.
6304 */
e42192b4 6305 quirks = update_display_info(connector, drm_edid);
0f0f8708 6306
e42192b4 6307 /* Depends on info->cea_rev set by update_display_info() above */
a2f9790d 6308 drm_edid_to_eld(connector, drm_edid);
58304630 6309
c867df70
AJ		 6310 /*
6311 * EDID spec says modes should be preferred in this order:
6312 * - preferred detailed mode
6313 * - other detailed modes from base block
6314 * - detailed modes from extension blocks
6315 * - CVT 3-byte code modes
6316 * - standard timing codes
6317 * - established timing codes
6318 * - modes inferred from GTF or CVT range information
6319 *
13931579 6320 * We get this pretty much right.
c867df70
AJ		 6321 *
6322 * XXX order for additional mode types in extension blocks?
6323 */
40f71f5b
JN		 6324 num_modes += add_detailed_modes(connector, drm_edid, quirks);
6325 num_modes += add_cvt_modes(connector, drm_edid);
6326 num_modes += add_standard_modes(connector, drm_edid);
6327 num_modes += add_established_modes(connector, drm_edid);
6328 num_modes += add_cea_modes(connector, drm_edid);
6329 num_modes += add_alternate_cea_modes(connector, drm_edid);
6330 num_modes += add_displayid_detailed_modes(connector, drm_edid);
6331 if (drm_edid->edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
6332 num_modes += add_inferred_modes(connector, drm_edid);
f453ba04
DA		 6333
6334 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
6335 edid_fixup_preferred(connector, quirks);
6336
e10aec65
MK		 6337 if (quirks & EDID_QUIRK_FORCE_6BPC)
6338 connector->display_info.bpc = 6;
6339
49d45a31
RM		 6340 if (quirks & EDID_QUIRK_FORCE_8BPC)
6341 connector->display_info.bpc = 8;
6342
e345da82
MK		 6343 if (quirks & EDID_QUIRK_FORCE_10BPC)
6344 connector->display_info.bpc = 10;
6345
bc5b9641
MK		 6346 if (quirks & EDID_QUIRK_FORCE_12BPC)
6347 connector->display_info.bpc = 12;
6348
f453ba04
DA		 6349 return num_modes;
6350}
f40ab034 6351
a819451e
JN		 6352static void _drm_update_tile_info(struct drm_connector *connector,
6353 const struct drm_edid *drm_edid);
02b16fbc 6354
b71c0aaa 6355static int _drm_edid_connector_property_update(struct drm_connector *connector,
a819451e 6356 const struct drm_edid *drm_edid)
02b16fbc
JN		 6357{
6358 struct drm_device *dev = connector->dev;
02b16fbc 6359 int ret;
02b16fbc 6360
02b16fbc 6361 if (connector->edid_blob_ptr) {
a819451e
JN		 6362 const struct edid *old_edid = connector->edid_blob_ptr->data;
6363
02b16fbc 6364 if (old_edid) {
a819451e 6365 if (!drm_edid_are_equal(drm_edid ? drm_edid->edid : NULL, old_edid)) {
f999b37e
JN		 6366 connector->epoch_counter++;
6367 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID changed, epoch counter %llu\n",
6368 connector->base.id, connector->name,
6369 connector->epoch_counter);
02b16fbc
JN		 6370 }
6371 }
6372 }
6373
02b16fbc
JN		 6374 ret = drm_property_replace_global_blob(dev,
6375 &connector->edid_blob_ptr,
a819451e
JN		 6376 drm_edid ? drm_edid->size : 0,
6377 drm_edid ? drm_edid->edid : NULL,
02b16fbc
JN		 6378 &connector->base,
6379 dev->mode_config.edid_property);
f999b37e
JN		 6380 if (ret) {
6381 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID property update failed (%d)\n",
6382 connector->base.id, connector->name, ret);
6383 goto out;
6384 }
6385
6386 ret = drm_object_property_set_value(&connector->base,
6387 dev->mode_config.non_desktop_property,
6388 connector->display_info.non_desktop);
6389 if (ret) {
6390 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Non-desktop property update failed (%d)\n",
6391 connector->base.id, connector->name, ret);
6392 goto out;
6393 }
6394
6395 ret = drm_connector_set_tile_property(connector);
6396 if (ret) {
6397 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Tile property update failed (%d)\n",
6398 connector->base.id, connector->name, ret);
6399 goto out;
6400 }
6401
6402out:
6403 return ret;
02b16fbc 6404}
a819451e 6405
b71c0aaa
JN		 6406/**
6407 * drm_edid_connector_update - Update connector information from EDID
6408 * @connector: Connector
6409 * @drm_edid: EDID
6410 *
6411 * Update the connector mode list, display info, ELD, HDR metadata, relevant
6412 * properties, etc. from the passed in EDID.
6413 *
6414 * If EDID is NULL, reset the information.
6415 *
6416 * Return: The number of modes added or 0 if we couldn't find any.
6417 */
6418int drm_edid_connector_update(struct drm_connector *connector,
6419 const struct drm_edid *drm_edid)
6420{
6421 int count;
6422
6423 /*
6424 * FIXME: Reconcile the differences in override_edid handling between
6425 * this and drm_connector_update_edid_property().
6426 *
6427 * If override_edid is set, and the EDID passed in here originates from
6428 * drm_edid_read() and friends, it will be the override EDID, and there
6429 * are no issues. drm_connector_update_edid_property() ignoring requests
6430 * to set the EDID dates back to a time when override EDID was not
6431 * handled at the low level EDID read.
6432 *
6433 * The only way the EDID passed in here can be different from the
6434 * override EDID is when a driver passes in an EDID that does *not*
6435 * originate from drm_edid_read() and friends, or passes in a stale
6436 * cached version. This, in turn, is a question of when an override EDID
6437 * set via debugfs should take effect.
6438 */
6439
6440 count = _drm_edid_connector_update(connector, drm_edid);
6441
6442 _drm_update_tile_info(connector, drm_edid);
6443
6444 /* Note: Ignore errors for now. */
6445 _drm_edid_connector_property_update(connector, drm_edid);
6446
6447 return count;
6448}
6449EXPORT_SYMBOL(drm_edid_connector_update);
6450
6451static int _drm_connector_update_edid_property(struct drm_connector *connector,
6452 const struct drm_edid *drm_edid)
6453{
6454 /* ignore requests to set edid when overridden */
6455 if (connector->override_edid)
6456 return 0;
6457
6458 /*
6459 * Set the display info, using edid if available, otherwise resetting
6460 * the values to defaults. This duplicates the work done in
6461 * drm_add_edid_modes, but that function is not consistently called
6462 * before this one in all drivers and the computation is cheap enough
6463 * that it seems better to duplicate it rather than attempt to ensure
6464 * some arbitrary ordering of calls.
6465 */
6466 if (drm_edid)
6467 update_display_info(connector, drm_edid);
6468 else
6469 drm_reset_display_info(connector);
6470
6471 _drm_update_tile_info(connector, drm_edid);
6472
6473 return _drm_edid_connector_property_update(connector, drm_edid);
6474}
6475
a819451e
JN		 6476/**
6477 * drm_connector_update_edid_property - update the edid property of a connector
6478 * @connector: drm connector
6479 * @edid: new value of the edid property
6480 *
6481 * This function creates a new blob modeset object and assigns its id to the
6482 * connector's edid property.
6483 * Since we also parse tile information from EDID's displayID block, we also
6484 * set the connector's tile property here. See drm_connector_set_tile_property()
6485 * for more details.
6486 *
b71c0aaa
JN		 6487 * This function is deprecated. Use drm_edid_connector_update() instead.
6488 *
a819451e
JN		 6489 * Returns:
6490 * Zero on success, negative errno on failure.
6491 */
6492int drm_connector_update_edid_property(struct drm_connector *connector,
6493 const struct edid *edid)
6494{
6495 struct drm_edid drm_edid;
6496
6497 return _drm_connector_update_edid_property(connector,
6498 drm_edid_legacy_init(&drm_edid, edid));
6499}
02b16fbc
JN		 6500EXPORT_SYMBOL(drm_connector_update_edid_property);
6501
f40ab034
JN		 6502/**
6503 * drm_add_edid_modes - add modes from EDID data, if available
6504 * @connector: connector we're probing
6505 * @edid: EDID data
6506 *
6507 * Add the specified modes to the connector's mode list. Also fills out the
6508 * &drm_display_info structure and ELD in @connector with any information which
6509 * can be derived from the edid.
6510 *
b71c0aaa
JN		 6511 * This function is deprecated. Use drm_edid_connector_update() instead.
6512 *
f40ab034
JN		 6513 * Return: The number of modes added or 0 if we couldn't find any.
6514 */
6515int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
6516{
22a27e05
JN		 6517 struct drm_edid drm_edid;
6518
f40ab034
JN		 6519 if (edid && !drm_edid_is_valid(edid)) {
6520 drm_warn(connector->dev, "%s: EDID invalid.\n",
6521 connector->name);
6522 edid = NULL;
6523 }
6524
b71c0aaa
JN		 6525 return _drm_edid_connector_update(connector,
6526 drm_edid_legacy_init(&drm_edid, edid));
f40ab034 6527}
f453ba04 6528EXPORT_SYMBOL(drm_add_edid_modes);
f0fda0a4
ZY		 6529
6530/**
6531 * drm_add_modes_noedid - add modes for the connectors without EDID
6532 * @connector: connector we're probing
6533 * @hdisplay: the horizontal display limit
6534 * @vdisplay: the vertical display limit
6535 *
6536 * Add the specified modes to the connector's mode list. Only when the
6537 * hdisplay/vdisplay is not beyond the given limit, it will be added.
6538 *
db6cf833 6539 * Return: The number of modes added or 0 if we couldn't find any.
f0fda0a4
ZY		 6540 */
6541int drm_add_modes_noedid(struct drm_connector *connector,
6542 int hdisplay, int vdisplay)
6543{
6544 int i, count, num_modes = 0;
b1f559ec 6545 struct drm_display_mode *mode;
f0fda0a4
ZY		 6546 struct drm_device *dev = connector->dev;
6547
fbb40b28 6548 count = ARRAY_SIZE(drm_dmt_modes);
f0fda0a4
ZY		 6549 if (hdisplay < 0)
6550 hdisplay = 0;
6551 if (vdisplay < 0)
6552 vdisplay = 0;
6553
6554 for (i = 0; i < count; i++) {
b1f559ec 6555 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
948de842 6556
f0fda0a4
ZY		 6557 if (hdisplay && vdisplay) {
6558 /*
6559 * Only when two are valid, they will be used to check
6560 * whether the mode should be added to the mode list of
6561 * the connector.
6562 */
6563 if (ptr->hdisplay > hdisplay ||
6564 ptr->vdisplay > vdisplay)
6565 continue;
6566 }
f985dedb
AJ		 6567 if (drm_mode_vrefresh(ptr) > 61)
6568 continue;
f0fda0a4
ZY		 6569 mode = drm_mode_duplicate(dev, ptr);
6570 if (mode) {
6571 drm_mode_probed_add(connector, mode);
6572 num_modes++;
6573 }
6574 }
6575 return num_modes;
6576}
6577EXPORT_SYMBOL(drm_add_modes_noedid);
10a85120 6578
db6cf833
TR		 6579/**
6580 * drm_set_preferred_mode - Sets the preferred mode of a connector
6581 * @connector: connector whose mode list should be processed
6582 * @hpref: horizontal resolution of preferred mode
6583 * @vpref: vertical resolution of preferred mode
6584 *
6585 * Marks a mode as preferred if it matches the resolution specified by @hpref
6586 * and @vpref.
6587 */
3cf70daf
GH		 6588void drm_set_preferred_mode(struct drm_connector *connector,
6589 int hpref, int vpref)
6590{
6591 struct drm_display_mode *mode;
6592
6593 list_for_each_entry(mode, &connector->probed_modes, head) {
db6cf833 6594 if (mode->hdisplay == hpref &&
9d3de138 6595 mode->vdisplay == vpref)
3cf70daf
GH		 6596 mode->type |= DRM_MODE_TYPE_PREFERRED;
6597 }
6598}
6599EXPORT_SYMBOL(drm_set_preferred_mode);
6600
192a3aa0 6601static bool is_hdmi2_sink(const struct drm_connector *connector)
13d0add3
VS		 6602{
6603 /*
6604 * FIXME: sil-sii8620 doesn't have a connector around when
6605 * we need one, so we have to be prepared for a NULL connector.
6606 */
6607 if (!connector)
6608 return true;
6609
6610 return connector->display_info.hdmi.scdc.supported ||
c03d0b52 6611 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR420;
13d0add3
VS		 6612}
6613
192a3aa0 6614static u8 drm_mode_hdmi_vic(const struct drm_connector *connector,
949561eb
VS		 6615 const struct drm_display_mode *mode)
6616{
6617 bool has_hdmi_infoframe = connector ?
6618 connector->display_info.has_hdmi_infoframe : false;
6619
6620 if (!has_hdmi_infoframe)
6621 return 0;
6622
6623 /* No HDMI VIC when signalling 3D video format */
6624 if (mode->flags & DRM_MODE_FLAG_3D_MASK)
6625 return 0;
6626
6627 return drm_match_hdmi_mode(mode);
6628}
6629
192a3aa0 6630static u8 drm_mode_cea_vic(const struct drm_connector *connector,
cfd6f8c3
VS		 6631 const struct drm_display_mode *mode)
6632{
cfd6f8c3
VS		 6633 u8 vic;
6634
6635 /*
6636 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
6637 * we should send its VIC in vendor infoframes, else send the
6638 * VIC in AVI infoframes. Lets check if this mode is present in
6639 * HDMI 1.4b 4K modes
6640 */
949561eb 6641 if (drm_mode_hdmi_vic(connector, mode))
cfd6f8c3
VS		 6642 return 0;
6643
6644 vic = drm_match_cea_mode(mode);
6645
6646 /*
6647 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
6648 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
6649 * have to make sure we dont break HDMI 1.4 sinks.
6650 */
6651 if (!is_hdmi2_sink(connector) && vic > 64)
6652 return 0;
6653
6654 return vic;
6655}
6656
10a85120
TR		 6657/**
6658 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
6659 * data from a DRM display mode
6660 * @frame: HDMI AVI infoframe
13d0add3 6661 * @connector: the connector
10a85120
TR		 6662 * @mode: DRM display mode
6663 *
db6cf833 6664 * Return: 0 on success or a negative error code on failure.
10a85120
TR		 6665 */
6666int
6667drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
192a3aa0 6668 const struct drm_connector *connector,
13d0add3 6669 const struct drm_display_mode *mode)
10a85120 6670{
a9c266c2 6671 enum hdmi_picture_aspect picture_aspect;
d2b43473 6672 u8 vic, hdmi_vic;
10a85120
TR		 6673
6674 if (!frame || !mode)
6675 return -EINVAL;
6676
5ee0caf1 6677 hdmi_avi_infoframe_init(frame);
10a85120 6678
bf02db99
DL		 6679 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
6680 frame->pixel_repeat = 1;
6681
d2b43473
WL		 6682 vic = drm_mode_cea_vic(connector, mode);
6683 hdmi_vic = drm_mode_hdmi_vic(connector, mode);
0c1f528c 6684
10a85120 6685 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
0967e6a5 6686
50525c33
SL		 6687 /*
6688 * As some drivers don't support atomic, we can't use connector state.
6689 * So just initialize the frame with default values, just the same way
6690 * as it's done with other properties here.
6691 */
6692 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
6693 frame->itc = 0;
6694
69ab6d35
VK		 6695 /*
6696 * Populate picture aspect ratio from either
d2b43473 6697 * user input (if specified) or from the CEA/HDMI mode lists.
69ab6d35 6698 */
a9c266c2 6699 picture_aspect = mode->picture_aspect_ratio;
d2b43473
WL		 6700 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) {
6701 if (vic)
6702 picture_aspect = drm_get_cea_aspect_ratio(vic);
6703 else if (hdmi_vic)
6704 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic);
6705 }
0967e6a5 6706
a9c266c2
VS		 6707 /*
6708 * The infoframe can't convey anything but none, 4:3
6709 * and 16:9, so if the user has asked for anything else
6710 * we can only satisfy it by specifying the right VIC.
6711 */
6712 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
d2b43473
WL		 6713 if (vic) {
6714 if (picture_aspect != drm_get_cea_aspect_ratio(vic))
6715 return -EINVAL;
6716 } else if (hdmi_vic) {
6717 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic))
6718 return -EINVAL;
6719 } else {
a9c266c2 6720 return -EINVAL;
d2b43473
WL		 6721 }
6722
a9c266c2
VS		 6723 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
6724 }
6725
d2b43473 6726 frame->video_code = vic;
a9c266c2 6727 frame->picture_aspect = picture_aspect;
10a85120 6728 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
24d01805 6729 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
10a85120
TR		 6730
6731 return 0;
6732}
6733EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
83dd0008 6734
a2ce26f8
VS		 6735/**
6736 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
6737 * quantization range information
6738 * @frame: HDMI AVI infoframe
13d0add3 6739 * @connector: the connector
779c4c28 6740 * @mode: DRM display mode
a2ce26f8 6741 * @rgb_quant_range: RGB quantization range (Q)
a2ce26f8
VS		 6742 */
6743void
6744drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
192a3aa0 6745 const struct drm_connector *connector,
779c4c28 6746 const struct drm_display_mode *mode,
1581b2df 6747 enum hdmi_quantization_range rgb_quant_range)
a2ce26f8 6748{
1581b2df
VS		 6749 const struct drm_display_info *info = &connector->display_info;
6750
a2ce26f8
VS		 6751 /*
6752 * CEA-861:
6753 * "A Source shall not send a non-zero Q value that does not correspond
6754 * to the default RGB Quantization Range for the transmitted Picture
6755 * unless the Sink indicates support for the Q bit in a Video
6756 * Capabilities Data Block."
779c4c28
VS		 6757 *
6758 * HDMI 2.0 recommends sending non-zero Q when it does match the
6759 * default RGB quantization range for the mode, even when QS=0.
a2ce26f8 6760 */
1581b2df 6761 if (info->rgb_quant_range_selectable ||
779c4c28 6762 rgb_quant_range == drm_default_rgb_quant_range(mode))
a2ce26f8
VS		 6763 frame->quantization_range = rgb_quant_range;
6764 else
6765 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
fcc8a22c
VS		 6766
6767 /*
6768 * CEA-861-F:
6769 * "When transmitting any RGB colorimetry, the Source should set the
6770 * YQ-field to match the RGB Quantization Range being transmitted
6771 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
6772 * set YQ=1) and the Sink shall ignore the YQ-field."
9271c0ca
VS		 6773 *
6774 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
6775 * by non-zero YQ when receiving RGB. There doesn't seem to be any
6776 * good way to tell which version of CEA-861 the sink supports, so
6777 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
6778 * on on CEA-861-F.
fcc8a22c 6779 */
13d0add3 6780 if (!is_hdmi2_sink(connector) ||
9271c0ca 6781 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
fcc8a22c
VS		 6782 frame->ycc_quantization_range =
6783 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
6784 else
6785 frame->ycc_quantization_range =
6786 HDMI_YCC_QUANTIZATION_RANGE_FULL;
a2ce26f8
VS		 6787}
6788EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
6789
4eed4a0a
DL		 6790static enum hdmi_3d_structure
6791s3d_structure_from_display_mode(const struct drm_display_mode *mode)
6792{
6793 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
6794
6795 switch (layout) {
6796 case DRM_MODE_FLAG_3D_FRAME_PACKING:
6797 return HDMI_3D_STRUCTURE_FRAME_PACKING;
6798 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
6799 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
6800 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
6801 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
6802 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
6803 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
6804 case DRM_MODE_FLAG_3D_L_DEPTH:
6805 return HDMI_3D_STRUCTURE_L_DEPTH;
6806 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
6807 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
6808 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
6809 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
6810 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
6811 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
6812 default:
6813 return HDMI_3D_STRUCTURE_INVALID;
6814 }
6815}
6816
83dd0008
LD		 6817/**
6818 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
6819 * data from a DRM display mode
6820 * @frame: HDMI vendor infoframe
f1781e9b 6821 * @connector: the connector
83dd0008
LD		 6822 * @mode: DRM display mode
6823 *
6824 * Note that there's is a need to send HDMI vendor infoframes only when using a
6825 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
6826 * function will return -EINVAL, error that can be safely ignored.
6827 *
db6cf833 6828 * Return: 0 on success or a negative error code on failure.
83dd0008
LD		 6829 */
6830int
6831drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
192a3aa0 6832 const struct drm_connector *connector,
83dd0008
LD		 6833 const struct drm_display_mode *mode)
6834{
f1781e9b
VS		 6835 /*
6836 * FIXME: sil-sii8620 doesn't have a connector around when
6837 * we need one, so we have to be prepared for a NULL connector.
6838 */
6839 bool has_hdmi_infoframe = connector ?
6840 connector->display_info.has_hdmi_infoframe : false;
83dd0008 6841 int err;
83dd0008
LD		 6842
6843 if (!frame || !mode)
6844 return -EINVAL;
6845
f1781e9b
VS		 6846 if (!has_hdmi_infoframe)
6847 return -EINVAL;
6848
949561eb
VS		 6849 err = hdmi_vendor_infoframe_init(frame);
6850 if (err < 0)
6851 return err;
4eed4a0a 6852
f1781e9b
VS		 6853 /*
6854 * Even if it's not absolutely necessary to send the infoframe
6855 * (ie.vic==0 and s3d_struct==0) we will still send it if we
6856 * know that the sink can handle it. This is based on a
6857 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
0ae865ef 6858 * have trouble realizing that they should switch from 3D to 2D
f1781e9b
VS		 6859 * mode if the source simply stops sending the infoframe when
6860 * it wants to switch from 3D to 2D.
6861 */
949561eb 6862 frame->vic = drm_mode_hdmi_vic(connector, mode);
f1781e9b 6863 frame->s3d_struct = s3d_structure_from_display_mode(mode);
83dd0008
LD		 6864
6865 return 0;
6866}
6867EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
40d9b043 6868
7f261afd
VS		 6869static void drm_parse_tiled_block(struct drm_connector *connector,
6870 const struct displayid_block *block)
5e546cd5 6871{
092c367a 6872 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
5e546cd5
DA		 6873 u16 w, h;
6874 u8 tile_v_loc, tile_h_loc;
6875 u8 num_v_tile, num_h_tile;
6876 struct drm_tile_group *tg;
6877
6878 w = tile->tile_size[0] | tile->tile_size[1] << 8;
6879 h = tile->tile_size[2] | tile->tile_size[3] << 8;
6880
6881 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
6882 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
6883 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
6884 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
6885
6886 connector->has_tile = true;
6887 if (tile->tile_cap & 0x80)
6888 connector->tile_is_single_monitor = true;
6889
6890 connector->num_h_tile = num_h_tile + 1;
6891 connector->num_v_tile = num_v_tile + 1;
6892 connector->tile_h_loc = tile_h_loc;
6893 connector->tile_v_loc = tile_v_loc;
6894 connector->tile_h_size = w + 1;
6895 connector->tile_v_size = h + 1;
6896
6897 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
6898 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
6899 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
6900 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
6901 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
6902
6903 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
392f9fcb 6904 if (!tg)
5e546cd5 6905 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
5e546cd5 6906 if (!tg)
7f261afd 6907 return;
5e546cd5
DA		 6908
6909 if (connector->tile_group != tg) {
6910 /* if we haven't got a pointer,
6911 take the reference, drop ref to old tile group */
392f9fcb 6912 if (connector->tile_group)
5e546cd5 6913 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5e546cd5 6914 connector->tile_group = tg;
392f9fcb 6915 } else {
5e546cd5
DA		 6916 /* if same tile group, then release the ref we just took. */
6917 drm_mode_put_tile_group(connector->dev, tg);
392f9fcb 6918 }
5e546cd5
DA		 6919}
6920
c7b2dee4
JN		 6921static void _drm_update_tile_info(struct drm_connector *connector,
6922 const struct drm_edid *drm_edid)
40d9b043 6923{
bfd4e192
JN		 6924 const struct displayid_block *block;
6925 struct displayid_iter iter;
36881184 6926
40d9b043 6927 connector->has_tile = false;
7f261afd 6928
d9ba1b4c 6929 displayid_iter_edid_begin(drm_edid, &iter);
bfd4e192
JN		 6930 displayid_iter_for_each(block, &iter) {
6931 if (block->tag == DATA_BLOCK_TILED_DISPLAY)
6932 drm_parse_tiled_block(connector, block);
40d9b043 6933 }
bfd4e192 6934 displayid_iter_end(&iter);
40d9b043 6935
7f261afd 6936 if (!connector->has_tile && connector->tile_group) {
40d9b043
DA		 6937 drm_mode_put_tile_group(connector->dev, connector->tile_group);
6938 connector->tile_group = NULL;
6939 }
40d9b043 6940}
Linux 6.x block layer and io_uring tree(s)