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drm/edid: Don't accept any old garbage as a display descriptor
[linux-2.6-block.git] / drivers / gpu / drm / drm_edid.c
CommitLineData
f453ba04
DA		 1/*
2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
61e57a8d 5 * Copyright 2010 Red Hat, Inc.
f453ba04
DA		 6 *
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
8 * FB layer.
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 */
9c79edec 30
10a85120 31#include <linux/hdmi.h>
f453ba04 32#include <linux/i2c.h>
9c79edec 33#include <linux/kernel.h>
47819ba2 34#include <linux/module.h>
9c79edec 35#include <linux/slab.h>
5cb8eaa2 36#include <linux/vga_switcheroo.h>
9c79edec
JN		 37
38#include <drm/drm_displayid.h>
39#include <drm/drm_drv.h>
760285e7 40#include <drm/drm_edid.h>
9338203c 41#include <drm/drm_encoder.h>
9c79edec 42#include <drm/drm_print.h>
62c58af3 43#include <drm/drm_scdc_helper.h>
f453ba04 44
969218fe
TI		 45#include "drm_crtc_internal.h"
46
13931579
AJ		 47#define version_greater(edid, maj, min) \
48 (((edid)->version > (maj)) || \
49 ((edid)->version == (maj) && (edid)->revision > (min)))
f453ba04 50
d1ff6409
AJ		 51#define EDID_EST_TIMINGS 16
52#define EDID_STD_TIMINGS 8
53#define EDID_DETAILED_TIMINGS 4
f453ba04
DA		 54
55/*
56 * EDID blocks out in the wild have a variety of bugs, try to collect
57 * them here (note that userspace may work around broken monitors first,
58 * but fixes should make their way here so that the kernel "just works"
59 * on as many displays as possible).
60 */
61
62/* First detailed mode wrong, use largest 60Hz mode */
63#define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
64/* Reported 135MHz pixel clock is too high, needs adjustment */
65#define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
66/* Prefer the largest mode at 75 Hz */
67#define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
68/* Detail timing is in cm not mm */
69#define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
70/* Detailed timing descriptors have bogus size values, so just take the
71 * maximum size and use that.
72 */
73#define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
f453ba04
DA		 74/* use +hsync +vsync for detailed mode */
75#define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
bc42aabc
AJ		 76/* Force reduced-blanking timings for detailed modes */
77#define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
49d45a31
RM		 78/* Force 8bpc */
79#define EDID_QUIRK_FORCE_8BPC (1 << 8)
bc5b9641
MK		 80/* Force 12bpc */
81#define EDID_QUIRK_FORCE_12BPC (1 << 9)
e10aec65
MK		 82/* Force 6bpc */
83#define EDID_QUIRK_FORCE_6BPC (1 << 10)
e345da82
MK		 84/* Force 10bpc */
85#define EDID_QUIRK_FORCE_10BPC (1 << 11)
66660d4c
DA		 86/* Non desktop display (i.e. HMD) */
87#define EDID_QUIRK_NON_DESKTOP (1 << 12)
3c537889 88
13931579
AJ		 89struct detailed_mode_closure {
90 struct drm_connector *connector;
91 struct edid *edid;
92 bool preferred;
93 u32 quirks;
94 int modes;
95};
f453ba04 96
5c61259e
ZY		 97#define LEVEL_DMT 0
98#define LEVEL_GTF 1
7a374350
AJ		 99#define LEVEL_GTF2 2
100#define LEVEL_CVT 3
5c61259e 101
23c4cfbd 102static const struct edid_quirk {
c51a3fd6 103 char vendor[4];
f453ba04
DA		 104 int product_id;
105 u32 quirks;
106} edid_quirk_list[] = {
107 /* Acer AL1706 */
108 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
109 /* Acer F51 */
110 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
f453ba04 111
e10aec65
MK		 112 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
113 { "AEO", 0, EDID_QUIRK_FORCE_6BPC },
114
0711a43b
KHF		 115 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
116 { "BOE", 0x78b, EDID_QUIRK_FORCE_6BPC },
117
06998a75
KHF		 118 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
119 { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC },
120
25da7504
KHF		 121 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
122 { "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC },
123
922dceff
LS		 124 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
125 { "BOE", 0x0771, EDID_QUIRK_FORCE_6BPC },
126
f453ba04
DA		 127 /* Belinea 10 15 55 */
128 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
129 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
130
131 /* Envision Peripherals, Inc. EN-7100e */
132 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
ba1163de
AJ		 133 /* Envision EN2028 */
134 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
f453ba04
DA		 135
136 /* Funai Electronics PM36B */
137 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
138 EDID_QUIRK_DETAILED_IN_CM },
139
e345da82
MK		 140 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
141 { "LGD", 764, EDID_QUIRK_FORCE_10BPC },
142
f453ba04
DA		 143 /* LG Philips LCD LP154W01-A5 */
144 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
145 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
146
f453ba04
DA		 147 /* Samsung SyncMaster 205BW. Note: irony */
148 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
149 /* Samsung SyncMaster 22[5-6]BW */
150 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
151 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
bc42aabc 152
bc5b9641
MK		 153 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
154 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
155
bc42aabc
AJ		 156 /* ViewSonic VA2026w */
157 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
118bdbd8
AD		 158
159 /* Medion MD 30217 PG */
160 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
49d45a31 161
11bcf5f7
KHF		 162 /* Lenovo G50 */
163 { "SDC", 18514, EDID_QUIRK_FORCE_6BPC },
164
49d45a31
RM		 165 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
166 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
36fc5797
TV		 167
168 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
169 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC },
acb1d8ee 170
30d62d44
AR		 171 /* Valve Index Headset */
172 { "VLV", 0x91a8, EDID_QUIRK_NON_DESKTOP },
173 { "VLV", 0x91b0, EDID_QUIRK_NON_DESKTOP },
174 { "VLV", 0x91b1, EDID_QUIRK_NON_DESKTOP },
175 { "VLV", 0x91b2, EDID_QUIRK_NON_DESKTOP },
176 { "VLV", 0x91b3, EDID_QUIRK_NON_DESKTOP },
177 { "VLV", 0x91b4, EDID_QUIRK_NON_DESKTOP },
178 { "VLV", 0x91b5, EDID_QUIRK_NON_DESKTOP },
179 { "VLV", 0x91b6, EDID_QUIRK_NON_DESKTOP },
180 { "VLV", 0x91b7, EDID_QUIRK_NON_DESKTOP },
181 { "VLV", 0x91b8, EDID_QUIRK_NON_DESKTOP },
182 { "VLV", 0x91b9, EDID_QUIRK_NON_DESKTOP },
183 { "VLV", 0x91ba, EDID_QUIRK_NON_DESKTOP },
184 { "VLV", 0x91bb, EDID_QUIRK_NON_DESKTOP },
185 { "VLV", 0x91bc, EDID_QUIRK_NON_DESKTOP },
186 { "VLV", 0x91bd, EDID_QUIRK_NON_DESKTOP },
187 { "VLV", 0x91be, EDID_QUIRK_NON_DESKTOP },
188 { "VLV", 0x91bf, EDID_QUIRK_NON_DESKTOP },
189
6931317c 190 /* HTC Vive and Vive Pro VR Headsets */
acb1d8ee 191 { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP },
6931317c 192 { "HVR", 0xaa02, EDID_QUIRK_NON_DESKTOP },
b3b12ea3
PZ		 193
194 /* Oculus Rift DK1, DK2, and CV1 VR Headsets */
195 { "OVR", 0x0001, EDID_QUIRK_NON_DESKTOP },
196 { "OVR", 0x0003, EDID_QUIRK_NON_DESKTOP },
197 { "OVR", 0x0004, EDID_QUIRK_NON_DESKTOP },
90eda8fc
PZ		 198
199 /* Windows Mixed Reality Headsets */
200 { "ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP },
201 { "HPN", 0x3515, EDID_QUIRK_NON_DESKTOP },
202 { "LEN", 0x0408, EDID_QUIRK_NON_DESKTOP },
203 { "LEN", 0xb800, EDID_QUIRK_NON_DESKTOP },
204 { "FUJ", 0x1970, EDID_QUIRK_NON_DESKTOP },
205 { "DEL", 0x7fce, EDID_QUIRK_NON_DESKTOP },
206 { "SEC", 0x144a, EDID_QUIRK_NON_DESKTOP },
207 { "AUS", 0xc102, EDID_QUIRK_NON_DESKTOP },
ccffc9eb
PZ		 208
209 /* Sony PlayStation VR Headset */
210 { "SNY", 0x0704, EDID_QUIRK_NON_DESKTOP },
29054230
RP		 211
212 /* Sensics VR Headsets */
213 { "SEN", 0x1019, EDID_QUIRK_NON_DESKTOP },
214
215 /* OSVR HDK and HDK2 VR Headsets */
216 { "SVR", 0x1019, EDID_QUIRK_NON_DESKTOP },
f453ba04
DA		 217};
218
a6b21831
TR		 219/*
220 * Autogenerated from the DMT spec.
221 * This table is copied from xfree86/modes/xf86EdidModes.c.
222 */
223static const struct drm_display_mode drm_dmt_modes[] = {
24b856b1 224 /* 0x01 - 640x350@85Hz */
a6b21831
TR		 225 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
226 736, 832, 0, 350, 382, 385, 445, 0,
227 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 228 /* 0x02 - 640x400@85Hz */
a6b21831
TR		 229 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
230 736, 832, 0, 400, 401, 404, 445, 0,
231 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 232 /* 0x03 - 720x400@85Hz */
a6b21831
TR		 233 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
234 828, 936, 0, 400, 401, 404, 446, 0,
235 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 236 /* 0x04 - 640x480@60Hz */
a6b21831 237 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
fcf22d05 238 752, 800, 0, 480, 490, 492, 525, 0,
a6b21831 239 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 240 /* 0x05 - 640x480@72Hz */
a6b21831
TR		 241 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
242 704, 832, 0, 480, 489, 492, 520, 0,
243 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 244 /* 0x06 - 640x480@75Hz */
a6b21831
TR		 245 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
246 720, 840, 0, 480, 481, 484, 500, 0,
247 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 248 /* 0x07 - 640x480@85Hz */
a6b21831
TR		 249 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
250 752, 832, 0, 480, 481, 484, 509, 0,
251 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 252 /* 0x08 - 800x600@56Hz */
a6b21831
TR		 253 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
254 896, 1024, 0, 600, 601, 603, 625, 0,
255 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 256 /* 0x09 - 800x600@60Hz */
a6b21831
TR		 257 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
258 968, 1056, 0, 600, 601, 605, 628, 0,
259 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 260 /* 0x0a - 800x600@72Hz */
a6b21831
TR		 261 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
262 976, 1040, 0, 600, 637, 643, 666, 0,
263 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 264 /* 0x0b - 800x600@75Hz */
a6b21831
TR		 265 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
266 896, 1056, 0, 600, 601, 604, 625, 0,
267 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 268 /* 0x0c - 800x600@85Hz */
a6b21831
TR		 269 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
270 896, 1048, 0, 600, 601, 604, 631, 0,
271 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 272 /* 0x0d - 800x600@120Hz RB */
a6b21831
TR		 273 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
274 880, 960, 0, 600, 603, 607, 636, 0,
275 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 276 /* 0x0e - 848x480@60Hz */
a6b21831
TR		 277 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
278 976, 1088, 0, 480, 486, 494, 517, 0,
279 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 280 /* 0x0f - 1024x768@43Hz, interlace */
a6b21831 281 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
735b100f 282 1208, 1264, 0, 768, 768, 776, 817, 0,
a6b21831 283 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
fcf22d05 284 DRM_MODE_FLAG_INTERLACE) },
24b856b1 285 /* 0x10 - 1024x768@60Hz */
a6b21831
TR		 286 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
287 1184, 1344, 0, 768, 771, 777, 806, 0,
288 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 289 /* 0x11 - 1024x768@70Hz */
a6b21831
TR		 290 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
291 1184, 1328, 0, 768, 771, 777, 806, 0,
292 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 293 /* 0x12 - 1024x768@75Hz */
a6b21831
TR		 294 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
295 1136, 1312, 0, 768, 769, 772, 800, 0,
296 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 297 /* 0x13 - 1024x768@85Hz */
a6b21831
TR		 298 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
299 1168, 1376, 0, 768, 769, 772, 808, 0,
300 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 301 /* 0x14 - 1024x768@120Hz RB */
a6b21831
TR		 302 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
303 1104, 1184, 0, 768, 771, 775, 813, 0,
304 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 305 /* 0x15 - 1152x864@75Hz */
a6b21831
TR		 306 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
307 1344, 1600, 0, 864, 865, 868, 900, 0,
308 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
bfcd74d2
VS		 309 /* 0x55 - 1280x720@60Hz */
310 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
311 1430, 1650, 0, 720, 725, 730, 750, 0,
312 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 313 /* 0x16 - 1280x768@60Hz RB */
a6b21831
TR		 314 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
315 1360, 1440, 0, 768, 771, 778, 790, 0,
316 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 317 /* 0x17 - 1280x768@60Hz */
a6b21831
TR		 318 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
319 1472, 1664, 0, 768, 771, 778, 798, 0,
320 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 321 /* 0x18 - 1280x768@75Hz */
a6b21831
TR		 322 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
323 1488, 1696, 0, 768, 771, 778, 805, 0,
fcf22d05 324 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 325 /* 0x19 - 1280x768@85Hz */
a6b21831
TR		 326 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
327 1496, 1712, 0, 768, 771, 778, 809, 0,
328 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 329 /* 0x1a - 1280x768@120Hz RB */
a6b21831
TR		 330 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
331 1360, 1440, 0, 768, 771, 778, 813, 0,
332 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 333 /* 0x1b - 1280x800@60Hz RB */
a6b21831
TR		 334 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
335 1360, 1440, 0, 800, 803, 809, 823, 0,
336 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 337 /* 0x1c - 1280x800@60Hz */
a6b21831
TR		 338 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
339 1480, 1680, 0, 800, 803, 809, 831, 0,
fcf22d05 340 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 341 /* 0x1d - 1280x800@75Hz */
a6b21831
TR		 342 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
343 1488, 1696, 0, 800, 803, 809, 838, 0,
344 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 345 /* 0x1e - 1280x800@85Hz */
a6b21831
TR		 346 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
347 1496, 1712, 0, 800, 803, 809, 843, 0,
348 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 349 /* 0x1f - 1280x800@120Hz RB */
a6b21831
TR		 350 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
351 1360, 1440, 0, 800, 803, 809, 847, 0,
352 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 353 /* 0x20 - 1280x960@60Hz */
a6b21831
TR		 354 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
355 1488, 1800, 0, 960, 961, 964, 1000, 0,
356 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 357 /* 0x21 - 1280x960@85Hz */
a6b21831
TR		 358 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
359 1504, 1728, 0, 960, 961, 964, 1011, 0,
360 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 361 /* 0x22 - 1280x960@120Hz RB */
a6b21831
TR		 362 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
363 1360, 1440, 0, 960, 963, 967, 1017, 0,
364 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 365 /* 0x23 - 1280x1024@60Hz */
a6b21831
TR		 366 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
367 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 369 /* 0x24 - 1280x1024@75Hz */
a6b21831
TR		 370 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
371 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
372 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 373 /* 0x25 - 1280x1024@85Hz */
a6b21831
TR		 374 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
375 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
376 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 377 /* 0x26 - 1280x1024@120Hz RB */
a6b21831
TR		 378 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
379 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
380 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 381 /* 0x27 - 1360x768@60Hz */
a6b21831
TR		 382 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
383 1536, 1792, 0, 768, 771, 777, 795, 0,
384 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 385 /* 0x28 - 1360x768@120Hz RB */
a6b21831
TR		 386 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
387 1440, 1520, 0, 768, 771, 776, 813, 0,
388 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 389 /* 0x51 - 1366x768@60Hz */
390 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
391 1579, 1792, 0, 768, 771, 774, 798, 0,
392 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
393 /* 0x56 - 1366x768@60Hz */
394 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
395 1436, 1500, 0, 768, 769, 772, 800, 0,
396 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 397 /* 0x29 - 1400x1050@60Hz RB */
a6b21831
TR		 398 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
399 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
400 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 401 /* 0x2a - 1400x1050@60Hz */
a6b21831
TR		 402 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
403 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
404 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 405 /* 0x2b - 1400x1050@75Hz */
a6b21831
TR		 406 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
407 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
408 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 409 /* 0x2c - 1400x1050@85Hz */
a6b21831
TR		 410 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
411 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
412 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 413 /* 0x2d - 1400x1050@120Hz RB */
a6b21831
TR		 414 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
415 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
416 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 417 /* 0x2e - 1440x900@60Hz RB */
a6b21831
TR		 418 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
419 1520, 1600, 0, 900, 903, 909, 926, 0,
420 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 421 /* 0x2f - 1440x900@60Hz */
a6b21831
TR		 422 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
423 1672, 1904, 0, 900, 903, 909, 934, 0,
424 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 425 /* 0x30 - 1440x900@75Hz */
a6b21831
TR		 426 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
427 1688, 1936, 0, 900, 903, 909, 942, 0,
428 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 429 /* 0x31 - 1440x900@85Hz */
a6b21831
TR		 430 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
431 1696, 1952, 0, 900, 903, 909, 948, 0,
432 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 433 /* 0x32 - 1440x900@120Hz RB */
a6b21831
TR		 434 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
435 1520, 1600, 0, 900, 903, 909, 953, 0,
436 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 437 /* 0x53 - 1600x900@60Hz */
438 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
439 1704, 1800, 0, 900, 901, 904, 1000, 0,
440 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 441 /* 0x33 - 1600x1200@60Hz */
a6b21831
TR		 442 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
443 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
444 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 445 /* 0x34 - 1600x1200@65Hz */
a6b21831
TR		 446 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
447 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
448 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 449 /* 0x35 - 1600x1200@70Hz */
a6b21831
TR		 450 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
451 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
452 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 453 /* 0x36 - 1600x1200@75Hz */
a6b21831
TR		 454 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
455 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
456 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 457 /* 0x37 - 1600x1200@85Hz */
a6b21831
TR		 458 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
459 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
460 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 461 /* 0x38 - 1600x1200@120Hz RB */
a6b21831
TR		 462 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
463 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
464 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 465 /* 0x39 - 1680x1050@60Hz RB */
a6b21831
TR		 466 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
467 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
468 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 469 /* 0x3a - 1680x1050@60Hz */
a6b21831
TR		 470 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
471 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
472 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 473 /* 0x3b - 1680x1050@75Hz */
a6b21831
TR		 474 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
475 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
476 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 477 /* 0x3c - 1680x1050@85Hz */
a6b21831
TR		 478 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
479 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
480 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 481 /* 0x3d - 1680x1050@120Hz RB */
a6b21831
TR		 482 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
483 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
484 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 485 /* 0x3e - 1792x1344@60Hz */
a6b21831
TR		 486 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
487 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
488 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 489 /* 0x3f - 1792x1344@75Hz */
a6b21831
TR		 490 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
491 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
492 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 493 /* 0x40 - 1792x1344@120Hz RB */
a6b21831
TR		 494 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
495 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
496 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 497 /* 0x41 - 1856x1392@60Hz */
a6b21831
TR		 498 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
499 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
500 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 501 /* 0x42 - 1856x1392@75Hz */
a6b21831 502 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
fcf22d05 503 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
a6b21831 504 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 505 /* 0x43 - 1856x1392@120Hz RB */
a6b21831
TR		 506 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
507 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
508 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 509 /* 0x52 - 1920x1080@60Hz */
510 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
511 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
512 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 513 /* 0x44 - 1920x1200@60Hz RB */
a6b21831
TR		 514 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
515 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
516 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 517 /* 0x45 - 1920x1200@60Hz */
a6b21831
TR		 518 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
519 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
520 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 521 /* 0x46 - 1920x1200@75Hz */
a6b21831
TR		 522 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
523 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
524 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 525 /* 0x47 - 1920x1200@85Hz */
a6b21831
TR		 526 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
527 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
528 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 529 /* 0x48 - 1920x1200@120Hz RB */
a6b21831
TR		 530 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
531 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
532 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 533 /* 0x49 - 1920x1440@60Hz */
a6b21831
TR		 534 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
535 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
536 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 537 /* 0x4a - 1920x1440@75Hz */
a6b21831
TR		 538 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
539 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
540 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 541 /* 0x4b - 1920x1440@120Hz RB */
a6b21831
TR		 542 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
543 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
544 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 545 /* 0x54 - 2048x1152@60Hz */
546 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
547 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
548 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 549 /* 0x4c - 2560x1600@60Hz RB */
a6b21831
TR		 550 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
551 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
552 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 553 /* 0x4d - 2560x1600@60Hz */
a6b21831
TR		 554 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
555 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
556 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 557 /* 0x4e - 2560x1600@75Hz */
a6b21831
TR		 558 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
559 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
560 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 561 /* 0x4f - 2560x1600@85Hz */
a6b21831
TR		 562 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
563 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
564 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 565 /* 0x50 - 2560x1600@120Hz RB */
a6b21831
TR		 566 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
567 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
568 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 569 /* 0x57 - 4096x2160@60Hz RB */
570 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
571 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
572 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
573 /* 0x58 - 4096x2160@59.94Hz RB */
574 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
575 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
576 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
a6b21831
TR		 577};
578
e7bfa5c4
VS		 579/*
580 * These more or less come from the DMT spec. The 720x400 modes are
581 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
582 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
583 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
584 * mode.
585 *
586 * The DMT modes have been fact-checked; the rest are mild guesses.
587 */
a6b21831
TR		 588static const struct drm_display_mode edid_est_modes[] = {
589 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
590 968, 1056, 0, 600, 601, 605, 628, 0,
591 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
592 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
593 896, 1024, 0, 600, 601, 603, 625, 0,
594 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
595 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
596 720, 840, 0, 480, 481, 484, 500, 0,
597 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
598 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
87707cfd 599 704, 832, 0, 480, 489, 492, 520, 0,
a6b21831
TR		 600 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
601 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
602 768, 864, 0, 480, 483, 486, 525, 0,
603 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
87707cfd 604 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
a6b21831
TR		 605 752, 800, 0, 480, 490, 492, 525, 0,
606 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
607 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
608 846, 900, 0, 400, 421, 423, 449, 0,
609 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
610 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
611 846, 900, 0, 400, 412, 414, 449, 0,
612 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
613 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
614 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
615 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
87707cfd 616 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
a6b21831
TR		 617 1136, 1312, 0, 768, 769, 772, 800, 0,
618 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
619 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
620 1184, 1328, 0, 768, 771, 777, 806, 0,
621 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
622 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
623 1184, 1344, 0, 768, 771, 777, 806, 0,
624 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
625 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
626 1208, 1264, 0, 768, 768, 776, 817, 0,
627 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
628 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
629 928, 1152, 0, 624, 625, 628, 667, 0,
630 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
631 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
632 896, 1056, 0, 600, 601, 604, 625, 0,
633 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
634 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
635 976, 1040, 0, 600, 637, 643, 666, 0,
636 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
637 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
638 1344, 1600, 0, 864, 865, 868, 900, 0,
639 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
640};
641
642struct minimode {
643 short w;
644 short h;
645 short r;
646 short rb;
647};
648
649static const struct minimode est3_modes[] = {
650 /* byte 6 */
651 { 640, 350, 85, 0 },
652 { 640, 400, 85, 0 },
653 { 720, 400, 85, 0 },
654 { 640, 480, 85, 0 },
655 { 848, 480, 60, 0 },
656 { 800, 600, 85, 0 },
657 { 1024, 768, 85, 0 },
658 { 1152, 864, 75, 0 },
659 /* byte 7 */
660 { 1280, 768, 60, 1 },
661 { 1280, 768, 60, 0 },
662 { 1280, 768, 75, 0 },
663 { 1280, 768, 85, 0 },
664 { 1280, 960, 60, 0 },
665 { 1280, 960, 85, 0 },
666 { 1280, 1024, 60, 0 },
667 { 1280, 1024, 85, 0 },
668 /* byte 8 */
669 { 1360, 768, 60, 0 },
670 { 1440, 900, 60, 1 },
671 { 1440, 900, 60, 0 },
672 { 1440, 900, 75, 0 },
673 { 1440, 900, 85, 0 },
674 { 1400, 1050, 60, 1 },
675 { 1400, 1050, 60, 0 },
676 { 1400, 1050, 75, 0 },
677 /* byte 9 */
678 { 1400, 1050, 85, 0 },
679 { 1680, 1050, 60, 1 },
680 { 1680, 1050, 60, 0 },
681 { 1680, 1050, 75, 0 },
682 { 1680, 1050, 85, 0 },
683 { 1600, 1200, 60, 0 },
684 { 1600, 1200, 65, 0 },
685 { 1600, 1200, 70, 0 },
686 /* byte 10 */
687 { 1600, 1200, 75, 0 },
688 { 1600, 1200, 85, 0 },
689 { 1792, 1344, 60, 0 },
c068b32a 690 { 1792, 1344, 75, 0 },
a6b21831
TR		 691 { 1856, 1392, 60, 0 },
692 { 1856, 1392, 75, 0 },
693 { 1920, 1200, 60, 1 },
694 { 1920, 1200, 60, 0 },
695 /* byte 11 */
696 { 1920, 1200, 75, 0 },
697 { 1920, 1200, 85, 0 },
698 { 1920, 1440, 60, 0 },
699 { 1920, 1440, 75, 0 },
700};
701
702static const struct minimode extra_modes[] = {
703 { 1024, 576, 60, 0 },
704 { 1366, 768, 60, 0 },
705 { 1600, 900, 60, 0 },
706 { 1680, 945, 60, 0 },
707 { 1920, 1080, 60, 0 },
708 { 2048, 1152, 60, 0 },
709 { 2048, 1536, 60, 0 },
710};
711
712/*
7befe621 713 * From CEA/CTA-861 spec.
d9278b4c 714 *
7befe621 715 * Do not access directly, instead always use cea_mode_for_vic().
a6b21831 716 */
8c1b2bd9 717static const struct drm_display_mode edid_cea_modes_1[] = {
78691960 718 /* 1 - 640x480@60Hz 4:3 */
a6b21831
TR		 719 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
720 752, 800, 0, 480, 490, 492, 525, 0,
ee7925bb 721 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 722 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 723 /* 2 - 720x480@60Hz 4:3 */
a6b21831
TR		 724 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
725 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 726 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 727 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 728 /* 3 - 720x480@60Hz 16:9 */
a6b21831
TR		 729 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
730 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 731 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 732 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 733 /* 4 - 1280x720@60Hz 16:9 */
a6b21831
TR		 734 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
735 1430, 1650, 0, 720, 725, 730, 750, 0,
ee7925bb 736 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 737 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 738 /* 5 - 1920x1080i@60Hz 16:9 */
a6b21831
TR		 739 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
740 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
741 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 742 DRM_MODE_FLAG_INTERLACE),
985e5dc2 743 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 744 /* 6 - 720(1440)x480i@60Hz 4:3 */
fb01d280
CT		 745 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
746 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 747 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 748 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 749 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 750 /* 7 - 720(1440)x480i@60Hz 16:9 */
fb01d280
CT		 751 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
752 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 753 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 754 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 755 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 756 /* 8 - 720(1440)x240@60Hz 4:3 */
fb01d280
CT		 757 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
758 801, 858, 0, 240, 244, 247, 262, 0,
a6b21831 759 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 760 DRM_MODE_FLAG_DBLCLK),
985e5dc2 761 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 762 /* 9 - 720(1440)x240@60Hz 16:9 */
fb01d280
CT		 763 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
764 801, 858, 0, 240, 244, 247, 262, 0,
a6b21831 765 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 766 DRM_MODE_FLAG_DBLCLK),
985e5dc2 767 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 768 /* 10 - 2880x480i@60Hz 4:3 */
a6b21831
TR		 769 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
770 3204, 3432, 0, 480, 488, 494, 525, 0,
771 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 772 DRM_MODE_FLAG_INTERLACE),
985e5dc2 773 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 774 /* 11 - 2880x480i@60Hz 16:9 */
a6b21831
TR		 775 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
776 3204, 3432, 0, 480, 488, 494, 525, 0,
777 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 778 DRM_MODE_FLAG_INTERLACE),
985e5dc2 779 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 780 /* 12 - 2880x240@60Hz 4:3 */
a6b21831
TR		 781 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
782 3204, 3432, 0, 240, 244, 247, 262, 0,
ee7925bb 783 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 784 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 785 /* 13 - 2880x240@60Hz 16:9 */
a6b21831
TR		 786 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
787 3204, 3432, 0, 240, 244, 247, 262, 0,
ee7925bb 788 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 789 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 790 /* 14 - 1440x480@60Hz 4:3 */
a6b21831
TR		 791 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
792 1596, 1716, 0, 480, 489, 495, 525, 0,
ee7925bb 793 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 794 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 795 /* 15 - 1440x480@60Hz 16:9 */
a6b21831
TR		 796 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
797 1596, 1716, 0, 480, 489, 495, 525, 0,
ee7925bb 798 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 799 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 800 /* 16 - 1920x1080@60Hz 16:9 */
a6b21831
TR		 801 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
802 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 803 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 804 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 805 /* 17 - 720x576@50Hz 4:3 */
a6b21831
TR		 806 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
807 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 808 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 809 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 810 /* 18 - 720x576@50Hz 16:9 */
a6b21831
TR		 811 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
812 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 813 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 814 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 815 /* 19 - 1280x720@50Hz 16:9 */
a6b21831
TR		 816 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
817 1760, 1980, 0, 720, 725, 730, 750, 0,
ee7925bb 818 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 819 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 820 /* 20 - 1920x1080i@50Hz 16:9 */
a6b21831
TR		 821 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
822 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
823 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 824 DRM_MODE_FLAG_INTERLACE),
985e5dc2 825 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 826 /* 21 - 720(1440)x576i@50Hz 4:3 */
fb01d280
CT		 827 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
828 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 829 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 830 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 831 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 832 /* 22 - 720(1440)x576i@50Hz 16:9 */
fb01d280
CT		 833 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
834 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 835 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 836 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 837 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 838 /* 23 - 720(1440)x288@50Hz 4:3 */
fb01d280
CT		 839 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
840 795, 864, 0, 288, 290, 293, 312, 0,
a6b21831 841 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 842 DRM_MODE_FLAG_DBLCLK),
985e5dc2 843 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 844 /* 24 - 720(1440)x288@50Hz 16:9 */
fb01d280
CT		 845 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
846 795, 864, 0, 288, 290, 293, 312, 0,
a6b21831 847 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 848 DRM_MODE_FLAG_DBLCLK),
985e5dc2 849 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 850 /* 25 - 2880x576i@50Hz 4:3 */
a6b21831
TR		 851 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
852 3180, 3456, 0, 576, 580, 586, 625, 0,
853 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 854 DRM_MODE_FLAG_INTERLACE),
985e5dc2 855 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 856 /* 26 - 2880x576i@50Hz 16:9 */
a6b21831
TR		 857 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
858 3180, 3456, 0, 576, 580, 586, 625, 0,
859 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 860 DRM_MODE_FLAG_INTERLACE),
985e5dc2 861 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 862 /* 27 - 2880x288@50Hz 4:3 */
a6b21831
TR		 863 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
864 3180, 3456, 0, 288, 290, 293, 312, 0,
ee7925bb 865 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 866 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 867 /* 28 - 2880x288@50Hz 16:9 */
a6b21831
TR		 868 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
869 3180, 3456, 0, 288, 290, 293, 312, 0,
ee7925bb 870 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 871 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 872 /* 29 - 1440x576@50Hz 4:3 */
a6b21831
TR		 873 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
874 1592, 1728, 0, 576, 581, 586, 625, 0,
ee7925bb 875 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 876 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 877 /* 30 - 1440x576@50Hz 16:9 */
a6b21831
TR		 878 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
879 1592, 1728, 0, 576, 581, 586, 625, 0,
ee7925bb 880 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 881 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 882 /* 31 - 1920x1080@50Hz 16:9 */
a6b21831
TR		 883 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
884 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 885 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 886 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 887 /* 32 - 1920x1080@24Hz 16:9 */
a6b21831
TR		 888 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
889 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 890 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 891 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 892 /* 33 - 1920x1080@25Hz 16:9 */
a6b21831
TR		 893 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
894 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 895 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 896 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 897 /* 34 - 1920x1080@30Hz 16:9 */
a6b21831
TR		 898 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
899 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 900 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 901 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 902 /* 35 - 2880x480@60Hz 4:3 */
a6b21831
TR		 903 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
904 3192, 3432, 0, 480, 489, 495, 525, 0,
ee7925bb 905 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 906 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 907 /* 36 - 2880x480@60Hz 16:9 */
a6b21831
TR		 908 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
909 3192, 3432, 0, 480, 489, 495, 525, 0,
ee7925bb 910 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 911 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 912 /* 37 - 2880x576@50Hz 4:3 */
a6b21831
TR		 913 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
914 3184, 3456, 0, 576, 581, 586, 625, 0,
ee7925bb 915 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 916 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 917 /* 38 - 2880x576@50Hz 16:9 */
a6b21831
TR		 918 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
919 3184, 3456, 0, 576, 581, 586, 625, 0,
ee7925bb 920 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 921 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 922 /* 39 - 1920x1080i@50Hz 16:9 */
a6b21831
TR		 923 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
924 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
925 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 926 DRM_MODE_FLAG_INTERLACE),
985e5dc2 927 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 928 /* 40 - 1920x1080i@100Hz 16:9 */
a6b21831
TR		 929 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
930 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
931 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 932 DRM_MODE_FLAG_INTERLACE),
985e5dc2 933 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 934 /* 41 - 1280x720@100Hz 16:9 */
a6b21831
TR		 935 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
936 1760, 1980, 0, 720, 725, 730, 750, 0,
ee7925bb 937 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 938 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 939 /* 42 - 720x576@100Hz 4:3 */
a6b21831
TR		 940 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
941 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 942 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 943 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 944 /* 43 - 720x576@100Hz 16:9 */
a6b21831
TR		 945 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
946 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 947 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 948 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 949 /* 44 - 720(1440)x576i@100Hz 4:3 */
fb01d280
CT		 950 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
951 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 952 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 953 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 954 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 955 /* 45 - 720(1440)x576i@100Hz 16:9 */
fb01d280
CT		 956 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
957 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 958 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 959 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 960 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 961 /* 46 - 1920x1080i@120Hz 16:9 */
a6b21831
TR		 962 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
963 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
964 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 965 DRM_MODE_FLAG_INTERLACE),
985e5dc2 966 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 967 /* 47 - 1280x720@120Hz 16:9 */
a6b21831
TR		 968 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
969 1430, 1650, 0, 720, 725, 730, 750, 0,
ee7925bb 970 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 971 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 972 /* 48 - 720x480@120Hz 4:3 */
a6b21831
TR		 973 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
974 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 975 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 976 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 977 /* 49 - 720x480@120Hz 16:9 */
a6b21831
TR		 978 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
979 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 980 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 981 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 982 /* 50 - 720(1440)x480i@120Hz 4:3 */
fb01d280
CT		 983 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
984 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 985 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 986 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 987 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 988 /* 51 - 720(1440)x480i@120Hz 16:9 */
fb01d280
CT		 989 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
990 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 991 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 992 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 993 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 994 /* 52 - 720x576@200Hz 4:3 */
a6b21831
TR		 995 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
996 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 997 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 998 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 999 /* 53 - 720x576@200Hz 16:9 */
a6b21831
TR		 1000 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1001 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 1002 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 1003 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1004 /* 54 - 720(1440)x576i@200Hz 4:3 */
fb01d280
CT		 1005 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1006 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 1007 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1008 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 1009 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1010 /* 55 - 720(1440)x576i@200Hz 16:9 */
fb01d280
CT		 1011 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1012 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 1013 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1014 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 1015 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1016 /* 56 - 720x480@240Hz 4:3 */
a6b21831
TR		 1017 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1018 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 1019 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 1020 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1021 /* 57 - 720x480@240Hz 16:9 */
a6b21831
TR		 1022 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1023 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 1024 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 1025 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1026 /* 58 - 720(1440)x480i@240Hz 4:3 */
fb01d280
CT		 1027 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1028 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 1029 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1030 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 1031 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1032 /* 59 - 720(1440)x480i@240Hz 16:9 */
fb01d280
CT		 1033 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1034 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 1035 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1036 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 1037 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1038 /* 60 - 1280x720@24Hz 16:9 */
a6b21831
TR		 1039 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1040 3080, 3300, 0, 720, 725, 730, 750, 0,
ee7925bb 1041 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 1042 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1043 /* 61 - 1280x720@25Hz 16:9 */
a6b21831
TR		 1044 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1045 3740, 3960, 0, 720, 725, 730, 750, 0,
ee7925bb 1046 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 1047 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1048 /* 62 - 1280x720@30Hz 16:9 */
a6b21831
TR		 1049 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1050 3080, 3300, 0, 720, 725, 730, 750, 0,
ee7925bb 1051 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 1052 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1053 /* 63 - 1920x1080@120Hz 16:9 */
a6b21831
TR		 1054 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1055 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 1056 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
78691960
VS		 1057 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1058 /* 64 - 1920x1080@100Hz 16:9 */
a6b21831 1059 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
8f0e4907 1060 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 1061 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
78691960
VS		 1062 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1063 /* 65 - 1280x720@24Hz 64:27 */
8ec6e075
SS		 1064 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1065 3080, 3300, 0, 720, 725, 730, 750, 0,
1066 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1067 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1068 /* 66 - 1280x720@25Hz 64:27 */
8ec6e075
SS		 1069 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1070 3740, 3960, 0, 720, 725, 730, 750, 0,
1071 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1072 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1073 /* 67 - 1280x720@30Hz 64:27 */
8ec6e075
SS		 1074 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1075 3080, 3300, 0, 720, 725, 730, 750, 0,
1076 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1077 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1078 /* 68 - 1280x720@50Hz 64:27 */
8ec6e075
SS		 1079 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1080 1760, 1980, 0, 720, 725, 730, 750, 0,
1081 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1082 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1083 /* 69 - 1280x720@60Hz 64:27 */
8ec6e075
SS		 1084 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1085 1430, 1650, 0, 720, 725, 730, 750, 0,
1086 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1087 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1088 /* 70 - 1280x720@100Hz 64:27 */
8ec6e075
SS		 1089 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1090 1760, 1980, 0, 720, 725, 730, 750, 0,
1091 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1092 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1093 /* 71 - 1280x720@120Hz 64:27 */
8ec6e075
SS		 1094 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1095 1430, 1650, 0, 720, 725, 730, 750, 0,
1096 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1097 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1098 /* 72 - 1920x1080@24Hz 64:27 */
8ec6e075
SS		 1099 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1100 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1101 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1102 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1103 /* 73 - 1920x1080@25Hz 64:27 */
8ec6e075
SS		 1104 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1105 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1106 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1107 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1108 /* 74 - 1920x1080@30Hz 64:27 */
8ec6e075
SS		 1109 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1110 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1111 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1112 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1113 /* 75 - 1920x1080@50Hz 64:27 */
8ec6e075
SS		 1114 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1115 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1116 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1117 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1118 /* 76 - 1920x1080@60Hz 64:27 */
8ec6e075
SS		 1119 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1120 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1121 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1122 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1123 /* 77 - 1920x1080@100Hz 64:27 */
8ec6e075
SS		 1124 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1125 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1126 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1127 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1128 /* 78 - 1920x1080@120Hz 64:27 */
8ec6e075
SS		 1129 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1130 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1131 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1132 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1133 /* 79 - 1680x720@24Hz 64:27 */
8ec6e075
SS		 1134 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1135 3080, 3300, 0, 720, 725, 730, 750, 0,
1136 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1137 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1138 /* 80 - 1680x720@25Hz 64:27 */
8ec6e075
SS		 1139 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1140 2948, 3168, 0, 720, 725, 730, 750, 0,
1141 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1142 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1143 /* 81 - 1680x720@30Hz 64:27 */
8ec6e075
SS		 1144 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1145 2420, 2640, 0, 720, 725, 730, 750, 0,
1146 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1147 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1148 /* 82 - 1680x720@50Hz 64:27 */
8ec6e075
SS		 1149 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1150 1980, 2200, 0, 720, 725, 730, 750, 0,
1151 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1152 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1153 /* 83 - 1680x720@60Hz 64:27 */
8ec6e075
SS		 1154 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1155 1980, 2200, 0, 720, 725, 730, 750, 0,
1156 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1157 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1158 /* 84 - 1680x720@100Hz 64:27 */
8ec6e075
SS		 1159 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1160 1780, 2000, 0, 720, 725, 730, 825, 0,
1161 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1162 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1163 /* 85 - 1680x720@120Hz 64:27 */
8ec6e075
SS		 1164 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1165 1780, 2000, 0, 720, 725, 730, 825, 0,
1166 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1167 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1168 /* 86 - 2560x1080@24Hz 64:27 */
8ec6e075
SS		 1169 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1170 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1171 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1172 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1173 /* 87 - 2560x1080@25Hz 64:27 */
8ec6e075
SS		 1174 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1175 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1176 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1177 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1178 /* 88 - 2560x1080@30Hz 64:27 */
8ec6e075
SS		 1179 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1180 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1181 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1182 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1183 /* 89 - 2560x1080@50Hz 64:27 */
8ec6e075
SS		 1184 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1185 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1186 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1187 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1188 /* 90 - 2560x1080@60Hz 64:27 */
8ec6e075
SS		 1189 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1190 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1191 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1192 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1193 /* 91 - 2560x1080@100Hz 64:27 */
8ec6e075
SS		 1194 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1195 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1196 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1197 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1198 /* 92 - 2560x1080@120Hz 64:27 */
8ec6e075
SS		 1199 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1200 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1201 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1202 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1203 /* 93 - 3840x2160@24Hz 16:9 */
8ec6e075
SS		 1204 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1205 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1206 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1207 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1208 /* 94 - 3840x2160@25Hz 16:9 */
8ec6e075
SS		 1209 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1210 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1211 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1212 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1213 /* 95 - 3840x2160@30Hz 16:9 */
8ec6e075
SS		 1214 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1215 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1216 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1217 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1218 /* 96 - 3840x2160@50Hz 16:9 */
8ec6e075
SS		 1219 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1220 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1221 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1222 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1223 /* 97 - 3840x2160@60Hz 16:9 */
8ec6e075
SS		 1224 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1225 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1226 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1227 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1228 /* 98 - 4096x2160@24Hz 256:135 */
8ec6e075
SS		 1229 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1230 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1231 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1232 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1233 /* 99 - 4096x2160@25Hz 256:135 */
8ec6e075
SS		 1234 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1235 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1236 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1237 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1238 /* 100 - 4096x2160@30Hz 256:135 */
8ec6e075
SS		 1239 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1240 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1241 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1242 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1243 /* 101 - 4096x2160@50Hz 256:135 */
8ec6e075
SS		 1244 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1245 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1246 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1247 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1248 /* 102 - 4096x2160@60Hz 256:135 */
8ec6e075
SS		 1249 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1250 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1251 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1252 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1253 /* 103 - 3840x2160@24Hz 64:27 */
8ec6e075
SS		 1254 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1255 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1256 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1257 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1258 /* 104 - 3840x2160@25Hz 64:27 */
8ec6e075
SS		 1259 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1260 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1261 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1262 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1263 /* 105 - 3840x2160@30Hz 64:27 */
8ec6e075
SS		 1264 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1265 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1266 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1267 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1268 /* 106 - 3840x2160@50Hz 64:27 */
8ec6e075
SS		 1269 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1270 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1271 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1272 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1273 /* 107 - 3840x2160@60Hz 64:27 */
8ec6e075
SS		 1274 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1275 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1277 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1278 /* 108 - 1280x720@48Hz 16:9 */
1279 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1280 2280, 2500, 0, 720, 725, 730, 750, 0,
1281 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1282 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1283 /* 109 - 1280x720@48Hz 64:27 */
1284 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1285 2280, 2500, 0, 720, 725, 730, 750, 0,
1286 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1287 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1288 /* 110 - 1680x720@48Hz 64:27 */
1289 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490,
1290 2530, 2750, 0, 720, 725, 730, 750, 0,
1291 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1292 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1293 /* 111 - 1920x1080@48Hz 16:9 */
1294 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1295 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1296 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1297 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1298 /* 112 - 1920x1080@48Hz 64:27 */
1299 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1300 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1301 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1302 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1303 /* 113 - 2560x1080@48Hz 64:27 */
1304 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558,
1305 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1306 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1307 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1308 /* 114 - 3840x2160@48Hz 16:9 */
1309 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1310 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1311 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1312 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1313 /* 115 - 4096x2160@48Hz 256:135 */
1314 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116,
1315 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1316 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1317 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1318 /* 116 - 3840x2160@48Hz 64:27 */
1319 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1320 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1321 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1322 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1323 /* 117 - 3840x2160@100Hz 16:9 */
1324 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1325 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1326 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1327 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1328 /* 118 - 3840x2160@120Hz 16:9 */
1329 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1330 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1331 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1332 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1333 /* 119 - 3840x2160@100Hz 64:27 */
1334 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1335 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1336 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1337 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1338 /* 120 - 3840x2160@120Hz 64:27 */
1339 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1340 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1341 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1342 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1343 /* 121 - 5120x2160@24Hz 64:27 */
1344 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116,
1345 7204, 7500, 0, 2160, 2168, 2178, 2200, 0,
1346 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1347 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1348 /* 122 - 5120x2160@25Hz 64:27 */
1349 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816,
1350 6904, 7200, 0, 2160, 2168, 2178, 2200, 0,
1351 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1352 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1353 /* 123 - 5120x2160@30Hz 64:27 */
1354 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784,
1355 5872, 6000, 0, 2160, 2168, 2178, 2200, 0,
1356 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1357 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1358 /* 124 - 5120x2160@48Hz 64:27 */
1359 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866,
1360 5954, 6250, 0, 2160, 2168, 2178, 2475, 0,
1361 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1362 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1363 /* 125 - 5120x2160@50Hz 64:27 */
1364 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216,
1365 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1366 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1367 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1368 /* 126 - 5120x2160@60Hz 64:27 */
1369 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284,
1370 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1371 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1372 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1373 /* 127 - 5120x2160@100Hz 64:27 */
1374 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216,
1375 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1376 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1377 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
a6b21831
TR		 1378};
1379
f7655d42
VS		 1380/*
1381 * From CEA/CTA-861 spec.
1382 *
1383 * Do not access directly, instead always use cea_mode_for_vic().
1384 */
1385static const struct drm_display_mode edid_cea_modes_193[] = {
1386 /* 193 - 5120x2160@120Hz 64:27 */
1387 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284,
1388 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1390 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1391 /* 194 - 7680x4320@24Hz 16:9 */
1392 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1393 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1394 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1395 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1396 /* 195 - 7680x4320@25Hz 16:9 */
1397 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1398 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1399 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1400 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1401 /* 196 - 7680x4320@30Hz 16:9 */
1402 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1403 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1404 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1405 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1406 /* 197 - 7680x4320@48Hz 16:9 */
1407 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1408 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1409 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1410 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1411 /* 198 - 7680x4320@50Hz 16:9 */
1412 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1413 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1414 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1415 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1416 /* 199 - 7680x4320@60Hz 16:9 */
1417 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1418 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1419 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1420 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1421 /* 200 - 7680x4320@100Hz 16:9 */
1422 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1423 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1424 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1425 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1426 /* 201 - 7680x4320@120Hz 16:9 */
1427 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1428 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1429 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1430 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1431 /* 202 - 7680x4320@24Hz 64:27 */
1432 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1433 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1434 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1435 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1436 /* 203 - 7680x4320@25Hz 64:27 */
1437 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1438 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1439 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1440 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1441 /* 204 - 7680x4320@30Hz 64:27 */
1442 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1443 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1444 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1445 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1446 /* 205 - 7680x4320@48Hz 64:27 */
1447 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1448 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1449 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1450 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1451 /* 206 - 7680x4320@50Hz 64:27 */
1452 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1453 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1454 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1455 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1456 /* 207 - 7680x4320@60Hz 64:27 */
1457 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1458 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1459 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1460 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1461 /* 208 - 7680x4320@100Hz 64:27 */
1462 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1463 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1464 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1465 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1466 /* 209 - 7680x4320@120Hz 64:27 */
1467 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1468 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1470 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1471 /* 210 - 10240x4320@24Hz 64:27 */
1472 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732,
1473 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1474 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1475 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1476 /* 211 - 10240x4320@25Hz 64:27 */
1477 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732,
1478 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1479 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1480 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1481 /* 212 - 10240x4320@30Hz 64:27 */
1482 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528,
1483 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1484 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1485 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1486 /* 213 - 10240x4320@48Hz 64:27 */
1487 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732,
1488 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1489 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1490 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1491 /* 214 - 10240x4320@50Hz 64:27 */
1492 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732,
1493 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1494 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1495 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1496 /* 215 - 10240x4320@60Hz 64:27 */
1497 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528,
1498 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1499 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1500 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1501 /* 216 - 10240x4320@100Hz 64:27 */
1502 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432,
1503 12608, 13200, 0, 4320, 4336, 4356, 4500, 0,
1504 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1505 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1506 /* 217 - 10240x4320@120Hz 64:27 */
1507 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528,
1508 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1509 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1510 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1511 /* 218 - 4096x2160@100Hz 256:135 */
1512 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896,
1513 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1514 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1515 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1516 /* 219 - 4096x2160@120Hz 256:135 */
1517 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184,
1518 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1519 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1520 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1521};
1522
7ebe1963 1523/*
d9278b4c 1524 * HDMI 1.4 4k modes. Index using the VIC.
7ebe1963
LD		 1525 */
1526static const struct drm_display_mode edid_4k_modes[] = {
d9278b4c
JN		 1527 /* 0 - dummy, VICs start at 1 */
1528 { },
7ebe1963
LD		 1529 /* 1 - 3840x2160@30Hz */
1530 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1531 3840, 4016, 4104, 4400, 0,
1532 2160, 2168, 2178, 2250, 0,
1533 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
d2b43473 1534 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
7ebe1963
LD		 1535 /* 2 - 3840x2160@25Hz */
1536 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1537 3840, 4896, 4984, 5280, 0,
1538 2160, 2168, 2178, 2250, 0,
1539 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
d2b43473 1540 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
7ebe1963
LD		 1541 /* 3 - 3840x2160@24Hz */
1542 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1543 3840, 5116, 5204, 5500, 0,
1544 2160, 2168, 2178, 2250, 0,
1545 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
d2b43473 1546 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
7ebe1963
LD		 1547 /* 4 - 4096x2160@24Hz (SMPTE) */
1548 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1549 4096, 5116, 5204, 5500, 0,
1550 2160, 2168, 2178, 2250, 0,
1551 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
d2b43473 1552 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
7ebe1963
LD		 1553};
1554
61e57a8d 1555/*** DDC fetch and block validation ***/
f453ba04 1556
083ae056
AJ		 1557static const u8 edid_header[] = {
1558 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1559};
f453ba04 1560
db6cf833
TR		 1561/**
1562 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1563 * @raw_edid: pointer to raw base EDID block
1564 *
1565 * Sanity check the header of the base EDID block.
1566 *
1567 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
051963d4
TR		 1568 */
1569int drm_edid_header_is_valid(const u8 *raw_edid)
1570{
1571 int i, score = 0;
1572
1573 for (i = 0; i < sizeof(edid_header); i++)
1574 if (raw_edid[i] == edid_header[i])
1575 score++;
1576
1577 return score;
1578}
1579EXPORT_SYMBOL(drm_edid_header_is_valid);
1580
47819ba2
AJ		 1581static int edid_fixup __read_mostly = 6;
1582module_param_named(edid_fixup, edid_fixup, int, 0400);
1583MODULE_PARM_DESC(edid_fixup,
1584 "Minimum number of valid EDID header bytes (0-8, default 6)");
051963d4 1585
40d9b043
DA		 1586static void drm_get_displayid(struct drm_connector *connector,
1587 struct edid *edid);
e28ad544 1588static int validate_displayid(u8 *displayid, int length, int idx);
da9df2f4 1589
c465bbc8
SB		 1590static int drm_edid_block_checksum(const u8 *raw_edid)
1591{
1592 int i;
e11f5bd8
JFZ		 1593 u8 csum = 0, crc = 0;
1594
1595 for (i = 0; i < EDID_LENGTH - 1; i++)
c465bbc8
SB		 1596 csum += raw_edid[i];
1597
e11f5bd8
JFZ		 1598 crc = 0x100 - csum;
1599
1600 return crc;
1601}
1602
1603static bool drm_edid_block_checksum_diff(const u8 *raw_edid, u8 real_checksum)
1604{
1605 if (raw_edid[EDID_LENGTH - 1] != real_checksum)
1606 return true;
1607 else
1608 return false;
c465bbc8
SB		 1609}
1610
d6885d65
SB		 1611static bool drm_edid_is_zero(const u8 *in_edid, int length)
1612{
1613 if (memchr_inv(in_edid, 0, length))
1614 return false;
1615
1616 return true;
1617}
1618
db6cf833
TR		 1619/**
1620 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1621 * @raw_edid: pointer to raw EDID block
1622 * @block: type of block to validate (0 for base, extension otherwise)
1623 * @print_bad_edid: if true, dump bad EDID blocks to the console
6ba2bd3d 1624 * @edid_corrupt: if true, the header or checksum is invalid
db6cf833
TR		 1625 *
1626 * Validate a base or extension EDID block and optionally dump bad blocks to
1627 * the console.
1628 *
1629 * Return: True if the block is valid, false otherwise.
f453ba04 1630 */
6ba2bd3d
TP		 1631bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
1632 bool *edid_corrupt)
f453ba04 1633{
c465bbc8 1634 u8 csum;
61e57a8d 1635 struct edid *edid = (struct edid *)raw_edid;
f453ba04 1636
fe2ef780
SWK		 1637 if (WARN_ON(!raw_edid))
1638 return false;
1639
47819ba2
AJ		 1640 if (edid_fixup > 8 || edid_fixup < 0)
1641 edid_fixup = 6;
1642
f89ec8a4 1643 if (block == 0) {
051963d4 1644 int score = drm_edid_header_is_valid(raw_edid);
6ba2bd3d
TP		 1645 if (score == 8) {
1646 if (edid_corrupt)
ac6f2e29 1647 *edid_corrupt = false;
6ba2bd3d
TP		 1648 } else if (score >= edid_fixup) {
1649 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
1650 * The corrupt flag needs to be set here otherwise, the
1651 * fix-up code here will correct the problem, the
1652 * checksum is correct and the test fails
1653 */
1654 if (edid_corrupt)
ac6f2e29 1655 *edid_corrupt = true;
61e57a8d
AJ		 1656 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1657 memcpy(raw_edid, edid_header, sizeof(edid_header));
1658 } else {
6ba2bd3d 1659 if (edid_corrupt)
ac6f2e29 1660 *edid_corrupt = true;
61e57a8d
AJ		 1661 goto bad;
1662 }
1663 }
f453ba04 1664
c465bbc8 1665 csum = drm_edid_block_checksum(raw_edid);
e11f5bd8 1666 if (drm_edid_block_checksum_diff(raw_edid, csum)) {
6ba2bd3d 1667 if (edid_corrupt)
ac6f2e29 1668 *edid_corrupt = true;
6ba2bd3d 1669
4a638b4e 1670 /* allow CEA to slide through, switches mangle this */
82d75356
TV		 1671 if (raw_edid[0] == CEA_EXT) {
1672 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum);
1673 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n");
1674 } else {
1675 if (print_bad_edid)
813a7878 1676 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum);
82d75356 1677
4a638b4e 1678 goto bad;
82d75356 1679 }
f453ba04
DA		 1680 }
1681
61e57a8d
AJ		 1682 /* per-block-type checks */
1683 switch (raw_edid[0]) {
1684 case 0: /* base */
1685 if (edid->version != 1) {
813a7878 1686 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version);
61e57a8d
AJ		 1687 goto bad;
1688 }
862b89c0 1689
61e57a8d
AJ		 1690 if (edid->revision > 4)
1691 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1692 break;
862b89c0 1693
61e57a8d
AJ		 1694 default:
1695 break;
1696 }
47ee4ccf 1697
fe2ef780 1698 return true;
f453ba04
DA		 1699
1700bad:
fe2ef780 1701 if (print_bad_edid) {
da4c07b7 1702 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
499447db 1703 pr_notice("EDID block is all zeroes\n");
da4c07b7 1704 } else {
499447db 1705 pr_notice("Raw EDID:\n");
813a7878
CW		 1706 print_hex_dump(KERN_NOTICE,
1707 " \t", DUMP_PREFIX_NONE, 16, 1,
1708 raw_edid, EDID_LENGTH, false);
da4c07b7 1709 }
f453ba04 1710 }
fe2ef780 1711 return false;
f453ba04 1712}
da0df92b 1713EXPORT_SYMBOL(drm_edid_block_valid);
61e57a8d
AJ		 1714
1715/**
1716 * drm_edid_is_valid - sanity check EDID data
1717 * @edid: EDID data
1718 *
1719 * Sanity-check an entire EDID record (including extensions)
db6cf833
TR		 1720 *
1721 * Return: True if the EDID data is valid, false otherwise.
61e57a8d
AJ		 1722 */
1723bool drm_edid_is_valid(struct edid *edid)
1724{
1725 int i;
1726 u8 *raw = (u8 *)edid;
1727
1728 if (!edid)
1729 return false;
1730
1731 for (i = 0; i <= edid->extensions; i++)
6ba2bd3d 1732 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
61e57a8d
AJ		 1733 return false;
1734
1735 return true;
1736}
3c537889 1737EXPORT_SYMBOL(drm_edid_is_valid);
f453ba04 1738
61e57a8d
AJ		 1739#define DDC_SEGMENT_ADDR 0x30
1740/**
db6cf833 1741 * drm_do_probe_ddc_edid() - get EDID information via I2C
7c58e87e 1742 * @data: I2C device adapter
fc66811c
DV		 1743 * @buf: EDID data buffer to be filled
1744 * @block: 128 byte EDID block to start fetching from
1745 * @len: EDID data buffer length to fetch
1746 *
db6cf833 1747 * Try to fetch EDID information by calling I2C driver functions.
61e57a8d 1748 *
db6cf833 1749 * Return: 0 on success or -1 on failure.
61e57a8d
AJ		 1750 */
1751static int
18df89fe 1752drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
61e57a8d 1753{
18df89fe 1754 struct i2c_adapter *adapter = data;
61e57a8d 1755 unsigned char start = block * EDID_LENGTH;
cd004b3f
S		 1756 unsigned char segment = block >> 1;
1757 unsigned char xfers = segment ? 3 : 2;
4819d2e4
CW		 1758 int ret, retries = 5;
1759
db6cf833
TR		 1760 /*
1761 * The core I2C driver will automatically retry the transfer if the
4819d2e4
CW		 1762 * adapter reports EAGAIN. However, we find that bit-banging transfers
1763 * are susceptible to errors under a heavily loaded machine and
1764 * generate spurious NAKs and timeouts. Retrying the transfer
1765 * of the individual block a few times seems to overcome this.
1766 */
1767 do {
1768 struct i2c_msg msgs[] = {
1769 {
cd004b3f
S		 1770 .addr = DDC_SEGMENT_ADDR,
1771 .flags = 0,
1772 .len = 1,
1773 .buf = &segment,
1774 }, {
4819d2e4
CW		 1775 .addr = DDC_ADDR,
1776 .flags = 0,
1777 .len = 1,
1778 .buf = &start,
1779 }, {
1780 .addr = DDC_ADDR,
1781 .flags = I2C_M_RD,
1782 .len = len,
1783 .buf = buf,
1784 }
1785 };
cd004b3f 1786
db6cf833
TR		 1787 /*
1788 * Avoid sending the segment addr to not upset non-compliant
1789 * DDC monitors.
1790 */
cd004b3f
S		 1791 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1792
9292f37e
ED		 1793 if (ret == -ENXIO) {
1794 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1795 adapter->name);
1796 break;
1797 }
cd004b3f 1798 } while (ret != xfers && --retries);
4819d2e4 1799
cd004b3f 1800 return ret == xfers ? 0 : -1;
61e57a8d
AJ		 1801}
1802
14544d09
CW		 1803static void connector_bad_edid(struct drm_connector *connector,
1804 u8 *edid, int num_blocks)
1805{
1806 int i;
e11f5bd8
JFZ		 1807 u8 num_of_ext = edid[0x7e];
1808
1809 /* Calculate real checksum for the last edid extension block data */
1810 connector->real_edid_checksum =
1811 drm_edid_block_checksum(edid + num_of_ext * EDID_LENGTH);
14544d09 1812
f0a8f533 1813 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
14544d09
CW		 1814 return;
1815
1816 dev_warn(connector->dev->dev,
1817 "%s: EDID is invalid:\n",
1818 connector->name);
1819 for (i = 0; i < num_blocks; i++) {
1820 u8 *block = edid + i * EDID_LENGTH;
1821 char prefix[20];
1822
1823 if (drm_edid_is_zero(block, EDID_LENGTH))
1824 sprintf(prefix, "\t[%02x] ZERO ", i);
1825 else if (!drm_edid_block_valid(block, i, false, NULL))
1826 sprintf(prefix, "\t[%02x] BAD ", i);
1827 else
1828 sprintf(prefix, "\t[%02x] GOOD ", i);
1829
1830 print_hex_dump(KERN_WARNING,
1831 prefix, DUMP_PREFIX_NONE, 16, 1,
1832 block, EDID_LENGTH, false);
1833 }
1834}
1835
56a2b7f2
JN		 1836/* Get override or firmware EDID */
1837static struct edid *drm_get_override_edid(struct drm_connector *connector)
1838{
1839 struct edid *override = NULL;
1840
1841 if (connector->override_edid)
1842 override = drm_edid_duplicate(connector->edid_blob_ptr->data);
1843
1844 if (!override)
1845 override = drm_load_edid_firmware(connector);
1846
1847 return IS_ERR(override) ? NULL : override;
1848}
1849
48eaeb76
JN		 1850/**
1851 * drm_add_override_edid_modes - add modes from override/firmware EDID
1852 * @connector: connector we're probing
1853 *
1854 * Add modes from the override/firmware EDID, if available. Only to be used from
1855 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
1856 * failed during drm_get_edid() and caused the override/firmware EDID to be
1857 * skipped.
1858 *
1859 * Return: The number of modes added or 0 if we couldn't find any.
1860 */
1861int drm_add_override_edid_modes(struct drm_connector *connector)
1862{
1863 struct edid *override;
1864 int num_modes = 0;
1865
1866 override = drm_get_override_edid(connector);
1867 if (override) {
1868 drm_connector_update_edid_property(connector, override);
1869 num_modes = drm_add_edid_modes(connector, override);
1870 kfree(override);
1871
1872 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
1873 connector->base.id, connector->name, num_modes);
1874 }
1875
1876 return num_modes;
1877}
1878EXPORT_SYMBOL(drm_add_override_edid_modes);
1879
18df89fe
LPC		 1880/**
1881 * drm_do_get_edid - get EDID data using a custom EDID block read function
1882 * @connector: connector we're probing
1883 * @get_edid_block: EDID block read function
1884 * @data: private data passed to the block read function
1885 *
1886 * When the I2C adapter connected to the DDC bus is hidden behind a device that
1887 * exposes a different interface to read EDID blocks this function can be used
1888 * to get EDID data using a custom block read function.
1889 *
1890 * As in the general case the DDC bus is accessible by the kernel at the I2C
1891 * level, drivers must make all reasonable efforts to expose it as an I2C
1892 * adapter and use drm_get_edid() instead of abusing this function.
1893 *
53fd40a9
JN		 1894 * The EDID may be overridden using debugfs override_edid or firmare EDID
1895 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
1896 * order. Having either of them bypasses actual EDID reads.
1897 *
18df89fe
LPC		 1898 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1899 */
1900struct edid *drm_do_get_edid(struct drm_connector *connector,
1901 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
1902 size_t len),
1903 void *data)
61e57a8d 1904{
0ea75e23 1905 int i, j = 0, valid_extensions = 0;
f14f3686 1906 u8 *edid, *new;
56a2b7f2 1907 struct edid *override;
53fd40a9 1908
56a2b7f2
JN		 1909 override = drm_get_override_edid(connector);
1910 if (override)
53fd40a9 1911 return override;
61e57a8d 1912
f14f3686 1913 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
61e57a8d
AJ		 1914 return NULL;
1915
1916 /* base block fetch */
1917 for (i = 0; i < 4; i++) {
f14f3686 1918 if (get_edid_block(data, edid, 0, EDID_LENGTH))
61e57a8d 1919 goto out;
14544d09 1920 if (drm_edid_block_valid(edid, 0, false,
6ba2bd3d 1921 &connector->edid_corrupt))
61e57a8d 1922 break;
f14f3686 1923 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) {
4a9a8b71
DA		 1924 connector->null_edid_counter++;
1925 goto carp;
1926 }
61e57a8d
AJ		 1927 }
1928 if (i == 4)
1929 goto carp;
1930
1931 /* if there's no extensions, we're done */
14544d09
CW		 1932 valid_extensions = edid[0x7e];
1933 if (valid_extensions == 0)
f14f3686 1934 return (struct edid *)edid;
61e57a8d 1935
14544d09 1936 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
61e57a8d
AJ		 1937 if (!new)
1938 goto out;
f14f3686 1939 edid = new;
61e57a8d 1940
f14f3686 1941 for (j = 1; j <= edid[0x7e]; j++) {
14544d09 1942 u8 *block = edid + j * EDID_LENGTH;
a28187cc 1943
61e57a8d 1944 for (i = 0; i < 4; i++) {
a28187cc 1945 if (get_edid_block(data, block, j, EDID_LENGTH))
61e57a8d 1946 goto out;
14544d09 1947 if (drm_edid_block_valid(block, j, false, NULL))
61e57a8d
AJ		 1948 break;
1949 }
f934ec8c 1950
14544d09
CW		 1951 if (i == 4)
1952 valid_extensions--;
0ea75e23
ST		 1953 }
1954
f14f3686 1955 if (valid_extensions != edid[0x7e]) {
14544d09
CW		 1956 u8 *base;
1957
1958 connector_bad_edid(connector, edid, edid[0x7e] + 1);
1959
f14f3686
CW		 1960 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions;
1961 edid[0x7e] = valid_extensions;
14544d09 1962
6da2ec56
KC		 1963 new = kmalloc_array(valid_extensions + 1, EDID_LENGTH,
1964 GFP_KERNEL);
0ea75e23
ST		 1965 if (!new)
1966 goto out;
14544d09
CW		 1967
1968 base = new;
1969 for (i = 0; i <= edid[0x7e]; i++) {
1970 u8 *block = edid + i * EDID_LENGTH;
1971
1972 if (!drm_edid_block_valid(block, i, false, NULL))
1973 continue;
1974
1975 memcpy(base, block, EDID_LENGTH);
1976 base += EDID_LENGTH;
1977 }
1978
1979 kfree(edid);
f14f3686 1980 edid = new;
61e57a8d
AJ		 1981 }
1982
f14f3686 1983 return (struct edid *)edid;
61e57a8d
AJ		 1984
1985carp:
14544d09 1986 connector_bad_edid(connector, edid, 1);
61e57a8d 1987out:
f14f3686 1988 kfree(edid);
61e57a8d
AJ		 1989 return NULL;
1990}
18df89fe 1991EXPORT_SYMBOL_GPL(drm_do_get_edid);
61e57a8d
AJ		 1992
1993/**
db6cf833
TR		 1994 * drm_probe_ddc() - probe DDC presence
1995 * @adapter: I2C adapter to probe
fc66811c 1996 *
db6cf833 1997 * Return: True on success, false on failure.
61e57a8d 1998 */
fbff4690 1999bool
61e57a8d
AJ		 2000drm_probe_ddc(struct i2c_adapter *adapter)
2001{
2002 unsigned char out;
2003
2004 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
2005}
fbff4690 2006EXPORT_SYMBOL(drm_probe_ddc);
61e57a8d
AJ		 2007
2008/**
2009 * drm_get_edid - get EDID data, if available
2010 * @connector: connector we're probing
db6cf833 2011 * @adapter: I2C adapter to use for DDC
61e57a8d 2012 *
db6cf833 2013 * Poke the given I2C channel to grab EDID data if possible. If found,
61e57a8d
AJ		 2014 * attach it to the connector.
2015 *
db6cf833 2016 * Return: Pointer to valid EDID or NULL if we couldn't find any.
61e57a8d
AJ		 2017 */
2018struct edid *drm_get_edid(struct drm_connector *connector,
2019 struct i2c_adapter *adapter)
2020{
40d9b043
DA		 2021 struct edid *edid;
2022
15f080f0
JN		 2023 if (connector->force == DRM_FORCE_OFF)
2024 return NULL;
2025
2026 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
18df89fe 2027 return NULL;
61e57a8d 2028
40d9b043
DA		 2029 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
2030 if (edid)
2031 drm_get_displayid(connector, edid);
2032 return edid;
61e57a8d
AJ		 2033}
2034EXPORT_SYMBOL(drm_get_edid);
2035
5cb8eaa2
LW		 2036/**
2037 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
2038 * @connector: connector we're probing
2039 * @adapter: I2C adapter to use for DDC
2040 *
2041 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
2042 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
2043 * switch DDC to the GPU which is retrieving EDID.
2044 *
2045 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2046 */
2047struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
2048 struct i2c_adapter *adapter)
2049{
2050 struct pci_dev *pdev = connector->dev->pdev;
2051 struct edid *edid;
2052
2053 vga_switcheroo_lock_ddc(pdev);
2054 edid = drm_get_edid(connector, adapter);
2055 vga_switcheroo_unlock_ddc(pdev);
2056
2057 return edid;
2058}
2059EXPORT_SYMBOL(drm_get_edid_switcheroo);
2060
51f8da59
JN		 2061/**
2062 * drm_edid_duplicate - duplicate an EDID and the extensions
2063 * @edid: EDID to duplicate
2064 *
db6cf833 2065 * Return: Pointer to duplicated EDID or NULL on allocation failure.
51f8da59
JN		 2066 */
2067struct edid *drm_edid_duplicate(const struct edid *edid)
2068{
2069 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
2070}
2071EXPORT_SYMBOL(drm_edid_duplicate);
2072
61e57a8d
AJ		 2073/*** EDID parsing ***/
2074
f453ba04
DA		 2075/**
2076 * edid_vendor - match a string against EDID's obfuscated vendor field
2077 * @edid: EDID to match
2078 * @vendor: vendor string
2079 *
2080 * Returns true if @vendor is in @edid, false otherwise
2081 */
170178fe 2082static bool edid_vendor(const struct edid *edid, const char *vendor)
f453ba04
DA		 2083{
2084 char edid_vendor[3];
2085
2086 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
2087 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
2088 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
16456c87 2089 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
f453ba04
DA		 2090
2091 return !strncmp(edid_vendor, vendor, 3);
2092}
2093
2094/**
2095 * edid_get_quirks - return quirk flags for a given EDID
2096 * @edid: EDID to process
2097 *
2098 * This tells subsequent routines what fixes they need to apply.
2099 */
170178fe 2100static u32 edid_get_quirks(const struct edid *edid)
f453ba04 2101{
23c4cfbd 2102 const struct edid_quirk *quirk;
f453ba04
DA		 2103 int i;
2104
2105 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
2106 quirk = &edid_quirk_list[i];
2107
2108 if (edid_vendor(edid, quirk->vendor) &&
2109 (EDID_PRODUCT_ID(edid) == quirk->product_id))
2110 return quirk->quirks;
2111 }
2112
2113 return 0;
2114}
2115
2116#define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
339d202c 2117#define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
f453ba04 2118
f453ba04
DA		 2119/**
2120 * edid_fixup_preferred - set preferred modes based on quirk list
2121 * @connector: has mode list to fix up
2122 * @quirks: quirks list
2123 *
2124 * Walk the mode list for @connector, clearing the preferred status
2125 * on existing modes and setting it anew for the right mode ala @quirks.
2126 */
2127static void edid_fixup_preferred(struct drm_connector *connector,
2128 u32 quirks)
2129{
2130 struct drm_display_mode *t, *cur_mode, *preferred_mode;
f890607b 2131 int target_refresh = 0;
339d202c 2132 int cur_vrefresh, preferred_vrefresh;
f453ba04
DA		 2133
2134 if (list_empty(&connector->probed_modes))
2135 return;
2136
2137 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
2138 target_refresh = 60;
2139 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
2140 target_refresh = 75;
2141
2142 preferred_mode = list_first_entry(&connector->probed_modes,
2143 struct drm_display_mode, head);
2144
2145 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
2146 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
2147
2148 if (cur_mode == preferred_mode)
2149 continue;
2150
2151 /* Largest mode is preferred */
2152 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
2153 preferred_mode = cur_mode;
2154
339d202c
AD		 2155 cur_vrefresh = cur_mode->vrefresh ?
2156 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode);
2157 preferred_vrefresh = preferred_mode->vrefresh ?
2158 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode);
f453ba04
DA		 2159 /* At a given size, try to get closest to target refresh */
2160 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
339d202c
AD		 2161 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
2162 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
f453ba04
DA		 2163 preferred_mode = cur_mode;
2164 }
2165 }
2166
2167 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
2168}
2169
f6e252ba
AJ		 2170static bool
2171mode_is_rb(const struct drm_display_mode *mode)
2172{
2173 return (mode->htotal - mode->hdisplay == 160) &&
2174 (mode->hsync_end - mode->hdisplay == 80) &&
2175 (mode->hsync_end - mode->hsync_start == 32) &&
2176 (mode->vsync_start - mode->vdisplay == 3);
2177}
2178
33c7531d
AJ		 2179/*
2180 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
2181 * @dev: Device to duplicate against
2182 * @hsize: Mode width
2183 * @vsize: Mode height
2184 * @fresh: Mode refresh rate
f6e252ba 2185 * @rb: Mode reduced-blanking-ness
33c7531d
AJ		 2186 *
2187 * Walk the DMT mode list looking for a match for the given parameters.
db6cf833
TR		 2188 *
2189 * Return: A newly allocated copy of the mode, or NULL if not found.
33c7531d 2190 */
1d42bbc8 2191struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
f6e252ba
AJ		 2192 int hsize, int vsize, int fresh,
2193 bool rb)
559ee21d 2194{
07a5e632 2195 int i;
559ee21d 2196
a6b21831 2197 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
b1f559ec 2198 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
f8b46a05
AJ		 2199 if (hsize != ptr->hdisplay)
2200 continue;
2201 if (vsize != ptr->vdisplay)
2202 continue;
2203 if (fresh != drm_mode_vrefresh(ptr))
2204 continue;
f6e252ba
AJ		 2205 if (rb != mode_is_rb(ptr))
2206 continue;
f8b46a05
AJ		 2207
2208 return drm_mode_duplicate(dev, ptr);
559ee21d 2209 }
f8b46a05
AJ		 2210
2211 return NULL;
559ee21d 2212}
1d42bbc8 2213EXPORT_SYMBOL(drm_mode_find_dmt);
23425cae 2214
a7a131ac
VS		 2215static bool is_display_descriptor(const u8 d[18], u8 tag)
2216{
2217 return d[0] == 0x00 && d[1] == 0x00 &&
2218 d[2] == 0x00 && d[3] == tag;
2219}
2220
d1ff6409
AJ		 2221typedef void detailed_cb(struct detailed_timing *timing, void *closure);
2222
4d76a221
AJ		 2223static void
2224cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
2225{
7304b981 2226 int i, n;
4966b2a9 2227 u8 d = ext[0x02];
4d76a221
AJ		 2228 u8 *det_base = ext + d;
2229
7304b981
VS		 2230 if (d < 4 || d > 127)
2231 return;
2232
4966b2a9 2233 n = (127 - d) / 18;
4d76a221
AJ		 2234 for (i = 0; i < n; i++)
2235 cb((struct detailed_timing *)(det_base + 18 * i), closure);
2236}
2237
cbba98f8
AJ		 2238static void
2239vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
2240{
2241 unsigned int i, n = min((int)ext[0x02], 6);
2242 u8 *det_base = ext + 5;
2243
2244 if (ext[0x01] != 1)
2245 return; /* unknown version */
2246
2247 for (i = 0; i < n; i++)
2248 cb((struct detailed_timing *)(det_base + 18 * i), closure);
2249}
2250
d1ff6409
AJ		 2251static void
2252drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
2253{
2254 int i;
2255 struct edid *edid = (struct edid *)raw_edid;
2256
2257 if (edid == NULL)
2258 return;
2259
2260 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
2261 cb(&(edid->detailed_timings[i]), closure);
2262
4d76a221
AJ		 2263 for (i = 1; i <= raw_edid[0x7e]; i++) {
2264 u8 *ext = raw_edid + (i * EDID_LENGTH);
2265 switch (*ext) {
2266 case CEA_EXT:
2267 cea_for_each_detailed_block(ext, cb, closure);
2268 break;
cbba98f8
AJ		 2269 case VTB_EXT:
2270 vtb_for_each_detailed_block(ext, cb, closure);
2271 break;
4d76a221
AJ		 2272 default:
2273 break;
2274 }
2275 }
d1ff6409
AJ		 2276}
2277
2278static void
2279is_rb(struct detailed_timing *t, void *data)
2280{
2281 u8 *r = (u8 *)t;
a7a131ac
VS		 2282
2283 if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE))
2284 return;
2285
2286 if (r[15] & 0x10)
2287 *(bool *)data = true;
d1ff6409
AJ		 2288}
2289
2290/* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
2291static bool
2292drm_monitor_supports_rb(struct edid *edid)
2293{
2294 if (edid->revision >= 4) {
b196a498 2295 bool ret = false;
d1ff6409
AJ		 2296 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
2297 return ret;
2298 }
2299
2300 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
2301}
2302
7a374350
AJ		 2303static void
2304find_gtf2(struct detailed_timing *t, void *data)
2305{
2306 u8 *r = (u8 *)t;
a7a131ac
VS		 2307
2308 if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE))
2309 return;
2310
2311 if (r[10] == 0x02)
7a374350
AJ		 2312 *(u8 **)data = r;
2313}
2314
2315/* Secondary GTF curve kicks in above some break frequency */
2316static int
2317drm_gtf2_hbreak(struct edid *edid)
2318{
2319 u8 *r = NULL;
2320 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2321 return r ? (r[12] * 2) : 0;
2322}
2323
2324static int
2325drm_gtf2_2c(struct edid *edid)
2326{
2327 u8 *r = NULL;
2328 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2329 return r ? r[13] : 0;
2330}
2331
2332static int
2333drm_gtf2_m(struct edid *edid)
2334{
2335 u8 *r = NULL;
2336 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2337 return r ? (r[15] << 8) + r[14] : 0;
2338}
2339
2340static int
2341drm_gtf2_k(struct edid *edid)
2342{
2343 u8 *r = NULL;
2344 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2345 return r ? r[16] : 0;
2346}
2347
2348static int
2349drm_gtf2_2j(struct edid *edid)
2350{
2351 u8 *r = NULL;
2352 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2353 return r ? r[17] : 0;
2354}
2355
2356/**
2357 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
2358 * @edid: EDID block to scan
2359 */
2360static int standard_timing_level(struct edid *edid)
2361{
2362 if (edid->revision >= 2) {
2363 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
2364 return LEVEL_CVT;
2365 if (drm_gtf2_hbreak(edid))
2366 return LEVEL_GTF2;
bfef04ad
LS		 2367 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
2368 return LEVEL_GTF;
7a374350
AJ		 2369 }
2370 return LEVEL_DMT;
2371}
2372
23425cae
AJ		 2373/*
2374 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
2375 * monitors fill with ascii space (0x20) instead.
2376 */
2377static int
2378bad_std_timing(u8 a, u8 b)
2379{
2380 return (a == 0x00 && b == 0x00) ||
2381 (a == 0x01 && b == 0x01) ||
2382 (a == 0x20 && b == 0x20);
2383}
2384
f453ba04
DA		 2385/**
2386 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
fc66811c
DV		 2387 * @connector: connector of for the EDID block
2388 * @edid: EDID block to scan
f453ba04
DA		 2389 * @t: standard timing params
2390 *
2391 * Take the standard timing params (in this case width, aspect, and refresh)
5c61259e 2392 * and convert them into a real mode using CVT/GTF/DMT.
f453ba04 2393 */
7ca6adb3 2394static struct drm_display_mode *
7a374350 2395drm_mode_std(struct drm_connector *connector, struct edid *edid,
464fdeca 2396 struct std_timing *t)
f453ba04 2397{
7ca6adb3
AJ		 2398 struct drm_device *dev = connector->dev;
2399 struct drm_display_mode *m, *mode = NULL;
5c61259e
ZY		 2400 int hsize, vsize;
2401 int vrefresh_rate;
0454beab
MD		 2402 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
2403 >> EDID_TIMING_ASPECT_SHIFT;
5c61259e
ZY		 2404 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
2405 >> EDID_TIMING_VFREQ_SHIFT;
7a374350 2406 int timing_level = standard_timing_level(edid);
5c61259e 2407
23425cae
AJ		 2408 if (bad_std_timing(t->hsize, t->vfreq_aspect))
2409 return NULL;
2410
5c61259e
ZY		 2411 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
2412 hsize = t->hsize * 8 + 248;
2413 /* vrefresh_rate = vfreq + 60 */
2414 vrefresh_rate = vfreq + 60;
2415 /* the vdisplay is calculated based on the aspect ratio */
f066a17d 2416 if (aspect_ratio == 0) {
464fdeca 2417 if (edid->revision < 3)
f066a17d
AJ		 2418 vsize = hsize;
2419 else
2420 vsize = (hsize * 10) / 16;
2421 } else if (aspect_ratio == 1)
f453ba04 2422 vsize = (hsize * 3) / 4;
0454beab 2423 else if (aspect_ratio == 2)
f453ba04
DA		 2424 vsize = (hsize * 4) / 5;
2425 else
2426 vsize = (hsize * 9) / 16;
a0910c8e
AJ		 2427
2428 /* HDTV hack, part 1 */
2429 if (vrefresh_rate == 60 &&
2430 ((hsize == 1360 && vsize == 765) ||
2431 (hsize == 1368 && vsize == 769))) {
2432 hsize = 1366;
2433 vsize = 768;
2434 }
2435
7ca6adb3
AJ		 2436 /*
2437 * If this connector already has a mode for this size and refresh
2438 * rate (because it came from detailed or CVT info), use that
2439 * instead. This way we don't have to guess at interlace or
2440 * reduced blanking.
2441 */
522032da 2442 list_for_each_entry(m, &connector->probed_modes, head)
7ca6adb3
AJ		 2443 if (m->hdisplay == hsize && m->vdisplay == vsize &&
2444 drm_mode_vrefresh(m) == vrefresh_rate)
2445 return NULL;
2446
a0910c8e
AJ		 2447 /* HDTV hack, part 2 */
2448 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
2449 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
d50ba256 2450 false);
a5ef6567
JM		 2451 if (!mode)
2452 return NULL;
559ee21d 2453 mode->hdisplay = 1366;
a4967de6
AJ		 2454 mode->hsync_start = mode->hsync_start - 1;
2455 mode->hsync_end = mode->hsync_end - 1;
559ee21d
ZY		 2456 return mode;
2457 }
a0910c8e 2458
559ee21d 2459 /* check whether it can be found in default mode table */
f6e252ba
AJ		 2460 if (drm_monitor_supports_rb(edid)) {
2461 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
2462 true);
2463 if (mode)
2464 return mode;
2465 }
2466 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
559ee21d
ZY		 2467 if (mode)
2468 return mode;
2469
f6e252ba 2470 /* okay, generate it */
5c61259e
ZY		 2471 switch (timing_level) {
2472 case LEVEL_DMT:
5c61259e
ZY		 2473 break;
2474 case LEVEL_GTF:
2475 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2476 break;
7a374350
AJ		 2477 case LEVEL_GTF2:
2478 /*
2479 * This is potentially wrong if there's ever a monitor with
2480 * more than one ranges section, each claiming a different
2481 * secondary GTF curve. Please don't do that.
2482 */
2483 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
fc48f169
TI		 2484 if (!mode)
2485 return NULL;
7a374350 2486 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
aefd330e 2487 drm_mode_destroy(dev, mode);
7a374350
AJ		 2488 mode = drm_gtf_mode_complex(dev, hsize, vsize,
2489 vrefresh_rate, 0, 0,
2490 drm_gtf2_m(edid),
2491 drm_gtf2_2c(edid),
2492 drm_gtf2_k(edid),
2493 drm_gtf2_2j(edid));
2494 }
2495 break;
5c61259e 2496 case LEVEL_CVT:
d50ba256
DA		 2497 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
2498 false);
5c61259e
ZY		 2499 break;
2500 }
f453ba04
DA		 2501 return mode;
2502}
2503
b58db2c6
AJ		 2504/*
2505 * EDID is delightfully ambiguous about how interlaced modes are to be
2506 * encoded. Our internal representation is of frame height, but some
2507 * HDTV detailed timings are encoded as field height.
2508 *
2509 * The format list here is from CEA, in frame size. Technically we
2510 * should be checking refresh rate too. Whatever.
2511 */
2512static void
2513drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
2514 struct detailed_pixel_timing *pt)
2515{
2516 int i;
2517 static const struct {
2518 int w, h;
2519 } cea_interlaced[] = {
2520 { 1920, 1080 },
2521 { 720, 480 },
2522 { 1440, 480 },
2523 { 2880, 480 },
2524 { 720, 576 },
2525 { 1440, 576 },
2526 { 2880, 576 },
2527 };
b58db2c6
AJ		 2528
2529 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
2530 return;
2531
3c581411 2532 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
b58db2c6
AJ		 2533 if ((mode->hdisplay == cea_interlaced[i].w) &&
2534 (mode->vdisplay == cea_interlaced[i].h / 2)) {
2535 mode->vdisplay *= 2;
2536 mode->vsync_start *= 2;
2537 mode->vsync_end *= 2;
2538 mode->vtotal *= 2;
2539 mode->vtotal |= 1;
2540 }
2541 }
2542
2543 mode->flags |= DRM_MODE_FLAG_INTERLACE;
2544}
2545
f453ba04
DA		 2546/**
2547 * drm_mode_detailed - create a new mode from an EDID detailed timing section
2548 * @dev: DRM device (needed to create new mode)
2549 * @edid: EDID block
2550 * @timing: EDID detailed timing info
2551 * @quirks: quirks to apply
2552 *
2553 * An EDID detailed timing block contains enough info for us to create and
2554 * return a new struct drm_display_mode.
2555 */
2556static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
2557 struct edid *edid,
2558 struct detailed_timing *timing,
2559 u32 quirks)
2560{
2561 struct drm_display_mode *mode;
2562 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
0454beab
MD		 2563 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
2564 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
2565 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
2566 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
e14cbee4
MD		 2567 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
2568 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
16dad1d7 2569 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
e14cbee4 2570 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
f453ba04 2571
fc438966 2572 /* ignore tiny modes */
0454beab 2573 if (hactive < 64 || vactive < 64)
fc438966
AJ		 2574 return NULL;
2575
0454beab 2576 if (pt->misc & DRM_EDID_PT_STEREO) {
c7d015f3 2577 DRM_DEBUG_KMS("stereo mode not supported\n");
f453ba04
DA		 2578 return NULL;
2579 }
0454beab 2580 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
c7d015f3 2581 DRM_DEBUG_KMS("composite sync not supported\n");
f453ba04
DA		 2582 }
2583
fcb45611
ZY		 2584 /* it is incorrect if hsync/vsync width is zero */
2585 if (!hsync_pulse_width || !vsync_pulse_width) {
2586 DRM_DEBUG_KMS("Incorrect Detailed timing. "
2587 "Wrong Hsync/Vsync pulse width\n");
2588 return NULL;
2589 }
bc42aabc
AJ		 2590
2591 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
2592 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
2593 if (!mode)
2594 return NULL;
2595
2596 goto set_size;
2597 }
2598
f453ba04
DA		 2599 mode = drm_mode_create(dev);
2600 if (!mode)
2601 return NULL;
2602
f453ba04 2603 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
0454beab
MD		 2604 timing->pixel_clock = cpu_to_le16(1088);
2605
2606 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
2607
2608 mode->hdisplay = hactive;
2609 mode->hsync_start = mode->hdisplay + hsync_offset;
2610 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
2611 mode->htotal = mode->hdisplay + hblank;
2612
2613 mode->vdisplay = vactive;
2614 mode->vsync_start = mode->vdisplay + vsync_offset;
2615 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
2616 mode->vtotal = mode->vdisplay + vblank;
f453ba04 2617
7064fef5
JB		 2618 /* Some EDIDs have bogus h/vtotal values */
2619 if (mode->hsync_end > mode->htotal)
2620 mode->htotal = mode->hsync_end + 1;
2621 if (mode->vsync_end > mode->vtotal)
2622 mode->vtotal = mode->vsync_end + 1;
2623
b58db2c6 2624 drm_mode_do_interlace_quirk(mode, pt);
f453ba04
DA		 2625
2626 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
0454beab 2627 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
f453ba04
DA		 2628 }
2629
0454beab
MD		 2630 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
2631 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
2632 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
2633 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
f453ba04 2634
bc42aabc 2635set_size:
e14cbee4
MD		 2636 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
2637 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
f453ba04
DA		 2638
2639 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
2640 mode->width_mm *= 10;
2641 mode->height_mm *= 10;
2642 }
2643
2644 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
2645 mode->width_mm = edid->width_cm * 10;
2646 mode->height_mm = edid->height_cm * 10;
2647 }
2648
bc42aabc 2649 mode->type = DRM_MODE_TYPE_DRIVER;
c19b3b0f 2650 mode->vrefresh = drm_mode_vrefresh(mode);
bc42aabc
AJ		 2651 drm_mode_set_name(mode);
2652
f453ba04
DA		 2653 return mode;
2654}
2655
b17e52ef 2656static bool
b1f559ec
CW		 2657mode_in_hsync_range(const struct drm_display_mode *mode,
2658 struct edid *edid, u8 *t)
b17e52ef
AJ		 2659{
2660 int hsync, hmin, hmax;
2661
2662 hmin = t[7];
2663 if (edid->revision >= 4)
2664 hmin += ((t[4] & 0x04) ? 255 : 0);
2665 hmax = t[8];
2666 if (edid->revision >= 4)
2667 hmax += ((t[4] & 0x08) ? 255 : 0);
07a5e632 2668 hsync = drm_mode_hsync(mode);
07a5e632 2669
b17e52ef
AJ		 2670 return (hsync <= hmax && hsync >= hmin);
2671}
2672
2673static bool
b1f559ec
CW		 2674mode_in_vsync_range(const struct drm_display_mode *mode,
2675 struct edid *edid, u8 *t)
b17e52ef
AJ		 2676{
2677 int vsync, vmin, vmax;
2678
2679 vmin = t[5];
2680 if (edid->revision >= 4)
2681 vmin += ((t[4] & 0x01) ? 255 : 0);
2682 vmax = t[6];
2683 if (edid->revision >= 4)
2684 vmax += ((t[4] & 0x02) ? 255 : 0);
2685 vsync = drm_mode_vrefresh(mode);
2686
2687 return (vsync <= vmax && vsync >= vmin);
2688}
2689
2690static u32
2691range_pixel_clock(struct edid *edid, u8 *t)
2692{
2693 /* unspecified */
2694 if (t[9] == 0 || t[9] == 255)
2695 return 0;
2696
2697 /* 1.4 with CVT support gives us real precision, yay */
2698 if (edid->revision >= 4 && t[10] == 0x04)
2699 return (t[9] * 10000) - ((t[12] >> 2) * 250);
2700
2701 /* 1.3 is pathetic, so fuzz up a bit */
2702 return t[9] * 10000 + 5001;
2703}
2704
b17e52ef 2705static bool
b1f559ec 2706mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
b17e52ef
AJ		 2707 struct detailed_timing *timing)
2708{
2709 u32 max_clock;
2710 u8 *t = (u8 *)timing;
2711
2712 if (!mode_in_hsync_range(mode, edid, t))
07a5e632
AJ		 2713 return false;
2714
b17e52ef 2715 if (!mode_in_vsync_range(mode, edid, t))
07a5e632
AJ		 2716 return false;
2717
b17e52ef 2718 if ((max_clock = range_pixel_clock(edid, t)))
07a5e632
AJ		 2719 if (mode->clock > max_clock)
2720 return false;
b17e52ef
AJ		 2721
2722 /* 1.4 max horizontal check */
2723 if (edid->revision >= 4 && t[10] == 0x04)
2724 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
2725 return false;
2726
2727 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
2728 return false;
07a5e632
AJ		 2729
2730 return true;
2731}
2732
7b668ebe
TI		 2733static bool valid_inferred_mode(const struct drm_connector *connector,
2734 const struct drm_display_mode *mode)
2735{
85f8fcd6 2736 const struct drm_display_mode *m;
7b668ebe
TI		 2737 bool ok = false;
2738
2739 list_for_each_entry(m, &connector->probed_modes, head) {
2740 if (mode->hdisplay == m->hdisplay &&
2741 mode->vdisplay == m->vdisplay &&
2742 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
2743 return false; /* duplicated */
2744 if (mode->hdisplay <= m->hdisplay &&
2745 mode->vdisplay <= m->vdisplay)
2746 ok = true;
2747 }
2748 return ok;
2749}
2750
b17e52ef 2751static int
cd4cd3de 2752drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
b17e52ef 2753 struct detailed_timing *timing)
07a5e632
AJ		 2754{
2755 int i, modes = 0;
2756 struct drm_display_mode *newmode;
2757 struct drm_device *dev = connector->dev;
2758
a6b21831 2759 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
7b668ebe
TI		 2760 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
2761 valid_inferred_mode(connector, drm_dmt_modes + i)) {
07a5e632
AJ		 2762 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
2763 if (newmode) {
2764 drm_mode_probed_add(connector, newmode);
2765 modes++;
2766 }
2767 }
2768 }
2769
2770 return modes;
2771}
2772
c09dedb7
TI		 2773/* fix up 1366x768 mode from 1368x768;
2774 * GFT/CVT can't express 1366 width which isn't dividable by 8
2775 */
969218fe 2776void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
c09dedb7
TI		 2777{
2778 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
2779 mode->hdisplay = 1366;
2780 mode->hsync_start--;
2781 mode->hsync_end--;
2782 drm_mode_set_name(mode);
2783 }
2784}
2785
b309bd37
AJ		 2786static int
2787drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
2788 struct detailed_timing *timing)
2789{
2790 int i, modes = 0;
2791 struct drm_display_mode *newmode;
2792 struct drm_device *dev = connector->dev;
2793
a6b21831 2794 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
b309bd37
AJ		 2795 const struct minimode *m = &extra_modes[i];
2796 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
fc48f169
TI		 2797 if (!newmode)
2798 return modes;
b309bd37 2799
969218fe 2800 drm_mode_fixup_1366x768(newmode);
7b668ebe
TI		 2801 if (!mode_in_range(newmode, edid, timing) ||
2802 !valid_inferred_mode(connector, newmode)) {
b309bd37
AJ		 2803 drm_mode_destroy(dev, newmode);
2804 continue;
2805 }
2806
2807 drm_mode_probed_add(connector, newmode);
2808 modes++;
2809 }
2810
2811 return modes;
2812}
2813
2814static int
2815drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2816 struct detailed_timing *timing)
2817{
2818 int i, modes = 0;
2819 struct drm_display_mode *newmode;
2820 struct drm_device *dev = connector->dev;
2821 bool rb = drm_monitor_supports_rb(edid);
2822
a6b21831 2823 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
b309bd37
AJ		 2824 const struct minimode *m = &extra_modes[i];
2825 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
fc48f169
TI		 2826 if (!newmode)
2827 return modes;
b309bd37 2828
969218fe 2829 drm_mode_fixup_1366x768(newmode);
7b668ebe
TI		 2830 if (!mode_in_range(newmode, edid, timing) ||
2831 !valid_inferred_mode(connector, newmode)) {
b309bd37
AJ		 2832 drm_mode_destroy(dev, newmode);
2833 continue;
2834 }
2835
2836 drm_mode_probed_add(connector, newmode);
2837 modes++;
2838 }
2839
2840 return modes;
2841}
2842
13931579
AJ		 2843static void
2844do_inferred_modes(struct detailed_timing *timing, void *c)
9340d8cf 2845{
13931579
AJ		 2846 struct detailed_mode_closure *closure = c;
2847 struct detailed_non_pixel *data = &timing->data.other_data;
b309bd37 2848 struct detailed_data_monitor_range *range = &data->data.range;
9340d8cf 2849
a7a131ac 2850 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE))
cb21aafe
AJ		 2851 return;
2852
2853 closure->modes += drm_dmt_modes_for_range(closure->connector,
2854 closure->edid,
2855 timing);
b309bd37
AJ		 2856
2857 if (!version_greater(closure->edid, 1, 1))
2858 return; /* GTF not defined yet */
2859
2860 switch (range->flags) {
2861 case 0x02: /* secondary gtf, XXX could do more */
2862 case 0x00: /* default gtf */
2863 closure->modes += drm_gtf_modes_for_range(closure->connector,
2864 closure->edid,
2865 timing);
2866 break;
2867 case 0x04: /* cvt, only in 1.4+ */
2868 if (!version_greater(closure->edid, 1, 3))
2869 break;
2870
2871 closure->modes += drm_cvt_modes_for_range(closure->connector,
2872 closure->edid,
2873 timing);
2874 break;
2875 case 0x01: /* just the ranges, no formula */
2876 default:
2877 break;
2878 }
13931579 2879}
69da3015 2880
13931579
AJ		 2881static int
2882add_inferred_modes(struct drm_connector *connector, struct edid *edid)
2883{
2884 struct detailed_mode_closure closure = {
d456ea2e
JL		 2885 .connector = connector,
2886 .edid = edid,
13931579 2887 };
9340d8cf 2888
13931579
AJ		 2889 if (version_greater(edid, 1, 0))
2890 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
2891 &closure);
9340d8cf 2892
13931579 2893 return closure.modes;
9340d8cf
AJ		 2894}
2895
2255be14
AJ		 2896static int
2897drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
2898{
2899 int i, j, m, modes = 0;
2900 struct drm_display_mode *mode;
f3a32d74 2901 u8 *est = ((u8 *)timing) + 6;
2255be14
AJ		 2902
2903 for (i = 0; i < 6; i++) {
891a7469 2904 for (j = 7; j >= 0; j--) {
2255be14 2905 m = (i * 8) + (7 - j);
3c581411 2906 if (m >= ARRAY_SIZE(est3_modes))
2255be14
AJ		 2907 break;
2908 if (est[i] & (1 << j)) {
1d42bbc8
DA		 2909 mode = drm_mode_find_dmt(connector->dev,
2910 est3_modes[m].w,
2911 est3_modes[m].h,
f6e252ba
AJ		 2912 est3_modes[m].r,
2913 est3_modes[m].rb);
2255be14
AJ		 2914 if (mode) {
2915 drm_mode_probed_add(connector, mode);
2916 modes++;
2917 }
2918 }
2919 }
2920 }
2921
2922 return modes;
2923}
2924
13931579
AJ		 2925static void
2926do_established_modes(struct detailed_timing *timing, void *c)
9cf00977 2927{
13931579 2928 struct detailed_mode_closure *closure = c;
9cf00977 2929
a7a131ac
VS		 2930 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_EST_TIMINGS))
2931 return;
2932
2933 closure->modes += drm_est3_modes(closure->connector, timing);
13931579 2934}
9cf00977 2935
13931579
AJ		 2936/**
2937 * add_established_modes - get est. modes from EDID and add them
db6cf833 2938 * @connector: connector to add mode(s) to
13931579
AJ		 2939 * @edid: EDID block to scan
2940 *
2941 * Each EDID block contains a bitmap of the supported "established modes" list
2942 * (defined above). Tease them out and add them to the global modes list.
2943 */
2944static int
2945add_established_modes(struct drm_connector *connector, struct edid *edid)
2946{
2947 struct drm_device *dev = connector->dev;
2948 unsigned long est_bits = edid->established_timings.t1 |
2949 (edid->established_timings.t2 << 8) |
2950 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
2951 int i, modes = 0;
2952 struct detailed_mode_closure closure = {
d456ea2e
JL		 2953 .connector = connector,
2954 .edid = edid,
13931579 2955 };
9cf00977 2956
13931579
AJ		 2957 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
2958 if (est_bits & (1<<i)) {
2959 struct drm_display_mode *newmode;
2960 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
2961 if (newmode) {
2962 drm_mode_probed_add(connector, newmode);
2963 modes++;
2964 }
2965 }
9cf00977
AJ		 2966 }
2967
13931579
AJ		 2968 if (version_greater(edid, 1, 0))
2969 drm_for_each_detailed_block((u8 *)edid,
2970 do_established_modes, &closure);
2971
2972 return modes + closure.modes;
2973}
2974
2975static void
2976do_standard_modes(struct detailed_timing *timing, void *c)
2977{
2978 struct detailed_mode_closure *closure = c;
2979 struct detailed_non_pixel *data = &timing->data.other_data;
2980 struct drm_connector *connector = closure->connector;
2981 struct edid *edid = closure->edid;
a7a131ac 2982 int i;
13931579 2983
a7a131ac
VS		 2984 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_STD_MODES))
2985 return;
9cf00977 2986
a7a131ac
VS		 2987 for (i = 0; i < 6; i++) {
2988 struct std_timing *std = &data->data.timings[i];
2989 struct drm_display_mode *newmode;
2990
2991 newmode = drm_mode_std(connector, edid, std);
2992 if (newmode) {
2993 drm_mode_probed_add(connector, newmode);
2994 closure->modes++;
9cf00977 2995 }
9cf00977 2996 }
9cf00977
AJ		 2997}
2998
f453ba04 2999/**
13931579 3000 * add_standard_modes - get std. modes from EDID and add them
db6cf833 3001 * @connector: connector to add mode(s) to
f453ba04 3002 * @edid: EDID block to scan
f453ba04 3003 *
13931579
AJ		 3004 * Standard modes can be calculated using the appropriate standard (DMT,
3005 * GTF or CVT. Grab them from @edid and add them to the list.
f453ba04 3006 */
13931579
AJ		 3007static int
3008add_standard_modes(struct drm_connector *connector, struct edid *edid)
f453ba04 3009{
9cf00977 3010 int i, modes = 0;
13931579 3011 struct detailed_mode_closure closure = {
d456ea2e
JL		 3012 .connector = connector,
3013 .edid = edid,
13931579
AJ		 3014 };
3015
3016 for (i = 0; i < EDID_STD_TIMINGS; i++) {
3017 struct drm_display_mode *newmode;
3018
3019 newmode = drm_mode_std(connector, edid,
464fdeca 3020 &edid->standard_timings[i]);
13931579
AJ		 3021 if (newmode) {
3022 drm_mode_probed_add(connector, newmode);
3023 modes++;
3024 }
3025 }
3026
3027 if (version_greater(edid, 1, 0))
3028 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
3029 &closure);
3030
3031 /* XXX should also look for standard codes in VTB blocks */
3032
3033 return modes + closure.modes;
3034}
f453ba04 3035
13931579
AJ		 3036static int drm_cvt_modes(struct drm_connector *connector,
3037 struct detailed_timing *timing)
3038{
3039 int i, j, modes = 0;
3040 struct drm_display_mode *newmode;
3041 struct drm_device *dev = connector->dev;
3042 struct cvt_timing *cvt;
3043 const int rates[] = { 60, 85, 75, 60, 50 };
3044 const u8 empty[3] = { 0, 0, 0 };
a327f6b8 3045
13931579
AJ		 3046 for (i = 0; i < 4; i++) {
3047 int uninitialized_var(width), height;
3048 cvt = &(timing->data.other_data.data.cvt[i]);
f453ba04 3049
13931579 3050 if (!memcmp(cvt->code, empty, 3))
9cf00977 3051 continue;
f453ba04 3052
13931579
AJ		 3053 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
3054 switch (cvt->code[1] & 0x0c) {
3055 case 0x00:
3056 width = height * 4 / 3;
3057 break;
3058 case 0x04:
3059 width = height * 16 / 9;
3060 break;
3061 case 0x08:
3062 width = height * 16 / 10;
3063 break;
3064 case 0x0c:
3065 width = height * 15 / 9;
3066 break;
3067 }
3068
3069 for (j = 1; j < 5; j++) {
3070 if (cvt->code[2] & (1 << j)) {
3071 newmode = drm_cvt_mode(dev, width, height,
3072 rates[j], j == 0,
3073 false, false);
3074 if (newmode) {
3075 drm_mode_probed_add(connector, newmode);
3076 modes++;
3077 }
3078 }
3079 }
f453ba04
DA		 3080 }
3081
3082 return modes;
3083}
9cf00977 3084
13931579
AJ		 3085static void
3086do_cvt_mode(struct detailed_timing *timing, void *c)
882f0219 3087{
13931579 3088 struct detailed_mode_closure *closure = c;
882f0219 3089
a7a131ac
VS		 3090 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_CVT_3BYTE))
3091 return;
3092
3093 closure->modes += drm_cvt_modes(closure->connector, timing);
13931579 3094}
882f0219 3095
13931579
AJ		 3096static int
3097add_cvt_modes(struct drm_connector *connector, struct edid *edid)
3098{
3099 struct detailed_mode_closure closure = {
d456ea2e
JL		 3100 .connector = connector,
3101 .edid = edid,
13931579 3102 };
882f0219 3103
13931579
AJ		 3104 if (version_greater(edid, 1, 2))
3105 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
882f0219 3106
13931579 3107 /* XXX should also look for CVT codes in VTB blocks */
882f0219 3108
13931579
AJ		 3109 return closure.modes;
3110}
3111
fa3a7340
VS		 3112static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
3113
13931579
AJ		 3114static void
3115do_detailed_mode(struct detailed_timing *timing, void *c)
3116{
3117 struct detailed_mode_closure *closure = c;
3118 struct drm_display_mode *newmode;
3119
3120 if (timing->pixel_clock) {
3121 newmode = drm_mode_detailed(closure->connector->dev,
3122 closure->edid, timing,
3123 closure->quirks);
3124 if (!newmode)
3125 return;
3126
3127 if (closure->preferred)
3128 newmode->type |= DRM_MODE_TYPE_PREFERRED;
3129
fa3a7340
VS		 3130 /*
3131 * Detailed modes are limited to 10kHz pixel clock resolution,
3132 * so fix up anything that looks like CEA/HDMI mode, but the clock
3133 * is just slightly off.
3134 */
3135 fixup_detailed_cea_mode_clock(newmode);
3136
13931579
AJ		 3137 drm_mode_probed_add(closure->connector, newmode);
3138 closure->modes++;
c2925bde 3139 closure->preferred = false;
882f0219 3140 }
13931579 3141}
882f0219 3142
13931579
AJ		 3143/*
3144 * add_detailed_modes - Add modes from detailed timings
3145 * @connector: attached connector
3146 * @edid: EDID block to scan
3147 * @quirks: quirks to apply
3148 */
3149static int
3150add_detailed_modes(struct drm_connector *connector, struct edid *edid,
3151 u32 quirks)
3152{
3153 struct detailed_mode_closure closure = {
d456ea2e
JL		 3154 .connector = connector,
3155 .edid = edid,
c2925bde 3156 .preferred = true,
d456ea2e 3157 .quirks = quirks,
13931579
AJ		 3158 };
3159
3160 if (closure.preferred && !version_greater(edid, 1, 3))
3161 closure.preferred =
3162 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
3163
3164 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
3165
3166 return closure.modes;
882f0219 3167}
f453ba04 3168
8fe9790d 3169#define AUDIO_BLOCK 0x01
54ac76f8 3170#define VIDEO_BLOCK 0x02
f23c20c8 3171#define VENDOR_BLOCK 0x03
76adaa34 3172#define SPEAKER_BLOCK 0x04
e85959d6 3173#define HDR_STATIC_METADATA_BLOCK 0x6
87563fc0
SS		 3174#define USE_EXTENDED_TAG 0x07
3175#define EXT_VIDEO_CAPABILITY_BLOCK 0x00
832d4f2f
SS		 3176#define EXT_VIDEO_DATA_BLOCK_420 0x0E
3177#define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F
8fe9790d 3178#define EDID_BASIC_AUDIO (1 << 6)
a988bc72
LPC		 3179#define EDID_CEA_YCRCB444 (1 << 5)
3180#define EDID_CEA_YCRCB422 (1 << 4)
b1edd6a6 3181#define EDID_CEA_VCDB_QS (1 << 6)
8fe9790d 3182
d4e4a31d 3183/*
8fe9790d 3184 * Search EDID for CEA extension block.
f23c20c8 3185 */
170178fe 3186static u8 *drm_find_edid_extension(const struct edid *edid, int ext_id)
f23c20c8 3187{
8fe9790d
ZW		 3188 u8 *edid_ext = NULL;
3189 int i;
f23c20c8
ML		 3190
3191 /* No EDID or EDID extensions */
3192 if (edid == NULL || edid->extensions == 0)
8fe9790d 3193 return NULL;
f23c20c8 3194
f23c20c8 3195 /* Find CEA extension */
7466f4cc 3196 for (i = 0; i < edid->extensions; i++) {
8fe9790d 3197 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
40d9b043 3198 if (edid_ext[0] == ext_id)
f23c20c8
ML		 3199 break;
3200 }
3201
7466f4cc 3202 if (i == edid->extensions)
8fe9790d
ZW		 3203 return NULL;
3204
3205 return edid_ext;
3206}
3207
40d9b043 3208
170178fe 3209static u8 *drm_find_displayid_extension(const struct edid *edid)
40d9b043
DA		 3210{
3211 return drm_find_edid_extension(edid, DISPLAYID_EXT);
3212}
3213
e28ad544
AR		 3214static u8 *drm_find_cea_extension(const struct edid *edid)
3215{
3216 int ret;
3217 int idx = 1;
3218 int length = EDID_LENGTH;
3219 struct displayid_block *block;
3220 u8 *cea;
3221 u8 *displayid;
3222
3223 /* Look for a top level CEA extension block */
3224 cea = drm_find_edid_extension(edid, CEA_EXT);
3225 if (cea)
3226 return cea;
3227
3228 /* CEA blocks can also be found embedded in a DisplayID block */
3229 displayid = drm_find_displayid_extension(edid);
3230 if (!displayid)
3231 return NULL;
3232
3233 ret = validate_displayid(displayid, length, idx);
3234 if (ret)
3235 return NULL;
3236
3237 idx += sizeof(struct displayid_hdr);
3238 for_each_displayid_db(displayid, block, idx, length) {
3239 if (block->tag == DATA_BLOCK_CTA) {
3240 cea = (u8 *)block;
3241 break;
3242 }
3243 }
3244
3245 return cea;
3246}
3247
7befe621
VS		 3248static const struct drm_display_mode *cea_mode_for_vic(u8 vic)
3249{
9212f8ee
VS		 3250 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127);
3251 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219);
3252
8c1b2bd9
VS		 3253 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1))
3254 return &edid_cea_modes_1[vic - 1];
f7655d42
VS		 3255 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193))
3256 return &edid_cea_modes_193[vic - 193];
7befe621
VS		 3257 return NULL;
3258}
3259
3260static u8 cea_num_vics(void)
3261{
f7655d42 3262 return 193 + ARRAY_SIZE(edid_cea_modes_193);
7befe621
VS		 3263}
3264
3265static u8 cea_next_vic(u8 vic)
3266{
8c1b2bd9 3267 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1))
f7655d42
VS		 3268 vic = 193;
3269 return vic;
7befe621
VS		 3270}
3271
e6e79209
VS		 3272/*
3273 * Calculate the alternate clock for the CEA mode
3274 * (60Hz vs. 59.94Hz etc.)
3275 */
3276static unsigned int
3277cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
3278{
3279 unsigned int clock = cea_mode->clock;
3280
3281 if (cea_mode->vrefresh % 6 != 0)
3282 return clock;
3283
3284 /*
3285 * edid_cea_modes contains the 59.94Hz
3286 * variant for 240 and 480 line modes,
3287 * and the 60Hz variant otherwise.
3288 */
3289 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
9afd808c 3290 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
e6e79209 3291 else
9afd808c 3292 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
e6e79209
VS		 3293
3294 return clock;
3295}
3296
c45a4e46
VS		 3297static bool
3298cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
3299{
3300 /*
3301 * For certain VICs the spec allows the vertical
3302 * front porch to vary by one or two lines.
3303 *
3304 * cea_modes[] stores the variant with the shortest
3305 * vertical front porch. We can adjust the mode to
3306 * get the other variants by simply increasing the
3307 * vertical front porch length.
3308 */
7befe621
VS		 3309 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 ||
3310 cea_mode_for_vic(9)->vtotal != 262 ||
3311 cea_mode_for_vic(12)->vtotal != 262 ||
3312 cea_mode_for_vic(13)->vtotal != 262 ||
3313 cea_mode_for_vic(23)->vtotal != 312 ||
3314 cea_mode_for_vic(24)->vtotal != 312 ||
3315 cea_mode_for_vic(27)->vtotal != 312 ||
3316 cea_mode_for_vic(28)->vtotal != 312);
c45a4e46
VS		 3317
3318 if (((vic == 8 || vic == 9 ||
3319 vic == 12 || vic == 13) && mode->vtotal < 263) ||
3320 ((vic == 23 || vic == 24 ||
3321 vic == 27 || vic == 28) && mode->vtotal < 314)) {
3322 mode->vsync_start++;
3323 mode->vsync_end++;
3324 mode->vtotal++;
3325
3326 return true;
3327 }
3328
3329 return false;
3330}
3331
4c6bcf44
VS		 3332static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
3333 unsigned int clock_tolerance)
3334{
357768cc 3335 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 3336 u8 vic;
4c6bcf44
VS		 3337
3338 if (!to_match->clock)
3339 return 0;
3340
357768cc
VS		 3341 if (to_match->picture_aspect_ratio)
3342 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3343
7befe621
VS		 3344 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
3345 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic);
4c6bcf44
VS		 3346 unsigned int clock1, clock2;
3347
3348 /* Check both 60Hz and 59.94Hz */
c45a4e46
VS		 3349 clock1 = cea_mode.clock;
3350 clock2 = cea_mode_alternate_clock(&cea_mode);
4c6bcf44
VS		 3351
3352 if (abs(to_match->clock - clock1) > clock_tolerance &&
3353 abs(to_match->clock - clock2) > clock_tolerance)
3354 continue;
3355
c45a4e46 3356 do {
357768cc 3357 if (drm_mode_match(to_match, &cea_mode, match_flags))
c45a4e46
VS		 3358 return vic;
3359 } while (cea_mode_alternate_timings(vic, &cea_mode));
4c6bcf44
VS		 3360 }
3361
3362 return 0;
3363}
3364
18316c8c
TR		 3365/**
3366 * drm_match_cea_mode - look for a CEA mode matching given mode
3367 * @to_match: display mode
3368 *
db6cf833 3369 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
18316c8c 3370 * mode.
a4799037 3371 */
18316c8c 3372u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
a4799037 3373{
357768cc 3374 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 3375 u8 vic;
a4799037 3376
a90b590e
VS		 3377 if (!to_match->clock)
3378 return 0;
3379
357768cc
VS		 3380 if (to_match->picture_aspect_ratio)
3381 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3382
7befe621
VS		 3383 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
3384 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic);
a90b590e
VS		 3385 unsigned int clock1, clock2;
3386
a90b590e 3387 /* Check both 60Hz and 59.94Hz */
c45a4e46
VS		 3388 clock1 = cea_mode.clock;
3389 clock2 = cea_mode_alternate_clock(&cea_mode);
a4799037 3390
c45a4e46
VS		 3391 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
3392 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
3393 continue;
3394
3395 do {
357768cc 3396 if (drm_mode_match(to_match, &cea_mode, match_flags))
c45a4e46
VS		 3397 return vic;
3398 } while (cea_mode_alternate_timings(vic, &cea_mode));
a4799037 3399 }
c45a4e46 3400
a4799037
SM		 3401 return 0;
3402}
3403EXPORT_SYMBOL(drm_match_cea_mode);
3404
d9278b4c
JN		 3405static bool drm_valid_cea_vic(u8 vic)
3406{
7befe621 3407 return cea_mode_for_vic(vic) != NULL;
d9278b4c
JN		 3408}
3409
28c03a44 3410static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
0967e6a5 3411{
7befe621
VS		 3412 const struct drm_display_mode *mode = cea_mode_for_vic(video_code);
3413
3414 if (mode)
3415 return mode->picture_aspect_ratio;
3416
3417 return HDMI_PICTURE_ASPECT_NONE;
0967e6a5 3418}
0967e6a5 3419
d2b43473
WL		 3420static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code)
3421{
3422 return edid_4k_modes[video_code].picture_aspect_ratio;
3423}
3424
3f2f6533
LD		 3425/*
3426 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
3427 * specific block).
3f2f6533
LD		 3428 */
3429static unsigned int
3430hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
3431{
3f2f6533
LD		 3432 return cea_mode_alternate_clock(hdmi_mode);
3433}
3434
4c6bcf44
VS		 3435static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
3436 unsigned int clock_tolerance)
3437{
357768cc 3438 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 3439 u8 vic;
4c6bcf44
VS		 3440
3441 if (!to_match->clock)
3442 return 0;
3443
d2b43473
WL		 3444 if (to_match->picture_aspect_ratio)
3445 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3446
d9278b4c
JN		 3447 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3448 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4c6bcf44
VS		 3449 unsigned int clock1, clock2;
3450
3451 /* Make sure to also match alternate clocks */
3452 clock1 = hdmi_mode->clock;
3453 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3454
3455 if (abs(to_match->clock - clock1) > clock_tolerance &&
3456 abs(to_match->clock - clock2) > clock_tolerance)
3457 continue;
3458
357768cc 3459 if (drm_mode_match(to_match, hdmi_mode, match_flags))
d9278b4c 3460 return vic;
4c6bcf44
VS		 3461 }
3462
3463 return 0;
3464}
3465
3f2f6533
LD		 3466/*
3467 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
3468 * @to_match: display mode
3469 *
3470 * An HDMI mode is one defined in the HDMI vendor specific block.
3471 *
3472 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
3473 */
3474static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
3475{
357768cc 3476 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 3477 u8 vic;
3f2f6533
LD		 3478
3479 if (!to_match->clock)
3480 return 0;
3481
d2b43473
WL		 3482 if (to_match->picture_aspect_ratio)
3483 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3484
d9278b4c
JN		 3485 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3486 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3f2f6533
LD		 3487 unsigned int clock1, clock2;
3488
3489 /* Make sure to also match alternate clocks */
3490 clock1 = hdmi_mode->clock;
3491 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3492
3493 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
3494 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
357768cc 3495 drm_mode_match(to_match, hdmi_mode, match_flags))
d9278b4c 3496 return vic;
3f2f6533
LD		 3497 }
3498 return 0;
3499}
3500
d9278b4c
JN		 3501static bool drm_valid_hdmi_vic(u8 vic)
3502{
3503 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
3504}
3505
e6e79209
VS		 3506static int
3507add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
3508{
3509 struct drm_device *dev = connector->dev;
3510 struct drm_display_mode *mode, *tmp;
3511 LIST_HEAD(list);
3512 int modes = 0;
3513
3514 /* Don't add CEA modes if the CEA extension block is missing */
3515 if (!drm_find_cea_extension(edid))
3516 return 0;
3517
3518 /*
3519 * Go through all probed modes and create a new mode
3520 * with the alternate clock for certain CEA modes.
3521 */
3522 list_for_each_entry(mode, &connector->probed_modes, head) {
3f2f6533 3523 const struct drm_display_mode *cea_mode = NULL;
e6e79209 3524 struct drm_display_mode *newmode;
d9278b4c 3525 u8 vic = drm_match_cea_mode(mode);
e6e79209
VS		 3526 unsigned int clock1, clock2;
3527
d9278b4c 3528 if (drm_valid_cea_vic(vic)) {
7befe621 3529 cea_mode = cea_mode_for_vic(vic);
3f2f6533
LD		 3530 clock2 = cea_mode_alternate_clock(cea_mode);
3531 } else {
d9278b4c
JN		 3532 vic = drm_match_hdmi_mode(mode);
3533 if (drm_valid_hdmi_vic(vic)) {
3534 cea_mode = &edid_4k_modes[vic];
3f2f6533
LD		 3535 clock2 = hdmi_mode_alternate_clock(cea_mode);
3536 }
3537 }
e6e79209 3538
3f2f6533
LD		 3539 if (!cea_mode)
3540 continue;
e6e79209
VS		 3541
3542 clock1 = cea_mode->clock;
e6e79209
VS		 3543
3544 if (clock1 == clock2)
3545 continue;
3546
3547 if (mode->clock != clock1 && mode->clock != clock2)
3548 continue;
3549
3550 newmode = drm_mode_duplicate(dev, cea_mode);
3551 if (!newmode)
3552 continue;
3553
27130212
DL		 3554 /* Carry over the stereo flags */
3555 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
3556
e6e79209
VS		 3557 /*
3558 * The current mode could be either variant. Make
3559 * sure to pick the "other" clock for the new mode.
3560 */
3561 if (mode->clock != clock1)
3562 newmode->clock = clock1;
3563 else
3564 newmode->clock = clock2;
3565
3566 list_add_tail(&newmode->head, &list);
3567 }
3568
3569 list_for_each_entry_safe(mode, tmp, &list, head) {
3570 list_del(&mode->head);
3571 drm_mode_probed_add(connector, mode);
3572 modes++;
3573 }
3574
3575 return modes;
3576}
a4799037 3577
8ec6e075
SS		 3578static u8 svd_to_vic(u8 svd)
3579{
3580 /* 0-6 bit vic, 7th bit native mode indicator */
3581 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
3582 return svd & 127;
3583
3584 return svd;
3585}
3586
aff04ace
TW		 3587static struct drm_display_mode *
3588drm_display_mode_from_vic_index(struct drm_connector *connector,
3589 const u8 *video_db, u8 video_len,
3590 u8 video_index)
54ac76f8
CS		 3591{
3592 struct drm_device *dev = connector->dev;
aff04ace 3593 struct drm_display_mode *newmode;
d9278b4c 3594 u8 vic;
54ac76f8 3595
aff04ace
TW		 3596 if (video_db == NULL || video_index >= video_len)
3597 return NULL;
3598
3599 /* CEA modes are numbered 1..127 */
8ec6e075 3600 vic = svd_to_vic(video_db[video_index]);
d9278b4c 3601 if (!drm_valid_cea_vic(vic))
aff04ace
TW		 3602 return NULL;
3603
7befe621 3604 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
409bbf1e
DL		 3605 if (!newmode)
3606 return NULL;
3607
aff04ace
TW		 3608 newmode->vrefresh = 0;
3609
3610 return newmode;
3611}
3612
832d4f2f
SS		 3613/*
3614 * do_y420vdb_modes - Parse YCBCR 420 only modes
3615 * @connector: connector corresponding to the HDMI sink
3616 * @svds: start of the data block of CEA YCBCR 420 VDB
3617 * @len: length of the CEA YCBCR 420 VDB
3618 *
3619 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
3620 * which contains modes which can be supported in YCBCR 420
3621 * output format only.
3622 */
3623static int do_y420vdb_modes(struct drm_connector *connector,
3624 const u8 *svds, u8 svds_len)
3625{
3626 int modes = 0, i;
3627 struct drm_device *dev = connector->dev;
3628 struct drm_display_info *info = &connector->display_info;
3629 struct drm_hdmi_info *hdmi = &info->hdmi;
3630
3631 for (i = 0; i < svds_len; i++) {
3632 u8 vic = svd_to_vic(svds[i]);
3633 struct drm_display_mode *newmode;
3634
3635 if (!drm_valid_cea_vic(vic))
3636 continue;
3637
7befe621 3638 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
832d4f2f
SS		 3639 if (!newmode)
3640 break;
3641 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
3642 drm_mode_probed_add(connector, newmode);
3643 modes++;
3644 }
3645
3646 if (modes > 0)
3647 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3648 return modes;
3649}
3650
3651/*
3652 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap
3653 * @connector: connector corresponding to the HDMI sink
3654 * @vic: CEA vic for the video mode to be added in the map
3655 *
3656 * Makes an entry for a videomode in the YCBCR 420 bitmap
3657 */
3658static void
3659drm_add_cmdb_modes(struct drm_connector *connector, u8 svd)
3660{
3661 u8 vic = svd_to_vic(svd);
3662 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3663
3664 if (!drm_valid_cea_vic(vic))
3665 return;
3666
3667 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
3668}
3669
aff04ace
TW		 3670static int
3671do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
3672{
3673 int i, modes = 0;
832d4f2f 3674 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
aff04ace
TW		 3675
3676 for (i = 0; i < len; i++) {
3677 struct drm_display_mode *mode;
3678 mode = drm_display_mode_from_vic_index(connector, db, len, i);
3679 if (mode) {
832d4f2f
SS		 3680 /*
3681 * YCBCR420 capability block contains a bitmap which
3682 * gives the index of CEA modes from CEA VDB, which
3683 * can support YCBCR 420 sampling output also (apart
3684 * from RGB/YCBCR444 etc).
3685 * For example, if the bit 0 in bitmap is set,
3686 * first mode in VDB can support YCBCR420 output too.
3687 * Add YCBCR420 modes only if sink is HDMI 2.0 capable.
3688 */
3689 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i))
3690 drm_add_cmdb_modes(connector, db[i]);
3691
aff04ace
TW		 3692 drm_mode_probed_add(connector, mode);
3693 modes++;
54ac76f8
CS		 3694 }
3695 }
3696
3697 return modes;
3698}
3699
c858cfca
DL		 3700struct stereo_mandatory_mode {
3701 int width, height, vrefresh;
3702 unsigned int flags;
3703};
3704
3705static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
f7e121b7
DL		 3706 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3707 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
c858cfca
DL		 3708 { 1920, 1080, 50,
3709 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3710 { 1920, 1080, 60,
3711 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
f7e121b7
DL		 3712 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3713 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
3714 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3715 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
c858cfca
DL		 3716};
3717
3718static bool
3719stereo_match_mandatory(const struct drm_display_mode *mode,
3720 const struct stereo_mandatory_mode *stereo_mode)
3721{
3722 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
3723
3724 return mode->hdisplay == stereo_mode->width &&
3725 mode->vdisplay == stereo_mode->height &&
3726 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
3727 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
3728}
3729
c858cfca
DL		 3730static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
3731{
3732 struct drm_device *dev = connector->dev;
3733 const struct drm_display_mode *mode;
3734 struct list_head stereo_modes;
f7e121b7 3735 int modes = 0, i;
c858cfca
DL		 3736
3737 INIT_LIST_HEAD(&stereo_modes);
3738
3739 list_for_each_entry(mode, &connector->probed_modes, head) {
f7e121b7
DL		 3740 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
3741 const struct stereo_mandatory_mode *mandatory;
c858cfca
DL		 3742 struct drm_display_mode *new_mode;
3743
f7e121b7
DL		 3744 if (!stereo_match_mandatory(mode,
3745 &stereo_mandatory_modes[i]))
3746 continue;
c858cfca 3747
f7e121b7 3748 mandatory = &stereo_mandatory_modes[i];
c858cfca
DL		 3749 new_mode = drm_mode_duplicate(dev, mode);
3750 if (!new_mode)
3751 continue;
3752
f7e121b7 3753 new_mode->flags |= mandatory->flags;
c858cfca
DL		 3754 list_add_tail(&new_mode->head, &stereo_modes);
3755 modes++;
f7e121b7 3756 }
c858cfca
DL		 3757 }
3758
3759 list_splice_tail(&stereo_modes, &connector->probed_modes);
3760
3761 return modes;
3762}
3763
1deee8d7
DL		 3764static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
3765{
3766 struct drm_device *dev = connector->dev;
3767 struct drm_display_mode *newmode;
3768
d9278b4c 3769 if (!drm_valid_hdmi_vic(vic)) {
1deee8d7
DL		 3770 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
3771 return 0;
3772 }
3773
3774 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
3775 if (!newmode)
3776 return 0;
3777
3778 drm_mode_probed_add(connector, newmode);
3779
3780 return 1;
3781}
3782
fbf46025
TW		 3783static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
3784 const u8 *video_db, u8 video_len, u8 video_index)
3785{
fbf46025
TW		 3786 struct drm_display_mode *newmode;
3787 int modes = 0;
fbf46025
TW		 3788
3789 if (structure & (1 << 0)) {
aff04ace
TW		 3790 newmode = drm_display_mode_from_vic_index(connector, video_db,
3791 video_len,
3792 video_index);
fbf46025
TW		 3793 if (newmode) {
3794 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
3795 drm_mode_probed_add(connector, newmode);
3796 modes++;
3797 }
3798 }
3799 if (structure & (1 << 6)) {
aff04ace
TW		 3800 newmode = drm_display_mode_from_vic_index(connector, video_db,
3801 video_len,
3802 video_index);
fbf46025
TW		 3803 if (newmode) {
3804 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3805 drm_mode_probed_add(connector, newmode);
3806 modes++;
3807 }
3808 }
3809 if (structure & (1 << 8)) {
aff04ace
TW		 3810 newmode = drm_display_mode_from_vic_index(connector, video_db,
3811 video_len,
3812 video_index);
fbf46025 3813 if (newmode) {
89570eeb 3814 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
fbf46025
TW		 3815 drm_mode_probed_add(connector, newmode);
3816 modes++;
3817 }
3818 }
3819
3820 return modes;
3821}
3822
7ebe1963
LD		 3823/*
3824 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
3825 * @connector: connector corresponding to the HDMI sink
3826 * @db: start of the CEA vendor specific block
3827 * @len: length of the CEA block payload, ie. one can access up to db[len]
3828 *
c858cfca
DL		 3829 * Parses the HDMI VSDB looking for modes to add to @connector. This function
3830 * also adds the stereo 3d modes when applicable.
7ebe1963
LD		 3831 */
3832static int
fbf46025
TW		 3833do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
3834 const u8 *video_db, u8 video_len)
7ebe1963 3835{
f1781e9b 3836 struct drm_display_info *info = &connector->display_info;
0e5083aa 3837 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
fbf46025
TW		 3838 u8 vic_len, hdmi_3d_len = 0;
3839 u16 mask;
3840 u16 structure_all;
7ebe1963
LD		 3841
3842 if (len < 8)
3843 goto out;
3844
3845 /* no HDMI_Video_Present */
3846 if (!(db[8] & (1 << 5)))
3847 goto out;
3848
3849 /* Latency_Fields_Present */
3850 if (db[8] & (1 << 7))
3851 offset += 2;
3852
3853 /* I_Latency_Fields_Present */
3854 if (db[8] & (1 << 6))
3855 offset += 2;
3856
3857 /* the declared length is not long enough for the 2 first bytes
3858 * of additional video format capabilities */
c858cfca 3859 if (len < (8 + offset + 2))
7ebe1963
LD		 3860 goto out;
3861
c858cfca
DL		 3862 /* 3D_Present */
3863 offset++;
fbf46025 3864 if (db[8 + offset] & (1 << 7)) {
c858cfca
DL		 3865 modes += add_hdmi_mandatory_stereo_modes(connector);
3866
fbf46025
TW		 3867 /* 3D_Multi_present */
3868 multi_present = (db[8 + offset] & 0x60) >> 5;
3869 }
3870
c858cfca 3871 offset++;
7ebe1963 3872 vic_len = db[8 + offset] >> 5;
fbf46025 3873 hdmi_3d_len = db[8 + offset] & 0x1f;
7ebe1963
LD		 3874
3875 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
7ebe1963
LD		 3876 u8 vic;
3877
3878 vic = db[9 + offset + i];
1deee8d7 3879 modes += add_hdmi_mode(connector, vic);
7ebe1963 3880 }
fbf46025
TW		 3881 offset += 1 + vic_len;
3882
0e5083aa
TW		 3883 if (multi_present == 1)
3884 multi_len = 2;
3885 else if (multi_present == 2)
3886 multi_len = 4;
3887 else
3888 multi_len = 0;
fbf46025 3889
0e5083aa 3890 if (len < (8 + offset + hdmi_3d_len - 1))
fbf46025
TW		 3891 goto out;
3892
0e5083aa 3893 if (hdmi_3d_len < multi_len)
fbf46025
TW		 3894 goto out;
3895
0e5083aa
TW		 3896 if (multi_present == 1 || multi_present == 2) {
3897 /* 3D_Structure_ALL */
3898 structure_all = (db[8 + offset] << 8) | db[9 + offset];
fbf46025 3899
0e5083aa
TW		 3900 /* check if 3D_MASK is present */
3901 if (multi_present == 2)
3902 mask = (db[10 + offset] << 8) | db[11 + offset];
3903 else
3904 mask = 0xffff;
3905
3906 for (i = 0; i < 16; i++) {
3907 if (mask & (1 << i))
3908 modes += add_3d_struct_modes(connector,
3909 structure_all,
3910 video_db,
3911 video_len, i);
3912 }
3913 }
3914
3915 offset += multi_len;
3916
3917 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
3918 int vic_index;
3919 struct drm_display_mode *newmode = NULL;
3920 unsigned int newflag = 0;
3921 bool detail_present;
3922
3923 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
3924
3925 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
3926 break;
3927
3928 /* 2D_VIC_order_X */
3929 vic_index = db[8 + offset + i] >> 4;
3930
3931 /* 3D_Structure_X */
3932 switch (db[8 + offset + i] & 0x0f) {
3933 case 0:
3934 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
3935 break;
3936 case 6:
3937 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3938 break;
3939 case 8:
3940 /* 3D_Detail_X */
3941 if ((db[9 + offset + i] >> 4) == 1)
3942 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3943 break;
3944 }
3945
3946 if (newflag != 0) {
3947 newmode = drm_display_mode_from_vic_index(connector,
3948 video_db,
3949 video_len,
3950 vic_index);
3951
3952 if (newmode) {
3953 newmode->flags |= newflag;
3954 drm_mode_probed_add(connector, newmode);
3955 modes++;
3956 }
3957 }
3958
3959 if (detail_present)
3960 i++;
fbf46025 3961 }
7ebe1963
LD		 3962
3963out:
f1781e9b
VS		 3964 if (modes > 0)
3965 info->has_hdmi_infoframe = true;
7ebe1963
LD		 3966 return modes;
3967}
3968
9e50b9d5
VS		 3969static int
3970cea_db_payload_len(const u8 *db)
3971{
3972 return db[0] & 0x1f;
3973}
3974
87563fc0
SS		 3975static int
3976cea_db_extended_tag(const u8 *db)
3977{
3978 return db[1];
3979}
3980
9e50b9d5
VS		 3981static int
3982cea_db_tag(const u8 *db)
3983{
3984 return db[0] >> 5;
3985}
3986
3987static int
3988cea_revision(const u8 *cea)
3989{
3990 return cea[1];
3991}
3992
3993static int
3994cea_db_offsets(const u8 *cea, int *start, int *end)
3995{
e28ad544
AR		 3996 /* DisplayID CTA extension blocks and top-level CEA EDID
3997 * block header definitions differ in the following bytes:
3998 * 1) Byte 2 of the header specifies length differently,
3999 * 2) Byte 3 is only present in the CEA top level block.
4000 *
4001 * The different definitions for byte 2 follow.
4002 *
4003 * DisplayID CTA extension block defines byte 2 as:
4004 * Number of payload bytes
4005 *
4006 * CEA EDID block defines byte 2 as:
4007 * Byte number (decimal) within this block where the 18-byte
4008 * DTDs begin. If no non-DTD data is present in this extension
4009 * block, the value should be set to 04h (the byte after next).
4010 * If set to 00h, there are no DTDs present in this block and
4011 * no non-DTD data.
4012 */
4013 if (cea[0] == DATA_BLOCK_CTA) {
4014 *start = 3;
4015 *end = *start + cea[2];
4016 } else if (cea[0] == CEA_EXT) {
4017 /* Data block offset in CEA extension block */
4018 *start = 4;
4019 *end = cea[2];
4020 if (*end == 0)
4021 *end = 127;
4022 if (*end < 4 || *end > 127)
4023 return -ERANGE;
4024 } else {
c7581a41 4025 return -EOPNOTSUPP;
e28ad544
AR		 4026 }
4027
9e50b9d5
VS		 4028 return 0;
4029}
4030
7ebe1963
LD		 4031static bool cea_db_is_hdmi_vsdb(const u8 *db)
4032{
4033 int hdmi_id;
4034
4035 if (cea_db_tag(db) != VENDOR_BLOCK)
4036 return false;
4037
4038 if (cea_db_payload_len(db) < 5)
4039 return false;
4040
4041 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
4042
6cb3b7f1 4043 return hdmi_id == HDMI_IEEE_OUI;
7ebe1963
LD		 4044}
4045
50dd1bd1
TR		 4046static bool cea_db_is_hdmi_forum_vsdb(const u8 *db)
4047{
4048 unsigned int oui;
4049
4050 if (cea_db_tag(db) != VENDOR_BLOCK)
4051 return false;
4052
4053 if (cea_db_payload_len(db) < 7)
4054 return false;
4055
4056 oui = db[3] << 16 | db[2] << 8 | db[1];
4057
4058 return oui == HDMI_FORUM_IEEE_OUI;
4059}
4060
1581b2df
VS		 4061static bool cea_db_is_vcdb(const u8 *db)
4062{
4063 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4064 return false;
4065
4066 if (cea_db_payload_len(db) != 2)
4067 return false;
4068
4069 if (cea_db_extended_tag(db) != EXT_VIDEO_CAPABILITY_BLOCK)
4070 return false;
4071
4072 return true;
4073}
4074
832d4f2f
SS		 4075static bool cea_db_is_y420cmdb(const u8 *db)
4076{
4077 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4078 return false;
4079
4080 if (!cea_db_payload_len(db))
4081 return false;
4082
4083 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB)
4084 return false;
4085
4086 return true;
4087}
4088
4089static bool cea_db_is_y420vdb(const u8 *db)
4090{
4091 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4092 return false;
4093
4094 if (!cea_db_payload_len(db))
4095 return false;
4096
4097 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420)
4098 return false;
4099
4100 return true;
4101}
4102
9e50b9d5
VS		 4103#define for_each_cea_db(cea, i, start, end) \
4104 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
4105
832d4f2f
SS		 4106static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector,
4107 const u8 *db)
4108{
4109 struct drm_display_info *info = &connector->display_info;
4110 struct drm_hdmi_info *hdmi = &info->hdmi;
4111 u8 map_len = cea_db_payload_len(db) - 1;
4112 u8 count;
4113 u64 map = 0;
4114
4115 if (map_len == 0) {
4116 /* All CEA modes support ycbcr420 sampling also.*/
4117 hdmi->y420_cmdb_map = U64_MAX;
4118 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
4119 return;
4120 }
4121
4122 /*
4123 * This map indicates which of the existing CEA block modes
4124 * from VDB can support YCBCR420 output too. So if bit=0 is
4125 * set, first mode from VDB can support YCBCR420 output too.
4126 * We will parse and keep this map, before parsing VDB itself
4127 * to avoid going through the same block again and again.
4128 *
4129 * Spec is not clear about max possible size of this block.
4130 * Clamping max bitmap block size at 8 bytes. Every byte can
4131 * address 8 CEA modes, in this way this map can address
4132 * 8*8 = first 64 SVDs.
4133 */
4134 if (WARN_ON_ONCE(map_len > 8))
4135 map_len = 8;
4136
4137 for (count = 0; count < map_len; count++)
4138 map |= (u64)db[2 + count] << (8 * count);
4139
4140 if (map)
4141 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
4142
4143 hdmi->y420_cmdb_map = map;
4144}
4145
54ac76f8
CS		 4146static int
4147add_cea_modes(struct drm_connector *connector, struct edid *edid)
4148{
13ac3f55 4149 const u8 *cea = drm_find_cea_extension(edid);
fbf46025
TW		 4150 const u8 *db, *hdmi = NULL, *video = NULL;
4151 u8 dbl, hdmi_len, video_len = 0;
54ac76f8
CS		 4152 int modes = 0;
4153
9e50b9d5
VS		 4154 if (cea && cea_revision(cea) >= 3) {
4155 int i, start, end;
4156
4157 if (cea_db_offsets(cea, &start, &end))
4158 return 0;
4159
4160 for_each_cea_db(cea, i, start, end) {
4161 db = &cea[i];
4162 dbl = cea_db_payload_len(db);
4163
fbf46025
TW		 4164 if (cea_db_tag(db) == VIDEO_BLOCK) {
4165 video = db + 1;
4166 video_len = dbl;
4167 modes += do_cea_modes(connector, video, dbl);
832d4f2f 4168 } else if (cea_db_is_hdmi_vsdb(db)) {
c858cfca
DL		 4169 hdmi = db;
4170 hdmi_len = dbl;
832d4f2f
SS		 4171 } else if (cea_db_is_y420vdb(db)) {
4172 const u8 *vdb420 = &db[2];
4173
4174 /* Add 4:2:0(only) modes present in EDID */
4175 modes += do_y420vdb_modes(connector,
4176 vdb420,
4177 dbl - 1);
c858cfca 4178 }
54ac76f8
CS		 4179 }
4180 }
4181
c858cfca
DL		 4182 /*
4183 * We parse the HDMI VSDB after having added the cea modes as we will
4184 * be patching their flags when the sink supports stereo 3D.
4185 */
4186 if (hdmi)
fbf46025
TW		 4187 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
4188 video_len);
c858cfca 4189
54ac76f8
CS		 4190 return modes;
4191}
4192
fa3a7340
VS		 4193static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
4194{
4195 const struct drm_display_mode *cea_mode;
4196 int clock1, clock2, clock;
d9278b4c 4197 u8 vic;
fa3a7340
VS		 4198 const char *type;
4199
4c6bcf44
VS		 4200 /*
4201 * allow 5kHz clock difference either way to account for
4202 * the 10kHz clock resolution limit of detailed timings.
4203 */
d9278b4c
JN		 4204 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
4205 if (drm_valid_cea_vic(vic)) {
fa3a7340 4206 type = "CEA";
7befe621 4207 cea_mode = cea_mode_for_vic(vic);
fa3a7340
VS		 4208 clock1 = cea_mode->clock;
4209 clock2 = cea_mode_alternate_clock(cea_mode);
4210 } else {
d9278b4c
JN		 4211 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
4212 if (drm_valid_hdmi_vic(vic)) {
fa3a7340 4213 type = "HDMI";
d9278b4c 4214 cea_mode = &edid_4k_modes[vic];
fa3a7340
VS		 4215 clock1 = cea_mode->clock;
4216 clock2 = hdmi_mode_alternate_clock(cea_mode);
4217 } else {
4218 return;
4219 }
4220 }
4221
4222 /* pick whichever is closest */
4223 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
4224 clock = clock1;
4225 else
4226 clock = clock2;
4227
4228 if (mode->clock == clock)
4229 return;
4230
4231 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
d9278b4c 4232 type, vic, mode->clock, clock);
fa3a7340
VS		 4233 mode->clock = clock;
4234}
4235
e85959d6
US		 4236static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db)
4237{
4238 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4239 return false;
4240
4241 if (db[1] != HDR_STATIC_METADATA_BLOCK)
4242 return false;
4243
4244 if (cea_db_payload_len(db) < 3)
4245 return false;
4246
4247 return true;
4248}
4249
4250static uint8_t eotf_supported(const u8 *edid_ext)
4251{
4252 return edid_ext[2] &
4253 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
4254 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
b5e3eed1
VS		 4255 BIT(HDMI_EOTF_SMPTE_ST2084) |
4256 BIT(HDMI_EOTF_BT_2100_HLG));
e85959d6
US		 4257}
4258
4259static uint8_t hdr_metadata_type(const u8 *edid_ext)
4260{
4261 return edid_ext[3] &
4262 BIT(HDMI_STATIC_METADATA_TYPE1);
4263}
4264
4265static void
4266drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
4267{
4268 u16 len;
4269
4270 len = cea_db_payload_len(db);
4271
4272 connector->hdr_sink_metadata.hdmi_type1.eotf =
4273 eotf_supported(db);
4274 connector->hdr_sink_metadata.hdmi_type1.metadata_type =
4275 hdr_metadata_type(db);
4276
4277 if (len >= 4)
4278 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4];
4279 if (len >= 5)
4280 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5];
4281 if (len >= 6)
4282 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6];
4283}
4284
76adaa34 4285static void
23ebf8b9 4286drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
76adaa34 4287{
8504072a 4288 u8 len = cea_db_payload_len(db);
76adaa34 4289
f7da7785
JN		 4290 if (len >= 6 && (db[6] & (1 << 7)))
4291 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
8504072a
VS		 4292 if (len >= 8) {
4293 connector->latency_present[0] = db[8] >> 7;
4294 connector->latency_present[1] = (db[8] >> 6) & 1;
4295 }
4296 if (len >= 9)
4297 connector->video_latency[0] = db[9];
4298 if (len >= 10)
4299 connector->audio_latency[0] = db[10];
4300 if (len >= 11)
4301 connector->video_latency[1] = db[11];
4302 if (len >= 12)
4303 connector->audio_latency[1] = db[12];
76adaa34 4304
23ebf8b9
VS		 4305 DRM_DEBUG_KMS("HDMI: latency present %d %d, "
4306 "video latency %d %d, "
4307 "audio latency %d %d\n",
4308 connector->latency_present[0],
4309 connector->latency_present[1],
4310 connector->video_latency[0],
4311 connector->video_latency[1],
4312 connector->audio_latency[0],
4313 connector->audio_latency[1]);
76adaa34
WF		 4314}
4315
4316static void
4317monitor_name(struct detailed_timing *t, void *data)
4318{
a7a131ac
VS		 4319 if (!is_display_descriptor((const u8 *)t, EDID_DETAIL_MONITOR_NAME))
4320 return;
4321
4322 *(u8 **)data = t->data.other_data.data.str.str;
14f77fdd
VS		 4323}
4324
59f7c0fa
JB		 4325static int get_monitor_name(struct edid *edid, char name[13])
4326{
4327 char *edid_name = NULL;
4328 int mnl;
4329
4330 if (!edid || !name)
4331 return 0;
4332
4333 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name);
4334 for (mnl = 0; edid_name && mnl < 13; mnl++) {
4335 if (edid_name[mnl] == 0x0a)
4336 break;
4337
4338 name[mnl] = edid_name[mnl];
4339 }
4340
4341 return mnl;
4342}
4343
4344/**
4345 * drm_edid_get_monitor_name - fetch the monitor name from the edid
4346 * @edid: monitor EDID information
4347 * @name: pointer to a character array to hold the name of the monitor
4348 * @bufsize: The size of the name buffer (should be at least 14 chars.)
4349 *
4350 */
4351void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize)
4352{
4353 int name_length;
4354 char buf[13];
4355
4356 if (bufsize <= 0)
4357 return;
4358
4359 name_length = min(get_monitor_name(edid, buf), bufsize - 1);
4360 memcpy(name, buf, name_length);
4361 name[name_length] = '\0';
4362}
4363EXPORT_SYMBOL(drm_edid_get_monitor_name);
4364
42750d39
JN		 4365static void clear_eld(struct drm_connector *connector)
4366{
4367 memset(connector->eld, 0, sizeof(connector->eld));
4368
4369 connector->latency_present[0] = false;
4370 connector->latency_present[1] = false;
4371 connector->video_latency[0] = 0;
4372 connector->audio_latency[0] = 0;
4373 connector->video_latency[1] = 0;
4374 connector->audio_latency[1] = 0;
4375}
4376
79436a1c 4377/*
76adaa34
WF		 4378 * drm_edid_to_eld - build ELD from EDID
4379 * @connector: connector corresponding to the HDMI/DP sink
4380 * @edid: EDID to parse
4381 *
db6cf833 4382 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
1d1c3665 4383 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
76adaa34 4384 */
79436a1c 4385static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
76adaa34
WF		 4386{
4387 uint8_t *eld = connector->eld;
4388 u8 *cea;
76adaa34 4389 u8 *db;
7c018782 4390 int total_sad_count = 0;
76adaa34
WF		 4391 int mnl;
4392 int dbl;
4393
42750d39 4394 clear_eld(connector);
85c91580 4395
e9bd0b84
JN		 4396 if (!edid)
4397 return;
4398
76adaa34
WF		 4399 cea = drm_find_cea_extension(edid);
4400 if (!cea) {
4401 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
4402 return;
4403 }
4404
f7da7785
JN		 4405 mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
4406 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]);
59f7c0fa 4407
f7da7785
JN		 4408 eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT;
4409 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
76adaa34 4410
f7da7785 4411 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
76adaa34 4412
f7da7785
JN		 4413 eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0];
4414 eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1];
4415 eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0];
4416 eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1];
76adaa34 4417
9e50b9d5
VS		 4418 if (cea_revision(cea) >= 3) {
4419 int i, start, end;
4420
4421 if (cea_db_offsets(cea, &start, &end)) {
4422 start = 0;
4423 end = 0;
4424 }
4425
4426 for_each_cea_db(cea, i, start, end) {
4427 db = &cea[i];
4428 dbl = cea_db_payload_len(db);
4429
4430 switch (cea_db_tag(db)) {
7c018782
VS		 4431 int sad_count;
4432
a0ab734d
CS		 4433 case AUDIO_BLOCK:
4434 /* Audio Data Block, contains SADs */
7c018782
VS		 4435 sad_count = min(dbl / 3, 15 - total_sad_count);
4436 if (sad_count >= 1)
f7da7785 4437 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
7c018782
VS		 4438 &db[1], sad_count * 3);
4439 total_sad_count += sad_count;
a0ab734d
CS		 4440 break;
4441 case SPEAKER_BLOCK:
9e50b9d5
VS		 4442 /* Speaker Allocation Data Block */
4443 if (dbl >= 1)
f7da7785 4444 eld[DRM_ELD_SPEAKER] = db[1];
a0ab734d
CS		 4445 break;
4446 case VENDOR_BLOCK:
4447 /* HDMI Vendor-Specific Data Block */
14f77fdd 4448 if (cea_db_is_hdmi_vsdb(db))
23ebf8b9 4449 drm_parse_hdmi_vsdb_audio(connector, db);
a0ab734d
CS		 4450 break;
4451 default:
4452 break;
4453 }
76adaa34 4454 }
9e50b9d5 4455 }
f7da7785 4456 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
76adaa34 4457
1d1c3665
JN		 4458 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
4459 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4460 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
4461 else
4462 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
76adaa34 4463
938fd8aa
JN		 4464 eld[DRM_ELD_BASELINE_ELD_LEN] =
4465 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
4466
4467 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
7c018782 4468 drm_eld_size(eld), total_sad_count);
76adaa34 4469}
76adaa34 4470
fe214163
RM		 4471/**
4472 * drm_edid_to_sad - extracts SADs from EDID
4473 * @edid: EDID to parse
4474 * @sads: pointer that will be set to the extracted SADs
4475 *
4476 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
fe214163 4477 *
db6cf833
TR		 4478 * Note: The returned pointer needs to be freed using kfree().
4479 *
4480 * Return: The number of found SADs or negative number on error.
fe214163
RM		 4481 */
4482int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
4483{
4484 int count = 0;
4485 int i, start, end, dbl;
4486 u8 *cea;
4487
4488 cea = drm_find_cea_extension(edid);
4489 if (!cea) {
4490 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
42908007 4491 return 0;
fe214163
RM		 4492 }
4493
4494 if (cea_revision(cea) < 3) {
4495 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
42908007 4496 return 0;
fe214163
RM		 4497 }
4498
4499 if (cea_db_offsets(cea, &start, &end)) {
4500 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4501 return -EPROTO;
4502 }
4503
4504 for_each_cea_db(cea, i, start, end) {
4505 u8 *db = &cea[i];
4506
4507 if (cea_db_tag(db) == AUDIO_BLOCK) {
4508 int j;
4509 dbl = cea_db_payload_len(db);
4510
4511 count = dbl / 3; /* SAD is 3B */
4512 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
4513 if (!*sads)
4514 return -ENOMEM;
4515 for (j = 0; j < count; j++) {
4516 u8 *sad = &db[1 + j * 3];
4517
4518 (*sads)[j].format = (sad[0] & 0x78) >> 3;
4519 (*sads)[j].channels = sad[0] & 0x7;
4520 (*sads)[j].freq = sad[1] & 0x7F;
4521 (*sads)[j].byte2 = sad[2];
4522 }
4523 break;
4524 }
4525 }
4526
4527 return count;
4528}
4529EXPORT_SYMBOL(drm_edid_to_sad);
4530
d105f476
AD		 4531/**
4532 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
4533 * @edid: EDID to parse
4534 * @sadb: pointer to the speaker block
4535 *
4536 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
d105f476 4537 *
db6cf833
TR		 4538 * Note: The returned pointer needs to be freed using kfree().
4539 *
4540 * Return: The number of found Speaker Allocation Blocks or negative number on
4541 * error.
d105f476
AD		 4542 */
4543int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
4544{
4545 int count = 0;
4546 int i, start, end, dbl;
4547 const u8 *cea;
4548
4549 cea = drm_find_cea_extension(edid);
4550 if (!cea) {
4551 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
42908007 4552 return 0;
d105f476
AD		 4553 }
4554
4555 if (cea_revision(cea) < 3) {
4556 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
42908007 4557 return 0;
d105f476
AD		 4558 }
4559
4560 if (cea_db_offsets(cea, &start, &end)) {
4561 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4562 return -EPROTO;
4563 }
4564
4565 for_each_cea_db(cea, i, start, end) {
4566 const u8 *db = &cea[i];
4567
4568 if (cea_db_tag(db) == SPEAKER_BLOCK) {
4569 dbl = cea_db_payload_len(db);
4570
4571 /* Speaker Allocation Data Block */
4572 if (dbl == 3) {
89086bca 4573 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
618e3776
AD		 4574 if (!*sadb)
4575 return -ENOMEM;
d105f476
AD		 4576 count = dbl;
4577 break;
4578 }
4579 }
4580 }
4581
4582 return count;
4583}
4584EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
4585
76adaa34 4586/**
db6cf833 4587 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
76adaa34
WF		 4588 * @connector: connector associated with the HDMI/DP sink
4589 * @mode: the display mode
db6cf833
TR		 4590 *
4591 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
4592 * the sink doesn't support audio or video.
76adaa34
WF		 4593 */
4594int drm_av_sync_delay(struct drm_connector *connector,
3a818d35 4595 const struct drm_display_mode *mode)
76adaa34
WF		 4596{
4597 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
4598 int a, v;
4599
4600 if (!connector->latency_present[0])
4601 return 0;
4602 if (!connector->latency_present[1])
4603 i = 0;
4604
4605 a = connector->audio_latency[i];
4606 v = connector->video_latency[i];
4607
4608 /*
4609 * HDMI/DP sink doesn't support audio or video?
4610 */
4611 if (a == 255 || v == 255)
4612 return 0;
4613
4614 /*
4615 * Convert raw EDID values to millisecond.
4616 * Treat unknown latency as 0ms.
4617 */
4618 if (a)
4619 a = min(2 * (a - 1), 500);
4620 if (v)
4621 v = min(2 * (v - 1), 500);
4622
4623 return max(v - a, 0);
4624}
4625EXPORT_SYMBOL(drm_av_sync_delay);
4626
8fe9790d 4627/**
db6cf833 4628 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
8fe9790d
ZW		 4629 * @edid: monitor EDID information
4630 *
4631 * Parse the CEA extension according to CEA-861-B.
db6cf833
TR		 4632 *
4633 * Return: True if the monitor is HDMI, false if not or unknown.
8fe9790d
ZW		 4634 */
4635bool drm_detect_hdmi_monitor(struct edid *edid)
4636{
4637 u8 *edid_ext;
14f77fdd 4638 int i;
8fe9790d 4639 int start_offset, end_offset;
8fe9790d
ZW		 4640
4641 edid_ext = drm_find_cea_extension(edid);
4642 if (!edid_ext)
14f77fdd 4643 return false;
f23c20c8 4644
9e50b9d5 4645 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
14f77fdd 4646 return false;
f23c20c8
ML		 4647
4648 /*
4649 * Because HDMI identifier is in Vendor Specific Block,
4650 * search it from all data blocks of CEA extension.
4651 */
9e50b9d5 4652 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
14f77fdd
VS		 4653 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
4654 return true;
f23c20c8
ML		 4655 }
4656
14f77fdd 4657 return false;
f23c20c8
ML		 4658}
4659EXPORT_SYMBOL(drm_detect_hdmi_monitor);
4660
8fe9790d
ZW		 4661/**
4662 * drm_detect_monitor_audio - check monitor audio capability
fc66811c 4663 * @edid: EDID block to scan
8fe9790d
ZW		 4664 *
4665 * Monitor should have CEA extension block.
4666 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
4667 * audio' only. If there is any audio extension block and supported
4668 * audio format, assume at least 'basic audio' support, even if 'basic
4669 * audio' is not defined in EDID.
4670 *
db6cf833 4671 * Return: True if the monitor supports audio, false otherwise.
8fe9790d
ZW		 4672 */
4673bool drm_detect_monitor_audio(struct edid *edid)
4674{
4675 u8 *edid_ext;
4676 int i, j;
4677 bool has_audio = false;
4678 int start_offset, end_offset;
4679
4680 edid_ext = drm_find_cea_extension(edid);
4681 if (!edid_ext)
4682 goto end;
4683
4684 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
4685
4686 if (has_audio) {
4687 DRM_DEBUG_KMS("Monitor has basic audio support\n");
4688 goto end;
4689 }
4690
9e50b9d5
VS		 4691 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4692 goto end;
8fe9790d 4693
9e50b9d5
VS		 4694 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4695 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
8fe9790d 4696 has_audio = true;
9e50b9d5 4697 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
8fe9790d
ZW		 4698 DRM_DEBUG_KMS("CEA audio format %d\n",
4699 (edid_ext[i + j] >> 3) & 0xf);
4700 goto end;
4701 }
4702 }
4703end:
4704 return has_audio;
4705}
4706EXPORT_SYMBOL(drm_detect_monitor_audio);
4707
b1edd6a6 4708
c8127cf0
VS		 4709/**
4710 * drm_default_rgb_quant_range - default RGB quantization range
4711 * @mode: display mode
4712 *
4713 * Determine the default RGB quantization range for the mode,
4714 * as specified in CEA-861.
4715 *
4716 * Return: The default RGB quantization range for the mode
4717 */
4718enum hdmi_quantization_range
4719drm_default_rgb_quant_range(const struct drm_display_mode *mode)
4720{
4721 /* All CEA modes other than VIC 1 use limited quantization range. */
4722 return drm_match_cea_mode(mode) > 1 ?
4723 HDMI_QUANTIZATION_RANGE_LIMITED :
4724 HDMI_QUANTIZATION_RANGE_FULL;
4725}
4726EXPORT_SYMBOL(drm_default_rgb_quant_range);
4727
1581b2df
VS		 4728static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
4729{
4730 struct drm_display_info *info = &connector->display_info;
4731
4732 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]);
4733
4734 if (db[2] & EDID_CEA_VCDB_QS)
4735 info->rgb_quant_range_selectable = true;
4736}
4737
e6a9a2c3
SS		 4738static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
4739 const u8 *db)
4740{
4741 u8 dc_mask;
4742 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4743
4744 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
9068e02f 4745 hdmi->y420_dc_modes = dc_mask;
e6a9a2c3
SS		 4746}
4747
afa1c763
SS		 4748static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector,
4749 const u8 *hf_vsdb)
4750{
62c58af3
SS		 4751 struct drm_display_info *display = &connector->display_info;
4752 struct drm_hdmi_info *hdmi = &display->hdmi;
afa1c763 4753
f1781e9b
VS		 4754 display->has_hdmi_infoframe = true;
4755
afa1c763
SS		 4756 if (hf_vsdb[6] & 0x80) {
4757 hdmi->scdc.supported = true;
4758 if (hf_vsdb[6] & 0x40)
4759 hdmi->scdc.read_request = true;
4760 }
62c58af3
SS		 4761
4762 /*
4763 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
4764 * And as per the spec, three factors confirm this:
4765 * * Availability of a HF-VSDB block in EDID (check)
4766 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
4767 * * SCDC support available (let's check)
4768 * Lets check it out.
4769 */
4770
4771 if (hf_vsdb[5]) {
4772 /* max clock is 5000 KHz times block value */
4773 u32 max_tmds_clock = hf_vsdb[5] * 5000;
4774 struct drm_scdc *scdc = &hdmi->scdc;
4775
4776 if (max_tmds_clock > 340000) {
4777 display->max_tmds_clock = max_tmds_clock;
4778 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
4779 display->max_tmds_clock);
4780 }
4781
4782 if (scdc->supported) {
4783 scdc->scrambling.supported = true;
4784
dbe2d2bf 4785 /* Few sinks support scrambling for clocks < 340M */
62c58af3
SS		 4786 if ((hf_vsdb[6] & 0x8))
4787 scdc->scrambling.low_rates = true;
4788 }
4789 }
e6a9a2c3
SS		 4790
4791 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb);
afa1c763
SS		 4792}
4793
1cea146a
VS		 4794static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
4795 const u8 *hdmi)
d0c94692 4796{
1826750f 4797 struct drm_display_info *info = &connector->display_info;
d0c94692
MK		 4798 unsigned int dc_bpc = 0;
4799
1cea146a
VS		 4800 /* HDMI supports at least 8 bpc */
4801 info->bpc = 8;
d0c94692 4802
1cea146a
VS		 4803 if (cea_db_payload_len(hdmi) < 6)
4804 return;
4805
4806 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
4807 dc_bpc = 10;
4808 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
4809 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
4810 connector->name);
4811 }
4812
4813 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
4814 dc_bpc = 12;
4815 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
4816 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
4817 connector->name);
4818 }
4819
4820 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
4821 dc_bpc = 16;
4822 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
4823 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
4824 connector->name);
4825 }
4826
4827 if (dc_bpc == 0) {
4828 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
4829 connector->name);
4830 return;
4831 }
4832
4833 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
4834 connector->name, dc_bpc);
4835 info->bpc = dc_bpc;
d0c94692
MK		 4836
4837 /*
1cea146a
VS		 4838 * Deep color support mandates RGB444 support for all video
4839 * modes and forbids YCRCB422 support for all video modes per
4840 * HDMI 1.3 spec.
d0c94692 4841 */
1cea146a 4842 info->color_formats = DRM_COLOR_FORMAT_RGB444;
d0c94692 4843
1cea146a
VS		 4844 /* YCRCB444 is optional according to spec. */
4845 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
4846 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4847 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
4848 connector->name);
4849 }
d0c94692 4850
1cea146a
VS		 4851 /*
4852 * Spec says that if any deep color mode is supported at all,
4853 * then deep color 36 bit must be supported.
4854 */
4855 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
4856 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
4857 connector->name);
4858 }
4859}
d0c94692 4860
23ebf8b9
VS		 4861static void
4862drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
4863{
4864 struct drm_display_info *info = &connector->display_info;
4865 u8 len = cea_db_payload_len(db);
4866
4867 if (len >= 6)
4868 info->dvi_dual = db[6] & 1;
4869 if (len >= 7)
4870 info->max_tmds_clock = db[7] * 5000;
4871
4872 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
4873 "max TMDS clock %d kHz\n",
4874 info->dvi_dual,
4875 info->max_tmds_clock);
4876
4877 drm_parse_hdmi_deep_color_info(connector, db);
4878}
4879
1cea146a 4880static void drm_parse_cea_ext(struct drm_connector *connector,
170178fe 4881 const struct edid *edid)
1cea146a
VS		 4882{
4883 struct drm_display_info *info = &connector->display_info;
4884 const u8 *edid_ext;
4885 int i, start, end;
d0c94692 4886
1cea146a
VS		 4887 edid_ext = drm_find_cea_extension(edid);
4888 if (!edid_ext)
4889 return;
d0c94692 4890
1cea146a 4891 info->cea_rev = edid_ext[1];
d0c94692 4892
1cea146a
VS		 4893 /* The existence of a CEA block should imply RGB support */
4894 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4895 if (edid_ext[3] & EDID_CEA_YCRCB444)
4896 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4897 if (edid_ext[3] & EDID_CEA_YCRCB422)
4898 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4899
4900 if (cea_db_offsets(edid_ext, &start, &end))
4901 return;
4902
4903 for_each_cea_db(edid_ext, i, start, end) {
4904 const u8 *db = &edid_ext[i];
4905
23ebf8b9
VS		 4906 if (cea_db_is_hdmi_vsdb(db))
4907 drm_parse_hdmi_vsdb_video(connector, db);
afa1c763
SS		 4908 if (cea_db_is_hdmi_forum_vsdb(db))
4909 drm_parse_hdmi_forum_vsdb(connector, db);
832d4f2f
SS		 4910 if (cea_db_is_y420cmdb(db))
4911 drm_parse_y420cmdb_bitmap(connector, db);
1581b2df
VS		 4912 if (cea_db_is_vcdb(db))
4913 drm_parse_vcdb(connector, db);
e85959d6
US		 4914 if (cea_db_is_hdmi_hdr_metadata_block(db))
4915 drm_parse_hdr_metadata_block(connector, db);
1cea146a 4916 }
d0c94692
MK		 4917}
4918
170178fe
KP		 4919/* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
4920 * all of the values which would have been set from EDID
4921 */
4922void
4923drm_reset_display_info(struct drm_connector *connector)
4924{
4925 struct drm_display_info *info = &connector->display_info;
4926
4927 info->width_mm = 0;
4928 info->height_mm = 0;
4929
4930 info->bpc = 0;
4931 info->color_formats = 0;
4932 info->cea_rev = 0;
4933 info->max_tmds_clock = 0;
4934 info->dvi_dual = false;
4935 info->has_hdmi_infoframe = false;
1581b2df 4936 info->rgb_quant_range_selectable = false;
1f6b8eef 4937 memset(&info->hdmi, 0, sizeof(info->hdmi));
170178fe
KP		 4938
4939 info->non_desktop = 0;
4940}
170178fe
KP		 4941
4942u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid)
3b11228b 4943{
1826750f 4944 struct drm_display_info *info = &connector->display_info;
ebec9a7b 4945
170178fe
KP		 4946 u32 quirks = edid_get_quirks(edid);
4947
1f6b8eef
VS		 4948 drm_reset_display_info(connector);
4949
3b11228b
JB		 4950 info->width_mm = edid->width_cm * 10;
4951 info->height_mm = edid->height_cm * 10;
4952
66660d4c
DA		 4953 info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP);
4954
170178fe
KP		 4955 DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop);
4956
a988bc72 4957 if (edid->revision < 3)
170178fe 4958 return quirks;
3b11228b
JB		 4959
4960 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
170178fe 4961 return quirks;
3b11228b 4962
1cea146a 4963 drm_parse_cea_ext(connector, edid);
d0c94692 4964
210a021d
MK		 4965 /*
4966 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
4967 *
4968 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
4969 * tells us to assume 8 bpc color depth if the EDID doesn't have
4970 * extensions which tell otherwise.
4971 */
3bde449f
VS		 4972 if (info->bpc == 0 && edid->revision == 3 &&
4973 edid->input & DRM_EDID_DIGITAL_DFP_1_X) {
210a021d
MK		 4974 info->bpc = 8;
4975 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
4976 connector->name, info->bpc);
4977 }
4978
a988bc72
LPC		 4979 /* Only defined for 1.4 with digital displays */
4980 if (edid->revision < 4)
170178fe 4981 return quirks;
a988bc72 4982
3b11228b
JB		 4983 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
4984 case DRM_EDID_DIGITAL_DEPTH_6:
4985 info->bpc = 6;
4986 break;
4987 case DRM_EDID_DIGITAL_DEPTH_8:
4988 info->bpc = 8;
4989 break;
4990 case DRM_EDID_DIGITAL_DEPTH_10:
4991 info->bpc = 10;
4992 break;
4993 case DRM_EDID_DIGITAL_DEPTH_12:
4994 info->bpc = 12;
4995 break;
4996 case DRM_EDID_DIGITAL_DEPTH_14:
4997 info->bpc = 14;
4998 break;
4999 case DRM_EDID_DIGITAL_DEPTH_16:
5000 info->bpc = 16;
5001 break;
5002 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
5003 default:
5004 info->bpc = 0;
5005 break;
5006 }
da05a5a7 5007
d0c94692 5008 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
25933820 5009 connector->name, info->bpc);
d0c94692 5010
a988bc72 5011 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
ee58808d
LPC		 5012 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
5013 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
5014 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
5015 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
170178fe 5016 return quirks;
3b11228b
JB		 5017}
5018
c9729177
DA		 5019static int validate_displayid(u8 *displayid, int length, int idx)
5020{
5021 int i;
5022 u8 csum = 0;
5023 struct displayid_hdr *base;
5024
5025 base = (struct displayid_hdr *)&displayid[idx];
5026
5027 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",
5028 base->rev, base->bytes, base->prod_id, base->ext_count);
5029
5030 if (base->bytes + 5 > length - idx)
5031 return -EINVAL;
5032 for (i = idx; i <= base->bytes + 5; i++) {
5033 csum += displayid[i];
5034 }
5035 if (csum) {
813a7878 5036 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum);
c9729177
DA		 5037 return -EINVAL;
5038 }
5039 return 0;
5040}
5041
a39ed680
DA		 5042static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
5043 struct displayid_detailed_timings_1 *timings)
5044{
5045 struct drm_display_mode *mode;
5046 unsigned pixel_clock = (timings->pixel_clock[0] |
5047 (timings->pixel_clock[1] << 8) |
5048 (timings->pixel_clock[2] << 16));
5049 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
5050 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
5051 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
5052 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
5053 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
5054 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
5055 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
5056 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
5057 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
5058 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
5059 mode = drm_mode_create(dev);
5060 if (!mode)
5061 return NULL;
5062
5063 mode->clock = pixel_clock * 10;
5064 mode->hdisplay = hactive;
5065 mode->hsync_start = mode->hdisplay + hsync;
5066 mode->hsync_end = mode->hsync_start + hsync_width;
5067 mode->htotal = mode->hdisplay + hblank;
5068
5069 mode->vdisplay = vactive;
5070 mode->vsync_start = mode->vdisplay + vsync;
5071 mode->vsync_end = mode->vsync_start + vsync_width;
5072 mode->vtotal = mode->vdisplay + vblank;
5073
5074 mode->flags = 0;
5075 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
5076 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
5077 mode->type = DRM_MODE_TYPE_DRIVER;
5078
5079 if (timings->flags & 0x80)
5080 mode->type |= DRM_MODE_TYPE_PREFERRED;
5081 mode->vrefresh = drm_mode_vrefresh(mode);
5082 drm_mode_set_name(mode);
5083
5084 return mode;
5085}
5086
5087static int add_displayid_detailed_1_modes(struct drm_connector *connector,
5088 struct displayid_block *block)
5089{
5090 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
5091 int i;
5092 int num_timings;
5093 struct drm_display_mode *newmode;
5094 int num_modes = 0;
5095 /* blocks must be multiple of 20 bytes length */
5096 if (block->num_bytes % 20)
5097 return 0;
5098
5099 num_timings = block->num_bytes / 20;
5100 for (i = 0; i < num_timings; i++) {
5101 struct displayid_detailed_timings_1 *timings = &det->timings[i];
5102
5103 newmode = drm_mode_displayid_detailed(connector->dev, timings);
5104 if (!newmode)
5105 continue;
5106
5107 drm_mode_probed_add(connector, newmode);
5108 num_modes++;
5109 }
5110 return num_modes;
5111}
5112
5113static int add_displayid_detailed_modes(struct drm_connector *connector,
5114 struct edid *edid)
5115{
5116 u8 *displayid;
5117 int ret;
5118 int idx = 1;
5119 int length = EDID_LENGTH;
5120 struct displayid_block *block;
5121 int num_modes = 0;
5122
5123 displayid = drm_find_displayid_extension(edid);
5124 if (!displayid)
5125 return 0;
5126
5127 ret = validate_displayid(displayid, length, idx);
5128 if (ret)
5129 return 0;
5130
5131 idx += sizeof(struct displayid_hdr);
80d42db0 5132 for_each_displayid_db(displayid, block, idx, length) {
a39ed680
DA		 5133 switch (block->tag) {
5134 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
5135 num_modes += add_displayid_detailed_1_modes(connector, block);
5136 break;
5137 }
5138 }
5139 return num_modes;
5140}
5141
f453ba04
DA		 5142/**
5143 * drm_add_edid_modes - add modes from EDID data, if available
5144 * @connector: connector we're probing
db6cf833 5145 * @edid: EDID data
f453ba04 5146 *
b3c6c8bf 5147 * Add the specified modes to the connector's mode list. Also fills out the
c945b8c1
JN		 5148 * &drm_display_info structure and ELD in @connector with any information which
5149 * can be derived from the edid.
f453ba04 5150 *
db6cf833 5151 * Return: The number of modes added or 0 if we couldn't find any.
f453ba04
DA		 5152 */
5153int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
5154{
5155 int num_modes = 0;
5156 u32 quirks;
5157
5158 if (edid == NULL) {
c945b8c1 5159 clear_eld(connector);
f453ba04
DA		 5160 return 0;
5161 }
3c537889 5162 if (!drm_edid_is_valid(edid)) {
c945b8c1 5163 clear_eld(connector);
dcdb1674 5164 dev_warn(connector->dev->dev, "%s: EDID invalid.\n",
25933820 5165 connector->name);
f453ba04
DA		 5166 return 0;
5167 }
5168
c945b8c1
JN		 5169 drm_edid_to_eld(connector, edid);
5170
0f0f8708
SS		 5171 /*
5172 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
5173 * To avoid multiple parsing of same block, lets parse that map
5174 * from sink info, before parsing CEA modes.
5175 */
170178fe 5176 quirks = drm_add_display_info(connector, edid);
0f0f8708 5177
c867df70
AJ		 5178 /*
5179 * EDID spec says modes should be preferred in this order:
5180 * - preferred detailed mode
5181 * - other detailed modes from base block
5182 * - detailed modes from extension blocks
5183 * - CVT 3-byte code modes
5184 * - standard timing codes
5185 * - established timing codes
5186 * - modes inferred from GTF or CVT range information
5187 *
13931579 5188 * We get this pretty much right.
c867df70
AJ		 5189 *
5190 * XXX order for additional mode types in extension blocks?
5191 */
13931579
AJ		 5192 num_modes += add_detailed_modes(connector, edid, quirks);
5193 num_modes += add_cvt_modes(connector, edid);
c867df70
AJ		 5194 num_modes += add_standard_modes(connector, edid);
5195 num_modes += add_established_modes(connector, edid);
54ac76f8 5196 num_modes += add_cea_modes(connector, edid);
e6e79209 5197 num_modes += add_alternate_cea_modes(connector, edid);
a39ed680 5198 num_modes += add_displayid_detailed_modes(connector, edid);
4d53dc0c
VS		 5199 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
5200 num_modes += add_inferred_modes(connector, edid);
f453ba04
DA		 5201
5202 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
5203 edid_fixup_preferred(connector, quirks);
5204
e10aec65
MK		 5205 if (quirks & EDID_QUIRK_FORCE_6BPC)
5206 connector->display_info.bpc = 6;
5207
49d45a31
RM		 5208 if (quirks & EDID_QUIRK_FORCE_8BPC)
5209 connector->display_info.bpc = 8;
5210
e345da82
MK		 5211 if (quirks & EDID_QUIRK_FORCE_10BPC)
5212 connector->display_info.bpc = 10;
5213
bc5b9641
MK		 5214 if (quirks & EDID_QUIRK_FORCE_12BPC)
5215 connector->display_info.bpc = 12;
5216
f453ba04
DA		 5217 return num_modes;
5218}
5219EXPORT_SYMBOL(drm_add_edid_modes);
f0fda0a4
ZY		 5220
5221/**
5222 * drm_add_modes_noedid - add modes for the connectors without EDID
5223 * @connector: connector we're probing
5224 * @hdisplay: the horizontal display limit
5225 * @vdisplay: the vertical display limit
5226 *
5227 * Add the specified modes to the connector's mode list. Only when the
5228 * hdisplay/vdisplay is not beyond the given limit, it will be added.
5229 *
db6cf833 5230 * Return: The number of modes added or 0 if we couldn't find any.
f0fda0a4
ZY		 5231 */
5232int drm_add_modes_noedid(struct drm_connector *connector,
5233 int hdisplay, int vdisplay)
5234{
5235 int i, count, num_modes = 0;
b1f559ec 5236 struct drm_display_mode *mode;
f0fda0a4
ZY		 5237 struct drm_device *dev = connector->dev;
5238
fbb40b28 5239 count = ARRAY_SIZE(drm_dmt_modes);
f0fda0a4
ZY		 5240 if (hdisplay < 0)
5241 hdisplay = 0;
5242 if (vdisplay < 0)
5243 vdisplay = 0;
5244
5245 for (i = 0; i < count; i++) {
b1f559ec 5246 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
f0fda0a4
ZY		 5247 if (hdisplay && vdisplay) {
5248 /*
5249 * Only when two are valid, they will be used to check
5250 * whether the mode should be added to the mode list of
5251 * the connector.
5252 */
5253 if (ptr->hdisplay > hdisplay ||
5254 ptr->vdisplay > vdisplay)
5255 continue;
5256 }
f985dedb
AJ		 5257 if (drm_mode_vrefresh(ptr) > 61)
5258 continue;
f0fda0a4
ZY		 5259 mode = drm_mode_duplicate(dev, ptr);
5260 if (mode) {
5261 drm_mode_probed_add(connector, mode);
5262 num_modes++;
5263 }
5264 }
5265 return num_modes;
5266}
5267EXPORT_SYMBOL(drm_add_modes_noedid);
10a85120 5268
db6cf833
TR		 5269/**
5270 * drm_set_preferred_mode - Sets the preferred mode of a connector
5271 * @connector: connector whose mode list should be processed
5272 * @hpref: horizontal resolution of preferred mode
5273 * @vpref: vertical resolution of preferred mode
5274 *
5275 * Marks a mode as preferred if it matches the resolution specified by @hpref
5276 * and @vpref.
5277 */
3cf70daf
GH		 5278void drm_set_preferred_mode(struct drm_connector *connector,
5279 int hpref, int vpref)
5280{
5281 struct drm_display_mode *mode;
5282
5283 list_for_each_entry(mode, &connector->probed_modes, head) {
db6cf833 5284 if (mode->hdisplay == hpref &&
9d3de138 5285 mode->vdisplay == vpref)
3cf70daf
GH		 5286 mode->type |= DRM_MODE_TYPE_PREFERRED;
5287 }
5288}
5289EXPORT_SYMBOL(drm_set_preferred_mode);
5290
13d0add3
VS		 5291static bool is_hdmi2_sink(struct drm_connector *connector)
5292{
5293 /*
5294 * FIXME: sil-sii8620 doesn't have a connector around when
5295 * we need one, so we have to be prepared for a NULL connector.
5296 */
5297 if (!connector)
5298 return true;
5299
5300 return connector->display_info.hdmi.scdc.supported ||
5301 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420;
5302}
5303
2cdbfd66
US		 5304static inline bool is_eotf_supported(u8 output_eotf, u8 sink_eotf)
5305{
5306 return sink_eotf & BIT(output_eotf);
5307}
5308
5309/**
5310 * drm_hdmi_infoframe_set_hdr_metadata() - fill an HDMI DRM infoframe with
5311 * HDR metadata from userspace
5312 * @frame: HDMI DRM infoframe
6ac98829 5313 * @conn_state: Connector state containing HDR metadata
2cdbfd66
US		 5314 *
5315 * Return: 0 on success or a negative error code on failure.
5316 */
5317int
5318drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame,
5319 const struct drm_connector_state *conn_state)
5320{
5321 struct drm_connector *connector;
5322 struct hdr_output_metadata *hdr_metadata;
5323 int err;
5324
5325 if (!frame || !conn_state)
5326 return -EINVAL;
5327
5328 connector = conn_state->connector;
5329
5330 if (!conn_state->hdr_output_metadata)
5331 return -EINVAL;
5332
5333 hdr_metadata = conn_state->hdr_output_metadata->data;
5334
5335 if (!hdr_metadata || !connector)
5336 return -EINVAL;
5337
5338 /* Sink EOTF is Bit map while infoframe is absolute values */
5339 if (!is_eotf_supported(hdr_metadata->hdmi_metadata_type1.eotf,
5340 connector->hdr_sink_metadata.hdmi_type1.eotf)) {
5341 DRM_DEBUG_KMS("EOTF Not Supported\n");
5342 return -EINVAL;
5343 }
5344
5345 err = hdmi_drm_infoframe_init(frame);
5346 if (err < 0)
5347 return err;
5348
5349 frame->eotf = hdr_metadata->hdmi_metadata_type1.eotf;
5350 frame->metadata_type = hdr_metadata->hdmi_metadata_type1.metadata_type;
5351
5352 BUILD_BUG_ON(sizeof(frame->display_primaries) !=
5353 sizeof(hdr_metadata->hdmi_metadata_type1.display_primaries));
5354 BUILD_BUG_ON(sizeof(frame->white_point) !=
5355 sizeof(hdr_metadata->hdmi_metadata_type1.white_point));
5356
5357 memcpy(&frame->display_primaries,
5358 &hdr_metadata->hdmi_metadata_type1.display_primaries,
5359 sizeof(frame->display_primaries));
5360
5361 memcpy(&frame->white_point,
5362 &hdr_metadata->hdmi_metadata_type1.white_point,
5363 sizeof(frame->white_point));
5364
5365 frame->max_display_mastering_luminance =
5366 hdr_metadata->hdmi_metadata_type1.max_display_mastering_luminance;
5367 frame->min_display_mastering_luminance =
5368 hdr_metadata->hdmi_metadata_type1.min_display_mastering_luminance;
5369 frame->max_fall = hdr_metadata->hdmi_metadata_type1.max_fall;
5370 frame->max_cll = hdr_metadata->hdmi_metadata_type1.max_cll;
5371
5372 return 0;
5373}
5374EXPORT_SYMBOL(drm_hdmi_infoframe_set_hdr_metadata);
5375
949561eb
VS		 5376static u8 drm_mode_hdmi_vic(struct drm_connector *connector,
5377 const struct drm_display_mode *mode)
5378{
5379 bool has_hdmi_infoframe = connector ?
5380 connector->display_info.has_hdmi_infoframe : false;
5381
5382 if (!has_hdmi_infoframe)
5383 return 0;
5384
5385 /* No HDMI VIC when signalling 3D video format */
5386 if (mode->flags & DRM_MODE_FLAG_3D_MASK)
5387 return 0;
5388
5389 return drm_match_hdmi_mode(mode);
5390}
5391
cfd6f8c3
VS		 5392static u8 drm_mode_cea_vic(struct drm_connector *connector,
5393 const struct drm_display_mode *mode)
5394{
cfd6f8c3
VS		 5395 u8 vic;
5396
5397 /*
5398 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
5399 * we should send its VIC in vendor infoframes, else send the
5400 * VIC in AVI infoframes. Lets check if this mode is present in
5401 * HDMI 1.4b 4K modes
5402 */
949561eb 5403 if (drm_mode_hdmi_vic(connector, mode))
cfd6f8c3
VS		 5404 return 0;
5405
5406 vic = drm_match_cea_mode(mode);
5407
5408 /*
5409 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
5410 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
5411 * have to make sure we dont break HDMI 1.4 sinks.
5412 */
5413 if (!is_hdmi2_sink(connector) && vic > 64)
5414 return 0;
5415
5416 return vic;
5417}
5418
10a85120
TR		 5419/**
5420 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
5421 * data from a DRM display mode
5422 * @frame: HDMI AVI infoframe
13d0add3 5423 * @connector: the connector
10a85120
TR		 5424 * @mode: DRM display mode
5425 *
db6cf833 5426 * Return: 0 on success or a negative error code on failure.
10a85120
TR		 5427 */
5428int
5429drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
13d0add3
VS		 5430 struct drm_connector *connector,
5431 const struct drm_display_mode *mode)
10a85120 5432{
a9c266c2 5433 enum hdmi_picture_aspect picture_aspect;
d2b43473 5434 u8 vic, hdmi_vic;
10a85120
TR		 5435 int err;
5436
5437 if (!frame || !mode)
5438 return -EINVAL;
5439
5440 err = hdmi_avi_infoframe_init(frame);
5441 if (err < 0)
5442 return err;
5443
bf02db99
DL		 5444 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
5445 frame->pixel_repeat = 1;
5446
d2b43473
WL		 5447 vic = drm_mode_cea_vic(connector, mode);
5448 hdmi_vic = drm_mode_hdmi_vic(connector, mode);
0c1f528c 5449
10a85120 5450 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
0967e6a5 5451
50525c33
SL		 5452 /*
5453 * As some drivers don't support atomic, we can't use connector state.
5454 * So just initialize the frame with default values, just the same way
5455 * as it's done with other properties here.
5456 */
5457 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
5458 frame->itc = 0;
5459
69ab6d35
VK		 5460 /*
5461 * Populate picture aspect ratio from either
d2b43473 5462 * user input (if specified) or from the CEA/HDMI mode lists.
69ab6d35 5463 */
a9c266c2 5464 picture_aspect = mode->picture_aspect_ratio;
d2b43473
WL		 5465 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) {
5466 if (vic)
5467 picture_aspect = drm_get_cea_aspect_ratio(vic);
5468 else if (hdmi_vic)
5469 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic);
5470 }
0967e6a5 5471
a9c266c2
VS		 5472 /*
5473 * The infoframe can't convey anything but none, 4:3
5474 * and 16:9, so if the user has asked for anything else
5475 * we can only satisfy it by specifying the right VIC.
5476 */
5477 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
d2b43473
WL		 5478 if (vic) {
5479 if (picture_aspect != drm_get_cea_aspect_ratio(vic))
5480 return -EINVAL;
5481 } else if (hdmi_vic) {
5482 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic))
5483 return -EINVAL;
5484 } else {
a9c266c2 5485 return -EINVAL;
d2b43473
WL		 5486 }
5487
a9c266c2
VS		 5488 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
5489 }
5490
d2b43473 5491 frame->video_code = vic;
a9c266c2 5492 frame->picture_aspect = picture_aspect;
10a85120 5493 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
24d01805 5494 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
10a85120
TR		 5495
5496 return 0;
5497}
5498EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
83dd0008 5499
0d68b887
US		 5500/* HDMI Colorspace Spec Definitions */
5501#define FULL_COLORIMETRY_MASK 0x1FF
5502#define NORMAL_COLORIMETRY_MASK 0x3
5503#define EXTENDED_COLORIMETRY_MASK 0x7
5504#define EXTENDED_ACE_COLORIMETRY_MASK 0xF
5505
5506#define C(x) ((x) << 0)
5507#define EC(x) ((x) << 2)
5508#define ACE(x) ((x) << 5)
5509
5510#define HDMI_COLORIMETRY_NO_DATA 0x0
5511#define HDMI_COLORIMETRY_SMPTE_170M_YCC (C(1) | EC(0) | ACE(0))
5512#define HDMI_COLORIMETRY_BT709_YCC (C(2) | EC(0) | ACE(0))
5513#define HDMI_COLORIMETRY_XVYCC_601 (C(3) | EC(0) | ACE(0))
5514#define HDMI_COLORIMETRY_XVYCC_709 (C(3) | EC(1) | ACE(0))
5515#define HDMI_COLORIMETRY_SYCC_601 (C(3) | EC(2) | ACE(0))
5516#define HDMI_COLORIMETRY_OPYCC_601 (C(3) | EC(3) | ACE(0))
5517#define HDMI_COLORIMETRY_OPRGB (C(3) | EC(4) | ACE(0))
5518#define HDMI_COLORIMETRY_BT2020_CYCC (C(3) | EC(5) | ACE(0))
5519#define HDMI_COLORIMETRY_BT2020_RGB (C(3) | EC(6) | ACE(0))
5520#define HDMI_COLORIMETRY_BT2020_YCC (C(3) | EC(6) | ACE(0))
5521#define HDMI_COLORIMETRY_DCI_P3_RGB_D65 (C(3) | EC(7) | ACE(0))
5522#define HDMI_COLORIMETRY_DCI_P3_RGB_THEATER (C(3) | EC(7) | ACE(1))
5523
5524static const u32 hdmi_colorimetry_val[] = {
5525 [DRM_MODE_COLORIMETRY_NO_DATA] = HDMI_COLORIMETRY_NO_DATA,
5526 [DRM_MODE_COLORIMETRY_SMPTE_170M_YCC] = HDMI_COLORIMETRY_SMPTE_170M_YCC,
5527 [DRM_MODE_COLORIMETRY_BT709_YCC] = HDMI_COLORIMETRY_BT709_YCC,
5528 [DRM_MODE_COLORIMETRY_XVYCC_601] = HDMI_COLORIMETRY_XVYCC_601,
5529 [DRM_MODE_COLORIMETRY_XVYCC_709] = HDMI_COLORIMETRY_XVYCC_709,
5530 [DRM_MODE_COLORIMETRY_SYCC_601] = HDMI_COLORIMETRY_SYCC_601,
5531 [DRM_MODE_COLORIMETRY_OPYCC_601] = HDMI_COLORIMETRY_OPYCC_601,
5532 [DRM_MODE_COLORIMETRY_OPRGB] = HDMI_COLORIMETRY_OPRGB,
5533 [DRM_MODE_COLORIMETRY_BT2020_CYCC] = HDMI_COLORIMETRY_BT2020_CYCC,
5534 [DRM_MODE_COLORIMETRY_BT2020_RGB] = HDMI_COLORIMETRY_BT2020_RGB,
5535 [DRM_MODE_COLORIMETRY_BT2020_YCC] = HDMI_COLORIMETRY_BT2020_YCC,
5536};
5537
5538#undef C
5539#undef EC
5540#undef ACE
5541
5542/**
5543 * drm_hdmi_avi_infoframe_colorspace() - fill the HDMI AVI infoframe
5544 * colorspace information
5545 * @frame: HDMI AVI infoframe
5546 * @conn_state: connector state
5547 */
5548void
5549drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame,
5550 const struct drm_connector_state *conn_state)
5551{
5552 u32 colorimetry_val;
5553 u32 colorimetry_index = conn_state->colorspace & FULL_COLORIMETRY_MASK;
5554
5555 if (colorimetry_index >= ARRAY_SIZE(hdmi_colorimetry_val))
5556 colorimetry_val = HDMI_COLORIMETRY_NO_DATA;
5557 else
5558 colorimetry_val = hdmi_colorimetry_val[colorimetry_index];
5559
5560 frame->colorimetry = colorimetry_val & NORMAL_COLORIMETRY_MASK;
5561 /*
5562 * ToDo: Extend it for ACE formats as well. Modify the infoframe
5563 * structure and extend it in drivers/video/hdmi
5564 */
5565 frame->extended_colorimetry = (colorimetry_val >> 2) &
5566 EXTENDED_COLORIMETRY_MASK;
5567}
5568EXPORT_SYMBOL(drm_hdmi_avi_infoframe_colorspace);
5569
a2ce26f8
VS		 5570/**
5571 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
5572 * quantization range information
5573 * @frame: HDMI AVI infoframe
13d0add3 5574 * @connector: the connector
779c4c28 5575 * @mode: DRM display mode
a2ce26f8 5576 * @rgb_quant_range: RGB quantization range (Q)
a2ce26f8
VS		 5577 */
5578void
5579drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
13d0add3 5580 struct drm_connector *connector,
779c4c28 5581 const struct drm_display_mode *mode,
1581b2df 5582 enum hdmi_quantization_range rgb_quant_range)
a2ce26f8 5583{
1581b2df
VS		 5584 const struct drm_display_info *info = &connector->display_info;
5585
a2ce26f8
VS		 5586 /*
5587 * CEA-861:
5588 * "A Source shall not send a non-zero Q value that does not correspond
5589 * to the default RGB Quantization Range for the transmitted Picture
5590 * unless the Sink indicates support for the Q bit in a Video
5591 * Capabilities Data Block."
779c4c28
VS		 5592 *
5593 * HDMI 2.0 recommends sending non-zero Q when it does match the
5594 * default RGB quantization range for the mode, even when QS=0.
a2ce26f8 5595 */
1581b2df 5596 if (info->rgb_quant_range_selectable ||
779c4c28 5597 rgb_quant_range == drm_default_rgb_quant_range(mode))
a2ce26f8
VS		 5598 frame->quantization_range = rgb_quant_range;
5599 else
5600 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
fcc8a22c
VS		 5601
5602 /*
5603 * CEA-861-F:
5604 * "When transmitting any RGB colorimetry, the Source should set the
5605 * YQ-field to match the RGB Quantization Range being transmitted
5606 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
5607 * set YQ=1) and the Sink shall ignore the YQ-field."
9271c0ca
VS		 5608 *
5609 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
5610 * by non-zero YQ when receiving RGB. There doesn't seem to be any
5611 * good way to tell which version of CEA-861 the sink supports, so
5612 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
5613 * on on CEA-861-F.
fcc8a22c 5614 */
13d0add3 5615 if (!is_hdmi2_sink(connector) ||
9271c0ca 5616 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
fcc8a22c
VS		 5617 frame->ycc_quantization_range =
5618 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
5619 else
5620 frame->ycc_quantization_range =
5621 HDMI_YCC_QUANTIZATION_RANGE_FULL;
a2ce26f8
VS		 5622}
5623EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
5624
076d9a5d
VS		 5625/**
5626 * drm_hdmi_avi_infoframe_bars() - fill the HDMI AVI infoframe
5627 * bar information
5628 * @frame: HDMI AVI infoframe
5629 * @conn_state: connector state
5630 */
5631void
5632drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe *frame,
5633 const struct drm_connector_state *conn_state)
5634{
5635 frame->right_bar = conn_state->tv.margins.right;
5636 frame->left_bar = conn_state->tv.margins.left;
5637 frame->top_bar = conn_state->tv.margins.top;
5638 frame->bottom_bar = conn_state->tv.margins.bottom;
5639}
5640EXPORT_SYMBOL(drm_hdmi_avi_infoframe_bars);
5641
4eed4a0a
DL		 5642static enum hdmi_3d_structure
5643s3d_structure_from_display_mode(const struct drm_display_mode *mode)
5644{
5645 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
5646
5647 switch (layout) {
5648 case DRM_MODE_FLAG_3D_FRAME_PACKING:
5649 return HDMI_3D_STRUCTURE_FRAME_PACKING;
5650 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
5651 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
5652 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
5653 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
5654 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
5655 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
5656 case DRM_MODE_FLAG_3D_L_DEPTH:
5657 return HDMI_3D_STRUCTURE_L_DEPTH;
5658 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
5659 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
5660 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
5661 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
5662 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
5663 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
5664 default:
5665 return HDMI_3D_STRUCTURE_INVALID;
5666 }
5667}
5668
83dd0008
LD		 5669/**
5670 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
5671 * data from a DRM display mode
5672 * @frame: HDMI vendor infoframe
f1781e9b 5673 * @connector: the connector
83dd0008
LD		 5674 * @mode: DRM display mode
5675 *
5676 * Note that there's is a need to send HDMI vendor infoframes only when using a
5677 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
5678 * function will return -EINVAL, error that can be safely ignored.
5679 *
db6cf833 5680 * Return: 0 on success or a negative error code on failure.
83dd0008
LD		 5681 */
5682int
5683drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
f1781e9b 5684 struct drm_connector *connector,
83dd0008
LD		 5685 const struct drm_display_mode *mode)
5686{
f1781e9b
VS		 5687 /*
5688 * FIXME: sil-sii8620 doesn't have a connector around when
5689 * we need one, so we have to be prepared for a NULL connector.
5690 */
5691 bool has_hdmi_infoframe = connector ?
5692 connector->display_info.has_hdmi_infoframe : false;
83dd0008 5693 int err;
83dd0008
LD		 5694
5695 if (!frame || !mode)
5696 return -EINVAL;
5697
f1781e9b
VS		 5698 if (!has_hdmi_infoframe)
5699 return -EINVAL;
5700
949561eb
VS		 5701 err = hdmi_vendor_infoframe_init(frame);
5702 if (err < 0)
5703 return err;
4eed4a0a 5704
f1781e9b
VS		 5705 /*
5706 * Even if it's not absolutely necessary to send the infoframe
5707 * (ie.vic==0 and s3d_struct==0) we will still send it if we
5708 * know that the sink can handle it. This is based on a
5709 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
5710 * have trouble realizing that they shuld switch from 3D to 2D
5711 * mode if the source simply stops sending the infoframe when
5712 * it wants to switch from 3D to 2D.
5713 */
949561eb 5714 frame->vic = drm_mode_hdmi_vic(connector, mode);
f1781e9b 5715 frame->s3d_struct = s3d_structure_from_display_mode(mode);
83dd0008
LD		 5716
5717 return 0;
5718}
5719EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
40d9b043 5720
5e546cd5
DA		 5721static int drm_parse_tiled_block(struct drm_connector *connector,
5722 struct displayid_block *block)
5723{
5724 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
5725 u16 w, h;
5726 u8 tile_v_loc, tile_h_loc;
5727 u8 num_v_tile, num_h_tile;
5728 struct drm_tile_group *tg;
5729
5730 w = tile->tile_size[0] | tile->tile_size[1] << 8;
5731 h = tile->tile_size[2] | tile->tile_size[3] << 8;
5732
5733 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
5734 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
5735 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
5736 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
5737
5738 connector->has_tile = true;
5739 if (tile->tile_cap & 0x80)
5740 connector->tile_is_single_monitor = true;
5741
5742 connector->num_h_tile = num_h_tile + 1;
5743 connector->num_v_tile = num_v_tile + 1;
5744 connector->tile_h_loc = tile_h_loc;
5745 connector->tile_v_loc = tile_v_loc;
5746 connector->tile_h_size = w + 1;
5747 connector->tile_v_size = h + 1;
5748
5749 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
5750 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
5751 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
5752 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
5753 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
5754
5755 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
5756 if (!tg) {
5757 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
5758 }
5759 if (!tg)
5760 return -ENOMEM;
5761
5762 if (connector->tile_group != tg) {
5763 /* if we haven't got a pointer,
5764 take the reference, drop ref to old tile group */
5765 if (connector->tile_group) {
5766 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5767 }
5768 connector->tile_group = tg;
5769 } else
5770 /* if same tile group, then release the ref we just took. */
5771 drm_mode_put_tile_group(connector->dev, tg);
5772 return 0;
5773}
5774
40d9b043
DA		 5775static int drm_parse_display_id(struct drm_connector *connector,
5776 u8 *displayid, int length,
5777 bool is_edid_extension)
5778{
5779 /* if this is an EDID extension the first byte will be 0x70 */
5780 int idx = 0;
40d9b043 5781 struct displayid_block *block;
5e546cd5 5782 int ret;
40d9b043
DA		 5783
5784 if (is_edid_extension)
5785 idx = 1;
5786
c9729177
DA		 5787 ret = validate_displayid(displayid, length, idx);
5788 if (ret)
5789 return ret;
40d9b043 5790
3a4a2ea3 5791 idx += sizeof(struct displayid_hdr);
80d42db0 5792 for_each_displayid_db(displayid, block, idx, length) {
3a4a2ea3
TB		 5793 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n",
5794 block->tag, block->rev, block->num_bytes);
5795
5796 switch (block->tag) {
5797 case DATA_BLOCK_TILED_DISPLAY:
5798 ret = drm_parse_tiled_block(connector, block);
5799 if (ret)
5800 return ret;
5801 break;
a39ed680
DA		 5802 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
5803 /* handled in mode gathering code. */
5804 break;
e28ad544
AR		 5805 case DATA_BLOCK_CTA:
5806 /* handled in the cea parser code. */
5807 break;
3a4a2ea3
TB		 5808 default:
5809 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag);
5810 break;
5811 }
40d9b043
DA		 5812 }
5813 return 0;
5814}
5815
5816static void drm_get_displayid(struct drm_connector *connector,
5817 struct edid *edid)
5818{
5819 void *displayid = NULL;
5820 int ret;
5821 connector->has_tile = false;
5822 displayid = drm_find_displayid_extension(edid);
5823 if (!displayid) {
5824 /* drop reference to any tile group we had */
5825 goto out_drop_ref;
5826 }
5827
5828 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true);
5829 if (ret < 0)
5830 goto out_drop_ref;
5831 if (!connector->has_tile)
5832 goto out_drop_ref;
5833 return;
5834out_drop_ref:
5835 if (connector->tile_group) {
5836 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5837 connector->tile_group = NULL;
5838 }
5839 return;
5840}
Linux 6.x block layer and io_uring tree(s)