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drm/edid/firmware: rename drm_load_edid_firmware() to drm_edid_load_firmware()
[linux-2.6-block.git] / drivers / gpu / drm / drm_edid.c
CommitLineData
f453ba04
DA		 1/*
2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
61e57a8d 5 * Copyright 2010 Red Hat, Inc.
f453ba04
DA		 6 *
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
8 * FB layer.
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 */
9c79edec 30
18a9cbbe 31#include <linux/bitfield.h>
10a85120 32#include <linux/hdmi.h>
f453ba04 33#include <linux/i2c.h>
9c79edec 34#include <linux/kernel.h>
47819ba2 35#include <linux/module.h>
36b73b05 36#include <linux/pci.h>
9c79edec 37#include <linux/slab.h>
5cb8eaa2 38#include <linux/vga_switcheroo.h>
9c79edec
JN		 39
40#include <drm/drm_displayid.h>
41#include <drm/drm_drv.h>
760285e7 42#include <drm/drm_edid.h>
9338203c 43#include <drm/drm_encoder.h>
9c79edec 44#include <drm/drm_print.h>
f453ba04 45
969218fe
TI		 46#include "drm_crtc_internal.h"
47
37eab1fe
JN		 48static int oui(u8 first, u8 second, u8 third)
49{
50 return (first << 16) | (second << 8) | third;
51}
52
d1ff6409
AJ		 53#define EDID_EST_TIMINGS 16
54#define EDID_STD_TIMINGS 8
55#define EDID_DETAILED_TIMINGS 4
f453ba04
DA		 56
57/*
58 * EDID blocks out in the wild have a variety of bugs, try to collect
59 * them here (note that userspace may work around broken monitors first,
60 * but fixes should make their way here so that the kernel "just works"
61 * on as many displays as possible).
62 */
63
64/* First detailed mode wrong, use largest 60Hz mode */
65#define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
66/* Reported 135MHz pixel clock is too high, needs adjustment */
67#define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
68/* Prefer the largest mode at 75 Hz */
69#define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
70/* Detail timing is in cm not mm */
71#define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
72/* Detailed timing descriptors have bogus size values, so just take the
73 * maximum size and use that.
74 */
75#define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
f453ba04
DA		 76/* use +hsync +vsync for detailed mode */
77#define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
bc42aabc
AJ		 78/* Force reduced-blanking timings for detailed modes */
79#define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
49d45a31
RM		 80/* Force 8bpc */
81#define EDID_QUIRK_FORCE_8BPC (1 << 8)
bc5b9641
MK		 82/* Force 12bpc */
83#define EDID_QUIRK_FORCE_12BPC (1 << 9)
e10aec65
MK		 84/* Force 6bpc */
85#define EDID_QUIRK_FORCE_6BPC (1 << 10)
e345da82
MK		 86/* Force 10bpc */
87#define EDID_QUIRK_FORCE_10BPC (1 << 11)
66660d4c
DA		 88/* Non desktop display (i.e. HMD) */
89#define EDID_QUIRK_NON_DESKTOP (1 << 12)
3c537889 90
2869f599
PZ		 91#define MICROSOFT_IEEE_OUI 0xca125c
92
13931579
AJ		 93struct detailed_mode_closure {
94 struct drm_connector *connector;
dd0f4470 95 const struct drm_edid *drm_edid;
13931579
AJ		 96 bool preferred;
97 u32 quirks;
98 int modes;
99};
f453ba04 100
5c61259e
ZY		 101#define LEVEL_DMT 0
102#define LEVEL_GTF 1
7a374350
AJ		 103#define LEVEL_GTF2 2
104#define LEVEL_CVT 3
5c61259e 105
7d1be0a0 106#define EDID_QUIRK(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _quirks) \
e8de4d55 107{ \
7d1be0a0
DA		 108 .panel_id = drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, \
109 product_id), \
e8de4d55
DA		 110 .quirks = _quirks \
111}
112
23c4cfbd 113static const struct edid_quirk {
e8de4d55 114 u32 panel_id;
f453ba04
DA		 115 u32 quirks;
116} edid_quirk_list[] = {
117 /* Acer AL1706 */
7d1be0a0 118 EDID_QUIRK('A', 'C', 'R', 44358, EDID_QUIRK_PREFER_LARGE_60),
f453ba04 119 /* Acer F51 */
7d1be0a0 120 EDID_QUIRK('A', 'P', 'I', 0x7602, EDID_QUIRK_PREFER_LARGE_60),
f453ba04 121
e10aec65 122 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
7d1be0a0 123 EDID_QUIRK('A', 'E', 'O', 0, EDID_QUIRK_FORCE_6BPC),
e10aec65 124
0711a43b 125 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
7d1be0a0 126 EDID_QUIRK('B', 'O', 'E', 0x78b, EDID_QUIRK_FORCE_6BPC),
0711a43b 127
06998a75 128 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
7d1be0a0 129 EDID_QUIRK('C', 'P', 'T', 0x17df, EDID_QUIRK_FORCE_6BPC),
06998a75 130
25da7504 131 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
7d1be0a0 132 EDID_QUIRK('S', 'D', 'C', 0x3652, EDID_QUIRK_FORCE_6BPC),
25da7504 133
922dceff 134 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
7d1be0a0 135 EDID_QUIRK('B', 'O', 'E', 0x0771, EDID_QUIRK_FORCE_6BPC),
922dceff 136
f453ba04 137 /* Belinea 10 15 55 */
7d1be0a0
DA		 138 EDID_QUIRK('M', 'A', 'X', 1516, EDID_QUIRK_PREFER_LARGE_60),
139 EDID_QUIRK('M', 'A', 'X', 0x77e, EDID_QUIRK_PREFER_LARGE_60),
f453ba04
DA		 140
141 /* Envision Peripherals, Inc. EN-7100e */
7d1be0a0 142 EDID_QUIRK('E', 'P', 'I', 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH),
ba1163de 143 /* Envision EN2028 */
7d1be0a0 144 EDID_QUIRK('E', 'P', 'I', 8232, EDID_QUIRK_PREFER_LARGE_60),
f453ba04
DA		 145
146 /* Funai Electronics PM36B */
7d1be0a0 147 EDID_QUIRK('F', 'C', 'M', 13600, EDID_QUIRK_PREFER_LARGE_75 |
e8de4d55 148 EDID_QUIRK_DETAILED_IN_CM),
f453ba04 149
e345da82 150 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
7d1be0a0 151 EDID_QUIRK('L', 'G', 'D', 764, EDID_QUIRK_FORCE_10BPC),
e345da82 152
f453ba04 153 /* LG Philips LCD LP154W01-A5 */
7d1be0a0
DA		 154 EDID_QUIRK('L', 'P', 'L', 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
155 EDID_QUIRK('L', 'P', 'L', 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
f453ba04 156
f453ba04 157 /* Samsung SyncMaster 205BW. Note: irony */
7d1be0a0 158 EDID_QUIRK('S', 'A', 'M', 541, EDID_QUIRK_DETAILED_SYNC_PP),
f453ba04 159 /* Samsung SyncMaster 22[5-6]BW */
7d1be0a0
DA		 160 EDID_QUIRK('S', 'A', 'M', 596, EDID_QUIRK_PREFER_LARGE_60),
161 EDID_QUIRK('S', 'A', 'M', 638, EDID_QUIRK_PREFER_LARGE_60),
bc42aabc 162
bc5b9641 163 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
7d1be0a0 164 EDID_QUIRK('S', 'N', 'Y', 0x2541, EDID_QUIRK_FORCE_12BPC),
bc5b9641 165
bc42aabc 166 /* ViewSonic VA2026w */
7d1be0a0 167 EDID_QUIRK('V', 'S', 'C', 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING),
118bdbd8
AD		 168
169 /* Medion MD 30217 PG */
7d1be0a0 170 EDID_QUIRK('M', 'E', 'D', 0x7b8, EDID_QUIRK_PREFER_LARGE_75),
49d45a31 171
11bcf5f7 172 /* Lenovo G50 */
7d1be0a0 173 EDID_QUIRK('S', 'D', 'C', 18514, EDID_QUIRK_FORCE_6BPC),
11bcf5f7 174
49d45a31 175 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
7d1be0a0 176 EDID_QUIRK('S', 'E', 'C', 0xd033, EDID_QUIRK_FORCE_8BPC),
36fc5797
TV		 177
178 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
7d1be0a0 179 EDID_QUIRK('E', 'T', 'R', 13896, EDID_QUIRK_FORCE_8BPC),
acb1d8ee 180
30d62d44 181 /* Valve Index Headset */
7d1be0a0
DA		 182 EDID_QUIRK('V', 'L', 'V', 0x91a8, EDID_QUIRK_NON_DESKTOP),
183 EDID_QUIRK('V', 'L', 'V', 0x91b0, EDID_QUIRK_NON_DESKTOP),
184 EDID_QUIRK('V', 'L', 'V', 0x91b1, EDID_QUIRK_NON_DESKTOP),
185 EDID_QUIRK('V', 'L', 'V', 0x91b2, EDID_QUIRK_NON_DESKTOP),
186 EDID_QUIRK('V', 'L', 'V', 0x91b3, EDID_QUIRK_NON_DESKTOP),
187 EDID_QUIRK('V', 'L', 'V', 0x91b4, EDID_QUIRK_NON_DESKTOP),
188 EDID_QUIRK('V', 'L', 'V', 0x91b5, EDID_QUIRK_NON_DESKTOP),
189 EDID_QUIRK('V', 'L', 'V', 0x91b6, EDID_QUIRK_NON_DESKTOP),
190 EDID_QUIRK('V', 'L', 'V', 0x91b7, EDID_QUIRK_NON_DESKTOP),
191 EDID_QUIRK('V', 'L', 'V', 0x91b8, EDID_QUIRK_NON_DESKTOP),
192 EDID_QUIRK('V', 'L', 'V', 0x91b9, EDID_QUIRK_NON_DESKTOP),
193 EDID_QUIRK('V', 'L', 'V', 0x91ba, EDID_QUIRK_NON_DESKTOP),
194 EDID_QUIRK('V', 'L', 'V', 0x91bb, EDID_QUIRK_NON_DESKTOP),
195 EDID_QUIRK('V', 'L', 'V', 0x91bc, EDID_QUIRK_NON_DESKTOP),
196 EDID_QUIRK('V', 'L', 'V', 0x91bd, EDID_QUIRK_NON_DESKTOP),
197 EDID_QUIRK('V', 'L', 'V', 0x91be, EDID_QUIRK_NON_DESKTOP),
198 EDID_QUIRK('V', 'L', 'V', 0x91bf, EDID_QUIRK_NON_DESKTOP),
30d62d44 199
6931317c 200 /* HTC Vive and Vive Pro VR Headsets */
7d1be0a0
DA		 201 EDID_QUIRK('H', 'V', 'R', 0xaa01, EDID_QUIRK_NON_DESKTOP),
202 EDID_QUIRK('H', 'V', 'R', 0xaa02, EDID_QUIRK_NON_DESKTOP),
b3b12ea3 203
5a3f6108 204 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */
7d1be0a0
DA		 205 EDID_QUIRK('O', 'V', 'R', 0x0001, EDID_QUIRK_NON_DESKTOP),
206 EDID_QUIRK('O', 'V', 'R', 0x0003, EDID_QUIRK_NON_DESKTOP),
207 EDID_QUIRK('O', 'V', 'R', 0x0004, EDID_QUIRK_NON_DESKTOP),
208 EDID_QUIRK('O', 'V', 'R', 0x0012, EDID_QUIRK_NON_DESKTOP),
90eda8fc
PZ		 209
210 /* Windows Mixed Reality Headsets */
7d1be0a0 211 EDID_QUIRK('A', 'C', 'R', 0x7fce, EDID_QUIRK_NON_DESKTOP),
7d1be0a0 212 EDID_QUIRK('L', 'E', 'N', 0x0408, EDID_QUIRK_NON_DESKTOP),
7d1be0a0
DA		 213 EDID_QUIRK('F', 'U', 'J', 0x1970, EDID_QUIRK_NON_DESKTOP),
214 EDID_QUIRK('D', 'E', 'L', 0x7fce, EDID_QUIRK_NON_DESKTOP),
215 EDID_QUIRK('S', 'E', 'C', 0x144a, EDID_QUIRK_NON_DESKTOP),
216 EDID_QUIRK('A', 'U', 'S', 0xc102, EDID_QUIRK_NON_DESKTOP),
ccffc9eb
PZ		 217
218 /* Sony PlayStation VR Headset */
7d1be0a0 219 EDID_QUIRK('S', 'N', 'Y', 0x0704, EDID_QUIRK_NON_DESKTOP),
29054230
RP		 220
221 /* Sensics VR Headsets */
7d1be0a0 222 EDID_QUIRK('S', 'E', 'N', 0x1019, EDID_QUIRK_NON_DESKTOP),
29054230
RP		 223
224 /* OSVR HDK and HDK2 VR Headsets */
7d1be0a0 225 EDID_QUIRK('S', 'V', 'R', 0x1019, EDID_QUIRK_NON_DESKTOP),
f453ba04
DA		 226};
227
a6b21831
TR		 228/*
229 * Autogenerated from the DMT spec.
230 * This table is copied from xfree86/modes/xf86EdidModes.c.
231 */
232static const struct drm_display_mode drm_dmt_modes[] = {
24b856b1 233 /* 0x01 - 640x350@85Hz */
a6b21831
TR		 234 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
235 736, 832, 0, 350, 382, 385, 445, 0,
236 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 237 /* 0x02 - 640x400@85Hz */
a6b21831
TR		 238 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
239 736, 832, 0, 400, 401, 404, 445, 0,
240 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 241 /* 0x03 - 720x400@85Hz */
a6b21831
TR		 242 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
243 828, 936, 0, 400, 401, 404, 446, 0,
244 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 245 /* 0x04 - 640x480@60Hz */
a6b21831 246 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
fcf22d05 247 752, 800, 0, 480, 490, 492, 525, 0,
a6b21831 248 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 249 /* 0x05 - 640x480@72Hz */
a6b21831
TR		 250 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
251 704, 832, 0, 480, 489, 492, 520, 0,
252 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 253 /* 0x06 - 640x480@75Hz */
a6b21831
TR		 254 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
255 720, 840, 0, 480, 481, 484, 500, 0,
256 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 257 /* 0x07 - 640x480@85Hz */
a6b21831
TR		 258 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
259 752, 832, 0, 480, 481, 484, 509, 0,
260 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 261 /* 0x08 - 800x600@56Hz */
a6b21831
TR		 262 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
263 896, 1024, 0, 600, 601, 603, 625, 0,
264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 265 /* 0x09 - 800x600@60Hz */
a6b21831
TR		 266 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
267 968, 1056, 0, 600, 601, 605, 628, 0,
268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 269 /* 0x0a - 800x600@72Hz */
a6b21831
TR		 270 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
271 976, 1040, 0, 600, 637, 643, 666, 0,
272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 273 /* 0x0b - 800x600@75Hz */
a6b21831
TR		 274 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
275 896, 1056, 0, 600, 601, 604, 625, 0,
276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 277 /* 0x0c - 800x600@85Hz */
a6b21831
TR		 278 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
279 896, 1048, 0, 600, 601, 604, 631, 0,
280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 281 /* 0x0d - 800x600@120Hz RB */
a6b21831
TR		 282 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
283 880, 960, 0, 600, 603, 607, 636, 0,
284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 285 /* 0x0e - 848x480@60Hz */
a6b21831
TR		 286 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
287 976, 1088, 0, 480, 486, 494, 517, 0,
288 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 289 /* 0x0f - 1024x768@43Hz, interlace */
a6b21831 290 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
735b100f 291 1208, 1264, 0, 768, 768, 776, 817, 0,
a6b21831 292 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
fcf22d05 293 DRM_MODE_FLAG_INTERLACE) },
24b856b1 294 /* 0x10 - 1024x768@60Hz */
a6b21831
TR		 295 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
296 1184, 1344, 0, 768, 771, 777, 806, 0,
297 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 298 /* 0x11 - 1024x768@70Hz */
a6b21831
TR		 299 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
300 1184, 1328, 0, 768, 771, 777, 806, 0,
301 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 302 /* 0x12 - 1024x768@75Hz */
a6b21831
TR		 303 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
304 1136, 1312, 0, 768, 769, 772, 800, 0,
305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 306 /* 0x13 - 1024x768@85Hz */
a6b21831
TR		 307 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
308 1168, 1376, 0, 768, 769, 772, 808, 0,
309 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 310 /* 0x14 - 1024x768@120Hz RB */
a6b21831
TR		 311 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
312 1104, 1184, 0, 768, 771, 775, 813, 0,
313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 314 /* 0x15 - 1152x864@75Hz */
a6b21831
TR		 315 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
316 1344, 1600, 0, 864, 865, 868, 900, 0,
317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
bfcd74d2
VS		 318 /* 0x55 - 1280x720@60Hz */
319 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
320 1430, 1650, 0, 720, 725, 730, 750, 0,
321 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 322 /* 0x16 - 1280x768@60Hz RB */
a6b21831
TR		 323 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
324 1360, 1440, 0, 768, 771, 778, 790, 0,
325 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 326 /* 0x17 - 1280x768@60Hz */
a6b21831
TR		 327 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
328 1472, 1664, 0, 768, 771, 778, 798, 0,
329 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 330 /* 0x18 - 1280x768@75Hz */
a6b21831
TR		 331 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
332 1488, 1696, 0, 768, 771, 778, 805, 0,
fcf22d05 333 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 334 /* 0x19 - 1280x768@85Hz */
a6b21831
TR		 335 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
336 1496, 1712, 0, 768, 771, 778, 809, 0,
337 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 338 /* 0x1a - 1280x768@120Hz RB */
a6b21831
TR		 339 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
340 1360, 1440, 0, 768, 771, 778, 813, 0,
341 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 342 /* 0x1b - 1280x800@60Hz RB */
a6b21831
TR		 343 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
344 1360, 1440, 0, 800, 803, 809, 823, 0,
345 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 346 /* 0x1c - 1280x800@60Hz */
a6b21831
TR		 347 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
348 1480, 1680, 0, 800, 803, 809, 831, 0,
fcf22d05 349 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 350 /* 0x1d - 1280x800@75Hz */
a6b21831
TR		 351 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
352 1488, 1696, 0, 800, 803, 809, 838, 0,
353 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 354 /* 0x1e - 1280x800@85Hz */
a6b21831
TR		 355 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
356 1496, 1712, 0, 800, 803, 809, 843, 0,
357 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 358 /* 0x1f - 1280x800@120Hz RB */
a6b21831
TR		 359 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
360 1360, 1440, 0, 800, 803, 809, 847, 0,
361 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 362 /* 0x20 - 1280x960@60Hz */
a6b21831
TR		 363 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
364 1488, 1800, 0, 960, 961, 964, 1000, 0,
365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 366 /* 0x21 - 1280x960@85Hz */
a6b21831
TR		 367 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
368 1504, 1728, 0, 960, 961, 964, 1011, 0,
369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 370 /* 0x22 - 1280x960@120Hz RB */
a6b21831
TR		 371 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
372 1360, 1440, 0, 960, 963, 967, 1017, 0,
373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 374 /* 0x23 - 1280x1024@60Hz */
a6b21831
TR		 375 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
376 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 378 /* 0x24 - 1280x1024@75Hz */
a6b21831
TR		 379 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
380 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
381 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 382 /* 0x25 - 1280x1024@85Hz */
a6b21831
TR		 383 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
384 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 386 /* 0x26 - 1280x1024@120Hz RB */
a6b21831
TR		 387 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
388 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 390 /* 0x27 - 1360x768@60Hz */
a6b21831
TR		 391 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
392 1536, 1792, 0, 768, 771, 777, 795, 0,
393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 394 /* 0x28 - 1360x768@120Hz RB */
a6b21831
TR		 395 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
396 1440, 1520, 0, 768, 771, 776, 813, 0,
397 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 398 /* 0x51 - 1366x768@60Hz */
399 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
400 1579, 1792, 0, 768, 771, 774, 798, 0,
401 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
402 /* 0x56 - 1366x768@60Hz */
403 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
404 1436, 1500, 0, 768, 769, 772, 800, 0,
405 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 406 /* 0x29 - 1400x1050@60Hz RB */
a6b21831
TR		 407 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
408 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
409 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 410 /* 0x2a - 1400x1050@60Hz */
a6b21831
TR		 411 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
412 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
413 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 414 /* 0x2b - 1400x1050@75Hz */
a6b21831
TR		 415 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
416 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
417 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 418 /* 0x2c - 1400x1050@85Hz */
a6b21831
TR		 419 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
420 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
421 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 422 /* 0x2d - 1400x1050@120Hz RB */
a6b21831
TR		 423 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
424 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
425 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 426 /* 0x2e - 1440x900@60Hz RB */
a6b21831
TR		 427 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
428 1520, 1600, 0, 900, 903, 909, 926, 0,
429 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 430 /* 0x2f - 1440x900@60Hz */
a6b21831
TR		 431 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
432 1672, 1904, 0, 900, 903, 909, 934, 0,
433 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 434 /* 0x30 - 1440x900@75Hz */
a6b21831
TR		 435 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
436 1688, 1936, 0, 900, 903, 909, 942, 0,
437 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 438 /* 0x31 - 1440x900@85Hz */
a6b21831
TR		 439 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
440 1696, 1952, 0, 900, 903, 909, 948, 0,
441 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 442 /* 0x32 - 1440x900@120Hz RB */
a6b21831
TR		 443 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
444 1520, 1600, 0, 900, 903, 909, 953, 0,
445 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 446 /* 0x53 - 1600x900@60Hz */
447 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
448 1704, 1800, 0, 900, 901, 904, 1000, 0,
449 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 450 /* 0x33 - 1600x1200@60Hz */
a6b21831
TR		 451 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
452 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 454 /* 0x34 - 1600x1200@65Hz */
a6b21831
TR		 455 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
456 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 458 /* 0x35 - 1600x1200@70Hz */
a6b21831
TR		 459 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
460 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 462 /* 0x36 - 1600x1200@75Hz */
a6b21831
TR		 463 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
464 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 466 /* 0x37 - 1600x1200@85Hz */
a6b21831
TR		 467 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
468 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 470 /* 0x38 - 1600x1200@120Hz RB */
a6b21831
TR		 471 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
472 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
473 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 474 /* 0x39 - 1680x1050@60Hz RB */
a6b21831
TR		 475 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
476 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
477 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 478 /* 0x3a - 1680x1050@60Hz */
a6b21831
TR		 479 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
480 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
481 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 482 /* 0x3b - 1680x1050@75Hz */
a6b21831
TR		 483 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
484 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
485 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 486 /* 0x3c - 1680x1050@85Hz */
a6b21831
TR		 487 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
488 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
489 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 490 /* 0x3d - 1680x1050@120Hz RB */
a6b21831
TR		 491 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
492 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
493 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 494 /* 0x3e - 1792x1344@60Hz */
a6b21831
TR		 495 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
496 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
497 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 498 /* 0x3f - 1792x1344@75Hz */
a6b21831
TR		 499 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
500 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
501 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 502 /* 0x40 - 1792x1344@120Hz RB */
a6b21831
TR		 503 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
504 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
505 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 506 /* 0x41 - 1856x1392@60Hz */
a6b21831
TR		 507 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
508 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
509 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 510 /* 0x42 - 1856x1392@75Hz */
a6b21831 511 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
fcf22d05 512 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
a6b21831 513 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 514 /* 0x43 - 1856x1392@120Hz RB */
a6b21831
TR		 515 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
516 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
517 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 518 /* 0x52 - 1920x1080@60Hz */
519 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
520 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
521 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 522 /* 0x44 - 1920x1200@60Hz RB */
a6b21831
TR		 523 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
524 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
525 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 526 /* 0x45 - 1920x1200@60Hz */
a6b21831
TR		 527 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
528 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
529 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 530 /* 0x46 - 1920x1200@75Hz */
a6b21831
TR		 531 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
532 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
533 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 534 /* 0x47 - 1920x1200@85Hz */
a6b21831
TR		 535 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
536 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
537 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 538 /* 0x48 - 1920x1200@120Hz RB */
a6b21831
TR		 539 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
540 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
541 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 542 /* 0x49 - 1920x1440@60Hz */
a6b21831
TR		 543 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
544 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
545 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 546 /* 0x4a - 1920x1440@75Hz */
a6b21831
TR		 547 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
548 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
549 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 550 /* 0x4b - 1920x1440@120Hz RB */
a6b21831
TR		 551 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
552 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
553 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 554 /* 0x54 - 2048x1152@60Hz */
555 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
556 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
557 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 558 /* 0x4c - 2560x1600@60Hz RB */
a6b21831
TR		 559 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
560 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
561 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 562 /* 0x4d - 2560x1600@60Hz */
a6b21831
TR		 563 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
564 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
565 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 566 /* 0x4e - 2560x1600@75Hz */
a6b21831
TR		 567 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
568 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
569 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 570 /* 0x4f - 2560x1600@85Hz */
a6b21831
TR		 571 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
572 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
573 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 574 /* 0x50 - 2560x1600@120Hz RB */
a6b21831
TR		 575 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
576 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
577 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 578 /* 0x57 - 4096x2160@60Hz RB */
579 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
580 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
581 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
582 /* 0x58 - 4096x2160@59.94Hz RB */
583 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
584 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
585 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
a6b21831
TR		 586};
587
e7bfa5c4
VS		 588/*
589 * These more or less come from the DMT spec. The 720x400 modes are
590 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
591 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
592 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
593 * mode.
594 *
595 * The DMT modes have been fact-checked; the rest are mild guesses.
596 */
a6b21831
TR		 597static const struct drm_display_mode edid_est_modes[] = {
598 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
599 968, 1056, 0, 600, 601, 605, 628, 0,
600 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
601 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
602 896, 1024, 0, 600, 601, 603, 625, 0,
603 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
604 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
605 720, 840, 0, 480, 481, 484, 500, 0,
606 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
607 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
87707cfd 608 704, 832, 0, 480, 489, 492, 520, 0,
a6b21831
TR		 609 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
610 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
611 768, 864, 0, 480, 483, 486, 525, 0,
612 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
87707cfd 613 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
a6b21831
TR		 614 752, 800, 0, 480, 490, 492, 525, 0,
615 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
616 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
617 846, 900, 0, 400, 421, 423, 449, 0,
618 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
619 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
620 846, 900, 0, 400, 412, 414, 449, 0,
621 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
622 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
623 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
624 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
87707cfd 625 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
a6b21831
TR		 626 1136, 1312, 0, 768, 769, 772, 800, 0,
627 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
628 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
629 1184, 1328, 0, 768, 771, 777, 806, 0,
630 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
631 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
632 1184, 1344, 0, 768, 771, 777, 806, 0,
633 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
634 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
635 1208, 1264, 0, 768, 768, 776, 817, 0,
636 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
637 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
638 928, 1152, 0, 624, 625, 628, 667, 0,
639 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
640 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
641 896, 1056, 0, 600, 601, 604, 625, 0,
642 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
643 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
644 976, 1040, 0, 600, 637, 643, 666, 0,
645 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
646 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
647 1344, 1600, 0, 864, 865, 868, 900, 0,
648 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
649};
650
651struct minimode {
652 short w;
653 short h;
654 short r;
655 short rb;
656};
657
658static const struct minimode est3_modes[] = {
659 /* byte 6 */
660 { 640, 350, 85, 0 },
661 { 640, 400, 85, 0 },
662 { 720, 400, 85, 0 },
663 { 640, 480, 85, 0 },
664 { 848, 480, 60, 0 },
665 { 800, 600, 85, 0 },
666 { 1024, 768, 85, 0 },
667 { 1152, 864, 75, 0 },
668 /* byte 7 */
669 { 1280, 768, 60, 1 },
670 { 1280, 768, 60, 0 },
671 { 1280, 768, 75, 0 },
672 { 1280, 768, 85, 0 },
673 { 1280, 960, 60, 0 },
674 { 1280, 960, 85, 0 },
675 { 1280, 1024, 60, 0 },
676 { 1280, 1024, 85, 0 },
677 /* byte 8 */
678 { 1360, 768, 60, 0 },
679 { 1440, 900, 60, 1 },
680 { 1440, 900, 60, 0 },
681 { 1440, 900, 75, 0 },
682 { 1440, 900, 85, 0 },
683 { 1400, 1050, 60, 1 },
684 { 1400, 1050, 60, 0 },
685 { 1400, 1050, 75, 0 },
686 /* byte 9 */
687 { 1400, 1050, 85, 0 },
688 { 1680, 1050, 60, 1 },
689 { 1680, 1050, 60, 0 },
690 { 1680, 1050, 75, 0 },
691 { 1680, 1050, 85, 0 },
692 { 1600, 1200, 60, 0 },
693 { 1600, 1200, 65, 0 },
694 { 1600, 1200, 70, 0 },
695 /* byte 10 */
696 { 1600, 1200, 75, 0 },
697 { 1600, 1200, 85, 0 },
698 { 1792, 1344, 60, 0 },
c068b32a 699 { 1792, 1344, 75, 0 },
a6b21831
TR		 700 { 1856, 1392, 60, 0 },
701 { 1856, 1392, 75, 0 },
702 { 1920, 1200, 60, 1 },
703 { 1920, 1200, 60, 0 },
704 /* byte 11 */
705 { 1920, 1200, 75, 0 },
706 { 1920, 1200, 85, 0 },
707 { 1920, 1440, 60, 0 },
708 { 1920, 1440, 75, 0 },
709};
710
711static const struct minimode extra_modes[] = {
712 { 1024, 576, 60, 0 },
713 { 1366, 768, 60, 0 },
714 { 1600, 900, 60, 0 },
715 { 1680, 945, 60, 0 },
716 { 1920, 1080, 60, 0 },
717 { 2048, 1152, 60, 0 },
718 { 2048, 1536, 60, 0 },
719};
720
721/*
7befe621 722 * From CEA/CTA-861 spec.
d9278b4c 723 *
7befe621 724 * Do not access directly, instead always use cea_mode_for_vic().
a6b21831 725 */
8c1b2bd9 726static const struct drm_display_mode edid_cea_modes_1[] = {
78691960 727 /* 1 - 640x480@60Hz 4:3 */
a6b21831
TR		 728 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
729 752, 800, 0, 480, 490, 492, 525, 0,
ee7925bb 730 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 731 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 732 /* 2 - 720x480@60Hz 4:3 */
a6b21831
TR		 733 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
734 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 735 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 736 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 737 /* 3 - 720x480@60Hz 16:9 */
a6b21831
TR		 738 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
739 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 740 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 741 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 742 /* 4 - 1280x720@60Hz 16:9 */
a6b21831
TR		 743 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
744 1430, 1650, 0, 720, 725, 730, 750, 0,
ee7925bb 745 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 746 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 747 /* 5 - 1920x1080i@60Hz 16:9 */
a6b21831
TR		 748 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
749 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
750 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 751 DRM_MODE_FLAG_INTERLACE),
0425662f 752 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 753 /* 6 - 720(1440)x480i@60Hz 4:3 */
fb01d280
CT		 754 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
755 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 756 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 757 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 758 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 759 /* 7 - 720(1440)x480i@60Hz 16:9 */
fb01d280
CT		 760 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
761 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 762 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 763 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 764 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 765 /* 8 - 720(1440)x240@60Hz 4:3 */
fb01d280
CT		 766 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
767 801, 858, 0, 240, 244, 247, 262, 0,
a6b21831 768 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 769 DRM_MODE_FLAG_DBLCLK),
0425662f 770 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 771 /* 9 - 720(1440)x240@60Hz 16:9 */
fb01d280
CT		 772 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
773 801, 858, 0, 240, 244, 247, 262, 0,
a6b21831 774 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 775 DRM_MODE_FLAG_DBLCLK),
0425662f 776 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 777 /* 10 - 2880x480i@60Hz 4:3 */
a6b21831
TR		 778 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
779 3204, 3432, 0, 480, 488, 494, 525, 0,
780 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 781 DRM_MODE_FLAG_INTERLACE),
0425662f 782 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 783 /* 11 - 2880x480i@60Hz 16:9 */
a6b21831
TR		 784 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
785 3204, 3432, 0, 480, 488, 494, 525, 0,
786 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 787 DRM_MODE_FLAG_INTERLACE),
0425662f 788 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 789 /* 12 - 2880x240@60Hz 4:3 */
a6b21831
TR		 790 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
791 3204, 3432, 0, 240, 244, 247, 262, 0,
ee7925bb 792 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 793 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 794 /* 13 - 2880x240@60Hz 16:9 */
a6b21831
TR		 795 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
796 3204, 3432, 0, 240, 244, 247, 262, 0,
ee7925bb 797 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 798 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 799 /* 14 - 1440x480@60Hz 4:3 */
a6b21831
TR		 800 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
801 1596, 1716, 0, 480, 489, 495, 525, 0,
ee7925bb 802 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 803 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 804 /* 15 - 1440x480@60Hz 16:9 */
a6b21831
TR		 805 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
806 1596, 1716, 0, 480, 489, 495, 525, 0,
ee7925bb 807 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 808 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 809 /* 16 - 1920x1080@60Hz 16:9 */
a6b21831
TR		 810 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
811 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 812 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 813 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 814 /* 17 - 720x576@50Hz 4:3 */
a6b21831
TR		 815 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
816 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 817 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 818 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 819 /* 18 - 720x576@50Hz 16:9 */
a6b21831
TR		 820 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
821 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 822 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 823 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 824 /* 19 - 1280x720@50Hz 16:9 */
a6b21831
TR		 825 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
826 1760, 1980, 0, 720, 725, 730, 750, 0,
ee7925bb 827 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 828 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 829 /* 20 - 1920x1080i@50Hz 16:9 */
a6b21831
TR		 830 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
831 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
832 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 833 DRM_MODE_FLAG_INTERLACE),
0425662f 834 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 835 /* 21 - 720(1440)x576i@50Hz 4:3 */
fb01d280
CT		 836 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
837 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 838 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 839 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 840 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 841 /* 22 - 720(1440)x576i@50Hz 16:9 */
fb01d280
CT		 842 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
843 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 844 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 845 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 846 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 847 /* 23 - 720(1440)x288@50Hz 4:3 */
fb01d280
CT		 848 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
849 795, 864, 0, 288, 290, 293, 312, 0,
a6b21831 850 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 851 DRM_MODE_FLAG_DBLCLK),
0425662f 852 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 853 /* 24 - 720(1440)x288@50Hz 16:9 */
fb01d280
CT		 854 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
855 795, 864, 0, 288, 290, 293, 312, 0,
a6b21831 856 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 857 DRM_MODE_FLAG_DBLCLK),
0425662f 858 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 859 /* 25 - 2880x576i@50Hz 4:3 */
a6b21831
TR		 860 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
861 3180, 3456, 0, 576, 580, 586, 625, 0,
862 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 863 DRM_MODE_FLAG_INTERLACE),
0425662f 864 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 865 /* 26 - 2880x576i@50Hz 16:9 */
a6b21831
TR		 866 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
867 3180, 3456, 0, 576, 580, 586, 625, 0,
868 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 869 DRM_MODE_FLAG_INTERLACE),
0425662f 870 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 871 /* 27 - 2880x288@50Hz 4:3 */
a6b21831
TR		 872 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
873 3180, 3456, 0, 288, 290, 293, 312, 0,
ee7925bb 874 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 875 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 876 /* 28 - 2880x288@50Hz 16:9 */
a6b21831
TR		 877 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
878 3180, 3456, 0, 288, 290, 293, 312, 0,
ee7925bb 879 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 880 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 881 /* 29 - 1440x576@50Hz 4:3 */
a6b21831
TR		 882 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
883 1592, 1728, 0, 576, 581, 586, 625, 0,
ee7925bb 884 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 885 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 886 /* 30 - 1440x576@50Hz 16:9 */
a6b21831
TR		 887 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
888 1592, 1728, 0, 576, 581, 586, 625, 0,
ee7925bb 889 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 890 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 891 /* 31 - 1920x1080@50Hz 16:9 */
a6b21831
TR		 892 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
893 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 894 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 895 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 896 /* 32 - 1920x1080@24Hz 16:9 */
a6b21831
TR		 897 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
898 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 899 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 900 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 901 /* 33 - 1920x1080@25Hz 16:9 */
a6b21831
TR		 902 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
903 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 904 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 905 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 906 /* 34 - 1920x1080@30Hz 16:9 */
a6b21831
TR		 907 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
908 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 909 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 910 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 911 /* 35 - 2880x480@60Hz 4:3 */
a6b21831
TR		 912 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
913 3192, 3432, 0, 480, 489, 495, 525, 0,
ee7925bb 914 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 915 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 916 /* 36 - 2880x480@60Hz 16:9 */
a6b21831
TR		 917 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
918 3192, 3432, 0, 480, 489, 495, 525, 0,
ee7925bb 919 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 920 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 921 /* 37 - 2880x576@50Hz 4:3 */
a6b21831
TR		 922 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
923 3184, 3456, 0, 576, 581, 586, 625, 0,
ee7925bb 924 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 925 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 926 /* 38 - 2880x576@50Hz 16:9 */
a6b21831
TR		 927 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
928 3184, 3456, 0, 576, 581, 586, 625, 0,
ee7925bb 929 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 930 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 931 /* 39 - 1920x1080i@50Hz 16:9 */
a6b21831
TR		 932 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
933 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
934 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 935 DRM_MODE_FLAG_INTERLACE),
0425662f 936 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 937 /* 40 - 1920x1080i@100Hz 16:9 */
a6b21831
TR		 938 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
939 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
940 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 941 DRM_MODE_FLAG_INTERLACE),
0425662f 942 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 943 /* 41 - 1280x720@100Hz 16:9 */
a6b21831
TR		 944 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
945 1760, 1980, 0, 720, 725, 730, 750, 0,
ee7925bb 946 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 947 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 948 /* 42 - 720x576@100Hz 4:3 */
a6b21831
TR		 949 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
950 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 951 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 952 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 953 /* 43 - 720x576@100Hz 16:9 */
a6b21831
TR		 954 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
955 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 956 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 957 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 958 /* 44 - 720(1440)x576i@100Hz 4:3 */
fb01d280
CT		 959 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
960 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 961 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 962 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 963 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 964 /* 45 - 720(1440)x576i@100Hz 16:9 */
fb01d280
CT		 965 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
966 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 967 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 968 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 969 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 970 /* 46 - 1920x1080i@120Hz 16:9 */
a6b21831
TR		 971 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
972 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
973 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 974 DRM_MODE_FLAG_INTERLACE),
0425662f 975 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 976 /* 47 - 1280x720@120Hz 16:9 */
a6b21831
TR		 977 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
978 1430, 1650, 0, 720, 725, 730, 750, 0,
ee7925bb 979 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 980 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 981 /* 48 - 720x480@120Hz 4:3 */
a6b21831
TR		 982 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
983 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 984 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 985 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 986 /* 49 - 720x480@120Hz 16:9 */
a6b21831
TR		 987 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
988 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 989 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 990 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 991 /* 50 - 720(1440)x480i@120Hz 4:3 */
fb01d280
CT		 992 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
993 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 994 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 995 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 996 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 997 /* 51 - 720(1440)x480i@120Hz 16:9 */
fb01d280
CT		 998 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
999 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 1000 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1001 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1002 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1003 /* 52 - 720x576@200Hz 4:3 */
a6b21831
TR		 1004 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1005 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 1006 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 1007 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1008 /* 53 - 720x576@200Hz 16:9 */
a6b21831
TR		 1009 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1010 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 1011 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 1012 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1013 /* 54 - 720(1440)x576i@200Hz 4:3 */
fb01d280
CT		 1014 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1015 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 1016 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1017 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1018 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1019 /* 55 - 720(1440)x576i@200Hz 16:9 */
fb01d280
CT		 1020 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1021 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 1022 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1023 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1024 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1025 /* 56 - 720x480@240Hz 4:3 */
a6b21831
TR		 1026 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1027 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 1028 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 1029 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1030 /* 57 - 720x480@240Hz 16:9 */
a6b21831
TR		 1031 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1032 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 1033 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 1034 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1035 /* 58 - 720(1440)x480i@240Hz 4:3 */
fb01d280
CT		 1036 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1037 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 1038 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1039 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1040 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1041 /* 59 - 720(1440)x480i@240Hz 16:9 */
fb01d280
CT		 1042 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1043 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 1044 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1045 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1046 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1047 /* 60 - 1280x720@24Hz 16:9 */
a6b21831
TR		 1048 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1049 3080, 3300, 0, 720, 725, 730, 750, 0,
ee7925bb 1050 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1051 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1052 /* 61 - 1280x720@25Hz 16:9 */
a6b21831
TR		 1053 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1054 3740, 3960, 0, 720, 725, 730, 750, 0,
ee7925bb 1055 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1056 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1057 /* 62 - 1280x720@30Hz 16:9 */
a6b21831
TR		 1058 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1059 3080, 3300, 0, 720, 725, 730, 750, 0,
ee7925bb 1060 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1061 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1062 /* 63 - 1920x1080@120Hz 16:9 */
a6b21831
TR		 1063 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1064 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 1065 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1066 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1067 /* 64 - 1920x1080@100Hz 16:9 */
a6b21831 1068 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
8f0e4907 1069 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 1070 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1071 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1072 /* 65 - 1280x720@24Hz 64:27 */
8ec6e075
SS		 1073 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1074 3080, 3300, 0, 720, 725, 730, 750, 0,
1075 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1076 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1077 /* 66 - 1280x720@25Hz 64:27 */
8ec6e075
SS		 1078 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1079 3740, 3960, 0, 720, 725, 730, 750, 0,
1080 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1081 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1082 /* 67 - 1280x720@30Hz 64:27 */
8ec6e075
SS		 1083 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1084 3080, 3300, 0, 720, 725, 730, 750, 0,
1085 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1086 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1087 /* 68 - 1280x720@50Hz 64:27 */
8ec6e075
SS		 1088 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1089 1760, 1980, 0, 720, 725, 730, 750, 0,
1090 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1091 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1092 /* 69 - 1280x720@60Hz 64:27 */
8ec6e075
SS		 1093 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1094 1430, 1650, 0, 720, 725, 730, 750, 0,
1095 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1096 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1097 /* 70 - 1280x720@100Hz 64:27 */
8ec6e075
SS		 1098 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1099 1760, 1980, 0, 720, 725, 730, 750, 0,
1100 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1101 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1102 /* 71 - 1280x720@120Hz 64:27 */
8ec6e075
SS		 1103 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1104 1430, 1650, 0, 720, 725, 730, 750, 0,
1105 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1106 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1107 /* 72 - 1920x1080@24Hz 64:27 */
8ec6e075
SS		 1108 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1109 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1110 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1111 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1112 /* 73 - 1920x1080@25Hz 64:27 */
8ec6e075
SS		 1113 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1114 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1115 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1116 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1117 /* 74 - 1920x1080@30Hz 64:27 */
8ec6e075
SS		 1118 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1119 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1120 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1121 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1122 /* 75 - 1920x1080@50Hz 64:27 */
8ec6e075
SS		 1123 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1124 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1125 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1126 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1127 /* 76 - 1920x1080@60Hz 64:27 */
8ec6e075
SS		 1128 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1129 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1130 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1131 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1132 /* 77 - 1920x1080@100Hz 64:27 */
8ec6e075
SS		 1133 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1134 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1135 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1136 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1137 /* 78 - 1920x1080@120Hz 64:27 */
8ec6e075
SS		 1138 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1139 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1140 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1141 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1142 /* 79 - 1680x720@24Hz 64:27 */
8ec6e075
SS		 1143 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1144 3080, 3300, 0, 720, 725, 730, 750, 0,
1145 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1146 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1147 /* 80 - 1680x720@25Hz 64:27 */
8ec6e075
SS		 1148 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1149 2948, 3168, 0, 720, 725, 730, 750, 0,
1150 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1151 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1152 /* 81 - 1680x720@30Hz 64:27 */
8ec6e075
SS		 1153 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1154 2420, 2640, 0, 720, 725, 730, 750, 0,
1155 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1156 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1157 /* 82 - 1680x720@50Hz 64:27 */
8ec6e075
SS		 1158 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1159 1980, 2200, 0, 720, 725, 730, 750, 0,
1160 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1161 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1162 /* 83 - 1680x720@60Hz 64:27 */
8ec6e075
SS		 1163 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1164 1980, 2200, 0, 720, 725, 730, 750, 0,
1165 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1166 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1167 /* 84 - 1680x720@100Hz 64:27 */
8ec6e075
SS		 1168 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1169 1780, 2000, 0, 720, 725, 730, 825, 0,
1170 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1171 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1172 /* 85 - 1680x720@120Hz 64:27 */
8ec6e075
SS		 1173 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1174 1780, 2000, 0, 720, 725, 730, 825, 0,
1175 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1176 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1177 /* 86 - 2560x1080@24Hz 64:27 */
8ec6e075
SS		 1178 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1179 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1180 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1181 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1182 /* 87 - 2560x1080@25Hz 64:27 */
8ec6e075
SS		 1183 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1184 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1185 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1186 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1187 /* 88 - 2560x1080@30Hz 64:27 */
8ec6e075
SS		 1188 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1189 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1190 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1191 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1192 /* 89 - 2560x1080@50Hz 64:27 */
8ec6e075
SS		 1193 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1194 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1195 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1196 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1197 /* 90 - 2560x1080@60Hz 64:27 */
8ec6e075
SS		 1198 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1199 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1200 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1201 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1202 /* 91 - 2560x1080@100Hz 64:27 */
8ec6e075
SS		 1203 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1204 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1205 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1206 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1207 /* 92 - 2560x1080@120Hz 64:27 */
8ec6e075
SS		 1208 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1209 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1210 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1211 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1212 /* 93 - 3840x2160@24Hz 16:9 */
8ec6e075
SS		 1213 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1214 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1215 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1216 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1217 /* 94 - 3840x2160@25Hz 16:9 */
8ec6e075
SS		 1218 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1219 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1220 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1221 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1222 /* 95 - 3840x2160@30Hz 16:9 */
8ec6e075
SS		 1223 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1224 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1225 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1226 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1227 /* 96 - 3840x2160@50Hz 16:9 */
8ec6e075
SS		 1228 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1229 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1230 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1231 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1232 /* 97 - 3840x2160@60Hz 16:9 */
8ec6e075
SS		 1233 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1234 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1235 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1236 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1237 /* 98 - 4096x2160@24Hz 256:135 */
8ec6e075
SS		 1238 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1239 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1240 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1241 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1242 /* 99 - 4096x2160@25Hz 256:135 */
8ec6e075
SS		 1243 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1244 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1245 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1246 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1247 /* 100 - 4096x2160@30Hz 256:135 */
8ec6e075
SS		 1248 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1249 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1250 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1251 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1252 /* 101 - 4096x2160@50Hz 256:135 */
8ec6e075
SS		 1253 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1254 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1255 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1256 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1257 /* 102 - 4096x2160@60Hz 256:135 */
8ec6e075
SS		 1258 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1259 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1260 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1261 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1262 /* 103 - 3840x2160@24Hz 64:27 */
8ec6e075
SS		 1263 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1264 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1265 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1266 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1267 /* 104 - 3840x2160@25Hz 64:27 */
8ec6e075
SS		 1268 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1269 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1270 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1271 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1272 /* 105 - 3840x2160@30Hz 64:27 */
8ec6e075
SS		 1273 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1274 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1275 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1276 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1277 /* 106 - 3840x2160@50Hz 64:27 */
8ec6e075
SS		 1278 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1279 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1281 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1282 /* 107 - 3840x2160@60Hz 64:27 */
8ec6e075
SS		 1283 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1284 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1285 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1286 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1287 /* 108 - 1280x720@48Hz 16:9 */
1288 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1289 2280, 2500, 0, 720, 725, 730, 750, 0,
1290 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1291 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1292 /* 109 - 1280x720@48Hz 64:27 */
1293 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1294 2280, 2500, 0, 720, 725, 730, 750, 0,
1295 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1296 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1297 /* 110 - 1680x720@48Hz 64:27 */
1298 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490,
1299 2530, 2750, 0, 720, 725, 730, 750, 0,
1300 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1301 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1302 /* 111 - 1920x1080@48Hz 16:9 */
1303 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1304 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1306 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1307 /* 112 - 1920x1080@48Hz 64:27 */
1308 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1309 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1310 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1311 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1312 /* 113 - 2560x1080@48Hz 64:27 */
1313 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558,
1314 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1315 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1316 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1317 /* 114 - 3840x2160@48Hz 16:9 */
1318 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1319 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1320 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1321 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1322 /* 115 - 4096x2160@48Hz 256:135 */
1323 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116,
1324 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1325 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1326 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
978f6b06
VS		 1327 /* 116 - 3840x2160@48Hz 64:27 */
1328 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1329 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1330 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1331 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1332 /* 117 - 3840x2160@100Hz 16:9 */
1333 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1334 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1335 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1336 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1337 /* 118 - 3840x2160@120Hz 16:9 */
1338 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1339 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1340 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1341 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1342 /* 119 - 3840x2160@100Hz 64:27 */
1343 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1344 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1345 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1346 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1347 /* 120 - 3840x2160@120Hz 64:27 */
1348 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1349 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1350 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1351 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1352 /* 121 - 5120x2160@24Hz 64:27 */
1353 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116,
1354 7204, 7500, 0, 2160, 2168, 2178, 2200, 0,
1355 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1356 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1357 /* 122 - 5120x2160@25Hz 64:27 */
1358 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816,
1359 6904, 7200, 0, 2160, 2168, 2178, 2200, 0,
1360 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1361 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1362 /* 123 - 5120x2160@30Hz 64:27 */
1363 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784,
1364 5872, 6000, 0, 2160, 2168, 2178, 2200, 0,
1365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1366 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1367 /* 124 - 5120x2160@48Hz 64:27 */
1368 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866,
1369 5954, 6250, 0, 2160, 2168, 2178, 2475, 0,
1370 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1371 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1372 /* 125 - 5120x2160@50Hz 64:27 */
1373 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216,
1374 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1375 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1376 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1377 /* 126 - 5120x2160@60Hz 64:27 */
1378 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284,
1379 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1380 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1381 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1382 /* 127 - 5120x2160@100Hz 64:27 */
1383 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216,
1384 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1386 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
a6b21831
TR		 1387};
1388
f7655d42
VS		 1389/*
1390 * From CEA/CTA-861 spec.
1391 *
1392 * Do not access directly, instead always use cea_mode_for_vic().
1393 */
1394static const struct drm_display_mode edid_cea_modes_193[] = {
1395 /* 193 - 5120x2160@120Hz 64:27 */
1396 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284,
1397 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1398 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1399 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1400 /* 194 - 7680x4320@24Hz 16:9 */
1401 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1402 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1403 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1404 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1405 /* 195 - 7680x4320@25Hz 16:9 */
1406 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1407 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1408 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1409 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1410 /* 196 - 7680x4320@30Hz 16:9 */
1411 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1412 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1413 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1414 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1415 /* 197 - 7680x4320@48Hz 16:9 */
1416 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1417 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1418 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1419 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1420 /* 198 - 7680x4320@50Hz 16:9 */
1421 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1422 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1423 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1424 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1425 /* 199 - 7680x4320@60Hz 16:9 */
1426 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1427 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1428 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1429 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1430 /* 200 - 7680x4320@100Hz 16:9 */
1431 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1432 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1433 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1434 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1435 /* 201 - 7680x4320@120Hz 16:9 */
1436 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1437 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1438 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1439 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1440 /* 202 - 7680x4320@24Hz 64:27 */
1441 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1442 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1443 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1444 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1445 /* 203 - 7680x4320@25Hz 64:27 */
1446 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1447 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1448 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1449 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1450 /* 204 - 7680x4320@30Hz 64:27 */
1451 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1452 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1454 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1455 /* 205 - 7680x4320@48Hz 64:27 */
1456 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1457 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1458 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1459 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1460 /* 206 - 7680x4320@50Hz 64:27 */
1461 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1462 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1463 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1464 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1465 /* 207 - 7680x4320@60Hz 64:27 */
1466 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1467 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1468 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1469 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1470 /* 208 - 7680x4320@100Hz 64:27 */
1471 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1472 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1473 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1474 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1475 /* 209 - 7680x4320@120Hz 64:27 */
1476 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1477 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1478 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1479 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1480 /* 210 - 10240x4320@24Hz 64:27 */
1481 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732,
1482 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1483 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1484 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1485 /* 211 - 10240x4320@25Hz 64:27 */
1486 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732,
1487 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1488 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1489 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1490 /* 212 - 10240x4320@30Hz 64:27 */
1491 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528,
1492 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1493 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1494 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1495 /* 213 - 10240x4320@48Hz 64:27 */
1496 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732,
1497 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1498 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1499 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1500 /* 214 - 10240x4320@50Hz 64:27 */
1501 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732,
1502 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1503 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1504 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1505 /* 215 - 10240x4320@60Hz 64:27 */
1506 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528,
1507 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1508 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1509 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1510 /* 216 - 10240x4320@100Hz 64:27 */
1511 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432,
1512 12608, 13200, 0, 4320, 4336, 4356, 4500, 0,
1513 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1514 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1515 /* 217 - 10240x4320@120Hz 64:27 */
1516 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528,
1517 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1518 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1519 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1520 /* 218 - 4096x2160@100Hz 256:135 */
1521 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896,
1522 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1523 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1524 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
f7655d42
VS		 1525 /* 219 - 4096x2160@120Hz 256:135 */
1526 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184,
1527 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1528 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1529 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
f7655d42
VS		 1530};
1531
7ebe1963 1532/*
d9278b4c 1533 * HDMI 1.4 4k modes. Index using the VIC.
7ebe1963
LD		 1534 */
1535static const struct drm_display_mode edid_4k_modes[] = {
d9278b4c
JN		 1536 /* 0 - dummy, VICs start at 1 */
1537 { },
7ebe1963
LD		 1538 /* 1 - 3840x2160@30Hz */
1539 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1540 3840, 4016, 4104, 4400, 0,
1541 2160, 2168, 2178, 2250, 0,
1542 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1543 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
7ebe1963
LD		 1544 /* 2 - 3840x2160@25Hz */
1545 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1546 3840, 4896, 4984, 5280, 0,
1547 2160, 2168, 2178, 2250, 0,
1548 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1549 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
7ebe1963
LD		 1550 /* 3 - 3840x2160@24Hz */
1551 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1552 3840, 5116, 5204, 5500, 0,
1553 2160, 2168, 2178, 2250, 0,
1554 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1555 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
7ebe1963
LD		 1556 /* 4 - 4096x2160@24Hz (SMPTE) */
1557 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1558 4096, 5116, 5204, 5500, 0,
1559 2160, 2168, 2178, 2250, 0,
1560 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1561 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
7ebe1963
LD		 1562};
1563
61e57a8d 1564/*** DDC fetch and block validation ***/
f453ba04 1565
e4ccf9a7
JN		 1566/*
1567 * The opaque EDID type, internal to drm_edid.c.
1568 */
1569struct drm_edid {
1570 /* Size allocated for edid */
1571 size_t size;
1572 const struct edid *edid;
1573};
1574
18e3c1d5
JN		 1575static int edid_hfeeodb_extension_block_count(const struct edid *edid);
1576
1577static int edid_hfeeodb_block_count(const struct edid *edid)
1578{
1579 int eeodb = edid_hfeeodb_extension_block_count(edid);
1580
1581 return eeodb ? eeodb + 1 : 0;
1582}
1583
f1e4c916
JN		 1584static int edid_extension_block_count(const struct edid *edid)
1585{
1586 return edid->extensions;
1587}
1588
1589static int edid_block_count(const struct edid *edid)
1590{
1591 return edid_extension_block_count(edid) + 1;
1592}
1593
1594static int edid_size_by_blocks(int num_blocks)
1595{
1596 return num_blocks * EDID_LENGTH;
1597}
1598
1599static int edid_size(const struct edid *edid)
1600{
1601 return edid_size_by_blocks(edid_block_count(edid));
1602}
1603
1604static const void *edid_block_data(const struct edid *edid, int index)
1605{
1606 BUILD_BUG_ON(sizeof(*edid) != EDID_LENGTH);
1607
1608 return edid + index;
1609}
1610
1611static const void *edid_extension_block_data(const struct edid *edid, int index)
1612{
1613 return edid_block_data(edid, index + 1);
1614}
1615
b16c9e6c
JN		 1616/* EDID block count indicated in EDID, may exceed allocated size */
1617static int __drm_edid_block_count(const struct drm_edid *drm_edid)
d9307f27
JN		 1618{
1619 int num_blocks;
1620
1621 /* Starting point */
1622 num_blocks = edid_block_count(drm_edid->edid);
1623
b1dee952
JN		 1624 /* HF-EEODB override */
1625 if (drm_edid->size >= edid_size_by_blocks(2)) {
1626 int eeodb;
1627
1628 /*
1629 * Note: HF-EEODB may specify a smaller extension count than the
1630 * regular one. Unlike in buffer allocation, here we can use it.
1631 */
1632 eeodb = edid_hfeeodb_block_count(drm_edid->edid);
1633 if (eeodb)
1634 num_blocks = eeodb;
1635 }
1636
d9307f27
JN		 1637 return num_blocks;
1638}
1639
b16c9e6c
JN		 1640/* EDID block count, limited by allocated size */
1641static int drm_edid_block_count(const struct drm_edid *drm_edid)
1642{
1643 /* Limit by allocated size */
1644 return min(__drm_edid_block_count(drm_edid),
1645 (int)drm_edid->size / EDID_LENGTH);
1646}
1647
1648/* EDID extension block count, limited by allocated size */
d9307f27
JN		 1649static int drm_edid_extension_block_count(const struct drm_edid *drm_edid)
1650{
1651 return drm_edid_block_count(drm_edid) - 1;
1652}
1653
1654static const void *drm_edid_block_data(const struct drm_edid *drm_edid, int index)
1655{
1656 return edid_block_data(drm_edid->edid, index);
1657}
1658
1659static const void *drm_edid_extension_block_data(const struct drm_edid *drm_edid,
1660 int index)
1661{
1662 return edid_extension_block_data(drm_edid->edid, index);
1663}
1664
22a27e05
JN		 1665/*
1666 * Initializer helper for legacy interfaces, where we have no choice but to
1667 * trust edid size. Not for general purpose use.
1668 */
1669static const struct drm_edid *drm_edid_legacy_init(struct drm_edid *drm_edid,
1670 const struct edid *edid)
1671{
1672 if (!edid)
1673 return NULL;
1674
1675 memset(drm_edid, 0, sizeof(*drm_edid));
1676
1677 drm_edid->edid = edid;
1678 drm_edid->size = edid_size(edid);
1679
1680 return drm_edid;
1681}
1682
94afc538
JN		 1683/*
1684 * EDID base and extension block iterator.
1685 *
1686 * struct drm_edid_iter iter;
1687 * const u8 *block;
1688 *
bbded689 1689 * drm_edid_iter_begin(drm_edid, &iter);
94afc538
JN		 1690 * drm_edid_iter_for_each(block, &iter) {
1691 * // do stuff with block
1692 * }
1693 * drm_edid_iter_end(&iter);
1694 */
1695struct drm_edid_iter {
bbded689 1696 const struct drm_edid *drm_edid;
94afc538
JN		 1697
1698 /* Current block index. */
1699 int index;
1700};
1701
bbded689 1702static void drm_edid_iter_begin(const struct drm_edid *drm_edid,
94afc538
JN		 1703 struct drm_edid_iter *iter)
1704{
1705 memset(iter, 0, sizeof(*iter));
1706
bbded689 1707 iter->drm_edid = drm_edid;
94afc538
JN		 1708}
1709
1710static const void *__drm_edid_iter_next(struct drm_edid_iter *iter)
1711{
1712 const void *block = NULL;
1713
bbded689 1714 if (!iter->drm_edid)
94afc538
JN		 1715 return NULL;
1716
d9307f27
JN		 1717 if (iter->index < drm_edid_block_count(iter->drm_edid))
1718 block = drm_edid_block_data(iter->drm_edid, iter->index++);
94afc538
JN		 1719
1720 return block;
1721}
1722
1723#define drm_edid_iter_for_each(__block, __iter) \
1724 while (((__block) = __drm_edid_iter_next(__iter)))
1725
1726static void drm_edid_iter_end(struct drm_edid_iter *iter)
1727{
1728 memset(iter, 0, sizeof(*iter));
1729}
1730
083ae056
AJ		 1731static const u8 edid_header[] = {
1732 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1733};
f453ba04 1734
0a612bbd
JN		 1735static void edid_header_fix(void *edid)
1736{
1737 memcpy(edid, edid_header, sizeof(edid_header));
1738}
1739
db6cf833
TR		 1740/**
1741 * drm_edid_header_is_valid - sanity check the header of the base EDID block
5d96fc9c 1742 * @_edid: pointer to raw base EDID block
db6cf833
TR		 1743 *
1744 * Sanity check the header of the base EDID block.
1745 *
1746 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
051963d4 1747 */
6d987ddd 1748int drm_edid_header_is_valid(const void *_edid)
051963d4 1749{
6d987ddd 1750 const struct edid *edid = _edid;
051963d4
TR		 1751 int i, score = 0;
1752
6d987ddd
JN		 1753 for (i = 0; i < sizeof(edid_header); i++) {
1754 if (edid->header[i] == edid_header[i])
051963d4 1755 score++;
6d987ddd 1756 }
051963d4
TR		 1757
1758 return score;
1759}
1760EXPORT_SYMBOL(drm_edid_header_is_valid);
1761
47819ba2
AJ		 1762static int edid_fixup __read_mostly = 6;
1763module_param_named(edid_fixup, edid_fixup, int, 0400);
1764MODULE_PARM_DESC(edid_fixup,
1765 "Minimum number of valid EDID header bytes (0-8, default 6)");
051963d4 1766
70e49ebe 1767static int edid_block_compute_checksum(const void *_block)
c465bbc8 1768{
70e49ebe 1769 const u8 *block = _block;
c465bbc8 1770 int i;
e11f5bd8
JFZ		 1771 u8 csum = 0, crc = 0;
1772
1773 for (i = 0; i < EDID_LENGTH - 1; i++)
70e49ebe 1774 csum += block[i];
c465bbc8 1775
e11f5bd8
JFZ		 1776 crc = 0x100 - csum;
1777
1778 return crc;
1779}
1780
70e49ebe 1781static int edid_block_get_checksum(const void *_block)
e11f5bd8 1782{
70e49ebe
JN		 1783 const struct edid *block = _block;
1784
1785 return block->checksum;
c465bbc8
SB		 1786}
1787
4ba0f53c
JN		 1788static int edid_block_tag(const void *_block)
1789{
1790 const u8 *block = _block;
1791
1792 return block[0];
1793}
1794
8baccb27 1795static bool edid_block_is_zero(const void *edid)
d6885d65 1796{
8baccb27 1797 return !memchr_inv(edid, 0, EDID_LENGTH);
d6885d65
SB		 1798}
1799
536faa45
SL		 1800/**
1801 * drm_edid_are_equal - compare two edid blobs.
1802 * @edid1: pointer to first blob
1803 * @edid2: pointer to second blob
1804 * This helper can be used during probing to determine if
1805 * edid had changed.
1806 */
1807bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2)
1808{
1809 int edid1_len, edid2_len;
1810 bool edid1_present = edid1 != NULL;
1811 bool edid2_present = edid2 != NULL;
1812
1813 if (edid1_present != edid2_present)
1814 return false;
1815
1816 if (edid1) {
f1e4c916
JN		 1817 edid1_len = edid_size(edid1);
1818 edid2_len = edid_size(edid2);
536faa45
SL		 1819
1820 if (edid1_len != edid2_len)
1821 return false;
1822
1823 if (memcmp(edid1, edid2, edid1_len))
1824 return false;
1825 }
1826
1827 return true;
1828}
1829EXPORT_SYMBOL(drm_edid_are_equal);
1830
1f221284
JN		 1831enum edid_block_status {
1832 EDID_BLOCK_OK = 0,
2deaf1c2 1833 EDID_BLOCK_READ_FAIL,
1f221284 1834 EDID_BLOCK_NULL,
49dc0558 1835 EDID_BLOCK_ZERO,
1f221284
JN		 1836 EDID_BLOCK_HEADER_CORRUPT,
1837 EDID_BLOCK_HEADER_REPAIR,
1838 EDID_BLOCK_HEADER_FIXED,
1839 EDID_BLOCK_CHECKSUM,
1840 EDID_BLOCK_VERSION,
1841};
1842
1843static enum edid_block_status edid_block_check(const void *_block,
1844 bool is_base_block)
1845{
1846 const struct edid *block = _block;
1847
1848 if (!block)
1849 return EDID_BLOCK_NULL;
1850
1851 if (is_base_block) {
1852 int score = drm_edid_header_is_valid(block);
1853
49dc0558
JN		 1854 if (score < clamp(edid_fixup, 0, 8)) {
1855 if (edid_block_is_zero(block))
1856 return EDID_BLOCK_ZERO;
1857 else
1858 return EDID_BLOCK_HEADER_CORRUPT;
1859 }
1f221284
JN		 1860
1861 if (score < 8)
1862 return EDID_BLOCK_HEADER_REPAIR;
1863 }
1864
49dc0558
JN		 1865 if (edid_block_compute_checksum(block) != edid_block_get_checksum(block)) {
1866 if (edid_block_is_zero(block))
1867 return EDID_BLOCK_ZERO;
1868 else
1869 return EDID_BLOCK_CHECKSUM;
1870 }
1f221284
JN		 1871
1872 if (is_base_block) {
1873 if (block->version != 1)
1874 return EDID_BLOCK_VERSION;
1875 }
1876
1877 return EDID_BLOCK_OK;
1878}
1879
1880static bool edid_block_status_valid(enum edid_block_status status, int tag)
1881{
1882 return status == EDID_BLOCK_OK ||
1883 status == EDID_BLOCK_HEADER_FIXED ||
1884 (status == EDID_BLOCK_CHECKSUM && tag == CEA_EXT);
1885}
1886
23e38d7b
JN		 1887static bool edid_block_valid(const void *block, bool base)
1888{
1889 return edid_block_status_valid(edid_block_check(block, base),
1890 edid_block_tag(block));
1891}
1892
cee2ce1a
JN		 1893static void edid_block_status_print(enum edid_block_status status,
1894 const struct edid *block,
1895 int block_num)
1896{
1897 switch (status) {
1898 case EDID_BLOCK_OK:
1899 break;
2deaf1c2
JN		 1900 case EDID_BLOCK_READ_FAIL:
1901 pr_debug("EDID block %d read failed\n", block_num);
1902 break;
cee2ce1a
JN		 1903 case EDID_BLOCK_NULL:
1904 pr_debug("EDID block %d pointer is NULL\n", block_num);
1905 break;
1906 case EDID_BLOCK_ZERO:
1907 pr_notice("EDID block %d is all zeroes\n", block_num);
1908 break;
1909 case EDID_BLOCK_HEADER_CORRUPT:
1910 pr_notice("EDID has corrupt header\n");
1911 break;
1912 case EDID_BLOCK_HEADER_REPAIR:
1913 pr_debug("EDID corrupt header needs repair\n");
1914 break;
1915 case EDID_BLOCK_HEADER_FIXED:
1916 pr_debug("EDID corrupt header fixed\n");
1917 break;
1918 case EDID_BLOCK_CHECKSUM:
1919 if (edid_block_status_valid(status, edid_block_tag(block))) {
1920 pr_debug("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d, ignoring\n",
1921 block_num, edid_block_tag(block),
1922 edid_block_compute_checksum(block));
1923 } else {
1924 pr_notice("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d\n",
1925 block_num, edid_block_tag(block),
1926 edid_block_compute_checksum(block));
1927 }
1928 break;
1929 case EDID_BLOCK_VERSION:
1930 pr_notice("EDID has major version %d, instead of 1\n",
1931 block->version);
1932 break;
1933 default:
1934 WARN(1, "EDID block %d unknown edid block status code %d\n",
1935 block_num, status);
1936 break;
1937 }
1938}
1939
9c7345de
JN		 1940static void edid_block_dump(const char *level, const void *block, int block_num)
1941{
1942 enum edid_block_status status;
1943 char prefix[20];
1944
1945 status = edid_block_check(block, block_num == 0);
1946 if (status == EDID_BLOCK_ZERO)
1947 sprintf(prefix, "\t[%02x] ZERO ", block_num);
1948 else if (!edid_block_status_valid(status, edid_block_tag(block)))
1949 sprintf(prefix, "\t[%02x] BAD ", block_num);
1950 else
1951 sprintf(prefix, "\t[%02x] GOOD ", block_num);
1952
1953 print_hex_dump(level, prefix, DUMP_PREFIX_NONE, 16, 1,
1954 block, EDID_LENGTH, false);
1955}
1956
db6cf833
TR		 1957/**
1958 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
5d96fc9c 1959 * @_block: pointer to raw EDID block
1f221284 1960 * @block_num: type of block to validate (0 for base, extension otherwise)
db6cf833 1961 * @print_bad_edid: if true, dump bad EDID blocks to the console
6ba2bd3d 1962 * @edid_corrupt: if true, the header or checksum is invalid
db6cf833
TR		 1963 *
1964 * Validate a base or extension EDID block and optionally dump bad blocks to
1965 * the console.
1966 *
1967 * Return: True if the block is valid, false otherwise.
f453ba04 1968 */
1f221284 1969bool drm_edid_block_valid(u8 *_block, int block_num, bool print_bad_edid,
6ba2bd3d 1970 bool *edid_corrupt)
f453ba04 1971{
1f221284
JN		 1972 struct edid *block = (struct edid *)_block;
1973 enum edid_block_status status;
1974 bool is_base_block = block_num == 0;
1975 bool valid;
f453ba04 1976
1f221284 1977 if (WARN_ON(!block))
fe2ef780
SWK		 1978 return false;
1979
1f221284
JN		 1980 status = edid_block_check(block, is_base_block);
1981 if (status == EDID_BLOCK_HEADER_REPAIR) {
1982 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1983 edid_header_fix(block);
1984
1985 /* Retry with fixed header, update status if that worked. */
1986 status = edid_block_check(block, is_base_block);
1987 if (status == EDID_BLOCK_OK)
1988 status = EDID_BLOCK_HEADER_FIXED;
61e57a8d 1989 }
f453ba04 1990
1f221284
JN		 1991 if (edid_corrupt) {
1992 /*
1993 * Unknown major version isn't corrupt but we can't use it. Only
1994 * the base block can reset edid_corrupt to false.
1995 */
1996 if (is_base_block &&
1997 (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION))
1998 *edid_corrupt = false;
1999 else if (status != EDID_BLOCK_OK)
ac6f2e29 2000 *edid_corrupt = true;
f453ba04
DA		 2001 }
2002
cee2ce1a
JN		 2003 edid_block_status_print(status, block, block_num);
2004
1f221284
JN		 2005 /* Determine whether we can use this block with this status. */
2006 valid = edid_block_status_valid(status, edid_block_tag(block));
2007
cee2ce1a
JN		 2008 if (!valid && print_bad_edid && status != EDID_BLOCK_ZERO) {
2009 pr_notice("Raw EDID:\n");
9c7345de 2010 edid_block_dump(KERN_NOTICE, block, block_num);
f453ba04 2011 }
1f221284
JN		 2012
2013 return valid;
f453ba04 2014}
da0df92b 2015EXPORT_SYMBOL(drm_edid_block_valid);
61e57a8d
AJ		 2016
2017/**
2018 * drm_edid_is_valid - sanity check EDID data
2019 * @edid: EDID data
2020 *
2021 * Sanity-check an entire EDID record (including extensions)
db6cf833
TR		 2022 *
2023 * Return: True if the EDID data is valid, false otherwise.
61e57a8d
AJ		 2024 */
2025bool drm_edid_is_valid(struct edid *edid)
2026{
2027 int i;
61e57a8d
AJ		 2028
2029 if (!edid)
2030 return false;
2031
f1e4c916
JN		 2032 for (i = 0; i < edid_block_count(edid); i++) {
2033 void *block = (void *)edid_block_data(edid, i);
2034
2035 if (!drm_edid_block_valid(block, i, true, NULL))
61e57a8d 2036 return false;
f1e4c916 2037 }
61e57a8d
AJ		 2038
2039 return true;
2040}
3c537889 2041EXPORT_SYMBOL(drm_edid_is_valid);
f453ba04 2042
6c9b3db7
JN		 2043/**
2044 * drm_edid_valid - sanity check EDID data
2045 * @drm_edid: EDID data
2046 *
2047 * Sanity check an EDID. Cross check block count against allocated size and
2048 * checksum the blocks.
2049 *
2050 * Return: True if the EDID data is valid, false otherwise.
2051 */
2052bool drm_edid_valid(const struct drm_edid *drm_edid)
2053{
2054 int i;
2055
2056 if (!drm_edid)
2057 return false;
2058
2059 if (edid_size_by_blocks(__drm_edid_block_count(drm_edid)) != drm_edid->size)
2060 return false;
2061
2062 for (i = 0; i < drm_edid_block_count(drm_edid); i++) {
2063 const void *block = drm_edid_block_data(drm_edid, i);
2064
2065 if (!edid_block_valid(block, i == 0))
2066 return false;
2067 }
2068
2069 return true;
2070}
2071EXPORT_SYMBOL(drm_edid_valid);
2072
89f4b4c5 2073static struct edid *edid_filter_invalid_blocks(struct edid *edid,
407d63b3 2074 size_t *alloc_size)
4ec53461 2075{
89f4b4c5
JN		 2076 struct edid *new;
2077 int i, valid_blocks = 0;
4ec53461 2078
18e3c1d5
JN		 2079 /*
2080 * Note: If the EDID uses HF-EEODB, but has invalid blocks, we'll revert
2081 * back to regular extension count here. We don't want to start
2082 * modifying the HF-EEODB extension too.
2083 */
89f4b4c5
JN		 2084 for (i = 0; i < edid_block_count(edid); i++) {
2085 const void *src_block = edid_block_data(edid, i);
407d63b3 2086
89f4b4c5
JN		 2087 if (edid_block_valid(src_block, i == 0)) {
2088 void *dst_block = (void *)edid_block_data(edid, valid_blocks);
4ec53461 2089
89f4b4c5
JN		 2090 memmove(dst_block, src_block, EDID_LENGTH);
2091 valid_blocks++;
2092 }
2093 }
4ec53461 2094
89f4b4c5
JN		 2095 /* We already trusted the base block to be valid here... */
2096 if (WARN_ON(!valid_blocks)) {
2097 kfree(edid);
2098 return NULL;
4ec53461
JN		 2099 }
2100
89f4b4c5
JN		 2101 edid->extensions = valid_blocks - 1;
2102 edid->checksum = edid_block_compute_checksum(edid);
4ec53461 2103
89f4b4c5
JN		 2104 *alloc_size = edid_size_by_blocks(valid_blocks);
2105
2106 new = krealloc(edid, *alloc_size, GFP_KERNEL);
2107 if (!new)
2108 kfree(edid);
4ec53461
JN		 2109
2110 return new;
2111}
2112
61e57a8d
AJ		 2113#define DDC_SEGMENT_ADDR 0x30
2114/**
db6cf833 2115 * drm_do_probe_ddc_edid() - get EDID information via I2C
7c58e87e 2116 * @data: I2C device adapter
fc66811c
DV		 2117 * @buf: EDID data buffer to be filled
2118 * @block: 128 byte EDID block to start fetching from
2119 * @len: EDID data buffer length to fetch
2120 *
db6cf833 2121 * Try to fetch EDID information by calling I2C driver functions.
61e57a8d 2122 *
db6cf833 2123 * Return: 0 on success or -1 on failure.
61e57a8d
AJ		 2124 */
2125static int
18df89fe 2126drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
61e57a8d 2127{
18df89fe 2128 struct i2c_adapter *adapter = data;
61e57a8d 2129 unsigned char start = block * EDID_LENGTH;
cd004b3f
S		 2130 unsigned char segment = block >> 1;
2131 unsigned char xfers = segment ? 3 : 2;
4819d2e4
CW		 2132 int ret, retries = 5;
2133
db6cf833
TR		 2134 /*
2135 * The core I2C driver will automatically retry the transfer if the
4819d2e4
CW		 2136 * adapter reports EAGAIN. However, we find that bit-banging transfers
2137 * are susceptible to errors under a heavily loaded machine and
2138 * generate spurious NAKs and timeouts. Retrying the transfer
2139 * of the individual block a few times seems to overcome this.
2140 */
2141 do {
2142 struct i2c_msg msgs[] = {
2143 {
cd004b3f
S		 2144 .addr = DDC_SEGMENT_ADDR,
2145 .flags = 0,
2146 .len = 1,
2147 .buf = &segment,
2148 }, {
4819d2e4
CW		 2149 .addr = DDC_ADDR,
2150 .flags = 0,
2151 .len = 1,
2152 .buf = &start,
2153 }, {
2154 .addr = DDC_ADDR,
2155 .flags = I2C_M_RD,
2156 .len = len,
2157 .buf = buf,
2158 }
2159 };
cd004b3f 2160
db6cf833
TR		 2161 /*
2162 * Avoid sending the segment addr to not upset non-compliant
2163 * DDC monitors.
2164 */
cd004b3f
S		 2165 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
2166
9292f37e
ED		 2167 if (ret == -ENXIO) {
2168 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
2169 adapter->name);
2170 break;
2171 }
cd004b3f 2172 } while (ret != xfers && --retries);
4819d2e4 2173
cd004b3f 2174 return ret == xfers ? 0 : -1;
61e57a8d
AJ		 2175}
2176
14544d09 2177static void connector_bad_edid(struct drm_connector *connector,
63cae081 2178 const struct edid *edid, int num_blocks)
14544d09
CW		 2179{
2180 int i;
97794170
DA		 2181 u8 last_block;
2182
2183 /*
2184 * 0x7e in the EDID is the number of extension blocks. The EDID
2185 * is 1 (base block) + num_ext_blocks big. That means we can think
2186 * of 0x7e in the EDID of the _index_ of the last block in the
2187 * combined chunk of memory.
2188 */
63cae081 2189 last_block = edid->extensions;
e11f5bd8
JFZ		 2190
2191 /* Calculate real checksum for the last edid extension block data */
97794170
DA		 2192 if (last_block < num_blocks)
2193 connector->real_edid_checksum =
63cae081 2194 edid_block_compute_checksum(edid + last_block);
14544d09 2195
f0a8f533 2196 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
14544d09
CW		 2197 return;
2198
fa3bfa35 2199 drm_dbg_kms(connector->dev, "%s: EDID is invalid:\n", connector->name);
63cae081
JN		 2200 for (i = 0; i < num_blocks; i++)
2201 edid_block_dump(KERN_DEBUG, edid + i, i);
14544d09
CW		 2202}
2203
56a2b7f2 2204/* Get override or firmware EDID */
407d63b3
JN		 2205static struct edid *drm_get_override_edid(struct drm_connector *connector,
2206 size_t *alloc_size)
56a2b7f2
JN		 2207{
2208 struct edid *override = NULL;
2209
90b575f5
JN		 2210 mutex_lock(&connector->edid_override_mutex);
2211
2212 if (connector->edid_override)
2213 override = drm_edid_duplicate(connector->edid_override->edid);
2214
2215 mutex_unlock(&connector->edid_override_mutex);
56a2b7f2
JN		 2216
2217 if (!override)
a05992d5 2218 override = drm_edid_load_firmware(connector);
56a2b7f2 2219
407d63b3
JN		 2220 /* FIXME: Get alloc size from deeper down the stack */
2221 if (!IS_ERR_OR_NULL(override) && alloc_size)
2222 *alloc_size = edid_size(override);
2223
56a2b7f2
JN		 2224 return IS_ERR(override) ? NULL : override;
2225}
2226
91ec9ab4
JN		 2227/* For debugfs edid_override implementation */
2228int drm_edid_override_show(struct drm_connector *connector, struct seq_file *m)
2229{
90b575f5 2230 const struct drm_edid *drm_edid;
91ec9ab4 2231
90b575f5
JN		 2232 mutex_lock(&connector->edid_override_mutex);
2233
2234 drm_edid = connector->edid_override;
2235 if (drm_edid)
2236 seq_write(m, drm_edid->edid, drm_edid->size);
2237
2238 mutex_unlock(&connector->edid_override_mutex);
91ec9ab4
JN		 2239
2240 return 0;
2241}
2242
6aa145bc
JN		 2243/* For debugfs edid_override implementation */
2244int drm_edid_override_set(struct drm_connector *connector, const void *edid,
2245 size_t size)
2246{
90b575f5 2247 const struct drm_edid *drm_edid;
6aa145bc 2248
90b575f5
JN		 2249 drm_edid = drm_edid_alloc(edid, size);
2250 if (!drm_edid_valid(drm_edid)) {
2251 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override invalid\n",
2252 connector->base.id, connector->name);
2253 drm_edid_free(drm_edid);
6aa145bc 2254 return -EINVAL;
90b575f5 2255 }
6aa145bc 2256
2c9332de
JN		 2257 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override set\n",
2258 connector->base.id, connector->name);
2259
90b575f5 2260 mutex_lock(&connector->edid_override_mutex);
6aa145bc 2261
90b575f5
JN		 2262 drm_edid_free(connector->edid_override);
2263 connector->edid_override = drm_edid;
2264
2265 mutex_unlock(&connector->edid_override_mutex);
2266
2267 return 0;
6aa145bc
JN		 2268}
2269
2270/* For debugfs edid_override implementation */
2271int drm_edid_override_reset(struct drm_connector *connector)
2272{
2c9332de
JN		 2273 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override reset\n",
2274 connector->base.id, connector->name);
2275
90b575f5
JN		 2276 mutex_lock(&connector->edid_override_mutex);
2277
2278 drm_edid_free(connector->edid_override);
2279 connector->edid_override = NULL;
2280
2281 mutex_unlock(&connector->edid_override_mutex);
2282
2283 return 0;
6aa145bc
JN		 2284}
2285
48eaeb76 2286/**
019b9387 2287 * drm_edid_override_connector_update - add modes from override/firmware EDID
48eaeb76
JN		 2288 * @connector: connector we're probing
2289 *
2290 * Add modes from the override/firmware EDID, if available. Only to be used from
2291 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
2292 * failed during drm_get_edid() and caused the override/firmware EDID to be
2293 * skipped.
2294 *
2295 * Return: The number of modes added or 0 if we couldn't find any.
2296 */
019b9387 2297int drm_edid_override_connector_update(struct drm_connector *connector)
48eaeb76
JN		 2298{
2299 struct edid *override;
2300 int num_modes = 0;
2301
407d63b3 2302 override = drm_get_override_edid(connector, NULL);
48eaeb76
JN		 2303 if (override) {
2304 drm_connector_update_edid_property(connector, override);
2305 num_modes = drm_add_edid_modes(connector, override);
2306 kfree(override);
2307
2308 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
2309 connector->base.id, connector->name, num_modes);
2310 }
2311
2312 return num_modes;
2313}
019b9387 2314EXPORT_SYMBOL(drm_edid_override_connector_update);
48eaeb76 2315
89fb7536
JN		 2316typedef int read_block_fn(void *context, u8 *buf, unsigned int block, size_t len);
2317
2deaf1c2
JN		 2318static enum edid_block_status edid_block_read(void *block, unsigned int block_num,
2319 read_block_fn read_block,
2320 void *context)
2321{
2322 enum edid_block_status status;
2323 bool is_base_block = block_num == 0;
2324 int try;
2325
2326 for (try = 0; try < 4; try++) {
2327 if (read_block(context, block, block_num, EDID_LENGTH))
2328 return EDID_BLOCK_READ_FAIL;
2329
2330 status = edid_block_check(block, is_base_block);
2331 if (status == EDID_BLOCK_HEADER_REPAIR) {
2332 edid_header_fix(block);
2333
2334 /* Retry with fixed header, update status if that worked. */
2335 status = edid_block_check(block, is_base_block);
2336 if (status == EDID_BLOCK_OK)
2337 status = EDID_BLOCK_HEADER_FIXED;
2338 }
2339
2340 if (edid_block_status_valid(status, edid_block_tag(block)))
2341 break;
2342
2343 /* Fail early for unrepairable base block all zeros. */
2344 if (try == 0 && is_base_block && status == EDID_BLOCK_ZERO)
2345 break;
2346 }
2347
2348 return status;
2349}
2350
6537f79a
JN		 2351static struct edid *_drm_do_get_edid(struct drm_connector *connector,
2352 read_block_fn read_block, void *context,
2353 size_t *size)
61e57a8d 2354{
c12561ce 2355 enum edid_block_status status;
18e3c1d5 2356 int i, num_blocks, invalid_blocks = 0;
b3eb97b6 2357 struct edid *edid, *new;
407d63b3 2358 size_t alloc_size = EDID_LENGTH;
53fd40a9 2359
407d63b3 2360 edid = drm_get_override_edid(connector, &alloc_size);
b3eb97b6 2361 if (edid)
1c788f69 2362 goto ok;
61e57a8d 2363
407d63b3 2364 edid = kmalloc(alloc_size, GFP_KERNEL);
e7bd95a7 2365 if (!edid)
61e57a8d 2366 return NULL;
61e57a8d 2367
c12561ce
JN		 2368 status = edid_block_read(edid, 0, read_block, context);
2369
2370 edid_block_status_print(status, edid, 0);
2371
2372 if (status == EDID_BLOCK_READ_FAIL)
1c788f69 2373 goto fail;
c12561ce
JN		 2374
2375 /* FIXME: Clarify what a corrupt EDID actually means. */
2376 if (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION)
2377 connector->edid_corrupt = false;
2378 else
2379 connector->edid_corrupt = true;
2380
2381 if (!edid_block_status_valid(status, edid_block_tag(edid))) {
2382 if (status == EDID_BLOCK_ZERO)
2383 connector->null_edid_counter++;
2384
2385 connector_bad_edid(connector, edid, 1);
1c788f69 2386 goto fail;
c12561ce
JN		 2387 }
2388
f1e4c916 2389 if (!edid_extension_block_count(edid))
1c788f69 2390 goto ok;
61e57a8d 2391
407d63b3
JN		 2392 alloc_size = edid_size(edid);
2393 new = krealloc(edid, alloc_size, GFP_KERNEL);
61e57a8d 2394 if (!new)
1c788f69 2395 goto fail;
f14f3686 2396 edid = new;
61e57a8d 2397
18e3c1d5
JN		 2398 num_blocks = edid_block_count(edid);
2399 for (i = 1; i < num_blocks; i++) {
f1e4c916 2400 void *block = (void *)edid_block_data(edid, i);
a28187cc 2401
f1e4c916 2402 status = edid_block_read(block, i, read_block, context);
d3da3f40 2403
f1e4c916 2404 edid_block_status_print(status, block, i);
f934ec8c 2405
d3da3f40
JN		 2406 if (!edid_block_status_valid(status, edid_block_tag(block))) {
2407 if (status == EDID_BLOCK_READ_FAIL)
1c788f69 2408 goto fail;
ccc97def 2409 invalid_blocks++;
18e3c1d5
JN		 2410 } else if (i == 1) {
2411 /*
2412 * If the first EDID extension is a CTA extension, and
2413 * the first Data Block is HF-EEODB, override the
2414 * extension block count.
2415 *
2416 * Note: HF-EEODB could specify a smaller extension
2417 * count too, but we can't risk allocating a smaller
2418 * amount.
2419 */
2420 int eeodb = edid_hfeeodb_block_count(edid);
2421
2422 if (eeodb > num_blocks) {
2423 num_blocks = eeodb;
2424 alloc_size = edid_size_by_blocks(num_blocks);
2425 new = krealloc(edid, alloc_size, GFP_KERNEL);
2426 if (!new)
2427 goto fail;
2428 edid = new;
2429 }
d3da3f40 2430 }
0ea75e23
ST		 2431 }
2432
ccc97def 2433 if (invalid_blocks) {
18e3c1d5 2434 connector_bad_edid(connector, edid, num_blocks);
14544d09 2435
89f4b4c5 2436 edid = edid_filter_invalid_blocks(edid, &alloc_size);
61e57a8d
AJ		 2437 }
2438
1c788f69 2439ok:
6537f79a
JN		 2440 if (size)
2441 *size = alloc_size;
2442
e9a9e076 2443 return edid;
61e57a8d 2444
1c788f69 2445fail:
f14f3686 2446 kfree(edid);
61e57a8d
AJ		 2447 return NULL;
2448}
6537f79a
JN		 2449
2450/**
2451 * drm_do_get_edid - get EDID data using a custom EDID block read function
2452 * @connector: connector we're probing
2453 * @read_block: EDID block read function
2454 * @context: private data passed to the block read function
2455 *
2456 * When the I2C adapter connected to the DDC bus is hidden behind a device that
2457 * exposes a different interface to read EDID blocks this function can be used
2458 * to get EDID data using a custom block read function.
2459 *
2460 * As in the general case the DDC bus is accessible by the kernel at the I2C
2461 * level, drivers must make all reasonable efforts to expose it as an I2C
2462 * adapter and use drm_get_edid() instead of abusing this function.
2463 *
2464 * The EDID may be overridden using debugfs override_edid or firmware EDID
a05992d5 2465 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
6537f79a
JN		 2466 * order. Having either of them bypasses actual EDID reads.
2467 *
2468 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2469 */
2470struct edid *drm_do_get_edid(struct drm_connector *connector,
2471 read_block_fn read_block,
2472 void *context)
2473{
2474 return _drm_do_get_edid(connector, read_block, context, NULL);
2475}
18df89fe 2476EXPORT_SYMBOL_GPL(drm_do_get_edid);
61e57a8d 2477
3d1ab66e
JN		 2478/**
2479 * drm_edid_raw - Get a pointer to the raw EDID data.
2480 * @drm_edid: drm_edid container
2481 *
2482 * Get a pointer to the raw EDID data.
2483 *
2484 * This is for transition only. Avoid using this like the plague.
2485 *
2486 * Return: Pointer to raw EDID data.
2487 */
2488const struct edid *drm_edid_raw(const struct drm_edid *drm_edid)
2489{
2490 if (!drm_edid || !drm_edid->size)
2491 return NULL;
2492
2493 /*
2494 * Do not return pointers where relying on EDID extension count would
2495 * lead to buffer overflow.
2496 */
2497 if (WARN_ON(edid_size(drm_edid->edid) > drm_edid->size))
2498 return NULL;
2499
2500 return drm_edid->edid;
2501}
2502EXPORT_SYMBOL(drm_edid_raw);
2503
6537f79a
JN		 2504/* Allocate struct drm_edid container *without* duplicating the edid data */
2505static const struct drm_edid *_drm_edid_alloc(const void *edid, size_t size)
2506{
2507 struct drm_edid *drm_edid;
2508
2509 if (!edid || !size || size < EDID_LENGTH)
2510 return NULL;
2511
2512 drm_edid = kzalloc(sizeof(*drm_edid), GFP_KERNEL);
2513 if (drm_edid) {
2514 drm_edid->edid = edid;
2515 drm_edid->size = size;
2516 }
2517
2518 return drm_edid;
2519}
2520
2521/**
2522 * drm_edid_alloc - Allocate a new drm_edid container
2523 * @edid: Pointer to raw EDID data
2524 * @size: Size of memory allocated for EDID
2525 *
2526 * Allocate a new drm_edid container. Do not calculate edid size from edid, pass
2527 * the actual size that has been allocated for the data. There is no validation
2528 * of the raw EDID data against the size, but at least the EDID base block must
2529 * fit in the buffer.
2530 *
2531 * The returned pointer must be freed using drm_edid_free().
2532 *
2533 * Return: drm_edid container, or NULL on errors
2534 */
2535const struct drm_edid *drm_edid_alloc(const void *edid, size_t size)
2536{
2537 const struct drm_edid *drm_edid;
2538
2539 if (!edid || !size || size < EDID_LENGTH)
2540 return NULL;
2541
2542 edid = kmemdup(edid, size, GFP_KERNEL);
2543 if (!edid)
2544 return NULL;
2545
2546 drm_edid = _drm_edid_alloc(edid, size);
2547 if (!drm_edid)
2548 kfree(edid);
2549
2550 return drm_edid;
2551}
2552EXPORT_SYMBOL(drm_edid_alloc);
2553
2554/**
2555 * drm_edid_dup - Duplicate a drm_edid container
2556 * @drm_edid: EDID to duplicate
2557 *
2558 * The returned pointer must be freed using drm_edid_free().
2559 *
2560 * Returns: drm_edid container copy, or NULL on errors
2561 */
2562const struct drm_edid *drm_edid_dup(const struct drm_edid *drm_edid)
2563{
2564 if (!drm_edid)
2565 return NULL;
2566
2567 return drm_edid_alloc(drm_edid->edid, drm_edid->size);
2568}
2569EXPORT_SYMBOL(drm_edid_dup);
2570
2571/**
2572 * drm_edid_free - Free the drm_edid container
2573 * @drm_edid: EDID to free
2574 */
2575void drm_edid_free(const struct drm_edid *drm_edid)
2576{
2577 if (!drm_edid)
2578 return;
2579
2580 kfree(drm_edid->edid);
2581 kfree(drm_edid);
2582}
2583EXPORT_SYMBOL(drm_edid_free);
2584
61e57a8d 2585/**
db6cf833
TR		 2586 * drm_probe_ddc() - probe DDC presence
2587 * @adapter: I2C adapter to probe
fc66811c 2588 *
db6cf833 2589 * Return: True on success, false on failure.
61e57a8d 2590 */
fbff4690 2591bool
61e57a8d
AJ		 2592drm_probe_ddc(struct i2c_adapter *adapter)
2593{
2594 unsigned char out;
2595
2596 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
2597}
fbff4690 2598EXPORT_SYMBOL(drm_probe_ddc);
61e57a8d
AJ		 2599
2600/**
2601 * drm_get_edid - get EDID data, if available
2602 * @connector: connector we're probing
db6cf833 2603 * @adapter: I2C adapter to use for DDC
61e57a8d 2604 *
db6cf833 2605 * Poke the given I2C channel to grab EDID data if possible. If found,
61e57a8d
AJ		 2606 * attach it to the connector.
2607 *
db6cf833 2608 * Return: Pointer to valid EDID or NULL if we couldn't find any.
61e57a8d
AJ		 2609 */
2610struct edid *drm_get_edid(struct drm_connector *connector,
2611 struct i2c_adapter *adapter)
2612{
5186421c
SL		 2613 struct edid *edid;
2614
15f080f0
JN		 2615 if (connector->force == DRM_FORCE_OFF)
2616 return NULL;
2617
2618 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
18df89fe 2619 return NULL;
61e57a8d 2620
6537f79a 2621 edid = _drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter, NULL);
5186421c
SL		 2622 drm_connector_update_edid_property(connector, edid);
2623 return edid;
61e57a8d
AJ		 2624}
2625EXPORT_SYMBOL(drm_get_edid);
2626
6537f79a
JN		 2627/**
2628 * drm_edid_read_custom - Read EDID data using given EDID block read function
2629 * @connector: Connector to use
2630 * @read_block: EDID block read function
2631 * @context: Private data passed to the block read function
2632 *
2633 * When the I2C adapter connected to the DDC bus is hidden behind a device that
2634 * exposes a different interface to read EDID blocks this function can be used
2635 * to get EDID data using a custom block read function.
2636 *
2637 * As in the general case the DDC bus is accessible by the kernel at the I2C
2638 * level, drivers must make all reasonable efforts to expose it as an I2C
2639 * adapter and use drm_edid_read() or drm_edid_read_ddc() instead of abusing
2640 * this function.
2641 *
2642 * The EDID may be overridden using debugfs override_edid or firmware EDID
a05992d5 2643 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
6537f79a
JN		 2644 * order. Having either of them bypasses actual EDID reads.
2645 *
2646 * The returned pointer must be freed using drm_edid_free().
2647 *
2648 * Return: Pointer to EDID, or NULL if probe/read failed.
2649 */
2650const struct drm_edid *drm_edid_read_custom(struct drm_connector *connector,
2651 read_block_fn read_block,
2652 void *context)
2653{
2654 const struct drm_edid *drm_edid;
2655 struct edid *edid;
2656 size_t size = 0;
2657
2658 edid = _drm_do_get_edid(connector, read_block, context, &size);
2659 if (!edid)
2660 return NULL;
2661
2662 /* Sanity check for now */
2663 drm_WARN_ON(connector->dev, !size);
2664
2665 drm_edid = _drm_edid_alloc(edid, size);
2666 if (!drm_edid)
2667 kfree(edid);
2668
2669 return drm_edid;
2670}
2671EXPORT_SYMBOL(drm_edid_read_custom);
2672
2673/**
2674 * drm_edid_read_ddc - Read EDID data using given I2C adapter
2675 * @connector: Connector to use
2676 * @adapter: I2C adapter to use for DDC
2677 *
2678 * Read EDID using the given I2C adapter.
2679 *
2680 * The EDID may be overridden using debugfs override_edid or firmware EDID
a05992d5 2681 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
6537f79a
JN		 2682 * order. Having either of them bypasses actual EDID reads.
2683 *
2684 * Prefer initializing connector->ddc with drm_connector_init_with_ddc() and
2685 * using drm_edid_read() instead of this function.
2686 *
2687 * The returned pointer must be freed using drm_edid_free().
2688 *
2689 * Return: Pointer to EDID, or NULL if probe/read failed.
2690 */
2691const struct drm_edid *drm_edid_read_ddc(struct drm_connector *connector,
2692 struct i2c_adapter *adapter)
2693{
2694 const struct drm_edid *drm_edid;
2695
2696 if (connector->force == DRM_FORCE_OFF)
2697 return NULL;
2698
2699 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2700 return NULL;
2701
2702 drm_edid = drm_edid_read_custom(connector, drm_do_probe_ddc_edid, adapter);
2703
2704 /* Note: Do *not* call connector updates here. */
2705
2706 return drm_edid;
2707}
2708EXPORT_SYMBOL(drm_edid_read_ddc);
2709
2710/**
2711 * drm_edid_read - Read EDID data using connector's I2C adapter
2712 * @connector: Connector to use
2713 *
2714 * Read EDID using the connector's I2C adapter.
2715 *
2716 * The EDID may be overridden using debugfs override_edid or firmware EDID
a05992d5 2717 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
6537f79a
JN		 2718 * order. Having either of them bypasses actual EDID reads.
2719 *
2720 * The returned pointer must be freed using drm_edid_free().
2721 *
2722 * Return: Pointer to EDID, or NULL if probe/read failed.
2723 */
2724const struct drm_edid *drm_edid_read(struct drm_connector *connector)
2725{
2726 if (drm_WARN_ON(connector->dev, !connector->ddc))
2727 return NULL;
2728
2729 return drm_edid_read_ddc(connector, connector->ddc);
2730}
2731EXPORT_SYMBOL(drm_edid_read);
2732
d9f91a10
DA		 2733static u32 edid_extract_panel_id(const struct edid *edid)
2734{
2735 /*
e8de4d55
DA		 2736 * We represent the ID as a 32-bit number so it can easily be compared
2737 * with "==".
d9f91a10
DA		 2738 *
2739 * NOTE that we deal with endianness differently for the top half
2740 * of this ID than for the bottom half. The bottom half (the product
2741 * id) gets decoded as little endian by the EDID_PRODUCT_ID because
2742 * that's how everyone seems to interpret it. The top half (the mfg_id)
2743 * gets stored as big endian because that makes
2744 * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier
2745 * to write (it's easier to extract the ASCII). It doesn't really
2746 * matter, though, as long as the number here is unique.
2747 */
2748 return (u32)edid->mfg_id[0] << 24 |
2749 (u32)edid->mfg_id[1] << 16 |
2750 (u32)EDID_PRODUCT_ID(edid);
2751}
2752
2753/**
2754 * drm_edid_get_panel_id - Get a panel's ID through DDC
2755 * @adapter: I2C adapter to use for DDC
2756 *
2757 * This function reads the first block of the EDID of a panel and (assuming
2758 * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value
2759 * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's
2760 * supposed to be different for each different modem of panel.
2761 *
2762 * This function is intended to be used during early probing on devices where
2763 * more than one panel might be present. Because of its intended use it must
2764 * assume that the EDID of the panel is correct, at least as far as the ID
2765 * is concerned (in other words, we don't process any overrides here).
2766 *
2767 * NOTE: it's expected that this function and drm_do_get_edid() will both
2768 * be read the EDID, but there is no caching between them. Since we're only
2769 * reading the first block, hopefully this extra overhead won't be too big.
2770 *
2771 * Return: A 32-bit ID that should be different for each make/model of panel.
2772 * See the functions drm_edid_encode_panel_id() and
2773 * drm_edid_decode_panel_id() for some details on the structure of this
2774 * ID.
2775 */
2776
2777u32 drm_edid_get_panel_id(struct i2c_adapter *adapter)
2778{
2deaf1c2
JN		 2779 enum edid_block_status status;
2780 void *base_block;
2781 u32 panel_id = 0;
d9f91a10
DA		 2782
2783 /*
2784 * There are no manufacturer IDs of 0, so if there is a problem reading
2785 * the EDID then we'll just return 0.
2786 */
2deaf1c2
JN		 2787
2788 base_block = kmalloc(EDID_LENGTH, GFP_KERNEL);
2789 if (!base_block)
d9f91a10
DA		 2790 return 0;
2791
2deaf1c2
JN		 2792 status = edid_block_read(base_block, 0, drm_do_probe_ddc_edid, adapter);
2793
2794 edid_block_status_print(status, base_block, 0);
2795
2796 if (edid_block_status_valid(status, edid_block_tag(base_block)))
2797 panel_id = edid_extract_panel_id(base_block);
2798
2799 kfree(base_block);
d9f91a10
DA		 2800
2801 return panel_id;
2802}
2803EXPORT_SYMBOL(drm_edid_get_panel_id);
2804
5cb8eaa2
LW		 2805/**
2806 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
2807 * @connector: connector we're probing
2808 * @adapter: I2C adapter to use for DDC
2809 *
2810 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
2811 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
2812 * switch DDC to the GPU which is retrieving EDID.
2813 *
2814 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2815 */
2816struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
2817 struct i2c_adapter *adapter)
2818{
36b73b05
TZ		 2819 struct drm_device *dev = connector->dev;
2820 struct pci_dev *pdev = to_pci_dev(dev->dev);
5cb8eaa2
LW		 2821 struct edid *edid;
2822
36b73b05
TZ		 2823 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev)))
2824 return NULL;
2825
5cb8eaa2
LW		 2826 vga_switcheroo_lock_ddc(pdev);
2827 edid = drm_get_edid(connector, adapter);
2828 vga_switcheroo_unlock_ddc(pdev);
2829
2830 return edid;
2831}
2832EXPORT_SYMBOL(drm_get_edid_switcheroo);
2833
51f8da59
JN		 2834/**
2835 * drm_edid_duplicate - duplicate an EDID and the extensions
2836 * @edid: EDID to duplicate
2837 *
db6cf833 2838 * Return: Pointer to duplicated EDID or NULL on allocation failure.
51f8da59
JN		 2839 */
2840struct edid *drm_edid_duplicate(const struct edid *edid)
2841{
f1e4c916 2842 return kmemdup(edid, edid_size(edid), GFP_KERNEL);
51f8da59
JN		 2843}
2844EXPORT_SYMBOL(drm_edid_duplicate);
2845
61e57a8d
AJ		 2846/*** EDID parsing ***/
2847
f453ba04
DA		 2848/**
2849 * edid_get_quirks - return quirk flags for a given EDID
e42192b4 2850 * @drm_edid: EDID to process
f453ba04
DA		 2851 *
2852 * This tells subsequent routines what fixes they need to apply.
2853 */
e42192b4 2854static u32 edid_get_quirks(const struct drm_edid *drm_edid)
f453ba04 2855{
e42192b4 2856 u32 panel_id = edid_extract_panel_id(drm_edid->edid);
23c4cfbd 2857 const struct edid_quirk *quirk;
f453ba04
DA		 2858 int i;
2859
2860 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
2861 quirk = &edid_quirk_list[i];
e8de4d55 2862 if (quirk->panel_id == panel_id)
f453ba04
DA		 2863 return quirk->quirks;
2864 }
2865
2866 return 0;
2867}
2868
2869#define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
339d202c 2870#define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
f453ba04 2871
17edb8e1
JN		 2872/*
2873 * Walk the mode list for connector, clearing the preferred status on existing
2874 * modes and setting it anew for the right mode ala quirks.
f453ba04
DA		 2875 */
2876static void edid_fixup_preferred(struct drm_connector *connector,
2877 u32 quirks)
2878{
2879 struct drm_display_mode *t, *cur_mode, *preferred_mode;
f890607b 2880 int target_refresh = 0;
339d202c 2881 int cur_vrefresh, preferred_vrefresh;
f453ba04
DA		 2882
2883 if (list_empty(&connector->probed_modes))
2884 return;
2885
2886 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
2887 target_refresh = 60;
2888 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
2889 target_refresh = 75;
2890
2891 preferred_mode = list_first_entry(&connector->probed_modes,
2892 struct drm_display_mode, head);
2893
2894 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
2895 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
2896
2897 if (cur_mode == preferred_mode)
2898 continue;
2899
2900 /* Largest mode is preferred */
2901 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
2902 preferred_mode = cur_mode;
2903
0425662f
VS		 2904 cur_vrefresh = drm_mode_vrefresh(cur_mode);
2905 preferred_vrefresh = drm_mode_vrefresh(preferred_mode);
f453ba04
DA		 2906 /* At a given size, try to get closest to target refresh */
2907 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
339d202c
AD		 2908 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
2909 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
f453ba04
DA		 2910 preferred_mode = cur_mode;
2911 }
2912 }
2913
2914 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
2915}
2916
f6e252ba
AJ		 2917static bool
2918mode_is_rb(const struct drm_display_mode *mode)
2919{
2920 return (mode->htotal - mode->hdisplay == 160) &&
2921 (mode->hsync_end - mode->hdisplay == 80) &&
2922 (mode->hsync_end - mode->hsync_start == 32) &&
2923 (mode->vsync_start - mode->vdisplay == 3);
2924}
2925
33c7531d
AJ		 2926/*
2927 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
2928 * @dev: Device to duplicate against
2929 * @hsize: Mode width
2930 * @vsize: Mode height
2931 * @fresh: Mode refresh rate
f6e252ba 2932 * @rb: Mode reduced-blanking-ness
33c7531d
AJ		 2933 *
2934 * Walk the DMT mode list looking for a match for the given parameters.
db6cf833
TR		 2935 *
2936 * Return: A newly allocated copy of the mode, or NULL if not found.
33c7531d 2937 */
1d42bbc8 2938struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
f6e252ba
AJ		 2939 int hsize, int vsize, int fresh,
2940 bool rb)
559ee21d 2941{
07a5e632 2942 int i;
559ee21d 2943
a6b21831 2944 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
b1f559ec 2945 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
948de842 2946
f8b46a05
AJ		 2947 if (hsize != ptr->hdisplay)
2948 continue;
2949 if (vsize != ptr->vdisplay)
2950 continue;
2951 if (fresh != drm_mode_vrefresh(ptr))
2952 continue;
f6e252ba
AJ		 2953 if (rb != mode_is_rb(ptr))
2954 continue;
f8b46a05
AJ		 2955
2956 return drm_mode_duplicate(dev, ptr);
559ee21d 2957 }
f8b46a05
AJ		 2958
2959 return NULL;
559ee21d 2960}
1d42bbc8 2961EXPORT_SYMBOL(drm_mode_find_dmt);
23425cae 2962
e379814b 2963static bool is_display_descriptor(const struct detailed_timing *descriptor, u8 type)
a7a131ac 2964{
e379814b
JN		 2965 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
2966 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.pad1) != 2);
2967 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.type) != 3);
2968
2969 return descriptor->pixel_clock == 0 &&
2970 descriptor->data.other_data.pad1 == 0 &&
2971 descriptor->data.other_data.type == type;
a7a131ac
VS		 2972}
2973
a9b1f15f 2974static bool is_detailed_timing_descriptor(const struct detailed_timing *descriptor)
f447dd1f 2975{
a9b1f15f
JN		 2976 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
2977
2978 return descriptor->pixel_clock != 0;
f447dd1f
VS		 2979}
2980
4194442d 2981typedef void detailed_cb(const struct detailed_timing *timing, void *closure);
d1ff6409 2982
4d76a221 2983static void
eed628f1 2984cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
4d76a221 2985{
7304b981 2986 int i, n;
4966b2a9 2987 u8 d = ext[0x02];
eed628f1 2988 const u8 *det_base = ext + d;
4d76a221 2989
7304b981
VS		 2990 if (d < 4 || d > 127)
2991 return;
2992
4966b2a9 2993 n = (127 - d) / 18;
4d76a221 2994 for (i = 0; i < n; i++)
eed628f1 2995 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
4d76a221
AJ		 2996}
2997
cbba98f8 2998static void
eed628f1 2999vtb_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
cbba98f8
AJ		 3000{
3001 unsigned int i, n = min((int)ext[0x02], 6);
eed628f1 3002 const u8 *det_base = ext + 5;
cbba98f8
AJ		 3003
3004 if (ext[0x01] != 1)
3005 return; /* unknown version */
3006
3007 for (i = 0; i < n; i++)
eed628f1 3008 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
cbba98f8
AJ		 3009}
3010
45aa2336
JN		 3011static void drm_for_each_detailed_block(const struct drm_edid *drm_edid,
3012 detailed_cb *cb, void *closure)
d1ff6409 3013{
ab1747cc
JN		 3014 struct drm_edid_iter edid_iter;
3015 const u8 *ext;
d1ff6409 3016 int i;
d1ff6409 3017
45aa2336 3018 if (!drm_edid)
d1ff6409
AJ		 3019 return;
3020
3021 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
45aa2336 3022 cb(&drm_edid->edid->detailed_timings[i], closure);
d1ff6409 3023
bbded689 3024 drm_edid_iter_begin(drm_edid, &edid_iter);
ab1747cc 3025 drm_edid_iter_for_each(ext, &edid_iter) {
4d76a221
AJ		 3026 switch (*ext) {
3027 case CEA_EXT:
3028 cea_for_each_detailed_block(ext, cb, closure);
3029 break;
cbba98f8
AJ		 3030 case VTB_EXT:
3031 vtb_for_each_detailed_block(ext, cb, closure);
3032 break;
4d76a221
AJ		 3033 default:
3034 break;
3035 }
3036 }
ab1747cc 3037 drm_edid_iter_end(&edid_iter);
d1ff6409
AJ		 3038}
3039
3040static void
4194442d 3041is_rb(const struct detailed_timing *descriptor, void *data)
d1ff6409 3042{
90fd588f 3043 bool *res = data;
a7a131ac 3044
90fd588f 3045 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
a7a131ac
VS		 3046 return;
3047
90fd588f
JN		 3048 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3049 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.cvt.flags) != 15);
3050
3051 if (descriptor->data.other_data.data.range.flags == DRM_EDID_CVT_SUPPORT_FLAG &&
afd4429e 3052 descriptor->data.other_data.data.range.formula.cvt.flags & DRM_EDID_CVT_FLAGS_REDUCED_BLANKING)
90fd588f 3053 *res = true;
d1ff6409
AJ		 3054}
3055
3056/* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
3057static bool
874d98ee 3058drm_monitor_supports_rb(const struct drm_edid *drm_edid)
d1ff6409 3059{
874d98ee 3060 if (drm_edid->edid->revision >= 4) {
b196a498 3061 bool ret = false;
948de842 3062
45aa2336 3063 drm_for_each_detailed_block(drm_edid, is_rb, &ret);
d1ff6409
AJ		 3064 return ret;
3065 }
3066
874d98ee 3067 return ((drm_edid->edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
d1ff6409
AJ		 3068}
3069
7a374350 3070static void
4194442d 3071find_gtf2(const struct detailed_timing *descriptor, void *data)
7a374350 3072{
4194442d 3073 const struct detailed_timing **res = data;
a7a131ac 3074
c8a4beba 3075 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
a7a131ac
VS		 3076 return;
3077
c8a4beba
JN		 3078 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3079
afd4429e 3080 if (descriptor->data.other_data.data.range.flags == DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG)
c8a4beba 3081 *res = descriptor;
7a374350
AJ		 3082}
3083
3084/* Secondary GTF curve kicks in above some break frequency */
3085static int
67d87fac 3086drm_gtf2_hbreak(const struct drm_edid *drm_edid)
7a374350 3087{
4194442d 3088 const struct detailed_timing *descriptor = NULL;
c8a4beba 3089
45aa2336 3090 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
948de842 3091
c8a4beba
JN		 3092 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12);
3093
3094 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.hfreq_start_khz * 2 : 0;
7a374350
AJ		 3095}
3096
3097static int
67d87fac 3098drm_gtf2_2c(const struct drm_edid *drm_edid)
7a374350 3099{
4194442d 3100 const struct detailed_timing *descriptor = NULL;
c8a4beba 3101
45aa2336 3102 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
c8a4beba
JN		 3103
3104 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.c) != 13);
948de842 3105
c8a4beba 3106 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.c : 0;
7a374350
AJ		 3107}
3108
3109static int
67d87fac 3110drm_gtf2_m(const struct drm_edid *drm_edid)
7a374350 3111{
4194442d 3112 const struct detailed_timing *descriptor = NULL;
948de842 3113
45aa2336 3114 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
c8a4beba
JN		 3115
3116 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.m) != 14);
3117
3118 return descriptor ? le16_to_cpu(descriptor->data.other_data.data.range.formula.gtf2.m) : 0;
7a374350
AJ		 3119}
3120
3121static int
67d87fac 3122drm_gtf2_k(const struct drm_edid *drm_edid)
7a374350 3123{
4194442d 3124 const struct detailed_timing *descriptor = NULL;
c8a4beba 3125
45aa2336 3126 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
948de842 3127
c8a4beba
JN		 3128 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.k) != 16);
3129
3130 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.k : 0;
7a374350
AJ		 3131}
3132
3133static int
67d87fac 3134drm_gtf2_2j(const struct drm_edid *drm_edid)
7a374350 3135{
4194442d 3136 const struct detailed_timing *descriptor = NULL;
c8a4beba 3137
45aa2336 3138 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
c8a4beba
JN		 3139
3140 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.j) != 17);
948de842 3141
c8a4beba 3142 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.j : 0;
7a374350
AJ		 3143}
3144
bf72b5ef
VS		 3145static void
3146get_timing_level(const struct detailed_timing *descriptor, void *data)
3147{
3148 int *res = data;
3149
3150 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3151 return;
3152
3153 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3154
3155 switch (descriptor->data.other_data.data.range.flags) {
3156 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG:
3157 *res = LEVEL_GTF;
3158 break;
3159 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG:
3160 *res = LEVEL_GTF2;
3161 break;
3162 case DRM_EDID_CVT_SUPPORT_FLAG:
3163 *res = LEVEL_CVT;
3164 break;
3165 default:
3166 break;
3167 }
3168}
3169
17edb8e1 3170/* Get standard timing level (CVT/GTF/DMT). */
67d87fac 3171static int standard_timing_level(const struct drm_edid *drm_edid)
7a374350 3172{
67d87fac
JN		 3173 const struct edid *edid = drm_edid->edid;
3174
bf72b5ef
VS		 3175 if (edid->revision >= 4) {
3176 /*
3177 * If the range descriptor doesn't
3178 * indicate otherwise default to CVT
3179 */
3180 int ret = LEVEL_CVT;
3181
3182 drm_for_each_detailed_block(drm_edid, get_timing_level, &ret);
3183
3184 return ret;
3185 } else if (edid->revision >= 3 && drm_gtf2_hbreak(drm_edid)) {
3186 return LEVEL_GTF2;
3187 } else if (edid->revision >= 2) {
3188 return LEVEL_GTF;
3189 } else {
3190 return LEVEL_DMT;
7a374350 3191 }
7a374350
AJ		 3192}
3193
23425cae
AJ		 3194/*
3195 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
3196 * monitors fill with ascii space (0x20) instead.
3197 */
3198static int
3199bad_std_timing(u8 a, u8 b)
3200{
3201 return (a == 0x00 && b == 0x00) ||
3202 (a == 0x01 && b == 0x01) ||
3203 (a == 0x20 && b == 0x20);
3204}
3205
58911c24
VS		 3206static int drm_mode_hsync(const struct drm_display_mode *mode)
3207{
3208 if (mode->htotal <= 0)
3209 return 0;
3210
3211 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal);
3212}
3213
86101bb7
VS		 3214static struct drm_display_mode *
3215drm_gtf2_mode(struct drm_device *dev,
3216 const struct drm_edid *drm_edid,
3217 int hsize, int vsize, int vrefresh_rate)
3218{
3219 struct drm_display_mode *mode;
3220
3221 /*
3222 * This is potentially wrong if there's ever a monitor with
3223 * more than one ranges section, each claiming a different
3224 * secondary GTF curve. Please don't do that.
3225 */
3226 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
3227 if (!mode)
3228 return NULL;
3229
3230 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(drm_edid)) {
3231 drm_mode_destroy(dev, mode);
3232 mode = drm_gtf_mode_complex(dev, hsize, vsize,
3233 vrefresh_rate, 0, 0,
3234 drm_gtf2_m(drm_edid),
3235 drm_gtf2_2c(drm_edid),
3236 drm_gtf2_k(drm_edid),
3237 drm_gtf2_2j(drm_edid));
3238 }
3239
3240 return mode;
3241}
3242
17edb8e1 3243/*
f453ba04 3244 * Take the standard timing params (in this case width, aspect, and refresh)
5c61259e 3245 * and convert them into a real mode using CVT/GTF/DMT.
f453ba04 3246 */
67d87fac
JN		 3247static struct drm_display_mode *drm_mode_std(struct drm_connector *connector,
3248 const struct drm_edid *drm_edid,
3249 const struct std_timing *t)
f453ba04 3250{
7ca6adb3
AJ		 3251 struct drm_device *dev = connector->dev;
3252 struct drm_display_mode *m, *mode = NULL;
5c61259e
ZY		 3253 int hsize, vsize;
3254 int vrefresh_rate;
0454beab
MD		 3255 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
3256 >> EDID_TIMING_ASPECT_SHIFT;
5c61259e
ZY		 3257 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
3258 >> EDID_TIMING_VFREQ_SHIFT;
67d87fac 3259 int timing_level = standard_timing_level(drm_edid);
5c61259e 3260
23425cae
AJ		 3261 if (bad_std_timing(t->hsize, t->vfreq_aspect))
3262 return NULL;
3263
5c61259e
ZY		 3264 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
3265 hsize = t->hsize * 8 + 248;
3266 /* vrefresh_rate = vfreq + 60 */
3267 vrefresh_rate = vfreq + 60;
3268 /* the vdisplay is calculated based on the aspect ratio */
f066a17d 3269 if (aspect_ratio == 0) {
67d87fac 3270 if (drm_edid->edid->revision < 3)
f066a17d
AJ		 3271 vsize = hsize;
3272 else
3273 vsize = (hsize * 10) / 16;
3274 } else if (aspect_ratio == 1)
f453ba04 3275 vsize = (hsize * 3) / 4;
0454beab 3276 else if (aspect_ratio == 2)
f453ba04
DA		 3277 vsize = (hsize * 4) / 5;
3278 else
3279 vsize = (hsize * 9) / 16;
a0910c8e
AJ		 3280
3281 /* HDTV hack, part 1 */
3282 if (vrefresh_rate == 60 &&
3283 ((hsize == 1360 && vsize == 765) ||
3284 (hsize == 1368 && vsize == 769))) {
3285 hsize = 1366;
3286 vsize = 768;
3287 }
3288
7ca6adb3
AJ		 3289 /*
3290 * If this connector already has a mode for this size and refresh
3291 * rate (because it came from detailed or CVT info), use that
3292 * instead. This way we don't have to guess at interlace or
3293 * reduced blanking.
3294 */
522032da 3295 list_for_each_entry(m, &connector->probed_modes, head)
7ca6adb3
AJ		 3296 if (m->hdisplay == hsize && m->vdisplay == vsize &&
3297 drm_mode_vrefresh(m) == vrefresh_rate)
3298 return NULL;
3299
a0910c8e
AJ		 3300 /* HDTV hack, part 2 */
3301 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
3302 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
d50ba256 3303 false);
a5ef6567
JM		 3304 if (!mode)
3305 return NULL;
559ee21d 3306 mode->hdisplay = 1366;
a4967de6
AJ		 3307 mode->hsync_start = mode->hsync_start - 1;
3308 mode->hsync_end = mode->hsync_end - 1;
559ee21d
ZY		 3309 return mode;
3310 }
a0910c8e 3311
559ee21d 3312 /* check whether it can be found in default mode table */
874d98ee 3313 if (drm_monitor_supports_rb(drm_edid)) {
f6e252ba
AJ		 3314 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
3315 true);
3316 if (mode)
3317 return mode;
3318 }
3319 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
559ee21d
ZY		 3320 if (mode)
3321 return mode;
3322
f6e252ba 3323 /* okay, generate it */
5c61259e
ZY		 3324 switch (timing_level) {
3325 case LEVEL_DMT:
5c61259e
ZY		 3326 break;
3327 case LEVEL_GTF:
3328 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
3329 break;
7a374350 3330 case LEVEL_GTF2:
86101bb7 3331 mode = drm_gtf2_mode(dev, drm_edid, hsize, vsize, vrefresh_rate);
7a374350 3332 break;
5c61259e 3333 case LEVEL_CVT:
d50ba256
DA		 3334 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
3335 false);
5c61259e
ZY		 3336 break;
3337 }
f453ba04
DA		 3338 return mode;
3339}
3340
b58db2c6
AJ		 3341/*
3342 * EDID is delightfully ambiguous about how interlaced modes are to be
3343 * encoded. Our internal representation is of frame height, but some
3344 * HDTV detailed timings are encoded as field height.
3345 *
3346 * The format list here is from CEA, in frame size. Technically we
3347 * should be checking refresh rate too. Whatever.
3348 */
3349static void
3350drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
fcfb2ea1 3351 const struct detailed_pixel_timing *pt)
b58db2c6
AJ		 3352{
3353 int i;
3354 static const struct {
3355 int w, h;
3356 } cea_interlaced[] = {
3357 { 1920, 1080 },
3358 { 720, 480 },
3359 { 1440, 480 },
3360 { 2880, 480 },
3361 { 720, 576 },
3362 { 1440, 576 },
3363 { 2880, 576 },
3364 };
b58db2c6
AJ		 3365
3366 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
3367 return;
3368
3c581411 3369 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
b58db2c6
AJ		 3370 if ((mode->hdisplay == cea_interlaced[i].w) &&
3371 (mode->vdisplay == cea_interlaced[i].h / 2)) {
3372 mode->vdisplay *= 2;
3373 mode->vsync_start *= 2;
3374 mode->vsync_end *= 2;
3375 mode->vtotal *= 2;
3376 mode->vtotal |= 1;
3377 }
3378 }
3379
3380 mode->flags |= DRM_MODE_FLAG_INTERLACE;
3381}
3382
17edb8e1
JN		 3383/*
3384 * Create a new mode from an EDID detailed timing section. An EDID detailed
3385 * timing block contains enough info for us to create and return a new struct
3386 * drm_display_mode.
f453ba04
DA		 3387 */
3388static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
f0d080ff 3389 const struct drm_edid *drm_edid,
fcfb2ea1 3390 const struct detailed_timing *timing,
f453ba04
DA		 3391 u32 quirks)
3392{
3393 struct drm_display_mode *mode;
fcfb2ea1 3394 const struct detailed_pixel_timing *pt = &timing->data.pixel_data;
0454beab
MD		 3395 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
3396 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
3397 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
3398 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
e14cbee4
MD		 3399 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
3400 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
16dad1d7 3401 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
e14cbee4 3402 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
f453ba04 3403
fc438966 3404 /* ignore tiny modes */
0454beab 3405 if (hactive < 64 || vactive < 64)
fc438966
AJ		 3406 return NULL;
3407
0454beab 3408 if (pt->misc & DRM_EDID_PT_STEREO) {
c7d015f3 3409 DRM_DEBUG_KMS("stereo mode not supported\n");
f453ba04
DA		 3410 return NULL;
3411 }
0454beab 3412 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
c7d015f3 3413 DRM_DEBUG_KMS("composite sync not supported\n");
f453ba04
DA		 3414 }
3415
fcb45611
ZY		 3416 /* it is incorrect if hsync/vsync width is zero */
3417 if (!hsync_pulse_width || !vsync_pulse_width) {
3418 DRM_DEBUG_KMS("Incorrect Detailed timing. "
3419 "Wrong Hsync/Vsync pulse width\n");
3420 return NULL;
3421 }
bc42aabc
AJ		 3422
3423 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
3424 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
3425 if (!mode)
3426 return NULL;
3427
3428 goto set_size;
3429 }
3430
f453ba04
DA		 3431 mode = drm_mode_create(dev);
3432 if (!mode)
3433 return NULL;
3434
f453ba04 3435 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
faacff8e
JN		 3436 mode->clock = 1088 * 10;
3437 else
3438 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
0454beab
MD		 3439
3440 mode->hdisplay = hactive;
3441 mode->hsync_start = mode->hdisplay + hsync_offset;
3442 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
3443 mode->htotal = mode->hdisplay + hblank;
3444
3445 mode->vdisplay = vactive;
3446 mode->vsync_start = mode->vdisplay + vsync_offset;
3447 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
3448 mode->vtotal = mode->vdisplay + vblank;
f453ba04 3449
7064fef5
JB		 3450 /* Some EDIDs have bogus h/vtotal values */
3451 if (mode->hsync_end > mode->htotal)
3452 mode->htotal = mode->hsync_end + 1;
3453 if (mode->vsync_end > mode->vtotal)
3454 mode->vtotal = mode->vsync_end + 1;
3455
b58db2c6 3456 drm_mode_do_interlace_quirk(mode, pt);
f453ba04
DA		 3457
3458 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
faacff8e
JN		 3459 mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC;
3460 } else {
3461 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
3462 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
3463 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
3464 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
f453ba04
DA		 3465 }
3466
bc42aabc 3467set_size:
e14cbee4
MD		 3468 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
3469 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
f453ba04
DA		 3470
3471 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
3472 mode->width_mm *= 10;
3473 mode->height_mm *= 10;
3474 }
3475
3476 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
f0d080ff
JN		 3477 mode->width_mm = drm_edid->edid->width_cm * 10;
3478 mode->height_mm = drm_edid->edid->height_cm * 10;
f453ba04
DA		 3479 }
3480
bc42aabc
AJ		 3481 mode->type = DRM_MODE_TYPE_DRIVER;
3482 drm_mode_set_name(mode);
3483
f453ba04
DA		 3484 return mode;
3485}
3486
b17e52ef 3487static bool
b1f559ec 3488mode_in_hsync_range(const struct drm_display_mode *mode,
c14e7241 3489 const struct edid *edid, const u8 *t)
b17e52ef
AJ		 3490{
3491 int hsync, hmin, hmax;
3492
3493 hmin = t[7];
3494 if (edid->revision >= 4)
3495 hmin += ((t[4] & 0x04) ? 255 : 0);
3496 hmax = t[8];
3497 if (edid->revision >= 4)
3498 hmax += ((t[4] & 0x08) ? 255 : 0);
07a5e632 3499 hsync = drm_mode_hsync(mode);
07a5e632 3500
b17e52ef
AJ		 3501 return (hsync <= hmax && hsync >= hmin);
3502}
3503
3504static bool
b1f559ec 3505mode_in_vsync_range(const struct drm_display_mode *mode,
c14e7241 3506 const struct edid *edid, const u8 *t)
b17e52ef
AJ		 3507{
3508 int vsync, vmin, vmax;
3509
3510 vmin = t[5];
3511 if (edid->revision >= 4)
3512 vmin += ((t[4] & 0x01) ? 255 : 0);
3513 vmax = t[6];
3514 if (edid->revision >= 4)
3515 vmax += ((t[4] & 0x02) ? 255 : 0);
3516 vsync = drm_mode_vrefresh(mode);
3517
3518 return (vsync <= vmax && vsync >= vmin);
3519}
3520
3521static u32
c14e7241 3522range_pixel_clock(const struct edid *edid, const u8 *t)
b17e52ef
AJ		 3523{
3524 /* unspecified */
3525 if (t[9] == 0 || t[9] == 255)
3526 return 0;
3527
3528 /* 1.4 with CVT support gives us real precision, yay */
afd4429e 3529 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG)
b17e52ef
AJ		 3530 return (t[9] * 10000) - ((t[12] >> 2) * 250);
3531
3532 /* 1.3 is pathetic, so fuzz up a bit */
3533 return t[9] * 10000 + 5001;
3534}
3535
874d98ee
JN		 3536static bool mode_in_range(const struct drm_display_mode *mode,
3537 const struct drm_edid *drm_edid,
3538 const struct detailed_timing *timing)
b17e52ef 3539{
874d98ee 3540 const struct edid *edid = drm_edid->edid;
b17e52ef 3541 u32 max_clock;
fcfb2ea1 3542 const u8 *t = (const u8 *)timing;
b17e52ef
AJ		 3543
3544 if (!mode_in_hsync_range(mode, edid, t))
07a5e632
AJ		 3545 return false;
3546
b17e52ef 3547 if (!mode_in_vsync_range(mode, edid, t))
07a5e632
AJ		 3548 return false;
3549
b17e52ef 3550 if ((max_clock = range_pixel_clock(edid, t)))
07a5e632
AJ		 3551 if (mode->clock > max_clock)
3552 return false;
b17e52ef
AJ		 3553
3554 /* 1.4 max horizontal check */
afd4429e 3555 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG)
b17e52ef
AJ		 3556 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
3557 return false;
3558
874d98ee 3559 if (mode_is_rb(mode) && !drm_monitor_supports_rb(drm_edid))
b17e52ef 3560 return false;
07a5e632
AJ		 3561
3562 return true;
3563}
3564
7b668ebe
TI		 3565static bool valid_inferred_mode(const struct drm_connector *connector,
3566 const struct drm_display_mode *mode)
3567{
85f8fcd6 3568 const struct drm_display_mode *m;
7b668ebe
TI		 3569 bool ok = false;
3570
3571 list_for_each_entry(m, &connector->probed_modes, head) {
3572 if (mode->hdisplay == m->hdisplay &&
3573 mode->vdisplay == m->vdisplay &&
3574 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
3575 return false; /* duplicated */
3576 if (mode->hdisplay <= m->hdisplay &&
3577 mode->vdisplay <= m->vdisplay)
3578 ok = true;
3579 }
3580 return ok;
3581}
3582
084c7a7c
JN		 3583static int drm_dmt_modes_for_range(struct drm_connector *connector,
3584 const struct drm_edid *drm_edid,
3585 const struct detailed_timing *timing)
07a5e632
AJ		 3586{
3587 int i, modes = 0;
3588 struct drm_display_mode *newmode;
3589 struct drm_device *dev = connector->dev;
3590
a6b21831 3591 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
874d98ee 3592 if (mode_in_range(drm_dmt_modes + i, drm_edid, timing) &&
7b668ebe 3593 valid_inferred_mode(connector, drm_dmt_modes + i)) {
07a5e632
AJ		 3594 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
3595 if (newmode) {
3596 drm_mode_probed_add(connector, newmode);
3597 modes++;
3598 }
3599 }
3600 }
3601
3602 return modes;
3603}
3604
c09dedb7
TI		 3605/* fix up 1366x768 mode from 1368x768;
3606 * GFT/CVT can't express 1366 width which isn't dividable by 8
3607 */
969218fe 3608void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
c09dedb7
TI		 3609{
3610 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
3611 mode->hdisplay = 1366;
3612 mode->hsync_start--;
3613 mode->hsync_end--;
3614 drm_mode_set_name(mode);
3615 }
3616}
3617
a77f7c89
JN		 3618static int drm_gtf_modes_for_range(struct drm_connector *connector,
3619 const struct drm_edid *drm_edid,
3620 const struct detailed_timing *timing)
b309bd37
AJ		 3621{
3622 int i, modes = 0;
3623 struct drm_display_mode *newmode;
3624 struct drm_device *dev = connector->dev;
3625
a6b21831 3626 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
b309bd37 3627 const struct minimode *m = &extra_modes[i];
948de842 3628
b309bd37 3629 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
fc48f169
TI		 3630 if (!newmode)
3631 return modes;
b309bd37 3632
969218fe 3633 drm_mode_fixup_1366x768(newmode);
874d98ee 3634 if (!mode_in_range(newmode, drm_edid, timing) ||
7b668ebe 3635 !valid_inferred_mode(connector, newmode)) {
b309bd37
AJ		 3636 drm_mode_destroy(dev, newmode);
3637 continue;
3638 }
3639
3640 drm_mode_probed_add(connector, newmode);
3641 modes++;
3642 }
3643
3644 return modes;
3645}
3646
9ed15f91
VS		 3647static int drm_gtf2_modes_for_range(struct drm_connector *connector,
3648 const struct drm_edid *drm_edid,
3649 const struct detailed_timing *timing)
3650{
3651 int i, modes = 0;
3652 struct drm_display_mode *newmode;
3653 struct drm_device *dev = connector->dev;
3654
3655 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3656 const struct minimode *m = &extra_modes[i];
3657
3658 newmode = drm_gtf2_mode(dev, drm_edid, m->w, m->h, m->r);
3659 if (!newmode)
3660 return modes;
3661
3662 drm_mode_fixup_1366x768(newmode);
3663 if (!mode_in_range(newmode, drm_edid, timing) ||
3664 !valid_inferred_mode(connector, newmode)) {
3665 drm_mode_destroy(dev, newmode);
3666 continue;
3667 }
3668
3669 drm_mode_probed_add(connector, newmode);
3670 modes++;
3671 }
3672
3673 return modes;
3674}
3675
7428bfbd
JN		 3676static int drm_cvt_modes_for_range(struct drm_connector *connector,
3677 const struct drm_edid *drm_edid,
3678 const struct detailed_timing *timing)
b309bd37
AJ		 3679{
3680 int i, modes = 0;
3681 struct drm_display_mode *newmode;
3682 struct drm_device *dev = connector->dev;
874d98ee 3683 bool rb = drm_monitor_supports_rb(drm_edid);
b309bd37 3684
a6b21831 3685 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
b309bd37 3686 const struct minimode *m = &extra_modes[i];
948de842 3687
b309bd37 3688 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
fc48f169
TI		 3689 if (!newmode)
3690 return modes;
b309bd37 3691
969218fe 3692 drm_mode_fixup_1366x768(newmode);
874d98ee 3693 if (!mode_in_range(newmode, drm_edid, timing) ||
7b668ebe 3694 !valid_inferred_mode(connector, newmode)) {
b309bd37
AJ		 3695 drm_mode_destroy(dev, newmode);
3696 continue;
3697 }
3698
3699 drm_mode_probed_add(connector, newmode);
3700 modes++;
3701 }
3702
3703 return modes;
3704}
3705
13931579 3706static void
4194442d 3707do_inferred_modes(const struct detailed_timing *timing, void *c)
9340d8cf 3708{
13931579 3709 struct detailed_mode_closure *closure = c;
fcfb2ea1
JN		 3710 const struct detailed_non_pixel *data = &timing->data.other_data;
3711 const struct detailed_data_monitor_range *range = &data->data.range;
9340d8cf 3712
e379814b 3713 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
cb21aafe
AJ		 3714 return;
3715
3716 closure->modes += drm_dmt_modes_for_range(closure->connector,
084c7a7c 3717 closure->drm_edid,
cb21aafe 3718 timing);
4d23f484 3719
dd3abfe4 3720 if (closure->drm_edid->edid->revision < 2)
b309bd37
AJ		 3721 return; /* GTF not defined yet */
3722
3723 switch (range->flags) {
9ed15f91
VS		 3724 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG:
3725 closure->modes += drm_gtf2_modes_for_range(closure->connector,
3726 closure->drm_edid,
3727 timing);
3728 break;
afd4429e 3729 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG:
b309bd37 3730 closure->modes += drm_gtf_modes_for_range(closure->connector,
a77f7c89 3731 closure->drm_edid,
b309bd37
AJ		 3732 timing);
3733 break;
afd4429e 3734 case DRM_EDID_CVT_SUPPORT_FLAG:
dd3abfe4 3735 if (closure->drm_edid->edid->revision < 4)
b309bd37
AJ		 3736 break;
3737
3738 closure->modes += drm_cvt_modes_for_range(closure->connector,
7428bfbd 3739 closure->drm_edid,
b309bd37
AJ		 3740 timing);
3741 break;
afd4429e 3742 case DRM_EDID_RANGE_LIMITS_ONLY_FLAG:
b309bd37
AJ		 3743 default:
3744 break;
3745 }
13931579 3746}
69da3015 3747
40f71f5b
JN		 3748static int add_inferred_modes(struct drm_connector *connector,
3749 const struct drm_edid *drm_edid)
13931579
AJ		 3750{
3751 struct detailed_mode_closure closure = {
d456ea2e 3752 .connector = connector,
dd0f4470 3753 .drm_edid = drm_edid,
13931579 3754 };
9340d8cf 3755
dd3abfe4 3756 if (drm_edid->edid->revision >= 1)
45aa2336 3757 drm_for_each_detailed_block(drm_edid, do_inferred_modes, &closure);
9340d8cf 3758
13931579 3759 return closure.modes;
9340d8cf
AJ		 3760}
3761
2255be14 3762static int
fcfb2ea1 3763drm_est3_modes(struct drm_connector *connector, const struct detailed_timing *timing)
2255be14
AJ		 3764{
3765 int i, j, m, modes = 0;
3766 struct drm_display_mode *mode;
fcfb2ea1 3767 const u8 *est = ((const u8 *)timing) + 6;
2255be14
AJ		 3768
3769 for (i = 0; i < 6; i++) {
891a7469 3770 for (j = 7; j >= 0; j--) {
2255be14 3771 m = (i * 8) + (7 - j);
3c581411 3772 if (m >= ARRAY_SIZE(est3_modes))
2255be14
AJ		 3773 break;
3774 if (est[i] & (1 << j)) {
1d42bbc8
DA		 3775 mode = drm_mode_find_dmt(connector->dev,
3776 est3_modes[m].w,
3777 est3_modes[m].h,
f6e252ba
AJ		 3778 est3_modes[m].r,
3779 est3_modes[m].rb);
2255be14
AJ		 3780 if (mode) {
3781 drm_mode_probed_add(connector, mode);
3782 modes++;
3783 }
3784 }
3785 }
3786 }
3787
3788 return modes;
3789}
3790
13931579 3791static void
4194442d 3792do_established_modes(const struct detailed_timing *timing, void *c)
9cf00977 3793{
13931579 3794 struct detailed_mode_closure *closure = c;
9cf00977 3795
e379814b 3796 if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS))
a7a131ac
VS		 3797 return;
3798
3799 closure->modes += drm_est3_modes(closure->connector, timing);
13931579 3800}
9cf00977 3801
17edb8e1
JN		 3802/*
3803 * Get established modes from EDID and add them. Each EDID block contains a
3804 * bitmap of the supported "established modes" list (defined above). Tease them
3805 * out and add them to the global modes list.
13931579 3806 */
40f71f5b
JN		 3807static int add_established_modes(struct drm_connector *connector,
3808 const struct drm_edid *drm_edid)
13931579
AJ		 3809{
3810 struct drm_device *dev = connector->dev;
40f71f5b 3811 const struct edid *edid = drm_edid->edid;
13931579
AJ		 3812 unsigned long est_bits = edid->established_timings.t1 |
3813 (edid->established_timings.t2 << 8) |
3814 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
3815 int i, modes = 0;
3816 struct detailed_mode_closure closure = {
d456ea2e 3817 .connector = connector,
dd0f4470 3818 .drm_edid = drm_edid,
13931579 3819 };
9cf00977 3820
13931579
AJ		 3821 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
3822 if (est_bits & (1<<i)) {
3823 struct drm_display_mode *newmode;
948de842 3824
13931579
AJ		 3825 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
3826 if (newmode) {
3827 drm_mode_probed_add(connector, newmode);
3828 modes++;
3829 }
3830 }
9cf00977
AJ		 3831 }
3832
dd3abfe4 3833 if (edid->revision >= 1)
45aa2336 3834 drm_for_each_detailed_block(drm_edid, do_established_modes,
eed628f1 3835 &closure);
13931579
AJ		 3836
3837 return modes + closure.modes;
3838}
3839
3840static void
4194442d 3841do_standard_modes(const struct detailed_timing *timing, void *c)
13931579
AJ		 3842{
3843 struct detailed_mode_closure *closure = c;
fcfb2ea1 3844 const struct detailed_non_pixel *data = &timing->data.other_data;
13931579 3845 struct drm_connector *connector = closure->connector;
a7a131ac 3846 int i;
13931579 3847
e379814b 3848 if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES))
a7a131ac 3849 return;
9cf00977 3850
a7a131ac 3851 for (i = 0; i < 6; i++) {
fcfb2ea1 3852 const struct std_timing *std = &data->data.timings[i];
a7a131ac
VS		 3853 struct drm_display_mode *newmode;
3854
67d87fac 3855 newmode = drm_mode_std(connector, closure->drm_edid, std);
a7a131ac
VS		 3856 if (newmode) {
3857 drm_mode_probed_add(connector, newmode);
3858 closure->modes++;
9cf00977 3859 }
9cf00977 3860 }
9cf00977
AJ		 3861}
3862
17edb8e1
JN		 3863/*
3864 * Get standard modes from EDID and add them. Standard modes can be calculated
3865 * using the appropriate standard (DMT, GTF, or CVT). Grab them from EDID and
3866 * add them to the list.
f453ba04 3867 */
40f71f5b
JN		 3868static int add_standard_modes(struct drm_connector *connector,
3869 const struct drm_edid *drm_edid)
f453ba04 3870{
9cf00977 3871 int i, modes = 0;
13931579 3872 struct detailed_mode_closure closure = {
d456ea2e 3873 .connector = connector,
dd0f4470 3874 .drm_edid = drm_edid,
13931579
AJ		 3875 };
3876
3877 for (i = 0; i < EDID_STD_TIMINGS; i++) {
3878 struct drm_display_mode *newmode;
3879
67d87fac 3880 newmode = drm_mode_std(connector, drm_edid,
40f71f5b 3881 &drm_edid->edid->standard_timings[i]);
13931579
AJ		 3882 if (newmode) {
3883 drm_mode_probed_add(connector, newmode);
3884 modes++;
3885 }
3886 }
3887
dd3abfe4 3888 if (drm_edid->edid->revision >= 1)
45aa2336 3889 drm_for_each_detailed_block(drm_edid, do_standard_modes,
13931579
AJ		 3890 &closure);
3891
3892 /* XXX should also look for standard codes in VTB blocks */
3893
3894 return modes + closure.modes;
3895}
f453ba04 3896
13931579 3897static int drm_cvt_modes(struct drm_connector *connector,
fcfb2ea1 3898 const struct detailed_timing *timing)
13931579
AJ		 3899{
3900 int i, j, modes = 0;
3901 struct drm_display_mode *newmode;
3902 struct drm_device *dev = connector->dev;
fcfb2ea1 3903 const struct cvt_timing *cvt;
13931579
AJ		 3904 const int rates[] = { 60, 85, 75, 60, 50 };
3905 const u8 empty[3] = { 0, 0, 0 };
a327f6b8 3906
13931579 3907 for (i = 0; i < 4; i++) {
3f649ab7 3908 int width, height;
948de842 3909
13931579 3910 cvt = &(timing->data.other_data.data.cvt[i]);
f453ba04 3911
13931579 3912 if (!memcmp(cvt->code, empty, 3))
9cf00977 3913 continue;
f453ba04 3914
13931579
AJ		 3915 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
3916 switch (cvt->code[1] & 0x0c) {
d652d5f1
LT		 3917 /* default - because compiler doesn't see that we've enumerated all cases */
3918 default:
13931579
AJ		 3919 case 0x00:
3920 width = height * 4 / 3;
3921 break;
3922 case 0x04:
3923 width = height * 16 / 9;
3924 break;
3925 case 0x08:
3926 width = height * 16 / 10;
3927 break;
3928 case 0x0c:
3929 width = height * 15 / 9;
3930 break;
3931 }
3932
3933 for (j = 1; j < 5; j++) {
3934 if (cvt->code[2] & (1 << j)) {
3935 newmode = drm_cvt_mode(dev, width, height,
3936 rates[j], j == 0,
3937 false, false);
3938 if (newmode) {
3939 drm_mode_probed_add(connector, newmode);
3940 modes++;
3941 }
3942 }
3943 }
f453ba04
DA		 3944 }
3945
3946 return modes;
3947}
9cf00977 3948
13931579 3949static void
4194442d 3950do_cvt_mode(const struct detailed_timing *timing, void *c)
882f0219 3951{
13931579 3952 struct detailed_mode_closure *closure = c;
882f0219 3953
e379814b 3954 if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE))
a7a131ac
VS		 3955 return;
3956
3957 closure->modes += drm_cvt_modes(closure->connector, timing);
13931579 3958}
882f0219 3959
13931579 3960static int
40f71f5b 3961add_cvt_modes(struct drm_connector *connector, const struct drm_edid *drm_edid)
4d23f484 3962{
13931579 3963 struct detailed_mode_closure closure = {
d456ea2e 3964 .connector = connector,
dd0f4470 3965 .drm_edid = drm_edid,
13931579 3966 };
882f0219 3967
dd3abfe4 3968 if (drm_edid->edid->revision >= 3)
45aa2336 3969 drm_for_each_detailed_block(drm_edid, do_cvt_mode, &closure);
882f0219 3970
13931579 3971 /* XXX should also look for CVT codes in VTB blocks */
882f0219 3972
13931579
AJ		 3973 return closure.modes;
3974}
3975
fa3a7340
VS		 3976static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
3977
13931579 3978static void
4194442d 3979do_detailed_mode(const struct detailed_timing *timing, void *c)
13931579
AJ		 3980{
3981 struct detailed_mode_closure *closure = c;
3982 struct drm_display_mode *newmode;
3983
a9b1f15f 3984 if (!is_detailed_timing_descriptor(timing))
f447dd1f
VS		 3985 return;
3986
3987 newmode = drm_mode_detailed(closure->connector->dev,
f0d080ff 3988 closure->drm_edid, timing,
f447dd1f
VS		 3989 closure->quirks);
3990 if (!newmode)
3991 return;
13931579 3992
f447dd1f
VS		 3993 if (closure->preferred)
3994 newmode->type |= DRM_MODE_TYPE_PREFERRED;
13931579 3995
f447dd1f
VS		 3996 /*
3997 * Detailed modes are limited to 10kHz pixel clock resolution,
3998 * so fix up anything that looks like CEA/HDMI mode, but the clock
3999 * is just slightly off.
4000 */
4001 fixup_detailed_cea_mode_clock(newmode);
fa3a7340 4002
f447dd1f
VS		 4003 drm_mode_probed_add(closure->connector, newmode);
4004 closure->modes++;
4005 closure->preferred = false;
13931579 4006}
882f0219 4007
13931579
AJ		 4008/*
4009 * add_detailed_modes - Add modes from detailed timings
4010 * @connector: attached connector
40f71f5b 4011 * @drm_edid: EDID block to scan
13931579
AJ		 4012 * @quirks: quirks to apply
4013 */
40f71f5b
JN		 4014static int add_detailed_modes(struct drm_connector *connector,
4015 const struct drm_edid *drm_edid, u32 quirks)
13931579
AJ		 4016{
4017 struct detailed_mode_closure closure = {
d456ea2e 4018 .connector = connector,
dd0f4470 4019 .drm_edid = drm_edid,
d456ea2e 4020 .quirks = quirks,
13931579
AJ		 4021 };
4022
dd3abfe4 4023 if (drm_edid->edid->revision >= 4)
f72f9529
VS		 4024 closure.preferred = true; /* first detailed timing is always preferred */
4025 else
13931579 4026 closure.preferred =
f72f9529 4027 drm_edid->edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING;
13931579 4028
45aa2336 4029 drm_for_each_detailed_block(drm_edid, do_detailed_mode, &closure);
13931579
AJ		 4030
4031 return closure.modes;
882f0219 4032}
f453ba04 4033
9d72b7e2
JN		 4034/* CTA-861-H Table 60 - CTA Tag Codes */
4035#define CTA_DB_AUDIO 1
4036#define CTA_DB_VIDEO 2
4037#define CTA_DB_VENDOR 3
4038#define CTA_DB_SPEAKER 4
4039#define CTA_DB_EXTENDED_TAG 7
4040
4041/* CTA-861-H Table 62 - CTA Extended Tag Codes */
4042#define CTA_EXT_DB_VIDEO_CAP 0
4043#define CTA_EXT_DB_VENDOR 1
4044#define CTA_EXT_DB_HDR_STATIC_METADATA 6
4045#define CTA_EXT_DB_420_VIDEO_DATA 14
4046#define CTA_EXT_DB_420_VIDEO_CAP_MAP 15
18e3c1d5 4047#define CTA_EXT_DB_HF_EEODB 0x78
9d72b7e2
JN		 4048#define CTA_EXT_DB_HF_SCDB 0x79
4049
8fe9790d 4050#define EDID_BASIC_AUDIO (1 << 6)
a988bc72
LPC		 4051#define EDID_CEA_YCRCB444 (1 << 5)
4052#define EDID_CEA_YCRCB422 (1 << 4)
b1edd6a6 4053#define EDID_CEA_VCDB_QS (1 << 6)
8fe9790d 4054
d4e4a31d 4055/*
8fe9790d 4056 * Search EDID for CEA extension block.
d9ba1b4c
JN		 4057 *
4058 * FIXME: Prefer not returning pointers to raw EDID data.
f23c20c8 4059 */
d9ba1b4c 4060const u8 *drm_find_edid_extension(const struct drm_edid *drm_edid,
4cc4f09e 4061 int ext_id, int *ext_index)
f23c20c8 4062{
43d16d84 4063 const u8 *edid_ext = NULL;
8fe9790d 4064 int i;
f23c20c8
ML		 4065
4066 /* No EDID or EDID extensions */
d9307f27 4067 if (!drm_edid || !drm_edid_extension_block_count(drm_edid))
8fe9790d 4068 return NULL;
f23c20c8 4069
f23c20c8 4070 /* Find CEA extension */
d9307f27
JN		 4071 for (i = *ext_index; i < drm_edid_extension_block_count(drm_edid); i++) {
4072 edid_ext = drm_edid_extension_block_data(drm_edid, i);
4ba0f53c 4073 if (edid_block_tag(edid_ext) == ext_id)
f23c20c8
ML		 4074 break;
4075 }
4076
d9307f27 4077 if (i >= drm_edid_extension_block_count(drm_edid))
8fe9790d
ZW		 4078 return NULL;
4079
8873cfa3
VS		 4080 *ext_index = i + 1;
4081
8fe9790d
ZW		 4082 return edid_ext;
4083}
4084
6ff1c19f 4085/* Return true if the EDID has a CTA extension or a DisplayID CTA data block */
40f71f5b 4086static bool drm_edid_has_cta_extension(const struct drm_edid *drm_edid)
e28ad544 4087{
43d16d84 4088 const struct displayid_block *block;
1ba63caf 4089 struct displayid_iter iter;
1ba63caf 4090 int ext_index = 0;
6ff1c19f 4091 bool found = false;
e28ad544
AR		 4092
4093 /* Look for a top level CEA extension block */
d9ba1b4c 4094 if (drm_find_edid_extension(drm_edid, CEA_EXT, &ext_index))
6ff1c19f 4095 return true;
e28ad544
AR		 4096
4097 /* CEA blocks can also be found embedded in a DisplayID block */
d9ba1b4c 4098 displayid_iter_edid_begin(drm_edid, &iter);
1ba63caf
JN		 4099 displayid_iter_for_each(block, &iter) {
4100 if (block->tag == DATA_BLOCK_CTA) {
6ff1c19f 4101 found = true;
1ba63caf 4102 break;
e28ad544
AR		 4103 }
4104 }
1ba63caf 4105 displayid_iter_end(&iter);
e28ad544 4106
6ff1c19f 4107 return found;
e28ad544
AR		 4108}
4109
e1cf35b9 4110static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic)
7befe621 4111{
9212f8ee
VS		 4112 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127);
4113 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219);
4114
8c1b2bd9
VS		 4115 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1))
4116 return &edid_cea_modes_1[vic - 1];
f7655d42
VS		 4117 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193))
4118 return &edid_cea_modes_193[vic - 193];
7befe621
VS		 4119 return NULL;
4120}
4121
4122static u8 cea_num_vics(void)
4123{
f7655d42 4124 return 193 + ARRAY_SIZE(edid_cea_modes_193);
7befe621
VS		 4125}
4126
4127static u8 cea_next_vic(u8 vic)
4128{
8c1b2bd9 4129 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1))
f7655d42
VS		 4130 vic = 193;
4131 return vic;
7befe621
VS		 4132}
4133
e6e79209
VS		 4134/*
4135 * Calculate the alternate clock for the CEA mode
4136 * (60Hz vs. 59.94Hz etc.)
4137 */
4138static unsigned int
4139cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
4140{
4141 unsigned int clock = cea_mode->clock;
4142
0425662f 4143 if (drm_mode_vrefresh(cea_mode) % 6 != 0)
e6e79209
VS		 4144 return clock;
4145
4146 /*
4147 * edid_cea_modes contains the 59.94Hz
4148 * variant for 240 and 480 line modes,
4149 * and the 60Hz variant otherwise.
4150 */
4151 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
9afd808c 4152 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
e6e79209 4153 else
9afd808c 4154 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
e6e79209
VS		 4155
4156 return clock;
4157}
4158
c45a4e46
VS		 4159static bool
4160cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
4161{
4162 /*
4163 * For certain VICs the spec allows the vertical
4164 * front porch to vary by one or two lines.
4165 *
4166 * cea_modes[] stores the variant with the shortest
4167 * vertical front porch. We can adjust the mode to
4168 * get the other variants by simply increasing the
4169 * vertical front porch length.
4170 */
7befe621
VS		 4171 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 ||
4172 cea_mode_for_vic(9)->vtotal != 262 ||
4173 cea_mode_for_vic(12)->vtotal != 262 ||
4174 cea_mode_for_vic(13)->vtotal != 262 ||
4175 cea_mode_for_vic(23)->vtotal != 312 ||
4176 cea_mode_for_vic(24)->vtotal != 312 ||
4177 cea_mode_for_vic(27)->vtotal != 312 ||
4178 cea_mode_for_vic(28)->vtotal != 312);
c45a4e46
VS		 4179
4180 if (((vic == 8 || vic == 9 ||
4181 vic == 12 || vic == 13) && mode->vtotal < 263) ||
4182 ((vic == 23 || vic == 24 ||
4183 vic == 27 || vic == 28) && mode->vtotal < 314)) {
4184 mode->vsync_start++;
4185 mode->vsync_end++;
4186 mode->vtotal++;
4187
4188 return true;
4189 }
4190
4191 return false;
4192}
4193
4c6bcf44
VS		 4194static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
4195 unsigned int clock_tolerance)
4196{
357768cc 4197 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 4198 u8 vic;
4c6bcf44
VS		 4199
4200 if (!to_match->clock)
4201 return 0;
4202
357768cc
VS		 4203 if (to_match->picture_aspect_ratio)
4204 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4205
7befe621 4206 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
563c4a75 4207 struct drm_display_mode cea_mode;
4c6bcf44
VS		 4208 unsigned int clock1, clock2;
4209
563c4a75
VS		 4210 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
4211
4c6bcf44 4212 /* Check both 60Hz and 59.94Hz */
c45a4e46
VS		 4213 clock1 = cea_mode.clock;
4214 clock2 = cea_mode_alternate_clock(&cea_mode);
4c6bcf44
VS		 4215
4216 if (abs(to_match->clock - clock1) > clock_tolerance &&
4217 abs(to_match->clock - clock2) > clock_tolerance)
4218 continue;
4219
c45a4e46 4220 do {
357768cc 4221 if (drm_mode_match(to_match, &cea_mode, match_flags))
c45a4e46
VS		 4222 return vic;
4223 } while (cea_mode_alternate_timings(vic, &cea_mode));
4c6bcf44
VS		 4224 }
4225
4226 return 0;
4227}
4228
18316c8c
TR		 4229/**
4230 * drm_match_cea_mode - look for a CEA mode matching given mode
4231 * @to_match: display mode
4232 *
db6cf833 4233 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
18316c8c 4234 * mode.
a4799037 4235 */
18316c8c 4236u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
a4799037 4237{
357768cc 4238 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 4239 u8 vic;
a4799037 4240
a90b590e
VS		 4241 if (!to_match->clock)
4242 return 0;
4243
357768cc
VS		 4244 if (to_match->picture_aspect_ratio)
4245 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4246
7befe621 4247 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
563c4a75 4248 struct drm_display_mode cea_mode;
a90b590e
VS		 4249 unsigned int clock1, clock2;
4250
563c4a75
VS		 4251 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
4252
a90b590e 4253 /* Check both 60Hz and 59.94Hz */
c45a4e46
VS		 4254 clock1 = cea_mode.clock;
4255 clock2 = cea_mode_alternate_clock(&cea_mode);
a4799037 4256
c45a4e46
VS		 4257 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
4258 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
4259 continue;
4260
4261 do {
357768cc 4262 if (drm_mode_match(to_match, &cea_mode, match_flags))
c45a4e46
VS		 4263 return vic;
4264 } while (cea_mode_alternate_timings(vic, &cea_mode));
a4799037 4265 }
c45a4e46 4266
a4799037
SM		 4267 return 0;
4268}
4269EXPORT_SYMBOL(drm_match_cea_mode);
4270
d9278b4c
JN		 4271static bool drm_valid_cea_vic(u8 vic)
4272{
7befe621 4273 return cea_mode_for_vic(vic) != NULL;
d9278b4c
JN		 4274}
4275
28c03a44 4276static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
0967e6a5 4277{
7befe621
VS		 4278 const struct drm_display_mode *mode = cea_mode_for_vic(video_code);
4279
4280 if (mode)
4281 return mode->picture_aspect_ratio;
4282
4283 return HDMI_PICTURE_ASPECT_NONE;
0967e6a5 4284}
0967e6a5 4285
d2b43473
WL		 4286static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code)
4287{
4288 return edid_4k_modes[video_code].picture_aspect_ratio;
4289}
4290
3f2f6533
LD		 4291/*
4292 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
4293 * specific block).
3f2f6533
LD		 4294 */
4295static unsigned int
4296hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
4297{
3f2f6533
LD		 4298 return cea_mode_alternate_clock(hdmi_mode);
4299}
4300
4c6bcf44
VS		 4301static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
4302 unsigned int clock_tolerance)
4303{
357768cc 4304 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 4305 u8 vic;
4c6bcf44
VS		 4306
4307 if (!to_match->clock)
4308 return 0;
4309
d2b43473
WL		 4310 if (to_match->picture_aspect_ratio)
4311 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4312
d9278b4c
JN		 4313 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
4314 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4c6bcf44
VS		 4315 unsigned int clock1, clock2;
4316
4317 /* Make sure to also match alternate clocks */
4318 clock1 = hdmi_mode->clock;
4319 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
4320
4321 if (abs(to_match->clock - clock1) > clock_tolerance &&
4322 abs(to_match->clock - clock2) > clock_tolerance)
4323 continue;
4324
357768cc 4325 if (drm_mode_match(to_match, hdmi_mode, match_flags))
d9278b4c 4326 return vic;
4c6bcf44
VS		 4327 }
4328
4329 return 0;
4330}
4331
3f2f6533
LD		 4332/*
4333 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
4334 * @to_match: display mode
4335 *
4336 * An HDMI mode is one defined in the HDMI vendor specific block.
4337 *
4338 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
4339 */
4340static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
4341{
357768cc 4342 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 4343 u8 vic;
3f2f6533
LD		 4344
4345 if (!to_match->clock)
4346 return 0;
4347
d2b43473
WL		 4348 if (to_match->picture_aspect_ratio)
4349 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4350
d9278b4c
JN		 4351 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
4352 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3f2f6533
LD		 4353 unsigned int clock1, clock2;
4354
4355 /* Make sure to also match alternate clocks */
4356 clock1 = hdmi_mode->clock;
4357 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
4358
4359 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
4360 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
357768cc 4361 drm_mode_match(to_match, hdmi_mode, match_flags))
d9278b4c 4362 return vic;
3f2f6533
LD		 4363 }
4364 return 0;
4365}
4366
d9278b4c
JN		 4367static bool drm_valid_hdmi_vic(u8 vic)
4368{
4369 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
4370}
4371
40f71f5b
JN		 4372static int add_alternate_cea_modes(struct drm_connector *connector,
4373 const struct drm_edid *drm_edid)
e6e79209
VS		 4374{
4375 struct drm_device *dev = connector->dev;
4376 struct drm_display_mode *mode, *tmp;
4377 LIST_HEAD(list);
4378 int modes = 0;
4379
6ff1c19f 4380 /* Don't add CTA modes if the CTA extension block is missing */
40f71f5b 4381 if (!drm_edid_has_cta_extension(drm_edid))
e6e79209
VS		 4382 return 0;
4383
4384 /*
4385 * Go through all probed modes and create a new mode
4386 * with the alternate clock for certain CEA modes.
4387 */
4388 list_for_each_entry(mode, &connector->probed_modes, head) {
3f2f6533 4389 const struct drm_display_mode *cea_mode = NULL;
e6e79209 4390 struct drm_display_mode *newmode;
d9278b4c 4391 u8 vic = drm_match_cea_mode(mode);
e6e79209
VS		 4392 unsigned int clock1, clock2;
4393
d9278b4c 4394 if (drm_valid_cea_vic(vic)) {
7befe621 4395 cea_mode = cea_mode_for_vic(vic);
3f2f6533
LD		 4396 clock2 = cea_mode_alternate_clock(cea_mode);
4397 } else {
d9278b4c
JN		 4398 vic = drm_match_hdmi_mode(mode);
4399 if (drm_valid_hdmi_vic(vic)) {
4400 cea_mode = &edid_4k_modes[vic];
3f2f6533
LD		 4401 clock2 = hdmi_mode_alternate_clock(cea_mode);
4402 }
4403 }
e6e79209 4404
3f2f6533
LD		 4405 if (!cea_mode)
4406 continue;
e6e79209
VS		 4407
4408 clock1 = cea_mode->clock;
e6e79209
VS		 4409
4410 if (clock1 == clock2)
4411 continue;
4412
4413 if (mode->clock != clock1 && mode->clock != clock2)
4414 continue;
4415
4416 newmode = drm_mode_duplicate(dev, cea_mode);
4417 if (!newmode)
4418 continue;
4419
27130212
DL		 4420 /* Carry over the stereo flags */
4421 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
4422
e6e79209
VS		 4423 /*
4424 * The current mode could be either variant. Make
4425 * sure to pick the "other" clock for the new mode.
4426 */
4427 if (mode->clock != clock1)
4428 newmode->clock = clock1;
4429 else
4430 newmode->clock = clock2;
4431
4432 list_add_tail(&newmode->head, &list);
4433 }
4434
4435 list_for_each_entry_safe(mode, tmp, &list, head) {
4436 list_del(&mode->head);
4437 drm_mode_probed_add(connector, mode);
4438 modes++;
4439 }
4440
4441 return modes;
4442}
a4799037 4443
8ec6e075
SS		 4444static u8 svd_to_vic(u8 svd)
4445{
4446 /* 0-6 bit vic, 7th bit native mode indicator */
4447 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
4448 return svd & 127;
4449
4450 return svd;
4451}
4452
aff04ace
TW		 4453static struct drm_display_mode *
4454drm_display_mode_from_vic_index(struct drm_connector *connector,
4455 const u8 *video_db, u8 video_len,
4456 u8 video_index)
54ac76f8
CS		 4457{
4458 struct drm_device *dev = connector->dev;
aff04ace 4459 struct drm_display_mode *newmode;
d9278b4c 4460 u8 vic;
54ac76f8 4461
aff04ace
TW		 4462 if (video_db == NULL || video_index >= video_len)
4463 return NULL;
4464
4465 /* CEA modes are numbered 1..127 */
8ec6e075 4466 vic = svd_to_vic(video_db[video_index]);
d9278b4c 4467 if (!drm_valid_cea_vic(vic))
aff04ace
TW		 4468 return NULL;
4469
7befe621 4470 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
409bbf1e
DL		 4471 if (!newmode)
4472 return NULL;
4473
aff04ace
TW		 4474 return newmode;
4475}
4476
832d4f2f
SS		 4477/*
4478 * do_y420vdb_modes - Parse YCBCR 420 only modes
4479 * @connector: connector corresponding to the HDMI sink
4480 * @svds: start of the data block of CEA YCBCR 420 VDB
4481 * @len: length of the CEA YCBCR 420 VDB
4482 *
4483 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
4484 * which contains modes which can be supported in YCBCR 420
4485 * output format only.
4486 */
4487static int do_y420vdb_modes(struct drm_connector *connector,
4488 const u8 *svds, u8 svds_len)
4489{
4490 int modes = 0, i;
4491 struct drm_device *dev = connector->dev;
4492 struct drm_display_info *info = &connector->display_info;
4493 struct drm_hdmi_info *hdmi = &info->hdmi;
4494
4495 for (i = 0; i < svds_len; i++) {
4496 u8 vic = svd_to_vic(svds[i]);
4497 struct drm_display_mode *newmode;
4498
4499 if (!drm_valid_cea_vic(vic))
4500 continue;
4501
7befe621 4502 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
832d4f2f
SS		 4503 if (!newmode)
4504 break;
4505 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
4506 drm_mode_probed_add(connector, newmode);
4507 modes++;
4508 }
4509
4510 if (modes > 0)
c03d0b52 4511 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
832d4f2f
SS		 4512 return modes;
4513}
4514
4515/*
4516 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap
4517 * @connector: connector corresponding to the HDMI sink
4518 * @vic: CEA vic for the video mode to be added in the map
4519 *
4520 * Makes an entry for a videomode in the YCBCR 420 bitmap
4521 */
4522static void
4523drm_add_cmdb_modes(struct drm_connector *connector, u8 svd)
4524{
4525 u8 vic = svd_to_vic(svd);
4526 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4527
4528 if (!drm_valid_cea_vic(vic))
4529 return;
4530
4531 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
4532}
4533
7af655bc
VS		 4534/**
4535 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC
4536 * @dev: DRM device
8d7d8c0a 4537 * @video_code: CEA VIC of the mode
7af655bc
VS		 4538 *
4539 * Creates a new mode matching the specified CEA VIC.
4540 *
4541 * Returns: A new drm_display_mode on success or NULL on failure
4542 */
4543struct drm_display_mode *
4544drm_display_mode_from_cea_vic(struct drm_device *dev,
4545 u8 video_code)
4546{
4547 const struct drm_display_mode *cea_mode;
4548 struct drm_display_mode *newmode;
4549
4550 cea_mode = cea_mode_for_vic(video_code);
4551 if (!cea_mode)
4552 return NULL;
4553
4554 newmode = drm_mode_duplicate(dev, cea_mode);
4555 if (!newmode)
4556 return NULL;
4557
4558 return newmode;
4559}
4560EXPORT_SYMBOL(drm_display_mode_from_cea_vic);
4561
aff04ace
TW		 4562static int
4563do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
4564{
4565 int i, modes = 0;
832d4f2f 4566 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
aff04ace
TW		 4567
4568 for (i = 0; i < len; i++) {
4569 struct drm_display_mode *mode;
948de842 4570
aff04ace
TW		 4571 mode = drm_display_mode_from_vic_index(connector, db, len, i);
4572 if (mode) {
832d4f2f
SS		 4573 /*
4574 * YCBCR420 capability block contains a bitmap which
4575 * gives the index of CEA modes from CEA VDB, which
4576 * can support YCBCR 420 sampling output also (apart
4577 * from RGB/YCBCR444 etc).
4578 * For example, if the bit 0 in bitmap is set,
4579 * first mode in VDB can support YCBCR420 output too.
4580 * Add YCBCR420 modes only if sink is HDMI 2.0 capable.
4581 */
4582 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i))
4583 drm_add_cmdb_modes(connector, db[i]);
4584
aff04ace
TW		 4585 drm_mode_probed_add(connector, mode);
4586 modes++;
54ac76f8
CS		 4587 }
4588 }
4589
4590 return modes;
4591}
4592
c858cfca
DL		 4593struct stereo_mandatory_mode {
4594 int width, height, vrefresh;
4595 unsigned int flags;
4596};
4597
4598static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
f7e121b7
DL		 4599 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4600 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
c858cfca
DL		 4601 { 1920, 1080, 50,
4602 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
4603 { 1920, 1080, 60,
4604 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
f7e121b7
DL		 4605 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4606 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
4607 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4608 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
c858cfca
DL		 4609};
4610
4611static bool
4612stereo_match_mandatory(const struct drm_display_mode *mode,
4613 const struct stereo_mandatory_mode *stereo_mode)
4614{
4615 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
4616
4617 return mode->hdisplay == stereo_mode->width &&
4618 mode->vdisplay == stereo_mode->height &&
4619 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
4620 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
4621}
4622
c858cfca
DL		 4623static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
4624{
4625 struct drm_device *dev = connector->dev;
4626 const struct drm_display_mode *mode;
4627 struct list_head stereo_modes;
f7e121b7 4628 int modes = 0, i;
c858cfca
DL		 4629
4630 INIT_LIST_HEAD(&stereo_modes);
4631
4632 list_for_each_entry(mode, &connector->probed_modes, head) {
f7e121b7
DL		 4633 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
4634 const struct stereo_mandatory_mode *mandatory;
c858cfca
DL		 4635 struct drm_display_mode *new_mode;
4636
f7e121b7
DL		 4637 if (!stereo_match_mandatory(mode,
4638 &stereo_mandatory_modes[i]))
4639 continue;
c858cfca 4640
f7e121b7 4641 mandatory = &stereo_mandatory_modes[i];
c858cfca
DL		 4642 new_mode = drm_mode_duplicate(dev, mode);
4643 if (!new_mode)
4644 continue;
4645
f7e121b7 4646 new_mode->flags |= mandatory->flags;
c858cfca
DL		 4647 list_add_tail(&new_mode->head, &stereo_modes);
4648 modes++;
f7e121b7 4649 }
c858cfca
DL		 4650 }
4651
4652 list_splice_tail(&stereo_modes, &connector->probed_modes);
4653
4654 return modes;
4655}
4656
1deee8d7
DL		 4657static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
4658{
4659 struct drm_device *dev = connector->dev;
4660 struct drm_display_mode *newmode;
4661
d9278b4c 4662 if (!drm_valid_hdmi_vic(vic)) {
1deee8d7
DL		 4663 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
4664 return 0;
4665 }
4666
4667 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
4668 if (!newmode)
4669 return 0;
4670
4671 drm_mode_probed_add(connector, newmode);
4672
4673 return 1;
4674}
4675
fbf46025
TW		 4676static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
4677 const u8 *video_db, u8 video_len, u8 video_index)
4678{
fbf46025
TW		 4679 struct drm_display_mode *newmode;
4680 int modes = 0;
fbf46025
TW		 4681
4682 if (structure & (1 << 0)) {
aff04ace
TW		 4683 newmode = drm_display_mode_from_vic_index(connector, video_db,
4684 video_len,
4685 video_index);
fbf46025
TW		 4686 if (newmode) {
4687 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
4688 drm_mode_probed_add(connector, newmode);
4689 modes++;
4690 }
4691 }
4692 if (structure & (1 << 6)) {
aff04ace
TW		 4693 newmode = drm_display_mode_from_vic_index(connector, video_db,
4694 video_len,
4695 video_index);
fbf46025
TW		 4696 if (newmode) {
4697 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4698 drm_mode_probed_add(connector, newmode);
4699 modes++;
4700 }
4701 }
4702 if (structure & (1 << 8)) {
aff04ace
TW		 4703 newmode = drm_display_mode_from_vic_index(connector, video_db,
4704 video_len,
4705 video_index);
fbf46025 4706 if (newmode) {
89570eeb 4707 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
fbf46025
TW		 4708 drm_mode_probed_add(connector, newmode);
4709 modes++;
4710 }
4711 }
4712
4713 return modes;
4714}
4715
7ebe1963
LD		 4716/*
4717 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
4718 * @connector: connector corresponding to the HDMI sink
4719 * @db: start of the CEA vendor specific block
4720 * @len: length of the CEA block payload, ie. one can access up to db[len]
4721 *
c858cfca
DL		 4722 * Parses the HDMI VSDB looking for modes to add to @connector. This function
4723 * also adds the stereo 3d modes when applicable.
7ebe1963
LD		 4724 */
4725static int
fbf46025
TW		 4726do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
4727 const u8 *video_db, u8 video_len)
7ebe1963 4728{
f1781e9b 4729 struct drm_display_info *info = &connector->display_info;
0e5083aa 4730 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
fbf46025
TW		 4731 u8 vic_len, hdmi_3d_len = 0;
4732 u16 mask;
4733 u16 structure_all;
7ebe1963
LD		 4734
4735 if (len < 8)
4736 goto out;
4737
4738 /* no HDMI_Video_Present */
4739 if (!(db[8] & (1 << 5)))
4740 goto out;
4741
4742 /* Latency_Fields_Present */
4743 if (db[8] & (1 << 7))
4744 offset += 2;
4745
4746 /* I_Latency_Fields_Present */
4747 if (db[8] & (1 << 6))
4748 offset += 2;
4749
4750 /* the declared length is not long enough for the 2 first bytes
4751 * of additional video format capabilities */
c858cfca 4752 if (len < (8 + offset + 2))
7ebe1963
LD		 4753 goto out;
4754
c858cfca
DL		 4755 /* 3D_Present */
4756 offset++;
fbf46025 4757 if (db[8 + offset] & (1 << 7)) {
c858cfca
DL		 4758 modes += add_hdmi_mandatory_stereo_modes(connector);
4759
fbf46025
TW		 4760 /* 3D_Multi_present */
4761 multi_present = (db[8 + offset] & 0x60) >> 5;
4762 }
4763
c858cfca 4764 offset++;
7ebe1963 4765 vic_len = db[8 + offset] >> 5;
fbf46025 4766 hdmi_3d_len = db[8 + offset] & 0x1f;
7ebe1963
LD		 4767
4768 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
7ebe1963
LD		 4769 u8 vic;
4770
4771 vic = db[9 + offset + i];
1deee8d7 4772 modes += add_hdmi_mode(connector, vic);
7ebe1963 4773 }
fbf46025
TW		 4774 offset += 1 + vic_len;
4775
0e5083aa
TW		 4776 if (multi_present == 1)
4777 multi_len = 2;
4778 else if (multi_present == 2)
4779 multi_len = 4;
4780 else
4781 multi_len = 0;
fbf46025 4782
0e5083aa 4783 if (len < (8 + offset + hdmi_3d_len - 1))
fbf46025
TW		 4784 goto out;
4785
0e5083aa 4786 if (hdmi_3d_len < multi_len)
fbf46025
TW		 4787 goto out;
4788
0e5083aa
TW		 4789 if (multi_present == 1 || multi_present == 2) {
4790 /* 3D_Structure_ALL */
4791 structure_all = (db[8 + offset] << 8) | db[9 + offset];
fbf46025 4792
0e5083aa
TW		 4793 /* check if 3D_MASK is present */
4794 if (multi_present == 2)
4795 mask = (db[10 + offset] << 8) | db[11 + offset];
4796 else
4797 mask = 0xffff;
4798
4799 for (i = 0; i < 16; i++) {
4800 if (mask & (1 << i))
4801 modes += add_3d_struct_modes(connector,
4802 structure_all,
4803 video_db,
4804 video_len, i);
4805 }
4806 }
4807
4808 offset += multi_len;
4809
4810 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
4811 int vic_index;
4812 struct drm_display_mode *newmode = NULL;
4813 unsigned int newflag = 0;
4814 bool detail_present;
4815
4816 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
4817
4818 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
4819 break;
4820
4821 /* 2D_VIC_order_X */
4822 vic_index = db[8 + offset + i] >> 4;
4823
4824 /* 3D_Structure_X */
4825 switch (db[8 + offset + i] & 0x0f) {
4826 case 0:
4827 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
4828 break;
4829 case 6:
4830 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4831 break;
4832 case 8:
4833 /* 3D_Detail_X */
4834 if ((db[9 + offset + i] >> 4) == 1)
4835 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4836 break;
4837 }
4838
4839 if (newflag != 0) {
4840 newmode = drm_display_mode_from_vic_index(connector,
4841 video_db,
4842 video_len,
4843 vic_index);
4844
4845 if (newmode) {
4846 newmode->flags |= newflag;
4847 drm_mode_probed_add(connector, newmode);
4848 modes++;
4849 }
4850 }
4851
4852 if (detail_present)
4853 i++;
fbf46025 4854 }
7ebe1963
LD		 4855
4856out:
f1781e9b
VS		 4857 if (modes > 0)
4858 info->has_hdmi_infoframe = true;
7ebe1963
LD		 4859 return modes;
4860}
4861
9e50b9d5
VS		 4862static int
4863cea_revision(const u8 *cea)
4864{
5036c0d0
VS		 4865 /*
4866 * FIXME is this correct for the DispID variant?
4867 * The DispID spec doesn't really specify whether
4868 * this is the revision of the CEA extension or
4869 * the DispID CEA data block. And the only value
4870 * given as an example is 0.
4871 */
9e50b9d5
VS		 4872 return cea[1];
4873}
4874
aba58254
JN		 4875/*
4876 * CTA Data Block iterator.
4877 *
4878 * Iterate through all CTA Data Blocks in both EDID CTA Extensions and DisplayID
4879 * CTA Data Blocks.
4880 *
4881 * struct cea_db *db:
4882 * struct cea_db_iter iter;
4883 *
4884 * cea_db_iter_edid_begin(edid, &iter);
4885 * cea_db_iter_for_each(db, &iter) {
4886 * // do stuff with db
4887 * }
4888 * cea_db_iter_end(&iter);
4889 */
4890struct cea_db_iter {
4891 struct drm_edid_iter edid_iter;
4892 struct displayid_iter displayid_iter;
4893
4894 /* Current Data Block Collection. */
4895 const u8 *collection;
4896
4897 /* Current Data Block index in current collection. */
4898 int index;
4899
4900 /* End index in current collection. */
4901 int end;
4902};
4903
4904/* CTA-861-H section 7.4 CTA Data BLock Collection */
4905struct cea_db {
4906 u8 tag_length;
4907 u8 data[];
4908} __packed;
4909
49a62a29 4910static int cea_db_tag(const struct cea_db *db)
aba58254 4911{
aba58254
JN		 4912 return db->tag_length >> 5;
4913}
4914
4915static int cea_db_payload_len(const void *_db)
4916{
4917 /* FIXME: Transition to passing struct cea_db * everywhere. */
4918 const struct cea_db *db = _db;
4919
4920 return db->tag_length & 0x1f;
4921}
4922
4923static const void *cea_db_data(const struct cea_db *db)
4924{
4925 return db->data;
4926}
4927
a9ec4fd0
JN		 4928static bool cea_db_is_extended_tag(const struct cea_db *db, int tag)
4929{
4930 return cea_db_tag(db) == CTA_DB_EXTENDED_TAG &&
4931 cea_db_payload_len(db) >= 1 &&
4932 db->data[0] == tag;
4933}
4934
4935static bool cea_db_is_vendor(const struct cea_db *db, int vendor_oui)
4936{
4937 const u8 *data = cea_db_data(db);
4938
4939 return cea_db_tag(db) == CTA_DB_VENDOR &&
4940 cea_db_payload_len(db) >= 3 &&
4941 oui(data[2], data[1], data[0]) == vendor_oui;
4942}
4943
5e87b2e5
JN		 4944static void cea_db_iter_edid_begin(const struct drm_edid *drm_edid,
4945 struct cea_db_iter *iter)
aba58254
JN		 4946{
4947 memset(iter, 0, sizeof(*iter));
4948
bbded689 4949 drm_edid_iter_begin(drm_edid, &iter->edid_iter);
d9ba1b4c 4950 displayid_iter_edid_begin(drm_edid, &iter->displayid_iter);
aba58254
JN		 4951}
4952
4953static const struct cea_db *
4954__cea_db_iter_current_block(const struct cea_db_iter *iter)
4955{
4956 const struct cea_db *db;
4957
4958 if (!iter->collection)
4959 return NULL;
4960
4961 db = (const struct cea_db *)&iter->collection[iter->index];
4962
4963 if (iter->index + sizeof(*db) <= iter->end &&
4964 iter->index + sizeof(*db) + cea_db_payload_len(db) <= iter->end)
4965 return db;
4966
4967 return NULL;
4968}
4969
11a8d095
JN		 4970/*
4971 * References:
4972 * - CTA-861-H section 7.3.3 CTA Extension Version 3
4973 */
4974static int cea_db_collection_size(const u8 *cta)
4975{
4976 u8 d = cta[2];
4977
4978 if (d < 4 || d > 127)
4979 return 0;
4980
4981 return d - 4;
4982}
4983
aba58254
JN		 4984/*
4985 * References:
4986 * - VESA E-EDID v1.4
4987 * - CTA-861-H section 7.3.3 CTA Extension Version 3
4988 */
4989static const void *__cea_db_iter_edid_next(struct cea_db_iter *iter)
4990{
4991 const u8 *ext;
4992
4993 drm_edid_iter_for_each(ext, &iter->edid_iter) {
11a8d095
JN		 4994 int size;
4995
aba58254
JN		 4996 /* Only support CTA Extension revision 3+ */
4997 if (ext[0] != CEA_EXT || cea_revision(ext) < 3)
4998 continue;
4999
11a8d095
JN		 5000 size = cea_db_collection_size(ext);
5001 if (!size)
aba58254
JN		 5002 continue;
5003
11a8d095
JN		 5004 iter->index = 4;
5005 iter->end = iter->index + size;
5006
aba58254
JN		 5007 return ext;
5008 }
5009
5010 return NULL;
5011}
5012
5013/*
5014 * References:
5015 * - DisplayID v1.3 Appendix C: CEA Data Block within a DisplayID Data Block
5016 * - DisplayID v2.0 section 4.10 CTA DisplayID Data Block
5017 *
5018 * Note that the above do not specify any connection between DisplayID Data
5019 * Block revision and CTA Extension versions.
5020 */
5021static const void *__cea_db_iter_displayid_next(struct cea_db_iter *iter)
5022{
5023 const struct displayid_block *block;
5024
5025 displayid_iter_for_each(block, &iter->displayid_iter) {
5026 if (block->tag != DATA_BLOCK_CTA)
5027 continue;
5028
5029 /*
5030 * The displayid iterator has already verified the block bounds
5031 * in displayid_iter_block().
5032 */
5033 iter->index = sizeof(*block);
5034 iter->end = iter->index + block->num_bytes;
5035
5036 return block;
5037 }
5038
5039 return NULL;
5040}
5041
5042static const struct cea_db *__cea_db_iter_next(struct cea_db_iter *iter)
5043{
5044 const struct cea_db *db;
5045
5046 if (iter->collection) {
5047 /* Current collection should always be valid. */
5048 db = __cea_db_iter_current_block(iter);
5049 if (WARN_ON(!db)) {
5050 iter->collection = NULL;
5051 return NULL;
5052 }
5053
5054 /* Next block in CTA Data Block Collection */
5055 iter->index += sizeof(*db) + cea_db_payload_len(db);
5056
5057 db = __cea_db_iter_current_block(iter);
5058 if (db)
5059 return db;
5060 }
5061
5062 for (;;) {
5063 /*
5064 * Find the next CTA Data Block Collection. First iterate all
5065 * the EDID CTA Extensions, then all the DisplayID CTA blocks.
5066 *
5067 * Per DisplayID v1.3 Appendix B: DisplayID as an EDID
5068 * Extension, it's recommended that DisplayID extensions are
5069 * exposed after all of the CTA Extensions.
5070 */
5071 iter->collection = __cea_db_iter_edid_next(iter);
5072 if (!iter->collection)
5073 iter->collection = __cea_db_iter_displayid_next(iter);
5074
5075 if (!iter->collection)
5076 return NULL;
5077
5078 db = __cea_db_iter_current_block(iter);
5079 if (db)
5080 return db;
5081 }
5082}
5083
5084#define cea_db_iter_for_each(__db, __iter) \
5085 while (((__db) = __cea_db_iter_next(__iter)))
5086
5087static void cea_db_iter_end(struct cea_db_iter *iter)
5088{
5089 displayid_iter_end(&iter->displayid_iter);
5090 drm_edid_iter_end(&iter->edid_iter);
5091
5092 memset(iter, 0, sizeof(*iter));
5093}
5094
49a62a29 5095static bool cea_db_is_hdmi_vsdb(const struct cea_db *db)
7ebe1963 5096{
a9ec4fd0
JN		 5097 return cea_db_is_vendor(db, HDMI_IEEE_OUI) &&
5098 cea_db_payload_len(db) >= 5;
7ebe1963
LD		 5099}
5100
49a62a29 5101static bool cea_db_is_hdmi_forum_vsdb(const struct cea_db *db)
50dd1bd1 5102{
a9ec4fd0
JN		 5103 return cea_db_is_vendor(db, HDMI_FORUM_IEEE_OUI) &&
5104 cea_db_payload_len(db) >= 7;
50dd1bd1
TR		 5105}
5106
18e3c1d5
JN		 5107static bool cea_db_is_hdmi_forum_eeodb(const void *db)
5108{
5109 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_EEODB) &&
5110 cea_db_payload_len(db) >= 2;
5111}
5112
49a62a29 5113static bool cea_db_is_microsoft_vsdb(const struct cea_db *db)
2869f599 5114{
a9ec4fd0
JN		 5115 return cea_db_is_vendor(db, MICROSOFT_IEEE_OUI) &&
5116 cea_db_payload_len(db) == 21;
2869f599
PZ		 5117}
5118
49a62a29 5119static bool cea_db_is_vcdb(const struct cea_db *db)
1581b2df 5120{
a9ec4fd0
JN		 5121 return cea_db_is_extended_tag(db, CTA_EXT_DB_VIDEO_CAP) &&
5122 cea_db_payload_len(db) == 2;
1581b2df
VS		 5123}
5124
49a62a29 5125static bool cea_db_is_hdmi_forum_scdb(const struct cea_db *db)
115fcf58 5126{
a9ec4fd0
JN		 5127 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_SCDB) &&
5128 cea_db_payload_len(db) >= 7;
115fcf58
LS		 5129}
5130
49a62a29 5131static bool cea_db_is_y420cmdb(const struct cea_db *db)
832d4f2f 5132{
a9ec4fd0 5133 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_CAP_MAP);
832d4f2f
SS		 5134}
5135
49a62a29 5136static bool cea_db_is_y420vdb(const struct cea_db *db)
832d4f2f 5137{
a9ec4fd0
JN		 5138 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_DATA);
5139}
832d4f2f 5140
49a62a29 5141static bool cea_db_is_hdmi_hdr_metadata_block(const struct cea_db *db)
a9ec4fd0
JN		 5142{
5143 return cea_db_is_extended_tag(db, CTA_EXT_DB_HDR_STATIC_METADATA) &&
5144 cea_db_payload_len(db) >= 3;
832d4f2f
SS		 5145}
5146
18e3c1d5
JN		 5147/*
5148 * Get the HF-EEODB override extension block count from EDID.
5149 *
5150 * The passed in EDID may be partially read, as long as it has at least two
5151 * blocks (base block and one extension block) if EDID extension count is > 0.
5152 *
5153 * Note that this is *not* how you should parse CTA Data Blocks in general; this
5154 * is only to handle partially read EDIDs. Normally, use the CTA Data Block
5155 * iterators instead.
5156 *
5157 * References:
5158 * - HDMI 2.1 section 10.3.6 HDMI Forum EDID Extension Override Data Block
5159 */
5160static int edid_hfeeodb_extension_block_count(const struct edid *edid)
5161{
5162 const u8 *cta;
5163
5164 /* No extensions according to base block, no HF-EEODB. */
5165 if (!edid_extension_block_count(edid))
5166 return 0;
5167
5168 /* HF-EEODB is always in the first EDID extension block only */
5169 cta = edid_extension_block_data(edid, 0);
5170 if (edid_block_tag(cta) != CEA_EXT || cea_revision(cta) < 3)
5171 return 0;
5172
5173 /* Need to have the data block collection, and at least 3 bytes. */
5174 if (cea_db_collection_size(cta) < 3)
5175 return 0;
5176
5177 /*
5178 * Sinks that include the HF-EEODB in their E-EDID shall include one and
5179 * only one instance of the HF-EEODB in the E-EDID, occupying bytes 4
5180 * through 6 of Block 1 of the E-EDID.
5181 */
5182 if (!cea_db_is_hdmi_forum_eeodb(&cta[4]))
5183 return 0;
5184
5185 return cta[4 + 2];
5186}
5187
832d4f2f
SS		 5188static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector,
5189 const u8 *db)
5190{
5191 struct drm_display_info *info = &connector->display_info;
5192 struct drm_hdmi_info *hdmi = &info->hdmi;
5193 u8 map_len = cea_db_payload_len(db) - 1;
5194 u8 count;
5195 u64 map = 0;
5196
5197 if (map_len == 0) {
5198 /* All CEA modes support ycbcr420 sampling also.*/
5199 hdmi->y420_cmdb_map = U64_MAX;
c03d0b52 5200 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
832d4f2f
SS		 5201 return;
5202 }
5203
5204 /*
5205 * This map indicates which of the existing CEA block modes
5206 * from VDB can support YCBCR420 output too. So if bit=0 is
5207 * set, first mode from VDB can support YCBCR420 output too.
5208 * We will parse and keep this map, before parsing VDB itself
5209 * to avoid going through the same block again and again.
5210 *
5211 * Spec is not clear about max possible size of this block.
5212 * Clamping max bitmap block size at 8 bytes. Every byte can
5213 * address 8 CEA modes, in this way this map can address
5214 * 8*8 = first 64 SVDs.
5215 */
5216 if (WARN_ON_ONCE(map_len > 8))
5217 map_len = 8;
5218
5219 for (count = 0; count < map_len; count++)
5220 map |= (u64)db[2 + count] << (8 * count);
5221
5222 if (map)
c03d0b52 5223 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
832d4f2f
SS		 5224
5225 hdmi->y420_cmdb_map = map;
5226}
5227
40f71f5b
JN		 5228static int add_cea_modes(struct drm_connector *connector,
5229 const struct drm_edid *drm_edid)
54ac76f8 5230{
537d9ed2
JN		 5231 const struct cea_db *db;
5232 struct cea_db_iter iter;
54ac76f8
CS		 5233 int modes = 0;
5234
5e87b2e5 5235 cea_db_iter_edid_begin(drm_edid, &iter);
537d9ed2
JN		 5236 cea_db_iter_for_each(db, &iter) {
5237 const u8 *hdmi = NULL, *video = NULL;
5238 u8 hdmi_len = 0, video_len = 0;
5239
5240 if (cea_db_tag(db) == CTA_DB_VIDEO) {
5241 video = cea_db_data(db);
5242 video_len = cea_db_payload_len(db);
5243 modes += do_cea_modes(connector, video, video_len);
5244 } else if (cea_db_is_hdmi_vsdb(db)) {
5245 /* FIXME: Switch to use cea_db_data() */
5246 hdmi = (const u8 *)db;
5247 hdmi_len = cea_db_payload_len(db);
5248 } else if (cea_db_is_y420vdb(db)) {
5249 const u8 *vdb420 = cea_db_data(db) + 1;
5250
5251 /* Add 4:2:0(only) modes present in EDID */
5252 modes += do_y420vdb_modes(connector, vdb420,
5253 cea_db_payload_len(db) - 1);
54ac76f8 5254 }
54ac76f8 5255
537d9ed2
JN		 5256 /*
5257 * We parse the HDMI VSDB after having added the cea modes as we
5258 * will be patching their flags when the sink supports stereo
5259 * 3D.
5260 */
5261 if (hdmi)
5262 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len,
5263 video, video_len);
5264 }
5265 cea_db_iter_end(&iter);
c858cfca 5266
54ac76f8
CS		 5267 return modes;
5268}
5269
fa3a7340
VS		 5270static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
5271{
5272 const struct drm_display_mode *cea_mode;
5273 int clock1, clock2, clock;
d9278b4c 5274 u8 vic;
fa3a7340
VS		 5275 const char *type;
5276
4c6bcf44
VS		 5277 /*
5278 * allow 5kHz clock difference either way to account for
5279 * the 10kHz clock resolution limit of detailed timings.
5280 */
d9278b4c
JN		 5281 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
5282 if (drm_valid_cea_vic(vic)) {
fa3a7340 5283 type = "CEA";
7befe621 5284 cea_mode = cea_mode_for_vic(vic);
fa3a7340
VS		 5285 clock1 = cea_mode->clock;
5286 clock2 = cea_mode_alternate_clock(cea_mode);
5287 } else {
d9278b4c
JN		 5288 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
5289 if (drm_valid_hdmi_vic(vic)) {
fa3a7340 5290 type = "HDMI";
d9278b4c 5291 cea_mode = &edid_4k_modes[vic];
fa3a7340
VS		 5292 clock1 = cea_mode->clock;
5293 clock2 = hdmi_mode_alternate_clock(cea_mode);
5294 } else {
5295 return;
5296 }
5297 }
5298
5299 /* pick whichever is closest */
5300 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
5301 clock = clock1;
5302 else
5303 clock = clock2;
5304
5305 if (mode->clock == clock)
5306 return;
5307
5308 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
d9278b4c 5309 type, vic, mode->clock, clock);
fa3a7340
VS		 5310 mode->clock = clock;
5311}
5312
82068ede
JH		 5313static void drm_calculate_luminance_range(struct drm_connector *connector)
5314{
5315 struct hdr_static_metadata *hdr_metadata = &connector->hdr_sink_metadata.hdmi_type1;
5316 struct drm_luminance_range_info *luminance_range =
5317 &connector->display_info.luminance_range;
5318 static const u8 pre_computed_values[] = {
5319 50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69,
5320 71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98
5321 };
5322 u32 max_avg, min_cll, max, min, q, r;
5323
5324 if (!(hdr_metadata->metadata_type & BIT(HDMI_STATIC_METADATA_TYPE1)))
5325 return;
5326
5327 max_avg = hdr_metadata->max_fall;
5328 min_cll = hdr_metadata->min_cll;
5329
5330 /*
5331 * From the specification (CTA-861-G), for calculating the maximum
5332 * luminance we need to use:
5333 * Luminance = 50*2**(CV/32)
5334 * Where CV is a one-byte value.
5335 * For calculating this expression we may need float point precision;
5336 * to avoid this complexity level, we take advantage that CV is divided
5337 * by a constant. From the Euclids division algorithm, we know that CV
5338 * can be written as: CV = 32*q + r. Next, we replace CV in the
5339 * Luminance expression and get 50*(2**q)*(2**(r/32)), hence we just
5340 * need to pre-compute the value of r/32. For pre-computing the values
5341 * We just used the following Ruby line:
5342 * (0...32).each {|cv| puts (50*2**(cv/32.0)).round}
5343 * The results of the above expressions can be verified at
5344 * pre_computed_values.
5345 */
5346 q = max_avg >> 5;
5347 r = max_avg % 32;
5348 max = (1 << q) * pre_computed_values[r];
5349
5350 /* min luminance: maxLum * (CV/255)^2 / 100 */
5351 q = DIV_ROUND_CLOSEST(min_cll, 255);
5352 min = max * DIV_ROUND_CLOSEST((q * q), 100);
5353
5354 luminance_range->min_luminance = min;
5355 luminance_range->max_luminance = max;
5356}
5357
e85959d6
US		 5358static uint8_t eotf_supported(const u8 *edid_ext)
5359{
5360 return edid_ext[2] &
5361 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
5362 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
b5e3eed1
VS		 5363 BIT(HDMI_EOTF_SMPTE_ST2084) |
5364 BIT(HDMI_EOTF_BT_2100_HLG));
e85959d6
US		 5365}
5366
5367static uint8_t hdr_metadata_type(const u8 *edid_ext)
5368{
5369 return edid_ext[3] &
5370 BIT(HDMI_STATIC_METADATA_TYPE1);
5371}
5372
5373static void
5374drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
5375{
5376 u16 len;
5377
5378 len = cea_db_payload_len(db);
5379
5380 connector->hdr_sink_metadata.hdmi_type1.eotf =
5381 eotf_supported(db);
5382 connector->hdr_sink_metadata.hdmi_type1.metadata_type =
5383 hdr_metadata_type(db);
5384
5385 if (len >= 4)
5386 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4];
5387 if (len >= 5)
5388 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5];
82068ede 5389 if (len >= 6) {
e85959d6 5390 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6];
82068ede
JH		 5391
5392 /* Calculate only when all values are available */
5393 drm_calculate_luminance_range(connector);
5394 }
e85959d6
US		 5395}
5396
76adaa34 5397static void
23ebf8b9 5398drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
76adaa34 5399{
8504072a 5400 u8 len = cea_db_payload_len(db);
76adaa34 5401
f7da7785
JN		 5402 if (len >= 6 && (db[6] & (1 << 7)))
5403 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
8504072a
VS		 5404 if (len >= 8) {
5405 connector->latency_present[0] = db[8] >> 7;
5406 connector->latency_present[1] = (db[8] >> 6) & 1;
5407 }
5408 if (len >= 9)
5409 connector->video_latency[0] = db[9];
5410 if (len >= 10)
5411 connector->audio_latency[0] = db[10];
5412 if (len >= 11)
5413 connector->video_latency[1] = db[11];
5414 if (len >= 12)
5415 connector->audio_latency[1] = db[12];
76adaa34 5416
23ebf8b9
VS		 5417 DRM_DEBUG_KMS("HDMI: latency present %d %d, "
5418 "video latency %d %d, "
5419 "audio latency %d %d\n",
5420 connector->latency_present[0],
5421 connector->latency_present[1],
5422 connector->video_latency[0],
5423 connector->video_latency[1],
5424 connector->audio_latency[0],
5425 connector->audio_latency[1]);
76adaa34
WF		 5426}
5427
5428static void
4194442d 5429monitor_name(const struct detailed_timing *timing, void *data)
76adaa34 5430{
4194442d
JN		 5431 const char **res = data;
5432
5433 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME))
a7a131ac
VS		 5434 return;
5435
4194442d 5436 *res = timing->data.other_data.data.str.str;
14f77fdd
VS		 5437}
5438
2c54f87c 5439static int get_monitor_name(const struct drm_edid *drm_edid, char name[13])
59f7c0fa 5440{
4194442d 5441 const char *edid_name = NULL;
59f7c0fa
JB		 5442 int mnl;
5443
2c54f87c 5444 if (!drm_edid || !name)
59f7c0fa
JB		 5445 return 0;
5446
45aa2336 5447 drm_for_each_detailed_block(drm_edid, monitor_name, &edid_name);
59f7c0fa
JB		 5448 for (mnl = 0; edid_name && mnl < 13; mnl++) {
5449 if (edid_name[mnl] == 0x0a)
5450 break;
5451
5452 name[mnl] = edid_name[mnl];
5453 }
5454
5455 return mnl;
5456}
5457
5458/**
5459 * drm_edid_get_monitor_name - fetch the monitor name from the edid
5460 * @edid: monitor EDID information
5461 * @name: pointer to a character array to hold the name of the monitor
5462 * @bufsize: The size of the name buffer (should be at least 14 chars.)
5463 *
5464 */
f4e558ec 5465void drm_edid_get_monitor_name(const struct edid *edid, char *name, int bufsize)
59f7c0fa 5466{
2c54f87c 5467 int name_length = 0;
4d23f484 5468
59f7c0fa
JB		 5469 if (bufsize <= 0)
5470 return;
5471
2c54f87c
JN		 5472 if (edid) {
5473 char buf[13];
5474 struct drm_edid drm_edid = {
5475 .edid = edid,
5476 .size = edid_size(edid),
5477 };
5478
5479 name_length = min(get_monitor_name(&drm_edid, buf), bufsize - 1);
5480 memcpy(name, buf, name_length);
5481 }
5482
59f7c0fa
JB		 5483 name[name_length] = '\0';
5484}
5485EXPORT_SYMBOL(drm_edid_get_monitor_name);
5486
42750d39
JN		 5487static void clear_eld(struct drm_connector *connector)
5488{
5489 memset(connector->eld, 0, sizeof(connector->eld));
5490
5491 connector->latency_present[0] = false;
5492 connector->latency_present[1] = false;
5493 connector->video_latency[0] = 0;
5494 connector->audio_latency[0] = 0;
5495 connector->video_latency[1] = 0;
5496 connector->audio_latency[1] = 0;
5497}
5498
79436a1c 5499/*
76adaa34
WF		 5500 * drm_edid_to_eld - build ELD from EDID
5501 * @connector: connector corresponding to the HDMI/DP sink
a2f9790d 5502 * @drm_edid: EDID to parse
76adaa34 5503 *
db6cf833 5504 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
1d1c3665 5505 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
76adaa34 5506 */
f4e558ec 5507static void drm_edid_to_eld(struct drm_connector *connector,
a2f9790d 5508 const struct drm_edid *drm_edid)
76adaa34 5509{
58304630 5510 const struct drm_display_info *info = &connector->display_info;
37852141
JN		 5511 const struct cea_db *db;
5512 struct cea_db_iter iter;
76adaa34 5513 uint8_t *eld = connector->eld;
7c018782 5514 int total_sad_count = 0;
76adaa34 5515 int mnl;
76adaa34 5516
42750d39 5517 clear_eld(connector);
85c91580 5518
a2f9790d 5519 if (!drm_edid)
e9bd0b84
JN		 5520 return;
5521
2c54f87c 5522 mnl = get_monitor_name(drm_edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
f7da7785 5523 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]);
59f7c0fa 5524
58304630 5525 eld[DRM_ELD_CEA_EDID_VER_MNL] = info->cea_rev << DRM_ELD_CEA_EDID_VER_SHIFT;
f7da7785 5526 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
76adaa34 5527
f7da7785 5528 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
76adaa34 5529
a2f9790d
JN		 5530 eld[DRM_ELD_MANUFACTURER_NAME0] = drm_edid->edid->mfg_id[0];
5531 eld[DRM_ELD_MANUFACTURER_NAME1] = drm_edid->edid->mfg_id[1];
5532 eld[DRM_ELD_PRODUCT_CODE0] = drm_edid->edid->prod_code[0];
5533 eld[DRM_ELD_PRODUCT_CODE1] = drm_edid->edid->prod_code[1];
76adaa34 5534
5e87b2e5 5535 cea_db_iter_edid_begin(drm_edid, &iter);
37852141
JN		 5536 cea_db_iter_for_each(db, &iter) {
5537 const u8 *data = cea_db_data(db);
5538 int len = cea_db_payload_len(db);
deec222e 5539 int sad_count;
9e50b9d5 5540
37852141
JN		 5541 switch (cea_db_tag(db)) {
5542 case CTA_DB_AUDIO:
5543 /* Audio Data Block, contains SADs */
5544 sad_count = min(len / 3, 15 - total_sad_count);
5545 if (sad_count >= 1)
5546 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
5547 data, sad_count * 3);
5548 total_sad_count += sad_count;
5549 break;
5550 case CTA_DB_SPEAKER:
5551 /* Speaker Allocation Data Block */
5552 if (len >= 1)
5553 eld[DRM_ELD_SPEAKER] = data[0];
5554 break;
5555 case CTA_DB_VENDOR:
5556 /* HDMI Vendor-Specific Data Block */
5557 if (cea_db_is_hdmi_vsdb(db))
5558 drm_parse_hdmi_vsdb_audio(connector, (const u8 *)db);
5559 break;
5560 default:
5561 break;
76adaa34 5562 }
9e50b9d5 5563 }
37852141
JN		 5564 cea_db_iter_end(&iter);
5565
f7da7785 5566 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
76adaa34 5567
1d1c3665
JN		 5568 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5569 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5570 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
5571 else
5572 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
76adaa34 5573
938fd8aa
JN		 5574 eld[DRM_ELD_BASELINE_ELD_LEN] =
5575 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
5576
5577 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
7c018782 5578 drm_eld_size(eld), total_sad_count);
76adaa34 5579}
76adaa34 5580
bba4b647
JN		 5581static int _drm_edid_to_sad(const struct drm_edid *drm_edid,
5582 struct cea_sad **sads)
fe214163 5583{
b07debc2
JN		 5584 const struct cea_db *db;
5585 struct cea_db_iter iter;
fe214163 5586 int count = 0;
fe214163 5587
5e87b2e5 5588 cea_db_iter_edid_begin(drm_edid, &iter);
b07debc2 5589 cea_db_iter_for_each(db, &iter) {
9d72b7e2 5590 if (cea_db_tag(db) == CTA_DB_AUDIO) {
fe214163 5591 int j;
948de842 5592
b07debc2 5593 count = cea_db_payload_len(db) / 3; /* SAD is 3B */
fe214163
RM		 5594 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
5595 if (!*sads)
5596 return -ENOMEM;
5597 for (j = 0; j < count; j++) {
b07debc2 5598 const u8 *sad = &db->data[j * 3];
fe214163
RM		 5599
5600 (*sads)[j].format = (sad[0] & 0x78) >> 3;
5601 (*sads)[j].channels = sad[0] & 0x7;
5602 (*sads)[j].freq = sad[1] & 0x7F;
5603 (*sads)[j].byte2 = sad[2];
5604 }
5605 break;
5606 }
5607 }
b07debc2
JN		 5608 cea_db_iter_end(&iter);
5609
5610 DRM_DEBUG_KMS("Found %d Short Audio Descriptors\n", count);
fe214163
RM		 5611
5612 return count;
5613}
bba4b647
JN		 5614
5615/**
5616 * drm_edid_to_sad - extracts SADs from EDID
5617 * @edid: EDID to parse
5618 * @sads: pointer that will be set to the extracted SADs
5619 *
5620 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
5621 *
5622 * Note: The returned pointer needs to be freed using kfree().
5623 *
5624 * Return: The number of found SADs or negative number on error.
5625 */
5626int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads)
5627{
5628 struct drm_edid drm_edid;
5629
5630 return _drm_edid_to_sad(drm_edid_legacy_init(&drm_edid, edid), sads);
5631}
fe214163
RM		 5632EXPORT_SYMBOL(drm_edid_to_sad);
5633
02703451
JN		 5634static int _drm_edid_to_speaker_allocation(const struct drm_edid *drm_edid,
5635 u8 **sadb)
d105f476 5636{
ed317307
JN		 5637 const struct cea_db *db;
5638 struct cea_db_iter iter;
d105f476 5639 int count = 0;
d105f476 5640
5e87b2e5 5641 cea_db_iter_edid_begin(drm_edid, &iter);
ed317307
JN		 5642 cea_db_iter_for_each(db, &iter) {
5643 if (cea_db_tag(db) == CTA_DB_SPEAKER &&
5644 cea_db_payload_len(db) == 3) {
5645 *sadb = kmemdup(db->data, cea_db_payload_len(db),
5646 GFP_KERNEL);
5647 if (!*sadb)
5648 return -ENOMEM;
5649 count = cea_db_payload_len(db);
5650 break;
d105f476
AD		 5651 }
5652 }
ed317307
JN		 5653 cea_db_iter_end(&iter);
5654
5655 DRM_DEBUG_KMS("Found %d Speaker Allocation Data Blocks\n", count);
d105f476
AD		 5656
5657 return count;
5658}
02703451
JN		 5659
5660/**
5661 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
5662 * @edid: EDID to parse
5663 * @sadb: pointer to the speaker block
5664 *
5665 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
5666 *
5667 * Note: The returned pointer needs to be freed using kfree().
5668 *
5669 * Return: The number of found Speaker Allocation Blocks or negative number on
5670 * error.
5671 */
5672int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb)
5673{
5674 struct drm_edid drm_edid;
5675
5676 return _drm_edid_to_speaker_allocation(drm_edid_legacy_init(&drm_edid, edid),
5677 sadb);
5678}
d105f476
AD		 5679EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
5680
76adaa34 5681/**
db6cf833 5682 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
76adaa34
WF		 5683 * @connector: connector associated with the HDMI/DP sink
5684 * @mode: the display mode
db6cf833
TR		 5685 *
5686 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
5687 * the sink doesn't support audio or video.
76adaa34
WF		 5688 */
5689int drm_av_sync_delay(struct drm_connector *connector,
3a818d35 5690 const struct drm_display_mode *mode)
76adaa34
WF		 5691{
5692 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
5693 int a, v;
5694
5695 if (!connector->latency_present[0])
5696 return 0;
5697 if (!connector->latency_present[1])
5698 i = 0;
5699
5700 a = connector->audio_latency[i];
5701 v = connector->video_latency[i];
5702
5703 /*
5704 * HDMI/DP sink doesn't support audio or video?
5705 */
5706 if (a == 255 || v == 255)
5707 return 0;
5708
5709 /*
5710 * Convert raw EDID values to millisecond.
5711 * Treat unknown latency as 0ms.
5712 */
5713 if (a)
5714 a = min(2 * (a - 1), 500);
5715 if (v)
5716 v = min(2 * (v - 1), 500);
5717
5718 return max(v - a, 0);
5719}
5720EXPORT_SYMBOL(drm_av_sync_delay);
5721
3176d092 5722static bool _drm_detect_hdmi_monitor(const struct drm_edid *drm_edid)
8fe9790d 5723{
4ce08703
JN		 5724 const struct cea_db *db;
5725 struct cea_db_iter iter;
5726 bool hdmi = false;
f23c20c8
ML		 5727
5728 /*
5729 * Because HDMI identifier is in Vendor Specific Block,
5730 * search it from all data blocks of CEA extension.
5731 */
5e87b2e5 5732 cea_db_iter_edid_begin(drm_edid, &iter);
4ce08703
JN		 5733 cea_db_iter_for_each(db, &iter) {
5734 if (cea_db_is_hdmi_vsdb(db)) {
5735 hdmi = true;
5736 break;
5737 }
f23c20c8 5738 }
4ce08703 5739 cea_db_iter_end(&iter);
f23c20c8 5740
4ce08703 5741 return hdmi;
f23c20c8 5742}
3176d092
JN		 5743
5744/**
5745 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
5746 * @edid: monitor EDID information
5747 *
5748 * Parse the CEA extension according to CEA-861-B.
5749 *
5750 * Drivers that have added the modes parsed from EDID to drm_display_info
5751 * should use &drm_display_info.is_hdmi instead of calling this function.
5752 *
5753 * Return: True if the monitor is HDMI, false if not or unknown.
5754 */
5755bool drm_detect_hdmi_monitor(const struct edid *edid)
5756{
5757 struct drm_edid drm_edid;
5758
5759 return _drm_detect_hdmi_monitor(drm_edid_legacy_init(&drm_edid, edid));
5760}
f23c20c8
ML		 5761EXPORT_SYMBOL(drm_detect_hdmi_monitor);
5762
0c057877 5763static bool _drm_detect_monitor_audio(const struct drm_edid *drm_edid)
8fe9790d 5764{
705bec3e 5765 struct drm_edid_iter edid_iter;
9975af04
JN		 5766 const struct cea_db *db;
5767 struct cea_db_iter iter;
43d16d84 5768 const u8 *edid_ext;
8fe9790d 5769 bool has_audio = false;
8fe9790d 5770
bbded689 5771 drm_edid_iter_begin(drm_edid, &edid_iter);
705bec3e
JN		 5772 drm_edid_iter_for_each(edid_ext, &edid_iter) {
5773 if (edid_ext[0] == CEA_EXT) {
5774 has_audio = edid_ext[3] & EDID_BASIC_AUDIO;
5775 if (has_audio)
5776 break;
5777 }
5778 }
5779 drm_edid_iter_end(&edid_iter);
8fe9790d
ZW		 5780
5781 if (has_audio) {
5782 DRM_DEBUG_KMS("Monitor has basic audio support\n");
5783 goto end;
5784 }
5785
5e87b2e5 5786 cea_db_iter_edid_begin(drm_edid, &iter);
9975af04
JN		 5787 cea_db_iter_for_each(db, &iter) {
5788 if (cea_db_tag(db) == CTA_DB_AUDIO) {
5789 const u8 *data = cea_db_data(db);
5790 int i;
8fe9790d 5791
9975af04 5792 for (i = 0; i < cea_db_payload_len(db); i += 3)
8fe9790d 5793 DRM_DEBUG_KMS("CEA audio format %d\n",
9975af04
JN		 5794 (data[i] >> 3) & 0xf);
5795 has_audio = true;
5796 break;
8fe9790d
ZW		 5797 }
5798 }
9975af04
JN		 5799 cea_db_iter_end(&iter);
5800
8fe9790d
ZW		 5801end:
5802 return has_audio;
5803}
0c057877
JN		 5804
5805/**
5806 * drm_detect_monitor_audio - check monitor audio capability
5807 * @edid: EDID block to scan
5808 *
5809 * Monitor should have CEA extension block.
5810 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
5811 * audio' only. If there is any audio extension block and supported
5812 * audio format, assume at least 'basic audio' support, even if 'basic
5813 * audio' is not defined in EDID.
5814 *
5815 * Return: True if the monitor supports audio, false otherwise.
5816 */
5817bool drm_detect_monitor_audio(const struct edid *edid)
5818{
5819 struct drm_edid drm_edid;
5820
5821 return _drm_detect_monitor_audio(drm_edid_legacy_init(&drm_edid, edid));
5822}
8fe9790d
ZW		 5823EXPORT_SYMBOL(drm_detect_monitor_audio);
5824
b1edd6a6 5825
c8127cf0
VS		 5826/**
5827 * drm_default_rgb_quant_range - default RGB quantization range
5828 * @mode: display mode
5829 *
5830 * Determine the default RGB quantization range for the mode,
5831 * as specified in CEA-861.
5832 *
5833 * Return: The default RGB quantization range for the mode
5834 */
5835enum hdmi_quantization_range
5836drm_default_rgb_quant_range(const struct drm_display_mode *mode)
5837{
5838 /* All CEA modes other than VIC 1 use limited quantization range. */
5839 return drm_match_cea_mode(mode) > 1 ?
5840 HDMI_QUANTIZATION_RANGE_LIMITED :
5841 HDMI_QUANTIZATION_RANGE_FULL;
5842}
5843EXPORT_SYMBOL(drm_default_rgb_quant_range);
5844
1581b2df
VS		 5845static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
5846{
5847 struct drm_display_info *info = &connector->display_info;
5848
5849 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]);
5850
5851 if (db[2] & EDID_CEA_VCDB_QS)
5852 info->rgb_quant_range_selectable = true;
5853}
5854
4499d488
SS		 5855static
5856void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane)
5857{
5858 switch (max_frl_rate) {
5859 case 1:
5860 *max_lanes = 3;
5861 *max_rate_per_lane = 3;
5862 break;
5863 case 2:
5864 *max_lanes = 3;
5865 *max_rate_per_lane = 6;
5866 break;
5867 case 3:
5868 *max_lanes = 4;
5869 *max_rate_per_lane = 6;
5870 break;
5871 case 4:
5872 *max_lanes = 4;
5873 *max_rate_per_lane = 8;
5874 break;
5875 case 5:
5876 *max_lanes = 4;
5877 *max_rate_per_lane = 10;
5878 break;
5879 case 6:
5880 *max_lanes = 4;
5881 *max_rate_per_lane = 12;
5882 break;
5883 case 0:
5884 default:
5885 *max_lanes = 0;
5886 *max_rate_per_lane = 0;
5887 }
5888}
5889
e6a9a2c3
SS		 5890static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
5891 const u8 *db)
5892{
5893 u8 dc_mask;
5894 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
5895
5896 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
9068e02f 5897 hdmi->y420_dc_modes = dc_mask;
e6a9a2c3
SS		 5898}
5899
5e706c4d
AN		 5900static void drm_parse_dsc_info(struct drm_hdmi_dsc_cap *hdmi_dsc,
5901 const u8 *hf_scds)
5902{
5e706c4d
AN		 5903 hdmi_dsc->v_1p2 = hf_scds[11] & DRM_EDID_DSC_1P2;
5904
5905 if (!hdmi_dsc->v_1p2)
5906 return;
5907
5908 hdmi_dsc->native_420 = hf_scds[11] & DRM_EDID_DSC_NATIVE_420;
5909 hdmi_dsc->all_bpp = hf_scds[11] & DRM_EDID_DSC_ALL_BPP;
5910
5911 if (hf_scds[11] & DRM_EDID_DSC_16BPC)
5912 hdmi_dsc->bpc_supported = 16;
5913 else if (hf_scds[11] & DRM_EDID_DSC_12BPC)
5914 hdmi_dsc->bpc_supported = 12;
5915 else if (hf_scds[11] & DRM_EDID_DSC_10BPC)
5916 hdmi_dsc->bpc_supported = 10;
5917 else
5918 /* Supports min 8 BPC if DSC 1.2 is supported*/
5919 hdmi_dsc->bpc_supported = 8;
5920
a07e6f56
AN		 5921 if (cea_db_payload_len(hf_scds) >= 12 && hf_scds[12]) {
5922 u8 dsc_max_slices;
5923 u8 dsc_max_frl_rate;
5e706c4d 5924
a07e6f56
AN		 5925 dsc_max_frl_rate = (hf_scds[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4;
5926 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes,
5927 &hdmi_dsc->max_frl_rate_per_lane);
5e706c4d 5928
a07e6f56
AN		 5929 dsc_max_slices = hf_scds[12] & DRM_EDID_DSC_MAX_SLICES;
5930
5931 switch (dsc_max_slices) {
5932 case 1:
5933 hdmi_dsc->max_slices = 1;
5934 hdmi_dsc->clk_per_slice = 340;
5935 break;
5936 case 2:
5937 hdmi_dsc->max_slices = 2;
5938 hdmi_dsc->clk_per_slice = 340;
5939 break;
5940 case 3:
5941 hdmi_dsc->max_slices = 4;
5942 hdmi_dsc->clk_per_slice = 340;
5943 break;
5944 case 4:
5945 hdmi_dsc->max_slices = 8;
5946 hdmi_dsc->clk_per_slice = 340;
5947 break;
5948 case 5:
5949 hdmi_dsc->max_slices = 8;
5950 hdmi_dsc->clk_per_slice = 400;
5951 break;
5952 case 6:
5953 hdmi_dsc->max_slices = 12;
5954 hdmi_dsc->clk_per_slice = 400;
5955 break;
5956 case 7:
5957 hdmi_dsc->max_slices = 16;
5958 hdmi_dsc->clk_per_slice = 400;
5959 break;
5960 case 0:
5961 default:
5962 hdmi_dsc->max_slices = 0;
5963 hdmi_dsc->clk_per_slice = 0;
5964 }
5e706c4d 5965 }
a07e6f56
AN		 5966
5967 if (cea_db_payload_len(hf_scds) >= 13 && hf_scds[13])
5968 hdmi_dsc->total_chunk_kbytes = hf_scds[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES;
5e706c4d
AN		 5969}
5970
d8cb49d2
JN		 5971/* Sink Capability Data Structure */
5972static void drm_parse_hdmi_forum_scds(struct drm_connector *connector,
5973 const u8 *hf_scds)
afa1c763 5974{
62c58af3
SS		 5975 struct drm_display_info *display = &connector->display_info;
5976 struct drm_hdmi_info *hdmi = &display->hdmi;
a07e6f56 5977 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap;
5e931c88
AN		 5978 int max_tmds_clock = 0;
5979 u8 max_frl_rate = 0;
5980 bool dsc_support = false;
afa1c763 5981
f1781e9b
VS		 5982 display->has_hdmi_infoframe = true;
5983
d8cb49d2 5984 if (hf_scds[6] & 0x80) {
afa1c763 5985 hdmi->scdc.supported = true;
d8cb49d2 5986 if (hf_scds[6] & 0x40)
afa1c763
SS		 5987 hdmi->scdc.read_request = true;
5988 }
62c58af3
SS		 5989
5990 /*
5991 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
5992 * And as per the spec, three factors confirm this:
5993 * * Availability of a HF-VSDB block in EDID (check)
5994 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
5995 * * SCDC support available (let's check)
5996 * Lets check it out.
5997 */
5998
d8cb49d2 5999 if (hf_scds[5]) {
62c58af3
SS		 6000 struct drm_scdc *scdc = &hdmi->scdc;
6001
5e931c88
AN		 6002 /* max clock is 5000 KHz times block value */
6003 max_tmds_clock = hf_scds[5] * 5000;
6004
62c58af3
SS		 6005 if (max_tmds_clock > 340000) {
6006 display->max_tmds_clock = max_tmds_clock;
62c58af3
SS		 6007 }
6008
6009 if (scdc->supported) {
6010 scdc->scrambling.supported = true;
6011
dbe2d2bf 6012 /* Few sinks support scrambling for clocks < 340M */
d8cb49d2 6013 if ((hf_scds[6] & 0x8))
62c58af3
SS		 6014 scdc->scrambling.low_rates = true;
6015 }
6016 }
e6a9a2c3 6017
d8cb49d2 6018 if (hf_scds[7]) {
d8cb49d2 6019 max_frl_rate = (hf_scds[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4;
4499d488
SS		 6020 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes,
6021 &hdmi->max_frl_rate_per_lane);
6022 }
6023
d8cb49d2 6024 drm_parse_ycbcr420_deep_color_info(connector, hf_scds);
a07e6f56 6025
5e931c88 6026 if (cea_db_payload_len(hf_scds) >= 11 && hf_scds[11]) {
a07e6f56 6027 drm_parse_dsc_info(hdmi_dsc, hf_scds);
5e931c88
AN		 6028 dsc_support = true;
6029 }
6030
6031 drm_dbg_kms(connector->dev,
6032 "HF-VSDB: max TMDS clock: %d KHz, HDMI 2.1 support: %s, DSC 1.2 support: %s\n",
6033 max_tmds_clock, str_yes_no(max_frl_rate), str_yes_no(dsc_support));
afa1c763
SS		 6034}
6035
1cea146a
VS		 6036static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
6037 const u8 *hdmi)
d0c94692 6038{
1826750f 6039 struct drm_display_info *info = &connector->display_info;
d0c94692
MK		 6040 unsigned int dc_bpc = 0;
6041
1cea146a
VS		 6042 /* HDMI supports at least 8 bpc */
6043 info->bpc = 8;
d0c94692 6044
1cea146a
VS		 6045 if (cea_db_payload_len(hdmi) < 6)
6046 return;
6047
6048 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
6049 dc_bpc = 10;
4adc33f3 6050 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_30;
1cea146a
VS		 6051 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
6052 connector->name);
6053 }
6054
6055 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
6056 dc_bpc = 12;
4adc33f3 6057 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_36;
1cea146a
VS		 6058 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
6059 connector->name);
6060 }
6061
6062 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
6063 dc_bpc = 16;
4adc33f3 6064 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_48;
1cea146a
VS		 6065 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
6066 connector->name);
6067 }
6068
6069 if (dc_bpc == 0) {
6070 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
6071 connector->name);
6072 return;
6073 }
6074
6075 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
6076 connector->name, dc_bpc);
6077 info->bpc = dc_bpc;
d0c94692 6078
1cea146a
VS		 6079 /* YCRCB444 is optional according to spec. */
6080 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
4adc33f3 6081 info->edid_hdmi_ycbcr444_dc_modes = info->edid_hdmi_rgb444_dc_modes;
1cea146a
VS		 6082 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
6083 connector->name);
6084 }
d0c94692 6085
1cea146a
VS		 6086 /*
6087 * Spec says that if any deep color mode is supported at all,
6088 * then deep color 36 bit must be supported.
6089 */
6090 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
6091 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
6092 connector->name);
6093 }
6094}
d0c94692 6095
23ebf8b9
VS		 6096static void
6097drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
6098{
6099 struct drm_display_info *info = &connector->display_info;
6100 u8 len = cea_db_payload_len(db);
6101
a92d083d
LP		 6102 info->is_hdmi = true;
6103
23ebf8b9
VS		 6104 if (len >= 6)
6105 info->dvi_dual = db[6] & 1;
6106 if (len >= 7)
6107 info->max_tmds_clock = db[7] * 5000;
6108
6109 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
6110 "max TMDS clock %d kHz\n",
6111 info->dvi_dual,
6112 info->max_tmds_clock);
6113
6114 drm_parse_hdmi_deep_color_info(connector, db);
6115}
6116
2869f599
PZ		 6117/*
6118 * See EDID extension for head-mounted and specialized monitors, specified at:
6119 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/specialized-monitors-edid-extension
6120 */
6121static void drm_parse_microsoft_vsdb(struct drm_connector *connector,
6122 const u8 *db)
6123{
6124 struct drm_display_info *info = &connector->display_info;
6125 u8 version = db[4];
6126 bool desktop_usage = db[5] & BIT(6);
6127
6128 /* Version 1 and 2 for HMDs, version 3 flags desktop usage explicitly */
6129 if (version == 1 || version == 2 || (version == 3 && !desktop_usage))
6130 info->non_desktop = true;
6131
6132 drm_dbg_kms(connector->dev, "HMD or specialized display VSDB version %u: 0x%02x\n",
6133 version, db[5]);
6134}
6135
1cea146a 6136static void drm_parse_cea_ext(struct drm_connector *connector,
e42192b4 6137 const struct drm_edid *drm_edid)
1cea146a
VS		 6138{
6139 struct drm_display_info *info = &connector->display_info;
8db73897 6140 struct drm_edid_iter edid_iter;
dfc03125
JN		 6141 const struct cea_db *db;
6142 struct cea_db_iter iter;
1cea146a 6143 const u8 *edid_ext;
d0c94692 6144
bbded689 6145 drm_edid_iter_begin(drm_edid, &edid_iter);
8db73897
JN		 6146 drm_edid_iter_for_each(edid_ext, &edid_iter) {
6147 if (edid_ext[0] != CEA_EXT)
6148 continue;
d0c94692 6149
8db73897
JN		 6150 if (!info->cea_rev)
6151 info->cea_rev = edid_ext[1];
d0c94692 6152
8db73897
JN		 6153 if (info->cea_rev != edid_ext[1])
6154 DRM_DEBUG_KMS("CEA extension version mismatch %u != %u\n",
6155 info->cea_rev, edid_ext[1]);
7344bad7 6156
8db73897
JN		 6157 /* The existence of a CTA extension should imply RGB support */
6158 info->color_formats = DRM_COLOR_FORMAT_RGB444;
7344bad7
JN		 6159 if (edid_ext[3] & EDID_CEA_YCRCB444)
6160 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
6161 if (edid_ext[3] & EDID_CEA_YCRCB422)
6162 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
6163 }
8db73897 6164 drm_edid_iter_end(&edid_iter);
1cea146a 6165
5e87b2e5 6166 cea_db_iter_edid_begin(drm_edid, &iter);
dfc03125
JN		 6167 cea_db_iter_for_each(db, &iter) {
6168 /* FIXME: convert parsers to use struct cea_db */
6169 const u8 *data = (const u8 *)db;
1cea146a 6170
23ebf8b9 6171 if (cea_db_is_hdmi_vsdb(db))
dfc03125 6172 drm_parse_hdmi_vsdb_video(connector, data);
be982415
JN		 6173 else if (cea_db_is_hdmi_forum_vsdb(db) ||
6174 cea_db_is_hdmi_forum_scdb(db))
dfc03125 6175 drm_parse_hdmi_forum_scds(connector, data);
be982415 6176 else if (cea_db_is_microsoft_vsdb(db))
dfc03125 6177 drm_parse_microsoft_vsdb(connector, data);
be982415 6178 else if (cea_db_is_y420cmdb(db))
dfc03125 6179 drm_parse_y420cmdb_bitmap(connector, data);
be982415 6180 else if (cea_db_is_vcdb(db))
dfc03125 6181 drm_parse_vcdb(connector, data);
be982415 6182 else if (cea_db_is_hdmi_hdr_metadata_block(db))
dfc03125 6183 drm_parse_hdr_metadata_block(connector, data);
1cea146a 6184 }
dfc03125 6185 cea_db_iter_end(&iter);
d0c94692
MK		 6186}
6187
a1d11d1e 6188static
c7943bb3 6189void get_monitor_range(const struct detailed_timing *timing, void *c)
a1d11d1e 6190{
c7943bb3
VS		 6191 struct detailed_mode_closure *closure = c;
6192 struct drm_display_info *info = &closure->connector->display_info;
6193 struct drm_monitor_range_info *monitor_range = &info->monitor_range;
a1d11d1e
MN		 6194 const struct detailed_non_pixel *data = &timing->data.other_data;
6195 const struct detailed_data_monitor_range *range = &data->data.range;
c7943bb3 6196 const struct edid *edid = closure->drm_edid->edid;
a1d11d1e 6197
e379814b 6198 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
a1d11d1e
MN		 6199 return;
6200
6201 /*
67d7469a
VS		 6202 * These limits are used to determine the VRR refresh
6203 * rate range. Only the "range limits only" variant
6204 * of the range descriptor seems to guarantee that
6205 * any and all timings are accepted by the sink, as
6206 * opposed to just timings conforming to the indicated
6207 * formula (GTF/GTF2/CVT). Thus other variants of the
6208 * range descriptor are not accepted here.
a1d11d1e
MN		 6209 */
6210 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG)
6211 return;
6212
6213 monitor_range->min_vfreq = range->min_vfreq;
6214 monitor_range->max_vfreq = range->max_vfreq;
c7943bb3
VS		 6215
6216 if (edid->revision >= 4) {
6217 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ)
6218 monitor_range->min_vfreq += 255;
6219 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MAX_VFREQ)
6220 monitor_range->max_vfreq += 255;
6221 }
a1d11d1e
MN		 6222}
6223
e42192b4
JN		 6224static void drm_get_monitor_range(struct drm_connector *connector,
6225 const struct drm_edid *drm_edid)
a1d11d1e 6226{
c7943bb3
VS		 6227 const struct drm_display_info *info = &connector->display_info;
6228 struct detailed_mode_closure closure = {
6229 .connector = connector,
6230 .drm_edid = drm_edid,
6231 };
a1d11d1e 6232
dd3abfe4 6233 if (drm_edid->edid->revision < 4)
ca2582c6
VS		 6234 return;
6235
6236 if (!(drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ))
a1d11d1e
MN		 6237 return;
6238
c7943bb3 6239 drm_for_each_detailed_block(drm_edid, get_monitor_range, &closure);
a1d11d1e
MN		 6240
6241 DRM_DEBUG_KMS("Supported Monitor Refresh rate range is %d Hz - %d Hz\n",
6242 info->monitor_range.min_vfreq,
6243 info->monitor_range.max_vfreq);
6244}
6245
18a9cbbe
JN		 6246static void drm_parse_vesa_mso_data(struct drm_connector *connector,
6247 const struct displayid_block *block)
6248{
6249 struct displayid_vesa_vendor_specific_block *vesa =
6250 (struct displayid_vesa_vendor_specific_block *)block;
6251 struct drm_display_info *info = &connector->display_info;
6252
6253 if (block->num_bytes < 3) {
6254 drm_dbg_kms(connector->dev, "Unexpected vendor block size %u\n",
6255 block->num_bytes);
6256 return;
6257 }
6258
6259 if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI)
6260 return;
6261
6262 if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
6263 drm_dbg_kms(connector->dev, "Unexpected VESA vendor block size\n");
6264 return;
6265 }
6266
6267 switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
6268 default:
6269 drm_dbg_kms(connector->dev, "Reserved MSO mode value\n");
6270 fallthrough;
6271 case 0:
6272 info->mso_stream_count = 0;
6273 break;
6274 case 1:
6275 info->mso_stream_count = 2; /* 2 or 4 links */
6276 break;
6277 case 2:
6278 info->mso_stream_count = 4; /* 4 links */
6279 break;
6280 }
6281
6282 if (!info->mso_stream_count) {
6283 info->mso_pixel_overlap = 0;
6284 return;
6285 }
6286
6287 info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
6288 if (info->mso_pixel_overlap > 8) {
6289 drm_dbg_kms(connector->dev, "Reserved MSO pixel overlap value %u\n",
6290 info->mso_pixel_overlap);
6291 info->mso_pixel_overlap = 8;
6292 }
6293
6294 drm_dbg_kms(connector->dev, "MSO stream count %u, pixel overlap %u\n",
6295 info->mso_stream_count, info->mso_pixel_overlap);
6296}
6297
e42192b4
JN		 6298static void drm_update_mso(struct drm_connector *connector,
6299 const struct drm_edid *drm_edid)
18a9cbbe
JN		 6300{
6301 const struct displayid_block *block;
6302 struct displayid_iter iter;
6303
d9ba1b4c 6304 displayid_iter_edid_begin(drm_edid, &iter);
18a9cbbe
JN		 6305 displayid_iter_for_each(block, &iter) {
6306 if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC)
6307 drm_parse_vesa_mso_data(connector, block);
6308 }
6309 displayid_iter_end(&iter);
6310}
6311
170178fe
KP		 6312/* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
6313 * all of the values which would have been set from EDID
6314 */
02b16fbc 6315static void drm_reset_display_info(struct drm_connector *connector)
170178fe
KP		 6316{
6317 struct drm_display_info *info = &connector->display_info;
6318
6319 info->width_mm = 0;
6320 info->height_mm = 0;
6321
6322 info->bpc = 0;
6323 info->color_formats = 0;
6324 info->cea_rev = 0;
6325 info->max_tmds_clock = 0;
6326 info->dvi_dual = false;
a92d083d 6327 info->is_hdmi = false;
170178fe 6328 info->has_hdmi_infoframe = false;
1581b2df 6329 info->rgb_quant_range_selectable = false;
1f6b8eef 6330 memset(&info->hdmi, 0, sizeof(info->hdmi));
170178fe 6331
70c0b80d
MR		 6332 info->edid_hdmi_rgb444_dc_modes = 0;
6333 info->edid_hdmi_ycbcr444_dc_modes = 0;
6334
170178fe 6335 info->non_desktop = 0;
a1d11d1e 6336 memset(&info->monitor_range, 0, sizeof(info->monitor_range));
82068ede 6337 memset(&info->luminance_range, 0, sizeof(info->luminance_range));
18a9cbbe
JN		 6338
6339 info->mso_stream_count = 0;
6340 info->mso_pixel_overlap = 0;
170178fe 6341}
170178fe 6342
e42192b4
JN		 6343static u32 update_display_info(struct drm_connector *connector,
6344 const struct drm_edid *drm_edid)
3b11228b 6345{
1826750f 6346 struct drm_display_info *info = &connector->display_info;
e42192b4 6347 const struct edid *edid = drm_edid->edid;
ebec9a7b 6348
e42192b4 6349 u32 quirks = edid_get_quirks(drm_edid);
170178fe 6350
1f6b8eef
VS		 6351 drm_reset_display_info(connector);
6352
3b11228b
JB		 6353 info->width_mm = edid->width_cm * 10;
6354 info->height_mm = edid->height_cm * 10;
6355
e42192b4 6356 drm_get_monitor_range(connector, drm_edid);
a1d11d1e 6357
a988bc72 6358 if (edid->revision < 3)
ce99534e 6359 goto out;
3b11228b
JB		 6360
6361 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
ce99534e 6362 goto out;
3b11228b 6363
ecbd4912 6364 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
e42192b4 6365 drm_parse_cea_ext(connector, drm_edid);
d0c94692 6366
210a021d
MK		 6367 /*
6368 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
6369 *
6370 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
6371 * tells us to assume 8 bpc color depth if the EDID doesn't have
6372 * extensions which tell otherwise.
6373 */
3bde449f
VS		 6374 if (info->bpc == 0 && edid->revision == 3 &&
6375 edid->input & DRM_EDID_DIGITAL_DFP_1_X) {
210a021d
MK		 6376 info->bpc = 8;
6377 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
6378 connector->name, info->bpc);
6379 }
6380
a988bc72
LPC		 6381 /* Only defined for 1.4 with digital displays */
6382 if (edid->revision < 4)
ce99534e 6383 goto out;
a988bc72 6384
3b11228b
JB		 6385 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
6386 case DRM_EDID_DIGITAL_DEPTH_6:
6387 info->bpc = 6;
6388 break;
6389 case DRM_EDID_DIGITAL_DEPTH_8:
6390 info->bpc = 8;
6391 break;
6392 case DRM_EDID_DIGITAL_DEPTH_10:
6393 info->bpc = 10;
6394 break;
6395 case DRM_EDID_DIGITAL_DEPTH_12:
6396 info->bpc = 12;
6397 break;
6398 case DRM_EDID_DIGITAL_DEPTH_14:
6399 info->bpc = 14;
6400 break;
6401 case DRM_EDID_DIGITAL_DEPTH_16:
6402 info->bpc = 16;
6403 break;
6404 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
6405 default:
6406 info->bpc = 0;
6407 break;
6408 }
da05a5a7 6409
d0c94692 6410 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
25933820 6411 connector->name, info->bpc);
d0c94692 6412
ee58808d 6413 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
c03d0b52 6414 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
ee58808d 6415 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
c03d0b52 6416 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
18a9cbbe 6417
e42192b4 6418 drm_update_mso(connector, drm_edid);
18a9cbbe 6419
ce99534e
JN		 6420out:
6421 if (quirks & EDID_QUIRK_NON_DESKTOP) {
6422 drm_dbg_kms(connector->dev, "Non-desktop display%s\n",
6423 info->non_desktop ? " (redundant quirk)" : "");
6424 info->non_desktop = true;
6425 }
6426
170178fe 6427 return quirks;
3b11228b
JB		 6428}
6429
a39ed680 6430static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
80ecb5d7
YB		 6431 struct displayid_detailed_timings_1 *timings,
6432 bool type_7)
a39ed680
DA		 6433{
6434 struct drm_display_mode *mode;
6435 unsigned pixel_clock = (timings->pixel_clock[0] |
6436 (timings->pixel_clock[1] << 8) |
6292b8ef 6437 (timings->pixel_clock[2] << 16)) + 1;
a39ed680
DA		 6438 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
6439 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
6440 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
6441 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
6442 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
6443 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
6444 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
6445 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
6446 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
6447 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
948de842 6448
a39ed680
DA		 6449 mode = drm_mode_create(dev);
6450 if (!mode)
6451 return NULL;
6452
80ecb5d7
YB		 6453 /* resolution is kHz for type VII, and 10 kHz for type I */
6454 mode->clock = type_7 ? pixel_clock : pixel_clock * 10;
a39ed680
DA		 6455 mode->hdisplay = hactive;
6456 mode->hsync_start = mode->hdisplay + hsync;
6457 mode->hsync_end = mode->hsync_start + hsync_width;
6458 mode->htotal = mode->hdisplay + hblank;
6459
6460 mode->vdisplay = vactive;
6461 mode->vsync_start = mode->vdisplay + vsync;
6462 mode->vsync_end = mode->vsync_start + vsync_width;
6463 mode->vtotal = mode->vdisplay + vblank;
6464
6465 mode->flags = 0;
6466 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
6467 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
6468 mode->type = DRM_MODE_TYPE_DRIVER;
6469
6470 if (timings->flags & 0x80)
6471 mode->type |= DRM_MODE_TYPE_PREFERRED;
a39ed680
DA		 6472 drm_mode_set_name(mode);
6473
6474 return mode;
6475}
6476
6477static int add_displayid_detailed_1_modes(struct drm_connector *connector,
43d16d84 6478 const struct displayid_block *block)
a39ed680
DA		 6479{
6480 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
6481 int i;
6482 int num_timings;
6483 struct drm_display_mode *newmode;
6484 int num_modes = 0;
80ecb5d7 6485 bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING;
a39ed680
DA		 6486 /* blocks must be multiple of 20 bytes length */
6487 if (block->num_bytes % 20)
6488 return 0;
6489
6490 num_timings = block->num_bytes / 20;
6491 for (i = 0; i < num_timings; i++) {
6492 struct displayid_detailed_timings_1 *timings = &det->timings[i];
6493
80ecb5d7 6494 newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7);
a39ed680
DA		 6495 if (!newmode)
6496 continue;
6497
6498 drm_mode_probed_add(connector, newmode);
6499 num_modes++;
6500 }
6501 return num_modes;
6502}
6503
6504static int add_displayid_detailed_modes(struct drm_connector *connector,
40f71f5b 6505 const struct drm_edid *drm_edid)
a39ed680 6506{
43d16d84 6507 const struct displayid_block *block;
5ef88dc5 6508 struct displayid_iter iter;
a39ed680
DA		 6509 int num_modes = 0;
6510
d9ba1b4c 6511 displayid_iter_edid_begin(drm_edid, &iter);
5ef88dc5 6512 displayid_iter_for_each(block, &iter) {
80ecb5d7
YB		 6513 if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING ||
6514 block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING)
5ef88dc5 6515 num_modes += add_displayid_detailed_1_modes(connector, block);
a39ed680 6516 }
5ef88dc5 6517 displayid_iter_end(&iter);
7f261afd 6518
a39ed680
DA		 6519 return num_modes;
6520}
6521
b71c0aaa
JN		 6522static int _drm_edid_connector_update(struct drm_connector *connector,
6523 const struct drm_edid *drm_edid)
f453ba04
DA		 6524{
6525 int num_modes = 0;
6526 u32 quirks;
6527
22a27e05 6528 if (!drm_edid) {
d10f7117 6529 drm_reset_display_info(connector);
c945b8c1 6530 clear_eld(connector);
f453ba04
DA		 6531 return 0;
6532 }
f453ba04 6533
0f0f8708
SS		 6534 /*
6535 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
6536 * To avoid multiple parsing of same block, lets parse that map
6537 * from sink info, before parsing CEA modes.
6538 */
e42192b4 6539 quirks = update_display_info(connector, drm_edid);
0f0f8708 6540
e42192b4 6541 /* Depends on info->cea_rev set by update_display_info() above */
a2f9790d 6542 drm_edid_to_eld(connector, drm_edid);
58304630 6543
c867df70
AJ		 6544 /*
6545 * EDID spec says modes should be preferred in this order:
6546 * - preferred detailed mode
6547 * - other detailed modes from base block
6548 * - detailed modes from extension blocks
6549 * - CVT 3-byte code modes
6550 * - standard timing codes
6551 * - established timing codes
6552 * - modes inferred from GTF or CVT range information
6553 *
13931579 6554 * We get this pretty much right.
c867df70
AJ		 6555 *
6556 * XXX order for additional mode types in extension blocks?
6557 */
40f71f5b
JN		 6558 num_modes += add_detailed_modes(connector, drm_edid, quirks);
6559 num_modes += add_cvt_modes(connector, drm_edid);
6560 num_modes += add_standard_modes(connector, drm_edid);
6561 num_modes += add_established_modes(connector, drm_edid);
6562 num_modes += add_cea_modes(connector, drm_edid);
6563 num_modes += add_alternate_cea_modes(connector, drm_edid);
6564 num_modes += add_displayid_detailed_modes(connector, drm_edid);
afd4429e 6565 if (drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ)
40f71f5b 6566 num_modes += add_inferred_modes(connector, drm_edid);
f453ba04
DA		 6567
6568 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
6569 edid_fixup_preferred(connector, quirks);
6570
e10aec65
MK		 6571 if (quirks & EDID_QUIRK_FORCE_6BPC)
6572 connector->display_info.bpc = 6;
6573
49d45a31
RM		 6574 if (quirks & EDID_QUIRK_FORCE_8BPC)
6575 connector->display_info.bpc = 8;
6576
e345da82
MK		 6577 if (quirks & EDID_QUIRK_FORCE_10BPC)
6578 connector->display_info.bpc = 10;
6579
bc5b9641
MK		 6580 if (quirks & EDID_QUIRK_FORCE_12BPC)
6581 connector->display_info.bpc = 12;
6582
f453ba04
DA		 6583 return num_modes;
6584}
f40ab034 6585
a819451e
JN		 6586static void _drm_update_tile_info(struct drm_connector *connector,
6587 const struct drm_edid *drm_edid);
02b16fbc 6588
b71c0aaa 6589static int _drm_edid_connector_property_update(struct drm_connector *connector,
a819451e 6590 const struct drm_edid *drm_edid)
02b16fbc
JN		 6591{
6592 struct drm_device *dev = connector->dev;
02b16fbc 6593 int ret;
02b16fbc 6594
02b16fbc 6595 if (connector->edid_blob_ptr) {
a819451e
JN		 6596 const struct edid *old_edid = connector->edid_blob_ptr->data;
6597
02b16fbc 6598 if (old_edid) {
a819451e 6599 if (!drm_edid_are_equal(drm_edid ? drm_edid->edid : NULL, old_edid)) {
f999b37e
JN		 6600 connector->epoch_counter++;
6601 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID changed, epoch counter %llu\n",
6602 connector->base.id, connector->name,
6603 connector->epoch_counter);
02b16fbc
JN		 6604 }
6605 }
6606 }
6607
02b16fbc
JN		 6608 ret = drm_property_replace_global_blob(dev,
6609 &connector->edid_blob_ptr,
a819451e
JN		 6610 drm_edid ? drm_edid->size : 0,
6611 drm_edid ? drm_edid->edid : NULL,
02b16fbc
JN		 6612 &connector->base,
6613 dev->mode_config.edid_property);
f999b37e
JN		 6614 if (ret) {
6615 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID property update failed (%d)\n",
6616 connector->base.id, connector->name, ret);
6617 goto out;
6618 }
6619
6620 ret = drm_object_property_set_value(&connector->base,
6621 dev->mode_config.non_desktop_property,
6622 connector->display_info.non_desktop);
6623 if (ret) {
6624 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Non-desktop property update failed (%d)\n",
6625 connector->base.id, connector->name, ret);
6626 goto out;
6627 }
6628
6629 ret = drm_connector_set_tile_property(connector);
6630 if (ret) {
6631 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Tile property update failed (%d)\n",
6632 connector->base.id, connector->name, ret);
6633 goto out;
6634 }
6635
6636out:
6637 return ret;
02b16fbc 6638}
a819451e 6639
b71c0aaa
JN		 6640/**
6641 * drm_edid_connector_update - Update connector information from EDID
6642 * @connector: Connector
6643 * @drm_edid: EDID
6644 *
6645 * Update the connector mode list, display info, ELD, HDR metadata, relevant
6646 * properties, etc. from the passed in EDID.
6647 *
6648 * If EDID is NULL, reset the information.
6649 *
6650 * Return: The number of modes added or 0 if we couldn't find any.
6651 */
6652int drm_edid_connector_update(struct drm_connector *connector,
6653 const struct drm_edid *drm_edid)
6654{
6655 int count;
6656
b71c0aaa
JN		 6657 count = _drm_edid_connector_update(connector, drm_edid);
6658
6659 _drm_update_tile_info(connector, drm_edid);
6660
6661 /* Note: Ignore errors for now. */
6662 _drm_edid_connector_property_update(connector, drm_edid);
6663
6664 return count;
6665}
6666EXPORT_SYMBOL(drm_edid_connector_update);
6667
6668static int _drm_connector_update_edid_property(struct drm_connector *connector,
6669 const struct drm_edid *drm_edid)
6670{
b71c0aaa
JN		 6671 /*
6672 * Set the display info, using edid if available, otherwise resetting
6673 * the values to defaults. This duplicates the work done in
6674 * drm_add_edid_modes, but that function is not consistently called
6675 * before this one in all drivers and the computation is cheap enough
6676 * that it seems better to duplicate it rather than attempt to ensure
6677 * some arbitrary ordering of calls.
6678 */
6679 if (drm_edid)
6680 update_display_info(connector, drm_edid);
6681 else
6682 drm_reset_display_info(connector);
6683
6684 _drm_update_tile_info(connector, drm_edid);
6685
6686 return _drm_edid_connector_property_update(connector, drm_edid);
6687}
6688
a819451e
JN		 6689/**
6690 * drm_connector_update_edid_property - update the edid property of a connector
6691 * @connector: drm connector
6692 * @edid: new value of the edid property
6693 *
6694 * This function creates a new blob modeset object and assigns its id to the
6695 * connector's edid property.
6696 * Since we also parse tile information from EDID's displayID block, we also
6697 * set the connector's tile property here. See drm_connector_set_tile_property()
6698 * for more details.
6699 *
b71c0aaa
JN		 6700 * This function is deprecated. Use drm_edid_connector_update() instead.
6701 *
a819451e
JN		 6702 * Returns:
6703 * Zero on success, negative errno on failure.
6704 */
6705int drm_connector_update_edid_property(struct drm_connector *connector,
6706 const struct edid *edid)
6707{
6708 struct drm_edid drm_edid;
6709
6710 return _drm_connector_update_edid_property(connector,
6711 drm_edid_legacy_init(&drm_edid, edid));
6712}
02b16fbc
JN		 6713EXPORT_SYMBOL(drm_connector_update_edid_property);
6714
f40ab034
JN		 6715/**
6716 * drm_add_edid_modes - add modes from EDID data, if available
6717 * @connector: connector we're probing
6718 * @edid: EDID data
6719 *
6720 * Add the specified modes to the connector's mode list. Also fills out the
6721 * &drm_display_info structure and ELD in @connector with any information which
6722 * can be derived from the edid.
6723 *
b71c0aaa
JN		 6724 * This function is deprecated. Use drm_edid_connector_update() instead.
6725 *
f40ab034
JN		 6726 * Return: The number of modes added or 0 if we couldn't find any.
6727 */
6728int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
6729{
22a27e05
JN		 6730 struct drm_edid drm_edid;
6731
f40ab034
JN		 6732 if (edid && !drm_edid_is_valid(edid)) {
6733 drm_warn(connector->dev, "%s: EDID invalid.\n",
6734 connector->name);
6735 edid = NULL;
6736 }
6737
b71c0aaa
JN		 6738 return _drm_edid_connector_update(connector,
6739 drm_edid_legacy_init(&drm_edid, edid));
f40ab034 6740}
f453ba04 6741EXPORT_SYMBOL(drm_add_edid_modes);
f0fda0a4
ZY		 6742
6743/**
6744 * drm_add_modes_noedid - add modes for the connectors without EDID
6745 * @connector: connector we're probing
6746 * @hdisplay: the horizontal display limit
6747 * @vdisplay: the vertical display limit
6748 *
6749 * Add the specified modes to the connector's mode list. Only when the
6750 * hdisplay/vdisplay is not beyond the given limit, it will be added.
6751 *
db6cf833 6752 * Return: The number of modes added or 0 if we couldn't find any.
f0fda0a4
ZY		 6753 */
6754int drm_add_modes_noedid(struct drm_connector *connector,
6755 int hdisplay, int vdisplay)
6756{
6757 int i, count, num_modes = 0;
b1f559ec 6758 struct drm_display_mode *mode;
f0fda0a4
ZY		 6759 struct drm_device *dev = connector->dev;
6760
fbb40b28 6761 count = ARRAY_SIZE(drm_dmt_modes);
f0fda0a4
ZY		 6762 if (hdisplay < 0)
6763 hdisplay = 0;
6764 if (vdisplay < 0)
6765 vdisplay = 0;
6766
6767 for (i = 0; i < count; i++) {
b1f559ec 6768 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
948de842 6769
f0fda0a4
ZY		 6770 if (hdisplay && vdisplay) {
6771 /*
6772 * Only when two are valid, they will be used to check
6773 * whether the mode should be added to the mode list of
6774 * the connector.
6775 */
6776 if (ptr->hdisplay > hdisplay ||
6777 ptr->vdisplay > vdisplay)
6778 continue;
6779 }
f985dedb
AJ		 6780 if (drm_mode_vrefresh(ptr) > 61)
6781 continue;
f0fda0a4
ZY		 6782 mode = drm_mode_duplicate(dev, ptr);
6783 if (mode) {
6784 drm_mode_probed_add(connector, mode);
6785 num_modes++;
6786 }
6787 }
6788 return num_modes;
6789}
6790EXPORT_SYMBOL(drm_add_modes_noedid);
10a85120 6791
db6cf833
TR		 6792/**
6793 * drm_set_preferred_mode - Sets the preferred mode of a connector
6794 * @connector: connector whose mode list should be processed
6795 * @hpref: horizontal resolution of preferred mode
6796 * @vpref: vertical resolution of preferred mode
6797 *
6798 * Marks a mode as preferred if it matches the resolution specified by @hpref
6799 * and @vpref.
6800 */
3cf70daf
GH		 6801void drm_set_preferred_mode(struct drm_connector *connector,
6802 int hpref, int vpref)
6803{
6804 struct drm_display_mode *mode;
6805
6806 list_for_each_entry(mode, &connector->probed_modes, head) {
db6cf833 6807 if (mode->hdisplay == hpref &&
9d3de138 6808 mode->vdisplay == vpref)
3cf70daf
GH		 6809 mode->type |= DRM_MODE_TYPE_PREFERRED;
6810 }
6811}
6812EXPORT_SYMBOL(drm_set_preferred_mode);
6813
192a3aa0 6814static bool is_hdmi2_sink(const struct drm_connector *connector)
13d0add3
VS		 6815{
6816 /*
6817 * FIXME: sil-sii8620 doesn't have a connector around when
6818 * we need one, so we have to be prepared for a NULL connector.
6819 */
6820 if (!connector)
6821 return true;
6822
6823 return connector->display_info.hdmi.scdc.supported ||
c03d0b52 6824 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR420;
13d0add3
VS		 6825}
6826
192a3aa0 6827static u8 drm_mode_hdmi_vic(const struct drm_connector *connector,
949561eb
VS		 6828 const struct drm_display_mode *mode)
6829{
6830 bool has_hdmi_infoframe = connector ?
6831 connector->display_info.has_hdmi_infoframe : false;
6832
6833 if (!has_hdmi_infoframe)
6834 return 0;
6835
6836 /* No HDMI VIC when signalling 3D video format */
6837 if (mode->flags & DRM_MODE_FLAG_3D_MASK)
6838 return 0;
6839
6840 return drm_match_hdmi_mode(mode);
6841}
6842
192a3aa0 6843static u8 drm_mode_cea_vic(const struct drm_connector *connector,
cfd6f8c3
VS		 6844 const struct drm_display_mode *mode)
6845{
cfd6f8c3
VS		 6846 u8 vic;
6847
6848 /*
6849 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
6850 * we should send its VIC in vendor infoframes, else send the
6851 * VIC in AVI infoframes. Lets check if this mode is present in
6852 * HDMI 1.4b 4K modes
6853 */
949561eb 6854 if (drm_mode_hdmi_vic(connector, mode))
cfd6f8c3
VS		 6855 return 0;
6856
6857 vic = drm_match_cea_mode(mode);
6858
6859 /*
6860 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
6861 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
6862 * have to make sure we dont break HDMI 1.4 sinks.
6863 */
6864 if (!is_hdmi2_sink(connector) && vic > 64)
6865 return 0;
6866
6867 return vic;
6868}
6869
10a85120
TR		 6870/**
6871 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
6872 * data from a DRM display mode
6873 * @frame: HDMI AVI infoframe
13d0add3 6874 * @connector: the connector
10a85120
TR		 6875 * @mode: DRM display mode
6876 *
db6cf833 6877 * Return: 0 on success or a negative error code on failure.
10a85120
TR		 6878 */
6879int
6880drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
192a3aa0 6881 const struct drm_connector *connector,
13d0add3 6882 const struct drm_display_mode *mode)
10a85120 6883{
a9c266c2 6884 enum hdmi_picture_aspect picture_aspect;
d2b43473 6885 u8 vic, hdmi_vic;
10a85120
TR		 6886
6887 if (!frame || !mode)
6888 return -EINVAL;
6889
5ee0caf1 6890 hdmi_avi_infoframe_init(frame);
10a85120 6891
bf02db99
DL		 6892 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
6893 frame->pixel_repeat = 1;
6894
d2b43473
WL		 6895 vic = drm_mode_cea_vic(connector, mode);
6896 hdmi_vic = drm_mode_hdmi_vic(connector, mode);
0c1f528c 6897
10a85120 6898 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
0967e6a5 6899
50525c33
SL		 6900 /*
6901 * As some drivers don't support atomic, we can't use connector state.
6902 * So just initialize the frame with default values, just the same way
6903 * as it's done with other properties here.
6904 */
6905 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
6906 frame->itc = 0;
6907
69ab6d35
VK		 6908 /*
6909 * Populate picture aspect ratio from either
d2b43473 6910 * user input (if specified) or from the CEA/HDMI mode lists.
69ab6d35 6911 */
a9c266c2 6912 picture_aspect = mode->picture_aspect_ratio;
d2b43473
WL		 6913 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) {
6914 if (vic)
6915 picture_aspect = drm_get_cea_aspect_ratio(vic);
6916 else if (hdmi_vic)
6917 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic);
6918 }
0967e6a5 6919
a9c266c2
VS		 6920 /*
6921 * The infoframe can't convey anything but none, 4:3
6922 * and 16:9, so if the user has asked for anything else
6923 * we can only satisfy it by specifying the right VIC.
6924 */
6925 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
d2b43473
WL		 6926 if (vic) {
6927 if (picture_aspect != drm_get_cea_aspect_ratio(vic))
6928 return -EINVAL;
6929 } else if (hdmi_vic) {
6930 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic))
6931 return -EINVAL;
6932 } else {
a9c266c2 6933 return -EINVAL;
d2b43473
WL		 6934 }
6935
a9c266c2
VS		 6936 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
6937 }
6938
d2b43473 6939 frame->video_code = vic;
a9c266c2 6940 frame->picture_aspect = picture_aspect;
10a85120 6941 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
24d01805 6942 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
10a85120
TR		 6943
6944 return 0;
6945}
6946EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
83dd0008 6947
a2ce26f8
VS		 6948/**
6949 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
6950 * quantization range information
6951 * @frame: HDMI AVI infoframe
13d0add3 6952 * @connector: the connector
779c4c28 6953 * @mode: DRM display mode
a2ce26f8 6954 * @rgb_quant_range: RGB quantization range (Q)
a2ce26f8
VS		 6955 */
6956void
6957drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
192a3aa0 6958 const struct drm_connector *connector,
779c4c28 6959 const struct drm_display_mode *mode,
1581b2df 6960 enum hdmi_quantization_range rgb_quant_range)
a2ce26f8 6961{
1581b2df
VS		 6962 const struct drm_display_info *info = &connector->display_info;
6963
a2ce26f8
VS		 6964 /*
6965 * CEA-861:
6966 * "A Source shall not send a non-zero Q value that does not correspond
6967 * to the default RGB Quantization Range for the transmitted Picture
6968 * unless the Sink indicates support for the Q bit in a Video
6969 * Capabilities Data Block."
779c4c28
VS		 6970 *
6971 * HDMI 2.0 recommends sending non-zero Q when it does match the
6972 * default RGB quantization range for the mode, even when QS=0.
a2ce26f8 6973 */
1581b2df 6974 if (info->rgb_quant_range_selectable ||
779c4c28 6975 rgb_quant_range == drm_default_rgb_quant_range(mode))
a2ce26f8
VS		 6976 frame->quantization_range = rgb_quant_range;
6977 else
6978 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
fcc8a22c
VS		 6979
6980 /*
6981 * CEA-861-F:
6982 * "When transmitting any RGB colorimetry, the Source should set the
6983 * YQ-field to match the RGB Quantization Range being transmitted
6984 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
6985 * set YQ=1) and the Sink shall ignore the YQ-field."
9271c0ca
VS		 6986 *
6987 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
6988 * by non-zero YQ when receiving RGB. There doesn't seem to be any
6989 * good way to tell which version of CEA-861 the sink supports, so
6990 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
96c92551 6991 * on CEA-861-F.
fcc8a22c 6992 */
13d0add3 6993 if (!is_hdmi2_sink(connector) ||
9271c0ca 6994 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
fcc8a22c
VS		 6995 frame->ycc_quantization_range =
6996 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
6997 else
6998 frame->ycc_quantization_range =
6999 HDMI_YCC_QUANTIZATION_RANGE_FULL;
a2ce26f8
VS		 7000}
7001EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
7002
4eed4a0a
DL		 7003static enum hdmi_3d_structure
7004s3d_structure_from_display_mode(const struct drm_display_mode *mode)
7005{
7006 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
7007
7008 switch (layout) {
7009 case DRM_MODE_FLAG_3D_FRAME_PACKING:
7010 return HDMI_3D_STRUCTURE_FRAME_PACKING;
7011 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
7012 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
7013 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
7014 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
7015 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
7016 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
7017 case DRM_MODE_FLAG_3D_L_DEPTH:
7018 return HDMI_3D_STRUCTURE_L_DEPTH;
7019 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
7020 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
7021 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
7022 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
7023 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
7024 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
7025 default:
7026 return HDMI_3D_STRUCTURE_INVALID;
7027 }
7028}
7029
83dd0008
LD		 7030/**
7031 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
7032 * data from a DRM display mode
7033 * @frame: HDMI vendor infoframe
f1781e9b 7034 * @connector: the connector
83dd0008
LD		 7035 * @mode: DRM display mode
7036 *
7037 * Note that there's is a need to send HDMI vendor infoframes only when using a
7038 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
7039 * function will return -EINVAL, error that can be safely ignored.
7040 *
db6cf833 7041 * Return: 0 on success or a negative error code on failure.
83dd0008
LD		 7042 */
7043int
7044drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
192a3aa0 7045 const struct drm_connector *connector,
83dd0008
LD		 7046 const struct drm_display_mode *mode)
7047{
f1781e9b
VS		 7048 /*
7049 * FIXME: sil-sii8620 doesn't have a connector around when
7050 * we need one, so we have to be prepared for a NULL connector.
7051 */
7052 bool has_hdmi_infoframe = connector ?
7053 connector->display_info.has_hdmi_infoframe : false;
83dd0008 7054 int err;
83dd0008
LD		 7055
7056 if (!frame || !mode)
7057 return -EINVAL;
7058
f1781e9b
VS		 7059 if (!has_hdmi_infoframe)
7060 return -EINVAL;
7061
949561eb
VS		 7062 err = hdmi_vendor_infoframe_init(frame);
7063 if (err < 0)
7064 return err;
4eed4a0a 7065
f1781e9b
VS		 7066 /*
7067 * Even if it's not absolutely necessary to send the infoframe
7068 * (ie.vic==0 and s3d_struct==0) we will still send it if we
7069 * know that the sink can handle it. This is based on a
7070 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
0ae865ef 7071 * have trouble realizing that they should switch from 3D to 2D
f1781e9b
VS		 7072 * mode if the source simply stops sending the infoframe when
7073 * it wants to switch from 3D to 2D.
7074 */
949561eb 7075 frame->vic = drm_mode_hdmi_vic(connector, mode);
f1781e9b 7076 frame->s3d_struct = s3d_structure_from_display_mode(mode);
83dd0008
LD		 7077
7078 return 0;
7079}
7080EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
40d9b043 7081
7f261afd
VS		 7082static void drm_parse_tiled_block(struct drm_connector *connector,
7083 const struct displayid_block *block)
5e546cd5 7084{
092c367a 7085 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
5e546cd5
DA		 7086 u16 w, h;
7087 u8 tile_v_loc, tile_h_loc;
7088 u8 num_v_tile, num_h_tile;
7089 struct drm_tile_group *tg;
7090
7091 w = tile->tile_size[0] | tile->tile_size[1] << 8;
7092 h = tile->tile_size[2] | tile->tile_size[3] << 8;
7093
7094 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
7095 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
7096 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
7097 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
7098
7099 connector->has_tile = true;
7100 if (tile->tile_cap & 0x80)
7101 connector->tile_is_single_monitor = true;
7102
7103 connector->num_h_tile = num_h_tile + 1;
7104 connector->num_v_tile = num_v_tile + 1;
7105 connector->tile_h_loc = tile_h_loc;
7106 connector->tile_v_loc = tile_v_loc;
7107 connector->tile_h_size = w + 1;
7108 connector->tile_v_size = h + 1;
7109
7110 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
7111 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
7112 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
7113 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
7114 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
7115
7116 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
392f9fcb 7117 if (!tg)
5e546cd5 7118 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
5e546cd5 7119 if (!tg)
7f261afd 7120 return;
5e546cd5
DA		 7121
7122 if (connector->tile_group != tg) {
7123 /* if we haven't got a pointer,
7124 take the reference, drop ref to old tile group */
392f9fcb 7125 if (connector->tile_group)
5e546cd5 7126 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5e546cd5 7127 connector->tile_group = tg;
392f9fcb 7128 } else {
5e546cd5
DA		 7129 /* if same tile group, then release the ref we just took. */
7130 drm_mode_put_tile_group(connector->dev, tg);
392f9fcb 7131 }
5e546cd5
DA		 7132}
7133
c7b2dee4
JN		 7134static void _drm_update_tile_info(struct drm_connector *connector,
7135 const struct drm_edid *drm_edid)
40d9b043 7136{
bfd4e192
JN		 7137 const struct displayid_block *block;
7138 struct displayid_iter iter;
36881184 7139
40d9b043 7140 connector->has_tile = false;
7f261afd 7141
d9ba1b4c 7142 displayid_iter_edid_begin(drm_edid, &iter);
bfd4e192
JN		 7143 displayid_iter_for_each(block, &iter) {
7144 if (block->tag == DATA_BLOCK_TILED_DISPLAY)
7145 drm_parse_tiled_block(connector, block);
40d9b043 7146 }
bfd4e192 7147 displayid_iter_end(&iter);
40d9b043 7148
7f261afd 7149 if (!connector->has_tile && connector->tile_group) {
40d9b043
DA		 7150 drm_mode_put_tile_group(connector->dev, connector->tile_group);
7151 connector->tile_group = NULL;
7152 }
40d9b043 7153}
Linux 6.x block layer and io_uring tree(s)