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drm/xen-front: fix pointer casts
[linux-2.6-block.git] / drivers / gpu / drm / drm_edid.c
CommitLineData
f453ba04
DA		 1/*
2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
61e57a8d 5 * Copyright 2010 Red Hat, Inc.
f453ba04
DA		 6 *
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
8 * FB layer.
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 */
30#include <linux/kernel.h>
5a0e3ad6 31#include <linux/slab.h>
10a85120 32#include <linux/hdmi.h>
f453ba04 33#include <linux/i2c.h>
47819ba2 34#include <linux/module.h>
5cb8eaa2 35#include <linux/vga_switcheroo.h>
760285e7
DH		 36#include <drm/drmP.h>
37#include <drm/drm_edid.h>
9338203c 38#include <drm/drm_encoder.h>
40d9b043 39#include <drm/drm_displayid.h>
62c58af3 40#include <drm/drm_scdc_helper.h>
f453ba04 41
969218fe
TI		 42#include "drm_crtc_internal.h"
43
13931579
AJ		 44#define version_greater(edid, maj, min) \
45 (((edid)->version > (maj)) || \
46 ((edid)->version == (maj) && (edid)->revision > (min)))
f453ba04 47
d1ff6409
AJ		 48#define EDID_EST_TIMINGS 16
49#define EDID_STD_TIMINGS 8
50#define EDID_DETAILED_TIMINGS 4
f453ba04
DA		 51
52/*
53 * EDID blocks out in the wild have a variety of bugs, try to collect
54 * them here (note that userspace may work around broken monitors first,
55 * but fixes should make their way here so that the kernel "just works"
56 * on as many displays as possible).
57 */
58
59/* First detailed mode wrong, use largest 60Hz mode */
60#define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
61/* Reported 135MHz pixel clock is too high, needs adjustment */
62#define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
63/* Prefer the largest mode at 75 Hz */
64#define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
65/* Detail timing is in cm not mm */
66#define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
67/* Detailed timing descriptors have bogus size values, so just take the
68 * maximum size and use that.
69 */
70#define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
71/* Monitor forgot to set the first detailed is preferred bit. */
72#define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5)
73/* use +hsync +vsync for detailed mode */
74#define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
bc42aabc
AJ		 75/* Force reduced-blanking timings for detailed modes */
76#define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
49d45a31
RM		 77/* Force 8bpc */
78#define EDID_QUIRK_FORCE_8BPC (1 << 8)
bc5b9641
MK		 79/* Force 12bpc */
80#define EDID_QUIRK_FORCE_12BPC (1 << 9)
e10aec65
MK		 81/* Force 6bpc */
82#define EDID_QUIRK_FORCE_6BPC (1 << 10)
e345da82
MK		 83/* Force 10bpc */
84#define EDID_QUIRK_FORCE_10BPC (1 << 11)
66660d4c
DA		 85/* Non desktop display (i.e. HMD) */
86#define EDID_QUIRK_NON_DESKTOP (1 << 12)
3c537889 87
13931579
AJ		 88struct detailed_mode_closure {
89 struct drm_connector *connector;
90 struct edid *edid;
91 bool preferred;
92 u32 quirks;
93 int modes;
94};
f453ba04 95
5c61259e
ZY		 96#define LEVEL_DMT 0
97#define LEVEL_GTF 1
7a374350
AJ		 98#define LEVEL_GTF2 2
99#define LEVEL_CVT 3
5c61259e 100
23c4cfbd 101static const struct edid_quirk {
c51a3fd6 102 char vendor[4];
f453ba04
DA		 103 int product_id;
104 u32 quirks;
105} edid_quirk_list[] = {
106 /* Acer AL1706 */
107 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
108 /* Acer F51 */
109 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
110 /* Unknown Acer */
111 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
112
e10aec65
MK		 113 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
114 { "AEO", 0, EDID_QUIRK_FORCE_6BPC },
115
06998a75
KHF		 116 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
117 { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC },
118
f453ba04
DA		 119 /* Belinea 10 15 55 */
120 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
121 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
122
123 /* Envision Peripherals, Inc. EN-7100e */
124 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
ba1163de
AJ		 125 /* Envision EN2028 */
126 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
f453ba04
DA		 127
128 /* Funai Electronics PM36B */
129 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
130 EDID_QUIRK_DETAILED_IN_CM },
131
e345da82
MK		 132 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
133 { "LGD", 764, EDID_QUIRK_FORCE_10BPC },
134
f453ba04
DA		 135 /* LG Philips LCD LP154W01-A5 */
136 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
137 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
138
139 /* Philips 107p5 CRT */
140 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
141
142 /* Proview AY765C */
143 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
144
145 /* Samsung SyncMaster 205BW. Note: irony */
146 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
147 /* Samsung SyncMaster 22[5-6]BW */
148 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
149 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
bc42aabc 150
bc5b9641
MK		 151 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
152 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
153
bc42aabc
AJ		 154 /* ViewSonic VA2026w */
155 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
118bdbd8
AD		 156
157 /* Medion MD 30217 PG */
158 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
49d45a31
RM		 159
160 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
161 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
36fc5797
TV		 162
163 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
164 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC },
acb1d8ee
DA		 165
166 /* HTC Vive VR Headset */
167 { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP },
b3b12ea3
PZ		 168
169 /* Oculus Rift DK1, DK2, and CV1 VR Headsets */
170 { "OVR", 0x0001, EDID_QUIRK_NON_DESKTOP },
171 { "OVR", 0x0003, EDID_QUIRK_NON_DESKTOP },
172 { "OVR", 0x0004, EDID_QUIRK_NON_DESKTOP },
90eda8fc
PZ		 173
174 /* Windows Mixed Reality Headsets */
175 { "ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP },
176 { "HPN", 0x3515, EDID_QUIRK_NON_DESKTOP },
177 { "LEN", 0x0408, EDID_QUIRK_NON_DESKTOP },
178 { "LEN", 0xb800, EDID_QUIRK_NON_DESKTOP },
179 { "FUJ", 0x1970, EDID_QUIRK_NON_DESKTOP },
180 { "DEL", 0x7fce, EDID_QUIRK_NON_DESKTOP },
181 { "SEC", 0x144a, EDID_QUIRK_NON_DESKTOP },
182 { "AUS", 0xc102, EDID_QUIRK_NON_DESKTOP },
ccffc9eb
PZ		 183
184 /* Sony PlayStation VR Headset */
185 { "SNY", 0x0704, EDID_QUIRK_NON_DESKTOP },
f453ba04
DA		 186};
187
a6b21831
TR		 188/*
189 * Autogenerated from the DMT spec.
190 * This table is copied from xfree86/modes/xf86EdidModes.c.
191 */
192static const struct drm_display_mode drm_dmt_modes[] = {
24b856b1 193 /* 0x01 - 640x350@85Hz */
a6b21831
TR		 194 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
195 736, 832, 0, 350, 382, 385, 445, 0,
196 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 197 /* 0x02 - 640x400@85Hz */
a6b21831
TR		 198 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
199 736, 832, 0, 400, 401, 404, 445, 0,
200 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 201 /* 0x03 - 720x400@85Hz */
a6b21831
TR		 202 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
203 828, 936, 0, 400, 401, 404, 446, 0,
204 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 205 /* 0x04 - 640x480@60Hz */
a6b21831 206 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
fcf22d05 207 752, 800, 0, 480, 490, 492, 525, 0,
a6b21831 208 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 209 /* 0x05 - 640x480@72Hz */
a6b21831
TR		 210 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
211 704, 832, 0, 480, 489, 492, 520, 0,
212 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 213 /* 0x06 - 640x480@75Hz */
a6b21831
TR		 214 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
215 720, 840, 0, 480, 481, 484, 500, 0,
216 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 217 /* 0x07 - 640x480@85Hz */
a6b21831
TR		 218 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
219 752, 832, 0, 480, 481, 484, 509, 0,
220 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 221 /* 0x08 - 800x600@56Hz */
a6b21831
TR		 222 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
223 896, 1024, 0, 600, 601, 603, 625, 0,
224 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 225 /* 0x09 - 800x600@60Hz */
a6b21831
TR		 226 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
227 968, 1056, 0, 600, 601, 605, 628, 0,
228 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 229 /* 0x0a - 800x600@72Hz */
a6b21831
TR		 230 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
231 976, 1040, 0, 600, 637, 643, 666, 0,
232 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 233 /* 0x0b - 800x600@75Hz */
a6b21831
TR		 234 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
235 896, 1056, 0, 600, 601, 604, 625, 0,
236 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 237 /* 0x0c - 800x600@85Hz */
a6b21831
TR		 238 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
239 896, 1048, 0, 600, 601, 604, 631, 0,
240 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 241 /* 0x0d - 800x600@120Hz RB */
a6b21831
TR		 242 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
243 880, 960, 0, 600, 603, 607, 636, 0,
244 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 245 /* 0x0e - 848x480@60Hz */
a6b21831
TR		 246 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
247 976, 1088, 0, 480, 486, 494, 517, 0,
248 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 249 /* 0x0f - 1024x768@43Hz, interlace */
a6b21831 250 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
735b100f 251 1208, 1264, 0, 768, 768, 776, 817, 0,
a6b21831 252 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
fcf22d05 253 DRM_MODE_FLAG_INTERLACE) },
24b856b1 254 /* 0x10 - 1024x768@60Hz */
a6b21831
TR		 255 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
256 1184, 1344, 0, 768, 771, 777, 806, 0,
257 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 258 /* 0x11 - 1024x768@70Hz */
a6b21831
TR		 259 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
260 1184, 1328, 0, 768, 771, 777, 806, 0,
261 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 262 /* 0x12 - 1024x768@75Hz */
a6b21831
TR		 263 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
264 1136, 1312, 0, 768, 769, 772, 800, 0,
265 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 266 /* 0x13 - 1024x768@85Hz */
a6b21831
TR		 267 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
268 1168, 1376, 0, 768, 769, 772, 808, 0,
269 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 270 /* 0x14 - 1024x768@120Hz RB */
a6b21831
TR		 271 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
272 1104, 1184, 0, 768, 771, 775, 813, 0,
273 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 274 /* 0x15 - 1152x864@75Hz */
a6b21831
TR		 275 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
276 1344, 1600, 0, 864, 865, 868, 900, 0,
277 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
bfcd74d2
VS		 278 /* 0x55 - 1280x720@60Hz */
279 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
280 1430, 1650, 0, 720, 725, 730, 750, 0,
281 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 282 /* 0x16 - 1280x768@60Hz RB */
a6b21831
TR		 283 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
284 1360, 1440, 0, 768, 771, 778, 790, 0,
285 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 286 /* 0x17 - 1280x768@60Hz */
a6b21831
TR		 287 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
288 1472, 1664, 0, 768, 771, 778, 798, 0,
289 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 290 /* 0x18 - 1280x768@75Hz */
a6b21831
TR		 291 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
292 1488, 1696, 0, 768, 771, 778, 805, 0,
fcf22d05 293 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 294 /* 0x19 - 1280x768@85Hz */
a6b21831
TR		 295 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
296 1496, 1712, 0, 768, 771, 778, 809, 0,
297 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 298 /* 0x1a - 1280x768@120Hz RB */
a6b21831
TR		 299 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
300 1360, 1440, 0, 768, 771, 778, 813, 0,
301 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 302 /* 0x1b - 1280x800@60Hz RB */
a6b21831
TR		 303 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
304 1360, 1440, 0, 800, 803, 809, 823, 0,
305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 306 /* 0x1c - 1280x800@60Hz */
a6b21831
TR		 307 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
308 1480, 1680, 0, 800, 803, 809, 831, 0,
fcf22d05 309 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 310 /* 0x1d - 1280x800@75Hz */
a6b21831
TR		 311 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
312 1488, 1696, 0, 800, 803, 809, 838, 0,
313 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 314 /* 0x1e - 1280x800@85Hz */
a6b21831
TR		 315 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
316 1496, 1712, 0, 800, 803, 809, 843, 0,
317 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 318 /* 0x1f - 1280x800@120Hz RB */
a6b21831
TR		 319 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
320 1360, 1440, 0, 800, 803, 809, 847, 0,
321 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 322 /* 0x20 - 1280x960@60Hz */
a6b21831
TR		 323 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
324 1488, 1800, 0, 960, 961, 964, 1000, 0,
325 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 326 /* 0x21 - 1280x960@85Hz */
a6b21831
TR		 327 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
328 1504, 1728, 0, 960, 961, 964, 1011, 0,
329 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 330 /* 0x22 - 1280x960@120Hz RB */
a6b21831
TR		 331 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
332 1360, 1440, 0, 960, 963, 967, 1017, 0,
333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 334 /* 0x23 - 1280x1024@60Hz */
a6b21831
TR		 335 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
336 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
337 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 338 /* 0x24 - 1280x1024@75Hz */
a6b21831
TR		 339 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
340 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
341 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 342 /* 0x25 - 1280x1024@85Hz */
a6b21831
TR		 343 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
344 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
345 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 346 /* 0x26 - 1280x1024@120Hz RB */
a6b21831
TR		 347 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
348 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
349 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 350 /* 0x27 - 1360x768@60Hz */
a6b21831
TR		 351 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
352 1536, 1792, 0, 768, 771, 777, 795, 0,
353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 354 /* 0x28 - 1360x768@120Hz RB */
a6b21831
TR		 355 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
356 1440, 1520, 0, 768, 771, 776, 813, 0,
357 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 358 /* 0x51 - 1366x768@60Hz */
359 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
360 1579, 1792, 0, 768, 771, 774, 798, 0,
361 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
362 /* 0x56 - 1366x768@60Hz */
363 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
364 1436, 1500, 0, 768, 769, 772, 800, 0,
365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 366 /* 0x29 - 1400x1050@60Hz RB */
a6b21831
TR		 367 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
368 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 370 /* 0x2a - 1400x1050@60Hz */
a6b21831
TR		 371 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
372 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
373 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 374 /* 0x2b - 1400x1050@75Hz */
a6b21831
TR		 375 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
376 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
377 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 378 /* 0x2c - 1400x1050@85Hz */
a6b21831
TR		 379 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
380 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
381 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 382 /* 0x2d - 1400x1050@120Hz RB */
a6b21831
TR		 383 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
384 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 386 /* 0x2e - 1440x900@60Hz RB */
a6b21831
TR		 387 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
388 1520, 1600, 0, 900, 903, 909, 926, 0,
389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 390 /* 0x2f - 1440x900@60Hz */
a6b21831
TR		 391 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
392 1672, 1904, 0, 900, 903, 909, 934, 0,
393 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 394 /* 0x30 - 1440x900@75Hz */
a6b21831
TR		 395 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
396 1688, 1936, 0, 900, 903, 909, 942, 0,
397 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 398 /* 0x31 - 1440x900@85Hz */
a6b21831
TR		 399 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
400 1696, 1952, 0, 900, 903, 909, 948, 0,
401 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 402 /* 0x32 - 1440x900@120Hz RB */
a6b21831
TR		 403 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
404 1520, 1600, 0, 900, 903, 909, 953, 0,
405 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 406 /* 0x53 - 1600x900@60Hz */
407 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
408 1704, 1800, 0, 900, 901, 904, 1000, 0,
409 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 410 /* 0x33 - 1600x1200@60Hz */
a6b21831
TR		 411 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
412 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
413 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 414 /* 0x34 - 1600x1200@65Hz */
a6b21831
TR		 415 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
416 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
417 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 418 /* 0x35 - 1600x1200@70Hz */
a6b21831
TR		 419 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
420 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
421 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 422 /* 0x36 - 1600x1200@75Hz */
a6b21831
TR		 423 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
424 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
425 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 426 /* 0x37 - 1600x1200@85Hz */
a6b21831
TR		 427 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
428 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
429 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 430 /* 0x38 - 1600x1200@120Hz RB */
a6b21831
TR		 431 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
432 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
433 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 434 /* 0x39 - 1680x1050@60Hz RB */
a6b21831
TR		 435 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
436 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
437 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 438 /* 0x3a - 1680x1050@60Hz */
a6b21831
TR		 439 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
440 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
441 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 442 /* 0x3b - 1680x1050@75Hz */
a6b21831
TR		 443 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
444 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
445 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 446 /* 0x3c - 1680x1050@85Hz */
a6b21831
TR		 447 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
448 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
449 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 450 /* 0x3d - 1680x1050@120Hz RB */
a6b21831
TR		 451 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
452 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 454 /* 0x3e - 1792x1344@60Hz */
a6b21831
TR		 455 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
456 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
457 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 458 /* 0x3f - 1792x1344@75Hz */
a6b21831
TR		 459 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
460 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
461 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 462 /* 0x40 - 1792x1344@120Hz RB */
a6b21831
TR		 463 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
464 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 466 /* 0x41 - 1856x1392@60Hz */
a6b21831
TR		 467 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
468 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
469 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 470 /* 0x42 - 1856x1392@75Hz */
a6b21831 471 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
fcf22d05 472 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
a6b21831 473 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 474 /* 0x43 - 1856x1392@120Hz RB */
a6b21831
TR		 475 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
476 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
477 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 478 /* 0x52 - 1920x1080@60Hz */
479 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
480 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
481 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 482 /* 0x44 - 1920x1200@60Hz RB */
a6b21831
TR		 483 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
484 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
485 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 486 /* 0x45 - 1920x1200@60Hz */
a6b21831
TR		 487 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
488 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
489 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 490 /* 0x46 - 1920x1200@75Hz */
a6b21831
TR		 491 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
492 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
493 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 494 /* 0x47 - 1920x1200@85Hz */
a6b21831
TR		 495 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
496 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
497 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 498 /* 0x48 - 1920x1200@120Hz RB */
a6b21831
TR		 499 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
500 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
501 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 502 /* 0x49 - 1920x1440@60Hz */
a6b21831
TR		 503 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
504 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
505 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 506 /* 0x4a - 1920x1440@75Hz */
a6b21831
TR		 507 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
508 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
509 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 510 /* 0x4b - 1920x1440@120Hz RB */
a6b21831
TR		 511 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
512 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
513 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 514 /* 0x54 - 2048x1152@60Hz */
515 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
516 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
517 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 518 /* 0x4c - 2560x1600@60Hz RB */
a6b21831
TR		 519 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
520 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
521 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 522 /* 0x4d - 2560x1600@60Hz */
a6b21831
TR		 523 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
524 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
525 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 526 /* 0x4e - 2560x1600@75Hz */
a6b21831
TR		 527 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
528 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
529 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 530 /* 0x4f - 2560x1600@85Hz */
a6b21831
TR		 531 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
532 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
533 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 534 /* 0x50 - 2560x1600@120Hz RB */
a6b21831
TR		 535 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
536 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
537 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 538 /* 0x57 - 4096x2160@60Hz RB */
539 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
540 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
541 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
542 /* 0x58 - 4096x2160@59.94Hz RB */
543 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
544 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
545 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
a6b21831
TR		 546};
547
e7bfa5c4
VS		 548/*
549 * These more or less come from the DMT spec. The 720x400 modes are
550 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
551 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
552 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
553 * mode.
554 *
555 * The DMT modes have been fact-checked; the rest are mild guesses.
556 */
a6b21831
TR		 557static const struct drm_display_mode edid_est_modes[] = {
558 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
559 968, 1056, 0, 600, 601, 605, 628, 0,
560 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
561 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
562 896, 1024, 0, 600, 601, 603, 625, 0,
563 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
564 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
565 720, 840, 0, 480, 481, 484, 500, 0,
566 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
567 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
87707cfd 568 704, 832, 0, 480, 489, 492, 520, 0,
a6b21831
TR		 569 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
570 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
571 768, 864, 0, 480, 483, 486, 525, 0,
572 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
87707cfd 573 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
a6b21831
TR		 574 752, 800, 0, 480, 490, 492, 525, 0,
575 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
576 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
577 846, 900, 0, 400, 421, 423, 449, 0,
578 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
579 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
580 846, 900, 0, 400, 412, 414, 449, 0,
581 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
582 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
583 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
584 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
87707cfd 585 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
a6b21831
TR		 586 1136, 1312, 0, 768, 769, 772, 800, 0,
587 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
588 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
589 1184, 1328, 0, 768, 771, 777, 806, 0,
590 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
591 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
592 1184, 1344, 0, 768, 771, 777, 806, 0,
593 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
594 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
595 1208, 1264, 0, 768, 768, 776, 817, 0,
596 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
597 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
598 928, 1152, 0, 624, 625, 628, 667, 0,
599 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
600 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
601 896, 1056, 0, 600, 601, 604, 625, 0,
602 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
603 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
604 976, 1040, 0, 600, 637, 643, 666, 0,
605 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
606 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
607 1344, 1600, 0, 864, 865, 868, 900, 0,
608 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
609};
610
611struct minimode {
612 short w;
613 short h;
614 short r;
615 short rb;
616};
617
618static const struct minimode est3_modes[] = {
619 /* byte 6 */
620 { 640, 350, 85, 0 },
621 { 640, 400, 85, 0 },
622 { 720, 400, 85, 0 },
623 { 640, 480, 85, 0 },
624 { 848, 480, 60, 0 },
625 { 800, 600, 85, 0 },
626 { 1024, 768, 85, 0 },
627 { 1152, 864, 75, 0 },
628 /* byte 7 */
629 { 1280, 768, 60, 1 },
630 { 1280, 768, 60, 0 },
631 { 1280, 768, 75, 0 },
632 { 1280, 768, 85, 0 },
633 { 1280, 960, 60, 0 },
634 { 1280, 960, 85, 0 },
635 { 1280, 1024, 60, 0 },
636 { 1280, 1024, 85, 0 },
637 /* byte 8 */
638 { 1360, 768, 60, 0 },
639 { 1440, 900, 60, 1 },
640 { 1440, 900, 60, 0 },
641 { 1440, 900, 75, 0 },
642 { 1440, 900, 85, 0 },
643 { 1400, 1050, 60, 1 },
644 { 1400, 1050, 60, 0 },
645 { 1400, 1050, 75, 0 },
646 /* byte 9 */
647 { 1400, 1050, 85, 0 },
648 { 1680, 1050, 60, 1 },
649 { 1680, 1050, 60, 0 },
650 { 1680, 1050, 75, 0 },
651 { 1680, 1050, 85, 0 },
652 { 1600, 1200, 60, 0 },
653 { 1600, 1200, 65, 0 },
654 { 1600, 1200, 70, 0 },
655 /* byte 10 */
656 { 1600, 1200, 75, 0 },
657 { 1600, 1200, 85, 0 },
658 { 1792, 1344, 60, 0 },
c068b32a 659 { 1792, 1344, 75, 0 },
a6b21831
TR		 660 { 1856, 1392, 60, 0 },
661 { 1856, 1392, 75, 0 },
662 { 1920, 1200, 60, 1 },
663 { 1920, 1200, 60, 0 },
664 /* byte 11 */
665 { 1920, 1200, 75, 0 },
666 { 1920, 1200, 85, 0 },
667 { 1920, 1440, 60, 0 },
668 { 1920, 1440, 75, 0 },
669};
670
671static const struct minimode extra_modes[] = {
672 { 1024, 576, 60, 0 },
673 { 1366, 768, 60, 0 },
674 { 1600, 900, 60, 0 },
675 { 1680, 945, 60, 0 },
676 { 1920, 1080, 60, 0 },
677 { 2048, 1152, 60, 0 },
678 { 2048, 1536, 60, 0 },
679};
680
681/*
682 * Probably taken from CEA-861 spec.
683 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c.
d9278b4c
JN		 684 *
685 * Index using the VIC.
a6b21831
TR		 686 */
687static const struct drm_display_mode edid_cea_modes[] = {
d9278b4c
JN		 688 /* 0 - dummy, VICs start at 1 */
689 { },
a6b21831
TR		 690 /* 1 - 640x480@60Hz */
691 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
692 752, 800, 0, 480, 490, 492, 525, 0,
ee7925bb 693 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 694 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 695 /* 2 - 720x480@60Hz */
696 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
697 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 698 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 699 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 700 /* 3 - 720x480@60Hz */
701 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
702 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 703 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 704 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 705 /* 4 - 1280x720@60Hz */
706 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
707 1430, 1650, 0, 720, 725, 730, 750, 0,
ee7925bb 708 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 709 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 710 /* 5 - 1920x1080i@60Hz */
711 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
712 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
713 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
ee7925bb 714 DRM_MODE_FLAG_INTERLACE),
985e5dc2 715 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
fb01d280
CT		 716 /* 6 - 720(1440)x480i@60Hz */
717 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
718 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 719 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 720 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 721 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
fb01d280
CT		 722 /* 7 - 720(1440)x480i@60Hz */
723 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
724 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 725 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 726 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 727 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
fb01d280
CT		 728 /* 8 - 720(1440)x240@60Hz */
729 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
730 801, 858, 0, 240, 244, 247, 262, 0,
a6b21831 731 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 732 DRM_MODE_FLAG_DBLCLK),
985e5dc2 733 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
fb01d280
CT		 734 /* 9 - 720(1440)x240@60Hz */
735 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
736 801, 858, 0, 240, 244, 247, 262, 0,
a6b21831 737 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 738 DRM_MODE_FLAG_DBLCLK),
985e5dc2 739 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 740 /* 10 - 2880x480i@60Hz */
741 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
742 3204, 3432, 0, 480, 488, 494, 525, 0,
743 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 744 DRM_MODE_FLAG_INTERLACE),
985e5dc2 745 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 746 /* 11 - 2880x480i@60Hz */
747 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
748 3204, 3432, 0, 480, 488, 494, 525, 0,
749 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 750 DRM_MODE_FLAG_INTERLACE),
985e5dc2 751 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 752 /* 12 - 2880x240@60Hz */
753 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
754 3204, 3432, 0, 240, 244, 247, 262, 0,
ee7925bb 755 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 756 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 757 /* 13 - 2880x240@60Hz */
758 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
759 3204, 3432, 0, 240, 244, 247, 262, 0,
ee7925bb 760 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 761 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 762 /* 14 - 1440x480@60Hz */
763 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
764 1596, 1716, 0, 480, 489, 495, 525, 0,
ee7925bb 765 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 766 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 767 /* 15 - 1440x480@60Hz */
768 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
769 1596, 1716, 0, 480, 489, 495, 525, 0,
ee7925bb 770 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 771 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 772 /* 16 - 1920x1080@60Hz */
773 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
774 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 775 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 776 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 777 /* 17 - 720x576@50Hz */
778 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
779 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 780 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 781 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 782 /* 18 - 720x576@50Hz */
783 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
784 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 785 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 786 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 787 /* 19 - 1280x720@50Hz */
788 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
789 1760, 1980, 0, 720, 725, 730, 750, 0,
ee7925bb 790 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 791 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 792 /* 20 - 1920x1080i@50Hz */
793 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
794 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
795 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
ee7925bb 796 DRM_MODE_FLAG_INTERLACE),
985e5dc2 797 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
fb01d280
CT		 798 /* 21 - 720(1440)x576i@50Hz */
799 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
800 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 801 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 802 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 803 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
fb01d280
CT		 804 /* 22 - 720(1440)x576i@50Hz */
805 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
806 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 807 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 808 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 809 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
fb01d280
CT		 810 /* 23 - 720(1440)x288@50Hz */
811 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
812 795, 864, 0, 288, 290, 293, 312, 0,
a6b21831 813 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 814 DRM_MODE_FLAG_DBLCLK),
985e5dc2 815 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
fb01d280
CT		 816 /* 24 - 720(1440)x288@50Hz */
817 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
818 795, 864, 0, 288, 290, 293, 312, 0,
a6b21831 819 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 820 DRM_MODE_FLAG_DBLCLK),
985e5dc2 821 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 822 /* 25 - 2880x576i@50Hz */
823 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
824 3180, 3456, 0, 576, 580, 586, 625, 0,
825 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 826 DRM_MODE_FLAG_INTERLACE),
985e5dc2 827 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 828 /* 26 - 2880x576i@50Hz */
829 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
830 3180, 3456, 0, 576, 580, 586, 625, 0,
831 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 832 DRM_MODE_FLAG_INTERLACE),
985e5dc2 833 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 834 /* 27 - 2880x288@50Hz */
835 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
836 3180, 3456, 0, 288, 290, 293, 312, 0,
ee7925bb 837 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 838 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 839 /* 28 - 2880x288@50Hz */
840 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
841 3180, 3456, 0, 288, 290, 293, 312, 0,
ee7925bb 842 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 843 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 844 /* 29 - 1440x576@50Hz */
845 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
846 1592, 1728, 0, 576, 581, 586, 625, 0,
ee7925bb 847 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 848 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 849 /* 30 - 1440x576@50Hz */
850 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
851 1592, 1728, 0, 576, 581, 586, 625, 0,
ee7925bb 852 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 853 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 854 /* 31 - 1920x1080@50Hz */
855 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
856 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 857 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 858 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 859 /* 32 - 1920x1080@24Hz */
860 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
861 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 862 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 863 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 864 /* 33 - 1920x1080@25Hz */
865 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
866 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 867 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 868 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 869 /* 34 - 1920x1080@30Hz */
870 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
871 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 872 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 873 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 874 /* 35 - 2880x480@60Hz */
875 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
876 3192, 3432, 0, 480, 489, 495, 525, 0,
ee7925bb 877 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 878 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 879 /* 36 - 2880x480@60Hz */
880 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
881 3192, 3432, 0, 480, 489, 495, 525, 0,
ee7925bb 882 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 883 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 884 /* 37 - 2880x576@50Hz */
885 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
886 3184, 3456, 0, 576, 581, 586, 625, 0,
ee7925bb 887 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 888 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 889 /* 38 - 2880x576@50Hz */
890 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
891 3184, 3456, 0, 576, 581, 586, 625, 0,
ee7925bb 892 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 893 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 894 /* 39 - 1920x1080i@50Hz */
895 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
896 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
897 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 898 DRM_MODE_FLAG_INTERLACE),
985e5dc2 899 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 900 /* 40 - 1920x1080i@100Hz */
901 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
902 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
903 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
ee7925bb 904 DRM_MODE_FLAG_INTERLACE),
985e5dc2 905 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 906 /* 41 - 1280x720@100Hz */
907 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
908 1760, 1980, 0, 720, 725, 730, 750, 0,
ee7925bb 909 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 910 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 911 /* 42 - 720x576@100Hz */
912 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
913 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 914 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 915 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 916 /* 43 - 720x576@100Hz */
917 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
918 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 919 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 920 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
fb01d280
CT		 921 /* 44 - 720(1440)x576i@100Hz */
922 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
923 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 924 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
5a11f7f8 925 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 926 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
fb01d280
CT		 927 /* 45 - 720(1440)x576i@100Hz */
928 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
929 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 930 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
5a11f7f8 931 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 932 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 933 /* 46 - 1920x1080i@120Hz */
934 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
935 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
936 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
ee7925bb 937 DRM_MODE_FLAG_INTERLACE),
985e5dc2 938 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 939 /* 47 - 1280x720@120Hz */
940 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
941 1430, 1650, 0, 720, 725, 730, 750, 0,
ee7925bb 942 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 943 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 944 /* 48 - 720x480@120Hz */
945 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
946 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 947 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 948 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 949 /* 49 - 720x480@120Hz */
950 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
951 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 952 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 953 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
fb01d280
CT		 954 /* 50 - 720(1440)x480i@120Hz */
955 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
956 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 957 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 958 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 959 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
fb01d280
CT		 960 /* 51 - 720(1440)x480i@120Hz */
961 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
962 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 963 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 964 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 965 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 966 /* 52 - 720x576@200Hz */
967 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
968 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 969 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 970 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 971 /* 53 - 720x576@200Hz */
972 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
973 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 974 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 975 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
fb01d280
CT		 976 /* 54 - 720(1440)x576i@200Hz */
977 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
978 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 979 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 980 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 981 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
fb01d280
CT		 982 /* 55 - 720(1440)x576i@200Hz */
983 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
984 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 985 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 986 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 987 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 988 /* 56 - 720x480@240Hz */
989 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
990 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 991 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 992 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 993 /* 57 - 720x480@240Hz */
994 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
995 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 996 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 997 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
e587803c 998 /* 58 - 720(1440)x480i@240Hz */
fb01d280
CT		 999 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1000 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 1001 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 1002 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 1003 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
e587803c 1004 /* 59 - 720(1440)x480i@240Hz */
fb01d280
CT		 1005 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1006 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 1007 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 1008 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 1009 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 1010 /* 60 - 1280x720@24Hz */
1011 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1012 3080, 3300, 0, 720, 725, 730, 750, 0,
ee7925bb 1013 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 1014 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 1015 /* 61 - 1280x720@25Hz */
1016 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1017 3740, 3960, 0, 720, 725, 730, 750, 0,
ee7925bb 1018 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 1019 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 1020 /* 62 - 1280x720@30Hz */
1021 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1022 3080, 3300, 0, 720, 725, 730, 750, 0,
ee7925bb 1023 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 1024 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 1025 /* 63 - 1920x1080@120Hz */
1026 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1027 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 1028 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 1029 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 1030 /* 64 - 1920x1080@100Hz */
1031 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
8f0e4907 1032 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 1033 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 1034 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
8ec6e075
SS		 1035 /* 65 - 1280x720@24Hz */
1036 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1037 3080, 3300, 0, 720, 725, 730, 750, 0,
1038 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1039 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1040 /* 66 - 1280x720@25Hz */
1041 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1042 3740, 3960, 0, 720, 725, 730, 750, 0,
1043 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1044 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1045 /* 67 - 1280x720@30Hz */
1046 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1047 3080, 3300, 0, 720, 725, 730, 750, 0,
1048 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1049 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1050 /* 68 - 1280x720@50Hz */
1051 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1052 1760, 1980, 0, 720, 725, 730, 750, 0,
1053 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1054 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1055 /* 69 - 1280x720@60Hz */
1056 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1057 1430, 1650, 0, 720, 725, 730, 750, 0,
1058 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1059 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1060 /* 70 - 1280x720@100Hz */
1061 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1062 1760, 1980, 0, 720, 725, 730, 750, 0,
1063 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1064 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1065 /* 71 - 1280x720@120Hz */
1066 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1067 1430, 1650, 0, 720, 725, 730, 750, 0,
1068 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1069 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1070 /* 72 - 1920x1080@24Hz */
1071 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1072 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1073 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1074 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1075 /* 73 - 1920x1080@25Hz */
1076 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1077 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1078 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1079 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1080 /* 74 - 1920x1080@30Hz */
1081 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1082 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1083 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1084 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1085 /* 75 - 1920x1080@50Hz */
1086 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1087 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1088 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1089 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1090 /* 76 - 1920x1080@60Hz */
1091 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1092 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1093 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1094 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1095 /* 77 - 1920x1080@100Hz */
1096 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1097 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1098 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1099 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1100 /* 78 - 1920x1080@120Hz */
1101 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1102 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1103 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1104 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1105 /* 79 - 1680x720@24Hz */
1106 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1107 3080, 3300, 0, 720, 725, 730, 750, 0,
1108 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1109 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1110 /* 80 - 1680x720@25Hz */
1111 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1112 2948, 3168, 0, 720, 725, 730, 750, 0,
1113 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1114 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1115 /* 81 - 1680x720@30Hz */
1116 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1117 2420, 2640, 0, 720, 725, 730, 750, 0,
1118 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1119 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1120 /* 82 - 1680x720@50Hz */
1121 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1122 1980, 2200, 0, 720, 725, 730, 750, 0,
1123 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1124 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1125 /* 83 - 1680x720@60Hz */
1126 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1127 1980, 2200, 0, 720, 725, 730, 750, 0,
1128 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1129 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1130 /* 84 - 1680x720@100Hz */
1131 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1132 1780, 2000, 0, 720, 725, 730, 825, 0,
1133 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1134 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1135 /* 85 - 1680x720@120Hz */
1136 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1137 1780, 2000, 0, 720, 725, 730, 825, 0,
1138 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1139 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1140 /* 86 - 2560x1080@24Hz */
1141 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1142 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1143 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1144 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1145 /* 87 - 2560x1080@25Hz */
1146 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1147 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1148 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1149 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1150 /* 88 - 2560x1080@30Hz */
1151 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1152 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1153 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1154 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1155 /* 89 - 2560x1080@50Hz */
1156 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1157 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1158 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1159 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1160 /* 90 - 2560x1080@60Hz */
1161 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1162 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1163 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1164 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1165 /* 91 - 2560x1080@100Hz */
1166 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1167 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1168 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1169 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1170 /* 92 - 2560x1080@120Hz */
1171 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1172 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1173 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1174 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1175 /* 93 - 3840x2160p@24Hz 16:9 */
1176 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1177 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1178 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1179 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1180 /* 94 - 3840x2160p@25Hz 16:9 */
1181 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1182 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1183 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1184 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1185 /* 95 - 3840x2160p@30Hz 16:9 */
1186 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1187 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1188 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1189 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1190 /* 96 - 3840x2160p@50Hz 16:9 */
1191 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1192 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1193 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1194 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1195 /* 97 - 3840x2160p@60Hz 16:9 */
1196 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1197 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1198 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1199 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1200 /* 98 - 4096x2160p@24Hz 256:135 */
1201 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1202 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1203 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1204 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1205 /* 99 - 4096x2160p@25Hz 256:135 */
1206 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1207 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1208 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1209 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1210 /* 100 - 4096x2160p@30Hz 256:135 */
1211 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1212 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1213 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1214 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1215 /* 101 - 4096x2160p@50Hz 256:135 */
1216 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1217 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1218 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1219 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1220 /* 102 - 4096x2160p@60Hz 256:135 */
1221 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1222 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1223 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1224 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1225 /* 103 - 3840x2160p@24Hz 64:27 */
1226 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1227 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1228 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1229 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1230 /* 104 - 3840x2160p@25Hz 64:27 */
1231 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1232 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1233 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1234 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1235 /* 105 - 3840x2160p@30Hz 64:27 */
1236 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1237 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1238 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1239 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1240 /* 106 - 3840x2160p@50Hz 64:27 */
1241 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1242 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1243 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1244 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1245 /* 107 - 3840x2160p@60Hz 64:27 */
1246 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1247 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1248 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1249 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
a6b21831
TR		 1250};
1251
7ebe1963 1252/*
d9278b4c 1253 * HDMI 1.4 4k modes. Index using the VIC.
7ebe1963
LD		 1254 */
1255static const struct drm_display_mode edid_4k_modes[] = {
d9278b4c
JN		 1256 /* 0 - dummy, VICs start at 1 */
1257 { },
7ebe1963
LD		 1258 /* 1 - 3840x2160@30Hz */
1259 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1260 3840, 4016, 4104, 4400, 0,
1261 2160, 2168, 2178, 2250, 0,
1262 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1263 .vrefresh = 30, },
1264 /* 2 - 3840x2160@25Hz */
1265 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1266 3840, 4896, 4984, 5280, 0,
1267 2160, 2168, 2178, 2250, 0,
1268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1269 .vrefresh = 25, },
1270 /* 3 - 3840x2160@24Hz */
1271 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1272 3840, 5116, 5204, 5500, 0,
1273 2160, 2168, 2178, 2250, 0,
1274 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1275 .vrefresh = 24, },
1276 /* 4 - 4096x2160@24Hz (SMPTE) */
1277 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1278 4096, 5116, 5204, 5500, 0,
1279 2160, 2168, 2178, 2250, 0,
1280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1281 .vrefresh = 24, },
1282};
1283
61e57a8d 1284/*** DDC fetch and block validation ***/
f453ba04 1285
083ae056
AJ		 1286static const u8 edid_header[] = {
1287 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1288};
f453ba04 1289
db6cf833
TR		 1290/**
1291 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1292 * @raw_edid: pointer to raw base EDID block
1293 *
1294 * Sanity check the header of the base EDID block.
1295 *
1296 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
051963d4
TR		 1297 */
1298int drm_edid_header_is_valid(const u8 *raw_edid)
1299{
1300 int i, score = 0;
1301
1302 for (i = 0; i < sizeof(edid_header); i++)
1303 if (raw_edid[i] == edid_header[i])
1304 score++;
1305
1306 return score;
1307}
1308EXPORT_SYMBOL(drm_edid_header_is_valid);
1309
47819ba2
AJ		 1310static int edid_fixup __read_mostly = 6;
1311module_param_named(edid_fixup, edid_fixup, int, 0400);
1312MODULE_PARM_DESC(edid_fixup,
1313 "Minimum number of valid EDID header bytes (0-8, default 6)");
051963d4 1314
40d9b043
DA		 1315static void drm_get_displayid(struct drm_connector *connector,
1316 struct edid *edid);
da9df2f4 1317
c465bbc8
SB		 1318static int drm_edid_block_checksum(const u8 *raw_edid)
1319{
1320 int i;
1321 u8 csum = 0;
1322 for (i = 0; i < EDID_LENGTH; i++)
1323 csum += raw_edid[i];
1324
1325 return csum;
1326}
1327
d6885d65
SB		 1328static bool drm_edid_is_zero(const u8 *in_edid, int length)
1329{
1330 if (memchr_inv(in_edid, 0, length))
1331 return false;
1332
1333 return true;
1334}
1335
db6cf833
TR		 1336/**
1337 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1338 * @raw_edid: pointer to raw EDID block
1339 * @block: type of block to validate (0 for base, extension otherwise)
1340 * @print_bad_edid: if true, dump bad EDID blocks to the console
6ba2bd3d 1341 * @edid_corrupt: if true, the header or checksum is invalid
db6cf833
TR		 1342 *
1343 * Validate a base or extension EDID block and optionally dump bad blocks to
1344 * the console.
1345 *
1346 * Return: True if the block is valid, false otherwise.
f453ba04 1347 */
6ba2bd3d
TP		 1348bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
1349 bool *edid_corrupt)
f453ba04 1350{
c465bbc8 1351 u8 csum;
61e57a8d 1352 struct edid *edid = (struct edid *)raw_edid;
f453ba04 1353
fe2ef780
SWK		 1354 if (WARN_ON(!raw_edid))
1355 return false;
1356
47819ba2
AJ		 1357 if (edid_fixup > 8 || edid_fixup < 0)
1358 edid_fixup = 6;
1359
f89ec8a4 1360 if (block == 0) {
051963d4 1361 int score = drm_edid_header_is_valid(raw_edid);
6ba2bd3d
TP		 1362 if (score == 8) {
1363 if (edid_corrupt)
ac6f2e29 1364 *edid_corrupt = false;
6ba2bd3d
TP		 1365 } else if (score >= edid_fixup) {
1366 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
1367 * The corrupt flag needs to be set here otherwise, the
1368 * fix-up code here will correct the problem, the
1369 * checksum is correct and the test fails
1370 */
1371 if (edid_corrupt)
ac6f2e29 1372 *edid_corrupt = true;
61e57a8d
AJ		 1373 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1374 memcpy(raw_edid, edid_header, sizeof(edid_header));
1375 } else {
6ba2bd3d 1376 if (edid_corrupt)
ac6f2e29 1377 *edid_corrupt = true;
61e57a8d
AJ		 1378 goto bad;
1379 }
1380 }
f453ba04 1381
c465bbc8 1382 csum = drm_edid_block_checksum(raw_edid);
f453ba04 1383 if (csum) {
6ba2bd3d 1384 if (edid_corrupt)
ac6f2e29 1385 *edid_corrupt = true;
6ba2bd3d 1386
4a638b4e 1387 /* allow CEA to slide through, switches mangle this */
82d75356
TV		 1388 if (raw_edid[0] == CEA_EXT) {
1389 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum);
1390 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n");
1391 } else {
1392 if (print_bad_edid)
813a7878 1393 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum);
82d75356 1394
4a638b4e 1395 goto bad;
82d75356 1396 }
f453ba04
DA		 1397 }
1398
61e57a8d
AJ		 1399 /* per-block-type checks */
1400 switch (raw_edid[0]) {
1401 case 0: /* base */
1402 if (edid->version != 1) {
813a7878 1403 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version);
61e57a8d
AJ		 1404 goto bad;
1405 }
862b89c0 1406
61e57a8d
AJ		 1407 if (edid->revision > 4)
1408 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1409 break;
862b89c0 1410
61e57a8d
AJ		 1411 default:
1412 break;
1413 }
47ee4ccf 1414
fe2ef780 1415 return true;
f453ba04
DA		 1416
1417bad:
fe2ef780 1418 if (print_bad_edid) {
da4c07b7 1419 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
499447db 1420 pr_notice("EDID block is all zeroes\n");
da4c07b7 1421 } else {
499447db 1422 pr_notice("Raw EDID:\n");
813a7878
CW		 1423 print_hex_dump(KERN_NOTICE,
1424 " \t", DUMP_PREFIX_NONE, 16, 1,
1425 raw_edid, EDID_LENGTH, false);
da4c07b7 1426 }
f453ba04 1427 }
fe2ef780 1428 return false;
f453ba04 1429}
da0df92b 1430EXPORT_SYMBOL(drm_edid_block_valid);
61e57a8d
AJ		 1431
1432/**
1433 * drm_edid_is_valid - sanity check EDID data
1434 * @edid: EDID data
1435 *
1436 * Sanity-check an entire EDID record (including extensions)
db6cf833
TR		 1437 *
1438 * Return: True if the EDID data is valid, false otherwise.
61e57a8d
AJ		 1439 */
1440bool drm_edid_is_valid(struct edid *edid)
1441{
1442 int i;
1443 u8 *raw = (u8 *)edid;
1444
1445 if (!edid)
1446 return false;
1447
1448 for (i = 0; i <= edid->extensions; i++)
6ba2bd3d 1449 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
61e57a8d
AJ		 1450 return false;
1451
1452 return true;
1453}
3c537889 1454EXPORT_SYMBOL(drm_edid_is_valid);
f453ba04 1455
61e57a8d
AJ		 1456#define DDC_SEGMENT_ADDR 0x30
1457/**
db6cf833 1458 * drm_do_probe_ddc_edid() - get EDID information via I2C
7c58e87e 1459 * @data: I2C device adapter
fc66811c
DV		 1460 * @buf: EDID data buffer to be filled
1461 * @block: 128 byte EDID block to start fetching from
1462 * @len: EDID data buffer length to fetch
1463 *
db6cf833 1464 * Try to fetch EDID information by calling I2C driver functions.
61e57a8d 1465 *
db6cf833 1466 * Return: 0 on success or -1 on failure.
61e57a8d
AJ		 1467 */
1468static int
18df89fe 1469drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
61e57a8d 1470{
18df89fe 1471 struct i2c_adapter *adapter = data;
61e57a8d 1472 unsigned char start = block * EDID_LENGTH;
cd004b3f
S		 1473 unsigned char segment = block >> 1;
1474 unsigned char xfers = segment ? 3 : 2;
4819d2e4
CW		 1475 int ret, retries = 5;
1476
db6cf833
TR		 1477 /*
1478 * The core I2C driver will automatically retry the transfer if the
4819d2e4
CW		 1479 * adapter reports EAGAIN. However, we find that bit-banging transfers
1480 * are susceptible to errors under a heavily loaded machine and
1481 * generate spurious NAKs and timeouts. Retrying the transfer
1482 * of the individual block a few times seems to overcome this.
1483 */
1484 do {
1485 struct i2c_msg msgs[] = {
1486 {
cd004b3f
S		 1487 .addr = DDC_SEGMENT_ADDR,
1488 .flags = 0,
1489 .len = 1,
1490 .buf = &segment,
1491 }, {
4819d2e4
CW		 1492 .addr = DDC_ADDR,
1493 .flags = 0,
1494 .len = 1,
1495 .buf = &start,
1496 }, {
1497 .addr = DDC_ADDR,
1498 .flags = I2C_M_RD,
1499 .len = len,
1500 .buf = buf,
1501 }
1502 };
cd004b3f 1503
db6cf833
TR		 1504 /*
1505 * Avoid sending the segment addr to not upset non-compliant
1506 * DDC monitors.
1507 */
cd004b3f
S		 1508 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1509
9292f37e
ED		 1510 if (ret == -ENXIO) {
1511 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1512 adapter->name);
1513 break;
1514 }
cd004b3f 1515 } while (ret != xfers && --retries);
4819d2e4 1516
cd004b3f 1517 return ret == xfers ? 0 : -1;
61e57a8d
AJ		 1518}
1519
14544d09
CW		 1520static void connector_bad_edid(struct drm_connector *connector,
1521 u8 *edid, int num_blocks)
1522{
1523 int i;
1524
1525 if (connector->bad_edid_counter++ && !(drm_debug & DRM_UT_KMS))
1526 return;
1527
1528 dev_warn(connector->dev->dev,
1529 "%s: EDID is invalid:\n",
1530 connector->name);
1531 for (i = 0; i < num_blocks; i++) {
1532 u8 *block = edid + i * EDID_LENGTH;
1533 char prefix[20];
1534
1535 if (drm_edid_is_zero(block, EDID_LENGTH))
1536 sprintf(prefix, "\t[%02x] ZERO ", i);
1537 else if (!drm_edid_block_valid(block, i, false, NULL))
1538 sprintf(prefix, "\t[%02x] BAD ", i);
1539 else
1540 sprintf(prefix, "\t[%02x] GOOD ", i);
1541
1542 print_hex_dump(KERN_WARNING,
1543 prefix, DUMP_PREFIX_NONE, 16, 1,
1544 block, EDID_LENGTH, false);
1545 }
1546}
1547
18df89fe
LPC		 1548/**
1549 * drm_do_get_edid - get EDID data using a custom EDID block read function
1550 * @connector: connector we're probing
1551 * @get_edid_block: EDID block read function
1552 * @data: private data passed to the block read function
1553 *
1554 * When the I2C adapter connected to the DDC bus is hidden behind a device that
1555 * exposes a different interface to read EDID blocks this function can be used
1556 * to get EDID data using a custom block read function.
1557 *
1558 * As in the general case the DDC bus is accessible by the kernel at the I2C
1559 * level, drivers must make all reasonable efforts to expose it as an I2C
1560 * adapter and use drm_get_edid() instead of abusing this function.
1561 *
53fd40a9
JN		 1562 * The EDID may be overridden using debugfs override_edid or firmare EDID
1563 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
1564 * order. Having either of them bypasses actual EDID reads.
1565 *
18df89fe
LPC		 1566 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1567 */
1568struct edid *drm_do_get_edid(struct drm_connector *connector,
1569 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
1570 size_t len),
1571 void *data)
61e57a8d 1572{
0ea75e23 1573 int i, j = 0, valid_extensions = 0;
f14f3686 1574 u8 *edid, *new;
53fd40a9
JN		 1575 struct edid *override = NULL;
1576
1577 if (connector->override_edid)
11b83e3f 1578 override = drm_edid_duplicate(connector->edid_blob_ptr->data);
53fd40a9
JN		 1579
1580 if (!override)
1581 override = drm_load_edid_firmware(connector);
1582
1583 if (!IS_ERR_OR_NULL(override))
1584 return override;
61e57a8d 1585
f14f3686 1586 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
61e57a8d
AJ		 1587 return NULL;
1588
1589 /* base block fetch */
1590 for (i = 0; i < 4; i++) {
f14f3686 1591 if (get_edid_block(data, edid, 0, EDID_LENGTH))
61e57a8d 1592 goto out;
14544d09 1593 if (drm_edid_block_valid(edid, 0, false,
6ba2bd3d 1594 &connector->edid_corrupt))
61e57a8d 1595 break;
f14f3686 1596 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) {
4a9a8b71
DA		 1597 connector->null_edid_counter++;
1598 goto carp;
1599 }
61e57a8d
AJ		 1600 }
1601 if (i == 4)
1602 goto carp;
1603
1604 /* if there's no extensions, we're done */
14544d09
CW		 1605 valid_extensions = edid[0x7e];
1606 if (valid_extensions == 0)
f14f3686 1607 return (struct edid *)edid;
61e57a8d 1608
14544d09 1609 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
61e57a8d
AJ		 1610 if (!new)
1611 goto out;
f14f3686 1612 edid = new;
61e57a8d 1613
f14f3686 1614 for (j = 1; j <= edid[0x7e]; j++) {
14544d09 1615 u8 *block = edid + j * EDID_LENGTH;
a28187cc 1616
61e57a8d 1617 for (i = 0; i < 4; i++) {
a28187cc 1618 if (get_edid_block(data, block, j, EDID_LENGTH))
61e57a8d 1619 goto out;
14544d09 1620 if (drm_edid_block_valid(block, j, false, NULL))
61e57a8d
AJ		 1621 break;
1622 }
f934ec8c 1623
14544d09
CW		 1624 if (i == 4)
1625 valid_extensions--;
0ea75e23
ST		 1626 }
1627
f14f3686 1628 if (valid_extensions != edid[0x7e]) {
14544d09
CW		 1629 u8 *base;
1630
1631 connector_bad_edid(connector, edid, edid[0x7e] + 1);
1632
f14f3686
CW		 1633 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions;
1634 edid[0x7e] = valid_extensions;
14544d09
CW		 1635
1636 new = kmalloc((valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
0ea75e23
ST		 1637 if (!new)
1638 goto out;
14544d09
CW		 1639
1640 base = new;
1641 for (i = 0; i <= edid[0x7e]; i++) {
1642 u8 *block = edid + i * EDID_LENGTH;
1643
1644 if (!drm_edid_block_valid(block, i, false, NULL))
1645 continue;
1646
1647 memcpy(base, block, EDID_LENGTH);
1648 base += EDID_LENGTH;
1649 }
1650
1651 kfree(edid);
f14f3686 1652 edid = new;
61e57a8d
AJ		 1653 }
1654
f14f3686 1655 return (struct edid *)edid;
61e57a8d
AJ		 1656
1657carp:
14544d09 1658 connector_bad_edid(connector, edid, 1);
61e57a8d 1659out:
f14f3686 1660 kfree(edid);
61e57a8d
AJ		 1661 return NULL;
1662}
18df89fe 1663EXPORT_SYMBOL_GPL(drm_do_get_edid);
61e57a8d
AJ		 1664
1665/**
db6cf833
TR		 1666 * drm_probe_ddc() - probe DDC presence
1667 * @adapter: I2C adapter to probe
fc66811c 1668 *
db6cf833 1669 * Return: True on success, false on failure.
61e57a8d 1670 */
fbff4690 1671bool
61e57a8d
AJ		 1672drm_probe_ddc(struct i2c_adapter *adapter)
1673{
1674 unsigned char out;
1675
1676 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
1677}
fbff4690 1678EXPORT_SYMBOL(drm_probe_ddc);
61e57a8d
AJ		 1679
1680/**
1681 * drm_get_edid - get EDID data, if available
1682 * @connector: connector we're probing
db6cf833 1683 * @adapter: I2C adapter to use for DDC
61e57a8d 1684 *
db6cf833 1685 * Poke the given I2C channel to grab EDID data if possible. If found,
61e57a8d
AJ		 1686 * attach it to the connector.
1687 *
db6cf833 1688 * Return: Pointer to valid EDID or NULL if we couldn't find any.
61e57a8d
AJ		 1689 */
1690struct edid *drm_get_edid(struct drm_connector *connector,
1691 struct i2c_adapter *adapter)
1692{
40d9b043
DA		 1693 struct edid *edid;
1694
15f080f0
JN		 1695 if (connector->force == DRM_FORCE_OFF)
1696 return NULL;
1697
1698 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
18df89fe 1699 return NULL;
61e57a8d 1700
40d9b043
DA		 1701 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
1702 if (edid)
1703 drm_get_displayid(connector, edid);
1704 return edid;
61e57a8d
AJ		 1705}
1706EXPORT_SYMBOL(drm_get_edid);
1707
5cb8eaa2
LW		 1708/**
1709 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
1710 * @connector: connector we're probing
1711 * @adapter: I2C adapter to use for DDC
1712 *
1713 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
1714 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
1715 * switch DDC to the GPU which is retrieving EDID.
1716 *
1717 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
1718 */
1719struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
1720 struct i2c_adapter *adapter)
1721{
1722 struct pci_dev *pdev = connector->dev->pdev;
1723 struct edid *edid;
1724
1725 vga_switcheroo_lock_ddc(pdev);
1726 edid = drm_get_edid(connector, adapter);
1727 vga_switcheroo_unlock_ddc(pdev);
1728
1729 return edid;
1730}
1731EXPORT_SYMBOL(drm_get_edid_switcheroo);
1732
51f8da59
JN		 1733/**
1734 * drm_edid_duplicate - duplicate an EDID and the extensions
1735 * @edid: EDID to duplicate
1736 *
db6cf833 1737 * Return: Pointer to duplicated EDID or NULL on allocation failure.
51f8da59
JN		 1738 */
1739struct edid *drm_edid_duplicate(const struct edid *edid)
1740{
1741 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1742}
1743EXPORT_SYMBOL(drm_edid_duplicate);
1744
61e57a8d
AJ		 1745/*** EDID parsing ***/
1746
f453ba04
DA		 1747/**
1748 * edid_vendor - match a string against EDID's obfuscated vendor field
1749 * @edid: EDID to match
1750 * @vendor: vendor string
1751 *
1752 * Returns true if @vendor is in @edid, false otherwise
1753 */
170178fe 1754static bool edid_vendor(const struct edid *edid, const char *vendor)
f453ba04
DA		 1755{
1756 char edid_vendor[3];
1757
1758 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
1759 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
1760 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
16456c87 1761 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
f453ba04
DA		 1762
1763 return !strncmp(edid_vendor, vendor, 3);
1764}
1765
1766/**
1767 * edid_get_quirks - return quirk flags for a given EDID
1768 * @edid: EDID to process
1769 *
1770 * This tells subsequent routines what fixes they need to apply.
1771 */
170178fe 1772static u32 edid_get_quirks(const struct edid *edid)
f453ba04 1773{
23c4cfbd 1774 const struct edid_quirk *quirk;
f453ba04
DA		 1775 int i;
1776
1777 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
1778 quirk = &edid_quirk_list[i];
1779
1780 if (edid_vendor(edid, quirk->vendor) &&
1781 (EDID_PRODUCT_ID(edid) == quirk->product_id))
1782 return quirk->quirks;
1783 }
1784
1785 return 0;
1786}
1787
1788#define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
339d202c 1789#define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
f453ba04 1790
f453ba04
DA		 1791/**
1792 * edid_fixup_preferred - set preferred modes based on quirk list
1793 * @connector: has mode list to fix up
1794 * @quirks: quirks list
1795 *
1796 * Walk the mode list for @connector, clearing the preferred status
1797 * on existing modes and setting it anew for the right mode ala @quirks.
1798 */
1799static void edid_fixup_preferred(struct drm_connector *connector,
1800 u32 quirks)
1801{
1802 struct drm_display_mode *t, *cur_mode, *preferred_mode;
f890607b 1803 int target_refresh = 0;
339d202c 1804 int cur_vrefresh, preferred_vrefresh;
f453ba04
DA		 1805
1806 if (list_empty(&connector->probed_modes))
1807 return;
1808
1809 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
1810 target_refresh = 60;
1811 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
1812 target_refresh = 75;
1813
1814 preferred_mode = list_first_entry(&connector->probed_modes,
1815 struct drm_display_mode, head);
1816
1817 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
1818 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
1819
1820 if (cur_mode == preferred_mode)
1821 continue;
1822
1823 /* Largest mode is preferred */
1824 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
1825 preferred_mode = cur_mode;
1826
339d202c
AD		 1827 cur_vrefresh = cur_mode->vrefresh ?
1828 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode);
1829 preferred_vrefresh = preferred_mode->vrefresh ?
1830 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode);
f453ba04
DA		 1831 /* At a given size, try to get closest to target refresh */
1832 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
339d202c
AD		 1833 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
1834 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
f453ba04
DA		 1835 preferred_mode = cur_mode;
1836 }
1837 }
1838
1839 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
1840}
1841
f6e252ba
AJ		 1842static bool
1843mode_is_rb(const struct drm_display_mode *mode)
1844{
1845 return (mode->htotal - mode->hdisplay == 160) &&
1846 (mode->hsync_end - mode->hdisplay == 80) &&
1847 (mode->hsync_end - mode->hsync_start == 32) &&
1848 (mode->vsync_start - mode->vdisplay == 3);
1849}
1850
33c7531d
AJ		 1851/*
1852 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
1853 * @dev: Device to duplicate against
1854 * @hsize: Mode width
1855 * @vsize: Mode height
1856 * @fresh: Mode refresh rate
f6e252ba 1857 * @rb: Mode reduced-blanking-ness
33c7531d
AJ		 1858 *
1859 * Walk the DMT mode list looking for a match for the given parameters.
db6cf833
TR		 1860 *
1861 * Return: A newly allocated copy of the mode, or NULL if not found.
33c7531d 1862 */
1d42bbc8 1863struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
f6e252ba
AJ		 1864 int hsize, int vsize, int fresh,
1865 bool rb)
559ee21d 1866{
07a5e632 1867 int i;
559ee21d 1868
a6b21831 1869 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
b1f559ec 1870 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
f8b46a05
AJ		 1871 if (hsize != ptr->hdisplay)
1872 continue;
1873 if (vsize != ptr->vdisplay)
1874 continue;
1875 if (fresh != drm_mode_vrefresh(ptr))
1876 continue;
f6e252ba
AJ		 1877 if (rb != mode_is_rb(ptr))
1878 continue;
f8b46a05
AJ		 1879
1880 return drm_mode_duplicate(dev, ptr);
559ee21d 1881 }
f8b46a05
AJ		 1882
1883 return NULL;
559ee21d 1884}
1d42bbc8 1885EXPORT_SYMBOL(drm_mode_find_dmt);
23425cae 1886
d1ff6409
AJ		 1887typedef void detailed_cb(struct detailed_timing *timing, void *closure);
1888
4d76a221
AJ		 1889static void
1890cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1891{
1892 int i, n = 0;
4966b2a9 1893 u8 d = ext[0x02];
4d76a221
AJ		 1894 u8 *det_base = ext + d;
1895
4966b2a9 1896 n = (127 - d) / 18;
4d76a221
AJ		 1897 for (i = 0; i < n; i++)
1898 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1899}
1900
cbba98f8
AJ		 1901static void
1902vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1903{
1904 unsigned int i, n = min((int)ext[0x02], 6);
1905 u8 *det_base = ext + 5;
1906
1907 if (ext[0x01] != 1)
1908 return; /* unknown version */
1909
1910 for (i = 0; i < n; i++)
1911 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1912}
1913
d1ff6409
AJ		 1914static void
1915drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
1916{
1917 int i;
1918 struct edid *edid = (struct edid *)raw_edid;
1919
1920 if (edid == NULL)
1921 return;
1922
1923 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
1924 cb(&(edid->detailed_timings[i]), closure);
1925
4d76a221
AJ		 1926 for (i = 1; i <= raw_edid[0x7e]; i++) {
1927 u8 *ext = raw_edid + (i * EDID_LENGTH);
1928 switch (*ext) {
1929 case CEA_EXT:
1930 cea_for_each_detailed_block(ext, cb, closure);
1931 break;
cbba98f8
AJ		 1932 case VTB_EXT:
1933 vtb_for_each_detailed_block(ext, cb, closure);
1934 break;
4d76a221
AJ		 1935 default:
1936 break;
1937 }
1938 }
d1ff6409
AJ		 1939}
1940
1941static void
1942is_rb(struct detailed_timing *t, void *data)
1943{
1944 u8 *r = (u8 *)t;
1945 if (r[3] == EDID_DETAIL_MONITOR_RANGE)
1946 if (r[15] & 0x10)
1947 *(bool *)data = true;
1948}
1949
1950/* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
1951static bool
1952drm_monitor_supports_rb(struct edid *edid)
1953{
1954 if (edid->revision >= 4) {
b196a498 1955 bool ret = false;
d1ff6409
AJ		 1956 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
1957 return ret;
1958 }
1959
1960 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
1961}
1962
7a374350
AJ		 1963static void
1964find_gtf2(struct detailed_timing *t, void *data)
1965{
1966 u8 *r = (u8 *)t;
1967 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02)
1968 *(u8 **)data = r;
1969}
1970
1971/* Secondary GTF curve kicks in above some break frequency */
1972static int
1973drm_gtf2_hbreak(struct edid *edid)
1974{
1975 u8 *r = NULL;
1976 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1977 return r ? (r[12] * 2) : 0;
1978}
1979
1980static int
1981drm_gtf2_2c(struct edid *edid)
1982{
1983 u8 *r = NULL;
1984 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1985 return r ? r[13] : 0;
1986}
1987
1988static int
1989drm_gtf2_m(struct edid *edid)
1990{
1991 u8 *r = NULL;
1992 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1993 return r ? (r[15] << 8) + r[14] : 0;
1994}
1995
1996static int
1997drm_gtf2_k(struct edid *edid)
1998{
1999 u8 *r = NULL;
2000 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2001 return r ? r[16] : 0;
2002}
2003
2004static int
2005drm_gtf2_2j(struct edid *edid)
2006{
2007 u8 *r = NULL;
2008 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2009 return r ? r[17] : 0;
2010}
2011
2012/**
2013 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
2014 * @edid: EDID block to scan
2015 */
2016static int standard_timing_level(struct edid *edid)
2017{
2018 if (edid->revision >= 2) {
2019 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
2020 return LEVEL_CVT;
2021 if (drm_gtf2_hbreak(edid))
2022 return LEVEL_GTF2;
2023 return LEVEL_GTF;
2024 }
2025 return LEVEL_DMT;
2026}
2027
23425cae
AJ		 2028/*
2029 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
2030 * monitors fill with ascii space (0x20) instead.
2031 */
2032static int
2033bad_std_timing(u8 a, u8 b)
2034{
2035 return (a == 0x00 && b == 0x00) ||
2036 (a == 0x01 && b == 0x01) ||
2037 (a == 0x20 && b == 0x20);
2038}
2039
f453ba04
DA		 2040/**
2041 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
fc66811c
DV		 2042 * @connector: connector of for the EDID block
2043 * @edid: EDID block to scan
f453ba04
DA		 2044 * @t: standard timing params
2045 *
2046 * Take the standard timing params (in this case width, aspect, and refresh)
5c61259e 2047 * and convert them into a real mode using CVT/GTF/DMT.
f453ba04 2048 */
7ca6adb3 2049static struct drm_display_mode *
7a374350 2050drm_mode_std(struct drm_connector *connector, struct edid *edid,
464fdeca 2051 struct std_timing *t)
f453ba04 2052{
7ca6adb3
AJ		 2053 struct drm_device *dev = connector->dev;
2054 struct drm_display_mode *m, *mode = NULL;
5c61259e
ZY		 2055 int hsize, vsize;
2056 int vrefresh_rate;
0454beab
MD		 2057 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
2058 >> EDID_TIMING_ASPECT_SHIFT;
5c61259e
ZY		 2059 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
2060 >> EDID_TIMING_VFREQ_SHIFT;
7a374350 2061 int timing_level = standard_timing_level(edid);
5c61259e 2062
23425cae
AJ		 2063 if (bad_std_timing(t->hsize, t->vfreq_aspect))
2064 return NULL;
2065
5c61259e
ZY		 2066 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
2067 hsize = t->hsize * 8 + 248;
2068 /* vrefresh_rate = vfreq + 60 */
2069 vrefresh_rate = vfreq + 60;
2070 /* the vdisplay is calculated based on the aspect ratio */
f066a17d 2071 if (aspect_ratio == 0) {
464fdeca 2072 if (edid->revision < 3)
f066a17d
AJ		 2073 vsize = hsize;
2074 else
2075 vsize = (hsize * 10) / 16;
2076 } else if (aspect_ratio == 1)
f453ba04 2077 vsize = (hsize * 3) / 4;
0454beab 2078 else if (aspect_ratio == 2)
f453ba04
DA		 2079 vsize = (hsize * 4) / 5;
2080 else
2081 vsize = (hsize * 9) / 16;
a0910c8e
AJ		 2082
2083 /* HDTV hack, part 1 */
2084 if (vrefresh_rate == 60 &&
2085 ((hsize == 1360 && vsize == 765) ||
2086 (hsize == 1368 && vsize == 769))) {
2087 hsize = 1366;
2088 vsize = 768;
2089 }
2090
7ca6adb3
AJ		 2091 /*
2092 * If this connector already has a mode for this size and refresh
2093 * rate (because it came from detailed or CVT info), use that
2094 * instead. This way we don't have to guess at interlace or
2095 * reduced blanking.
2096 */
522032da 2097 list_for_each_entry(m, &connector->probed_modes, head)
7ca6adb3
AJ		 2098 if (m->hdisplay == hsize && m->vdisplay == vsize &&
2099 drm_mode_vrefresh(m) == vrefresh_rate)
2100 return NULL;
2101
a0910c8e
AJ		 2102 /* HDTV hack, part 2 */
2103 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
2104 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
d50ba256 2105 false);
a5ef6567
JM		 2106 if (!mode)
2107 return NULL;
559ee21d 2108 mode->hdisplay = 1366;
a4967de6
AJ		 2109 mode->hsync_start = mode->hsync_start - 1;
2110 mode->hsync_end = mode->hsync_end - 1;
559ee21d
ZY		 2111 return mode;
2112 }
a0910c8e 2113
559ee21d 2114 /* check whether it can be found in default mode table */
f6e252ba
AJ		 2115 if (drm_monitor_supports_rb(edid)) {
2116 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
2117 true);
2118 if (mode)
2119 return mode;
2120 }
2121 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
559ee21d
ZY		 2122 if (mode)
2123 return mode;
2124
f6e252ba 2125 /* okay, generate it */
5c61259e
ZY		 2126 switch (timing_level) {
2127 case LEVEL_DMT:
5c61259e
ZY		 2128 break;
2129 case LEVEL_GTF:
2130 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2131 break;
7a374350
AJ		 2132 case LEVEL_GTF2:
2133 /*
2134 * This is potentially wrong if there's ever a monitor with
2135 * more than one ranges section, each claiming a different
2136 * secondary GTF curve. Please don't do that.
2137 */
2138 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
fc48f169
TI		 2139 if (!mode)
2140 return NULL;
7a374350 2141 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
aefd330e 2142 drm_mode_destroy(dev, mode);
7a374350
AJ		 2143 mode = drm_gtf_mode_complex(dev, hsize, vsize,
2144 vrefresh_rate, 0, 0,
2145 drm_gtf2_m(edid),
2146 drm_gtf2_2c(edid),
2147 drm_gtf2_k(edid),
2148 drm_gtf2_2j(edid));
2149 }
2150 break;
5c61259e 2151 case LEVEL_CVT:
d50ba256
DA		 2152 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
2153 false);
5c61259e
ZY		 2154 break;
2155 }
f453ba04
DA		 2156 return mode;
2157}
2158
b58db2c6
AJ		 2159/*
2160 * EDID is delightfully ambiguous about how interlaced modes are to be
2161 * encoded. Our internal representation is of frame height, but some
2162 * HDTV detailed timings are encoded as field height.
2163 *
2164 * The format list here is from CEA, in frame size. Technically we
2165 * should be checking refresh rate too. Whatever.
2166 */
2167static void
2168drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
2169 struct detailed_pixel_timing *pt)
2170{
2171 int i;
2172 static const struct {
2173 int w, h;
2174 } cea_interlaced[] = {
2175 { 1920, 1080 },
2176 { 720, 480 },
2177 { 1440, 480 },
2178 { 2880, 480 },
2179 { 720, 576 },
2180 { 1440, 576 },
2181 { 2880, 576 },
2182 };
b58db2c6
AJ		 2183
2184 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
2185 return;
2186
3c581411 2187 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
b58db2c6
AJ		 2188 if ((mode->hdisplay == cea_interlaced[i].w) &&
2189 (mode->vdisplay == cea_interlaced[i].h / 2)) {
2190 mode->vdisplay *= 2;
2191 mode->vsync_start *= 2;
2192 mode->vsync_end *= 2;
2193 mode->vtotal *= 2;
2194 mode->vtotal |= 1;
2195 }
2196 }
2197
2198 mode->flags |= DRM_MODE_FLAG_INTERLACE;
2199}
2200
f453ba04
DA		 2201/**
2202 * drm_mode_detailed - create a new mode from an EDID detailed timing section
2203 * @dev: DRM device (needed to create new mode)
2204 * @edid: EDID block
2205 * @timing: EDID detailed timing info
2206 * @quirks: quirks to apply
2207 *
2208 * An EDID detailed timing block contains enough info for us to create and
2209 * return a new struct drm_display_mode.
2210 */
2211static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
2212 struct edid *edid,
2213 struct detailed_timing *timing,
2214 u32 quirks)
2215{
2216 struct drm_display_mode *mode;
2217 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
0454beab
MD		 2218 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
2219 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
2220 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
2221 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
e14cbee4
MD		 2222 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
2223 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
16dad1d7 2224 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
e14cbee4 2225 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
f453ba04 2226
fc438966 2227 /* ignore tiny modes */
0454beab 2228 if (hactive < 64 || vactive < 64)
fc438966
AJ		 2229 return NULL;
2230
0454beab 2231 if (pt->misc & DRM_EDID_PT_STEREO) {
c7d015f3 2232 DRM_DEBUG_KMS("stereo mode not supported\n");
f453ba04
DA		 2233 return NULL;
2234 }
0454beab 2235 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
c7d015f3 2236 DRM_DEBUG_KMS("composite sync not supported\n");
f453ba04
DA		 2237 }
2238
fcb45611
ZY		 2239 /* it is incorrect if hsync/vsync width is zero */
2240 if (!hsync_pulse_width || !vsync_pulse_width) {
2241 DRM_DEBUG_KMS("Incorrect Detailed timing. "
2242 "Wrong Hsync/Vsync pulse width\n");
2243 return NULL;
2244 }
bc42aabc
AJ		 2245
2246 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
2247 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
2248 if (!mode)
2249 return NULL;
2250
2251 goto set_size;
2252 }
2253
f453ba04
DA		 2254 mode = drm_mode_create(dev);
2255 if (!mode)
2256 return NULL;
2257
f453ba04 2258 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
0454beab
MD		 2259 timing->pixel_clock = cpu_to_le16(1088);
2260
2261 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
2262
2263 mode->hdisplay = hactive;
2264 mode->hsync_start = mode->hdisplay + hsync_offset;
2265 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
2266 mode->htotal = mode->hdisplay + hblank;
2267
2268 mode->vdisplay = vactive;
2269 mode->vsync_start = mode->vdisplay + vsync_offset;
2270 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
2271 mode->vtotal = mode->vdisplay + vblank;
f453ba04 2272
7064fef5
JB		 2273 /* Some EDIDs have bogus h/vtotal values */
2274 if (mode->hsync_end > mode->htotal)
2275 mode->htotal = mode->hsync_end + 1;
2276 if (mode->vsync_end > mode->vtotal)
2277 mode->vtotal = mode->vsync_end + 1;
2278
b58db2c6 2279 drm_mode_do_interlace_quirk(mode, pt);
f453ba04
DA		 2280
2281 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
0454beab 2282 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
f453ba04
DA		 2283 }
2284
0454beab
MD		 2285 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
2286 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
2287 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
2288 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
f453ba04 2289
bc42aabc 2290set_size:
e14cbee4
MD		 2291 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
2292 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
f453ba04
DA		 2293
2294 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
2295 mode->width_mm *= 10;
2296 mode->height_mm *= 10;
2297 }
2298
2299 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
2300 mode->width_mm = edid->width_cm * 10;
2301 mode->height_mm = edid->height_cm * 10;
2302 }
2303
bc42aabc 2304 mode->type = DRM_MODE_TYPE_DRIVER;
c19b3b0f 2305 mode->vrefresh = drm_mode_vrefresh(mode);
bc42aabc
AJ		 2306 drm_mode_set_name(mode);
2307
f453ba04
DA		 2308 return mode;
2309}
2310
b17e52ef 2311static bool
b1f559ec
CW		 2312mode_in_hsync_range(const struct drm_display_mode *mode,
2313 struct edid *edid, u8 *t)
b17e52ef
AJ		 2314{
2315 int hsync, hmin, hmax;
2316
2317 hmin = t[7];
2318 if (edid->revision >= 4)
2319 hmin += ((t[4] & 0x04) ? 255 : 0);
2320 hmax = t[8];
2321 if (edid->revision >= 4)
2322 hmax += ((t[4] & 0x08) ? 255 : 0);
07a5e632 2323 hsync = drm_mode_hsync(mode);
07a5e632 2324
b17e52ef
AJ		 2325 return (hsync <= hmax && hsync >= hmin);
2326}
2327
2328static bool
b1f559ec
CW		 2329mode_in_vsync_range(const struct drm_display_mode *mode,
2330 struct edid *edid, u8 *t)
b17e52ef
AJ		 2331{
2332 int vsync, vmin, vmax;
2333
2334 vmin = t[5];
2335 if (edid->revision >= 4)
2336 vmin += ((t[4] & 0x01) ? 255 : 0);
2337 vmax = t[6];
2338 if (edid->revision >= 4)
2339 vmax += ((t[4] & 0x02) ? 255 : 0);
2340 vsync = drm_mode_vrefresh(mode);
2341
2342 return (vsync <= vmax && vsync >= vmin);
2343}
2344
2345static u32
2346range_pixel_clock(struct edid *edid, u8 *t)
2347{
2348 /* unspecified */
2349 if (t[9] == 0 || t[9] == 255)
2350 return 0;
2351
2352 /* 1.4 with CVT support gives us real precision, yay */
2353 if (edid->revision >= 4 && t[10] == 0x04)
2354 return (t[9] * 10000) - ((t[12] >> 2) * 250);
2355
2356 /* 1.3 is pathetic, so fuzz up a bit */
2357 return t[9] * 10000 + 5001;
2358}
2359
b17e52ef 2360static bool
b1f559ec 2361mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
b17e52ef
AJ		 2362 struct detailed_timing *timing)
2363{
2364 u32 max_clock;
2365 u8 *t = (u8 *)timing;
2366
2367 if (!mode_in_hsync_range(mode, edid, t))
07a5e632
AJ		 2368 return false;
2369
b17e52ef 2370 if (!mode_in_vsync_range(mode, edid, t))
07a5e632
AJ		 2371 return false;
2372
b17e52ef 2373 if ((max_clock = range_pixel_clock(edid, t)))
07a5e632
AJ		 2374 if (mode->clock > max_clock)
2375 return false;
b17e52ef
AJ		 2376
2377 /* 1.4 max horizontal check */
2378 if (edid->revision >= 4 && t[10] == 0x04)
2379 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
2380 return false;
2381
2382 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
2383 return false;
07a5e632
AJ		 2384
2385 return true;
2386}
2387
7b668ebe
TI		 2388static bool valid_inferred_mode(const struct drm_connector *connector,
2389 const struct drm_display_mode *mode)
2390{
85f8fcd6 2391 const struct drm_display_mode *m;
7b668ebe
TI		 2392 bool ok = false;
2393
2394 list_for_each_entry(m, &connector->probed_modes, head) {
2395 if (mode->hdisplay == m->hdisplay &&
2396 mode->vdisplay == m->vdisplay &&
2397 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
2398 return false; /* duplicated */
2399 if (mode->hdisplay <= m->hdisplay &&
2400 mode->vdisplay <= m->vdisplay)
2401 ok = true;
2402 }
2403 return ok;
2404}
2405
b17e52ef 2406static int
cd4cd3de 2407drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
b17e52ef 2408 struct detailed_timing *timing)
07a5e632
AJ		 2409{
2410 int i, modes = 0;
2411 struct drm_display_mode *newmode;
2412 struct drm_device *dev = connector->dev;
2413
a6b21831 2414 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
7b668ebe
TI		 2415 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
2416 valid_inferred_mode(connector, drm_dmt_modes + i)) {
07a5e632
AJ		 2417 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
2418 if (newmode) {
2419 drm_mode_probed_add(connector, newmode);
2420 modes++;
2421 }
2422 }
2423 }
2424
2425 return modes;
2426}
2427
c09dedb7
TI		 2428/* fix up 1366x768 mode from 1368x768;
2429 * GFT/CVT can't express 1366 width which isn't dividable by 8
2430 */
969218fe 2431void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
c09dedb7
TI		 2432{
2433 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
2434 mode->hdisplay = 1366;
2435 mode->hsync_start--;
2436 mode->hsync_end--;
2437 drm_mode_set_name(mode);
2438 }
2439}
2440
b309bd37
AJ		 2441static int
2442drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
2443 struct detailed_timing *timing)
2444{
2445 int i, modes = 0;
2446 struct drm_display_mode *newmode;
2447 struct drm_device *dev = connector->dev;
2448
a6b21831 2449 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
b309bd37
AJ		 2450 const struct minimode *m = &extra_modes[i];
2451 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
fc48f169
TI		 2452 if (!newmode)
2453 return modes;
b309bd37 2454
969218fe 2455 drm_mode_fixup_1366x768(newmode);
7b668ebe
TI		 2456 if (!mode_in_range(newmode, edid, timing) ||
2457 !valid_inferred_mode(connector, newmode)) {
b309bd37
AJ		 2458 drm_mode_destroy(dev, newmode);
2459 continue;
2460 }
2461
2462 drm_mode_probed_add(connector, newmode);
2463 modes++;
2464 }
2465
2466 return modes;
2467}
2468
2469static int
2470drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2471 struct detailed_timing *timing)
2472{
2473 int i, modes = 0;
2474 struct drm_display_mode *newmode;
2475 struct drm_device *dev = connector->dev;
2476 bool rb = drm_monitor_supports_rb(edid);
2477
a6b21831 2478 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
b309bd37
AJ		 2479 const struct minimode *m = &extra_modes[i];
2480 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
fc48f169
TI		 2481 if (!newmode)
2482 return modes;
b309bd37 2483
969218fe 2484 drm_mode_fixup_1366x768(newmode);
7b668ebe
TI		 2485 if (!mode_in_range(newmode, edid, timing) ||
2486 !valid_inferred_mode(connector, newmode)) {
b309bd37
AJ		 2487 drm_mode_destroy(dev, newmode);
2488 continue;
2489 }
2490
2491 drm_mode_probed_add(connector, newmode);
2492 modes++;
2493 }
2494
2495 return modes;
2496}
2497
13931579
AJ		 2498static void
2499do_inferred_modes(struct detailed_timing *timing, void *c)
9340d8cf 2500{
13931579
AJ		 2501 struct detailed_mode_closure *closure = c;
2502 struct detailed_non_pixel *data = &timing->data.other_data;
b309bd37 2503 struct detailed_data_monitor_range *range = &data->data.range;
9340d8cf 2504
cb21aafe
AJ		 2505 if (data->type != EDID_DETAIL_MONITOR_RANGE)
2506 return;
2507
2508 closure->modes += drm_dmt_modes_for_range(closure->connector,
2509 closure->edid,
2510 timing);
b309bd37
AJ		 2511
2512 if (!version_greater(closure->edid, 1, 1))
2513 return; /* GTF not defined yet */
2514
2515 switch (range->flags) {
2516 case 0x02: /* secondary gtf, XXX could do more */
2517 case 0x00: /* default gtf */
2518 closure->modes += drm_gtf_modes_for_range(closure->connector,
2519 closure->edid,
2520 timing);
2521 break;
2522 case 0x04: /* cvt, only in 1.4+ */
2523 if (!version_greater(closure->edid, 1, 3))
2524 break;
2525
2526 closure->modes += drm_cvt_modes_for_range(closure->connector,
2527 closure->edid,
2528 timing);
2529 break;
2530 case 0x01: /* just the ranges, no formula */
2531 default:
2532 break;
2533 }
13931579 2534}
69da3015 2535
13931579
AJ		 2536static int
2537add_inferred_modes(struct drm_connector *connector, struct edid *edid)
2538{
2539 struct detailed_mode_closure closure = {
d456ea2e
JL		 2540 .connector = connector,
2541 .edid = edid,
13931579 2542 };
9340d8cf 2543
13931579
AJ		 2544 if (version_greater(edid, 1, 0))
2545 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
2546 &closure);
9340d8cf 2547
13931579 2548 return closure.modes;
9340d8cf
AJ		 2549}
2550
2255be14
AJ		 2551static int
2552drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
2553{
2554 int i, j, m, modes = 0;
2555 struct drm_display_mode *mode;
f3a32d74 2556 u8 *est = ((u8 *)timing) + 6;
2255be14
AJ		 2557
2558 for (i = 0; i < 6; i++) {
891a7469 2559 for (j = 7; j >= 0; j--) {
2255be14 2560 m = (i * 8) + (7 - j);
3c581411 2561 if (m >= ARRAY_SIZE(est3_modes))
2255be14
AJ		 2562 break;
2563 if (est[i] & (1 << j)) {
1d42bbc8
DA		 2564 mode = drm_mode_find_dmt(connector->dev,
2565 est3_modes[m].w,
2566 est3_modes[m].h,
f6e252ba
AJ		 2567 est3_modes[m].r,
2568 est3_modes[m].rb);
2255be14
AJ		 2569 if (mode) {
2570 drm_mode_probed_add(connector, mode);
2571 modes++;
2572 }
2573 }
2574 }
2575 }
2576
2577 return modes;
2578}
2579
13931579
AJ		 2580static void
2581do_established_modes(struct detailed_timing *timing, void *c)
9cf00977 2582{
13931579 2583 struct detailed_mode_closure *closure = c;
9cf00977 2584 struct detailed_non_pixel *data = &timing->data.other_data;
9cf00977 2585
13931579
AJ		 2586 if (data->type == EDID_DETAIL_EST_TIMINGS)
2587 closure->modes += drm_est3_modes(closure->connector, timing);
2588}
9cf00977 2589
13931579
AJ		 2590/**
2591 * add_established_modes - get est. modes from EDID and add them
db6cf833 2592 * @connector: connector to add mode(s) to
13931579
AJ		 2593 * @edid: EDID block to scan
2594 *
2595 * Each EDID block contains a bitmap of the supported "established modes" list
2596 * (defined above). Tease them out and add them to the global modes list.
2597 */
2598static int
2599add_established_modes(struct drm_connector *connector, struct edid *edid)
2600{
2601 struct drm_device *dev = connector->dev;
2602 unsigned long est_bits = edid->established_timings.t1 |
2603 (edid->established_timings.t2 << 8) |
2604 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
2605 int i, modes = 0;
2606 struct detailed_mode_closure closure = {
d456ea2e
JL		 2607 .connector = connector,
2608 .edid = edid,
13931579 2609 };
9cf00977 2610
13931579
AJ		 2611 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
2612 if (est_bits & (1<<i)) {
2613 struct drm_display_mode *newmode;
2614 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
2615 if (newmode) {
2616 drm_mode_probed_add(connector, newmode);
2617 modes++;
2618 }
2619 }
9cf00977
AJ		 2620 }
2621
13931579
AJ		 2622 if (version_greater(edid, 1, 0))
2623 drm_for_each_detailed_block((u8 *)edid,
2624 do_established_modes, &closure);
2625
2626 return modes + closure.modes;
2627}
2628
2629static void
2630do_standard_modes(struct detailed_timing *timing, void *c)
2631{
2632 struct detailed_mode_closure *closure = c;
2633 struct detailed_non_pixel *data = &timing->data.other_data;
2634 struct drm_connector *connector = closure->connector;
2635 struct edid *edid = closure->edid;
2636
2637 if (data->type == EDID_DETAIL_STD_MODES) {
2638 int i;
9cf00977
AJ		 2639 for (i = 0; i < 6; i++) {
2640 struct std_timing *std;
2641 struct drm_display_mode *newmode;
2642
2643 std = &data->data.timings[i];
464fdeca 2644 newmode = drm_mode_std(connector, edid, std);
9cf00977
AJ		 2645 if (newmode) {
2646 drm_mode_probed_add(connector, newmode);
13931579 2647 closure->modes++;
9cf00977
AJ		 2648 }
2649 }
9cf00977 2650 }
9cf00977
AJ		 2651}
2652
f453ba04 2653/**
13931579 2654 * add_standard_modes - get std. modes from EDID and add them
db6cf833 2655 * @connector: connector to add mode(s) to
f453ba04 2656 * @edid: EDID block to scan
f453ba04 2657 *
13931579
AJ		 2658 * Standard modes can be calculated using the appropriate standard (DMT,
2659 * GTF or CVT. Grab them from @edid and add them to the list.
f453ba04 2660 */
13931579
AJ		 2661static int
2662add_standard_modes(struct drm_connector *connector, struct edid *edid)
f453ba04 2663{
9cf00977 2664 int i, modes = 0;
13931579 2665 struct detailed_mode_closure closure = {
d456ea2e
JL		 2666 .connector = connector,
2667 .edid = edid,
13931579
AJ		 2668 };
2669
2670 for (i = 0; i < EDID_STD_TIMINGS; i++) {
2671 struct drm_display_mode *newmode;
2672
2673 newmode = drm_mode_std(connector, edid,
464fdeca 2674 &edid->standard_timings[i]);
13931579
AJ		 2675 if (newmode) {
2676 drm_mode_probed_add(connector, newmode);
2677 modes++;
2678 }
2679 }
2680
2681 if (version_greater(edid, 1, 0))
2682 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
2683 &closure);
2684
2685 /* XXX should also look for standard codes in VTB blocks */
2686
2687 return modes + closure.modes;
2688}
f453ba04 2689
13931579
AJ		 2690static int drm_cvt_modes(struct drm_connector *connector,
2691 struct detailed_timing *timing)
2692{
2693 int i, j, modes = 0;
2694 struct drm_display_mode *newmode;
2695 struct drm_device *dev = connector->dev;
2696 struct cvt_timing *cvt;
2697 const int rates[] = { 60, 85, 75, 60, 50 };
2698 const u8 empty[3] = { 0, 0, 0 };
a327f6b8 2699
13931579
AJ		 2700 for (i = 0; i < 4; i++) {
2701 int uninitialized_var(width), height;
2702 cvt = &(timing->data.other_data.data.cvt[i]);
f453ba04 2703
13931579 2704 if (!memcmp(cvt->code, empty, 3))
9cf00977 2705 continue;
f453ba04 2706
13931579
AJ		 2707 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
2708 switch (cvt->code[1] & 0x0c) {
2709 case 0x00:
2710 width = height * 4 / 3;
2711 break;
2712 case 0x04:
2713 width = height * 16 / 9;
2714 break;
2715 case 0x08:
2716 width = height * 16 / 10;
2717 break;
2718 case 0x0c:
2719 width = height * 15 / 9;
2720 break;
2721 }
2722
2723 for (j = 1; j < 5; j++) {
2724 if (cvt->code[2] & (1 << j)) {
2725 newmode = drm_cvt_mode(dev, width, height,
2726 rates[j], j == 0,
2727 false, false);
2728 if (newmode) {
2729 drm_mode_probed_add(connector, newmode);
2730 modes++;
2731 }
2732 }
2733 }
f453ba04
DA		 2734 }
2735
2736 return modes;
2737}
9cf00977 2738
13931579
AJ		 2739static void
2740do_cvt_mode(struct detailed_timing *timing, void *c)
882f0219 2741{
13931579
AJ		 2742 struct detailed_mode_closure *closure = c;
2743 struct detailed_non_pixel *data = &timing->data.other_data;
882f0219 2744
13931579
AJ		 2745 if (data->type == EDID_DETAIL_CVT_3BYTE)
2746 closure->modes += drm_cvt_modes(closure->connector, timing);
2747}
882f0219 2748
13931579
AJ		 2749static int
2750add_cvt_modes(struct drm_connector *connector, struct edid *edid)
2751{
2752 struct detailed_mode_closure closure = {
d456ea2e
JL		 2753 .connector = connector,
2754 .edid = edid,
13931579 2755 };
882f0219 2756
13931579
AJ		 2757 if (version_greater(edid, 1, 2))
2758 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
882f0219 2759
13931579 2760 /* XXX should also look for CVT codes in VTB blocks */
882f0219 2761
13931579
AJ		 2762 return closure.modes;
2763}
2764
fa3a7340
VS		 2765static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
2766
13931579
AJ		 2767static void
2768do_detailed_mode(struct detailed_timing *timing, void *c)
2769{
2770 struct detailed_mode_closure *closure = c;
2771 struct drm_display_mode *newmode;
2772
2773 if (timing->pixel_clock) {
2774 newmode = drm_mode_detailed(closure->connector->dev,
2775 closure->edid, timing,
2776 closure->quirks);
2777 if (!newmode)
2778 return;
2779
2780 if (closure->preferred)
2781 newmode->type |= DRM_MODE_TYPE_PREFERRED;
2782
fa3a7340
VS		 2783 /*
2784 * Detailed modes are limited to 10kHz pixel clock resolution,
2785 * so fix up anything that looks like CEA/HDMI mode, but the clock
2786 * is just slightly off.
2787 */
2788 fixup_detailed_cea_mode_clock(newmode);
2789
13931579
AJ		 2790 drm_mode_probed_add(closure->connector, newmode);
2791 closure->modes++;
c2925bde 2792 closure->preferred = false;
882f0219 2793 }
13931579 2794}
882f0219 2795
13931579
AJ		 2796/*
2797 * add_detailed_modes - Add modes from detailed timings
2798 * @connector: attached connector
2799 * @edid: EDID block to scan
2800 * @quirks: quirks to apply
2801 */
2802static int
2803add_detailed_modes(struct drm_connector *connector, struct edid *edid,
2804 u32 quirks)
2805{
2806 struct detailed_mode_closure closure = {
d456ea2e
JL		 2807 .connector = connector,
2808 .edid = edid,
c2925bde 2809 .preferred = true,
d456ea2e 2810 .quirks = quirks,
13931579
AJ		 2811 };
2812
2813 if (closure.preferred && !version_greater(edid, 1, 3))
2814 closure.preferred =
2815 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
2816
2817 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
2818
2819 return closure.modes;
882f0219 2820}
f453ba04 2821
8fe9790d 2822#define AUDIO_BLOCK 0x01
54ac76f8 2823#define VIDEO_BLOCK 0x02
f23c20c8 2824#define VENDOR_BLOCK 0x03
76adaa34 2825#define SPEAKER_BLOCK 0x04
87563fc0
SS		 2826#define USE_EXTENDED_TAG 0x07
2827#define EXT_VIDEO_CAPABILITY_BLOCK 0x00
832d4f2f
SS		 2828#define EXT_VIDEO_DATA_BLOCK_420 0x0E
2829#define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F
8fe9790d 2830#define EDID_BASIC_AUDIO (1 << 6)
a988bc72
LPC		 2831#define EDID_CEA_YCRCB444 (1 << 5)
2832#define EDID_CEA_YCRCB422 (1 << 4)
b1edd6a6 2833#define EDID_CEA_VCDB_QS (1 << 6)
8fe9790d 2834
d4e4a31d 2835/*
8fe9790d 2836 * Search EDID for CEA extension block.
f23c20c8 2837 */
170178fe 2838static u8 *drm_find_edid_extension(const struct edid *edid, int ext_id)
f23c20c8 2839{
8fe9790d
ZW		 2840 u8 *edid_ext = NULL;
2841 int i;
f23c20c8
ML		 2842
2843 /* No EDID or EDID extensions */
2844 if (edid == NULL || edid->extensions == 0)
8fe9790d 2845 return NULL;
f23c20c8 2846
f23c20c8 2847 /* Find CEA extension */
7466f4cc 2848 for (i = 0; i < edid->extensions; i++) {
8fe9790d 2849 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
40d9b043 2850 if (edid_ext[0] == ext_id)
f23c20c8
ML		 2851 break;
2852 }
2853
7466f4cc 2854 if (i == edid->extensions)
8fe9790d
ZW		 2855 return NULL;
2856
2857 return edid_ext;
2858}
2859
170178fe 2860static u8 *drm_find_cea_extension(const struct edid *edid)
40d9b043
DA		 2861{
2862 return drm_find_edid_extension(edid, CEA_EXT);
2863}
2864
170178fe 2865static u8 *drm_find_displayid_extension(const struct edid *edid)
40d9b043
DA		 2866{
2867 return drm_find_edid_extension(edid, DISPLAYID_EXT);
2868}
2869
e6e79209
VS		 2870/*
2871 * Calculate the alternate clock for the CEA mode
2872 * (60Hz vs. 59.94Hz etc.)
2873 */
2874static unsigned int
2875cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
2876{
2877 unsigned int clock = cea_mode->clock;
2878
2879 if (cea_mode->vrefresh % 6 != 0)
2880 return clock;
2881
2882 /*
2883 * edid_cea_modes contains the 59.94Hz
2884 * variant for 240 and 480 line modes,
2885 * and the 60Hz variant otherwise.
2886 */
2887 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
9afd808c 2888 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
e6e79209 2889 else
9afd808c 2890 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
e6e79209
VS		 2891
2892 return clock;
2893}
2894
c45a4e46
VS		 2895static bool
2896cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
2897{
2898 /*
2899 * For certain VICs the spec allows the vertical
2900 * front porch to vary by one or two lines.
2901 *
2902 * cea_modes[] stores the variant with the shortest
2903 * vertical front porch. We can adjust the mode to
2904 * get the other variants by simply increasing the
2905 * vertical front porch length.
2906 */
2907 BUILD_BUG_ON(edid_cea_modes[8].vtotal != 262 ||
2908 edid_cea_modes[9].vtotal != 262 ||
2909 edid_cea_modes[12].vtotal != 262 ||
2910 edid_cea_modes[13].vtotal != 262 ||
2911 edid_cea_modes[23].vtotal != 312 ||
2912 edid_cea_modes[24].vtotal != 312 ||
2913 edid_cea_modes[27].vtotal != 312 ||
2914 edid_cea_modes[28].vtotal != 312);
2915
2916 if (((vic == 8 || vic == 9 ||
2917 vic == 12 || vic == 13) && mode->vtotal < 263) ||
2918 ((vic == 23 || vic == 24 ||
2919 vic == 27 || vic == 28) && mode->vtotal < 314)) {
2920 mode->vsync_start++;
2921 mode->vsync_end++;
2922 mode->vtotal++;
2923
2924 return true;
2925 }
2926
2927 return false;
2928}
2929
4c6bcf44
VS		 2930static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
2931 unsigned int clock_tolerance)
2932{
357768cc 2933 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 2934 u8 vic;
4c6bcf44
VS		 2935
2936 if (!to_match->clock)
2937 return 0;
2938
357768cc
VS		 2939 if (to_match->picture_aspect_ratio)
2940 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
2941
d9278b4c 2942 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
c45a4e46 2943 struct drm_display_mode cea_mode = edid_cea_modes[vic];
4c6bcf44
VS		 2944 unsigned int clock1, clock2;
2945
2946 /* Check both 60Hz and 59.94Hz */
c45a4e46
VS		 2947 clock1 = cea_mode.clock;
2948 clock2 = cea_mode_alternate_clock(&cea_mode);
4c6bcf44
VS		 2949
2950 if (abs(to_match->clock - clock1) > clock_tolerance &&
2951 abs(to_match->clock - clock2) > clock_tolerance)
2952 continue;
2953
c45a4e46 2954 do {
357768cc 2955 if (drm_mode_match(to_match, &cea_mode, match_flags))
c45a4e46
VS		 2956 return vic;
2957 } while (cea_mode_alternate_timings(vic, &cea_mode));
4c6bcf44
VS		 2958 }
2959
2960 return 0;
2961}
2962
18316c8c
TR		 2963/**
2964 * drm_match_cea_mode - look for a CEA mode matching given mode
2965 * @to_match: display mode
2966 *
db6cf833 2967 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
18316c8c 2968 * mode.
a4799037 2969 */
18316c8c 2970u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
a4799037 2971{
357768cc 2972 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 2973 u8 vic;
a4799037 2974
a90b590e
VS		 2975 if (!to_match->clock)
2976 return 0;
2977
357768cc
VS		 2978 if (to_match->picture_aspect_ratio)
2979 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
2980
d9278b4c 2981 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
c45a4e46 2982 struct drm_display_mode cea_mode = edid_cea_modes[vic];
a90b590e
VS		 2983 unsigned int clock1, clock2;
2984
a90b590e 2985 /* Check both 60Hz and 59.94Hz */
c45a4e46
VS		 2986 clock1 = cea_mode.clock;
2987 clock2 = cea_mode_alternate_clock(&cea_mode);
a4799037 2988
c45a4e46
VS		 2989 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
2990 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
2991 continue;
2992
2993 do {
357768cc 2994 if (drm_mode_match(to_match, &cea_mode, match_flags))
c45a4e46
VS		 2995 return vic;
2996 } while (cea_mode_alternate_timings(vic, &cea_mode));
a4799037 2997 }
c45a4e46 2998
a4799037
SM		 2999 return 0;
3000}
3001EXPORT_SYMBOL(drm_match_cea_mode);
3002
d9278b4c
JN		 3003static bool drm_valid_cea_vic(u8 vic)
3004{
3005 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes);
3006}
3007
0967e6a5
VK		 3008/**
3009 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to
3010 * the input VIC from the CEA mode list
3011 * @video_code: ID given to each of the CEA modes
3012 *
3013 * Returns picture aspect ratio
3014 */
3015enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
3016{
d9278b4c 3017 return edid_cea_modes[video_code].picture_aspect_ratio;
0967e6a5
VK		 3018}
3019EXPORT_SYMBOL(drm_get_cea_aspect_ratio);
3020
3f2f6533
LD		 3021/*
3022 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
3023 * specific block).
3024 *
3025 * It's almost like cea_mode_alternate_clock(), we just need to add an
3026 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this
3027 * one.
3028 */
3029static unsigned int
3030hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
3031{
3032 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160)
3033 return hdmi_mode->clock;
3034
3035 return cea_mode_alternate_clock(hdmi_mode);
3036}
3037
4c6bcf44
VS		 3038static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
3039 unsigned int clock_tolerance)
3040{
357768cc 3041 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 3042 u8 vic;
4c6bcf44
VS		 3043
3044 if (!to_match->clock)
3045 return 0;
3046
d9278b4c
JN		 3047 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3048 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4c6bcf44
VS		 3049 unsigned int clock1, clock2;
3050
3051 /* Make sure to also match alternate clocks */
3052 clock1 = hdmi_mode->clock;
3053 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3054
3055 if (abs(to_match->clock - clock1) > clock_tolerance &&
3056 abs(to_match->clock - clock2) > clock_tolerance)
3057 continue;
3058
357768cc 3059 if (drm_mode_match(to_match, hdmi_mode, match_flags))
d9278b4c 3060 return vic;
4c6bcf44
VS		 3061 }
3062
3063 return 0;
3064}
3065
3f2f6533
LD		 3066/*
3067 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
3068 * @to_match: display mode
3069 *
3070 * An HDMI mode is one defined in the HDMI vendor specific block.
3071 *
3072 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
3073 */
3074static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
3075{
357768cc 3076 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 3077 u8 vic;
3f2f6533
LD		 3078
3079 if (!to_match->clock)
3080 return 0;
3081
d9278b4c
JN		 3082 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3083 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3f2f6533
LD		 3084 unsigned int clock1, clock2;
3085
3086 /* Make sure to also match alternate clocks */
3087 clock1 = hdmi_mode->clock;
3088 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3089
3090 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
3091 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
357768cc 3092 drm_mode_match(to_match, hdmi_mode, match_flags))
d9278b4c 3093 return vic;
3f2f6533
LD		 3094 }
3095 return 0;
3096}
3097
d9278b4c
JN		 3098static bool drm_valid_hdmi_vic(u8 vic)
3099{
3100 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
3101}
3102
e6e79209
VS		 3103static int
3104add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
3105{
3106 struct drm_device *dev = connector->dev;
3107 struct drm_display_mode *mode, *tmp;
3108 LIST_HEAD(list);
3109 int modes = 0;
3110
3111 /* Don't add CEA modes if the CEA extension block is missing */
3112 if (!drm_find_cea_extension(edid))
3113 return 0;
3114
3115 /*
3116 * Go through all probed modes and create a new mode
3117 * with the alternate clock for certain CEA modes.
3118 */
3119 list_for_each_entry(mode, &connector->probed_modes, head) {
3f2f6533 3120 const struct drm_display_mode *cea_mode = NULL;
e6e79209 3121 struct drm_display_mode *newmode;
d9278b4c 3122 u8 vic = drm_match_cea_mode(mode);
e6e79209
VS		 3123 unsigned int clock1, clock2;
3124
d9278b4c
JN		 3125 if (drm_valid_cea_vic(vic)) {
3126 cea_mode = &edid_cea_modes[vic];
3f2f6533
LD		 3127 clock2 = cea_mode_alternate_clock(cea_mode);
3128 } else {
d9278b4c
JN		 3129 vic = drm_match_hdmi_mode(mode);
3130 if (drm_valid_hdmi_vic(vic)) {
3131 cea_mode = &edid_4k_modes[vic];
3f2f6533
LD		 3132 clock2 = hdmi_mode_alternate_clock(cea_mode);
3133 }
3134 }
e6e79209 3135
3f2f6533
LD		 3136 if (!cea_mode)
3137 continue;
e6e79209
VS		 3138
3139 clock1 = cea_mode->clock;
e6e79209
VS		 3140
3141 if (clock1 == clock2)
3142 continue;
3143
3144 if (mode->clock != clock1 && mode->clock != clock2)
3145 continue;
3146
3147 newmode = drm_mode_duplicate(dev, cea_mode);
3148 if (!newmode)
3149 continue;
3150
27130212
DL		 3151 /* Carry over the stereo flags */
3152 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
3153
e6e79209
VS		 3154 /*
3155 * The current mode could be either variant. Make
3156 * sure to pick the "other" clock for the new mode.
3157 */
3158 if (mode->clock != clock1)
3159 newmode->clock = clock1;
3160 else
3161 newmode->clock = clock2;
3162
3163 list_add_tail(&newmode->head, &list);
3164 }
3165
3166 list_for_each_entry_safe(mode, tmp, &list, head) {
3167 list_del(&mode->head);
3168 drm_mode_probed_add(connector, mode);
3169 modes++;
3170 }
3171
3172 return modes;
3173}
a4799037 3174
8ec6e075
SS		 3175static u8 svd_to_vic(u8 svd)
3176{
3177 /* 0-6 bit vic, 7th bit native mode indicator */
3178 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
3179 return svd & 127;
3180
3181 return svd;
3182}
3183
aff04ace
TW		 3184static struct drm_display_mode *
3185drm_display_mode_from_vic_index(struct drm_connector *connector,
3186 const u8 *video_db, u8 video_len,
3187 u8 video_index)
54ac76f8
CS		 3188{
3189 struct drm_device *dev = connector->dev;
aff04ace 3190 struct drm_display_mode *newmode;
d9278b4c 3191 u8 vic;
54ac76f8 3192
aff04ace
TW		 3193 if (video_db == NULL || video_index >= video_len)
3194 return NULL;
3195
3196 /* CEA modes are numbered 1..127 */
8ec6e075 3197 vic = svd_to_vic(video_db[video_index]);
d9278b4c 3198 if (!drm_valid_cea_vic(vic))
aff04ace
TW		 3199 return NULL;
3200
d9278b4c 3201 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
409bbf1e
DL		 3202 if (!newmode)
3203 return NULL;
3204
aff04ace
TW		 3205 newmode->vrefresh = 0;
3206
3207 return newmode;
3208}
3209
832d4f2f
SS		 3210/*
3211 * do_y420vdb_modes - Parse YCBCR 420 only modes
3212 * @connector: connector corresponding to the HDMI sink
3213 * @svds: start of the data block of CEA YCBCR 420 VDB
3214 * @len: length of the CEA YCBCR 420 VDB
3215 *
3216 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
3217 * which contains modes which can be supported in YCBCR 420
3218 * output format only.
3219 */
3220static int do_y420vdb_modes(struct drm_connector *connector,
3221 const u8 *svds, u8 svds_len)
3222{
3223 int modes = 0, i;
3224 struct drm_device *dev = connector->dev;
3225 struct drm_display_info *info = &connector->display_info;
3226 struct drm_hdmi_info *hdmi = &info->hdmi;
3227
3228 for (i = 0; i < svds_len; i++) {
3229 u8 vic = svd_to_vic(svds[i]);
3230 struct drm_display_mode *newmode;
3231
3232 if (!drm_valid_cea_vic(vic))
3233 continue;
3234
3235 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
3236 if (!newmode)
3237 break;
3238 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
3239 drm_mode_probed_add(connector, newmode);
3240 modes++;
3241 }
3242
3243 if (modes > 0)
3244 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3245 return modes;
3246}
3247
3248/*
3249 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap
3250 * @connector: connector corresponding to the HDMI sink
3251 * @vic: CEA vic for the video mode to be added in the map
3252 *
3253 * Makes an entry for a videomode in the YCBCR 420 bitmap
3254 */
3255static void
3256drm_add_cmdb_modes(struct drm_connector *connector, u8 svd)
3257{
3258 u8 vic = svd_to_vic(svd);
3259 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3260
3261 if (!drm_valid_cea_vic(vic))
3262 return;
3263
3264 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
3265}
3266
aff04ace
TW		 3267static int
3268do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
3269{
3270 int i, modes = 0;
832d4f2f 3271 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
aff04ace
TW		 3272
3273 for (i = 0; i < len; i++) {
3274 struct drm_display_mode *mode;
3275 mode = drm_display_mode_from_vic_index(connector, db, len, i);
3276 if (mode) {
832d4f2f
SS		 3277 /*
3278 * YCBCR420 capability block contains a bitmap which
3279 * gives the index of CEA modes from CEA VDB, which
3280 * can support YCBCR 420 sampling output also (apart
3281 * from RGB/YCBCR444 etc).
3282 * For example, if the bit 0 in bitmap is set,
3283 * first mode in VDB can support YCBCR420 output too.
3284 * Add YCBCR420 modes only if sink is HDMI 2.0 capable.
3285 */
3286 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i))
3287 drm_add_cmdb_modes(connector, db[i]);
3288
aff04ace
TW		 3289 drm_mode_probed_add(connector, mode);
3290 modes++;
54ac76f8
CS		 3291 }
3292 }
3293
3294 return modes;
3295}
3296
c858cfca
DL		 3297struct stereo_mandatory_mode {
3298 int width, height, vrefresh;
3299 unsigned int flags;
3300};
3301
3302static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
f7e121b7
DL		 3303 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3304 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
c858cfca
DL		 3305 { 1920, 1080, 50,
3306 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3307 { 1920, 1080, 60,
3308 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
f7e121b7
DL		 3309 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3310 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
3311 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3312 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
c858cfca
DL		 3313};
3314
3315static bool
3316stereo_match_mandatory(const struct drm_display_mode *mode,
3317 const struct stereo_mandatory_mode *stereo_mode)
3318{
3319 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
3320
3321 return mode->hdisplay == stereo_mode->width &&
3322 mode->vdisplay == stereo_mode->height &&
3323 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
3324 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
3325}
3326
c858cfca
DL		 3327static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
3328{
3329 struct drm_device *dev = connector->dev;
3330 const struct drm_display_mode *mode;
3331 struct list_head stereo_modes;
f7e121b7 3332 int modes = 0, i;
c858cfca
DL		 3333
3334 INIT_LIST_HEAD(&stereo_modes);
3335
3336 list_for_each_entry(mode, &connector->probed_modes, head) {
f7e121b7
DL		 3337 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
3338 const struct stereo_mandatory_mode *mandatory;
c858cfca
DL		 3339 struct drm_display_mode *new_mode;
3340
f7e121b7
DL		 3341 if (!stereo_match_mandatory(mode,
3342 &stereo_mandatory_modes[i]))
3343 continue;
c858cfca 3344
f7e121b7 3345 mandatory = &stereo_mandatory_modes[i];
c858cfca
DL		 3346 new_mode = drm_mode_duplicate(dev, mode);
3347 if (!new_mode)
3348 continue;
3349
f7e121b7 3350 new_mode->flags |= mandatory->flags;
c858cfca
DL		 3351 list_add_tail(&new_mode->head, &stereo_modes);
3352 modes++;
f7e121b7 3353 }
c858cfca
DL		 3354 }
3355
3356 list_splice_tail(&stereo_modes, &connector->probed_modes);
3357
3358 return modes;
3359}
3360
1deee8d7
DL		 3361static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
3362{
3363 struct drm_device *dev = connector->dev;
3364 struct drm_display_mode *newmode;
3365
d9278b4c 3366 if (!drm_valid_hdmi_vic(vic)) {
1deee8d7
DL		 3367 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
3368 return 0;
3369 }
3370
3371 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
3372 if (!newmode)
3373 return 0;
3374
3375 drm_mode_probed_add(connector, newmode);
3376
3377 return 1;
3378}
3379
fbf46025
TW		 3380static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
3381 const u8 *video_db, u8 video_len, u8 video_index)
3382{
fbf46025
TW		 3383 struct drm_display_mode *newmode;
3384 int modes = 0;
fbf46025
TW		 3385
3386 if (structure & (1 << 0)) {
aff04ace
TW		 3387 newmode = drm_display_mode_from_vic_index(connector, video_db,
3388 video_len,
3389 video_index);
fbf46025
TW		 3390 if (newmode) {
3391 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
3392 drm_mode_probed_add(connector, newmode);
3393 modes++;
3394 }
3395 }
3396 if (structure & (1 << 6)) {
aff04ace
TW		 3397 newmode = drm_display_mode_from_vic_index(connector, video_db,
3398 video_len,
3399 video_index);
fbf46025
TW		 3400 if (newmode) {
3401 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3402 drm_mode_probed_add(connector, newmode);
3403 modes++;
3404 }
3405 }
3406 if (structure & (1 << 8)) {
aff04ace
TW		 3407 newmode = drm_display_mode_from_vic_index(connector, video_db,
3408 video_len,
3409 video_index);
fbf46025 3410 if (newmode) {
89570eeb 3411 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
fbf46025
TW		 3412 drm_mode_probed_add(connector, newmode);
3413 modes++;
3414 }
3415 }
3416
3417 return modes;
3418}
3419
7ebe1963
LD		 3420/*
3421 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
3422 * @connector: connector corresponding to the HDMI sink
3423 * @db: start of the CEA vendor specific block
3424 * @len: length of the CEA block payload, ie. one can access up to db[len]
3425 *
c858cfca
DL		 3426 * Parses the HDMI VSDB looking for modes to add to @connector. This function
3427 * also adds the stereo 3d modes when applicable.
7ebe1963
LD		 3428 */
3429static int
fbf46025
TW		 3430do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
3431 const u8 *video_db, u8 video_len)
7ebe1963 3432{
f1781e9b 3433 struct drm_display_info *info = &connector->display_info;
0e5083aa 3434 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
fbf46025
TW		 3435 u8 vic_len, hdmi_3d_len = 0;
3436 u16 mask;
3437 u16 structure_all;
7ebe1963
LD		 3438
3439 if (len < 8)
3440 goto out;
3441
3442 /* no HDMI_Video_Present */
3443 if (!(db[8] & (1 << 5)))
3444 goto out;
3445
3446 /* Latency_Fields_Present */
3447 if (db[8] & (1 << 7))
3448 offset += 2;
3449
3450 /* I_Latency_Fields_Present */
3451 if (db[8] & (1 << 6))
3452 offset += 2;
3453
3454 /* the declared length is not long enough for the 2 first bytes
3455 * of additional video format capabilities */
c858cfca 3456 if (len < (8 + offset + 2))
7ebe1963
LD		 3457 goto out;
3458
c858cfca
DL		 3459 /* 3D_Present */
3460 offset++;
fbf46025 3461 if (db[8 + offset] & (1 << 7)) {
c858cfca
DL		 3462 modes += add_hdmi_mandatory_stereo_modes(connector);
3463
fbf46025
TW		 3464 /* 3D_Multi_present */
3465 multi_present = (db[8 + offset] & 0x60) >> 5;
3466 }
3467
c858cfca 3468 offset++;
7ebe1963 3469 vic_len = db[8 + offset] >> 5;
fbf46025 3470 hdmi_3d_len = db[8 + offset] & 0x1f;
7ebe1963
LD		 3471
3472 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
7ebe1963
LD		 3473 u8 vic;
3474
3475 vic = db[9 + offset + i];
1deee8d7 3476 modes += add_hdmi_mode(connector, vic);
7ebe1963 3477 }
fbf46025
TW		 3478 offset += 1 + vic_len;
3479
0e5083aa
TW		 3480 if (multi_present == 1)
3481 multi_len = 2;
3482 else if (multi_present == 2)
3483 multi_len = 4;
3484 else
3485 multi_len = 0;
fbf46025 3486
0e5083aa 3487 if (len < (8 + offset + hdmi_3d_len - 1))
fbf46025
TW		 3488 goto out;
3489
0e5083aa 3490 if (hdmi_3d_len < multi_len)
fbf46025
TW		 3491 goto out;
3492
0e5083aa
TW		 3493 if (multi_present == 1 || multi_present == 2) {
3494 /* 3D_Structure_ALL */
3495 structure_all = (db[8 + offset] << 8) | db[9 + offset];
fbf46025 3496
0e5083aa
TW		 3497 /* check if 3D_MASK is present */
3498 if (multi_present == 2)
3499 mask = (db[10 + offset] << 8) | db[11 + offset];
3500 else
3501 mask = 0xffff;
3502
3503 for (i = 0; i < 16; i++) {
3504 if (mask & (1 << i))
3505 modes += add_3d_struct_modes(connector,
3506 structure_all,
3507 video_db,
3508 video_len, i);
3509 }
3510 }
3511
3512 offset += multi_len;
3513
3514 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
3515 int vic_index;
3516 struct drm_display_mode *newmode = NULL;
3517 unsigned int newflag = 0;
3518 bool detail_present;
3519
3520 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
3521
3522 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
3523 break;
3524
3525 /* 2D_VIC_order_X */
3526 vic_index = db[8 + offset + i] >> 4;
3527
3528 /* 3D_Structure_X */
3529 switch (db[8 + offset + i] & 0x0f) {
3530 case 0:
3531 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
3532 break;
3533 case 6:
3534 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3535 break;
3536 case 8:
3537 /* 3D_Detail_X */
3538 if ((db[9 + offset + i] >> 4) == 1)
3539 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3540 break;
3541 }
3542
3543 if (newflag != 0) {
3544 newmode = drm_display_mode_from_vic_index(connector,
3545 video_db,
3546 video_len,
3547 vic_index);
3548
3549 if (newmode) {
3550 newmode->flags |= newflag;
3551 drm_mode_probed_add(connector, newmode);
3552 modes++;
3553 }
3554 }
3555
3556 if (detail_present)
3557 i++;
fbf46025 3558 }
7ebe1963
LD		 3559
3560out:
f1781e9b
VS		 3561 if (modes > 0)
3562 info->has_hdmi_infoframe = true;
7ebe1963
LD		 3563 return modes;
3564}
3565
9e50b9d5
VS		 3566static int
3567cea_db_payload_len(const u8 *db)
3568{
3569 return db[0] & 0x1f;
3570}
3571
87563fc0
SS		 3572static int
3573cea_db_extended_tag(const u8 *db)
3574{
3575 return db[1];
3576}
3577
9e50b9d5
VS		 3578static int
3579cea_db_tag(const u8 *db)
3580{
3581 return db[0] >> 5;
3582}
3583
3584static int
3585cea_revision(const u8 *cea)
3586{
3587 return cea[1];
3588}
3589
3590static int
3591cea_db_offsets(const u8 *cea, int *start, int *end)
3592{
3593 /* Data block offset in CEA extension block */
3594 *start = 4;
3595 *end = cea[2];
3596 if (*end == 0)
3597 *end = 127;
3598 if (*end < 4 || *end > 127)
3599 return -ERANGE;
3600 return 0;
3601}
3602
7ebe1963
LD		 3603static bool cea_db_is_hdmi_vsdb(const u8 *db)
3604{
3605 int hdmi_id;
3606
3607 if (cea_db_tag(db) != VENDOR_BLOCK)
3608 return false;
3609
3610 if (cea_db_payload_len(db) < 5)
3611 return false;
3612
3613 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
3614
6cb3b7f1 3615 return hdmi_id == HDMI_IEEE_OUI;
7ebe1963
LD		 3616}
3617
50dd1bd1
TR		 3618static bool cea_db_is_hdmi_forum_vsdb(const u8 *db)
3619{
3620 unsigned int oui;
3621
3622 if (cea_db_tag(db) != VENDOR_BLOCK)
3623 return false;
3624
3625 if (cea_db_payload_len(db) < 7)
3626 return false;
3627
3628 oui = db[3] << 16 | db[2] << 8 | db[1];
3629
3630 return oui == HDMI_FORUM_IEEE_OUI;
3631}
3632
832d4f2f
SS		 3633static bool cea_db_is_y420cmdb(const u8 *db)
3634{
3635 if (cea_db_tag(db) != USE_EXTENDED_TAG)
3636 return false;
3637
3638 if (!cea_db_payload_len(db))
3639 return false;
3640
3641 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB)
3642 return false;
3643
3644 return true;
3645}
3646
3647static bool cea_db_is_y420vdb(const u8 *db)
3648{
3649 if (cea_db_tag(db) != USE_EXTENDED_TAG)
3650 return false;
3651
3652 if (!cea_db_payload_len(db))
3653 return false;
3654
3655 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420)
3656 return false;
3657
3658 return true;
3659}
3660
9e50b9d5
VS		 3661#define for_each_cea_db(cea, i, start, end) \
3662 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
3663
832d4f2f
SS		 3664static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector,
3665 const u8 *db)
3666{
3667 struct drm_display_info *info = &connector->display_info;
3668 struct drm_hdmi_info *hdmi = &info->hdmi;
3669 u8 map_len = cea_db_payload_len(db) - 1;
3670 u8 count;
3671 u64 map = 0;
3672
3673 if (map_len == 0) {
3674 /* All CEA modes support ycbcr420 sampling also.*/
3675 hdmi->y420_cmdb_map = U64_MAX;
3676 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3677 return;
3678 }
3679
3680 /*
3681 * This map indicates which of the existing CEA block modes
3682 * from VDB can support YCBCR420 output too. So if bit=0 is
3683 * set, first mode from VDB can support YCBCR420 output too.
3684 * We will parse and keep this map, before parsing VDB itself
3685 * to avoid going through the same block again and again.
3686 *
3687 * Spec is not clear about max possible size of this block.
3688 * Clamping max bitmap block size at 8 bytes. Every byte can
3689 * address 8 CEA modes, in this way this map can address
3690 * 8*8 = first 64 SVDs.
3691 */
3692 if (WARN_ON_ONCE(map_len > 8))
3693 map_len = 8;
3694
3695 for (count = 0; count < map_len; count++)
3696 map |= (u64)db[2 + count] << (8 * count);
3697
3698 if (map)
3699 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3700
3701 hdmi->y420_cmdb_map = map;
3702}
3703
54ac76f8
CS		 3704static int
3705add_cea_modes(struct drm_connector *connector, struct edid *edid)
3706{
13ac3f55 3707 const u8 *cea = drm_find_cea_extension(edid);
fbf46025
TW		 3708 const u8 *db, *hdmi = NULL, *video = NULL;
3709 u8 dbl, hdmi_len, video_len = 0;
54ac76f8
CS		 3710 int modes = 0;
3711
9e50b9d5
VS		 3712 if (cea && cea_revision(cea) >= 3) {
3713 int i, start, end;
3714
3715 if (cea_db_offsets(cea, &start, &end))
3716 return 0;
3717
3718 for_each_cea_db(cea, i, start, end) {
3719 db = &cea[i];
3720 dbl = cea_db_payload_len(db);
3721
fbf46025
TW		 3722 if (cea_db_tag(db) == VIDEO_BLOCK) {
3723 video = db + 1;
3724 video_len = dbl;
3725 modes += do_cea_modes(connector, video, dbl);
832d4f2f 3726 } else if (cea_db_is_hdmi_vsdb(db)) {
c858cfca
DL		 3727 hdmi = db;
3728 hdmi_len = dbl;
832d4f2f
SS		 3729 } else if (cea_db_is_y420vdb(db)) {
3730 const u8 *vdb420 = &db[2];
3731
3732 /* Add 4:2:0(only) modes present in EDID */
3733 modes += do_y420vdb_modes(connector,
3734 vdb420,
3735 dbl - 1);
c858cfca 3736 }
54ac76f8
CS		 3737 }
3738 }
3739
c858cfca
DL		 3740 /*
3741 * We parse the HDMI VSDB after having added the cea modes as we will
3742 * be patching their flags when the sink supports stereo 3D.
3743 */
3744 if (hdmi)
fbf46025
TW		 3745 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
3746 video_len);
c858cfca 3747
54ac76f8
CS		 3748 return modes;
3749}
3750
fa3a7340
VS		 3751static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
3752{
3753 const struct drm_display_mode *cea_mode;
3754 int clock1, clock2, clock;
d9278b4c 3755 u8 vic;
fa3a7340
VS		 3756 const char *type;
3757
4c6bcf44
VS		 3758 /*
3759 * allow 5kHz clock difference either way to account for
3760 * the 10kHz clock resolution limit of detailed timings.
3761 */
d9278b4c
JN		 3762 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
3763 if (drm_valid_cea_vic(vic)) {
fa3a7340 3764 type = "CEA";
d9278b4c 3765 cea_mode = &edid_cea_modes[vic];
fa3a7340
VS		 3766 clock1 = cea_mode->clock;
3767 clock2 = cea_mode_alternate_clock(cea_mode);
3768 } else {
d9278b4c
JN		 3769 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
3770 if (drm_valid_hdmi_vic(vic)) {
fa3a7340 3771 type = "HDMI";
d9278b4c 3772 cea_mode = &edid_4k_modes[vic];
fa3a7340
VS		 3773 clock1 = cea_mode->clock;
3774 clock2 = hdmi_mode_alternate_clock(cea_mode);
3775 } else {
3776 return;
3777 }
3778 }
3779
3780 /* pick whichever is closest */
3781 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
3782 clock = clock1;
3783 else
3784 clock = clock2;
3785
3786 if (mode->clock == clock)
3787 return;
3788
3789 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
d9278b4c 3790 type, vic, mode->clock, clock);
fa3a7340
VS		 3791 mode->clock = clock;
3792}
3793
76adaa34 3794static void
23ebf8b9 3795drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
76adaa34 3796{
8504072a 3797 u8 len = cea_db_payload_len(db);
76adaa34 3798
f7da7785
JN		 3799 if (len >= 6 && (db[6] & (1 << 7)))
3800 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
8504072a
VS		 3801 if (len >= 8) {
3802 connector->latency_present[0] = db[8] >> 7;
3803 connector->latency_present[1] = (db[8] >> 6) & 1;
3804 }
3805 if (len >= 9)
3806 connector->video_latency[0] = db[9];
3807 if (len >= 10)
3808 connector->audio_latency[0] = db[10];
3809 if (len >= 11)
3810 connector->video_latency[1] = db[11];
3811 if (len >= 12)
3812 connector->audio_latency[1] = db[12];
76adaa34 3813
23ebf8b9
VS		 3814 DRM_DEBUG_KMS("HDMI: latency present %d %d, "
3815 "video latency %d %d, "
3816 "audio latency %d %d\n",
3817 connector->latency_present[0],
3818 connector->latency_present[1],
3819 connector->video_latency[0],
3820 connector->video_latency[1],
3821 connector->audio_latency[0],
3822 connector->audio_latency[1]);
76adaa34
WF		 3823}
3824
3825static void
3826monitor_name(struct detailed_timing *t, void *data)
3827{
3828 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME)
3829 *(u8 **)data = t->data.other_data.data.str.str;
14f77fdd
VS		 3830}
3831
59f7c0fa
JB		 3832static int get_monitor_name(struct edid *edid, char name[13])
3833{
3834 char *edid_name = NULL;
3835 int mnl;
3836
3837 if (!edid || !name)
3838 return 0;
3839
3840 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name);
3841 for (mnl = 0; edid_name && mnl < 13; mnl++) {
3842 if (edid_name[mnl] == 0x0a)
3843 break;
3844
3845 name[mnl] = edid_name[mnl];
3846 }
3847
3848 return mnl;
3849}
3850
3851/**
3852 * drm_edid_get_monitor_name - fetch the monitor name from the edid
3853 * @edid: monitor EDID information
3854 * @name: pointer to a character array to hold the name of the monitor
3855 * @bufsize: The size of the name buffer (should be at least 14 chars.)
3856 *
3857 */
3858void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize)
3859{
3860 int name_length;
3861 char buf[13];
3862
3863 if (bufsize <= 0)
3864 return;
3865
3866 name_length = min(get_monitor_name(edid, buf), bufsize - 1);
3867 memcpy(name, buf, name_length);
3868 name[name_length] = '\0';
3869}
3870EXPORT_SYMBOL(drm_edid_get_monitor_name);
3871
42750d39
JN		 3872static void clear_eld(struct drm_connector *connector)
3873{
3874 memset(connector->eld, 0, sizeof(connector->eld));
3875
3876 connector->latency_present[0] = false;
3877 connector->latency_present[1] = false;
3878 connector->video_latency[0] = 0;
3879 connector->audio_latency[0] = 0;
3880 connector->video_latency[1] = 0;
3881 connector->audio_latency[1] = 0;
3882}
3883
79436a1c 3884/*
76adaa34
WF		 3885 * drm_edid_to_eld - build ELD from EDID
3886 * @connector: connector corresponding to the HDMI/DP sink
3887 * @edid: EDID to parse
3888 *
db6cf833 3889 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
1d1c3665 3890 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
76adaa34 3891 */
79436a1c 3892static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
76adaa34
WF		 3893{
3894 uint8_t *eld = connector->eld;
3895 u8 *cea;
76adaa34 3896 u8 *db;
7c018782 3897 int total_sad_count = 0;
76adaa34
WF		 3898 int mnl;
3899 int dbl;
3900
42750d39 3901 clear_eld(connector);
85c91580 3902
e9bd0b84
JN		 3903 if (!edid)
3904 return;
3905
76adaa34
WF		 3906 cea = drm_find_cea_extension(edid);
3907 if (!cea) {
3908 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
3909 return;
3910 }
3911
f7da7785
JN		 3912 mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
3913 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]);
59f7c0fa 3914
f7da7785
JN		 3915 eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT;
3916 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
76adaa34 3917
f7da7785 3918 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
76adaa34 3919
f7da7785
JN		 3920 eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0];
3921 eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1];
3922 eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0];
3923 eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1];
76adaa34 3924
9e50b9d5
VS		 3925 if (cea_revision(cea) >= 3) {
3926 int i, start, end;
3927
3928 if (cea_db_offsets(cea, &start, &end)) {
3929 start = 0;
3930 end = 0;
3931 }
3932
3933 for_each_cea_db(cea, i, start, end) {
3934 db = &cea[i];
3935 dbl = cea_db_payload_len(db);
3936
3937 switch (cea_db_tag(db)) {
7c018782
VS		 3938 int sad_count;
3939
a0ab734d
CS		 3940 case AUDIO_BLOCK:
3941 /* Audio Data Block, contains SADs */
7c018782
VS		 3942 sad_count = min(dbl / 3, 15 - total_sad_count);
3943 if (sad_count >= 1)
f7da7785 3944 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
7c018782
VS		 3945 &db[1], sad_count * 3);
3946 total_sad_count += sad_count;
a0ab734d
CS		 3947 break;
3948 case SPEAKER_BLOCK:
9e50b9d5
VS		 3949 /* Speaker Allocation Data Block */
3950 if (dbl >= 1)
f7da7785 3951 eld[DRM_ELD_SPEAKER] = db[1];
a0ab734d
CS		 3952 break;
3953 case VENDOR_BLOCK:
3954 /* HDMI Vendor-Specific Data Block */
14f77fdd 3955 if (cea_db_is_hdmi_vsdb(db))
23ebf8b9 3956 drm_parse_hdmi_vsdb_audio(connector, db);
a0ab734d
CS		 3957 break;
3958 default:
3959 break;
3960 }
76adaa34 3961 }
9e50b9d5 3962 }
f7da7785 3963 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
76adaa34 3964
1d1c3665
JN		 3965 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
3966 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3967 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
3968 else
3969 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
76adaa34 3970
938fd8aa
JN		 3971 eld[DRM_ELD_BASELINE_ELD_LEN] =
3972 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
3973
3974 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
7c018782 3975 drm_eld_size(eld), total_sad_count);
76adaa34 3976}
76adaa34 3977
fe214163
RM		 3978/**
3979 * drm_edid_to_sad - extracts SADs from EDID
3980 * @edid: EDID to parse
3981 * @sads: pointer that will be set to the extracted SADs
3982 *
3983 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
fe214163 3984 *
db6cf833
TR		 3985 * Note: The returned pointer needs to be freed using kfree().
3986 *
3987 * Return: The number of found SADs or negative number on error.
fe214163
RM		 3988 */
3989int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
3990{
3991 int count = 0;
3992 int i, start, end, dbl;
3993 u8 *cea;
3994
3995 cea = drm_find_cea_extension(edid);
3996 if (!cea) {
3997 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
3998 return -ENOENT;
3999 }
4000
4001 if (cea_revision(cea) < 3) {
4002 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4003 return -ENOTSUPP;
4004 }
4005
4006 if (cea_db_offsets(cea, &start, &end)) {
4007 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4008 return -EPROTO;
4009 }
4010
4011 for_each_cea_db(cea, i, start, end) {
4012 u8 *db = &cea[i];
4013
4014 if (cea_db_tag(db) == AUDIO_BLOCK) {
4015 int j;
4016 dbl = cea_db_payload_len(db);
4017
4018 count = dbl / 3; /* SAD is 3B */
4019 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
4020 if (!*sads)
4021 return -ENOMEM;
4022 for (j = 0; j < count; j++) {
4023 u8 *sad = &db[1 + j * 3];
4024
4025 (*sads)[j].format = (sad[0] & 0x78) >> 3;
4026 (*sads)[j].channels = sad[0] & 0x7;
4027 (*sads)[j].freq = sad[1] & 0x7F;
4028 (*sads)[j].byte2 = sad[2];
4029 }
4030 break;
4031 }
4032 }
4033
4034 return count;
4035}
4036EXPORT_SYMBOL(drm_edid_to_sad);
4037
d105f476
AD		 4038/**
4039 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
4040 * @edid: EDID to parse
4041 * @sadb: pointer to the speaker block
4042 *
4043 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
d105f476 4044 *
db6cf833
TR		 4045 * Note: The returned pointer needs to be freed using kfree().
4046 *
4047 * Return: The number of found Speaker Allocation Blocks or negative number on
4048 * error.
d105f476
AD		 4049 */
4050int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
4051{
4052 int count = 0;
4053 int i, start, end, dbl;
4054 const u8 *cea;
4055
4056 cea = drm_find_cea_extension(edid);
4057 if (!cea) {
4058 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4059 return -ENOENT;
4060 }
4061
4062 if (cea_revision(cea) < 3) {
4063 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4064 return -ENOTSUPP;
4065 }
4066
4067 if (cea_db_offsets(cea, &start, &end)) {
4068 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4069 return -EPROTO;
4070 }
4071
4072 for_each_cea_db(cea, i, start, end) {
4073 const u8 *db = &cea[i];
4074
4075 if (cea_db_tag(db) == SPEAKER_BLOCK) {
4076 dbl = cea_db_payload_len(db);
4077
4078 /* Speaker Allocation Data Block */
4079 if (dbl == 3) {
89086bca 4080 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
618e3776
AD		 4081 if (!*sadb)
4082 return -ENOMEM;
d105f476
AD		 4083 count = dbl;
4084 break;
4085 }
4086 }
4087 }
4088
4089 return count;
4090}
4091EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
4092
76adaa34 4093/**
db6cf833 4094 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
76adaa34
WF		 4095 * @connector: connector associated with the HDMI/DP sink
4096 * @mode: the display mode
db6cf833
TR		 4097 *
4098 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
4099 * the sink doesn't support audio or video.
76adaa34
WF		 4100 */
4101int drm_av_sync_delay(struct drm_connector *connector,
3a818d35 4102 const struct drm_display_mode *mode)
76adaa34
WF		 4103{
4104 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
4105 int a, v;
4106
4107 if (!connector->latency_present[0])
4108 return 0;
4109 if (!connector->latency_present[1])
4110 i = 0;
4111
4112 a = connector->audio_latency[i];
4113 v = connector->video_latency[i];
4114
4115 /*
4116 * HDMI/DP sink doesn't support audio or video?
4117 */
4118 if (a == 255 || v == 255)
4119 return 0;
4120
4121 /*
4122 * Convert raw EDID values to millisecond.
4123 * Treat unknown latency as 0ms.
4124 */
4125 if (a)
4126 a = min(2 * (a - 1), 500);
4127 if (v)
4128 v = min(2 * (v - 1), 500);
4129
4130 return max(v - a, 0);
4131}
4132EXPORT_SYMBOL(drm_av_sync_delay);
4133
8fe9790d 4134/**
db6cf833 4135 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
8fe9790d
ZW		 4136 * @edid: monitor EDID information
4137 *
4138 * Parse the CEA extension according to CEA-861-B.
db6cf833
TR		 4139 *
4140 * Return: True if the monitor is HDMI, false if not or unknown.
8fe9790d
ZW		 4141 */
4142bool drm_detect_hdmi_monitor(struct edid *edid)
4143{
4144 u8 *edid_ext;
14f77fdd 4145 int i;
8fe9790d 4146 int start_offset, end_offset;
8fe9790d
ZW		 4147
4148 edid_ext = drm_find_cea_extension(edid);
4149 if (!edid_ext)
14f77fdd 4150 return false;
f23c20c8 4151
9e50b9d5 4152 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
14f77fdd 4153 return false;
f23c20c8
ML		 4154
4155 /*
4156 * Because HDMI identifier is in Vendor Specific Block,
4157 * search it from all data blocks of CEA extension.
4158 */
9e50b9d5 4159 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
14f77fdd
VS		 4160 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
4161 return true;
f23c20c8
ML		 4162 }
4163
14f77fdd 4164 return false;
f23c20c8
ML		 4165}
4166EXPORT_SYMBOL(drm_detect_hdmi_monitor);
4167
8fe9790d
ZW		 4168/**
4169 * drm_detect_monitor_audio - check monitor audio capability
fc66811c 4170 * @edid: EDID block to scan
8fe9790d
ZW		 4171 *
4172 * Monitor should have CEA extension block.
4173 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
4174 * audio' only. If there is any audio extension block and supported
4175 * audio format, assume at least 'basic audio' support, even if 'basic
4176 * audio' is not defined in EDID.
4177 *
db6cf833 4178 * Return: True if the monitor supports audio, false otherwise.
8fe9790d
ZW		 4179 */
4180bool drm_detect_monitor_audio(struct edid *edid)
4181{
4182 u8 *edid_ext;
4183 int i, j;
4184 bool has_audio = false;
4185 int start_offset, end_offset;
4186
4187 edid_ext = drm_find_cea_extension(edid);
4188 if (!edid_ext)
4189 goto end;
4190
4191 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
4192
4193 if (has_audio) {
4194 DRM_DEBUG_KMS("Monitor has basic audio support\n");
4195 goto end;
4196 }
4197
9e50b9d5
VS		 4198 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4199 goto end;
8fe9790d 4200
9e50b9d5
VS		 4201 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4202 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
8fe9790d 4203 has_audio = true;
9e50b9d5 4204 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
8fe9790d
ZW		 4205 DRM_DEBUG_KMS("CEA audio format %d\n",
4206 (edid_ext[i + j] >> 3) & 0xf);
4207 goto end;
4208 }
4209 }
4210end:
4211 return has_audio;
4212}
4213EXPORT_SYMBOL(drm_detect_monitor_audio);
4214
b1edd6a6
VS		 4215/**
4216 * drm_rgb_quant_range_selectable - is RGB quantization range selectable?
fc66811c 4217 * @edid: EDID block to scan
b1edd6a6
VS		 4218 *
4219 * Check whether the monitor reports the RGB quantization range selection
4220 * as supported. The AVI infoframe can then be used to inform the monitor
4221 * which quantization range (full or limited) is used.
db6cf833
TR		 4222 *
4223 * Return: True if the RGB quantization range is selectable, false otherwise.
b1edd6a6
VS		 4224 */
4225bool drm_rgb_quant_range_selectable(struct edid *edid)
4226{
4227 u8 *edid_ext;
4228 int i, start, end;
4229
4230 edid_ext = drm_find_cea_extension(edid);
4231 if (!edid_ext)
4232 return false;
4233
4234 if (cea_db_offsets(edid_ext, &start, &end))
4235 return false;
4236
4237 for_each_cea_db(edid_ext, i, start, end) {
87563fc0
SS		 4238 if (cea_db_tag(&edid_ext[i]) == USE_EXTENDED_TAG &&
4239 cea_db_payload_len(&edid_ext[i]) == 2 &&
4240 cea_db_extended_tag(&edid_ext[i]) ==
4241 EXT_VIDEO_CAPABILITY_BLOCK) {
b1edd6a6
VS		 4242 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]);
4243 return edid_ext[i + 2] & EDID_CEA_VCDB_QS;
4244 }
4245 }
4246
4247 return false;
4248}
4249EXPORT_SYMBOL(drm_rgb_quant_range_selectable);
4250
c8127cf0
VS		 4251/**
4252 * drm_default_rgb_quant_range - default RGB quantization range
4253 * @mode: display mode
4254 *
4255 * Determine the default RGB quantization range for the mode,
4256 * as specified in CEA-861.
4257 *
4258 * Return: The default RGB quantization range for the mode
4259 */
4260enum hdmi_quantization_range
4261drm_default_rgb_quant_range(const struct drm_display_mode *mode)
4262{
4263 /* All CEA modes other than VIC 1 use limited quantization range. */
4264 return drm_match_cea_mode(mode) > 1 ?
4265 HDMI_QUANTIZATION_RANGE_LIMITED :
4266 HDMI_QUANTIZATION_RANGE_FULL;
4267}
4268EXPORT_SYMBOL(drm_default_rgb_quant_range);
4269
e6a9a2c3
SS		 4270static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
4271 const u8 *db)
4272{
4273 u8 dc_mask;
4274 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4275
4276 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
4277 hdmi->y420_dc_modes |= dc_mask;
4278}
4279
afa1c763
SS		 4280static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector,
4281 const u8 *hf_vsdb)
4282{
62c58af3
SS		 4283 struct drm_display_info *display = &connector->display_info;
4284 struct drm_hdmi_info *hdmi = &display->hdmi;
afa1c763 4285
f1781e9b
VS		 4286 display->has_hdmi_infoframe = true;
4287
afa1c763
SS		 4288 if (hf_vsdb[6] & 0x80) {
4289 hdmi->scdc.supported = true;
4290 if (hf_vsdb[6] & 0x40)
4291 hdmi->scdc.read_request = true;
4292 }
62c58af3
SS		 4293
4294 /*
4295 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
4296 * And as per the spec, three factors confirm this:
4297 * * Availability of a HF-VSDB block in EDID (check)
4298 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
4299 * * SCDC support available (let's check)
4300 * Lets check it out.
4301 */
4302
4303 if (hf_vsdb[5]) {
4304 /* max clock is 5000 KHz times block value */
4305 u32 max_tmds_clock = hf_vsdb[5] * 5000;
4306 struct drm_scdc *scdc = &hdmi->scdc;
4307
4308 if (max_tmds_clock > 340000) {
4309 display->max_tmds_clock = max_tmds_clock;
4310 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
4311 display->max_tmds_clock);
4312 }
4313
4314 if (scdc->supported) {
4315 scdc->scrambling.supported = true;
4316
4317 /* Few sinks support scrambling for cloks < 340M */
4318 if ((hf_vsdb[6] & 0x8))
4319 scdc->scrambling.low_rates = true;
4320 }
4321 }
e6a9a2c3
SS		 4322
4323 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb);
afa1c763
SS		 4324}
4325
1cea146a
VS		 4326static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
4327 const u8 *hdmi)
d0c94692 4328{
1826750f 4329 struct drm_display_info *info = &connector->display_info;
d0c94692
MK		 4330 unsigned int dc_bpc = 0;
4331
1cea146a
VS		 4332 /* HDMI supports at least 8 bpc */
4333 info->bpc = 8;
d0c94692 4334
1cea146a
VS		 4335 if (cea_db_payload_len(hdmi) < 6)
4336 return;
4337
4338 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
4339 dc_bpc = 10;
4340 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
4341 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
4342 connector->name);
4343 }
4344
4345 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
4346 dc_bpc = 12;
4347 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
4348 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
4349 connector->name);
4350 }
4351
4352 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
4353 dc_bpc = 16;
4354 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
4355 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
4356 connector->name);
4357 }
4358
4359 if (dc_bpc == 0) {
4360 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
4361 connector->name);
4362 return;
4363 }
4364
4365 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
4366 connector->name, dc_bpc);
4367 info->bpc = dc_bpc;
d0c94692
MK		 4368
4369 /*
1cea146a
VS		 4370 * Deep color support mandates RGB444 support for all video
4371 * modes and forbids YCRCB422 support for all video modes per
4372 * HDMI 1.3 spec.
d0c94692 4373 */
1cea146a 4374 info->color_formats = DRM_COLOR_FORMAT_RGB444;
d0c94692 4375
1cea146a
VS		 4376 /* YCRCB444 is optional according to spec. */
4377 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
4378 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4379 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
4380 connector->name);
4381 }
d0c94692 4382
1cea146a
VS		 4383 /*
4384 * Spec says that if any deep color mode is supported at all,
4385 * then deep color 36 bit must be supported.
4386 */
4387 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
4388 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
4389 connector->name);
4390 }
4391}
d0c94692 4392
23ebf8b9
VS		 4393static void
4394drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
4395{
4396 struct drm_display_info *info = &connector->display_info;
4397 u8 len = cea_db_payload_len(db);
4398
4399 if (len >= 6)
4400 info->dvi_dual = db[6] & 1;
4401 if (len >= 7)
4402 info->max_tmds_clock = db[7] * 5000;
4403
4404 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
4405 "max TMDS clock %d kHz\n",
4406 info->dvi_dual,
4407 info->max_tmds_clock);
4408
4409 drm_parse_hdmi_deep_color_info(connector, db);
4410}
4411
1cea146a 4412static void drm_parse_cea_ext(struct drm_connector *connector,
170178fe 4413 const struct edid *edid)
1cea146a
VS		 4414{
4415 struct drm_display_info *info = &connector->display_info;
4416 const u8 *edid_ext;
4417 int i, start, end;
d0c94692 4418
1cea146a
VS		 4419 edid_ext = drm_find_cea_extension(edid);
4420 if (!edid_ext)
4421 return;
d0c94692 4422
1cea146a 4423 info->cea_rev = edid_ext[1];
d0c94692 4424
1cea146a
VS		 4425 /* The existence of a CEA block should imply RGB support */
4426 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4427 if (edid_ext[3] & EDID_CEA_YCRCB444)
4428 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4429 if (edid_ext[3] & EDID_CEA_YCRCB422)
4430 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4431
4432 if (cea_db_offsets(edid_ext, &start, &end))
4433 return;
4434
4435 for_each_cea_db(edid_ext, i, start, end) {
4436 const u8 *db = &edid_ext[i];
4437
23ebf8b9
VS		 4438 if (cea_db_is_hdmi_vsdb(db))
4439 drm_parse_hdmi_vsdb_video(connector, db);
afa1c763
SS		 4440 if (cea_db_is_hdmi_forum_vsdb(db))
4441 drm_parse_hdmi_forum_vsdb(connector, db);
832d4f2f
SS		 4442 if (cea_db_is_y420cmdb(db))
4443 drm_parse_y420cmdb_bitmap(connector, db);
1cea146a 4444 }
d0c94692
MK		 4445}
4446
170178fe
KP		 4447/* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
4448 * all of the values which would have been set from EDID
4449 */
4450void
4451drm_reset_display_info(struct drm_connector *connector)
4452{
4453 struct drm_display_info *info = &connector->display_info;
4454
4455 info->width_mm = 0;
4456 info->height_mm = 0;
4457
4458 info->bpc = 0;
4459 info->color_formats = 0;
4460 info->cea_rev = 0;
4461 info->max_tmds_clock = 0;
4462 info->dvi_dual = false;
4463 info->has_hdmi_infoframe = false;
1f6b8eef 4464 memset(&info->hdmi, 0, sizeof(info->hdmi));
170178fe
KP		 4465
4466 info->non_desktop = 0;
4467}
170178fe
KP		 4468
4469u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid)
3b11228b 4470{
1826750f 4471 struct drm_display_info *info = &connector->display_info;
ebec9a7b 4472
170178fe
KP		 4473 u32 quirks = edid_get_quirks(edid);
4474
1f6b8eef
VS		 4475 drm_reset_display_info(connector);
4476
3b11228b
JB		 4477 info->width_mm = edid->width_cm * 10;
4478 info->height_mm = edid->height_cm * 10;
4479
66660d4c
DA		 4480 info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP);
4481
170178fe
KP		 4482 DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop);
4483
a988bc72 4484 if (edid->revision < 3)
170178fe 4485 return quirks;
3b11228b
JB		 4486
4487 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
170178fe 4488 return quirks;
3b11228b 4489
1cea146a 4490 drm_parse_cea_ext(connector, edid);
d0c94692 4491
210a021d
MK		 4492 /*
4493 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
4494 *
4495 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
4496 * tells us to assume 8 bpc color depth if the EDID doesn't have
4497 * extensions which tell otherwise.
4498 */
4499 if ((info->bpc == 0) && (edid->revision < 4) &&
4500 (edid->input & DRM_EDID_DIGITAL_TYPE_DVI)) {
4501 info->bpc = 8;
4502 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
4503 connector->name, info->bpc);
4504 }
4505
a988bc72
LPC		 4506 /* Only defined for 1.4 with digital displays */
4507 if (edid->revision < 4)
170178fe 4508 return quirks;
a988bc72 4509
3b11228b
JB		 4510 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
4511 case DRM_EDID_DIGITAL_DEPTH_6:
4512 info->bpc = 6;
4513 break;
4514 case DRM_EDID_DIGITAL_DEPTH_8:
4515 info->bpc = 8;
4516 break;
4517 case DRM_EDID_DIGITAL_DEPTH_10:
4518 info->bpc = 10;
4519 break;
4520 case DRM_EDID_DIGITAL_DEPTH_12:
4521 info->bpc = 12;
4522 break;
4523 case DRM_EDID_DIGITAL_DEPTH_14:
4524 info->bpc = 14;
4525 break;
4526 case DRM_EDID_DIGITAL_DEPTH_16:
4527 info->bpc = 16;
4528 break;
4529 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
4530 default:
4531 info->bpc = 0;
4532 break;
4533 }
da05a5a7 4534
d0c94692 4535 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
25933820 4536 connector->name, info->bpc);
d0c94692 4537
a988bc72 4538 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
ee58808d
LPC		 4539 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
4540 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4541 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
4542 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
170178fe 4543 return quirks;
3b11228b
JB		 4544}
4545
c9729177
DA		 4546static int validate_displayid(u8 *displayid, int length, int idx)
4547{
4548 int i;
4549 u8 csum = 0;
4550 struct displayid_hdr *base;
4551
4552 base = (struct displayid_hdr *)&displayid[idx];
4553
4554 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",
4555 base->rev, base->bytes, base->prod_id, base->ext_count);
4556
4557 if (base->bytes + 5 > length - idx)
4558 return -EINVAL;
4559 for (i = idx; i <= base->bytes + 5; i++) {
4560 csum += displayid[i];
4561 }
4562 if (csum) {
813a7878 4563 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum);
c9729177
DA		 4564 return -EINVAL;
4565 }
4566 return 0;
4567}
4568
a39ed680
DA		 4569static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
4570 struct displayid_detailed_timings_1 *timings)
4571{
4572 struct drm_display_mode *mode;
4573 unsigned pixel_clock = (timings->pixel_clock[0] |
4574 (timings->pixel_clock[1] << 8) |
4575 (timings->pixel_clock[2] << 16));
4576 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
4577 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
4578 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
4579 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
4580 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
4581 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
4582 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
4583 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
4584 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
4585 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
4586 mode = drm_mode_create(dev);
4587 if (!mode)
4588 return NULL;
4589
4590 mode->clock = pixel_clock * 10;
4591 mode->hdisplay = hactive;
4592 mode->hsync_start = mode->hdisplay + hsync;
4593 mode->hsync_end = mode->hsync_start + hsync_width;
4594 mode->htotal = mode->hdisplay + hblank;
4595
4596 mode->vdisplay = vactive;
4597 mode->vsync_start = mode->vdisplay + vsync;
4598 mode->vsync_end = mode->vsync_start + vsync_width;
4599 mode->vtotal = mode->vdisplay + vblank;
4600
4601 mode->flags = 0;
4602 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
4603 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
4604 mode->type = DRM_MODE_TYPE_DRIVER;
4605
4606 if (timings->flags & 0x80)
4607 mode->type |= DRM_MODE_TYPE_PREFERRED;
4608 mode->vrefresh = drm_mode_vrefresh(mode);
4609 drm_mode_set_name(mode);
4610
4611 return mode;
4612}
4613
4614static int add_displayid_detailed_1_modes(struct drm_connector *connector,
4615 struct displayid_block *block)
4616{
4617 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
4618 int i;
4619 int num_timings;
4620 struct drm_display_mode *newmode;
4621 int num_modes = 0;
4622 /* blocks must be multiple of 20 bytes length */
4623 if (block->num_bytes % 20)
4624 return 0;
4625
4626 num_timings = block->num_bytes / 20;
4627 for (i = 0; i < num_timings; i++) {
4628 struct displayid_detailed_timings_1 *timings = &det->timings[i];
4629
4630 newmode = drm_mode_displayid_detailed(connector->dev, timings);
4631 if (!newmode)
4632 continue;
4633
4634 drm_mode_probed_add(connector, newmode);
4635 num_modes++;
4636 }
4637 return num_modes;
4638}
4639
4640static int add_displayid_detailed_modes(struct drm_connector *connector,
4641 struct edid *edid)
4642{
4643 u8 *displayid;
4644 int ret;
4645 int idx = 1;
4646 int length = EDID_LENGTH;
4647 struct displayid_block *block;
4648 int num_modes = 0;
4649
4650 displayid = drm_find_displayid_extension(edid);
4651 if (!displayid)
4652 return 0;
4653
4654 ret = validate_displayid(displayid, length, idx);
4655 if (ret)
4656 return 0;
4657
4658 idx += sizeof(struct displayid_hdr);
4659 while (block = (struct displayid_block *)&displayid[idx],
4660 idx + sizeof(struct displayid_block) <= length &&
4661 idx + sizeof(struct displayid_block) + block->num_bytes <= length &&
4662 block->num_bytes > 0) {
4663 idx += block->num_bytes + sizeof(struct displayid_block);
4664 switch (block->tag) {
4665 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
4666 num_modes += add_displayid_detailed_1_modes(connector, block);
4667 break;
4668 }
4669 }
4670 return num_modes;
4671}
4672
f453ba04
DA		 4673/**
4674 * drm_add_edid_modes - add modes from EDID data, if available
4675 * @connector: connector we're probing
db6cf833 4676 * @edid: EDID data
f453ba04 4677 *
b3c6c8bf 4678 * Add the specified modes to the connector's mode list. Also fills out the
c945b8c1
JN		 4679 * &drm_display_info structure and ELD in @connector with any information which
4680 * can be derived from the edid.
f453ba04 4681 *
db6cf833 4682 * Return: The number of modes added or 0 if we couldn't find any.
f453ba04
DA		 4683 */
4684int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
4685{
4686 int num_modes = 0;
4687 u32 quirks;
4688
4689 if (edid == NULL) {
c945b8c1 4690 clear_eld(connector);
f453ba04
DA		 4691 return 0;
4692 }
3c537889 4693 if (!drm_edid_is_valid(edid)) {
c945b8c1 4694 clear_eld(connector);
dcdb1674 4695 dev_warn(connector->dev->dev, "%s: EDID invalid.\n",
25933820 4696 connector->name);
f453ba04
DA		 4697 return 0;
4698 }
4699
c945b8c1
JN		 4700 drm_edid_to_eld(connector, edid);
4701
0f0f8708
SS		 4702 /*
4703 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
4704 * To avoid multiple parsing of same block, lets parse that map
4705 * from sink info, before parsing CEA modes.
4706 */
170178fe 4707 quirks = drm_add_display_info(connector, edid);
0f0f8708 4708
c867df70
AJ		 4709 /*
4710 * EDID spec says modes should be preferred in this order:
4711 * - preferred detailed mode
4712 * - other detailed modes from base block
4713 * - detailed modes from extension blocks
4714 * - CVT 3-byte code modes
4715 * - standard timing codes
4716 * - established timing codes
4717 * - modes inferred from GTF or CVT range information
4718 *
13931579 4719 * We get this pretty much right.
c867df70
AJ		 4720 *
4721 * XXX order for additional mode types in extension blocks?
4722 */
13931579
AJ		 4723 num_modes += add_detailed_modes(connector, edid, quirks);
4724 num_modes += add_cvt_modes(connector, edid);
c867df70
AJ		 4725 num_modes += add_standard_modes(connector, edid);
4726 num_modes += add_established_modes(connector, edid);
54ac76f8 4727 num_modes += add_cea_modes(connector, edid);
e6e79209 4728 num_modes += add_alternate_cea_modes(connector, edid);
a39ed680 4729 num_modes += add_displayid_detailed_modes(connector, edid);
4d53dc0c
VS		 4730 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
4731 num_modes += add_inferred_modes(connector, edid);
f453ba04
DA		 4732
4733 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
4734 edid_fixup_preferred(connector, quirks);
4735
e10aec65
MK		 4736 if (quirks & EDID_QUIRK_FORCE_6BPC)
4737 connector->display_info.bpc = 6;
4738
49d45a31
RM		 4739 if (quirks & EDID_QUIRK_FORCE_8BPC)
4740 connector->display_info.bpc = 8;
4741
e345da82
MK		 4742 if (quirks & EDID_QUIRK_FORCE_10BPC)
4743 connector->display_info.bpc = 10;
4744
bc5b9641
MK		 4745 if (quirks & EDID_QUIRK_FORCE_12BPC)
4746 connector->display_info.bpc = 12;
4747
f453ba04
DA		 4748 return num_modes;
4749}
4750EXPORT_SYMBOL(drm_add_edid_modes);
f0fda0a4
ZY		 4751
4752/**
4753 * drm_add_modes_noedid - add modes for the connectors without EDID
4754 * @connector: connector we're probing
4755 * @hdisplay: the horizontal display limit
4756 * @vdisplay: the vertical display limit
4757 *
4758 * Add the specified modes to the connector's mode list. Only when the
4759 * hdisplay/vdisplay is not beyond the given limit, it will be added.
4760 *
db6cf833 4761 * Return: The number of modes added or 0 if we couldn't find any.
f0fda0a4
ZY		 4762 */
4763int drm_add_modes_noedid(struct drm_connector *connector,
4764 int hdisplay, int vdisplay)
4765{
4766 int i, count, num_modes = 0;
b1f559ec 4767 struct drm_display_mode *mode;
f0fda0a4
ZY		 4768 struct drm_device *dev = connector->dev;
4769
fbb40b28 4770 count = ARRAY_SIZE(drm_dmt_modes);
f0fda0a4
ZY		 4771 if (hdisplay < 0)
4772 hdisplay = 0;
4773 if (vdisplay < 0)
4774 vdisplay = 0;
4775
4776 for (i = 0; i < count; i++) {
b1f559ec 4777 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
f0fda0a4
ZY		 4778 if (hdisplay && vdisplay) {
4779 /*
4780 * Only when two are valid, they will be used to check
4781 * whether the mode should be added to the mode list of
4782 * the connector.
4783 */
4784 if (ptr->hdisplay > hdisplay ||
4785 ptr->vdisplay > vdisplay)
4786 continue;
4787 }
f985dedb
AJ		 4788 if (drm_mode_vrefresh(ptr) > 61)
4789 continue;
f0fda0a4
ZY		 4790 mode = drm_mode_duplicate(dev, ptr);
4791 if (mode) {
4792 drm_mode_probed_add(connector, mode);
4793 num_modes++;
4794 }
4795 }
4796 return num_modes;
4797}
4798EXPORT_SYMBOL(drm_add_modes_noedid);
10a85120 4799
db6cf833
TR		 4800/**
4801 * drm_set_preferred_mode - Sets the preferred mode of a connector
4802 * @connector: connector whose mode list should be processed
4803 * @hpref: horizontal resolution of preferred mode
4804 * @vpref: vertical resolution of preferred mode
4805 *
4806 * Marks a mode as preferred if it matches the resolution specified by @hpref
4807 * and @vpref.
4808 */
3cf70daf
GH		 4809void drm_set_preferred_mode(struct drm_connector *connector,
4810 int hpref, int vpref)
4811{
4812 struct drm_display_mode *mode;
4813
4814 list_for_each_entry(mode, &connector->probed_modes, head) {
db6cf833 4815 if (mode->hdisplay == hpref &&
9d3de138 4816 mode->vdisplay == vpref)
3cf70daf
GH		 4817 mode->type |= DRM_MODE_TYPE_PREFERRED;
4818 }
4819}
4820EXPORT_SYMBOL(drm_set_preferred_mode);
4821
10a85120
TR		 4822/**
4823 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
4824 * data from a DRM display mode
4825 * @frame: HDMI AVI infoframe
4826 * @mode: DRM display mode
0c1f528c 4827 * @is_hdmi2_sink: Sink is HDMI 2.0 compliant
10a85120 4828 *
db6cf833 4829 * Return: 0 on success or a negative error code on failure.
10a85120
TR		 4830 */
4831int
4832drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
0c1f528c
SS		 4833 const struct drm_display_mode *mode,
4834 bool is_hdmi2_sink)
10a85120 4835{
a9c266c2 4836 enum hdmi_picture_aspect picture_aspect;
10a85120
TR		 4837 int err;
4838
4839 if (!frame || !mode)
4840 return -EINVAL;
4841
4842 err = hdmi_avi_infoframe_init(frame);
4843 if (err < 0)
4844 return err;
4845
bf02db99
DL		 4846 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
4847 frame->pixel_repeat = 1;
4848
10a85120 4849 frame->video_code = drm_match_cea_mode(mode);
10a85120 4850
0c1f528c
SS		 4851 /*
4852 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
4853 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
4854 * have to make sure we dont break HDMI 1.4 sinks.
4855 */
4856 if (!is_hdmi2_sink && frame->video_code > 64)
4857 frame->video_code = 0;
4858
4859 /*
4860 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
4861 * we should send its VIC in vendor infoframes, else send the
4862 * VIC in AVI infoframes. Lets check if this mode is present in
4863 * HDMI 1.4b 4K modes
4864 */
4865 if (frame->video_code) {
4866 u8 vendor_if_vic = drm_match_hdmi_mode(mode);
4867 bool is_s3d = mode->flags & DRM_MODE_FLAG_3D_MASK;
4868
4869 if (drm_valid_hdmi_vic(vendor_if_vic) && !is_s3d)
4870 frame->video_code = 0;
4871 }
4872
10a85120 4873 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
0967e6a5 4874
50525c33
SL		 4875 /*
4876 * As some drivers don't support atomic, we can't use connector state.
4877 * So just initialize the frame with default values, just the same way
4878 * as it's done with other properties here.
4879 */
4880 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
4881 frame->itc = 0;
4882
69ab6d35
VK		 4883 /*
4884 * Populate picture aspect ratio from either
4885 * user input (if specified) or from the CEA mode list.
4886 */
a9c266c2
VS		 4887 picture_aspect = mode->picture_aspect_ratio;
4888 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE)
4889 picture_aspect = drm_get_cea_aspect_ratio(frame->video_code);
0967e6a5 4890
a9c266c2
VS		 4891 /*
4892 * The infoframe can't convey anything but none, 4:3
4893 * and 16:9, so if the user has asked for anything else
4894 * we can only satisfy it by specifying the right VIC.
4895 */
4896 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
4897 if (picture_aspect !=
4898 drm_get_cea_aspect_ratio(frame->video_code))
4899 return -EINVAL;
4900 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
4901 }
4902
4903 frame->picture_aspect = picture_aspect;
10a85120 4904 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
24d01805 4905 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
10a85120
TR		 4906
4907 return 0;
4908}
4909EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
83dd0008 4910
a2ce26f8
VS		 4911/**
4912 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
4913 * quantization range information
4914 * @frame: HDMI AVI infoframe
779c4c28 4915 * @mode: DRM display mode
a2ce26f8
VS		 4916 * @rgb_quant_range: RGB quantization range (Q)
4917 * @rgb_quant_range_selectable: Sink support selectable RGB quantization range (QS)
7cdeb37c
DV		 4918 * @is_hdmi2_sink: HDMI 2.0 sink, which has different default recommendations
4919 *
4920 * Note that @is_hdmi2_sink can be derived by looking at the
4921 * &drm_scdc.supported flag stored in &drm_hdmi_info.scdc,
4922 * &drm_display_info.hdmi, which can be found in &drm_connector.display_info.
a2ce26f8
VS		 4923 */
4924void
4925drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
779c4c28 4926 const struct drm_display_mode *mode,
a2ce26f8 4927 enum hdmi_quantization_range rgb_quant_range,
9271c0ca
VS		 4928 bool rgb_quant_range_selectable,
4929 bool is_hdmi2_sink)
a2ce26f8
VS		 4930{
4931 /*
4932 * CEA-861:
4933 * "A Source shall not send a non-zero Q value that does not correspond
4934 * to the default RGB Quantization Range for the transmitted Picture
4935 * unless the Sink indicates support for the Q bit in a Video
4936 * Capabilities Data Block."
779c4c28
VS		 4937 *
4938 * HDMI 2.0 recommends sending non-zero Q when it does match the
4939 * default RGB quantization range for the mode, even when QS=0.
a2ce26f8 4940 */
779c4c28
VS		 4941 if (rgb_quant_range_selectable ||
4942 rgb_quant_range == drm_default_rgb_quant_range(mode))
a2ce26f8
VS		 4943 frame->quantization_range = rgb_quant_range;
4944 else
4945 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
fcc8a22c
VS		 4946
4947 /*
4948 * CEA-861-F:
4949 * "When transmitting any RGB colorimetry, the Source should set the
4950 * YQ-field to match the RGB Quantization Range being transmitted
4951 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
4952 * set YQ=1) and the Sink shall ignore the YQ-field."
9271c0ca
VS		 4953 *
4954 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
4955 * by non-zero YQ when receiving RGB. There doesn't seem to be any
4956 * good way to tell which version of CEA-861 the sink supports, so
4957 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
4958 * on on CEA-861-F.
fcc8a22c 4959 */
9271c0ca
VS		 4960 if (!is_hdmi2_sink ||
4961 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
fcc8a22c
VS		 4962 frame->ycc_quantization_range =
4963 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
4964 else
4965 frame->ycc_quantization_range =
4966 HDMI_YCC_QUANTIZATION_RANGE_FULL;
a2ce26f8
VS		 4967}
4968EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
4969
4eed4a0a
DL		 4970static enum hdmi_3d_structure
4971s3d_structure_from_display_mode(const struct drm_display_mode *mode)
4972{
4973 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
4974
4975 switch (layout) {
4976 case DRM_MODE_FLAG_3D_FRAME_PACKING:
4977 return HDMI_3D_STRUCTURE_FRAME_PACKING;
4978 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
4979 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
4980 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
4981 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
4982 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
4983 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
4984 case DRM_MODE_FLAG_3D_L_DEPTH:
4985 return HDMI_3D_STRUCTURE_L_DEPTH;
4986 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
4987 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
4988 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
4989 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
4990 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
4991 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
4992 default:
4993 return HDMI_3D_STRUCTURE_INVALID;
4994 }
4995}
4996
83dd0008
LD		 4997/**
4998 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
4999 * data from a DRM display mode
5000 * @frame: HDMI vendor infoframe
f1781e9b 5001 * @connector: the connector
83dd0008
LD		 5002 * @mode: DRM display mode
5003 *
5004 * Note that there's is a need to send HDMI vendor infoframes only when using a
5005 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
5006 * function will return -EINVAL, error that can be safely ignored.
5007 *
db6cf833 5008 * Return: 0 on success or a negative error code on failure.
83dd0008
LD		 5009 */
5010int
5011drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
f1781e9b 5012 struct drm_connector *connector,
83dd0008
LD		 5013 const struct drm_display_mode *mode)
5014{
f1781e9b
VS		 5015 /*
5016 * FIXME: sil-sii8620 doesn't have a connector around when
5017 * we need one, so we have to be prepared for a NULL connector.
5018 */
5019 bool has_hdmi_infoframe = connector ?
5020 connector->display_info.has_hdmi_infoframe : false;
83dd0008 5021 int err;
4eed4a0a 5022 u32 s3d_flags;
83dd0008
LD		 5023 u8 vic;
5024
5025 if (!frame || !mode)
5026 return -EINVAL;
5027
f1781e9b
VS		 5028 if (!has_hdmi_infoframe)
5029 return -EINVAL;
5030
83dd0008 5031 vic = drm_match_hdmi_mode(mode);
4eed4a0a
DL		 5032 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK;
5033
f1781e9b
VS		 5034 /*
5035 * Even if it's not absolutely necessary to send the infoframe
5036 * (ie.vic==0 and s3d_struct==0) we will still send it if we
5037 * know that the sink can handle it. This is based on a
5038 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
5039 * have trouble realizing that they shuld switch from 3D to 2D
5040 * mode if the source simply stops sending the infoframe when
5041 * it wants to switch from 3D to 2D.
5042 */
4eed4a0a
DL		 5043
5044 if (vic && s3d_flags)
83dd0008
LD		 5045 return -EINVAL;
5046
5047 err = hdmi_vendor_infoframe_init(frame);
5048 if (err < 0)
5049 return err;
5050
f1781e9b
VS		 5051 frame->vic = vic;
5052 frame->s3d_struct = s3d_structure_from_display_mode(mode);
83dd0008
LD		 5053
5054 return 0;
5055}
5056EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
40d9b043 5057
5e546cd5
DA		 5058static int drm_parse_tiled_block(struct drm_connector *connector,
5059 struct displayid_block *block)
5060{
5061 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
5062 u16 w, h;
5063 u8 tile_v_loc, tile_h_loc;
5064 u8 num_v_tile, num_h_tile;
5065 struct drm_tile_group *tg;
5066
5067 w = tile->tile_size[0] | tile->tile_size[1] << 8;
5068 h = tile->tile_size[2] | tile->tile_size[3] << 8;
5069
5070 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
5071 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
5072 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
5073 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
5074
5075 connector->has_tile = true;
5076 if (tile->tile_cap & 0x80)
5077 connector->tile_is_single_monitor = true;
5078
5079 connector->num_h_tile = num_h_tile + 1;
5080 connector->num_v_tile = num_v_tile + 1;
5081 connector->tile_h_loc = tile_h_loc;
5082 connector->tile_v_loc = tile_v_loc;
5083 connector->tile_h_size = w + 1;
5084 connector->tile_v_size = h + 1;
5085
5086 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
5087 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
5088 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
5089 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
5090 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
5091
5092 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
5093 if (!tg) {
5094 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
5095 }
5096 if (!tg)
5097 return -ENOMEM;
5098
5099 if (connector->tile_group != tg) {
5100 /* if we haven't got a pointer,
5101 take the reference, drop ref to old tile group */
5102 if (connector->tile_group) {
5103 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5104 }
5105 connector->tile_group = tg;
5106 } else
5107 /* if same tile group, then release the ref we just took. */
5108 drm_mode_put_tile_group(connector->dev, tg);
5109 return 0;
5110}
5111
40d9b043
DA		 5112static int drm_parse_display_id(struct drm_connector *connector,
5113 u8 *displayid, int length,
5114 bool is_edid_extension)
5115{
5116 /* if this is an EDID extension the first byte will be 0x70 */
5117 int idx = 0;
40d9b043 5118 struct displayid_block *block;
5e546cd5 5119 int ret;
40d9b043
DA		 5120
5121 if (is_edid_extension)
5122 idx = 1;
5123
c9729177
DA		 5124 ret = validate_displayid(displayid, length, idx);
5125 if (ret)
5126 return ret;
40d9b043 5127
3a4a2ea3
TB		 5128 idx += sizeof(struct displayid_hdr);
5129 while (block = (struct displayid_block *)&displayid[idx],
5130 idx + sizeof(struct displayid_block) <= length &&
5131 idx + sizeof(struct displayid_block) + block->num_bytes <= length &&
5132 block->num_bytes > 0) {
5133 idx += block->num_bytes + sizeof(struct displayid_block);
5134 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n",
5135 block->tag, block->rev, block->num_bytes);
5136
5137 switch (block->tag) {
5138 case DATA_BLOCK_TILED_DISPLAY:
5139 ret = drm_parse_tiled_block(connector, block);
5140 if (ret)
5141 return ret;
5142 break;
a39ed680
DA		 5143 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
5144 /* handled in mode gathering code. */
5145 break;
3a4a2ea3
TB		 5146 default:
5147 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag);
5148 break;
5149 }
40d9b043
DA		 5150 }
5151 return 0;
5152}
5153
5154static void drm_get_displayid(struct drm_connector *connector,
5155 struct edid *edid)
5156{
5157 void *displayid = NULL;
5158 int ret;
5159 connector->has_tile = false;
5160 displayid = drm_find_displayid_extension(edid);
5161 if (!displayid) {
5162 /* drop reference to any tile group we had */
5163 goto out_drop_ref;
5164 }
5165
5166 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true);
5167 if (ret < 0)
5168 goto out_drop_ref;
5169 if (!connector->has_tile)
5170 goto out_drop_ref;
5171 return;
5172out_drop_ref:
5173 if (connector->tile_group) {
5174 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5175 connector->tile_group = NULL;
5176 }
5177 return;
5178}
Linux 6.x block layer and io_uring tree(s)