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fbcon: Fix delayed takeover locking
[linux-2.6-block.git] / drivers / gpu / drm / drm_edid.c
CommitLineData
f453ba04
DA		 1/*
2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
61e57a8d 5 * Copyright 2010 Red Hat, Inc.
f453ba04
DA		 6 *
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
8 * FB layer.
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 */
9c79edec 30
18a9cbbe 31#include <linux/bitfield.h>
10a85120 32#include <linux/hdmi.h>
f453ba04 33#include <linux/i2c.h>
9c79edec 34#include <linux/kernel.h>
47819ba2 35#include <linux/module.h>
36b73b05 36#include <linux/pci.h>
9c79edec 37#include <linux/slab.h>
5cb8eaa2 38#include <linux/vga_switcheroo.h>
9c79edec
JN		 39
40#include <drm/drm_displayid.h>
41#include <drm/drm_drv.h>
760285e7 42#include <drm/drm_edid.h>
9338203c 43#include <drm/drm_encoder.h>
9c79edec 44#include <drm/drm_print.h>
62c58af3 45#include <drm/drm_scdc_helper.h>
f453ba04 46
969218fe
TI		 47#include "drm_crtc_internal.h"
48
13931579
AJ		 49#define version_greater(edid, maj, min) \
50 (((edid)->version > (maj)) || \
51 ((edid)->version == (maj) && (edid)->revision > (min)))
f453ba04 52
37eab1fe
JN		 53static int oui(u8 first, u8 second, u8 third)
54{
55 return (first << 16) | (second << 8) | third;
56}
57
d1ff6409
AJ		 58#define EDID_EST_TIMINGS 16
59#define EDID_STD_TIMINGS 8
60#define EDID_DETAILED_TIMINGS 4
f453ba04
DA		 61
62/*
63 * EDID blocks out in the wild have a variety of bugs, try to collect
64 * them here (note that userspace may work around broken monitors first,
65 * but fixes should make their way here so that the kernel "just works"
66 * on as many displays as possible).
67 */
68
69/* First detailed mode wrong, use largest 60Hz mode */
70#define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
71/* Reported 135MHz pixel clock is too high, needs adjustment */
72#define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
73/* Prefer the largest mode at 75 Hz */
74#define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
75/* Detail timing is in cm not mm */
76#define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
77/* Detailed timing descriptors have bogus size values, so just take the
78 * maximum size and use that.
79 */
80#define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
f453ba04
DA		 81/* use +hsync +vsync for detailed mode */
82#define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
bc42aabc
AJ		 83/* Force reduced-blanking timings for detailed modes */
84#define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
49d45a31
RM		 85/* Force 8bpc */
86#define EDID_QUIRK_FORCE_8BPC (1 << 8)
bc5b9641
MK		 87/* Force 12bpc */
88#define EDID_QUIRK_FORCE_12BPC (1 << 9)
e10aec65
MK		 89/* Force 6bpc */
90#define EDID_QUIRK_FORCE_6BPC (1 << 10)
e345da82
MK		 91/* Force 10bpc */
92#define EDID_QUIRK_FORCE_10BPC (1 << 11)
66660d4c
DA		 93/* Non desktop display (i.e. HMD) */
94#define EDID_QUIRK_NON_DESKTOP (1 << 12)
3c537889 95
2869f599
PZ		 96#define MICROSOFT_IEEE_OUI 0xca125c
97
13931579
AJ		 98struct detailed_mode_closure {
99 struct drm_connector *connector;
c14e7241 100 const struct edid *edid;
13931579
AJ		 101 bool preferred;
102 u32 quirks;
103 int modes;
104};
f453ba04 105
5c61259e
ZY		 106#define LEVEL_DMT 0
107#define LEVEL_GTF 1
7a374350
AJ		 108#define LEVEL_GTF2 2
109#define LEVEL_CVT 3
5c61259e 110
7d1be0a0 111#define EDID_QUIRK(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _quirks) \
e8de4d55 112{ \
7d1be0a0
DA		 113 .panel_id = drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, \
114 product_id), \
e8de4d55
DA		 115 .quirks = _quirks \
116}
117
23c4cfbd 118static const struct edid_quirk {
e8de4d55 119 u32 panel_id;
f453ba04
DA		 120 u32 quirks;
121} edid_quirk_list[] = {
122 /* Acer AL1706 */
7d1be0a0 123 EDID_QUIRK('A', 'C', 'R', 44358, EDID_QUIRK_PREFER_LARGE_60),
f453ba04 124 /* Acer F51 */
7d1be0a0 125 EDID_QUIRK('A', 'P', 'I', 0x7602, EDID_QUIRK_PREFER_LARGE_60),
f453ba04 126
e10aec65 127 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
7d1be0a0 128 EDID_QUIRK('A', 'E', 'O', 0, EDID_QUIRK_FORCE_6BPC),
e10aec65 129
0711a43b 130 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
7d1be0a0 131 EDID_QUIRK('B', 'O', 'E', 0x78b, EDID_QUIRK_FORCE_6BPC),
0711a43b 132
06998a75 133 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
7d1be0a0 134 EDID_QUIRK('C', 'P', 'T', 0x17df, EDID_QUIRK_FORCE_6BPC),
06998a75 135
25da7504 136 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
7d1be0a0 137 EDID_QUIRK('S', 'D', 'C', 0x3652, EDID_QUIRK_FORCE_6BPC),
25da7504 138
922dceff 139 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
7d1be0a0 140 EDID_QUIRK('B', 'O', 'E', 0x0771, EDID_QUIRK_FORCE_6BPC),
922dceff 141
f453ba04 142 /* Belinea 10 15 55 */
7d1be0a0
DA		 143 EDID_QUIRK('M', 'A', 'X', 1516, EDID_QUIRK_PREFER_LARGE_60),
144 EDID_QUIRK('M', 'A', 'X', 0x77e, EDID_QUIRK_PREFER_LARGE_60),
f453ba04
DA		 145
146 /* Envision Peripherals, Inc. EN-7100e */
7d1be0a0 147 EDID_QUIRK('E', 'P', 'I', 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH),
ba1163de 148 /* Envision EN2028 */
7d1be0a0 149 EDID_QUIRK('E', 'P', 'I', 8232, EDID_QUIRK_PREFER_LARGE_60),
f453ba04
DA		 150
151 /* Funai Electronics PM36B */
7d1be0a0 152 EDID_QUIRK('F', 'C', 'M', 13600, EDID_QUIRK_PREFER_LARGE_75 |
e8de4d55 153 EDID_QUIRK_DETAILED_IN_CM),
f453ba04 154
e345da82 155 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
7d1be0a0 156 EDID_QUIRK('L', 'G', 'D', 764, EDID_QUIRK_FORCE_10BPC),
e345da82 157
f453ba04 158 /* LG Philips LCD LP154W01-A5 */
7d1be0a0
DA		 159 EDID_QUIRK('L', 'P', 'L', 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
160 EDID_QUIRK('L', 'P', 'L', 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
f453ba04 161
f453ba04 162 /* Samsung SyncMaster 205BW. Note: irony */
7d1be0a0 163 EDID_QUIRK('S', 'A', 'M', 541, EDID_QUIRK_DETAILED_SYNC_PP),
f453ba04 164 /* Samsung SyncMaster 22[5-6]BW */
7d1be0a0
DA		 165 EDID_QUIRK('S', 'A', 'M', 596, EDID_QUIRK_PREFER_LARGE_60),
166 EDID_QUIRK('S', 'A', 'M', 638, EDID_QUIRK_PREFER_LARGE_60),
bc42aabc 167
bc5b9641 168 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
7d1be0a0 169 EDID_QUIRK('S', 'N', 'Y', 0x2541, EDID_QUIRK_FORCE_12BPC),
bc5b9641 170
bc42aabc 171 /* ViewSonic VA2026w */
7d1be0a0 172 EDID_QUIRK('V', 'S', 'C', 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING),
118bdbd8
AD		 173
174 /* Medion MD 30217 PG */
7d1be0a0 175 EDID_QUIRK('M', 'E', 'D', 0x7b8, EDID_QUIRK_PREFER_LARGE_75),
49d45a31 176
11bcf5f7 177 /* Lenovo G50 */
7d1be0a0 178 EDID_QUIRK('S', 'D', 'C', 18514, EDID_QUIRK_FORCE_6BPC),
11bcf5f7 179
49d45a31 180 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
7d1be0a0 181 EDID_QUIRK('S', 'E', 'C', 0xd033, EDID_QUIRK_FORCE_8BPC),
36fc5797
TV		 182
183 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
7d1be0a0 184 EDID_QUIRK('E', 'T', 'R', 13896, EDID_QUIRK_FORCE_8BPC),
acb1d8ee 185
30d62d44 186 /* Valve Index Headset */
7d1be0a0
DA		 187 EDID_QUIRK('V', 'L', 'V', 0x91a8, EDID_QUIRK_NON_DESKTOP),
188 EDID_QUIRK('V', 'L', 'V', 0x91b0, EDID_QUIRK_NON_DESKTOP),
189 EDID_QUIRK('V', 'L', 'V', 0x91b1, EDID_QUIRK_NON_DESKTOP),
190 EDID_QUIRK('V', 'L', 'V', 0x91b2, EDID_QUIRK_NON_DESKTOP),
191 EDID_QUIRK('V', 'L', 'V', 0x91b3, EDID_QUIRK_NON_DESKTOP),
192 EDID_QUIRK('V', 'L', 'V', 0x91b4, EDID_QUIRK_NON_DESKTOP),
193 EDID_QUIRK('V', 'L', 'V', 0x91b5, EDID_QUIRK_NON_DESKTOP),
194 EDID_QUIRK('V', 'L', 'V', 0x91b6, EDID_QUIRK_NON_DESKTOP),
195 EDID_QUIRK('V', 'L', 'V', 0x91b7, EDID_QUIRK_NON_DESKTOP),
196 EDID_QUIRK('V', 'L', 'V', 0x91b8, EDID_QUIRK_NON_DESKTOP),
197 EDID_QUIRK('V', 'L', 'V', 0x91b9, EDID_QUIRK_NON_DESKTOP),
198 EDID_QUIRK('V', 'L', 'V', 0x91ba, EDID_QUIRK_NON_DESKTOP),
199 EDID_QUIRK('V', 'L', 'V', 0x91bb, EDID_QUIRK_NON_DESKTOP),
200 EDID_QUIRK('V', 'L', 'V', 0x91bc, EDID_QUIRK_NON_DESKTOP),
201 EDID_QUIRK('V', 'L', 'V', 0x91bd, EDID_QUIRK_NON_DESKTOP),
202 EDID_QUIRK('V', 'L', 'V', 0x91be, EDID_QUIRK_NON_DESKTOP),
203 EDID_QUIRK('V', 'L', 'V', 0x91bf, EDID_QUIRK_NON_DESKTOP),
30d62d44 204
6931317c 205 /* HTC Vive and Vive Pro VR Headsets */
7d1be0a0
DA		 206 EDID_QUIRK('H', 'V', 'R', 0xaa01, EDID_QUIRK_NON_DESKTOP),
207 EDID_QUIRK('H', 'V', 'R', 0xaa02, EDID_QUIRK_NON_DESKTOP),
b3b12ea3 208
5a3f6108 209 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */
7d1be0a0
DA		 210 EDID_QUIRK('O', 'V', 'R', 0x0001, EDID_QUIRK_NON_DESKTOP),
211 EDID_QUIRK('O', 'V', 'R', 0x0003, EDID_QUIRK_NON_DESKTOP),
212 EDID_QUIRK('O', 'V', 'R', 0x0004, EDID_QUIRK_NON_DESKTOP),
213 EDID_QUIRK('O', 'V', 'R', 0x0012, EDID_QUIRK_NON_DESKTOP),
90eda8fc
PZ		 214
215 /* Windows Mixed Reality Headsets */
7d1be0a0 216 EDID_QUIRK('A', 'C', 'R', 0x7fce, EDID_QUIRK_NON_DESKTOP),
7d1be0a0 217 EDID_QUIRK('L', 'E', 'N', 0x0408, EDID_QUIRK_NON_DESKTOP),
7d1be0a0
DA		 218 EDID_QUIRK('F', 'U', 'J', 0x1970, EDID_QUIRK_NON_DESKTOP),
219 EDID_QUIRK('D', 'E', 'L', 0x7fce, EDID_QUIRK_NON_DESKTOP),
220 EDID_QUIRK('S', 'E', 'C', 0x144a, EDID_QUIRK_NON_DESKTOP),
221 EDID_QUIRK('A', 'U', 'S', 0xc102, EDID_QUIRK_NON_DESKTOP),
ccffc9eb
PZ		 222
223 /* Sony PlayStation VR Headset */
7d1be0a0 224 EDID_QUIRK('S', 'N', 'Y', 0x0704, EDID_QUIRK_NON_DESKTOP),
29054230
RP		 225
226 /* Sensics VR Headsets */
7d1be0a0 227 EDID_QUIRK('S', 'E', 'N', 0x1019, EDID_QUIRK_NON_DESKTOP),
29054230
RP		 228
229 /* OSVR HDK and HDK2 VR Headsets */
7d1be0a0 230 EDID_QUIRK('S', 'V', 'R', 0x1019, EDID_QUIRK_NON_DESKTOP),
f453ba04
DA		 231};
232
a6b21831
TR		 233/*
234 * Autogenerated from the DMT spec.
235 * This table is copied from xfree86/modes/xf86EdidModes.c.
236 */
237static const struct drm_display_mode drm_dmt_modes[] = {
24b856b1 238 /* 0x01 - 640x350@85Hz */
a6b21831
TR		 239 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
240 736, 832, 0, 350, 382, 385, 445, 0,
241 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 242 /* 0x02 - 640x400@85Hz */
a6b21831
TR		 243 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
244 736, 832, 0, 400, 401, 404, 445, 0,
245 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 246 /* 0x03 - 720x400@85Hz */
a6b21831
TR		 247 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
248 828, 936, 0, 400, 401, 404, 446, 0,
249 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 250 /* 0x04 - 640x480@60Hz */
a6b21831 251 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
fcf22d05 252 752, 800, 0, 480, 490, 492, 525, 0,
a6b21831 253 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 254 /* 0x05 - 640x480@72Hz */
a6b21831
TR		 255 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
256 704, 832, 0, 480, 489, 492, 520, 0,
257 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 258 /* 0x06 - 640x480@75Hz */
a6b21831
TR		 259 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
260 720, 840, 0, 480, 481, 484, 500, 0,
261 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 262 /* 0x07 - 640x480@85Hz */
a6b21831
TR		 263 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
264 752, 832, 0, 480, 481, 484, 509, 0,
265 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 266 /* 0x08 - 800x600@56Hz */
a6b21831
TR		 267 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
268 896, 1024, 0, 600, 601, 603, 625, 0,
269 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 270 /* 0x09 - 800x600@60Hz */
a6b21831
TR		 271 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
272 968, 1056, 0, 600, 601, 605, 628, 0,
273 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 274 /* 0x0a - 800x600@72Hz */
a6b21831
TR		 275 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
276 976, 1040, 0, 600, 637, 643, 666, 0,
277 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 278 /* 0x0b - 800x600@75Hz */
a6b21831
TR		 279 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
280 896, 1056, 0, 600, 601, 604, 625, 0,
281 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 282 /* 0x0c - 800x600@85Hz */
a6b21831
TR		 283 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
284 896, 1048, 0, 600, 601, 604, 631, 0,
285 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 286 /* 0x0d - 800x600@120Hz RB */
a6b21831
TR		 287 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
288 880, 960, 0, 600, 603, 607, 636, 0,
289 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 290 /* 0x0e - 848x480@60Hz */
a6b21831
TR		 291 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
292 976, 1088, 0, 480, 486, 494, 517, 0,
293 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 294 /* 0x0f - 1024x768@43Hz, interlace */
a6b21831 295 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
735b100f 296 1208, 1264, 0, 768, 768, 776, 817, 0,
a6b21831 297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
fcf22d05 298 DRM_MODE_FLAG_INTERLACE) },
24b856b1 299 /* 0x10 - 1024x768@60Hz */
a6b21831
TR		 300 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
301 1184, 1344, 0, 768, 771, 777, 806, 0,
302 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 303 /* 0x11 - 1024x768@70Hz */
a6b21831
TR		 304 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
305 1184, 1328, 0, 768, 771, 777, 806, 0,
306 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 307 /* 0x12 - 1024x768@75Hz */
a6b21831
TR		 308 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
309 1136, 1312, 0, 768, 769, 772, 800, 0,
310 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 311 /* 0x13 - 1024x768@85Hz */
a6b21831
TR		 312 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
313 1168, 1376, 0, 768, 769, 772, 808, 0,
314 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 315 /* 0x14 - 1024x768@120Hz RB */
a6b21831
TR		 316 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
317 1104, 1184, 0, 768, 771, 775, 813, 0,
318 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 319 /* 0x15 - 1152x864@75Hz */
a6b21831
TR		 320 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
321 1344, 1600, 0, 864, 865, 868, 900, 0,
322 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
bfcd74d2
VS		 323 /* 0x55 - 1280x720@60Hz */
324 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
325 1430, 1650, 0, 720, 725, 730, 750, 0,
326 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 327 /* 0x16 - 1280x768@60Hz RB */
a6b21831
TR		 328 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
329 1360, 1440, 0, 768, 771, 778, 790, 0,
330 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 331 /* 0x17 - 1280x768@60Hz */
a6b21831
TR		 332 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
333 1472, 1664, 0, 768, 771, 778, 798, 0,
334 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 335 /* 0x18 - 1280x768@75Hz */
a6b21831
TR		 336 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
337 1488, 1696, 0, 768, 771, 778, 805, 0,
fcf22d05 338 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 339 /* 0x19 - 1280x768@85Hz */
a6b21831
TR		 340 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
341 1496, 1712, 0, 768, 771, 778, 809, 0,
342 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 343 /* 0x1a - 1280x768@120Hz RB */
a6b21831
TR		 344 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
345 1360, 1440, 0, 768, 771, 778, 813, 0,
346 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 347 /* 0x1b - 1280x800@60Hz RB */
a6b21831
TR		 348 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
349 1360, 1440, 0, 800, 803, 809, 823, 0,
350 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 351 /* 0x1c - 1280x800@60Hz */
a6b21831
TR		 352 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
353 1480, 1680, 0, 800, 803, 809, 831, 0,
fcf22d05 354 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 355 /* 0x1d - 1280x800@75Hz */
a6b21831
TR		 356 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
357 1488, 1696, 0, 800, 803, 809, 838, 0,
358 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 359 /* 0x1e - 1280x800@85Hz */
a6b21831
TR		 360 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
361 1496, 1712, 0, 800, 803, 809, 843, 0,
362 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 363 /* 0x1f - 1280x800@120Hz RB */
a6b21831
TR		 364 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
365 1360, 1440, 0, 800, 803, 809, 847, 0,
366 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 367 /* 0x20 - 1280x960@60Hz */
a6b21831
TR		 368 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
369 1488, 1800, 0, 960, 961, 964, 1000, 0,
370 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 371 /* 0x21 - 1280x960@85Hz */
a6b21831
TR		 372 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
373 1504, 1728, 0, 960, 961, 964, 1011, 0,
374 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 375 /* 0x22 - 1280x960@120Hz RB */
a6b21831
TR		 376 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
377 1360, 1440, 0, 960, 963, 967, 1017, 0,
378 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 379 /* 0x23 - 1280x1024@60Hz */
a6b21831
TR		 380 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
381 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
382 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 383 /* 0x24 - 1280x1024@75Hz */
a6b21831
TR		 384 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
385 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
386 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 387 /* 0x25 - 1280x1024@85Hz */
a6b21831
TR		 388 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
389 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
390 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 391 /* 0x26 - 1280x1024@120Hz RB */
a6b21831
TR		 392 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
393 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
394 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 395 /* 0x27 - 1360x768@60Hz */
a6b21831
TR		 396 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
397 1536, 1792, 0, 768, 771, 777, 795, 0,
398 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 399 /* 0x28 - 1360x768@120Hz RB */
a6b21831
TR		 400 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
401 1440, 1520, 0, 768, 771, 776, 813, 0,
402 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 403 /* 0x51 - 1366x768@60Hz */
404 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
405 1579, 1792, 0, 768, 771, 774, 798, 0,
406 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
407 /* 0x56 - 1366x768@60Hz */
408 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
409 1436, 1500, 0, 768, 769, 772, 800, 0,
410 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 411 /* 0x29 - 1400x1050@60Hz RB */
a6b21831
TR		 412 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
413 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
414 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 415 /* 0x2a - 1400x1050@60Hz */
a6b21831
TR		 416 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
417 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
418 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 419 /* 0x2b - 1400x1050@75Hz */
a6b21831
TR		 420 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
421 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
422 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 423 /* 0x2c - 1400x1050@85Hz */
a6b21831
TR		 424 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
425 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
426 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 427 /* 0x2d - 1400x1050@120Hz RB */
a6b21831
TR		 428 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
429 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
430 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 431 /* 0x2e - 1440x900@60Hz RB */
a6b21831
TR		 432 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
433 1520, 1600, 0, 900, 903, 909, 926, 0,
434 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 435 /* 0x2f - 1440x900@60Hz */
a6b21831
TR		 436 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
437 1672, 1904, 0, 900, 903, 909, 934, 0,
438 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 439 /* 0x30 - 1440x900@75Hz */
a6b21831
TR		 440 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
441 1688, 1936, 0, 900, 903, 909, 942, 0,
442 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 443 /* 0x31 - 1440x900@85Hz */
a6b21831
TR		 444 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
445 1696, 1952, 0, 900, 903, 909, 948, 0,
446 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 447 /* 0x32 - 1440x900@120Hz RB */
a6b21831
TR		 448 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
449 1520, 1600, 0, 900, 903, 909, 953, 0,
450 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 451 /* 0x53 - 1600x900@60Hz */
452 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
453 1704, 1800, 0, 900, 901, 904, 1000, 0,
454 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 455 /* 0x33 - 1600x1200@60Hz */
a6b21831
TR		 456 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
457 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
458 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 459 /* 0x34 - 1600x1200@65Hz */
a6b21831
TR		 460 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
461 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
462 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 463 /* 0x35 - 1600x1200@70Hz */
a6b21831
TR		 464 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
465 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
466 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 467 /* 0x36 - 1600x1200@75Hz */
a6b21831
TR		 468 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
469 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
470 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 471 /* 0x37 - 1600x1200@85Hz */
a6b21831
TR		 472 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
473 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
474 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 475 /* 0x38 - 1600x1200@120Hz RB */
a6b21831
TR		 476 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
477 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
478 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 479 /* 0x39 - 1680x1050@60Hz RB */
a6b21831
TR		 480 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
481 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
482 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 483 /* 0x3a - 1680x1050@60Hz */
a6b21831
TR		 484 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
485 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
486 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 487 /* 0x3b - 1680x1050@75Hz */
a6b21831
TR		 488 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
489 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
490 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 491 /* 0x3c - 1680x1050@85Hz */
a6b21831
TR		 492 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
493 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
494 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 495 /* 0x3d - 1680x1050@120Hz RB */
a6b21831
TR		 496 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
497 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
498 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 499 /* 0x3e - 1792x1344@60Hz */
a6b21831
TR		 500 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
501 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
502 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 503 /* 0x3f - 1792x1344@75Hz */
a6b21831
TR		 504 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
505 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
506 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 507 /* 0x40 - 1792x1344@120Hz RB */
a6b21831
TR		 508 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
509 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
510 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 511 /* 0x41 - 1856x1392@60Hz */
a6b21831
TR		 512 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
513 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
514 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 515 /* 0x42 - 1856x1392@75Hz */
a6b21831 516 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
fcf22d05 517 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
a6b21831 518 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 519 /* 0x43 - 1856x1392@120Hz RB */
a6b21831
TR		 520 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
521 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
522 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 523 /* 0x52 - 1920x1080@60Hz */
524 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
525 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
526 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 527 /* 0x44 - 1920x1200@60Hz RB */
a6b21831
TR		 528 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
529 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
530 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 531 /* 0x45 - 1920x1200@60Hz */
a6b21831
TR		 532 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
533 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
534 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 535 /* 0x46 - 1920x1200@75Hz */
a6b21831
TR		 536 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
537 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
538 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 539 /* 0x47 - 1920x1200@85Hz */
a6b21831
TR		 540 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
541 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
542 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 543 /* 0x48 - 1920x1200@120Hz RB */
a6b21831
TR		 544 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
545 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
546 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 547 /* 0x49 - 1920x1440@60Hz */
a6b21831
TR		 548 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
549 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
550 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 551 /* 0x4a - 1920x1440@75Hz */
a6b21831
TR		 552 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
553 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
554 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 555 /* 0x4b - 1920x1440@120Hz RB */
a6b21831
TR		 556 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
557 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
558 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 559 /* 0x54 - 2048x1152@60Hz */
560 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
561 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
562 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 563 /* 0x4c - 2560x1600@60Hz RB */
a6b21831
TR		 564 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
565 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
566 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 567 /* 0x4d - 2560x1600@60Hz */
a6b21831
TR		 568 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
569 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
570 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 571 /* 0x4e - 2560x1600@75Hz */
a6b21831
TR		 572 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
573 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
574 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 575 /* 0x4f - 2560x1600@85Hz */
a6b21831
TR		 576 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
577 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
578 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 579 /* 0x50 - 2560x1600@120Hz RB */
a6b21831
TR		 580 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
581 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
582 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 583 /* 0x57 - 4096x2160@60Hz RB */
584 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
585 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
586 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
587 /* 0x58 - 4096x2160@59.94Hz RB */
588 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
589 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
590 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
a6b21831
TR		 591};
592
e7bfa5c4
VS		 593/*
594 * These more or less come from the DMT spec. The 720x400 modes are
595 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
596 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
597 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
598 * mode.
599 *
600 * The DMT modes have been fact-checked; the rest are mild guesses.
601 */
a6b21831
TR		 602static const struct drm_display_mode edid_est_modes[] = {
603 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
604 968, 1056, 0, 600, 601, 605, 628, 0,
605 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
606 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
607 896, 1024, 0, 600, 601, 603, 625, 0,
608 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
609 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
610 720, 840, 0, 480, 481, 484, 500, 0,
611 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
612 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
87707cfd 613 704, 832, 0, 480, 489, 492, 520, 0,
a6b21831
TR		 614 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
615 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
616 768, 864, 0, 480, 483, 486, 525, 0,
617 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
87707cfd 618 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
a6b21831
TR		 619 752, 800, 0, 480, 490, 492, 525, 0,
620 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
621 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
622 846, 900, 0, 400, 421, 423, 449, 0,
623 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
624 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
625 846, 900, 0, 400, 412, 414, 449, 0,
626 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
627 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
628 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
629 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
87707cfd 630 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
a6b21831
TR		 631 1136, 1312, 0, 768, 769, 772, 800, 0,
632 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
633 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
634 1184, 1328, 0, 768, 771, 777, 806, 0,
635 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
636 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
637 1184, 1344, 0, 768, 771, 777, 806, 0,
638 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
639 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
640 1208, 1264, 0, 768, 768, 776, 817, 0,
641 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
642 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
643 928, 1152, 0, 624, 625, 628, 667, 0,
644 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
645 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
646 896, 1056, 0, 600, 601, 604, 625, 0,
647 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
648 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
649 976, 1040, 0, 600, 637, 643, 666, 0,
650 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
651 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
652 1344, 1600, 0, 864, 865, 868, 900, 0,
653 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
654};
655
656struct minimode {
657 short w;
658 short h;
659 short r;
660 short rb;
661};
662
663static const struct minimode est3_modes[] = {
664 /* byte 6 */
665 { 640, 350, 85, 0 },
666 { 640, 400, 85, 0 },
667 { 720, 400, 85, 0 },
668 { 640, 480, 85, 0 },
669 { 848, 480, 60, 0 },
670 { 800, 600, 85, 0 },
671 { 1024, 768, 85, 0 },
672 { 1152, 864, 75, 0 },
673 /* byte 7 */
674 { 1280, 768, 60, 1 },
675 { 1280, 768, 60, 0 },
676 { 1280, 768, 75, 0 },
677 { 1280, 768, 85, 0 },
678 { 1280, 960, 60, 0 },
679 { 1280, 960, 85, 0 },
680 { 1280, 1024, 60, 0 },
681 { 1280, 1024, 85, 0 },
682 /* byte 8 */
683 { 1360, 768, 60, 0 },
684 { 1440, 900, 60, 1 },
685 { 1440, 900, 60, 0 },
686 { 1440, 900, 75, 0 },
687 { 1440, 900, 85, 0 },
688 { 1400, 1050, 60, 1 },
689 { 1400, 1050, 60, 0 },
690 { 1400, 1050, 75, 0 },
691 /* byte 9 */
692 { 1400, 1050, 85, 0 },
693 { 1680, 1050, 60, 1 },
694 { 1680, 1050, 60, 0 },
695 { 1680, 1050, 75, 0 },
696 { 1680, 1050, 85, 0 },
697 { 1600, 1200, 60, 0 },
698 { 1600, 1200, 65, 0 },
699 { 1600, 1200, 70, 0 },
700 /* byte 10 */
701 { 1600, 1200, 75, 0 },
702 { 1600, 1200, 85, 0 },
703 { 1792, 1344, 60, 0 },
c068b32a 704 { 1792, 1344, 75, 0 },
a6b21831
TR		 705 { 1856, 1392, 60, 0 },
706 { 1856, 1392, 75, 0 },
707 { 1920, 1200, 60, 1 },
708 { 1920, 1200, 60, 0 },
709 /* byte 11 */
710 { 1920, 1200, 75, 0 },
711 { 1920, 1200, 85, 0 },
712 { 1920, 1440, 60, 0 },
713 { 1920, 1440, 75, 0 },
714};
715
716static const struct minimode extra_modes[] = {
717 { 1024, 576, 60, 0 },
718 { 1366, 768, 60, 0 },
719 { 1600, 900, 60, 0 },
720 { 1680, 945, 60, 0 },
721 { 1920, 1080, 60, 0 },
722 { 2048, 1152, 60, 0 },
723 { 2048, 1536, 60, 0 },
724};
725
726/*
7befe621 727 * From CEA/CTA-861 spec.
d9278b4c 728 *
7befe621 729 * Do not access directly, instead always use cea_mode_for_vic().
a6b21831 730 */
8c1b2bd9 731static const struct drm_display_mode edid_cea_modes_1[] = {
78691960 732 /* 1 - 640x480@60Hz 4:3 */
a6b21831
TR		 733 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
734 752, 800, 0, 480, 490, 492, 525, 0,
ee7925bb 735 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 736 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 737 /* 2 - 720x480@60Hz 4:3 */
a6b21831
TR		 738 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
739 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 740 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 741 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 742 /* 3 - 720x480@60Hz 16:9 */
a6b21831
TR		 743 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
744 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 745 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 746 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 747 /* 4 - 1280x720@60Hz 16:9 */
a6b21831
TR		 748 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
749 1430, 1650, 0, 720, 725, 730, 750, 0,
ee7925bb 750 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 751 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 752 /* 5 - 1920x1080i@60Hz 16:9 */
a6b21831
TR		 753 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
754 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
755 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 756 DRM_MODE_FLAG_INTERLACE),
0425662f 757 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 758 /* 6 - 720(1440)x480i@60Hz 4:3 */
fb01d280
CT		 759 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
760 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 761 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 762 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 763 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 764 /* 7 - 720(1440)x480i@60Hz 16:9 */
fb01d280
CT		 765 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
766 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 767 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 768 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 769 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 770 /* 8 - 720(1440)x240@60Hz 4:3 */
fb01d280
CT		 771 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
772 801, 858, 0, 240, 244, 247, 262, 0,
a6b21831 773 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 774 DRM_MODE_FLAG_DBLCLK),
0425662f 775 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 776 /* 9 - 720(1440)x240@60Hz 16:9 */
fb01d280
CT		 777 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
778 801, 858, 0, 240, 244, 247, 262, 0,
a6b21831 779 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 780 DRM_MODE_FLAG_DBLCLK),
0425662f 781 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 782 /* 10 - 2880x480i@60Hz 4:3 */
a6b21831
TR		 783 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
784 3204, 3432, 0, 480, 488, 494, 525, 0,
785 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 786 DRM_MODE_FLAG_INTERLACE),
0425662f 787 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 788 /* 11 - 2880x480i@60Hz 16:9 */
a6b21831
TR		 789 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
790 3204, 3432, 0, 480, 488, 494, 525, 0,
791 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 792 DRM_MODE_FLAG_INTERLACE),
0425662f 793 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 794 /* 12 - 2880x240@60Hz 4:3 */
a6b21831
TR		 795 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
796 3204, 3432, 0, 240, 244, 247, 262, 0,
ee7925bb 797 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 798 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 799 /* 13 - 2880x240@60Hz 16:9 */
a6b21831
TR		 800 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
801 3204, 3432, 0, 240, 244, 247, 262, 0,
ee7925bb 802 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 803 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 804 /* 14 - 1440x480@60Hz 4:3 */
a6b21831
TR		 805 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
806 1596, 1716, 0, 480, 489, 495, 525, 0,
ee7925bb 807 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 808 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 809 /* 15 - 1440x480@60Hz 16:9 */
a6b21831
TR		 810 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
811 1596, 1716, 0, 480, 489, 495, 525, 0,
ee7925bb 812 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 813 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 814 /* 16 - 1920x1080@60Hz 16:9 */
a6b21831
TR		 815 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
816 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 817 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 818 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 819 /* 17 - 720x576@50Hz 4:3 */
a6b21831
TR		 820 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
821 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 822 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 823 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 824 /* 18 - 720x576@50Hz 16:9 */
a6b21831
TR		 825 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
826 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 827 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 828 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 829 /* 19 - 1280x720@50Hz 16:9 */
a6b21831
TR		 830 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
831 1760, 1980, 0, 720, 725, 730, 750, 0,
ee7925bb 832 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 833 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 834 /* 20 - 1920x1080i@50Hz 16:9 */
a6b21831
TR		 835 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
836 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
837 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 838 DRM_MODE_FLAG_INTERLACE),
0425662f 839 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 840 /* 21 - 720(1440)x576i@50Hz 4:3 */
fb01d280
CT		 841 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
842 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 843 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 844 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 845 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 846 /* 22 - 720(1440)x576i@50Hz 16:9 */
fb01d280
CT		 847 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
848 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 849 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 850 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 851 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 852 /* 23 - 720(1440)x288@50Hz 4:3 */
fb01d280
CT		 853 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
854 795, 864, 0, 288, 290, 293, 312, 0,
a6b21831 855 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 856 DRM_MODE_FLAG_DBLCLK),
0425662f 857 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 858 /* 24 - 720(1440)x288@50Hz 16:9 */
fb01d280
CT		 859 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
860 795, 864, 0, 288, 290, 293, 312, 0,
a6b21831 861 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 862 DRM_MODE_FLAG_DBLCLK),
0425662f 863 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 864 /* 25 - 2880x576i@50Hz 4:3 */
a6b21831
TR		 865 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
866 3180, 3456, 0, 576, 580, 586, 625, 0,
867 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 868 DRM_MODE_FLAG_INTERLACE),
0425662f 869 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 870 /* 26 - 2880x576i@50Hz 16:9 */
a6b21831
TR		 871 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
872 3180, 3456, 0, 576, 580, 586, 625, 0,
873 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 874 DRM_MODE_FLAG_INTERLACE),
0425662f 875 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 876 /* 27 - 2880x288@50Hz 4:3 */
a6b21831
TR		 877 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
878 3180, 3456, 0, 288, 290, 293, 312, 0,
ee7925bb 879 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 880 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 881 /* 28 - 2880x288@50Hz 16:9 */
a6b21831
TR		 882 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
883 3180, 3456, 0, 288, 290, 293, 312, 0,
ee7925bb 884 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 885 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 886 /* 29 - 1440x576@50Hz 4:3 */
a6b21831
TR		 887 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
888 1592, 1728, 0, 576, 581, 586, 625, 0,
ee7925bb 889 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 890 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 891 /* 30 - 1440x576@50Hz 16:9 */
a6b21831
TR		 892 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
893 1592, 1728, 0, 576, 581, 586, 625, 0,
ee7925bb 894 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 895 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 896 /* 31 - 1920x1080@50Hz 16:9 */
a6b21831
TR		 897 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
898 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 899 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 900 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 901 /* 32 - 1920x1080@24Hz 16:9 */
a6b21831
TR		 902 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
903 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 904 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 905 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 906 /* 33 - 1920x1080@25Hz 16:9 */
a6b21831
TR		 907 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
908 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 909 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 910 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 911 /* 34 - 1920x1080@30Hz 16:9 */
a6b21831
TR		 912 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
913 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 914 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 915 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 916 /* 35 - 2880x480@60Hz 4:3 */
a6b21831
TR		 917 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
918 3192, 3432, 0, 480, 489, 495, 525, 0,
ee7925bb 919 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 920 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 921 /* 36 - 2880x480@60Hz 16:9 */
a6b21831
TR		 922 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
923 3192, 3432, 0, 480, 489, 495, 525, 0,
ee7925bb 924 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 925 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 926 /* 37 - 2880x576@50Hz 4:3 */
a6b21831
TR		 927 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
928 3184, 3456, 0, 576, 581, 586, 625, 0,
ee7925bb 929 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 930 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 931 /* 38 - 2880x576@50Hz 16:9 */
a6b21831
TR		 932 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
933 3184, 3456, 0, 576, 581, 586, 625, 0,
ee7925bb 934 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 935 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 936 /* 39 - 1920x1080i@50Hz 16:9 */
a6b21831
TR		 937 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
938 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
939 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 940 DRM_MODE_FLAG_INTERLACE),
0425662f 941 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 942 /* 40 - 1920x1080i@100Hz 16:9 */
a6b21831
TR		 943 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
944 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
945 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 946 DRM_MODE_FLAG_INTERLACE),
0425662f 947 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 948 /* 41 - 1280x720@100Hz 16:9 */
a6b21831
TR		 949 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
950 1760, 1980, 0, 720, 725, 730, 750, 0,
ee7925bb 951 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 952 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 953 /* 42 - 720x576@100Hz 4:3 */
a6b21831
TR		 954 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
955 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 956 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 957 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 958 /* 43 - 720x576@100Hz 16:9 */
a6b21831
TR		 959 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
960 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 961 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 962 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 963 /* 44 - 720(1440)x576i@100Hz 4:3 */
fb01d280
CT		 964 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
965 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 966 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 967 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 968 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 969 /* 45 - 720(1440)x576i@100Hz 16:9 */
fb01d280
CT		 970 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
971 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 972 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 973 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 974 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 975 /* 46 - 1920x1080i@120Hz 16:9 */
a6b21831
TR		 976 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
977 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
978 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 979 DRM_MODE_FLAG_INTERLACE),
0425662f 980 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 981 /* 47 - 1280x720@120Hz 16:9 */
a6b21831
TR		 982 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
983 1430, 1650, 0, 720, 725, 730, 750, 0,
ee7925bb 984 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 985 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 986 /* 48 - 720x480@120Hz 4:3 */
a6b21831
TR		 987 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
988 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 989 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 990 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 991 /* 49 - 720x480@120Hz 16:9 */
a6b21831
TR		 992 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
993 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 994 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 995 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 996 /* 50 - 720(1440)x480i@120Hz 4:3 */
fb01d280
CT		 997 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
998 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 999 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1000 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1001 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1002 /* 51 - 720(1440)x480i@120Hz 16:9 */
fb01d280
CT		 1003 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
1004 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 1005 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1006 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1007 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1008 /* 52 - 720x576@200Hz 4:3 */
a6b21831
TR		 1009 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1010 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 1011 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 1012 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1013 /* 53 - 720x576@200Hz 16:9 */
a6b21831
TR		 1014 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1015 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 1016 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 1017 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1018 /* 54 - 720(1440)x576i@200Hz 4:3 */
fb01d280
CT		 1019 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1020 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 1021 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1022 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1023 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1024 /* 55 - 720(1440)x576i@200Hz 16:9 */
fb01d280
CT		 1025 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1026 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 1027 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1028 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1029 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1030 /* 56 - 720x480@240Hz 4:3 */
a6b21831
TR		 1031 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1032 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 1033 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 1034 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1035 /* 57 - 720x480@240Hz 16:9 */
a6b21831
TR		 1036 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1037 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 1038 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 1039 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1040 /* 58 - 720(1440)x480i@240Hz 4:3 */
fb01d280
CT		 1041 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1042 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 1043 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1044 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1045 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1046 /* 59 - 720(1440)x480i@240Hz 16:9 */
fb01d280
CT		 1047 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1048 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 1049 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1050 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1051 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1052 /* 60 - 1280x720@24Hz 16:9 */
a6b21831
TR		 1053 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1054 3080, 3300, 0, 720, 725, 730, 750, 0,
ee7925bb 1055 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1056 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1057 /* 61 - 1280x720@25Hz 16:9 */
a6b21831
TR		 1058 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1059 3740, 3960, 0, 720, 725, 730, 750, 0,
ee7925bb 1060 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1061 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1062 /* 62 - 1280x720@30Hz 16:9 */
a6b21831
TR		 1063 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1064 3080, 3300, 0, 720, 725, 730, 750, 0,
ee7925bb 1065 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1066 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1067 /* 63 - 1920x1080@120Hz 16:9 */
a6b21831
TR		 1068 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1069 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 1070 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1071 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1072 /* 64 - 1920x1080@100Hz 16:9 */
a6b21831 1073 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
8f0e4907 1074 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 1075 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1076 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1077 /* 65 - 1280x720@24Hz 64:27 */
8ec6e075
SS		 1078 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1079 3080, 3300, 0, 720, 725, 730, 750, 0,
1080 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1081 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1082 /* 66 - 1280x720@25Hz 64:27 */
8ec6e075
SS		 1083 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1084 3740, 3960, 0, 720, 725, 730, 750, 0,
1085 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1086 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1087 /* 67 - 1280x720@30Hz 64:27 */
8ec6e075
SS		 1088 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1089 3080, 3300, 0, 720, 725, 730, 750, 0,
1090 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1091 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1092 /* 68 - 1280x720@50Hz 64:27 */
8ec6e075
SS		 1093 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1094 1760, 1980, 0, 720, 725, 730, 750, 0,
1095 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1096 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1097 /* 69 - 1280x720@60Hz 64:27 */
8ec6e075
SS		 1098 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1099 1430, 1650, 0, 720, 725, 730, 750, 0,
1100 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1101 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1102 /* 70 - 1280x720@100Hz 64:27 */
8ec6e075
SS		 1103 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1104 1760, 1980, 0, 720, 725, 730, 750, 0,
1105 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1106 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1107 /* 71 - 1280x720@120Hz 64:27 */
8ec6e075
SS		 1108 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1109 1430, 1650, 0, 720, 725, 730, 750, 0,
1110 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1111 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1112 /* 72 - 1920x1080@24Hz 64:27 */
8ec6e075
SS		 1113 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1114 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1115 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1116 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1117 /* 73 - 1920x1080@25Hz 64:27 */
8ec6e075
SS		 1118 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1119 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1120 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1121 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1122 /* 74 - 1920x1080@30Hz 64:27 */
8ec6e075
SS		 1123 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1124 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1125 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1126 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1127 /* 75 - 1920x1080@50Hz 64:27 */
8ec6e075
SS		 1128 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1129 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1130 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1131 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1132 /* 76 - 1920x1080@60Hz 64:27 */
8ec6e075
SS		 1133 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1134 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1135 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1136 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1137 /* 77 - 1920x1080@100Hz 64:27 */
8ec6e075
SS		 1138 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1139 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1140 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1141 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1142 /* 78 - 1920x1080@120Hz 64:27 */
8ec6e075
SS		 1143 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1144 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1145 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1146 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1147 /* 79 - 1680x720@24Hz 64:27 */
8ec6e075
SS		 1148 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1149 3080, 3300, 0, 720, 725, 730, 750, 0,
1150 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1151 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1152 /* 80 - 1680x720@25Hz 64:27 */
8ec6e075
SS		 1153 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1154 2948, 3168, 0, 720, 725, 730, 750, 0,
1155 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1156 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1157 /* 81 - 1680x720@30Hz 64:27 */
8ec6e075
SS		 1158 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1159 2420, 2640, 0, 720, 725, 730, 750, 0,
1160 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1161 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1162 /* 82 - 1680x720@50Hz 64:27 */
8ec6e075
SS		 1163 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1164 1980, 2200, 0, 720, 725, 730, 750, 0,
1165 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1166 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1167 /* 83 - 1680x720@60Hz 64:27 */
8ec6e075
SS		 1168 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1169 1980, 2200, 0, 720, 725, 730, 750, 0,
1170 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1171 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1172 /* 84 - 1680x720@100Hz 64:27 */
8ec6e075
SS		 1173 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1174 1780, 2000, 0, 720, 725, 730, 825, 0,
1175 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1176 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1177 /* 85 - 1680x720@120Hz 64:27 */
8ec6e075
SS		 1178 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1179 1780, 2000, 0, 720, 725, 730, 825, 0,
1180 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1181 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1182 /* 86 - 2560x1080@24Hz 64:27 */
8ec6e075
SS		 1183 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1184 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1185 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1186 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1187 /* 87 - 2560x1080@25Hz 64:27 */
8ec6e075
SS		 1188 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1189 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1190 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1191 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1192 /* 88 - 2560x1080@30Hz 64:27 */
8ec6e075
SS		 1193 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1194 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1195 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1196 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1197 /* 89 - 2560x1080@50Hz 64:27 */
8ec6e075
SS		 1198 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1199 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1200 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1201 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1202 /* 90 - 2560x1080@60Hz 64:27 */
8ec6e075
SS		 1203 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1204 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1205 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1206 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1207 /* 91 - 2560x1080@100Hz 64:27 */
8ec6e075
SS		 1208 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1209 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1210 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1211 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1212 /* 92 - 2560x1080@120Hz 64:27 */
8ec6e075
SS		 1213 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1214 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1215 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1216 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1217 /* 93 - 3840x2160@24Hz 16:9 */
8ec6e075
SS		 1218 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1219 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1220 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1221 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1222 /* 94 - 3840x2160@25Hz 16:9 */
8ec6e075
SS		 1223 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1224 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1225 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1226 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1227 /* 95 - 3840x2160@30Hz 16:9 */
8ec6e075
SS		 1228 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1229 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1230 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1231 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1232 /* 96 - 3840x2160@50Hz 16:9 */
8ec6e075
SS		 1233 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1234 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1235 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1236 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1237 /* 97 - 3840x2160@60Hz 16:9 */
8ec6e075
SS		 1238 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1239 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1240 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1241 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1242 /* 98 - 4096x2160@24Hz 256:135 */
8ec6e075
SS		 1243 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1244 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1245 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1246 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1247 /* 99 - 4096x2160@25Hz 256:135 */
8ec6e075
SS		 1248 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1249 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1250 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1251 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1252 /* 100 - 4096x2160@30Hz 256:135 */
8ec6e075
SS		 1253 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1254 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1255 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1256 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1257 /* 101 - 4096x2160@50Hz 256:135 */
8ec6e075
SS		 1258 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1259 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1260 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1261 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1262 /* 102 - 4096x2160@60Hz 256:135 */
8ec6e075
SS		 1263 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1264 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1265 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1266 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1267 /* 103 - 3840x2160@24Hz 64:27 */
8ec6e075
SS		 1268 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1269 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1270 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1271 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1272 /* 104 - 3840x2160@25Hz 64:27 */
8ec6e075
SS		 1273 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1274 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1275 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1276 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1277 /* 105 - 3840x2160@30Hz 64:27 */
8ec6e075
SS		 1278 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1279 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1281 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1282 /* 106 - 3840x2160@50Hz 64:27 */
8ec6e075
SS		 1283 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1284 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1285 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1286 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1287 /* 107 - 3840x2160@60Hz 64:27 */
8ec6e075
SS		 1288 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1289 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1290 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1291 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1292 /* 108 - 1280x720@48Hz 16:9 */
1293 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1294 2280, 2500, 0, 720, 725, 730, 750, 0,
1295 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1296 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1297 /* 109 - 1280x720@48Hz 64:27 */
1298 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1299 2280, 2500, 0, 720, 725, 730, 750, 0,
1300 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1301 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1302 /* 110 - 1680x720@48Hz 64:27 */
1303 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490,
1304 2530, 2750, 0, 720, 725, 730, 750, 0,
1305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1306 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1307 /* 111 - 1920x1080@48Hz 16:9 */
1308 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1309 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1310 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1311 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1312 /* 112 - 1920x1080@48Hz 64:27 */
1313 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1314 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1315 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1316 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1317 /* 113 - 2560x1080@48Hz 64:27 */
1318 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558,
1319 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1320 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1321 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1322 /* 114 - 3840x2160@48Hz 16:9 */
1323 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1324 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1325 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1326 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1327 /* 115 - 4096x2160@48Hz 256:135 */
1328 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116,
1329 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1330 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1331 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
978f6b06
VS		 1332 /* 116 - 3840x2160@48Hz 64:27 */
1333 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1334 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1335 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1336 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1337 /* 117 - 3840x2160@100Hz 16:9 */
1338 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1339 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1340 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1341 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1342 /* 118 - 3840x2160@120Hz 16:9 */
1343 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1344 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1345 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1346 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1347 /* 119 - 3840x2160@100Hz 64:27 */
1348 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1349 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1350 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1351 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1352 /* 120 - 3840x2160@120Hz 64:27 */
1353 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1354 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1355 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1356 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1357 /* 121 - 5120x2160@24Hz 64:27 */
1358 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116,
1359 7204, 7500, 0, 2160, 2168, 2178, 2200, 0,
1360 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1361 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1362 /* 122 - 5120x2160@25Hz 64:27 */
1363 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816,
1364 6904, 7200, 0, 2160, 2168, 2178, 2200, 0,
1365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1366 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1367 /* 123 - 5120x2160@30Hz 64:27 */
1368 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784,
1369 5872, 6000, 0, 2160, 2168, 2178, 2200, 0,
1370 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1371 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1372 /* 124 - 5120x2160@48Hz 64:27 */
1373 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866,
1374 5954, 6250, 0, 2160, 2168, 2178, 2475, 0,
1375 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1376 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1377 /* 125 - 5120x2160@50Hz 64:27 */
1378 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216,
1379 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1380 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1381 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1382 /* 126 - 5120x2160@60Hz 64:27 */
1383 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284,
1384 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1386 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1387 /* 127 - 5120x2160@100Hz 64:27 */
1388 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216,
1389 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1390 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1391 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
a6b21831
TR		 1392};
1393
f7655d42
VS		 1394/*
1395 * From CEA/CTA-861 spec.
1396 *
1397 * Do not access directly, instead always use cea_mode_for_vic().
1398 */
1399static const struct drm_display_mode edid_cea_modes_193[] = {
1400 /* 193 - 5120x2160@120Hz 64:27 */
1401 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284,
1402 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1403 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1404 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1405 /* 194 - 7680x4320@24Hz 16:9 */
1406 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1407 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1408 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1409 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1410 /* 195 - 7680x4320@25Hz 16:9 */
1411 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1412 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1413 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1414 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1415 /* 196 - 7680x4320@30Hz 16:9 */
1416 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1417 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1418 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1419 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1420 /* 197 - 7680x4320@48Hz 16:9 */
1421 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1422 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1423 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1424 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1425 /* 198 - 7680x4320@50Hz 16:9 */
1426 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1427 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1428 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1429 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1430 /* 199 - 7680x4320@60Hz 16:9 */
1431 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1432 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1433 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1434 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1435 /* 200 - 7680x4320@100Hz 16:9 */
1436 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1437 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1438 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1439 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1440 /* 201 - 7680x4320@120Hz 16:9 */
1441 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1442 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1443 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1444 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1445 /* 202 - 7680x4320@24Hz 64:27 */
1446 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1447 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1448 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1449 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1450 /* 203 - 7680x4320@25Hz 64:27 */
1451 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1452 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1454 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1455 /* 204 - 7680x4320@30Hz 64:27 */
1456 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1457 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1458 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1459 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1460 /* 205 - 7680x4320@48Hz 64:27 */
1461 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1462 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1463 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1464 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1465 /* 206 - 7680x4320@50Hz 64:27 */
1466 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1467 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1468 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1469 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1470 /* 207 - 7680x4320@60Hz 64:27 */
1471 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1472 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1473 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1474 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1475 /* 208 - 7680x4320@100Hz 64:27 */
1476 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1477 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1478 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1479 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1480 /* 209 - 7680x4320@120Hz 64:27 */
1481 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1482 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1483 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1484 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1485 /* 210 - 10240x4320@24Hz 64:27 */
1486 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732,
1487 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1488 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1489 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1490 /* 211 - 10240x4320@25Hz 64:27 */
1491 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732,
1492 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1493 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1494 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1495 /* 212 - 10240x4320@30Hz 64:27 */
1496 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528,
1497 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1498 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1499 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1500 /* 213 - 10240x4320@48Hz 64:27 */
1501 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732,
1502 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1503 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1504 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1505 /* 214 - 10240x4320@50Hz 64:27 */
1506 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732,
1507 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1508 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1509 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1510 /* 215 - 10240x4320@60Hz 64:27 */
1511 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528,
1512 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1513 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1514 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1515 /* 216 - 10240x4320@100Hz 64:27 */
1516 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432,
1517 12608, 13200, 0, 4320, 4336, 4356, 4500, 0,
1518 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1519 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1520 /* 217 - 10240x4320@120Hz 64:27 */
1521 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528,
1522 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1523 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1524 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1525 /* 218 - 4096x2160@100Hz 256:135 */
1526 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896,
1527 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1528 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1529 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
f7655d42
VS		 1530 /* 219 - 4096x2160@120Hz 256:135 */
1531 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184,
1532 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1533 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1534 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
f7655d42
VS		 1535};
1536
7ebe1963 1537/*
d9278b4c 1538 * HDMI 1.4 4k modes. Index using the VIC.
7ebe1963
LD		 1539 */
1540static const struct drm_display_mode edid_4k_modes[] = {
d9278b4c
JN		 1541 /* 0 - dummy, VICs start at 1 */
1542 { },
7ebe1963
LD		 1543 /* 1 - 3840x2160@30Hz */
1544 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1545 3840, 4016, 4104, 4400, 0,
1546 2160, 2168, 2178, 2250, 0,
1547 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1548 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
7ebe1963
LD		 1549 /* 2 - 3840x2160@25Hz */
1550 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1551 3840, 4896, 4984, 5280, 0,
1552 2160, 2168, 2178, 2250, 0,
1553 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1554 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
7ebe1963
LD		 1555 /* 3 - 3840x2160@24Hz */
1556 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1557 3840, 5116, 5204, 5500, 0,
1558 2160, 2168, 2178, 2250, 0,
1559 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1560 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
7ebe1963
LD		 1561 /* 4 - 4096x2160@24Hz (SMPTE) */
1562 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1563 4096, 5116, 5204, 5500, 0,
1564 2160, 2168, 2178, 2250, 0,
1565 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1566 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
7ebe1963
LD		 1567};
1568
61e57a8d 1569/*** DDC fetch and block validation ***/
f453ba04 1570
083ae056
AJ		 1571static const u8 edid_header[] = {
1572 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1573};
f453ba04 1574
0a612bbd
JN		 1575static void edid_header_fix(void *edid)
1576{
1577 memcpy(edid, edid_header, sizeof(edid_header));
1578}
1579
db6cf833
TR		 1580/**
1581 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1582 * @raw_edid: pointer to raw base EDID block
1583 *
1584 * Sanity check the header of the base EDID block.
1585 *
1586 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
051963d4 1587 */
6d987ddd 1588int drm_edid_header_is_valid(const void *_edid)
051963d4 1589{
6d987ddd 1590 const struct edid *edid = _edid;
051963d4
TR		 1591 int i, score = 0;
1592
6d987ddd
JN		 1593 for (i = 0; i < sizeof(edid_header); i++) {
1594 if (edid->header[i] == edid_header[i])
051963d4 1595 score++;
6d987ddd 1596 }
051963d4
TR		 1597
1598 return score;
1599}
1600EXPORT_SYMBOL(drm_edid_header_is_valid);
1601
47819ba2
AJ		 1602static int edid_fixup __read_mostly = 6;
1603module_param_named(edid_fixup, edid_fixup, int, 0400);
1604MODULE_PARM_DESC(edid_fixup,
1605 "Minimum number of valid EDID header bytes (0-8, default 6)");
051963d4 1606
70e49ebe 1607static int edid_block_compute_checksum(const void *_block)
c465bbc8 1608{
70e49ebe 1609 const u8 *block = _block;
c465bbc8 1610 int i;
e11f5bd8
JFZ		 1611 u8 csum = 0, crc = 0;
1612
1613 for (i = 0; i < EDID_LENGTH - 1; i++)
70e49ebe 1614 csum += block[i];
c465bbc8 1615
e11f5bd8
JFZ		 1616 crc = 0x100 - csum;
1617
1618 return crc;
1619}
1620
70e49ebe 1621static int edid_block_get_checksum(const void *_block)
e11f5bd8 1622{
70e49ebe
JN		 1623 const struct edid *block = _block;
1624
1625 return block->checksum;
c465bbc8
SB		 1626}
1627
4ba0f53c
JN		 1628static int edid_block_tag(const void *_block)
1629{
1630 const u8 *block = _block;
1631
1632 return block[0];
1633}
1634
aa6292a3 1635static bool edid_is_zero(const void *edid, int length)
d6885d65 1636{
aa6292a3 1637 return !memchr_inv(edid, 0, length);
d6885d65
SB		 1638}
1639
536faa45
SL		 1640/**
1641 * drm_edid_are_equal - compare two edid blobs.
1642 * @edid1: pointer to first blob
1643 * @edid2: pointer to second blob
1644 * This helper can be used during probing to determine if
1645 * edid had changed.
1646 */
1647bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2)
1648{
1649 int edid1_len, edid2_len;
1650 bool edid1_present = edid1 != NULL;
1651 bool edid2_present = edid2 != NULL;
1652
1653 if (edid1_present != edid2_present)
1654 return false;
1655
1656 if (edid1) {
536faa45
SL		 1657 edid1_len = EDID_LENGTH * (1 + edid1->extensions);
1658 edid2_len = EDID_LENGTH * (1 + edid2->extensions);
1659
1660 if (edid1_len != edid2_len)
1661 return false;
1662
1663 if (memcmp(edid1, edid2, edid1_len))
1664 return false;
1665 }
1666
1667 return true;
1668}
1669EXPORT_SYMBOL(drm_edid_are_equal);
1670
1f221284
JN		 1671enum edid_block_status {
1672 EDID_BLOCK_OK = 0,
1673 EDID_BLOCK_NULL,
1674 EDID_BLOCK_HEADER_CORRUPT,
1675 EDID_BLOCK_HEADER_REPAIR,
1676 EDID_BLOCK_HEADER_FIXED,
1677 EDID_BLOCK_CHECKSUM,
1678 EDID_BLOCK_VERSION,
1679};
1680
1681static enum edid_block_status edid_block_check(const void *_block,
1682 bool is_base_block)
1683{
1684 const struct edid *block = _block;
1685
1686 if (!block)
1687 return EDID_BLOCK_NULL;
1688
1689 if (is_base_block) {
1690 int score = drm_edid_header_is_valid(block);
1691
1692 if (score < clamp(edid_fixup, 0, 8))
1693 return EDID_BLOCK_HEADER_CORRUPT;
1694
1695 if (score < 8)
1696 return EDID_BLOCK_HEADER_REPAIR;
1697 }
1698
1699 if (edid_block_compute_checksum(block) != edid_block_get_checksum(block))
1700 return EDID_BLOCK_CHECKSUM;
1701
1702 if (is_base_block) {
1703 if (block->version != 1)
1704 return EDID_BLOCK_VERSION;
1705 }
1706
1707 return EDID_BLOCK_OK;
1708}
1709
1710static bool edid_block_status_valid(enum edid_block_status status, int tag)
1711{
1712 return status == EDID_BLOCK_OK ||
1713 status == EDID_BLOCK_HEADER_FIXED ||
1714 (status == EDID_BLOCK_CHECKSUM && tag == CEA_EXT);
1715}
1716
23e38d7b
JN		 1717static bool edid_block_valid(const void *block, bool base)
1718{
1719 return edid_block_status_valid(edid_block_check(block, base),
1720 edid_block_tag(block));
1721}
1722
db6cf833
TR		 1723/**
1724 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1725 * @raw_edid: pointer to raw EDID block
1f221284 1726 * @block_num: type of block to validate (0 for base, extension otherwise)
db6cf833 1727 * @print_bad_edid: if true, dump bad EDID blocks to the console
6ba2bd3d 1728 * @edid_corrupt: if true, the header or checksum is invalid
db6cf833
TR		 1729 *
1730 * Validate a base or extension EDID block and optionally dump bad blocks to
1731 * the console.
1732 *
1733 * Return: True if the block is valid, false otherwise.
f453ba04 1734 */
1f221284 1735bool drm_edid_block_valid(u8 *_block, int block_num, bool print_bad_edid,
6ba2bd3d 1736 bool *edid_corrupt)
f453ba04 1737{
1f221284
JN		 1738 struct edid *block = (struct edid *)_block;
1739 enum edid_block_status status;
1740 bool is_base_block = block_num == 0;
1741 bool valid;
f453ba04 1742
1f221284 1743 if (WARN_ON(!block))
fe2ef780
SWK		 1744 return false;
1745
1f221284
JN		 1746 status = edid_block_check(block, is_base_block);
1747 if (status == EDID_BLOCK_HEADER_REPAIR) {
1748 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1749 edid_header_fix(block);
1750
1751 /* Retry with fixed header, update status if that worked. */
1752 status = edid_block_check(block, is_base_block);
1753 if (status == EDID_BLOCK_OK)
1754 status = EDID_BLOCK_HEADER_FIXED;
61e57a8d 1755 }
f453ba04 1756
1f221284
JN		 1757 if (edid_corrupt) {
1758 /*
1759 * Unknown major version isn't corrupt but we can't use it. Only
1760 * the base block can reset edid_corrupt to false.
1761 */
1762 if (is_base_block &&
1763 (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION))
1764 *edid_corrupt = false;
1765 else if (status != EDID_BLOCK_OK)
ac6f2e29 1766 *edid_corrupt = true;
f453ba04
DA		 1767 }
1768
1f221284
JN		 1769 /* Determine whether we can use this block with this status. */
1770 valid = edid_block_status_valid(status, edid_block_tag(block));
1771
1772 /* Some fairly random status printouts. */
1773 if (status == EDID_BLOCK_CHECKSUM) {
1774 if (valid) {
1775 DRM_DEBUG("EDID block checksum is invalid, remainder is %d\n",
1776 edid_block_compute_checksum(block));
1777 DRM_DEBUG("Assuming a KVM switch modified the block but left the original checksum\n");
1778 } else if (print_bad_edid) {
1779 DRM_NOTE("EDID block checksum is invalid, remainder is %d\n",
1780 edid_block_compute_checksum(block));
61e57a8d 1781 }
1f221284
JN		 1782 } else if (status == EDID_BLOCK_VERSION) {
1783 DRM_NOTE("EDID has major version %d, instead of 1\n",
1784 block->version);
61e57a8d 1785 }
47ee4ccf 1786
1f221284
JN		 1787 if (!valid && print_bad_edid) {
1788 if (edid_is_zero(block, EDID_LENGTH)) {
499447db 1789 pr_notice("EDID block is all zeroes\n");
da4c07b7 1790 } else {
499447db 1791 pr_notice("Raw EDID:\n");
813a7878
CW		 1792 print_hex_dump(KERN_NOTICE,
1793 " \t", DUMP_PREFIX_NONE, 16, 1,
1f221284 1794 block, EDID_LENGTH, false);
da4c07b7 1795 }
f453ba04 1796 }
1f221284
JN		 1797
1798 return valid;
f453ba04 1799}
da0df92b 1800EXPORT_SYMBOL(drm_edid_block_valid);
61e57a8d
AJ		 1801
1802/**
1803 * drm_edid_is_valid - sanity check EDID data
1804 * @edid: EDID data
1805 *
1806 * Sanity-check an entire EDID record (including extensions)
db6cf833
TR		 1807 *
1808 * Return: True if the EDID data is valid, false otherwise.
61e57a8d
AJ		 1809 */
1810bool drm_edid_is_valid(struct edid *edid)
1811{
1812 int i;
1813 u8 *raw = (u8 *)edid;
1814
1815 if (!edid)
1816 return false;
1817
1818 for (i = 0; i <= edid->extensions; i++)
6ba2bd3d 1819 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
61e57a8d
AJ		 1820 return false;
1821
1822 return true;
1823}
3c537889 1824EXPORT_SYMBOL(drm_edid_is_valid);
f453ba04 1825
4ec53461 1826static struct edid *edid_filter_invalid_blocks(const struct edid *edid,
ccc97def 1827 int invalid_blocks)
4ec53461
JN		 1828{
1829 struct edid *new, *dest_block;
ccc97def 1830 int valid_extensions = edid->extensions - invalid_blocks;
4ec53461
JN		 1831 int i;
1832
1833 new = kmalloc_array(valid_extensions + 1, EDID_LENGTH, GFP_KERNEL);
1834 if (!new)
1835 goto out;
1836
1837 dest_block = new;
1838 for (i = 0; i <= edid->extensions; i++) {
1839 const void *block = edid + i;
1840
1841 if (edid_block_valid(block, i == 0))
1842 memcpy(dest_block++, block, EDID_LENGTH);
1843 }
1844
4ec53461 1845 new->extensions = valid_extensions;
ab0609a5 1846 new->checksum = edid_block_compute_checksum(new);
4ec53461
JN		 1847
1848out:
1849 kfree(edid);
1850
1851 return new;
1852}
1853
61e57a8d
AJ		 1854#define DDC_SEGMENT_ADDR 0x30
1855/**
db6cf833 1856 * drm_do_probe_ddc_edid() - get EDID information via I2C
7c58e87e 1857 * @data: I2C device adapter
fc66811c
DV		 1858 * @buf: EDID data buffer to be filled
1859 * @block: 128 byte EDID block to start fetching from
1860 * @len: EDID data buffer length to fetch
1861 *
db6cf833 1862 * Try to fetch EDID information by calling I2C driver functions.
61e57a8d 1863 *
db6cf833 1864 * Return: 0 on success or -1 on failure.
61e57a8d
AJ		 1865 */
1866static int
18df89fe 1867drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
61e57a8d 1868{
18df89fe 1869 struct i2c_adapter *adapter = data;
61e57a8d 1870 unsigned char start = block * EDID_LENGTH;
cd004b3f
S		 1871 unsigned char segment = block >> 1;
1872 unsigned char xfers = segment ? 3 : 2;
4819d2e4
CW		 1873 int ret, retries = 5;
1874
db6cf833
TR		 1875 /*
1876 * The core I2C driver will automatically retry the transfer if the
4819d2e4
CW		 1877 * adapter reports EAGAIN. However, we find that bit-banging transfers
1878 * are susceptible to errors under a heavily loaded machine and
1879 * generate spurious NAKs and timeouts. Retrying the transfer
1880 * of the individual block a few times seems to overcome this.
1881 */
1882 do {
1883 struct i2c_msg msgs[] = {
1884 {
cd004b3f
S		 1885 .addr = DDC_SEGMENT_ADDR,
1886 .flags = 0,
1887 .len = 1,
1888 .buf = &segment,
1889 }, {
4819d2e4
CW		 1890 .addr = DDC_ADDR,
1891 .flags = 0,
1892 .len = 1,
1893 .buf = &start,
1894 }, {
1895 .addr = DDC_ADDR,
1896 .flags = I2C_M_RD,
1897 .len = len,
1898 .buf = buf,
1899 }
1900 };
cd004b3f 1901
db6cf833
TR		 1902 /*
1903 * Avoid sending the segment addr to not upset non-compliant
1904 * DDC monitors.
1905 */
cd004b3f
S		 1906 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1907
9292f37e
ED		 1908 if (ret == -ENXIO) {
1909 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1910 adapter->name);
1911 break;
1912 }
cd004b3f 1913 } while (ret != xfers && --retries);
4819d2e4 1914
cd004b3f 1915 return ret == xfers ? 0 : -1;
61e57a8d
AJ		 1916}
1917
14544d09
CW		 1918static void connector_bad_edid(struct drm_connector *connector,
1919 u8 *edid, int num_blocks)
1920{
1921 int i;
97794170
DA		 1922 u8 last_block;
1923
1924 /*
1925 * 0x7e in the EDID is the number of extension blocks. The EDID
1926 * is 1 (base block) + num_ext_blocks big. That means we can think
1927 * of 0x7e in the EDID of the _index_ of the last block in the
1928 * combined chunk of memory.
1929 */
1930 last_block = edid[0x7e];
e11f5bd8
JFZ		 1931
1932 /* Calculate real checksum for the last edid extension block data */
97794170
DA		 1933 if (last_block < num_blocks)
1934 connector->real_edid_checksum =
70e49ebe 1935 edid_block_compute_checksum(edid + last_block * EDID_LENGTH);
14544d09 1936
f0a8f533 1937 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
14544d09
CW		 1938 return;
1939
fa3bfa35 1940 drm_dbg_kms(connector->dev, "%s: EDID is invalid:\n", connector->name);
14544d09
CW		 1941 for (i = 0; i < num_blocks; i++) {
1942 u8 *block = edid + i * EDID_LENGTH;
1943 char prefix[20];
1944
aa6292a3 1945 if (edid_is_zero(block, EDID_LENGTH))
14544d09
CW		 1946 sprintf(prefix, "\t[%02x] ZERO ", i);
1947 else if (!drm_edid_block_valid(block, i, false, NULL))
1948 sprintf(prefix, "\t[%02x] BAD ", i);
1949 else
1950 sprintf(prefix, "\t[%02x] GOOD ", i);
1951
fa3bfa35 1952 print_hex_dump(KERN_DEBUG,
14544d09
CW		 1953 prefix, DUMP_PREFIX_NONE, 16, 1,
1954 block, EDID_LENGTH, false);
1955 }
1956}
1957
56a2b7f2
JN		 1958/* Get override or firmware EDID */
1959static struct edid *drm_get_override_edid(struct drm_connector *connector)
1960{
1961 struct edid *override = NULL;
1962
1963 if (connector->override_edid)
1964 override = drm_edid_duplicate(connector->edid_blob_ptr->data);
1965
1966 if (!override)
1967 override = drm_load_edid_firmware(connector);
1968
1969 return IS_ERR(override) ? NULL : override;
1970}
1971
48eaeb76
JN		 1972/**
1973 * drm_add_override_edid_modes - add modes from override/firmware EDID
1974 * @connector: connector we're probing
1975 *
1976 * Add modes from the override/firmware EDID, if available. Only to be used from
1977 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
1978 * failed during drm_get_edid() and caused the override/firmware EDID to be
1979 * skipped.
1980 *
1981 * Return: The number of modes added or 0 if we couldn't find any.
1982 */
1983int drm_add_override_edid_modes(struct drm_connector *connector)
1984{
1985 struct edid *override;
1986 int num_modes = 0;
1987
1988 override = drm_get_override_edid(connector);
1989 if (override) {
1990 drm_connector_update_edid_property(connector, override);
1991 num_modes = drm_add_edid_modes(connector, override);
1992 kfree(override);
1993
1994 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
1995 connector->base.id, connector->name, num_modes);
1996 }
1997
1998 return num_modes;
1999}
2000EXPORT_SYMBOL(drm_add_override_edid_modes);
2001
e7bd95a7 2002static struct edid *drm_do_get_edid_base_block(struct drm_connector *connector,
bac9c294
DA		 2003 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
2004 size_t len),
e7bd95a7 2005 void *data)
bac9c294 2006{
e7bd95a7
DA		 2007 int *null_edid_counter = connector ? &connector->null_edid_counter : NULL;
2008 bool *edid_corrupt = connector ? &connector->edid_corrupt : NULL;
bac9c294 2009 void *edid;
18d83450 2010 int try;
bac9c294
DA		 2011
2012 edid = kmalloc(EDID_LENGTH, GFP_KERNEL);
2013 if (edid == NULL)
2014 return NULL;
2015
2016 /* base block fetch */
18d83450 2017 for (try = 0; try < 4; try++) {
bac9c294
DA		 2018 if (get_edid_block(data, edid, 0, EDID_LENGTH))
2019 goto out;
2020 if (drm_edid_block_valid(edid, 0, false, edid_corrupt))
2021 break;
18d83450 2022 if (try == 0 && edid_is_zero(edid, EDID_LENGTH)) {
bac9c294
DA		 2023 if (null_edid_counter)
2024 (*null_edid_counter)++;
2025 goto carp;
2026 }
2027 }
18d83450 2028 if (try == 4)
bac9c294
DA		 2029 goto carp;
2030
2031 return edid;
2032
2033carp:
e7bd95a7
DA		 2034 if (connector)
2035 connector_bad_edid(connector, edid, 1);
bac9c294
DA		 2036out:
2037 kfree(edid);
2038 return NULL;
2039}
2040
18df89fe
LPC		 2041/**
2042 * drm_do_get_edid - get EDID data using a custom EDID block read function
2043 * @connector: connector we're probing
2044 * @get_edid_block: EDID block read function
2045 * @data: private data passed to the block read function
2046 *
2047 * When the I2C adapter connected to the DDC bus is hidden behind a device that
2048 * exposes a different interface to read EDID blocks this function can be used
2049 * to get EDID data using a custom block read function.
2050 *
2051 * As in the general case the DDC bus is accessible by the kernel at the I2C
2052 * level, drivers must make all reasonable efforts to expose it as an I2C
2053 * adapter and use drm_get_edid() instead of abusing this function.
2054 *
0ae865ef 2055 * The EDID may be overridden using debugfs override_edid or firmware EDID
53fd40a9
JN		 2056 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
2057 * order. Having either of them bypasses actual EDID reads.
2058 *
18df89fe
LPC		 2059 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2060 */
2061struct edid *drm_do_get_edid(struct drm_connector *connector,
2062 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
2063 size_t len),
2064 void *data)
61e57a8d 2065{
ccc97def 2066 int j, invalid_blocks = 0;
e9a9e076 2067 struct edid *edid, *new, *override;
53fd40a9 2068
56a2b7f2
JN		 2069 override = drm_get_override_edid(connector);
2070 if (override)
53fd40a9 2071 return override;
61e57a8d 2072
e9a9e076 2073 edid = drm_do_get_edid_base_block(connector, get_edid_block, data);
e7bd95a7 2074 if (!edid)
61e57a8d 2075 return NULL;
61e57a8d 2076
ccc97def 2077 if (edid->extensions == 0)
e9a9e076 2078 return edid;
61e57a8d 2079
ccc97def 2080 new = krealloc(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
61e57a8d
AJ		 2081 if (!new)
2082 goto out;
f14f3686 2083 edid = new;
61e57a8d 2084
e9a9e076
JN		 2085 for (j = 1; j <= edid->extensions; j++) {
2086 void *block = edid + j;
18d83450 2087 int try;
a28187cc 2088
18d83450 2089 for (try = 0; try < 4; try++) {
a28187cc 2090 if (get_edid_block(data, block, j, EDID_LENGTH))
61e57a8d 2091 goto out;
14544d09 2092 if (drm_edid_block_valid(block, j, false, NULL))
61e57a8d
AJ		 2093 break;
2094 }
f934ec8c 2095
18d83450 2096 if (try == 4)
ccc97def 2097 invalid_blocks++;
0ea75e23
ST		 2098 }
2099
ccc97def 2100 if (invalid_blocks) {
e9a9e076 2101 connector_bad_edid(connector, (u8 *)edid, edid->extensions + 1);
14544d09 2102
ccc97def 2103 edid = edid_filter_invalid_blocks(edid, invalid_blocks);
61e57a8d
AJ		 2104 }
2105
e9a9e076 2106 return edid;
61e57a8d 2107
61e57a8d 2108out:
f14f3686 2109 kfree(edid);
61e57a8d
AJ		 2110 return NULL;
2111}
18df89fe 2112EXPORT_SYMBOL_GPL(drm_do_get_edid);
61e57a8d
AJ		 2113
2114/**
db6cf833
TR		 2115 * drm_probe_ddc() - probe DDC presence
2116 * @adapter: I2C adapter to probe
fc66811c 2117 *
db6cf833 2118 * Return: True on success, false on failure.
61e57a8d 2119 */
fbff4690 2120bool
61e57a8d
AJ		 2121drm_probe_ddc(struct i2c_adapter *adapter)
2122{
2123 unsigned char out;
2124
2125 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
2126}
fbff4690 2127EXPORT_SYMBOL(drm_probe_ddc);
61e57a8d
AJ		 2128
2129/**
2130 * drm_get_edid - get EDID data, if available
2131 * @connector: connector we're probing
db6cf833 2132 * @adapter: I2C adapter to use for DDC
61e57a8d 2133 *
db6cf833 2134 * Poke the given I2C channel to grab EDID data if possible. If found,
61e57a8d
AJ		 2135 * attach it to the connector.
2136 *
db6cf833 2137 * Return: Pointer to valid EDID or NULL if we couldn't find any.
61e57a8d
AJ		 2138 */
2139struct edid *drm_get_edid(struct drm_connector *connector,
2140 struct i2c_adapter *adapter)
2141{
5186421c
SL		 2142 struct edid *edid;
2143
15f080f0
JN		 2144 if (connector->force == DRM_FORCE_OFF)
2145 return NULL;
2146
2147 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
18df89fe 2148 return NULL;
61e57a8d 2149
5186421c
SL		 2150 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
2151 drm_connector_update_edid_property(connector, edid);
2152 return edid;
61e57a8d
AJ		 2153}
2154EXPORT_SYMBOL(drm_get_edid);
2155
d9f91a10
DA		 2156static u32 edid_extract_panel_id(const struct edid *edid)
2157{
2158 /*
e8de4d55
DA		 2159 * We represent the ID as a 32-bit number so it can easily be compared
2160 * with "==".
d9f91a10
DA		 2161 *
2162 * NOTE that we deal with endianness differently for the top half
2163 * of this ID than for the bottom half. The bottom half (the product
2164 * id) gets decoded as little endian by the EDID_PRODUCT_ID because
2165 * that's how everyone seems to interpret it. The top half (the mfg_id)
2166 * gets stored as big endian because that makes
2167 * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier
2168 * to write (it's easier to extract the ASCII). It doesn't really
2169 * matter, though, as long as the number here is unique.
2170 */
2171 return (u32)edid->mfg_id[0] << 24 |
2172 (u32)edid->mfg_id[1] << 16 |
2173 (u32)EDID_PRODUCT_ID(edid);
2174}
2175
2176/**
2177 * drm_edid_get_panel_id - Get a panel's ID through DDC
2178 * @adapter: I2C adapter to use for DDC
2179 *
2180 * This function reads the first block of the EDID of a panel and (assuming
2181 * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value
2182 * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's
2183 * supposed to be different for each different modem of panel.
2184 *
2185 * This function is intended to be used during early probing on devices where
2186 * more than one panel might be present. Because of its intended use it must
2187 * assume that the EDID of the panel is correct, at least as far as the ID
2188 * is concerned (in other words, we don't process any overrides here).
2189 *
2190 * NOTE: it's expected that this function and drm_do_get_edid() will both
2191 * be read the EDID, but there is no caching between them. Since we're only
2192 * reading the first block, hopefully this extra overhead won't be too big.
2193 *
2194 * Return: A 32-bit ID that should be different for each make/model of panel.
2195 * See the functions drm_edid_encode_panel_id() and
2196 * drm_edid_decode_panel_id() for some details on the structure of this
2197 * ID.
2198 */
2199
2200u32 drm_edid_get_panel_id(struct i2c_adapter *adapter)
2201{
f4e558ec 2202 const struct edid *edid;
d9f91a10
DA		 2203 u32 panel_id;
2204
e7bd95a7 2205 edid = drm_do_get_edid_base_block(NULL, drm_do_probe_ddc_edid, adapter);
d9f91a10
DA		 2206
2207 /*
2208 * There are no manufacturer IDs of 0, so if there is a problem reading
2209 * the EDID then we'll just return 0.
2210 */
e7bd95a7 2211 if (!edid)
d9f91a10
DA		 2212 return 0;
2213
2214 panel_id = edid_extract_panel_id(edid);
2215 kfree(edid);
2216
2217 return panel_id;
2218}
2219EXPORT_SYMBOL(drm_edid_get_panel_id);
2220
5cb8eaa2
LW		 2221/**
2222 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
2223 * @connector: connector we're probing
2224 * @adapter: I2C adapter to use for DDC
2225 *
2226 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
2227 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
2228 * switch DDC to the GPU which is retrieving EDID.
2229 *
2230 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2231 */
2232struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
2233 struct i2c_adapter *adapter)
2234{
36b73b05
TZ		 2235 struct drm_device *dev = connector->dev;
2236 struct pci_dev *pdev = to_pci_dev(dev->dev);
5cb8eaa2
LW		 2237 struct edid *edid;
2238
36b73b05
TZ		 2239 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev)))
2240 return NULL;
2241
5cb8eaa2
LW		 2242 vga_switcheroo_lock_ddc(pdev);
2243 edid = drm_get_edid(connector, adapter);
2244 vga_switcheroo_unlock_ddc(pdev);
2245
2246 return edid;
2247}
2248EXPORT_SYMBOL(drm_get_edid_switcheroo);
2249
51f8da59
JN		 2250/**
2251 * drm_edid_duplicate - duplicate an EDID and the extensions
2252 * @edid: EDID to duplicate
2253 *
db6cf833 2254 * Return: Pointer to duplicated EDID or NULL on allocation failure.
51f8da59
JN		 2255 */
2256struct edid *drm_edid_duplicate(const struct edid *edid)
2257{
2258 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
2259}
2260EXPORT_SYMBOL(drm_edid_duplicate);
2261
61e57a8d
AJ		 2262/*** EDID parsing ***/
2263
f453ba04
DA		 2264/**
2265 * edid_get_quirks - return quirk flags for a given EDID
2266 * @edid: EDID to process
2267 *
2268 * This tells subsequent routines what fixes they need to apply.
2269 */
170178fe 2270static u32 edid_get_quirks(const struct edid *edid)
f453ba04 2271{
e8de4d55 2272 u32 panel_id = edid_extract_panel_id(edid);
23c4cfbd 2273 const struct edid_quirk *quirk;
f453ba04
DA		 2274 int i;
2275
2276 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
2277 quirk = &edid_quirk_list[i];
e8de4d55 2278 if (quirk->panel_id == panel_id)
f453ba04
DA		 2279 return quirk->quirks;
2280 }
2281
2282 return 0;
2283}
2284
2285#define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
339d202c 2286#define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
f453ba04 2287
f453ba04
DA		 2288/**
2289 * edid_fixup_preferred - set preferred modes based on quirk list
2290 * @connector: has mode list to fix up
2291 * @quirks: quirks list
2292 *
2293 * Walk the mode list for @connector, clearing the preferred status
2294 * on existing modes and setting it anew for the right mode ala @quirks.
2295 */
2296static void edid_fixup_preferred(struct drm_connector *connector,
2297 u32 quirks)
2298{
2299 struct drm_display_mode *t, *cur_mode, *preferred_mode;
f890607b 2300 int target_refresh = 0;
339d202c 2301 int cur_vrefresh, preferred_vrefresh;
f453ba04
DA		 2302
2303 if (list_empty(&connector->probed_modes))
2304 return;
2305
2306 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
2307 target_refresh = 60;
2308 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
2309 target_refresh = 75;
2310
2311 preferred_mode = list_first_entry(&connector->probed_modes,
2312 struct drm_display_mode, head);
2313
2314 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
2315 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
2316
2317 if (cur_mode == preferred_mode)
2318 continue;
2319
2320 /* Largest mode is preferred */
2321 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
2322 preferred_mode = cur_mode;
2323
0425662f
VS		 2324 cur_vrefresh = drm_mode_vrefresh(cur_mode);
2325 preferred_vrefresh = drm_mode_vrefresh(preferred_mode);
f453ba04
DA		 2326 /* At a given size, try to get closest to target refresh */
2327 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
339d202c
AD		 2328 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
2329 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
f453ba04
DA		 2330 preferred_mode = cur_mode;
2331 }
2332 }
2333
2334 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
2335}
2336
f6e252ba
AJ		 2337static bool
2338mode_is_rb(const struct drm_display_mode *mode)
2339{
2340 return (mode->htotal - mode->hdisplay == 160) &&
2341 (mode->hsync_end - mode->hdisplay == 80) &&
2342 (mode->hsync_end - mode->hsync_start == 32) &&
2343 (mode->vsync_start - mode->vdisplay == 3);
2344}
2345
33c7531d
AJ		 2346/*
2347 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
2348 * @dev: Device to duplicate against
2349 * @hsize: Mode width
2350 * @vsize: Mode height
2351 * @fresh: Mode refresh rate
f6e252ba 2352 * @rb: Mode reduced-blanking-ness
33c7531d
AJ		 2353 *
2354 * Walk the DMT mode list looking for a match for the given parameters.
db6cf833
TR		 2355 *
2356 * Return: A newly allocated copy of the mode, or NULL if not found.
33c7531d 2357 */
1d42bbc8 2358struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
f6e252ba
AJ		 2359 int hsize, int vsize, int fresh,
2360 bool rb)
559ee21d 2361{
07a5e632 2362 int i;
559ee21d 2363
a6b21831 2364 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
b1f559ec 2365 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
948de842 2366
f8b46a05
AJ		 2367 if (hsize != ptr->hdisplay)
2368 continue;
2369 if (vsize != ptr->vdisplay)
2370 continue;
2371 if (fresh != drm_mode_vrefresh(ptr))
2372 continue;
f6e252ba
AJ		 2373 if (rb != mode_is_rb(ptr))
2374 continue;
f8b46a05
AJ		 2375
2376 return drm_mode_duplicate(dev, ptr);
559ee21d 2377 }
f8b46a05
AJ		 2378
2379 return NULL;
559ee21d 2380}
1d42bbc8 2381EXPORT_SYMBOL(drm_mode_find_dmt);
23425cae 2382
e379814b 2383static bool is_display_descriptor(const struct detailed_timing *descriptor, u8 type)
a7a131ac 2384{
e379814b
JN		 2385 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
2386 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.pad1) != 2);
2387 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.type) != 3);
2388
2389 return descriptor->pixel_clock == 0 &&
2390 descriptor->data.other_data.pad1 == 0 &&
2391 descriptor->data.other_data.type == type;
a7a131ac
VS		 2392}
2393
a9b1f15f 2394static bool is_detailed_timing_descriptor(const struct detailed_timing *descriptor)
f447dd1f 2395{
a9b1f15f
JN		 2396 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
2397
2398 return descriptor->pixel_clock != 0;
f447dd1f
VS		 2399}
2400
4194442d 2401typedef void detailed_cb(const struct detailed_timing *timing, void *closure);
d1ff6409 2402
4d76a221 2403static void
eed628f1 2404cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
4d76a221 2405{
7304b981 2406 int i, n;
4966b2a9 2407 u8 d = ext[0x02];
eed628f1 2408 const u8 *det_base = ext + d;
4d76a221 2409
7304b981
VS		 2410 if (d < 4 || d > 127)
2411 return;
2412
4966b2a9 2413 n = (127 - d) / 18;
4d76a221 2414 for (i = 0; i < n; i++)
eed628f1 2415 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
4d76a221
AJ		 2416}
2417
cbba98f8 2418static void
eed628f1 2419vtb_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
cbba98f8
AJ		 2420{
2421 unsigned int i, n = min((int)ext[0x02], 6);
eed628f1 2422 const u8 *det_base = ext + 5;
cbba98f8
AJ		 2423
2424 if (ext[0x01] != 1)
2425 return; /* unknown version */
2426
2427 for (i = 0; i < n; i++)
eed628f1 2428 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
cbba98f8
AJ		 2429}
2430
d1ff6409 2431static void
eed628f1 2432drm_for_each_detailed_block(const struct edid *edid, detailed_cb *cb, void *closure)
d1ff6409
AJ		 2433{
2434 int i;
d1ff6409
AJ		 2435
2436 if (edid == NULL)
2437 return;
2438
2439 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
2440 cb(&(edid->detailed_timings[i]), closure);
2441
eed628f1
JN		 2442 for (i = 1; i <= edid->extensions; i++) {
2443 const u8 *ext = (const u8 *)edid + (i * EDID_LENGTH);
948de842 2444
4d76a221
AJ		 2445 switch (*ext) {
2446 case CEA_EXT:
2447 cea_for_each_detailed_block(ext, cb, closure);
2448 break;
cbba98f8
AJ		 2449 case VTB_EXT:
2450 vtb_for_each_detailed_block(ext, cb, closure);
2451 break;
4d76a221
AJ		 2452 default:
2453 break;
2454 }
2455 }
d1ff6409
AJ		 2456}
2457
2458static void
4194442d 2459is_rb(const struct detailed_timing *descriptor, void *data)
d1ff6409 2460{
90fd588f 2461 bool *res = data;
a7a131ac 2462
90fd588f 2463 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
a7a131ac
VS		 2464 return;
2465
90fd588f
JN		 2466 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
2467 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.cvt.flags) != 15);
2468
2469 if (descriptor->data.other_data.data.range.flags == DRM_EDID_CVT_SUPPORT_FLAG &&
2470 descriptor->data.other_data.data.range.formula.cvt.flags & 0x10)
2471 *res = true;
d1ff6409
AJ		 2472}
2473
2474/* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
2475static bool
c14e7241 2476drm_monitor_supports_rb(const struct edid *edid)
d1ff6409
AJ		 2477{
2478 if (edid->revision >= 4) {
b196a498 2479 bool ret = false;
948de842 2480
eed628f1 2481 drm_for_each_detailed_block(edid, is_rb, &ret);
d1ff6409
AJ		 2482 return ret;
2483 }
2484
2485 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
2486}
2487
7a374350 2488static void
4194442d 2489find_gtf2(const struct detailed_timing *descriptor, void *data)
7a374350 2490{
4194442d 2491 const struct detailed_timing **res = data;
a7a131ac 2492
c8a4beba 2493 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
a7a131ac
VS		 2494 return;
2495
c8a4beba
JN		 2496 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
2497
2498 if (descriptor->data.other_data.data.range.flags == 0x02)
2499 *res = descriptor;
7a374350
AJ		 2500}
2501
2502/* Secondary GTF curve kicks in above some break frequency */
2503static int
c14e7241 2504drm_gtf2_hbreak(const struct edid *edid)
7a374350 2505{
4194442d 2506 const struct detailed_timing *descriptor = NULL;
c8a4beba 2507
eed628f1 2508 drm_for_each_detailed_block(edid, find_gtf2, &descriptor);
948de842 2509
c8a4beba
JN		 2510 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12);
2511
2512 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.hfreq_start_khz * 2 : 0;
7a374350
AJ		 2513}
2514
2515static int
c14e7241 2516drm_gtf2_2c(const struct edid *edid)
7a374350 2517{
4194442d 2518 const struct detailed_timing *descriptor = NULL;
c8a4beba 2519
eed628f1 2520 drm_for_each_detailed_block(edid, find_gtf2, &descriptor);
c8a4beba
JN		 2521
2522 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.c) != 13);
948de842 2523
c8a4beba 2524 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.c : 0;
7a374350
AJ		 2525}
2526
2527static int
c14e7241 2528drm_gtf2_m(const struct edid *edid)
7a374350 2529{
4194442d 2530 const struct detailed_timing *descriptor = NULL;
948de842 2531
eed628f1 2532 drm_for_each_detailed_block(edid, find_gtf2, &descriptor);
c8a4beba
JN		 2533
2534 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.m) != 14);
2535
2536 return descriptor ? le16_to_cpu(descriptor->data.other_data.data.range.formula.gtf2.m) : 0;
7a374350
AJ		 2537}
2538
2539static int
c14e7241 2540drm_gtf2_k(const struct edid *edid)
7a374350 2541{
4194442d 2542 const struct detailed_timing *descriptor = NULL;
c8a4beba 2543
eed628f1 2544 drm_for_each_detailed_block(edid, find_gtf2, &descriptor);
948de842 2545
c8a4beba
JN		 2546 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.k) != 16);
2547
2548 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.k : 0;
7a374350
AJ		 2549}
2550
2551static int
c14e7241 2552drm_gtf2_2j(const struct edid *edid)
7a374350 2553{
4194442d 2554 const struct detailed_timing *descriptor = NULL;
c8a4beba 2555
eed628f1 2556 drm_for_each_detailed_block(edid, find_gtf2, &descriptor);
c8a4beba
JN		 2557
2558 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.j) != 17);
948de842 2559
c8a4beba 2560 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.j : 0;
7a374350
AJ		 2561}
2562
2563/**
2564 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
2565 * @edid: EDID block to scan
2566 */
c14e7241 2567static int standard_timing_level(const struct edid *edid)
7a374350
AJ		 2568{
2569 if (edid->revision >= 2) {
2570 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
2571 return LEVEL_CVT;
2572 if (drm_gtf2_hbreak(edid))
2573 return LEVEL_GTF2;
bfef04ad
LS		 2574 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
2575 return LEVEL_GTF;
7a374350
AJ		 2576 }
2577 return LEVEL_DMT;
2578}
2579
23425cae
AJ		 2580/*
2581 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
2582 * monitors fill with ascii space (0x20) instead.
2583 */
2584static int
2585bad_std_timing(u8 a, u8 b)
2586{
2587 return (a == 0x00 && b == 0x00) ||
2588 (a == 0x01 && b == 0x01) ||
2589 (a == 0x20 && b == 0x20);
2590}
2591
58911c24
VS		 2592static int drm_mode_hsync(const struct drm_display_mode *mode)
2593{
2594 if (mode->htotal <= 0)
2595 return 0;
2596
2597 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal);
2598}
2599
f453ba04
DA		 2600/**
2601 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
fc66811c
DV		 2602 * @connector: connector of for the EDID block
2603 * @edid: EDID block to scan
f453ba04
DA		 2604 * @t: standard timing params
2605 *
2606 * Take the standard timing params (in this case width, aspect, and refresh)
5c61259e 2607 * and convert them into a real mode using CVT/GTF/DMT.
f453ba04 2608 */
7ca6adb3 2609static struct drm_display_mode *
c14e7241 2610drm_mode_std(struct drm_connector *connector, const struct edid *edid,
fcfb2ea1 2611 const struct std_timing *t)
f453ba04 2612{
7ca6adb3
AJ		 2613 struct drm_device *dev = connector->dev;
2614 struct drm_display_mode *m, *mode = NULL;
5c61259e
ZY		 2615 int hsize, vsize;
2616 int vrefresh_rate;
0454beab
MD		 2617 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
2618 >> EDID_TIMING_ASPECT_SHIFT;
5c61259e
ZY		 2619 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
2620 >> EDID_TIMING_VFREQ_SHIFT;
7a374350 2621 int timing_level = standard_timing_level(edid);
5c61259e 2622
23425cae
AJ		 2623 if (bad_std_timing(t->hsize, t->vfreq_aspect))
2624 return NULL;
2625
5c61259e
ZY		 2626 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
2627 hsize = t->hsize * 8 + 248;
2628 /* vrefresh_rate = vfreq + 60 */
2629 vrefresh_rate = vfreq + 60;
2630 /* the vdisplay is calculated based on the aspect ratio */
f066a17d 2631 if (aspect_ratio == 0) {
464fdeca 2632 if (edid->revision < 3)
f066a17d
AJ		 2633 vsize = hsize;
2634 else
2635 vsize = (hsize * 10) / 16;
2636 } else if (aspect_ratio == 1)
f453ba04 2637 vsize = (hsize * 3) / 4;
0454beab 2638 else if (aspect_ratio == 2)
f453ba04
DA		 2639 vsize = (hsize * 4) / 5;
2640 else
2641 vsize = (hsize * 9) / 16;
a0910c8e
AJ		 2642
2643 /* HDTV hack, part 1 */
2644 if (vrefresh_rate == 60 &&
2645 ((hsize == 1360 && vsize == 765) ||
2646 (hsize == 1368 && vsize == 769))) {
2647 hsize = 1366;
2648 vsize = 768;
2649 }
2650
7ca6adb3
AJ		 2651 /*
2652 * If this connector already has a mode for this size and refresh
2653 * rate (because it came from detailed or CVT info), use that
2654 * instead. This way we don't have to guess at interlace or
2655 * reduced blanking.
2656 */
522032da 2657 list_for_each_entry(m, &connector->probed_modes, head)
7ca6adb3
AJ		 2658 if (m->hdisplay == hsize && m->vdisplay == vsize &&
2659 drm_mode_vrefresh(m) == vrefresh_rate)
2660 return NULL;
2661
a0910c8e
AJ		 2662 /* HDTV hack, part 2 */
2663 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
2664 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
d50ba256 2665 false);
a5ef6567
JM		 2666 if (!mode)
2667 return NULL;
559ee21d 2668 mode->hdisplay = 1366;
a4967de6
AJ		 2669 mode->hsync_start = mode->hsync_start - 1;
2670 mode->hsync_end = mode->hsync_end - 1;
559ee21d
ZY		 2671 return mode;
2672 }
a0910c8e 2673
559ee21d 2674 /* check whether it can be found in default mode table */
f6e252ba
AJ		 2675 if (drm_monitor_supports_rb(edid)) {
2676 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
2677 true);
2678 if (mode)
2679 return mode;
2680 }
2681 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
559ee21d
ZY		 2682 if (mode)
2683 return mode;
2684
f6e252ba 2685 /* okay, generate it */
5c61259e
ZY		 2686 switch (timing_level) {
2687 case LEVEL_DMT:
5c61259e
ZY		 2688 break;
2689 case LEVEL_GTF:
2690 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2691 break;
7a374350
AJ		 2692 case LEVEL_GTF2:
2693 /*
2694 * This is potentially wrong if there's ever a monitor with
2695 * more than one ranges section, each claiming a different
2696 * secondary GTF curve. Please don't do that.
2697 */
2698 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
fc48f169
TI		 2699 if (!mode)
2700 return NULL;
7a374350 2701 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
aefd330e 2702 drm_mode_destroy(dev, mode);
7a374350
AJ		 2703 mode = drm_gtf_mode_complex(dev, hsize, vsize,
2704 vrefresh_rate, 0, 0,
2705 drm_gtf2_m(edid),
2706 drm_gtf2_2c(edid),
2707 drm_gtf2_k(edid),
2708 drm_gtf2_2j(edid));
2709 }
2710 break;
5c61259e 2711 case LEVEL_CVT:
d50ba256
DA		 2712 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
2713 false);
5c61259e
ZY		 2714 break;
2715 }
f453ba04
DA		 2716 return mode;
2717}
2718
b58db2c6
AJ		 2719/*
2720 * EDID is delightfully ambiguous about how interlaced modes are to be
2721 * encoded. Our internal representation is of frame height, but some
2722 * HDTV detailed timings are encoded as field height.
2723 *
2724 * The format list here is from CEA, in frame size. Technically we
2725 * should be checking refresh rate too. Whatever.
2726 */
2727static void
2728drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
fcfb2ea1 2729 const struct detailed_pixel_timing *pt)
b58db2c6
AJ		 2730{
2731 int i;
2732 static const struct {
2733 int w, h;
2734 } cea_interlaced[] = {
2735 { 1920, 1080 },
2736 { 720, 480 },
2737 { 1440, 480 },
2738 { 2880, 480 },
2739 { 720, 576 },
2740 { 1440, 576 },
2741 { 2880, 576 },
2742 };
b58db2c6
AJ		 2743
2744 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
2745 return;
2746
3c581411 2747 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
b58db2c6
AJ		 2748 if ((mode->hdisplay == cea_interlaced[i].w) &&
2749 (mode->vdisplay == cea_interlaced[i].h / 2)) {
2750 mode->vdisplay *= 2;
2751 mode->vsync_start *= 2;
2752 mode->vsync_end *= 2;
2753 mode->vtotal *= 2;
2754 mode->vtotal |= 1;
2755 }
2756 }
2757
2758 mode->flags |= DRM_MODE_FLAG_INTERLACE;
2759}
2760
f453ba04
DA		 2761/**
2762 * drm_mode_detailed - create a new mode from an EDID detailed timing section
2763 * @dev: DRM device (needed to create new mode)
2764 * @edid: EDID block
2765 * @timing: EDID detailed timing info
2766 * @quirks: quirks to apply
2767 *
2768 * An EDID detailed timing block contains enough info for us to create and
2769 * return a new struct drm_display_mode.
2770 */
2771static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
c14e7241 2772 const struct edid *edid,
fcfb2ea1 2773 const struct detailed_timing *timing,
f453ba04
DA		 2774 u32 quirks)
2775{
2776 struct drm_display_mode *mode;
fcfb2ea1 2777 const struct detailed_pixel_timing *pt = &timing->data.pixel_data;
0454beab
MD		 2778 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
2779 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
2780 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
2781 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
e14cbee4
MD		 2782 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
2783 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
16dad1d7 2784 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
e14cbee4 2785 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
f453ba04 2786
fc438966 2787 /* ignore tiny modes */
0454beab 2788 if (hactive < 64 || vactive < 64)
fc438966
AJ		 2789 return NULL;
2790
0454beab 2791 if (pt->misc & DRM_EDID_PT_STEREO) {
c7d015f3 2792 DRM_DEBUG_KMS("stereo mode not supported\n");
f453ba04
DA		 2793 return NULL;
2794 }
0454beab 2795 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
c7d015f3 2796 DRM_DEBUG_KMS("composite sync not supported\n");
f453ba04
DA		 2797 }
2798
fcb45611
ZY		 2799 /* it is incorrect if hsync/vsync width is zero */
2800 if (!hsync_pulse_width || !vsync_pulse_width) {
2801 DRM_DEBUG_KMS("Incorrect Detailed timing. "
2802 "Wrong Hsync/Vsync pulse width\n");
2803 return NULL;
2804 }
bc42aabc
AJ		 2805
2806 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
2807 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
2808 if (!mode)
2809 return NULL;
2810
2811 goto set_size;
2812 }
2813
f453ba04
DA		 2814 mode = drm_mode_create(dev);
2815 if (!mode)
2816 return NULL;
2817
f453ba04 2818 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
faacff8e
JN		 2819 mode->clock = 1088 * 10;
2820 else
2821 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
0454beab
MD		 2822
2823 mode->hdisplay = hactive;
2824 mode->hsync_start = mode->hdisplay + hsync_offset;
2825 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
2826 mode->htotal = mode->hdisplay + hblank;
2827
2828 mode->vdisplay = vactive;
2829 mode->vsync_start = mode->vdisplay + vsync_offset;
2830 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
2831 mode->vtotal = mode->vdisplay + vblank;
f453ba04 2832
7064fef5
JB		 2833 /* Some EDIDs have bogus h/vtotal values */
2834 if (mode->hsync_end > mode->htotal)
2835 mode->htotal = mode->hsync_end + 1;
2836 if (mode->vsync_end > mode->vtotal)
2837 mode->vtotal = mode->vsync_end + 1;
2838
b58db2c6 2839 drm_mode_do_interlace_quirk(mode, pt);
f453ba04
DA		 2840
2841 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
faacff8e
JN		 2842 mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC;
2843 } else {
2844 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
2845 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
2846 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
2847 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
f453ba04
DA		 2848 }
2849
bc42aabc 2850set_size:
e14cbee4
MD		 2851 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
2852 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
f453ba04
DA		 2853
2854 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
2855 mode->width_mm *= 10;
2856 mode->height_mm *= 10;
2857 }
2858
2859 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
2860 mode->width_mm = edid->width_cm * 10;
2861 mode->height_mm = edid->height_cm * 10;
2862 }
2863
bc42aabc
AJ		 2864 mode->type = DRM_MODE_TYPE_DRIVER;
2865 drm_mode_set_name(mode);
2866
f453ba04
DA		 2867 return mode;
2868}
2869
b17e52ef 2870static bool
b1f559ec 2871mode_in_hsync_range(const struct drm_display_mode *mode,
c14e7241 2872 const struct edid *edid, const u8 *t)
b17e52ef
AJ		 2873{
2874 int hsync, hmin, hmax;
2875
2876 hmin = t[7];
2877 if (edid->revision >= 4)
2878 hmin += ((t[4] & 0x04) ? 255 : 0);
2879 hmax = t[8];
2880 if (edid->revision >= 4)
2881 hmax += ((t[4] & 0x08) ? 255 : 0);
07a5e632 2882 hsync = drm_mode_hsync(mode);
07a5e632 2883
b17e52ef
AJ		 2884 return (hsync <= hmax && hsync >= hmin);
2885}
2886
2887static bool
b1f559ec 2888mode_in_vsync_range(const struct drm_display_mode *mode,
c14e7241 2889 const struct edid *edid, const u8 *t)
b17e52ef
AJ		 2890{
2891 int vsync, vmin, vmax;
2892
2893 vmin = t[5];
2894 if (edid->revision >= 4)
2895 vmin += ((t[4] & 0x01) ? 255 : 0);
2896 vmax = t[6];
2897 if (edid->revision >= 4)
2898 vmax += ((t[4] & 0x02) ? 255 : 0);
2899 vsync = drm_mode_vrefresh(mode);
2900
2901 return (vsync <= vmax && vsync >= vmin);
2902}
2903
2904static u32
c14e7241 2905range_pixel_clock(const struct edid *edid, const u8 *t)
b17e52ef
AJ		 2906{
2907 /* unspecified */
2908 if (t[9] == 0 || t[9] == 255)
2909 return 0;
2910
2911 /* 1.4 with CVT support gives us real precision, yay */
2912 if (edid->revision >= 4 && t[10] == 0x04)
2913 return (t[9] * 10000) - ((t[12] >> 2) * 250);
2914
2915 /* 1.3 is pathetic, so fuzz up a bit */
2916 return t[9] * 10000 + 5001;
2917}
2918
b17e52ef 2919static bool
c14e7241 2920mode_in_range(const struct drm_display_mode *mode, const struct edid *edid,
fcfb2ea1 2921 const struct detailed_timing *timing)
b17e52ef
AJ		 2922{
2923 u32 max_clock;
fcfb2ea1 2924 const u8 *t = (const u8 *)timing;
b17e52ef
AJ		 2925
2926 if (!mode_in_hsync_range(mode, edid, t))
07a5e632
AJ		 2927 return false;
2928
b17e52ef 2929 if (!mode_in_vsync_range(mode, edid, t))
07a5e632
AJ		 2930 return false;
2931
b17e52ef 2932 if ((max_clock = range_pixel_clock(edid, t)))
07a5e632
AJ		 2933 if (mode->clock > max_clock)
2934 return false;
b17e52ef
AJ		 2935
2936 /* 1.4 max horizontal check */
2937 if (edid->revision >= 4 && t[10] == 0x04)
2938 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
2939 return false;
2940
2941 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
2942 return false;
07a5e632
AJ		 2943
2944 return true;
2945}
2946
7b668ebe
TI		 2947static bool valid_inferred_mode(const struct drm_connector *connector,
2948 const struct drm_display_mode *mode)
2949{
85f8fcd6 2950 const struct drm_display_mode *m;
7b668ebe
TI		 2951 bool ok = false;
2952
2953 list_for_each_entry(m, &connector->probed_modes, head) {
2954 if (mode->hdisplay == m->hdisplay &&
2955 mode->vdisplay == m->vdisplay &&
2956 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
2957 return false; /* duplicated */
2958 if (mode->hdisplay <= m->hdisplay &&
2959 mode->vdisplay <= m->vdisplay)
2960 ok = true;
2961 }
2962 return ok;
2963}
2964
b17e52ef 2965static int
c14e7241 2966drm_dmt_modes_for_range(struct drm_connector *connector, const struct edid *edid,
fcfb2ea1 2967 const struct detailed_timing *timing)
07a5e632
AJ		 2968{
2969 int i, modes = 0;
2970 struct drm_display_mode *newmode;
2971 struct drm_device *dev = connector->dev;
2972
a6b21831 2973 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
7b668ebe
TI		 2974 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
2975 valid_inferred_mode(connector, drm_dmt_modes + i)) {
07a5e632
AJ		 2976 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
2977 if (newmode) {
2978 drm_mode_probed_add(connector, newmode);
2979 modes++;
2980 }
2981 }
2982 }
2983
2984 return modes;
2985}
2986
c09dedb7
TI		 2987/* fix up 1366x768 mode from 1368x768;
2988 * GFT/CVT can't express 1366 width which isn't dividable by 8
2989 */
969218fe 2990void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
c09dedb7
TI		 2991{
2992 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
2993 mode->hdisplay = 1366;
2994 mode->hsync_start--;
2995 mode->hsync_end--;
2996 drm_mode_set_name(mode);
2997 }
2998}
2999
b309bd37 3000static int
c14e7241 3001drm_gtf_modes_for_range(struct drm_connector *connector, const struct edid *edid,
fcfb2ea1 3002 const struct detailed_timing *timing)
b309bd37
AJ		 3003{
3004 int i, modes = 0;
3005 struct drm_display_mode *newmode;
3006 struct drm_device *dev = connector->dev;
3007
a6b21831 3008 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
b309bd37 3009 const struct minimode *m = &extra_modes[i];
948de842 3010
b309bd37 3011 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
fc48f169
TI		 3012 if (!newmode)
3013 return modes;
b309bd37 3014
969218fe 3015 drm_mode_fixup_1366x768(newmode);
7b668ebe
TI		 3016 if (!mode_in_range(newmode, edid, timing) ||
3017 !valid_inferred_mode(connector, newmode)) {
b309bd37
AJ		 3018 drm_mode_destroy(dev, newmode);
3019 continue;
3020 }
3021
3022 drm_mode_probed_add(connector, newmode);
3023 modes++;
3024 }
3025
3026 return modes;
3027}
3028
3029static int
c14e7241 3030drm_cvt_modes_for_range(struct drm_connector *connector, const struct edid *edid,
fcfb2ea1 3031 const struct detailed_timing *timing)
b309bd37
AJ		 3032{
3033 int i, modes = 0;
3034 struct drm_display_mode *newmode;
3035 struct drm_device *dev = connector->dev;
3036 bool rb = drm_monitor_supports_rb(edid);
3037
a6b21831 3038 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
b309bd37 3039 const struct minimode *m = &extra_modes[i];
948de842 3040
b309bd37 3041 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
fc48f169
TI		 3042 if (!newmode)
3043 return modes;
b309bd37 3044
969218fe 3045 drm_mode_fixup_1366x768(newmode);
7b668ebe
TI		 3046 if (!mode_in_range(newmode, edid, timing) ||
3047 !valid_inferred_mode(connector, newmode)) {
b309bd37
AJ		 3048 drm_mode_destroy(dev, newmode);
3049 continue;
3050 }
3051
3052 drm_mode_probed_add(connector, newmode);
3053 modes++;
3054 }
3055
3056 return modes;
3057}
3058
13931579 3059static void
4194442d 3060do_inferred_modes(const struct detailed_timing *timing, void *c)
9340d8cf 3061{
13931579 3062 struct detailed_mode_closure *closure = c;
fcfb2ea1
JN		 3063 const struct detailed_non_pixel *data = &timing->data.other_data;
3064 const struct detailed_data_monitor_range *range = &data->data.range;
9340d8cf 3065
e379814b 3066 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
cb21aafe
AJ		 3067 return;
3068
3069 closure->modes += drm_dmt_modes_for_range(closure->connector,
3070 closure->edid,
3071 timing);
4d23f484 3072
b309bd37
AJ		 3073 if (!version_greater(closure->edid, 1, 1))
3074 return; /* GTF not defined yet */
3075
3076 switch (range->flags) {
3077 case 0x02: /* secondary gtf, XXX could do more */
3078 case 0x00: /* default gtf */
3079 closure->modes += drm_gtf_modes_for_range(closure->connector,
3080 closure->edid,
3081 timing);
3082 break;
3083 case 0x04: /* cvt, only in 1.4+ */
3084 if (!version_greater(closure->edid, 1, 3))
3085 break;
3086
3087 closure->modes += drm_cvt_modes_for_range(closure->connector,
3088 closure->edid,
3089 timing);
3090 break;
3091 case 0x01: /* just the ranges, no formula */
3092 default:
3093 break;
3094 }
13931579 3095}
69da3015 3096
13931579 3097static int
c14e7241 3098add_inferred_modes(struct drm_connector *connector, const struct edid *edid)
13931579
AJ		 3099{
3100 struct detailed_mode_closure closure = {
d456ea2e
JL		 3101 .connector = connector,
3102 .edid = edid,
13931579 3103 };
9340d8cf 3104
13931579 3105 if (version_greater(edid, 1, 0))
eed628f1 3106 drm_for_each_detailed_block(edid, do_inferred_modes, &closure);
9340d8cf 3107
13931579 3108 return closure.modes;
9340d8cf
AJ		 3109}
3110
2255be14 3111static int
fcfb2ea1 3112drm_est3_modes(struct drm_connector *connector, const struct detailed_timing *timing)
2255be14
AJ		 3113{
3114 int i, j, m, modes = 0;
3115 struct drm_display_mode *mode;
fcfb2ea1 3116 const u8 *est = ((const u8 *)timing) + 6;
2255be14
AJ		 3117
3118 for (i = 0; i < 6; i++) {
891a7469 3119 for (j = 7; j >= 0; j--) {
2255be14 3120 m = (i * 8) + (7 - j);
3c581411 3121 if (m >= ARRAY_SIZE(est3_modes))
2255be14
AJ		 3122 break;
3123 if (est[i] & (1 << j)) {
1d42bbc8
DA		 3124 mode = drm_mode_find_dmt(connector->dev,
3125 est3_modes[m].w,
3126 est3_modes[m].h,
f6e252ba
AJ		 3127 est3_modes[m].r,
3128 est3_modes[m].rb);
2255be14
AJ		 3129 if (mode) {
3130 drm_mode_probed_add(connector, mode);
3131 modes++;
3132 }
3133 }
3134 }
3135 }
3136
3137 return modes;
3138}
3139
13931579 3140static void
4194442d 3141do_established_modes(const struct detailed_timing *timing, void *c)
9cf00977 3142{
13931579 3143 struct detailed_mode_closure *closure = c;
9cf00977 3144
e379814b 3145 if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS))
a7a131ac
VS		 3146 return;
3147
3148 closure->modes += drm_est3_modes(closure->connector, timing);
13931579 3149}
9cf00977 3150
13931579
AJ		 3151/**
3152 * add_established_modes - get est. modes from EDID and add them
db6cf833 3153 * @connector: connector to add mode(s) to
13931579
AJ		 3154 * @edid: EDID block to scan
3155 *
3156 * Each EDID block contains a bitmap of the supported "established modes" list
3157 * (defined above). Tease them out and add them to the global modes list.
3158 */
3159static int
c14e7241 3160add_established_modes(struct drm_connector *connector, const struct edid *edid)
13931579
AJ		 3161{
3162 struct drm_device *dev = connector->dev;
3163 unsigned long est_bits = edid->established_timings.t1 |
3164 (edid->established_timings.t2 << 8) |
3165 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
3166 int i, modes = 0;
3167 struct detailed_mode_closure closure = {
d456ea2e
JL		 3168 .connector = connector,
3169 .edid = edid,
13931579 3170 };
9cf00977 3171
13931579
AJ		 3172 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
3173 if (est_bits & (1<<i)) {
3174 struct drm_display_mode *newmode;
948de842 3175
13931579
AJ		 3176 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
3177 if (newmode) {
3178 drm_mode_probed_add(connector, newmode);
3179 modes++;
3180 }
3181 }
9cf00977
AJ		 3182 }
3183
13931579 3184 if (version_greater(edid, 1, 0))
eed628f1
JN		 3185 drm_for_each_detailed_block(edid, do_established_modes,
3186 &closure);
13931579
AJ		 3187
3188 return modes + closure.modes;
3189}
3190
3191static void
4194442d 3192do_standard_modes(const struct detailed_timing *timing, void *c)
13931579
AJ		 3193{
3194 struct detailed_mode_closure *closure = c;
fcfb2ea1 3195 const struct detailed_non_pixel *data = &timing->data.other_data;
13931579 3196 struct drm_connector *connector = closure->connector;
c14e7241 3197 const struct edid *edid = closure->edid;
a7a131ac 3198 int i;
13931579 3199
e379814b 3200 if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES))
a7a131ac 3201 return;
9cf00977 3202
a7a131ac 3203 for (i = 0; i < 6; i++) {
fcfb2ea1 3204 const struct std_timing *std = &data->data.timings[i];
a7a131ac
VS		 3205 struct drm_display_mode *newmode;
3206
3207 newmode = drm_mode_std(connector, edid, std);
3208 if (newmode) {
3209 drm_mode_probed_add(connector, newmode);
3210 closure->modes++;
9cf00977 3211 }
9cf00977 3212 }
9cf00977
AJ		 3213}
3214
f453ba04 3215/**
13931579 3216 * add_standard_modes - get std. modes from EDID and add them
db6cf833 3217 * @connector: connector to add mode(s) to
f453ba04 3218 * @edid: EDID block to scan
f453ba04 3219 *
13931579
AJ		 3220 * Standard modes can be calculated using the appropriate standard (DMT,
3221 * GTF or CVT. Grab them from @edid and add them to the list.
f453ba04 3222 */
13931579 3223static int
c14e7241 3224add_standard_modes(struct drm_connector *connector, const struct edid *edid)
f453ba04 3225{
9cf00977 3226 int i, modes = 0;
13931579 3227 struct detailed_mode_closure closure = {
d456ea2e
JL		 3228 .connector = connector,
3229 .edid = edid,
13931579
AJ		 3230 };
3231
3232 for (i = 0; i < EDID_STD_TIMINGS; i++) {
3233 struct drm_display_mode *newmode;
3234
3235 newmode = drm_mode_std(connector, edid,
464fdeca 3236 &edid->standard_timings[i]);
13931579
AJ		 3237 if (newmode) {
3238 drm_mode_probed_add(connector, newmode);
3239 modes++;
3240 }
3241 }
3242
3243 if (version_greater(edid, 1, 0))
eed628f1 3244 drm_for_each_detailed_block(edid, do_standard_modes,
13931579
AJ		 3245 &closure);
3246
3247 /* XXX should also look for standard codes in VTB blocks */
3248
3249 return modes + closure.modes;
3250}
f453ba04 3251
13931579 3252static int drm_cvt_modes(struct drm_connector *connector,
fcfb2ea1 3253 const struct detailed_timing *timing)
13931579
AJ		 3254{
3255 int i, j, modes = 0;
3256 struct drm_display_mode *newmode;
3257 struct drm_device *dev = connector->dev;
fcfb2ea1 3258 const struct cvt_timing *cvt;
13931579
AJ		 3259 const int rates[] = { 60, 85, 75, 60, 50 };
3260 const u8 empty[3] = { 0, 0, 0 };
a327f6b8 3261
13931579 3262 for (i = 0; i < 4; i++) {
3f649ab7 3263 int width, height;
948de842 3264
13931579 3265 cvt = &(timing->data.other_data.data.cvt[i]);
f453ba04 3266
13931579 3267 if (!memcmp(cvt->code, empty, 3))
9cf00977 3268 continue;
f453ba04 3269
13931579
AJ		 3270 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
3271 switch (cvt->code[1] & 0x0c) {
d652d5f1
LT		 3272 /* default - because compiler doesn't see that we've enumerated all cases */
3273 default:
13931579
AJ		 3274 case 0x00:
3275 width = height * 4 / 3;
3276 break;
3277 case 0x04:
3278 width = height * 16 / 9;
3279 break;
3280 case 0x08:
3281 width = height * 16 / 10;
3282 break;
3283 case 0x0c:
3284 width = height * 15 / 9;
3285 break;
3286 }
3287
3288 for (j = 1; j < 5; j++) {
3289 if (cvt->code[2] & (1 << j)) {
3290 newmode = drm_cvt_mode(dev, width, height,
3291 rates[j], j == 0,
3292 false, false);
3293 if (newmode) {
3294 drm_mode_probed_add(connector, newmode);
3295 modes++;
3296 }
3297 }
3298 }
f453ba04
DA		 3299 }
3300
3301 return modes;
3302}
9cf00977 3303
13931579 3304static void
4194442d 3305do_cvt_mode(const struct detailed_timing *timing, void *c)
882f0219 3306{
13931579 3307 struct detailed_mode_closure *closure = c;
882f0219 3308
e379814b 3309 if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE))
a7a131ac
VS		 3310 return;
3311
3312 closure->modes += drm_cvt_modes(closure->connector, timing);
13931579 3313}
882f0219 3314
13931579 3315static int
c14e7241 3316add_cvt_modes(struct drm_connector *connector, const struct edid *edid)
4d23f484 3317{
13931579 3318 struct detailed_mode_closure closure = {
d456ea2e
JL		 3319 .connector = connector,
3320 .edid = edid,
13931579 3321 };
882f0219 3322
13931579 3323 if (version_greater(edid, 1, 2))
eed628f1 3324 drm_for_each_detailed_block(edid, do_cvt_mode, &closure);
882f0219 3325
13931579 3326 /* XXX should also look for CVT codes in VTB blocks */
882f0219 3327
13931579
AJ		 3328 return closure.modes;
3329}
3330
fa3a7340
VS		 3331static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
3332
13931579 3333static void
4194442d 3334do_detailed_mode(const struct detailed_timing *timing, void *c)
13931579
AJ		 3335{
3336 struct detailed_mode_closure *closure = c;
3337 struct drm_display_mode *newmode;
3338
a9b1f15f 3339 if (!is_detailed_timing_descriptor(timing))
f447dd1f
VS		 3340 return;
3341
3342 newmode = drm_mode_detailed(closure->connector->dev,
3343 closure->edid, timing,
3344 closure->quirks);
3345 if (!newmode)
3346 return;
13931579 3347
f447dd1f
VS		 3348 if (closure->preferred)
3349 newmode->type |= DRM_MODE_TYPE_PREFERRED;
13931579 3350
f447dd1f
VS		 3351 /*
3352 * Detailed modes are limited to 10kHz pixel clock resolution,
3353 * so fix up anything that looks like CEA/HDMI mode, but the clock
3354 * is just slightly off.
3355 */
3356 fixup_detailed_cea_mode_clock(newmode);
fa3a7340 3357
f447dd1f
VS		 3358 drm_mode_probed_add(closure->connector, newmode);
3359 closure->modes++;
3360 closure->preferred = false;
13931579 3361}
882f0219 3362
13931579
AJ		 3363/*
3364 * add_detailed_modes - Add modes from detailed timings
3365 * @connector: attached connector
3366 * @edid: EDID block to scan
3367 * @quirks: quirks to apply
3368 */
3369static int
c14e7241 3370add_detailed_modes(struct drm_connector *connector, const struct edid *edid,
13931579
AJ		 3371 u32 quirks)
3372{
3373 struct detailed_mode_closure closure = {
d456ea2e
JL		 3374 .connector = connector,
3375 .edid = edid,
c2925bde 3376 .preferred = true,
d456ea2e 3377 .quirks = quirks,
13931579
AJ		 3378 };
3379
3380 if (closure.preferred && !version_greater(edid, 1, 3))
3381 closure.preferred =
3382 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
3383
eed628f1 3384 drm_for_each_detailed_block(edid, do_detailed_mode, &closure);
13931579
AJ		 3385
3386 return closure.modes;
882f0219 3387}
f453ba04 3388
8fe9790d 3389#define AUDIO_BLOCK 0x01
54ac76f8 3390#define VIDEO_BLOCK 0x02
f23c20c8 3391#define VENDOR_BLOCK 0x03
76adaa34 3392#define SPEAKER_BLOCK 0x04
e85959d6 3393#define HDR_STATIC_METADATA_BLOCK 0x6
87563fc0
SS		 3394#define USE_EXTENDED_TAG 0x07
3395#define EXT_VIDEO_CAPABILITY_BLOCK 0x00
832d4f2f
SS		 3396#define EXT_VIDEO_DATA_BLOCK_420 0x0E
3397#define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F
8fe9790d 3398#define EDID_BASIC_AUDIO (1 << 6)
a988bc72
LPC		 3399#define EDID_CEA_YCRCB444 (1 << 5)
3400#define EDID_CEA_YCRCB422 (1 << 4)
b1edd6a6 3401#define EDID_CEA_VCDB_QS (1 << 6)
8fe9790d 3402
d4e4a31d 3403/*
8fe9790d 3404 * Search EDID for CEA extension block.
f23c20c8 3405 */
4cc4f09e
JN		 3406const u8 *drm_find_edid_extension(const struct edid *edid,
3407 int ext_id, int *ext_index)
f23c20c8 3408{
43d16d84 3409 const u8 *edid_ext = NULL;
8fe9790d 3410 int i;
f23c20c8
ML		 3411
3412 /* No EDID or EDID extensions */
3413 if (edid == NULL || edid->extensions == 0)
8fe9790d 3414 return NULL;
f23c20c8 3415
f23c20c8 3416 /* Find CEA extension */
8873cfa3 3417 for (i = *ext_index; i < edid->extensions; i++) {
43d16d84 3418 edid_ext = (const u8 *)edid + EDID_LENGTH * (i + 1);
4ba0f53c 3419 if (edid_block_tag(edid_ext) == ext_id)
f23c20c8
ML		 3420 break;
3421 }
3422
8873cfa3 3423 if (i >= edid->extensions)
8fe9790d
ZW		 3424 return NULL;
3425
8873cfa3
VS		 3426 *ext_index = i + 1;
3427
8fe9790d
ZW		 3428 return edid_ext;
3429}
3430
43d16d84 3431static const u8 *drm_find_cea_extension(const struct edid *edid)
e28ad544 3432{
43d16d84 3433 const struct displayid_block *block;
1ba63caf 3434 struct displayid_iter iter;
43d16d84 3435 const u8 *cea;
1ba63caf 3436 int ext_index = 0;
e28ad544
AR		 3437
3438 /* Look for a top level CEA extension block */
7f261afd 3439 /* FIXME: make callers iterate through multiple CEA ext blocks? */
8873cfa3 3440 cea = drm_find_edid_extension(edid, CEA_EXT, &ext_index);
e28ad544
AR		 3441 if (cea)
3442 return cea;
3443
3444 /* CEA blocks can also be found embedded in a DisplayID block */
1ba63caf
JN		 3445 displayid_iter_edid_begin(edid, &iter);
3446 displayid_iter_for_each(block, &iter) {
3447 if (block->tag == DATA_BLOCK_CTA) {
3448 cea = (const u8 *)block;
3449 break;
e28ad544
AR		 3450 }
3451 }
1ba63caf 3452 displayid_iter_end(&iter);
e28ad544 3453
1ba63caf 3454 return cea;
e28ad544
AR		 3455}
3456
e1cf35b9 3457static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic)
7befe621 3458{
9212f8ee
VS		 3459 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127);
3460 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219);
3461
8c1b2bd9
VS		 3462 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1))
3463 return &edid_cea_modes_1[vic - 1];
f7655d42
VS		 3464 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193))
3465 return &edid_cea_modes_193[vic - 193];
7befe621
VS		 3466 return NULL;
3467}
3468
3469static u8 cea_num_vics(void)
3470{
f7655d42 3471 return 193 + ARRAY_SIZE(edid_cea_modes_193);
7befe621
VS		 3472}
3473
3474static u8 cea_next_vic(u8 vic)
3475{
8c1b2bd9 3476 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1))
f7655d42
VS		 3477 vic = 193;
3478 return vic;
7befe621
VS		 3479}
3480
e6e79209
VS		 3481/*
3482 * Calculate the alternate clock for the CEA mode
3483 * (60Hz vs. 59.94Hz etc.)
3484 */
3485static unsigned int
3486cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
3487{
3488 unsigned int clock = cea_mode->clock;
3489
0425662f 3490 if (drm_mode_vrefresh(cea_mode) % 6 != 0)
e6e79209
VS		 3491 return clock;
3492
3493 /*
3494 * edid_cea_modes contains the 59.94Hz
3495 * variant for 240 and 480 line modes,
3496 * and the 60Hz variant otherwise.
3497 */
3498 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
9afd808c 3499 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
e6e79209 3500 else
9afd808c 3501 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
e6e79209
VS		 3502
3503 return clock;
3504}
3505
c45a4e46
VS		 3506static bool
3507cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
3508{
3509 /*
3510 * For certain VICs the spec allows the vertical
3511 * front porch to vary by one or two lines.
3512 *
3513 * cea_modes[] stores the variant with the shortest
3514 * vertical front porch. We can adjust the mode to
3515 * get the other variants by simply increasing the
3516 * vertical front porch length.
3517 */
7befe621
VS		 3518 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 ||
3519 cea_mode_for_vic(9)->vtotal != 262 ||
3520 cea_mode_for_vic(12)->vtotal != 262 ||
3521 cea_mode_for_vic(13)->vtotal != 262 ||
3522 cea_mode_for_vic(23)->vtotal != 312 ||
3523 cea_mode_for_vic(24)->vtotal != 312 ||
3524 cea_mode_for_vic(27)->vtotal != 312 ||
3525 cea_mode_for_vic(28)->vtotal != 312);
c45a4e46
VS		 3526
3527 if (((vic == 8 || vic == 9 ||
3528 vic == 12 || vic == 13) && mode->vtotal < 263) ||
3529 ((vic == 23 || vic == 24 ||
3530 vic == 27 || vic == 28) && mode->vtotal < 314)) {
3531 mode->vsync_start++;
3532 mode->vsync_end++;
3533 mode->vtotal++;
3534
3535 return true;
3536 }
3537
3538 return false;
3539}
3540
4c6bcf44
VS		 3541static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
3542 unsigned int clock_tolerance)
3543{
357768cc 3544 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 3545 u8 vic;
4c6bcf44
VS		 3546
3547 if (!to_match->clock)
3548 return 0;
3549
357768cc
VS		 3550 if (to_match->picture_aspect_ratio)
3551 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3552
7befe621 3553 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
563c4a75 3554 struct drm_display_mode cea_mode;
4c6bcf44
VS		 3555 unsigned int clock1, clock2;
3556
563c4a75
VS		 3557 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
3558
4c6bcf44 3559 /* Check both 60Hz and 59.94Hz */
c45a4e46
VS		 3560 clock1 = cea_mode.clock;
3561 clock2 = cea_mode_alternate_clock(&cea_mode);
4c6bcf44
VS		 3562
3563 if (abs(to_match->clock - clock1) > clock_tolerance &&
3564 abs(to_match->clock - clock2) > clock_tolerance)
3565 continue;
3566
c45a4e46 3567 do {
357768cc 3568 if (drm_mode_match(to_match, &cea_mode, match_flags))
c45a4e46
VS		 3569 return vic;
3570 } while (cea_mode_alternate_timings(vic, &cea_mode));
4c6bcf44
VS		 3571 }
3572
3573 return 0;
3574}
3575
18316c8c
TR		 3576/**
3577 * drm_match_cea_mode - look for a CEA mode matching given mode
3578 * @to_match: display mode
3579 *
db6cf833 3580 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
18316c8c 3581 * mode.
a4799037 3582 */
18316c8c 3583u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
a4799037 3584{
357768cc 3585 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 3586 u8 vic;
a4799037 3587
a90b590e
VS		 3588 if (!to_match->clock)
3589 return 0;
3590
357768cc
VS		 3591 if (to_match->picture_aspect_ratio)
3592 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3593
7befe621 3594 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
563c4a75 3595 struct drm_display_mode cea_mode;
a90b590e
VS		 3596 unsigned int clock1, clock2;
3597
563c4a75
VS		 3598 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
3599
a90b590e 3600 /* Check both 60Hz and 59.94Hz */
c45a4e46
VS		 3601 clock1 = cea_mode.clock;
3602 clock2 = cea_mode_alternate_clock(&cea_mode);
a4799037 3603
c45a4e46
VS		 3604 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
3605 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
3606 continue;
3607
3608 do {
357768cc 3609 if (drm_mode_match(to_match, &cea_mode, match_flags))
c45a4e46
VS		 3610 return vic;
3611 } while (cea_mode_alternate_timings(vic, &cea_mode));
a4799037 3612 }
c45a4e46 3613
a4799037
SM		 3614 return 0;
3615}
3616EXPORT_SYMBOL(drm_match_cea_mode);
3617
d9278b4c
JN		 3618static bool drm_valid_cea_vic(u8 vic)
3619{
7befe621 3620 return cea_mode_for_vic(vic) != NULL;
d9278b4c
JN		 3621}
3622
28c03a44 3623static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
0967e6a5 3624{
7befe621
VS		 3625 const struct drm_display_mode *mode = cea_mode_for_vic(video_code);
3626
3627 if (mode)
3628 return mode->picture_aspect_ratio;
3629
3630 return HDMI_PICTURE_ASPECT_NONE;
0967e6a5 3631}
0967e6a5 3632
d2b43473
WL		 3633static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code)
3634{
3635 return edid_4k_modes[video_code].picture_aspect_ratio;
3636}
3637
3f2f6533
LD		 3638/*
3639 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
3640 * specific block).
3f2f6533
LD		 3641 */
3642static unsigned int
3643hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
3644{
3f2f6533
LD		 3645 return cea_mode_alternate_clock(hdmi_mode);
3646}
3647
4c6bcf44
VS		 3648static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
3649 unsigned int clock_tolerance)
3650{
357768cc 3651 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 3652 u8 vic;
4c6bcf44
VS		 3653
3654 if (!to_match->clock)
3655 return 0;
3656
d2b43473
WL		 3657 if (to_match->picture_aspect_ratio)
3658 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3659
d9278b4c
JN		 3660 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3661 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4c6bcf44
VS		 3662 unsigned int clock1, clock2;
3663
3664 /* Make sure to also match alternate clocks */
3665 clock1 = hdmi_mode->clock;
3666 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3667
3668 if (abs(to_match->clock - clock1) > clock_tolerance &&
3669 abs(to_match->clock - clock2) > clock_tolerance)
3670 continue;
3671
357768cc 3672 if (drm_mode_match(to_match, hdmi_mode, match_flags))
d9278b4c 3673 return vic;
4c6bcf44
VS		 3674 }
3675
3676 return 0;
3677}
3678
3f2f6533
LD		 3679/*
3680 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
3681 * @to_match: display mode
3682 *
3683 * An HDMI mode is one defined in the HDMI vendor specific block.
3684 *
3685 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
3686 */
3687static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
3688{
357768cc 3689 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 3690 u8 vic;
3f2f6533
LD		 3691
3692 if (!to_match->clock)
3693 return 0;
3694
d2b43473
WL		 3695 if (to_match->picture_aspect_ratio)
3696 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3697
d9278b4c
JN		 3698 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3699 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3f2f6533
LD		 3700 unsigned int clock1, clock2;
3701
3702 /* Make sure to also match alternate clocks */
3703 clock1 = hdmi_mode->clock;
3704 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3705
3706 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
3707 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
357768cc 3708 drm_mode_match(to_match, hdmi_mode, match_flags))
d9278b4c 3709 return vic;
3f2f6533
LD		 3710 }
3711 return 0;
3712}
3713
d9278b4c
JN		 3714static bool drm_valid_hdmi_vic(u8 vic)
3715{
3716 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
3717}
3718
e6e79209 3719static int
f4e558ec 3720add_alternate_cea_modes(struct drm_connector *connector, const struct edid *edid)
e6e79209
VS		 3721{
3722 struct drm_device *dev = connector->dev;
3723 struct drm_display_mode *mode, *tmp;
3724 LIST_HEAD(list);
3725 int modes = 0;
3726
3727 /* Don't add CEA modes if the CEA extension block is missing */
3728 if (!drm_find_cea_extension(edid))
3729 return 0;
3730
3731 /*
3732 * Go through all probed modes and create a new mode
3733 * with the alternate clock for certain CEA modes.
3734 */
3735 list_for_each_entry(mode, &connector->probed_modes, head) {
3f2f6533 3736 const struct drm_display_mode *cea_mode = NULL;
e6e79209 3737 struct drm_display_mode *newmode;
d9278b4c 3738 u8 vic = drm_match_cea_mode(mode);
e6e79209
VS		 3739 unsigned int clock1, clock2;
3740
d9278b4c 3741 if (drm_valid_cea_vic(vic)) {
7befe621 3742 cea_mode = cea_mode_for_vic(vic);
3f2f6533
LD		 3743 clock2 = cea_mode_alternate_clock(cea_mode);
3744 } else {
d9278b4c
JN		 3745 vic = drm_match_hdmi_mode(mode);
3746 if (drm_valid_hdmi_vic(vic)) {
3747 cea_mode = &edid_4k_modes[vic];
3f2f6533
LD		 3748 clock2 = hdmi_mode_alternate_clock(cea_mode);
3749 }
3750 }
e6e79209 3751
3f2f6533
LD		 3752 if (!cea_mode)
3753 continue;
e6e79209
VS		 3754
3755 clock1 = cea_mode->clock;
e6e79209
VS		 3756
3757 if (clock1 == clock2)
3758 continue;
3759
3760 if (mode->clock != clock1 && mode->clock != clock2)
3761 continue;
3762
3763 newmode = drm_mode_duplicate(dev, cea_mode);
3764 if (!newmode)
3765 continue;
3766
27130212
DL		 3767 /* Carry over the stereo flags */
3768 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
3769
e6e79209
VS		 3770 /*
3771 * The current mode could be either variant. Make
3772 * sure to pick the "other" clock for the new mode.
3773 */
3774 if (mode->clock != clock1)
3775 newmode->clock = clock1;
3776 else
3777 newmode->clock = clock2;
3778
3779 list_add_tail(&newmode->head, &list);
3780 }
3781
3782 list_for_each_entry_safe(mode, tmp, &list, head) {
3783 list_del(&mode->head);
3784 drm_mode_probed_add(connector, mode);
3785 modes++;
3786 }
3787
3788 return modes;
3789}
a4799037 3790
8ec6e075
SS		 3791static u8 svd_to_vic(u8 svd)
3792{
3793 /* 0-6 bit vic, 7th bit native mode indicator */
3794 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
3795 return svd & 127;
3796
3797 return svd;
3798}
3799
aff04ace
TW		 3800static struct drm_display_mode *
3801drm_display_mode_from_vic_index(struct drm_connector *connector,
3802 const u8 *video_db, u8 video_len,
3803 u8 video_index)
54ac76f8
CS		 3804{
3805 struct drm_device *dev = connector->dev;
aff04ace 3806 struct drm_display_mode *newmode;
d9278b4c 3807 u8 vic;
54ac76f8 3808
aff04ace
TW		 3809 if (video_db == NULL || video_index >= video_len)
3810 return NULL;
3811
3812 /* CEA modes are numbered 1..127 */
8ec6e075 3813 vic = svd_to_vic(video_db[video_index]);
d9278b4c 3814 if (!drm_valid_cea_vic(vic))
aff04ace
TW		 3815 return NULL;
3816
7befe621 3817 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
409bbf1e
DL		 3818 if (!newmode)
3819 return NULL;
3820
aff04ace
TW		 3821 return newmode;
3822}
3823
832d4f2f
SS		 3824/*
3825 * do_y420vdb_modes - Parse YCBCR 420 only modes
3826 * @connector: connector corresponding to the HDMI sink
3827 * @svds: start of the data block of CEA YCBCR 420 VDB
3828 * @len: length of the CEA YCBCR 420 VDB
3829 *
3830 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
3831 * which contains modes which can be supported in YCBCR 420
3832 * output format only.
3833 */
3834static int do_y420vdb_modes(struct drm_connector *connector,
3835 const u8 *svds, u8 svds_len)
3836{
3837 int modes = 0, i;
3838 struct drm_device *dev = connector->dev;
3839 struct drm_display_info *info = &connector->display_info;
3840 struct drm_hdmi_info *hdmi = &info->hdmi;
3841
3842 for (i = 0; i < svds_len; i++) {
3843 u8 vic = svd_to_vic(svds[i]);
3844 struct drm_display_mode *newmode;
3845
3846 if (!drm_valid_cea_vic(vic))
3847 continue;
3848
7befe621 3849 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
832d4f2f
SS		 3850 if (!newmode)
3851 break;
3852 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
3853 drm_mode_probed_add(connector, newmode);
3854 modes++;
3855 }
3856
3857 if (modes > 0)
c03d0b52 3858 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
832d4f2f
SS		 3859 return modes;
3860}
3861
3862/*
3863 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap
3864 * @connector: connector corresponding to the HDMI sink
3865 * @vic: CEA vic for the video mode to be added in the map
3866 *
3867 * Makes an entry for a videomode in the YCBCR 420 bitmap
3868 */
3869static void
3870drm_add_cmdb_modes(struct drm_connector *connector, u8 svd)
3871{
3872 u8 vic = svd_to_vic(svd);
3873 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3874
3875 if (!drm_valid_cea_vic(vic))
3876 return;
3877
3878 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
3879}
3880
7af655bc
VS		 3881/**
3882 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC
3883 * @dev: DRM device
8d7d8c0a 3884 * @video_code: CEA VIC of the mode
7af655bc
VS		 3885 *
3886 * Creates a new mode matching the specified CEA VIC.
3887 *
3888 * Returns: A new drm_display_mode on success or NULL on failure
3889 */
3890struct drm_display_mode *
3891drm_display_mode_from_cea_vic(struct drm_device *dev,
3892 u8 video_code)
3893{
3894 const struct drm_display_mode *cea_mode;
3895 struct drm_display_mode *newmode;
3896
3897 cea_mode = cea_mode_for_vic(video_code);
3898 if (!cea_mode)
3899 return NULL;
3900
3901 newmode = drm_mode_duplicate(dev, cea_mode);
3902 if (!newmode)
3903 return NULL;
3904
3905 return newmode;
3906}
3907EXPORT_SYMBOL(drm_display_mode_from_cea_vic);
3908
aff04ace
TW		 3909static int
3910do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
3911{
3912 int i, modes = 0;
832d4f2f 3913 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
aff04ace
TW		 3914
3915 for (i = 0; i < len; i++) {
3916 struct drm_display_mode *mode;
948de842 3917
aff04ace
TW		 3918 mode = drm_display_mode_from_vic_index(connector, db, len, i);
3919 if (mode) {
832d4f2f
SS		 3920 /*
3921 * YCBCR420 capability block contains a bitmap which
3922 * gives the index of CEA modes from CEA VDB, which
3923 * can support YCBCR 420 sampling output also (apart
3924 * from RGB/YCBCR444 etc).
3925 * For example, if the bit 0 in bitmap is set,
3926 * first mode in VDB can support YCBCR420 output too.
3927 * Add YCBCR420 modes only if sink is HDMI 2.0 capable.
3928 */
3929 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i))
3930 drm_add_cmdb_modes(connector, db[i]);
3931
aff04ace
TW		 3932 drm_mode_probed_add(connector, mode);
3933 modes++;
54ac76f8
CS		 3934 }
3935 }
3936
3937 return modes;
3938}
3939
c858cfca
DL		 3940struct stereo_mandatory_mode {
3941 int width, height, vrefresh;
3942 unsigned int flags;
3943};
3944
3945static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
f7e121b7
DL		 3946 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3947 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
c858cfca
DL		 3948 { 1920, 1080, 50,
3949 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3950 { 1920, 1080, 60,
3951 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
f7e121b7
DL		 3952 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3953 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
3954 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3955 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
c858cfca
DL		 3956};
3957
3958static bool
3959stereo_match_mandatory(const struct drm_display_mode *mode,
3960 const struct stereo_mandatory_mode *stereo_mode)
3961{
3962 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
3963
3964 return mode->hdisplay == stereo_mode->width &&
3965 mode->vdisplay == stereo_mode->height &&
3966 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
3967 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
3968}
3969
c858cfca
DL		 3970static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
3971{
3972 struct drm_device *dev = connector->dev;
3973 const struct drm_display_mode *mode;
3974 struct list_head stereo_modes;
f7e121b7 3975 int modes = 0, i;
c858cfca
DL		 3976
3977 INIT_LIST_HEAD(&stereo_modes);
3978
3979 list_for_each_entry(mode, &connector->probed_modes, head) {
f7e121b7
DL		 3980 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
3981 const struct stereo_mandatory_mode *mandatory;
c858cfca
DL		 3982 struct drm_display_mode *new_mode;
3983
f7e121b7
DL		 3984 if (!stereo_match_mandatory(mode,
3985 &stereo_mandatory_modes[i]))
3986 continue;
c858cfca 3987
f7e121b7 3988 mandatory = &stereo_mandatory_modes[i];
c858cfca
DL		 3989 new_mode = drm_mode_duplicate(dev, mode);
3990 if (!new_mode)
3991 continue;
3992
f7e121b7 3993 new_mode->flags |= mandatory->flags;
c858cfca
DL		 3994 list_add_tail(&new_mode->head, &stereo_modes);
3995 modes++;
f7e121b7 3996 }
c858cfca
DL		 3997 }
3998
3999 list_splice_tail(&stereo_modes, &connector->probed_modes);
4000
4001 return modes;
4002}
4003
1deee8d7
DL		 4004static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
4005{
4006 struct drm_device *dev = connector->dev;
4007 struct drm_display_mode *newmode;
4008
d9278b4c 4009 if (!drm_valid_hdmi_vic(vic)) {
1deee8d7
DL		 4010 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
4011 return 0;
4012 }
4013
4014 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
4015 if (!newmode)
4016 return 0;
4017
4018 drm_mode_probed_add(connector, newmode);
4019
4020 return 1;
4021}
4022
fbf46025
TW		 4023static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
4024 const u8 *video_db, u8 video_len, u8 video_index)
4025{
fbf46025
TW		 4026 struct drm_display_mode *newmode;
4027 int modes = 0;
fbf46025
TW		 4028
4029 if (structure & (1 << 0)) {
aff04ace
TW		 4030 newmode = drm_display_mode_from_vic_index(connector, video_db,
4031 video_len,
4032 video_index);
fbf46025
TW		 4033 if (newmode) {
4034 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
4035 drm_mode_probed_add(connector, newmode);
4036 modes++;
4037 }
4038 }
4039 if (structure & (1 << 6)) {
aff04ace
TW		 4040 newmode = drm_display_mode_from_vic_index(connector, video_db,
4041 video_len,
4042 video_index);
fbf46025
TW		 4043 if (newmode) {
4044 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4045 drm_mode_probed_add(connector, newmode);
4046 modes++;
4047 }
4048 }
4049 if (structure & (1 << 8)) {
aff04ace
TW		 4050 newmode = drm_display_mode_from_vic_index(connector, video_db,
4051 video_len,
4052 video_index);
fbf46025 4053 if (newmode) {
89570eeb 4054 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
fbf46025
TW		 4055 drm_mode_probed_add(connector, newmode);
4056 modes++;
4057 }
4058 }
4059
4060 return modes;
4061}
4062
7ebe1963
LD		 4063/*
4064 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
4065 * @connector: connector corresponding to the HDMI sink
4066 * @db: start of the CEA vendor specific block
4067 * @len: length of the CEA block payload, ie. one can access up to db[len]
4068 *
c858cfca
DL		 4069 * Parses the HDMI VSDB looking for modes to add to @connector. This function
4070 * also adds the stereo 3d modes when applicable.
7ebe1963
LD		 4071 */
4072static int
fbf46025
TW		 4073do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
4074 const u8 *video_db, u8 video_len)
7ebe1963 4075{
f1781e9b 4076 struct drm_display_info *info = &connector->display_info;
0e5083aa 4077 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
fbf46025
TW		 4078 u8 vic_len, hdmi_3d_len = 0;
4079 u16 mask;
4080 u16 structure_all;
7ebe1963
LD		 4081
4082 if (len < 8)
4083 goto out;
4084
4085 /* no HDMI_Video_Present */
4086 if (!(db[8] & (1 << 5)))
4087 goto out;
4088
4089 /* Latency_Fields_Present */
4090 if (db[8] & (1 << 7))
4091 offset += 2;
4092
4093 /* I_Latency_Fields_Present */
4094 if (db[8] & (1 << 6))
4095 offset += 2;
4096
4097 /* the declared length is not long enough for the 2 first bytes
4098 * of additional video format capabilities */
c858cfca 4099 if (len < (8 + offset + 2))
7ebe1963
LD		 4100 goto out;
4101
c858cfca
DL		 4102 /* 3D_Present */
4103 offset++;
fbf46025 4104 if (db[8 + offset] & (1 << 7)) {
c858cfca
DL		 4105 modes += add_hdmi_mandatory_stereo_modes(connector);
4106
fbf46025
TW		 4107 /* 3D_Multi_present */
4108 multi_present = (db[8 + offset] & 0x60) >> 5;
4109 }
4110
c858cfca 4111 offset++;
7ebe1963 4112 vic_len = db[8 + offset] >> 5;
fbf46025 4113 hdmi_3d_len = db[8 + offset] & 0x1f;
7ebe1963
LD		 4114
4115 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
7ebe1963
LD		 4116 u8 vic;
4117
4118 vic = db[9 + offset + i];
1deee8d7 4119 modes += add_hdmi_mode(connector, vic);
7ebe1963 4120 }
fbf46025
TW		 4121 offset += 1 + vic_len;
4122
0e5083aa
TW		 4123 if (multi_present == 1)
4124 multi_len = 2;
4125 else if (multi_present == 2)
4126 multi_len = 4;
4127 else
4128 multi_len = 0;
fbf46025 4129
0e5083aa 4130 if (len < (8 + offset + hdmi_3d_len - 1))
fbf46025
TW		 4131 goto out;
4132
0e5083aa 4133 if (hdmi_3d_len < multi_len)
fbf46025
TW		 4134 goto out;
4135
0e5083aa
TW		 4136 if (multi_present == 1 || multi_present == 2) {
4137 /* 3D_Structure_ALL */
4138 structure_all = (db[8 + offset] << 8) | db[9 + offset];
fbf46025 4139
0e5083aa
TW		 4140 /* check if 3D_MASK is present */
4141 if (multi_present == 2)
4142 mask = (db[10 + offset] << 8) | db[11 + offset];
4143 else
4144 mask = 0xffff;
4145
4146 for (i = 0; i < 16; i++) {
4147 if (mask & (1 << i))
4148 modes += add_3d_struct_modes(connector,
4149 structure_all,
4150 video_db,
4151 video_len, i);
4152 }
4153 }
4154
4155 offset += multi_len;
4156
4157 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
4158 int vic_index;
4159 struct drm_display_mode *newmode = NULL;
4160 unsigned int newflag = 0;
4161 bool detail_present;
4162
4163 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
4164
4165 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
4166 break;
4167
4168 /* 2D_VIC_order_X */
4169 vic_index = db[8 + offset + i] >> 4;
4170
4171 /* 3D_Structure_X */
4172 switch (db[8 + offset + i] & 0x0f) {
4173 case 0:
4174 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
4175 break;
4176 case 6:
4177 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4178 break;
4179 case 8:
4180 /* 3D_Detail_X */
4181 if ((db[9 + offset + i] >> 4) == 1)
4182 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4183 break;
4184 }
4185
4186 if (newflag != 0) {
4187 newmode = drm_display_mode_from_vic_index(connector,
4188 video_db,
4189 video_len,
4190 vic_index);
4191
4192 if (newmode) {
4193 newmode->flags |= newflag;
4194 drm_mode_probed_add(connector, newmode);
4195 modes++;
4196 }
4197 }
4198
4199 if (detail_present)
4200 i++;
fbf46025 4201 }
7ebe1963
LD		 4202
4203out:
f1781e9b
VS		 4204 if (modes > 0)
4205 info->has_hdmi_infoframe = true;
7ebe1963
LD		 4206 return modes;
4207}
4208
9e50b9d5
VS		 4209static int
4210cea_db_payload_len(const u8 *db)
4211{
4212 return db[0] & 0x1f;
4213}
4214
87563fc0
SS		 4215static int
4216cea_db_extended_tag(const u8 *db)
4217{
4218 return db[1];
4219}
4220
9e50b9d5
VS		 4221static int
4222cea_db_tag(const u8 *db)
4223{
4224 return db[0] >> 5;
4225}
4226
4227static int
4228cea_revision(const u8 *cea)
4229{
5036c0d0
VS		 4230 /*
4231 * FIXME is this correct for the DispID variant?
4232 * The DispID spec doesn't really specify whether
4233 * this is the revision of the CEA extension or
4234 * the DispID CEA data block. And the only value
4235 * given as an example is 0.
4236 */
9e50b9d5
VS		 4237 return cea[1];
4238}
4239
4240static int
4241cea_db_offsets(const u8 *cea, int *start, int *end)
4242{
e28ad544
AR		 4243 /* DisplayID CTA extension blocks and top-level CEA EDID
4244 * block header definitions differ in the following bytes:
4245 * 1) Byte 2 of the header specifies length differently,
4246 * 2) Byte 3 is only present in the CEA top level block.
4247 *
4248 * The different definitions for byte 2 follow.
4249 *
4250 * DisplayID CTA extension block defines byte 2 as:
4251 * Number of payload bytes
4252 *
4253 * CEA EDID block defines byte 2 as:
4254 * Byte number (decimal) within this block where the 18-byte
4255 * DTDs begin. If no non-DTD data is present in this extension
4256 * block, the value should be set to 04h (the byte after next).
4257 * If set to 00h, there are no DTDs present in this block and
4258 * no non-DTD data.
4259 */
4260 if (cea[0] == DATA_BLOCK_CTA) {
6e8a942b
VS		 4261 /*
4262 * for_each_displayid_db() has already verified
4263 * that these stay within expected bounds.
4264 */
e28ad544
AR		 4265 *start = 3;
4266 *end = *start + cea[2];
4267 } else if (cea[0] == CEA_EXT) {
4268 /* Data block offset in CEA extension block */
4269 *start = 4;
4270 *end = cea[2];
4271 if (*end == 0)
4272 *end = 127;
4273 if (*end < 4 || *end > 127)
4274 return -ERANGE;
4275 } else {
c7581a41 4276 return -EOPNOTSUPP;
e28ad544
AR		 4277 }
4278
9e50b9d5
VS		 4279 return 0;
4280}
4281
7ebe1963
LD		 4282static bool cea_db_is_hdmi_vsdb(const u8 *db)
4283{
7ebe1963
LD		 4284 if (cea_db_tag(db) != VENDOR_BLOCK)
4285 return false;
4286
4287 if (cea_db_payload_len(db) < 5)
4288 return false;
4289
37eab1fe 4290 return oui(db[3], db[2], db[1]) == HDMI_IEEE_OUI;
7ebe1963
LD		 4291}
4292
50dd1bd1
TR		 4293static bool cea_db_is_hdmi_forum_vsdb(const u8 *db)
4294{
50dd1bd1
TR		 4295 if (cea_db_tag(db) != VENDOR_BLOCK)
4296 return false;
4297
4298 if (cea_db_payload_len(db) < 7)
4299 return false;
4300
37eab1fe 4301 return oui(db[3], db[2], db[1]) == HDMI_FORUM_IEEE_OUI;
50dd1bd1
TR		 4302}
4303
2869f599
PZ		 4304static bool cea_db_is_microsoft_vsdb(const u8 *db)
4305{
4306 if (cea_db_tag(db) != VENDOR_BLOCK)
4307 return false;
4308
4309 if (cea_db_payload_len(db) != 21)
4310 return false;
4311
4312 return oui(db[3], db[2], db[1]) == MICROSOFT_IEEE_OUI;
4313}
4314
1581b2df
VS		 4315static bool cea_db_is_vcdb(const u8 *db)
4316{
4317 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4318 return false;
4319
4320 if (cea_db_payload_len(db) != 2)
4321 return false;
4322
4323 if (cea_db_extended_tag(db) != EXT_VIDEO_CAPABILITY_BLOCK)
4324 return false;
4325
4326 return true;
4327}
4328
832d4f2f
SS		 4329static bool cea_db_is_y420cmdb(const u8 *db)
4330{
4331 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4332 return false;
4333
4334 if (!cea_db_payload_len(db))
4335 return false;
4336
4337 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB)
4338 return false;
4339
4340 return true;
4341}
4342
4343static bool cea_db_is_y420vdb(const u8 *db)
4344{
4345 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4346 return false;
4347
4348 if (!cea_db_payload_len(db))
4349 return false;
4350
4351 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420)
4352 return false;
4353
4354 return true;
4355}
4356
9e50b9d5
VS		 4357#define for_each_cea_db(cea, i, start, end) \
4358 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
4359
832d4f2f
SS		 4360static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector,
4361 const u8 *db)
4362{
4363 struct drm_display_info *info = &connector->display_info;
4364 struct drm_hdmi_info *hdmi = &info->hdmi;
4365 u8 map_len = cea_db_payload_len(db) - 1;
4366 u8 count;
4367 u64 map = 0;
4368
4369 if (map_len == 0) {
4370 /* All CEA modes support ycbcr420 sampling also.*/
4371 hdmi->y420_cmdb_map = U64_MAX;
c03d0b52 4372 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
832d4f2f
SS		 4373 return;
4374 }
4375
4376 /*
4377 * This map indicates which of the existing CEA block modes
4378 * from VDB can support YCBCR420 output too. So if bit=0 is
4379 * set, first mode from VDB can support YCBCR420 output too.
4380 * We will parse and keep this map, before parsing VDB itself
4381 * to avoid going through the same block again and again.
4382 *
4383 * Spec is not clear about max possible size of this block.
4384 * Clamping max bitmap block size at 8 bytes. Every byte can
4385 * address 8 CEA modes, in this way this map can address
4386 * 8*8 = first 64 SVDs.
4387 */
4388 if (WARN_ON_ONCE(map_len > 8))
4389 map_len = 8;
4390
4391 for (count = 0; count < map_len; count++)
4392 map |= (u64)db[2 + count] << (8 * count);
4393
4394 if (map)
c03d0b52 4395 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
832d4f2f
SS		 4396
4397 hdmi->y420_cmdb_map = map;
4398}
4399
54ac76f8 4400static int
f4e558ec 4401add_cea_modes(struct drm_connector *connector, const struct edid *edid)
54ac76f8 4402{
13ac3f55 4403 const u8 *cea = drm_find_cea_extension(edid);
fbf46025
TW		 4404 const u8 *db, *hdmi = NULL, *video = NULL;
4405 u8 dbl, hdmi_len, video_len = 0;
54ac76f8
CS		 4406 int modes = 0;
4407
9e50b9d5
VS		 4408 if (cea && cea_revision(cea) >= 3) {
4409 int i, start, end;
4410
4411 if (cea_db_offsets(cea, &start, &end))
4412 return 0;
4413
4414 for_each_cea_db(cea, i, start, end) {
4415 db = &cea[i];
4416 dbl = cea_db_payload_len(db);
4417
fbf46025
TW		 4418 if (cea_db_tag(db) == VIDEO_BLOCK) {
4419 video = db + 1;
4420 video_len = dbl;
4421 modes += do_cea_modes(connector, video, dbl);
832d4f2f 4422 } else if (cea_db_is_hdmi_vsdb(db)) {
c858cfca
DL		 4423 hdmi = db;
4424 hdmi_len = dbl;
832d4f2f
SS		 4425 } else if (cea_db_is_y420vdb(db)) {
4426 const u8 *vdb420 = &db[2];
4427
4428 /* Add 4:2:0(only) modes present in EDID */
4429 modes += do_y420vdb_modes(connector,
4430 vdb420,
4431 dbl - 1);
c858cfca 4432 }
54ac76f8
CS		 4433 }
4434 }
4435
c858cfca
DL		 4436 /*
4437 * We parse the HDMI VSDB after having added the cea modes as we will
4438 * be patching their flags when the sink supports stereo 3D.
4439 */
4440 if (hdmi)
fbf46025
TW		 4441 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
4442 video_len);
c858cfca 4443
54ac76f8
CS		 4444 return modes;
4445}
4446
fa3a7340
VS		 4447static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
4448{
4449 const struct drm_display_mode *cea_mode;
4450 int clock1, clock2, clock;
d9278b4c 4451 u8 vic;
fa3a7340
VS		 4452 const char *type;
4453
4c6bcf44
VS		 4454 /*
4455 * allow 5kHz clock difference either way to account for
4456 * the 10kHz clock resolution limit of detailed timings.
4457 */
d9278b4c
JN		 4458 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
4459 if (drm_valid_cea_vic(vic)) {
fa3a7340 4460 type = "CEA";
7befe621 4461 cea_mode = cea_mode_for_vic(vic);
fa3a7340
VS		 4462 clock1 = cea_mode->clock;
4463 clock2 = cea_mode_alternate_clock(cea_mode);
4464 } else {
d9278b4c
JN		 4465 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
4466 if (drm_valid_hdmi_vic(vic)) {
fa3a7340 4467 type = "HDMI";
d9278b4c 4468 cea_mode = &edid_4k_modes[vic];
fa3a7340
VS		 4469 clock1 = cea_mode->clock;
4470 clock2 = hdmi_mode_alternate_clock(cea_mode);
4471 } else {
4472 return;
4473 }
4474 }
4475
4476 /* pick whichever is closest */
4477 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
4478 clock = clock1;
4479 else
4480 clock = clock2;
4481
4482 if (mode->clock == clock)
4483 return;
4484
4485 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
d9278b4c 4486 type, vic, mode->clock, clock);
fa3a7340
VS		 4487 mode->clock = clock;
4488}
4489
e85959d6
US		 4490static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db)
4491{
4492 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4493 return false;
4494
4495 if (db[1] != HDR_STATIC_METADATA_BLOCK)
4496 return false;
4497
4498 if (cea_db_payload_len(db) < 3)
4499 return false;
4500
4501 return true;
4502}
4503
4504static uint8_t eotf_supported(const u8 *edid_ext)
4505{
4506 return edid_ext[2] &
4507 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
4508 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
b5e3eed1
VS		 4509 BIT(HDMI_EOTF_SMPTE_ST2084) |
4510 BIT(HDMI_EOTF_BT_2100_HLG));
e85959d6
US		 4511}
4512
4513static uint8_t hdr_metadata_type(const u8 *edid_ext)
4514{
4515 return edid_ext[3] &
4516 BIT(HDMI_STATIC_METADATA_TYPE1);
4517}
4518
4519static void
4520drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
4521{
4522 u16 len;
4523
4524 len = cea_db_payload_len(db);
4525
4526 connector->hdr_sink_metadata.hdmi_type1.eotf =
4527 eotf_supported(db);
4528 connector->hdr_sink_metadata.hdmi_type1.metadata_type =
4529 hdr_metadata_type(db);
4530
4531 if (len >= 4)
4532 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4];
4533 if (len >= 5)
4534 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5];
4535 if (len >= 6)
4536 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6];
4537}
4538
76adaa34 4539static void
23ebf8b9 4540drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
76adaa34 4541{
8504072a 4542 u8 len = cea_db_payload_len(db);
76adaa34 4543
f7da7785
JN		 4544 if (len >= 6 && (db[6] & (1 << 7)))
4545 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
8504072a
VS		 4546 if (len >= 8) {
4547 connector->latency_present[0] = db[8] >> 7;
4548 connector->latency_present[1] = (db[8] >> 6) & 1;
4549 }
4550 if (len >= 9)
4551 connector->video_latency[0] = db[9];
4552 if (len >= 10)
4553 connector->audio_latency[0] = db[10];
4554 if (len >= 11)
4555 connector->video_latency[1] = db[11];
4556 if (len >= 12)
4557 connector->audio_latency[1] = db[12];
76adaa34 4558
23ebf8b9
VS		 4559 DRM_DEBUG_KMS("HDMI: latency present %d %d, "
4560 "video latency %d %d, "
4561 "audio latency %d %d\n",
4562 connector->latency_present[0],
4563 connector->latency_present[1],
4564 connector->video_latency[0],
4565 connector->video_latency[1],
4566 connector->audio_latency[0],
4567 connector->audio_latency[1]);
76adaa34
WF		 4568}
4569
4570static void
4194442d 4571monitor_name(const struct detailed_timing *timing, void *data)
76adaa34 4572{
4194442d
JN		 4573 const char **res = data;
4574
4575 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME))
a7a131ac
VS		 4576 return;
4577
4194442d 4578 *res = timing->data.other_data.data.str.str;
14f77fdd
VS		 4579}
4580
c14e7241 4581static int get_monitor_name(const struct edid *edid, char name[13])
59f7c0fa 4582{
4194442d 4583 const char *edid_name = NULL;
59f7c0fa
JB		 4584 int mnl;
4585
4586 if (!edid || !name)
4587 return 0;
4588
eed628f1 4589 drm_for_each_detailed_block(edid, monitor_name, &edid_name);
59f7c0fa
JB		 4590 for (mnl = 0; edid_name && mnl < 13; mnl++) {
4591 if (edid_name[mnl] == 0x0a)
4592 break;
4593
4594 name[mnl] = edid_name[mnl];
4595 }
4596
4597 return mnl;
4598}
4599
4600/**
4601 * drm_edid_get_monitor_name - fetch the monitor name from the edid
4602 * @edid: monitor EDID information
4603 * @name: pointer to a character array to hold the name of the monitor
4604 * @bufsize: The size of the name buffer (should be at least 14 chars.)
4605 *
4606 */
f4e558ec 4607void drm_edid_get_monitor_name(const struct edid *edid, char *name, int bufsize)
59f7c0fa
JB		 4608{
4609 int name_length;
4610 char buf[13];
4d23f484 4611
59f7c0fa
JB		 4612 if (bufsize <= 0)
4613 return;
4614
4615 name_length = min(get_monitor_name(edid, buf), bufsize - 1);
4616 memcpy(name, buf, name_length);
4617 name[name_length] = '\0';
4618}
4619EXPORT_SYMBOL(drm_edid_get_monitor_name);
4620
42750d39
JN		 4621static void clear_eld(struct drm_connector *connector)
4622{
4623 memset(connector->eld, 0, sizeof(connector->eld));
4624
4625 connector->latency_present[0] = false;
4626 connector->latency_present[1] = false;
4627 connector->video_latency[0] = 0;
4628 connector->audio_latency[0] = 0;
4629 connector->video_latency[1] = 0;
4630 connector->audio_latency[1] = 0;
4631}
4632
79436a1c 4633/*
76adaa34
WF		 4634 * drm_edid_to_eld - build ELD from EDID
4635 * @connector: connector corresponding to the HDMI/DP sink
4636 * @edid: EDID to parse
4637 *
db6cf833 4638 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
1d1c3665 4639 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
76adaa34 4640 */
f4e558ec
JN		 4641static void drm_edid_to_eld(struct drm_connector *connector,
4642 const struct edid *edid)
76adaa34
WF		 4643{
4644 uint8_t *eld = connector->eld;
43d16d84
JN		 4645 const u8 *cea;
4646 const u8 *db;
7c018782 4647 int total_sad_count = 0;
76adaa34
WF		 4648 int mnl;
4649 int dbl;
4650
42750d39 4651 clear_eld(connector);
85c91580 4652
e9bd0b84
JN		 4653 if (!edid)
4654 return;
4655
76adaa34
WF		 4656 cea = drm_find_cea_extension(edid);
4657 if (!cea) {
4658 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
4659 return;
4660 }
4661
f7da7785
JN		 4662 mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
4663 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]);
59f7c0fa 4664
f7da7785
JN		 4665 eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT;
4666 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
76adaa34 4667
f7da7785 4668 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
76adaa34 4669
f7da7785
JN		 4670 eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0];
4671 eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1];
4672 eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0];
4673 eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1];
76adaa34 4674
9e50b9d5
VS		 4675 if (cea_revision(cea) >= 3) {
4676 int i, start, end;
deec222e 4677 int sad_count;
9e50b9d5
VS		 4678
4679 if (cea_db_offsets(cea, &start, &end)) {
4680 start = 0;
4681 end = 0;
4682 }
4683
4684 for_each_cea_db(cea, i, start, end) {
4685 db = &cea[i];
4686 dbl = cea_db_payload_len(db);
4687
4688 switch (cea_db_tag(db)) {
a0ab734d
CS		 4689 case AUDIO_BLOCK:
4690 /* Audio Data Block, contains SADs */
7c018782
VS		 4691 sad_count = min(dbl / 3, 15 - total_sad_count);
4692 if (sad_count >= 1)
f7da7785 4693 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
7c018782
VS		 4694 &db[1], sad_count * 3);
4695 total_sad_count += sad_count;
a0ab734d
CS		 4696 break;
4697 case SPEAKER_BLOCK:
9e50b9d5
VS		 4698 /* Speaker Allocation Data Block */
4699 if (dbl >= 1)
f7da7785 4700 eld[DRM_ELD_SPEAKER] = db[1];
a0ab734d
CS		 4701 break;
4702 case VENDOR_BLOCK:
4703 /* HDMI Vendor-Specific Data Block */
14f77fdd 4704 if (cea_db_is_hdmi_vsdb(db))
23ebf8b9 4705 drm_parse_hdmi_vsdb_audio(connector, db);
a0ab734d
CS		 4706 break;
4707 default:
4708 break;
4709 }
76adaa34 4710 }
9e50b9d5 4711 }
f7da7785 4712 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
76adaa34 4713
1d1c3665
JN		 4714 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
4715 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4716 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
4717 else
4718 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
76adaa34 4719
938fd8aa
JN		 4720 eld[DRM_ELD_BASELINE_ELD_LEN] =
4721 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
4722
4723 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
7c018782 4724 drm_eld_size(eld), total_sad_count);
76adaa34 4725}
76adaa34 4726
fe214163
RM		 4727/**
4728 * drm_edid_to_sad - extracts SADs from EDID
4729 * @edid: EDID to parse
4730 * @sads: pointer that will be set to the extracted SADs
4731 *
4732 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
fe214163 4733 *
db6cf833
TR		 4734 * Note: The returned pointer needs to be freed using kfree().
4735 *
4736 * Return: The number of found SADs or negative number on error.
fe214163 4737 */
f4e558ec 4738int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads)
fe214163
RM		 4739{
4740 int count = 0;
4741 int i, start, end, dbl;
43d16d84 4742 const u8 *cea;
fe214163
RM		 4743
4744 cea = drm_find_cea_extension(edid);
4745 if (!cea) {
4746 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
42908007 4747 return 0;
fe214163
RM		 4748 }
4749
4750 if (cea_revision(cea) < 3) {
4751 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
42908007 4752 return 0;
fe214163
RM		 4753 }
4754
4755 if (cea_db_offsets(cea, &start, &end)) {
4756 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4757 return -EPROTO;
4758 }
4759
4760 for_each_cea_db(cea, i, start, end) {
43d16d84 4761 const u8 *db = &cea[i];
fe214163
RM		 4762
4763 if (cea_db_tag(db) == AUDIO_BLOCK) {
4764 int j;
948de842 4765
fe214163
RM		 4766 dbl = cea_db_payload_len(db);
4767
4768 count = dbl / 3; /* SAD is 3B */
4769 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
4770 if (!*sads)
4771 return -ENOMEM;
4772 for (j = 0; j < count; j++) {
43d16d84 4773 const u8 *sad = &db[1 + j * 3];
fe214163
RM		 4774
4775 (*sads)[j].format = (sad[0] & 0x78) >> 3;
4776 (*sads)[j].channels = sad[0] & 0x7;
4777 (*sads)[j].freq = sad[1] & 0x7F;
4778 (*sads)[j].byte2 = sad[2];
4779 }
4780 break;
4781 }
4782 }
4783
4784 return count;
4785}
4786EXPORT_SYMBOL(drm_edid_to_sad);
4787
d105f476
AD		 4788/**
4789 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
4790 * @edid: EDID to parse
4791 * @sadb: pointer to the speaker block
4792 *
4793 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
d105f476 4794 *
db6cf833
TR		 4795 * Note: The returned pointer needs to be freed using kfree().
4796 *
4797 * Return: The number of found Speaker Allocation Blocks or negative number on
4798 * error.
d105f476 4799 */
f4e558ec 4800int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb)
d105f476
AD		 4801{
4802 int count = 0;
4803 int i, start, end, dbl;
4804 const u8 *cea;
4805
4806 cea = drm_find_cea_extension(edid);
4807 if (!cea) {
4808 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
42908007 4809 return 0;
d105f476
AD		 4810 }
4811
4812 if (cea_revision(cea) < 3) {
4813 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
42908007 4814 return 0;
d105f476
AD		 4815 }
4816
4817 if (cea_db_offsets(cea, &start, &end)) {
4818 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4819 return -EPROTO;
4820 }
4821
4822 for_each_cea_db(cea, i, start, end) {
4823 const u8 *db = &cea[i];
4824
4825 if (cea_db_tag(db) == SPEAKER_BLOCK) {
4826 dbl = cea_db_payload_len(db);
4827
4828 /* Speaker Allocation Data Block */
4829 if (dbl == 3) {
89086bca 4830 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
618e3776
AD		 4831 if (!*sadb)
4832 return -ENOMEM;
d105f476
AD		 4833 count = dbl;
4834 break;
4835 }
4836 }
4837 }
4838
4839 return count;
4840}
4841EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
4842
76adaa34 4843/**
db6cf833 4844 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
76adaa34
WF		 4845 * @connector: connector associated with the HDMI/DP sink
4846 * @mode: the display mode
db6cf833
TR		 4847 *
4848 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
4849 * the sink doesn't support audio or video.
76adaa34
WF		 4850 */
4851int drm_av_sync_delay(struct drm_connector *connector,
3a818d35 4852 const struct drm_display_mode *mode)
76adaa34
WF		 4853{
4854 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
4855 int a, v;
4856
4857 if (!connector->latency_present[0])
4858 return 0;
4859 if (!connector->latency_present[1])
4860 i = 0;
4861
4862 a = connector->audio_latency[i];
4863 v = connector->video_latency[i];
4864
4865 /*
4866 * HDMI/DP sink doesn't support audio or video?
4867 */
4868 if (a == 255 || v == 255)
4869 return 0;
4870
4871 /*
4872 * Convert raw EDID values to millisecond.
4873 * Treat unknown latency as 0ms.
4874 */
4875 if (a)
4876 a = min(2 * (a - 1), 500);
4877 if (v)
4878 v = min(2 * (v - 1), 500);
4879
4880 return max(v - a, 0);
4881}
4882EXPORT_SYMBOL(drm_av_sync_delay);
4883
8fe9790d 4884/**
db6cf833 4885 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
8fe9790d
ZW		 4886 * @edid: monitor EDID information
4887 *
4888 * Parse the CEA extension according to CEA-861-B.
db6cf833 4889 *
a92d083d
LP		 4890 * Drivers that have added the modes parsed from EDID to drm_display_info
4891 * should use &drm_display_info.is_hdmi instead of calling this function.
4892 *
db6cf833 4893 * Return: True if the monitor is HDMI, false if not or unknown.
8fe9790d 4894 */
f4e558ec 4895bool drm_detect_hdmi_monitor(const struct edid *edid)
8fe9790d 4896{
43d16d84 4897 const u8 *edid_ext;
14f77fdd 4898 int i;
8fe9790d 4899 int start_offset, end_offset;
8fe9790d
ZW		 4900
4901 edid_ext = drm_find_cea_extension(edid);
4902 if (!edid_ext)
14f77fdd 4903 return false;
f23c20c8 4904
9e50b9d5 4905 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
14f77fdd 4906 return false;
f23c20c8
ML		 4907
4908 /*
4909 * Because HDMI identifier is in Vendor Specific Block,
4910 * search it from all data blocks of CEA extension.
4911 */
9e50b9d5 4912 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
14f77fdd
VS		 4913 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
4914 return true;
f23c20c8
ML		 4915 }
4916
14f77fdd 4917 return false;
f23c20c8
ML		 4918}
4919EXPORT_SYMBOL(drm_detect_hdmi_monitor);
4920
8fe9790d
ZW		 4921/**
4922 * drm_detect_monitor_audio - check monitor audio capability
fc66811c 4923 * @edid: EDID block to scan
8fe9790d
ZW		 4924 *
4925 * Monitor should have CEA extension block.
4926 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
4927 * audio' only. If there is any audio extension block and supported
4928 * audio format, assume at least 'basic audio' support, even if 'basic
4929 * audio' is not defined in EDID.
4930 *
db6cf833 4931 * Return: True if the monitor supports audio, false otherwise.
8fe9790d 4932 */
f4e558ec 4933bool drm_detect_monitor_audio(const struct edid *edid)
8fe9790d 4934{
43d16d84 4935 const u8 *edid_ext;
8fe9790d
ZW		 4936 int i, j;
4937 bool has_audio = false;
4938 int start_offset, end_offset;
4939
4940 edid_ext = drm_find_cea_extension(edid);
4941 if (!edid_ext)
4942 goto end;
4943
5662abf6
CC		 4944 has_audio = (edid_ext[0] == CEA_EXT &&
4945 (edid_ext[3] & EDID_BASIC_AUDIO) != 0);
8fe9790d
ZW		 4946
4947 if (has_audio) {
4948 DRM_DEBUG_KMS("Monitor has basic audio support\n");
4949 goto end;
4950 }
4951
9e50b9d5
VS		 4952 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4953 goto end;
8fe9790d 4954
9e50b9d5
VS		 4955 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4956 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
8fe9790d 4957 has_audio = true;
9e50b9d5 4958 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
8fe9790d
ZW		 4959 DRM_DEBUG_KMS("CEA audio format %d\n",
4960 (edid_ext[i + j] >> 3) & 0xf);
4961 goto end;
4962 }
4963 }
4964end:
4965 return has_audio;
4966}
4967EXPORT_SYMBOL(drm_detect_monitor_audio);
4968
b1edd6a6 4969
c8127cf0
VS		 4970/**
4971 * drm_default_rgb_quant_range - default RGB quantization range
4972 * @mode: display mode
4973 *
4974 * Determine the default RGB quantization range for the mode,
4975 * as specified in CEA-861.
4976 *
4977 * Return: The default RGB quantization range for the mode
4978 */
4979enum hdmi_quantization_range
4980drm_default_rgb_quant_range(const struct drm_display_mode *mode)
4981{
4982 /* All CEA modes other than VIC 1 use limited quantization range. */
4983 return drm_match_cea_mode(mode) > 1 ?
4984 HDMI_QUANTIZATION_RANGE_LIMITED :
4985 HDMI_QUANTIZATION_RANGE_FULL;
4986}
4987EXPORT_SYMBOL(drm_default_rgb_quant_range);
4988
1581b2df
VS		 4989static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
4990{
4991 struct drm_display_info *info = &connector->display_info;
4992
4993 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]);
4994
4995 if (db[2] & EDID_CEA_VCDB_QS)
4996 info->rgb_quant_range_selectable = true;
4997}
4998
4499d488
SS		 4999static
5000void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane)
5001{
5002 switch (max_frl_rate) {
5003 case 1:
5004 *max_lanes = 3;
5005 *max_rate_per_lane = 3;
5006 break;
5007 case 2:
5008 *max_lanes = 3;
5009 *max_rate_per_lane = 6;
5010 break;
5011 case 3:
5012 *max_lanes = 4;
5013 *max_rate_per_lane = 6;
5014 break;
5015 case 4:
5016 *max_lanes = 4;
5017 *max_rate_per_lane = 8;
5018 break;
5019 case 5:
5020 *max_lanes = 4;
5021 *max_rate_per_lane = 10;
5022 break;
5023 case 6:
5024 *max_lanes = 4;
5025 *max_rate_per_lane = 12;
5026 break;
5027 case 0:
5028 default:
5029 *max_lanes = 0;
5030 *max_rate_per_lane = 0;
5031 }
5032}
5033
e6a9a2c3
SS		 5034static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
5035 const u8 *db)
5036{
5037 u8 dc_mask;
5038 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
5039
5040 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
9068e02f 5041 hdmi->y420_dc_modes = dc_mask;
e6a9a2c3
SS		 5042}
5043
afa1c763
SS		 5044static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector,
5045 const u8 *hf_vsdb)
5046{
62c58af3
SS		 5047 struct drm_display_info *display = &connector->display_info;
5048 struct drm_hdmi_info *hdmi = &display->hdmi;
afa1c763 5049
f1781e9b
VS		 5050 display->has_hdmi_infoframe = true;
5051
afa1c763
SS		 5052 if (hf_vsdb[6] & 0x80) {
5053 hdmi->scdc.supported = true;
5054 if (hf_vsdb[6] & 0x40)
5055 hdmi->scdc.read_request = true;
5056 }
62c58af3
SS		 5057
5058 /*
5059 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
5060 * And as per the spec, three factors confirm this:
5061 * * Availability of a HF-VSDB block in EDID (check)
5062 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
5063 * * SCDC support available (let's check)
5064 * Lets check it out.
5065 */
5066
5067 if (hf_vsdb[5]) {
5068 /* max clock is 5000 KHz times block value */
5069 u32 max_tmds_clock = hf_vsdb[5] * 5000;
5070 struct drm_scdc *scdc = &hdmi->scdc;
5071
5072 if (max_tmds_clock > 340000) {
5073 display->max_tmds_clock = max_tmds_clock;
5074 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
5075 display->max_tmds_clock);
5076 }
5077
5078 if (scdc->supported) {
5079 scdc->scrambling.supported = true;
5080
dbe2d2bf 5081 /* Few sinks support scrambling for clocks < 340M */
62c58af3
SS		 5082 if ((hf_vsdb[6] & 0x8))
5083 scdc->scrambling.low_rates = true;
5084 }
5085 }
e6a9a2c3 5086
4499d488
SS		 5087 if (hf_vsdb[7]) {
5088 u8 max_frl_rate;
76ee7b90
AN		 5089 u8 dsc_max_frl_rate;
5090 u8 dsc_max_slices;
5091 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap;
4499d488
SS		 5092
5093 DRM_DEBUG_KMS("hdmi_21 sink detected. parsing edid\n");
5094 max_frl_rate = (hf_vsdb[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4;
5095 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes,
5096 &hdmi->max_frl_rate_per_lane);
76ee7b90
AN		 5097 hdmi_dsc->v_1p2 = hf_vsdb[11] & DRM_EDID_DSC_1P2;
5098
5099 if (hdmi_dsc->v_1p2) {
5100 hdmi_dsc->native_420 = hf_vsdb[11] & DRM_EDID_DSC_NATIVE_420;
5101 hdmi_dsc->all_bpp = hf_vsdb[11] & DRM_EDID_DSC_ALL_BPP;
5102
5103 if (hf_vsdb[11] & DRM_EDID_DSC_16BPC)
5104 hdmi_dsc->bpc_supported = 16;
5105 else if (hf_vsdb[11] & DRM_EDID_DSC_12BPC)
5106 hdmi_dsc->bpc_supported = 12;
5107 else if (hf_vsdb[11] & DRM_EDID_DSC_10BPC)
5108 hdmi_dsc->bpc_supported = 10;
5109 else
5110 hdmi_dsc->bpc_supported = 0;
5111
5112 dsc_max_frl_rate = (hf_vsdb[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4;
5113 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes,
5114 &hdmi_dsc->max_frl_rate_per_lane);
5115 hdmi_dsc->total_chunk_kbytes = hf_vsdb[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES;
5116
5117 dsc_max_slices = hf_vsdb[12] & DRM_EDID_DSC_MAX_SLICES;
5118 switch (dsc_max_slices) {
5119 case 1:
5120 hdmi_dsc->max_slices = 1;
5121 hdmi_dsc->clk_per_slice = 340;
5122 break;
5123 case 2:
5124 hdmi_dsc->max_slices = 2;
5125 hdmi_dsc->clk_per_slice = 340;
5126 break;
5127 case 3:
5128 hdmi_dsc->max_slices = 4;
5129 hdmi_dsc->clk_per_slice = 340;
5130 break;
5131 case 4:
5132 hdmi_dsc->max_slices = 8;
5133 hdmi_dsc->clk_per_slice = 340;
5134 break;
5135 case 5:
5136 hdmi_dsc->max_slices = 8;
5137 hdmi_dsc->clk_per_slice = 400;
5138 break;
5139 case 6:
5140 hdmi_dsc->max_slices = 12;
5141 hdmi_dsc->clk_per_slice = 400;
5142 break;
5143 case 7:
5144 hdmi_dsc->max_slices = 16;
5145 hdmi_dsc->clk_per_slice = 400;
5146 break;
5147 case 0:
5148 default:
5149 hdmi_dsc->max_slices = 0;
5150 hdmi_dsc->clk_per_slice = 0;
5151 }
5152 }
4499d488
SS		 5153 }
5154
e6a9a2c3 5155 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb);
afa1c763
SS		 5156}
5157
1cea146a
VS		 5158static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
5159 const u8 *hdmi)
d0c94692 5160{
1826750f 5161 struct drm_display_info *info = &connector->display_info;
d0c94692
MK		 5162 unsigned int dc_bpc = 0;
5163
1cea146a
VS		 5164 /* HDMI supports at least 8 bpc */
5165 info->bpc = 8;
d0c94692 5166
1cea146a
VS		 5167 if (cea_db_payload_len(hdmi) < 6)
5168 return;
5169
5170 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
5171 dc_bpc = 10;
4adc33f3 5172 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_30;
1cea146a
VS		 5173 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
5174 connector->name);
5175 }
5176
5177 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
5178 dc_bpc = 12;
4adc33f3 5179 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_36;
1cea146a
VS		 5180 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
5181 connector->name);
5182 }
5183
5184 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
5185 dc_bpc = 16;
4adc33f3 5186 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_48;
1cea146a
VS		 5187 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
5188 connector->name);
5189 }
5190
5191 if (dc_bpc == 0) {
5192 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
5193 connector->name);
5194 return;
5195 }
5196
5197 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
5198 connector->name, dc_bpc);
5199 info->bpc = dc_bpc;
d0c94692 5200
1cea146a
VS		 5201 /* YCRCB444 is optional according to spec. */
5202 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
4adc33f3 5203 info->edid_hdmi_ycbcr444_dc_modes = info->edid_hdmi_rgb444_dc_modes;
1cea146a
VS		 5204 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
5205 connector->name);
5206 }
d0c94692 5207
1cea146a
VS		 5208 /*
5209 * Spec says that if any deep color mode is supported at all,
5210 * then deep color 36 bit must be supported.
5211 */
5212 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
5213 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
5214 connector->name);
5215 }
5216}
d0c94692 5217
23ebf8b9
VS		 5218static void
5219drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
5220{
5221 struct drm_display_info *info = &connector->display_info;
5222 u8 len = cea_db_payload_len(db);
5223
a92d083d
LP		 5224 info->is_hdmi = true;
5225
23ebf8b9
VS		 5226 if (len >= 6)
5227 info->dvi_dual = db[6] & 1;
5228 if (len >= 7)
5229 info->max_tmds_clock = db[7] * 5000;
5230
5231 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
5232 "max TMDS clock %d kHz\n",
5233 info->dvi_dual,
5234 info->max_tmds_clock);
5235
5236 drm_parse_hdmi_deep_color_info(connector, db);
5237}
5238
2869f599
PZ		 5239/*
5240 * See EDID extension for head-mounted and specialized monitors, specified at:
5241 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/specialized-monitors-edid-extension
5242 */
5243static void drm_parse_microsoft_vsdb(struct drm_connector *connector,
5244 const u8 *db)
5245{
5246 struct drm_display_info *info = &connector->display_info;
5247 u8 version = db[4];
5248 bool desktop_usage = db[5] & BIT(6);
5249
5250 /* Version 1 and 2 for HMDs, version 3 flags desktop usage explicitly */
5251 if (version == 1 || version == 2 || (version == 3 && !desktop_usage))
5252 info->non_desktop = true;
5253
5254 drm_dbg_kms(connector->dev, "HMD or specialized display VSDB version %u: 0x%02x\n",
5255 version, db[5]);
5256}
5257
1cea146a 5258static void drm_parse_cea_ext(struct drm_connector *connector,
170178fe 5259 const struct edid *edid)
1cea146a
VS		 5260{
5261 struct drm_display_info *info = &connector->display_info;
5262 const u8 *edid_ext;
5263 int i, start, end;
d0c94692 5264
1cea146a
VS		 5265 edid_ext = drm_find_cea_extension(edid);
5266 if (!edid_ext)
5267 return;
d0c94692 5268
1cea146a 5269 info->cea_rev = edid_ext[1];
d0c94692 5270
1cea146a
VS		 5271 /* The existence of a CEA block should imply RGB support */
5272 info->color_formats = DRM_COLOR_FORMAT_RGB444;
7344bad7
JN		 5273
5274 /* CTA DisplayID Data Block does not have byte #3 */
5275 if (edid_ext[0] == CEA_EXT) {
5276 if (edid_ext[3] & EDID_CEA_YCRCB444)
5277 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
5278 if (edid_ext[3] & EDID_CEA_YCRCB422)
5279 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
5280 }
1cea146a
VS		 5281
5282 if (cea_db_offsets(edid_ext, &start, &end))
5283 return;
5284
5285 for_each_cea_db(edid_ext, i, start, end) {
5286 const u8 *db = &edid_ext[i];
5287
23ebf8b9
VS		 5288 if (cea_db_is_hdmi_vsdb(db))
5289 drm_parse_hdmi_vsdb_video(connector, db);
afa1c763
SS		 5290 if (cea_db_is_hdmi_forum_vsdb(db))
5291 drm_parse_hdmi_forum_vsdb(connector, db);
2869f599
PZ		 5292 if (cea_db_is_microsoft_vsdb(db))
5293 drm_parse_microsoft_vsdb(connector, db);
832d4f2f
SS		 5294 if (cea_db_is_y420cmdb(db))
5295 drm_parse_y420cmdb_bitmap(connector, db);
1581b2df
VS		 5296 if (cea_db_is_vcdb(db))
5297 drm_parse_vcdb(connector, db);
e85959d6
US		 5298 if (cea_db_is_hdmi_hdr_metadata_block(db))
5299 drm_parse_hdr_metadata_block(connector, db);
1cea146a 5300 }
d0c94692
MK		 5301}
5302
a1d11d1e 5303static
4194442d 5304void get_monitor_range(const struct detailed_timing *timing,
a1d11d1e
MN		 5305 void *info_monitor_range)
5306{
5307 struct drm_monitor_range_info *monitor_range = info_monitor_range;
5308 const struct detailed_non_pixel *data = &timing->data.other_data;
5309 const struct detailed_data_monitor_range *range = &data->data.range;
5310
e379814b 5311 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
a1d11d1e
MN		 5312 return;
5313
5314 /*
5315 * Check for flag range limits only. If flag == 1 then
5316 * no additional timing information provided.
5317 * Default GTF, GTF Secondary curve and CVT are not
5318 * supported
5319 */
5320 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG)
5321 return;
5322
5323 monitor_range->min_vfreq = range->min_vfreq;
5324 monitor_range->max_vfreq = range->max_vfreq;
5325}
5326
5327static
5328void drm_get_monitor_range(struct drm_connector *connector,
5329 const struct edid *edid)
5330{
5331 struct drm_display_info *info = &connector->display_info;
5332
5333 if (!version_greater(edid, 1, 1))
5334 return;
5335
eed628f1 5336 drm_for_each_detailed_block(edid, get_monitor_range,
a1d11d1e
MN		 5337 &info->monitor_range);
5338
5339 DRM_DEBUG_KMS("Supported Monitor Refresh rate range is %d Hz - %d Hz\n",
5340 info->monitor_range.min_vfreq,
5341 info->monitor_range.max_vfreq);
5342}
5343
18a9cbbe
JN		 5344static void drm_parse_vesa_mso_data(struct drm_connector *connector,
5345 const struct displayid_block *block)
5346{
5347 struct displayid_vesa_vendor_specific_block *vesa =
5348 (struct displayid_vesa_vendor_specific_block *)block;
5349 struct drm_display_info *info = &connector->display_info;
5350
5351 if (block->num_bytes < 3) {
5352 drm_dbg_kms(connector->dev, "Unexpected vendor block size %u\n",
5353 block->num_bytes);
5354 return;
5355 }
5356
5357 if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI)
5358 return;
5359
5360 if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
5361 drm_dbg_kms(connector->dev, "Unexpected VESA vendor block size\n");
5362 return;
5363 }
5364
5365 switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
5366 default:
5367 drm_dbg_kms(connector->dev, "Reserved MSO mode value\n");
5368 fallthrough;
5369 case 0:
5370 info->mso_stream_count = 0;
5371 break;
5372 case 1:
5373 info->mso_stream_count = 2; /* 2 or 4 links */
5374 break;
5375 case 2:
5376 info->mso_stream_count = 4; /* 4 links */
5377 break;
5378 }
5379
5380 if (!info->mso_stream_count) {
5381 info->mso_pixel_overlap = 0;
5382 return;
5383 }
5384
5385 info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
5386 if (info->mso_pixel_overlap > 8) {
5387 drm_dbg_kms(connector->dev, "Reserved MSO pixel overlap value %u\n",
5388 info->mso_pixel_overlap);
5389 info->mso_pixel_overlap = 8;
5390 }
5391
5392 drm_dbg_kms(connector->dev, "MSO stream count %u, pixel overlap %u\n",
5393 info->mso_stream_count, info->mso_pixel_overlap);
5394}
5395
5396static void drm_update_mso(struct drm_connector *connector, const struct edid *edid)
5397{
5398 const struct displayid_block *block;
5399 struct displayid_iter iter;
5400
5401 displayid_iter_edid_begin(edid, &iter);
5402 displayid_iter_for_each(block, &iter) {
5403 if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC)
5404 drm_parse_vesa_mso_data(connector, block);
5405 }
5406 displayid_iter_end(&iter);
5407}
5408
170178fe
KP		 5409/* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
5410 * all of the values which would have been set from EDID
5411 */
5412void
5413drm_reset_display_info(struct drm_connector *connector)
5414{
5415 struct drm_display_info *info = &connector->display_info;
5416
5417 info->width_mm = 0;
5418 info->height_mm = 0;
5419
5420 info->bpc = 0;
5421 info->color_formats = 0;
5422 info->cea_rev = 0;
5423 info->max_tmds_clock = 0;
5424 info->dvi_dual = false;
a92d083d 5425 info->is_hdmi = false;
170178fe 5426 info->has_hdmi_infoframe = false;
1581b2df 5427 info->rgb_quant_range_selectable = false;
1f6b8eef 5428 memset(&info->hdmi, 0, sizeof(info->hdmi));
170178fe 5429
70c0b80d
MR		 5430 info->edid_hdmi_rgb444_dc_modes = 0;
5431 info->edid_hdmi_ycbcr444_dc_modes = 0;
5432
170178fe 5433 info->non_desktop = 0;
a1d11d1e 5434 memset(&info->monitor_range, 0, sizeof(info->monitor_range));
18a9cbbe
JN		 5435
5436 info->mso_stream_count = 0;
5437 info->mso_pixel_overlap = 0;
170178fe 5438}
170178fe
KP		 5439
5440u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid)
3b11228b 5441{
1826750f 5442 struct drm_display_info *info = &connector->display_info;
ebec9a7b 5443
170178fe
KP		 5444 u32 quirks = edid_get_quirks(edid);
5445
1f6b8eef
VS		 5446 drm_reset_display_info(connector);
5447
3b11228b
JB		 5448 info->width_mm = edid->width_cm * 10;
5449 info->height_mm = edid->height_cm * 10;
5450
a1d11d1e
MN		 5451 drm_get_monitor_range(connector, edid);
5452
a988bc72 5453 if (edid->revision < 3)
ce99534e 5454 goto out;
3b11228b
JB		 5455
5456 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
ce99534e 5457 goto out;
3b11228b 5458
ecbd4912 5459 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
1cea146a 5460 drm_parse_cea_ext(connector, edid);
d0c94692 5461
210a021d
MK		 5462 /*
5463 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
5464 *
5465 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
5466 * tells us to assume 8 bpc color depth if the EDID doesn't have
5467 * extensions which tell otherwise.
5468 */
3bde449f
VS		 5469 if (info->bpc == 0 && edid->revision == 3 &&
5470 edid->input & DRM_EDID_DIGITAL_DFP_1_X) {
210a021d
MK		 5471 info->bpc = 8;
5472 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
5473 connector->name, info->bpc);
5474 }
5475
a988bc72
LPC		 5476 /* Only defined for 1.4 with digital displays */
5477 if (edid->revision < 4)
ce99534e 5478 goto out;
a988bc72 5479
3b11228b
JB		 5480 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
5481 case DRM_EDID_DIGITAL_DEPTH_6:
5482 info->bpc = 6;
5483 break;
5484 case DRM_EDID_DIGITAL_DEPTH_8:
5485 info->bpc = 8;
5486 break;
5487 case DRM_EDID_DIGITAL_DEPTH_10:
5488 info->bpc = 10;
5489 break;
5490 case DRM_EDID_DIGITAL_DEPTH_12:
5491 info->bpc = 12;
5492 break;
5493 case DRM_EDID_DIGITAL_DEPTH_14:
5494 info->bpc = 14;
5495 break;
5496 case DRM_EDID_DIGITAL_DEPTH_16:
5497 info->bpc = 16;
5498 break;
5499 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
5500 default:
5501 info->bpc = 0;
5502 break;
5503 }
da05a5a7 5504
d0c94692 5505 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
25933820 5506 connector->name, info->bpc);
d0c94692 5507
ee58808d 5508 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
c03d0b52 5509 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
ee58808d 5510 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
c03d0b52 5511 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
18a9cbbe
JN		 5512
5513 drm_update_mso(connector, edid);
5514
ce99534e
JN		 5515out:
5516 if (quirks & EDID_QUIRK_NON_DESKTOP) {
5517 drm_dbg_kms(connector->dev, "Non-desktop display%s\n",
5518 info->non_desktop ? " (redundant quirk)" : "");
5519 info->non_desktop = true;
5520 }
5521
170178fe 5522 return quirks;
3b11228b
JB		 5523}
5524
a39ed680 5525static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
80ecb5d7
YB		 5526 struct displayid_detailed_timings_1 *timings,
5527 bool type_7)
a39ed680
DA		 5528{
5529 struct drm_display_mode *mode;
5530 unsigned pixel_clock = (timings->pixel_clock[0] |
5531 (timings->pixel_clock[1] << 8) |
6292b8ef 5532 (timings->pixel_clock[2] << 16)) + 1;
a39ed680
DA		 5533 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
5534 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
5535 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
5536 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
5537 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
5538 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
5539 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
5540 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
5541 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
5542 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
948de842 5543
a39ed680
DA		 5544 mode = drm_mode_create(dev);
5545 if (!mode)
5546 return NULL;
5547
80ecb5d7
YB		 5548 /* resolution is kHz for type VII, and 10 kHz for type I */
5549 mode->clock = type_7 ? pixel_clock : pixel_clock * 10;
a39ed680
DA		 5550 mode->hdisplay = hactive;
5551 mode->hsync_start = mode->hdisplay + hsync;
5552 mode->hsync_end = mode->hsync_start + hsync_width;
5553 mode->htotal = mode->hdisplay + hblank;
5554
5555 mode->vdisplay = vactive;
5556 mode->vsync_start = mode->vdisplay + vsync;
5557 mode->vsync_end = mode->vsync_start + vsync_width;
5558 mode->vtotal = mode->vdisplay + vblank;
5559
5560 mode->flags = 0;
5561 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
5562 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
5563 mode->type = DRM_MODE_TYPE_DRIVER;
5564
5565 if (timings->flags & 0x80)
5566 mode->type |= DRM_MODE_TYPE_PREFERRED;
a39ed680
DA		 5567 drm_mode_set_name(mode);
5568
5569 return mode;
5570}
5571
5572static int add_displayid_detailed_1_modes(struct drm_connector *connector,
43d16d84 5573 const struct displayid_block *block)
a39ed680
DA		 5574{
5575 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
5576 int i;
5577 int num_timings;
5578 struct drm_display_mode *newmode;
5579 int num_modes = 0;
80ecb5d7 5580 bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING;
a39ed680
DA		 5581 /* blocks must be multiple of 20 bytes length */
5582 if (block->num_bytes % 20)
5583 return 0;
5584
5585 num_timings = block->num_bytes / 20;
5586 for (i = 0; i < num_timings; i++) {
5587 struct displayid_detailed_timings_1 *timings = &det->timings[i];
5588
80ecb5d7 5589 newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7);
a39ed680
DA		 5590 if (!newmode)
5591 continue;
5592
5593 drm_mode_probed_add(connector, newmode);
5594 num_modes++;
5595 }
5596 return num_modes;
5597}
5598
5599static int add_displayid_detailed_modes(struct drm_connector *connector,
f4e558ec 5600 const struct edid *edid)
a39ed680 5601{
43d16d84 5602 const struct displayid_block *block;
5ef88dc5 5603 struct displayid_iter iter;
a39ed680
DA		 5604 int num_modes = 0;
5605
5ef88dc5
JN		 5606 displayid_iter_edid_begin(edid, &iter);
5607 displayid_iter_for_each(block, &iter) {
80ecb5d7
YB		 5608 if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING ||
5609 block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING)
5ef88dc5 5610 num_modes += add_displayid_detailed_1_modes(connector, block);
a39ed680 5611 }
5ef88dc5 5612 displayid_iter_end(&iter);
7f261afd 5613
a39ed680
DA		 5614 return num_modes;
5615}
5616
f40ab034
JN		 5617static int drm_edid_connector_update(struct drm_connector *connector,
5618 const struct edid *edid)
f453ba04
DA		 5619{
5620 int num_modes = 0;
5621 u32 quirks;
5622
5623 if (edid == NULL) {
c945b8c1 5624 clear_eld(connector);
f453ba04
DA		 5625 return 0;
5626 }
f453ba04 5627
c945b8c1
JN		 5628 drm_edid_to_eld(connector, edid);
5629
0f0f8708
SS		 5630 /*
5631 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
5632 * To avoid multiple parsing of same block, lets parse that map
5633 * from sink info, before parsing CEA modes.
5634 */
170178fe 5635 quirks = drm_add_display_info(connector, edid);
0f0f8708 5636
c867df70
AJ		 5637 /*
5638 * EDID spec says modes should be preferred in this order:
5639 * - preferred detailed mode
5640 * - other detailed modes from base block
5641 * - detailed modes from extension blocks
5642 * - CVT 3-byte code modes
5643 * - standard timing codes
5644 * - established timing codes
5645 * - modes inferred from GTF or CVT range information
5646 *
13931579 5647 * We get this pretty much right.
c867df70
AJ		 5648 *
5649 * XXX order for additional mode types in extension blocks?
5650 */
13931579
AJ		 5651 num_modes += add_detailed_modes(connector, edid, quirks);
5652 num_modes += add_cvt_modes(connector, edid);
c867df70
AJ		 5653 num_modes += add_standard_modes(connector, edid);
5654 num_modes += add_established_modes(connector, edid);
54ac76f8 5655 num_modes += add_cea_modes(connector, edid);
e6e79209 5656 num_modes += add_alternate_cea_modes(connector, edid);
a39ed680 5657 num_modes += add_displayid_detailed_modes(connector, edid);
4d53dc0c
VS		 5658 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
5659 num_modes += add_inferred_modes(connector, edid);
f453ba04
DA		 5660
5661 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
5662 edid_fixup_preferred(connector, quirks);
5663
e10aec65
MK		 5664 if (quirks & EDID_QUIRK_FORCE_6BPC)
5665 connector->display_info.bpc = 6;
5666
49d45a31
RM		 5667 if (quirks & EDID_QUIRK_FORCE_8BPC)
5668 connector->display_info.bpc = 8;
5669
e345da82
MK		 5670 if (quirks & EDID_QUIRK_FORCE_10BPC)
5671 connector->display_info.bpc = 10;
5672
bc5b9641
MK		 5673 if (quirks & EDID_QUIRK_FORCE_12BPC)
5674 connector->display_info.bpc = 12;
5675
f453ba04
DA		 5676 return num_modes;
5677}
f40ab034
JN		 5678
5679/**
5680 * drm_add_edid_modes - add modes from EDID data, if available
5681 * @connector: connector we're probing
5682 * @edid: EDID data
5683 *
5684 * Add the specified modes to the connector's mode list. Also fills out the
5685 * &drm_display_info structure and ELD in @connector with any information which
5686 * can be derived from the edid.
5687 *
5688 * Return: The number of modes added or 0 if we couldn't find any.
5689 */
5690int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
5691{
5692 if (edid && !drm_edid_is_valid(edid)) {
5693 drm_warn(connector->dev, "%s: EDID invalid.\n",
5694 connector->name);
5695 edid = NULL;
5696 }
5697
5698 return drm_edid_connector_update(connector, edid);
5699}
f453ba04 5700EXPORT_SYMBOL(drm_add_edid_modes);
f0fda0a4
ZY		 5701
5702/**
5703 * drm_add_modes_noedid - add modes for the connectors without EDID
5704 * @connector: connector we're probing
5705 * @hdisplay: the horizontal display limit
5706 * @vdisplay: the vertical display limit
5707 *
5708 * Add the specified modes to the connector's mode list. Only when the
5709 * hdisplay/vdisplay is not beyond the given limit, it will be added.
5710 *
db6cf833 5711 * Return: The number of modes added or 0 if we couldn't find any.
f0fda0a4
ZY		 5712 */
5713int drm_add_modes_noedid(struct drm_connector *connector,
5714 int hdisplay, int vdisplay)
5715{
5716 int i, count, num_modes = 0;
b1f559ec 5717 struct drm_display_mode *mode;
f0fda0a4
ZY		 5718 struct drm_device *dev = connector->dev;
5719
fbb40b28 5720 count = ARRAY_SIZE(drm_dmt_modes);
f0fda0a4
ZY		 5721 if (hdisplay < 0)
5722 hdisplay = 0;
5723 if (vdisplay < 0)
5724 vdisplay = 0;
5725
5726 for (i = 0; i < count; i++) {
b1f559ec 5727 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
948de842 5728
f0fda0a4
ZY		 5729 if (hdisplay && vdisplay) {
5730 /*
5731 * Only when two are valid, they will be used to check
5732 * whether the mode should be added to the mode list of
5733 * the connector.
5734 */
5735 if (ptr->hdisplay > hdisplay ||
5736 ptr->vdisplay > vdisplay)
5737 continue;
5738 }
f985dedb
AJ		 5739 if (drm_mode_vrefresh(ptr) > 61)
5740 continue;
f0fda0a4
ZY		 5741 mode = drm_mode_duplicate(dev, ptr);
5742 if (mode) {
5743 drm_mode_probed_add(connector, mode);
5744 num_modes++;
5745 }
5746 }
5747 return num_modes;
5748}
5749EXPORT_SYMBOL(drm_add_modes_noedid);
10a85120 5750
db6cf833
TR		 5751/**
5752 * drm_set_preferred_mode - Sets the preferred mode of a connector
5753 * @connector: connector whose mode list should be processed
5754 * @hpref: horizontal resolution of preferred mode
5755 * @vpref: vertical resolution of preferred mode
5756 *
5757 * Marks a mode as preferred if it matches the resolution specified by @hpref
5758 * and @vpref.
5759 */
3cf70daf
GH		 5760void drm_set_preferred_mode(struct drm_connector *connector,
5761 int hpref, int vpref)
5762{
5763 struct drm_display_mode *mode;
5764
5765 list_for_each_entry(mode, &connector->probed_modes, head) {
db6cf833 5766 if (mode->hdisplay == hpref &&
9d3de138 5767 mode->vdisplay == vpref)
3cf70daf
GH		 5768 mode->type |= DRM_MODE_TYPE_PREFERRED;
5769 }
5770}
5771EXPORT_SYMBOL(drm_set_preferred_mode);
5772
192a3aa0 5773static bool is_hdmi2_sink(const struct drm_connector *connector)
13d0add3
VS		 5774{
5775 /*
5776 * FIXME: sil-sii8620 doesn't have a connector around when
5777 * we need one, so we have to be prepared for a NULL connector.
5778 */
5779 if (!connector)
5780 return true;
5781
5782 return connector->display_info.hdmi.scdc.supported ||
c03d0b52 5783 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR420;
13d0add3
VS		 5784}
5785
2cdbfd66
US		 5786static inline bool is_eotf_supported(u8 output_eotf, u8 sink_eotf)
5787{
5788 return sink_eotf & BIT(output_eotf);
5789}
5790
5791/**
5792 * drm_hdmi_infoframe_set_hdr_metadata() - fill an HDMI DRM infoframe with
5793 * HDR metadata from userspace
5794 * @frame: HDMI DRM infoframe
6ac98829 5795 * @conn_state: Connector state containing HDR metadata
2cdbfd66
US		 5796 *
5797 * Return: 0 on success or a negative error code on failure.
5798 */
5799int
5800drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame,
5801 const struct drm_connector_state *conn_state)
5802{
5803 struct drm_connector *connector;
5804 struct hdr_output_metadata *hdr_metadata;
5805 int err;
5806
5807 if (!frame || !conn_state)
5808 return -EINVAL;
5809
5810 connector = conn_state->connector;
5811
5812 if (!conn_state->hdr_output_metadata)
5813 return -EINVAL;
5814
5815 hdr_metadata = conn_state->hdr_output_metadata->data;
5816
5817 if (!hdr_metadata || !connector)
5818 return -EINVAL;
5819
5820 /* Sink EOTF is Bit map while infoframe is absolute values */
5821 if (!is_eotf_supported(hdr_metadata->hdmi_metadata_type1.eotf,
5822 connector->hdr_sink_metadata.hdmi_type1.eotf)) {
5823 DRM_DEBUG_KMS("EOTF Not Supported\n");
5824 return -EINVAL;
5825 }
5826
5827 err = hdmi_drm_infoframe_init(frame);
5828 if (err < 0)
5829 return err;
5830
5831 frame->eotf = hdr_metadata->hdmi_metadata_type1.eotf;
5832 frame->metadata_type = hdr_metadata->hdmi_metadata_type1.metadata_type;
5833
5834 BUILD_BUG_ON(sizeof(frame->display_primaries) !=
5835 sizeof(hdr_metadata->hdmi_metadata_type1.display_primaries));
5836 BUILD_BUG_ON(sizeof(frame->white_point) !=
5837 sizeof(hdr_metadata->hdmi_metadata_type1.white_point));
5838
5839 memcpy(&frame->display_primaries,
5840 &hdr_metadata->hdmi_metadata_type1.display_primaries,
5841 sizeof(frame->display_primaries));
5842
5843 memcpy(&frame->white_point,
5844 &hdr_metadata->hdmi_metadata_type1.white_point,
5845 sizeof(frame->white_point));
5846
5847 frame->max_display_mastering_luminance =
5848 hdr_metadata->hdmi_metadata_type1.max_display_mastering_luminance;
5849 frame->min_display_mastering_luminance =
5850 hdr_metadata->hdmi_metadata_type1.min_display_mastering_luminance;
5851 frame->max_fall = hdr_metadata->hdmi_metadata_type1.max_fall;
5852 frame->max_cll = hdr_metadata->hdmi_metadata_type1.max_cll;
5853
5854 return 0;
5855}
5856EXPORT_SYMBOL(drm_hdmi_infoframe_set_hdr_metadata);
5857
192a3aa0 5858static u8 drm_mode_hdmi_vic(const struct drm_connector *connector,
949561eb
VS		 5859 const struct drm_display_mode *mode)
5860{
5861 bool has_hdmi_infoframe = connector ?
5862 connector->display_info.has_hdmi_infoframe : false;
5863
5864 if (!has_hdmi_infoframe)
5865 return 0;
5866
5867 /* No HDMI VIC when signalling 3D video format */
5868 if (mode->flags & DRM_MODE_FLAG_3D_MASK)
5869 return 0;
5870
5871 return drm_match_hdmi_mode(mode);
5872}
5873
192a3aa0 5874static u8 drm_mode_cea_vic(const struct drm_connector *connector,
cfd6f8c3
VS		 5875 const struct drm_display_mode *mode)
5876{
cfd6f8c3
VS		 5877 u8 vic;
5878
5879 /*
5880 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
5881 * we should send its VIC in vendor infoframes, else send the
5882 * VIC in AVI infoframes. Lets check if this mode is present in
5883 * HDMI 1.4b 4K modes
5884 */
949561eb 5885 if (drm_mode_hdmi_vic(connector, mode))
cfd6f8c3
VS		 5886 return 0;
5887
5888 vic = drm_match_cea_mode(mode);
5889
5890 /*
5891 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
5892 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
5893 * have to make sure we dont break HDMI 1.4 sinks.
5894 */
5895 if (!is_hdmi2_sink(connector) && vic > 64)
5896 return 0;
5897
5898 return vic;
5899}
5900
10a85120
TR		 5901/**
5902 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
5903 * data from a DRM display mode
5904 * @frame: HDMI AVI infoframe
13d0add3 5905 * @connector: the connector
10a85120
TR		 5906 * @mode: DRM display mode
5907 *
db6cf833 5908 * Return: 0 on success or a negative error code on failure.
10a85120
TR		 5909 */
5910int
5911drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
192a3aa0 5912 const struct drm_connector *connector,
13d0add3 5913 const struct drm_display_mode *mode)
10a85120 5914{
a9c266c2 5915 enum hdmi_picture_aspect picture_aspect;
d2b43473 5916 u8 vic, hdmi_vic;
10a85120
TR		 5917
5918 if (!frame || !mode)
5919 return -EINVAL;
5920
5ee0caf1 5921 hdmi_avi_infoframe_init(frame);
10a85120 5922
bf02db99
DL		 5923 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
5924 frame->pixel_repeat = 1;
5925
d2b43473
WL		 5926 vic = drm_mode_cea_vic(connector, mode);
5927 hdmi_vic = drm_mode_hdmi_vic(connector, mode);
0c1f528c 5928
10a85120 5929 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
0967e6a5 5930
50525c33
SL		 5931 /*
5932 * As some drivers don't support atomic, we can't use connector state.
5933 * So just initialize the frame with default values, just the same way
5934 * as it's done with other properties here.
5935 */
5936 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
5937 frame->itc = 0;
5938
69ab6d35
VK		 5939 /*
5940 * Populate picture aspect ratio from either
d2b43473 5941 * user input (if specified) or from the CEA/HDMI mode lists.
69ab6d35 5942 */
a9c266c2 5943 picture_aspect = mode->picture_aspect_ratio;
d2b43473
WL		 5944 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) {
5945 if (vic)
5946 picture_aspect = drm_get_cea_aspect_ratio(vic);
5947 else if (hdmi_vic)
5948 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic);
5949 }
0967e6a5 5950
a9c266c2
VS		 5951 /*
5952 * The infoframe can't convey anything but none, 4:3
5953 * and 16:9, so if the user has asked for anything else
5954 * we can only satisfy it by specifying the right VIC.
5955 */
5956 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
d2b43473
WL		 5957 if (vic) {
5958 if (picture_aspect != drm_get_cea_aspect_ratio(vic))
5959 return -EINVAL;
5960 } else if (hdmi_vic) {
5961 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic))
5962 return -EINVAL;
5963 } else {
a9c266c2 5964 return -EINVAL;
d2b43473
WL		 5965 }
5966
a9c266c2
VS		 5967 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
5968 }
5969
d2b43473 5970 frame->video_code = vic;
a9c266c2 5971 frame->picture_aspect = picture_aspect;
10a85120 5972 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
24d01805 5973 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
10a85120
TR		 5974
5975 return 0;
5976}
5977EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
83dd0008 5978
0d68b887
US		 5979/* HDMI Colorspace Spec Definitions */
5980#define FULL_COLORIMETRY_MASK 0x1FF
5981#define NORMAL_COLORIMETRY_MASK 0x3
5982#define EXTENDED_COLORIMETRY_MASK 0x7
5983#define EXTENDED_ACE_COLORIMETRY_MASK 0xF
5984
5985#define C(x) ((x) << 0)
5986#define EC(x) ((x) << 2)
5987#define ACE(x) ((x) << 5)
5988
5989#define HDMI_COLORIMETRY_NO_DATA 0x0
5990#define HDMI_COLORIMETRY_SMPTE_170M_YCC (C(1) | EC(0) | ACE(0))
5991#define HDMI_COLORIMETRY_BT709_YCC (C(2) | EC(0) | ACE(0))
5992#define HDMI_COLORIMETRY_XVYCC_601 (C(3) | EC(0) | ACE(0))
5993#define HDMI_COLORIMETRY_XVYCC_709 (C(3) | EC(1) | ACE(0))
5994#define HDMI_COLORIMETRY_SYCC_601 (C(3) | EC(2) | ACE(0))
5995#define HDMI_COLORIMETRY_OPYCC_601 (C(3) | EC(3) | ACE(0))
5996#define HDMI_COLORIMETRY_OPRGB (C(3) | EC(4) | ACE(0))
5997#define HDMI_COLORIMETRY_BT2020_CYCC (C(3) | EC(5) | ACE(0))
5998#define HDMI_COLORIMETRY_BT2020_RGB (C(3) | EC(6) | ACE(0))
5999#define HDMI_COLORIMETRY_BT2020_YCC (C(3) | EC(6) | ACE(0))
6000#define HDMI_COLORIMETRY_DCI_P3_RGB_D65 (C(3) | EC(7) | ACE(0))
6001#define HDMI_COLORIMETRY_DCI_P3_RGB_THEATER (C(3) | EC(7) | ACE(1))
6002
6003static const u32 hdmi_colorimetry_val[] = {
6004 [DRM_MODE_COLORIMETRY_NO_DATA] = HDMI_COLORIMETRY_NO_DATA,
6005 [DRM_MODE_COLORIMETRY_SMPTE_170M_YCC] = HDMI_COLORIMETRY_SMPTE_170M_YCC,
6006 [DRM_MODE_COLORIMETRY_BT709_YCC] = HDMI_COLORIMETRY_BT709_YCC,
6007 [DRM_MODE_COLORIMETRY_XVYCC_601] = HDMI_COLORIMETRY_XVYCC_601,
6008 [DRM_MODE_COLORIMETRY_XVYCC_709] = HDMI_COLORIMETRY_XVYCC_709,
6009 [DRM_MODE_COLORIMETRY_SYCC_601] = HDMI_COLORIMETRY_SYCC_601,
6010 [DRM_MODE_COLORIMETRY_OPYCC_601] = HDMI_COLORIMETRY_OPYCC_601,
6011 [DRM_MODE_COLORIMETRY_OPRGB] = HDMI_COLORIMETRY_OPRGB,
6012 [DRM_MODE_COLORIMETRY_BT2020_CYCC] = HDMI_COLORIMETRY_BT2020_CYCC,
6013 [DRM_MODE_COLORIMETRY_BT2020_RGB] = HDMI_COLORIMETRY_BT2020_RGB,
6014 [DRM_MODE_COLORIMETRY_BT2020_YCC] = HDMI_COLORIMETRY_BT2020_YCC,
6015};
6016
6017#undef C
6018#undef EC
6019#undef ACE
6020
6021/**
4a46e5d2
MR		 6022 * drm_hdmi_avi_infoframe_colorimetry() - fill the HDMI AVI infoframe
6023 * colorimetry information
0d68b887
US		 6024 * @frame: HDMI AVI infoframe
6025 * @conn_state: connector state
6026 */
6027void
4a46e5d2 6028drm_hdmi_avi_infoframe_colorimetry(struct hdmi_avi_infoframe *frame,
0d68b887
US		 6029 const struct drm_connector_state *conn_state)
6030{
6031 u32 colorimetry_val;
6032 u32 colorimetry_index = conn_state->colorspace & FULL_COLORIMETRY_MASK;
6033
6034 if (colorimetry_index >= ARRAY_SIZE(hdmi_colorimetry_val))
6035 colorimetry_val = HDMI_COLORIMETRY_NO_DATA;
6036 else
6037 colorimetry_val = hdmi_colorimetry_val[colorimetry_index];
6038
6039 frame->colorimetry = colorimetry_val & NORMAL_COLORIMETRY_MASK;
6040 /*
6041 * ToDo: Extend it for ACE formats as well. Modify the infoframe
6042 * structure and extend it in drivers/video/hdmi
6043 */
6044 frame->extended_colorimetry = (colorimetry_val >> 2) &
6045 EXTENDED_COLORIMETRY_MASK;
6046}
4a46e5d2 6047EXPORT_SYMBOL(drm_hdmi_avi_infoframe_colorimetry);
0d68b887 6048
a2ce26f8
VS		 6049/**
6050 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
6051 * quantization range information
6052 * @frame: HDMI AVI infoframe
13d0add3 6053 * @connector: the connector
779c4c28 6054 * @mode: DRM display mode
a2ce26f8 6055 * @rgb_quant_range: RGB quantization range (Q)
a2ce26f8
VS		 6056 */
6057void
6058drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
192a3aa0 6059 const struct drm_connector *connector,
779c4c28 6060 const struct drm_display_mode *mode,
1581b2df 6061 enum hdmi_quantization_range rgb_quant_range)
a2ce26f8 6062{
1581b2df
VS		 6063 const struct drm_display_info *info = &connector->display_info;
6064
a2ce26f8
VS		 6065 /*
6066 * CEA-861:
6067 * "A Source shall not send a non-zero Q value that does not correspond
6068 * to the default RGB Quantization Range for the transmitted Picture
6069 * unless the Sink indicates support for the Q bit in a Video
6070 * Capabilities Data Block."
779c4c28
VS		 6071 *
6072 * HDMI 2.0 recommends sending non-zero Q when it does match the
6073 * default RGB quantization range for the mode, even when QS=0.
a2ce26f8 6074 */
1581b2df 6075 if (info->rgb_quant_range_selectable ||
779c4c28 6076 rgb_quant_range == drm_default_rgb_quant_range(mode))
a2ce26f8
VS		 6077 frame->quantization_range = rgb_quant_range;
6078 else
6079 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
fcc8a22c
VS		 6080
6081 /*
6082 * CEA-861-F:
6083 * "When transmitting any RGB colorimetry, the Source should set the
6084 * YQ-field to match the RGB Quantization Range being transmitted
6085 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
6086 * set YQ=1) and the Sink shall ignore the YQ-field."
9271c0ca
VS		 6087 *
6088 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
6089 * by non-zero YQ when receiving RGB. There doesn't seem to be any
6090 * good way to tell which version of CEA-861 the sink supports, so
6091 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
6092 * on on CEA-861-F.
fcc8a22c 6093 */
13d0add3 6094 if (!is_hdmi2_sink(connector) ||
9271c0ca 6095 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
fcc8a22c
VS		 6096 frame->ycc_quantization_range =
6097 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
6098 else
6099 frame->ycc_quantization_range =
6100 HDMI_YCC_QUANTIZATION_RANGE_FULL;
a2ce26f8
VS		 6101}
6102EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
6103
076d9a5d
VS		 6104/**
6105 * drm_hdmi_avi_infoframe_bars() - fill the HDMI AVI infoframe
6106 * bar information
6107 * @frame: HDMI AVI infoframe
6108 * @conn_state: connector state
6109 */
6110void
6111drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe *frame,
6112 const struct drm_connector_state *conn_state)
6113{
6114 frame->right_bar = conn_state->tv.margins.right;
6115 frame->left_bar = conn_state->tv.margins.left;
6116 frame->top_bar = conn_state->tv.margins.top;
6117 frame->bottom_bar = conn_state->tv.margins.bottom;
6118}
6119EXPORT_SYMBOL(drm_hdmi_avi_infoframe_bars);
6120
4eed4a0a
DL		 6121static enum hdmi_3d_structure
6122s3d_structure_from_display_mode(const struct drm_display_mode *mode)
6123{
6124 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
6125
6126 switch (layout) {
6127 case DRM_MODE_FLAG_3D_FRAME_PACKING:
6128 return HDMI_3D_STRUCTURE_FRAME_PACKING;
6129 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
6130 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
6131 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
6132 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
6133 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
6134 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
6135 case DRM_MODE_FLAG_3D_L_DEPTH:
6136 return HDMI_3D_STRUCTURE_L_DEPTH;
6137 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
6138 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
6139 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
6140 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
6141 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
6142 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
6143 default:
6144 return HDMI_3D_STRUCTURE_INVALID;
6145 }
6146}
6147
83dd0008
LD		 6148/**
6149 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
6150 * data from a DRM display mode
6151 * @frame: HDMI vendor infoframe
f1781e9b 6152 * @connector: the connector
83dd0008
LD		 6153 * @mode: DRM display mode
6154 *
6155 * Note that there's is a need to send HDMI vendor infoframes only when using a
6156 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
6157 * function will return -EINVAL, error that can be safely ignored.
6158 *
db6cf833 6159 * Return: 0 on success or a negative error code on failure.
83dd0008
LD		 6160 */
6161int
6162drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
192a3aa0 6163 const struct drm_connector *connector,
83dd0008
LD		 6164 const struct drm_display_mode *mode)
6165{
f1781e9b
VS		 6166 /*
6167 * FIXME: sil-sii8620 doesn't have a connector around when
6168 * we need one, so we have to be prepared for a NULL connector.
6169 */
6170 bool has_hdmi_infoframe = connector ?
6171 connector->display_info.has_hdmi_infoframe : false;
83dd0008 6172 int err;
83dd0008
LD		 6173
6174 if (!frame || !mode)
6175 return -EINVAL;
6176
f1781e9b
VS		 6177 if (!has_hdmi_infoframe)
6178 return -EINVAL;
6179
949561eb
VS		 6180 err = hdmi_vendor_infoframe_init(frame);
6181 if (err < 0)
6182 return err;
4eed4a0a 6183
f1781e9b
VS		 6184 /*
6185 * Even if it's not absolutely necessary to send the infoframe
6186 * (ie.vic==0 and s3d_struct==0) we will still send it if we
6187 * know that the sink can handle it. This is based on a
6188 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
0ae865ef 6189 * have trouble realizing that they should switch from 3D to 2D
f1781e9b
VS		 6190 * mode if the source simply stops sending the infoframe when
6191 * it wants to switch from 3D to 2D.
6192 */
949561eb 6193 frame->vic = drm_mode_hdmi_vic(connector, mode);
f1781e9b 6194 frame->s3d_struct = s3d_structure_from_display_mode(mode);
83dd0008
LD		 6195
6196 return 0;
6197}
6198EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
40d9b043 6199
7f261afd
VS		 6200static void drm_parse_tiled_block(struct drm_connector *connector,
6201 const struct displayid_block *block)
5e546cd5 6202{
092c367a 6203 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
5e546cd5
DA		 6204 u16 w, h;
6205 u8 tile_v_loc, tile_h_loc;
6206 u8 num_v_tile, num_h_tile;
6207 struct drm_tile_group *tg;
6208
6209 w = tile->tile_size[0] | tile->tile_size[1] << 8;
6210 h = tile->tile_size[2] | tile->tile_size[3] << 8;
6211
6212 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
6213 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
6214 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
6215 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
6216
6217 connector->has_tile = true;
6218 if (tile->tile_cap & 0x80)
6219 connector->tile_is_single_monitor = true;
6220
6221 connector->num_h_tile = num_h_tile + 1;
6222 connector->num_v_tile = num_v_tile + 1;
6223 connector->tile_h_loc = tile_h_loc;
6224 connector->tile_v_loc = tile_v_loc;
6225 connector->tile_h_size = w + 1;
6226 connector->tile_v_size = h + 1;
6227
6228 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
6229 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
6230 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
6231 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
6232 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
6233
6234 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
392f9fcb 6235 if (!tg)
5e546cd5 6236 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
5e546cd5 6237 if (!tg)
7f261afd 6238 return;
5e546cd5
DA		 6239
6240 if (connector->tile_group != tg) {
6241 /* if we haven't got a pointer,
6242 take the reference, drop ref to old tile group */
392f9fcb 6243 if (connector->tile_group)
5e546cd5 6244 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5e546cd5 6245 connector->tile_group = tg;
392f9fcb 6246 } else {
5e546cd5
DA		 6247 /* if same tile group, then release the ref we just took. */
6248 drm_mode_put_tile_group(connector->dev, tg);
392f9fcb 6249 }
5e546cd5
DA		 6250}
6251
092c367a
VS		 6252void drm_update_tile_info(struct drm_connector *connector,
6253 const struct edid *edid)
40d9b043 6254{
bfd4e192
JN		 6255 const struct displayid_block *block;
6256 struct displayid_iter iter;
36881184 6257
40d9b043 6258 connector->has_tile = false;
7f261afd 6259
bfd4e192
JN		 6260 displayid_iter_edid_begin(edid, &iter);
6261 displayid_iter_for_each(block, &iter) {
6262 if (block->tag == DATA_BLOCK_TILED_DISPLAY)
6263 drm_parse_tiled_block(connector, block);
40d9b043 6264 }
bfd4e192 6265 displayid_iter_end(&iter);
40d9b043 6266
7f261afd 6267 if (!connector->has_tile && connector->tile_group) {
40d9b043
DA		 6268 drm_mode_put_tile_group(connector->dev, connector->tile_group);
6269 connector->tile_group = NULL;
6270 }
40d9b043 6271}
Linux 6.x block layer and io_uring tree(s)