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drm/edid: Don't clear formats if using deep color
[linux-2.6-block.git] / drivers / gpu / drm / drm_edid.c
CommitLineData
f453ba04
DA		 1/*
2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
61e57a8d 5 * Copyright 2010 Red Hat, Inc.
f453ba04
DA		 6 *
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
8 * FB layer.
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 */
9c79edec 30
18a9cbbe 31#include <linux/bitfield.h>
10a85120 32#include <linux/hdmi.h>
f453ba04 33#include <linux/i2c.h>
9c79edec 34#include <linux/kernel.h>
47819ba2 35#include <linux/module.h>
36b73b05 36#include <linux/pci.h>
9c79edec 37#include <linux/slab.h>
5cb8eaa2 38#include <linux/vga_switcheroo.h>
9c79edec
JN		 39
40#include <drm/drm_displayid.h>
41#include <drm/drm_drv.h>
760285e7 42#include <drm/drm_edid.h>
9338203c 43#include <drm/drm_encoder.h>
9c79edec 44#include <drm/drm_print.h>
62c58af3 45#include <drm/drm_scdc_helper.h>
f453ba04 46
969218fe
TI		 47#include "drm_crtc_internal.h"
48
13931579
AJ		 49#define version_greater(edid, maj, min) \
50 (((edid)->version > (maj)) || \
51 ((edid)->version == (maj) && (edid)->revision > (min)))
f453ba04 52
37eab1fe
JN		 53static int oui(u8 first, u8 second, u8 third)
54{
55 return (first << 16) | (second << 8) | third;
56}
57
d1ff6409
AJ		 58#define EDID_EST_TIMINGS 16
59#define EDID_STD_TIMINGS 8
60#define EDID_DETAILED_TIMINGS 4
f453ba04
DA		 61
62/*
63 * EDID blocks out in the wild have a variety of bugs, try to collect
64 * them here (note that userspace may work around broken monitors first,
65 * but fixes should make their way here so that the kernel "just works"
66 * on as many displays as possible).
67 */
68
69/* First detailed mode wrong, use largest 60Hz mode */
70#define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
71/* Reported 135MHz pixel clock is too high, needs adjustment */
72#define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
73/* Prefer the largest mode at 75 Hz */
74#define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
75/* Detail timing is in cm not mm */
76#define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
77/* Detailed timing descriptors have bogus size values, so just take the
78 * maximum size and use that.
79 */
80#define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
f453ba04
DA		 81/* use +hsync +vsync for detailed mode */
82#define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
bc42aabc
AJ		 83/* Force reduced-blanking timings for detailed modes */
84#define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
49d45a31
RM		 85/* Force 8bpc */
86#define EDID_QUIRK_FORCE_8BPC (1 << 8)
bc5b9641
MK		 87/* Force 12bpc */
88#define EDID_QUIRK_FORCE_12BPC (1 << 9)
e10aec65
MK		 89/* Force 6bpc */
90#define EDID_QUIRK_FORCE_6BPC (1 << 10)
e345da82
MK		 91/* Force 10bpc */
92#define EDID_QUIRK_FORCE_10BPC (1 << 11)
66660d4c
DA		 93/* Non desktop display (i.e. HMD) */
94#define EDID_QUIRK_NON_DESKTOP (1 << 12)
3c537889 95
2869f599
PZ		 96#define MICROSOFT_IEEE_OUI 0xca125c
97
13931579
AJ		 98struct detailed_mode_closure {
99 struct drm_connector *connector;
100 struct edid *edid;
101 bool preferred;
102 u32 quirks;
103 int modes;
104};
f453ba04 105
5c61259e
ZY		 106#define LEVEL_DMT 0
107#define LEVEL_GTF 1
7a374350
AJ		 108#define LEVEL_GTF2 2
109#define LEVEL_CVT 3
5c61259e 110
7d1be0a0 111#define EDID_QUIRK(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _quirks) \
e8de4d55 112{ \
7d1be0a0
DA		 113 .panel_id = drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, \
114 product_id), \
e8de4d55
DA		 115 .quirks = _quirks \
116}
117
23c4cfbd 118static const struct edid_quirk {
e8de4d55 119 u32 panel_id;
f453ba04
DA		 120 u32 quirks;
121} edid_quirk_list[] = {
122 /* Acer AL1706 */
7d1be0a0 123 EDID_QUIRK('A', 'C', 'R', 44358, EDID_QUIRK_PREFER_LARGE_60),
f453ba04 124 /* Acer F51 */
7d1be0a0 125 EDID_QUIRK('A', 'P', 'I', 0x7602, EDID_QUIRK_PREFER_LARGE_60),
f453ba04 126
e10aec65 127 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
7d1be0a0 128 EDID_QUIRK('A', 'E', 'O', 0, EDID_QUIRK_FORCE_6BPC),
e10aec65 129
0711a43b 130 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
7d1be0a0 131 EDID_QUIRK('B', 'O', 'E', 0x78b, EDID_QUIRK_FORCE_6BPC),
0711a43b 132
06998a75 133 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
7d1be0a0 134 EDID_QUIRK('C', 'P', 'T', 0x17df, EDID_QUIRK_FORCE_6BPC),
06998a75 135
25da7504 136 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
7d1be0a0 137 EDID_QUIRK('S', 'D', 'C', 0x3652, EDID_QUIRK_FORCE_6BPC),
25da7504 138
922dceff 139 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
7d1be0a0 140 EDID_QUIRK('B', 'O', 'E', 0x0771, EDID_QUIRK_FORCE_6BPC),
922dceff 141
f453ba04 142 /* Belinea 10 15 55 */
7d1be0a0
DA		 143 EDID_QUIRK('M', 'A', 'X', 1516, EDID_QUIRK_PREFER_LARGE_60),
144 EDID_QUIRK('M', 'A', 'X', 0x77e, EDID_QUIRK_PREFER_LARGE_60),
f453ba04
DA		 145
146 /* Envision Peripherals, Inc. EN-7100e */
7d1be0a0 147 EDID_QUIRK('E', 'P', 'I', 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH),
ba1163de 148 /* Envision EN2028 */
7d1be0a0 149 EDID_QUIRK('E', 'P', 'I', 8232, EDID_QUIRK_PREFER_LARGE_60),
f453ba04
DA		 150
151 /* Funai Electronics PM36B */
7d1be0a0 152 EDID_QUIRK('F', 'C', 'M', 13600, EDID_QUIRK_PREFER_LARGE_75 |
e8de4d55 153 EDID_QUIRK_DETAILED_IN_CM),
f453ba04 154
e345da82 155 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
7d1be0a0 156 EDID_QUIRK('L', 'G', 'D', 764, EDID_QUIRK_FORCE_10BPC),
e345da82 157
f453ba04 158 /* LG Philips LCD LP154W01-A5 */
7d1be0a0
DA		 159 EDID_QUIRK('L', 'P', 'L', 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
160 EDID_QUIRK('L', 'P', 'L', 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
f453ba04 161
f453ba04 162 /* Samsung SyncMaster 205BW. Note: irony */
7d1be0a0 163 EDID_QUIRK('S', 'A', 'M', 541, EDID_QUIRK_DETAILED_SYNC_PP),
f453ba04 164 /* Samsung SyncMaster 22[5-6]BW */
7d1be0a0
DA		 165 EDID_QUIRK('S', 'A', 'M', 596, EDID_QUIRK_PREFER_LARGE_60),
166 EDID_QUIRK('S', 'A', 'M', 638, EDID_QUIRK_PREFER_LARGE_60),
bc42aabc 167
bc5b9641 168 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
7d1be0a0 169 EDID_QUIRK('S', 'N', 'Y', 0x2541, EDID_QUIRK_FORCE_12BPC),
bc5b9641 170
bc42aabc 171 /* ViewSonic VA2026w */
7d1be0a0 172 EDID_QUIRK('V', 'S', 'C', 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING),
118bdbd8
AD		 173
174 /* Medion MD 30217 PG */
7d1be0a0 175 EDID_QUIRK('M', 'E', 'D', 0x7b8, EDID_QUIRK_PREFER_LARGE_75),
49d45a31 176
11bcf5f7 177 /* Lenovo G50 */
7d1be0a0 178 EDID_QUIRK('S', 'D', 'C', 18514, EDID_QUIRK_FORCE_6BPC),
11bcf5f7 179
49d45a31 180 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
7d1be0a0 181 EDID_QUIRK('S', 'E', 'C', 0xd033, EDID_QUIRK_FORCE_8BPC),
36fc5797
TV		 182
183 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
7d1be0a0 184 EDID_QUIRK('E', 'T', 'R', 13896, EDID_QUIRK_FORCE_8BPC),
acb1d8ee 185
30d62d44 186 /* Valve Index Headset */
7d1be0a0
DA		 187 EDID_QUIRK('V', 'L', 'V', 0x91a8, EDID_QUIRK_NON_DESKTOP),
188 EDID_QUIRK('V', 'L', 'V', 0x91b0, EDID_QUIRK_NON_DESKTOP),
189 EDID_QUIRK('V', 'L', 'V', 0x91b1, EDID_QUIRK_NON_DESKTOP),
190 EDID_QUIRK('V', 'L', 'V', 0x91b2, EDID_QUIRK_NON_DESKTOP),
191 EDID_QUIRK('V', 'L', 'V', 0x91b3, EDID_QUIRK_NON_DESKTOP),
192 EDID_QUIRK('V', 'L', 'V', 0x91b4, EDID_QUIRK_NON_DESKTOP),
193 EDID_QUIRK('V', 'L', 'V', 0x91b5, EDID_QUIRK_NON_DESKTOP),
194 EDID_QUIRK('V', 'L', 'V', 0x91b6, EDID_QUIRK_NON_DESKTOP),
195 EDID_QUIRK('V', 'L', 'V', 0x91b7, EDID_QUIRK_NON_DESKTOP),
196 EDID_QUIRK('V', 'L', 'V', 0x91b8, EDID_QUIRK_NON_DESKTOP),
197 EDID_QUIRK('V', 'L', 'V', 0x91b9, EDID_QUIRK_NON_DESKTOP),
198 EDID_QUIRK('V', 'L', 'V', 0x91ba, EDID_QUIRK_NON_DESKTOP),
199 EDID_QUIRK('V', 'L', 'V', 0x91bb, EDID_QUIRK_NON_DESKTOP),
200 EDID_QUIRK('V', 'L', 'V', 0x91bc, EDID_QUIRK_NON_DESKTOP),
201 EDID_QUIRK('V', 'L', 'V', 0x91bd, EDID_QUIRK_NON_DESKTOP),
202 EDID_QUIRK('V', 'L', 'V', 0x91be, EDID_QUIRK_NON_DESKTOP),
203 EDID_QUIRK('V', 'L', 'V', 0x91bf, EDID_QUIRK_NON_DESKTOP),
30d62d44 204
6931317c 205 /* HTC Vive and Vive Pro VR Headsets */
7d1be0a0
DA		 206 EDID_QUIRK('H', 'V', 'R', 0xaa01, EDID_QUIRK_NON_DESKTOP),
207 EDID_QUIRK('H', 'V', 'R', 0xaa02, EDID_QUIRK_NON_DESKTOP),
b3b12ea3 208
5a3f6108 209 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */
7d1be0a0
DA		 210 EDID_QUIRK('O', 'V', 'R', 0x0001, EDID_QUIRK_NON_DESKTOP),
211 EDID_QUIRK('O', 'V', 'R', 0x0003, EDID_QUIRK_NON_DESKTOP),
212 EDID_QUIRK('O', 'V', 'R', 0x0004, EDID_QUIRK_NON_DESKTOP),
213 EDID_QUIRK('O', 'V', 'R', 0x0012, EDID_QUIRK_NON_DESKTOP),
90eda8fc
PZ		 214
215 /* Windows Mixed Reality Headsets */
7d1be0a0 216 EDID_QUIRK('A', 'C', 'R', 0x7fce, EDID_QUIRK_NON_DESKTOP),
7d1be0a0 217 EDID_QUIRK('L', 'E', 'N', 0x0408, EDID_QUIRK_NON_DESKTOP),
7d1be0a0
DA		 218 EDID_QUIRK('F', 'U', 'J', 0x1970, EDID_QUIRK_NON_DESKTOP),
219 EDID_QUIRK('D', 'E', 'L', 0x7fce, EDID_QUIRK_NON_DESKTOP),
220 EDID_QUIRK('S', 'E', 'C', 0x144a, EDID_QUIRK_NON_DESKTOP),
221 EDID_QUIRK('A', 'U', 'S', 0xc102, EDID_QUIRK_NON_DESKTOP),
ccffc9eb
PZ		 222
223 /* Sony PlayStation VR Headset */
7d1be0a0 224 EDID_QUIRK('S', 'N', 'Y', 0x0704, EDID_QUIRK_NON_DESKTOP),
29054230
RP		 225
226 /* Sensics VR Headsets */
7d1be0a0 227 EDID_QUIRK('S', 'E', 'N', 0x1019, EDID_QUIRK_NON_DESKTOP),
29054230
RP		 228
229 /* OSVR HDK and HDK2 VR Headsets */
7d1be0a0 230 EDID_QUIRK('S', 'V', 'R', 0x1019, EDID_QUIRK_NON_DESKTOP),
f453ba04
DA		 231};
232
a6b21831
TR		 233/*
234 * Autogenerated from the DMT spec.
235 * This table is copied from xfree86/modes/xf86EdidModes.c.
236 */
237static const struct drm_display_mode drm_dmt_modes[] = {
24b856b1 238 /* 0x01 - 640x350@85Hz */
a6b21831
TR		 239 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
240 736, 832, 0, 350, 382, 385, 445, 0,
241 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 242 /* 0x02 - 640x400@85Hz */
a6b21831
TR		 243 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
244 736, 832, 0, 400, 401, 404, 445, 0,
245 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 246 /* 0x03 - 720x400@85Hz */
a6b21831
TR		 247 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
248 828, 936, 0, 400, 401, 404, 446, 0,
249 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 250 /* 0x04 - 640x480@60Hz */
a6b21831 251 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
fcf22d05 252 752, 800, 0, 480, 490, 492, 525, 0,
a6b21831 253 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 254 /* 0x05 - 640x480@72Hz */
a6b21831
TR		 255 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
256 704, 832, 0, 480, 489, 492, 520, 0,
257 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 258 /* 0x06 - 640x480@75Hz */
a6b21831
TR		 259 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
260 720, 840, 0, 480, 481, 484, 500, 0,
261 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 262 /* 0x07 - 640x480@85Hz */
a6b21831
TR		 263 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
264 752, 832, 0, 480, 481, 484, 509, 0,
265 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 266 /* 0x08 - 800x600@56Hz */
a6b21831
TR		 267 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
268 896, 1024, 0, 600, 601, 603, 625, 0,
269 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 270 /* 0x09 - 800x600@60Hz */
a6b21831
TR		 271 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
272 968, 1056, 0, 600, 601, 605, 628, 0,
273 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 274 /* 0x0a - 800x600@72Hz */
a6b21831
TR		 275 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
276 976, 1040, 0, 600, 637, 643, 666, 0,
277 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 278 /* 0x0b - 800x600@75Hz */
a6b21831
TR		 279 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
280 896, 1056, 0, 600, 601, 604, 625, 0,
281 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 282 /* 0x0c - 800x600@85Hz */
a6b21831
TR		 283 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
284 896, 1048, 0, 600, 601, 604, 631, 0,
285 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 286 /* 0x0d - 800x600@120Hz RB */
a6b21831
TR		 287 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
288 880, 960, 0, 600, 603, 607, 636, 0,
289 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 290 /* 0x0e - 848x480@60Hz */
a6b21831
TR		 291 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
292 976, 1088, 0, 480, 486, 494, 517, 0,
293 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 294 /* 0x0f - 1024x768@43Hz, interlace */
a6b21831 295 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
735b100f 296 1208, 1264, 0, 768, 768, 776, 817, 0,
a6b21831 297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
fcf22d05 298 DRM_MODE_FLAG_INTERLACE) },
24b856b1 299 /* 0x10 - 1024x768@60Hz */
a6b21831
TR		 300 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
301 1184, 1344, 0, 768, 771, 777, 806, 0,
302 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 303 /* 0x11 - 1024x768@70Hz */
a6b21831
TR		 304 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
305 1184, 1328, 0, 768, 771, 777, 806, 0,
306 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 307 /* 0x12 - 1024x768@75Hz */
a6b21831
TR		 308 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
309 1136, 1312, 0, 768, 769, 772, 800, 0,
310 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 311 /* 0x13 - 1024x768@85Hz */
a6b21831
TR		 312 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
313 1168, 1376, 0, 768, 769, 772, 808, 0,
314 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 315 /* 0x14 - 1024x768@120Hz RB */
a6b21831
TR		 316 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
317 1104, 1184, 0, 768, 771, 775, 813, 0,
318 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 319 /* 0x15 - 1152x864@75Hz */
a6b21831
TR		 320 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
321 1344, 1600, 0, 864, 865, 868, 900, 0,
322 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
bfcd74d2
VS		 323 /* 0x55 - 1280x720@60Hz */
324 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
325 1430, 1650, 0, 720, 725, 730, 750, 0,
326 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 327 /* 0x16 - 1280x768@60Hz RB */
a6b21831
TR		 328 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
329 1360, 1440, 0, 768, 771, 778, 790, 0,
330 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 331 /* 0x17 - 1280x768@60Hz */
a6b21831
TR		 332 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
333 1472, 1664, 0, 768, 771, 778, 798, 0,
334 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 335 /* 0x18 - 1280x768@75Hz */
a6b21831
TR		 336 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
337 1488, 1696, 0, 768, 771, 778, 805, 0,
fcf22d05 338 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 339 /* 0x19 - 1280x768@85Hz */
a6b21831
TR		 340 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
341 1496, 1712, 0, 768, 771, 778, 809, 0,
342 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 343 /* 0x1a - 1280x768@120Hz RB */
a6b21831
TR		 344 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
345 1360, 1440, 0, 768, 771, 778, 813, 0,
346 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 347 /* 0x1b - 1280x800@60Hz RB */
a6b21831
TR		 348 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
349 1360, 1440, 0, 800, 803, 809, 823, 0,
350 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 351 /* 0x1c - 1280x800@60Hz */
a6b21831
TR		 352 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
353 1480, 1680, 0, 800, 803, 809, 831, 0,
fcf22d05 354 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 355 /* 0x1d - 1280x800@75Hz */
a6b21831
TR		 356 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
357 1488, 1696, 0, 800, 803, 809, 838, 0,
358 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 359 /* 0x1e - 1280x800@85Hz */
a6b21831
TR		 360 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
361 1496, 1712, 0, 800, 803, 809, 843, 0,
362 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 363 /* 0x1f - 1280x800@120Hz RB */
a6b21831
TR		 364 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
365 1360, 1440, 0, 800, 803, 809, 847, 0,
366 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 367 /* 0x20 - 1280x960@60Hz */
a6b21831
TR		 368 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
369 1488, 1800, 0, 960, 961, 964, 1000, 0,
370 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 371 /* 0x21 - 1280x960@85Hz */
a6b21831
TR		 372 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
373 1504, 1728, 0, 960, 961, 964, 1011, 0,
374 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 375 /* 0x22 - 1280x960@120Hz RB */
a6b21831
TR		 376 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
377 1360, 1440, 0, 960, 963, 967, 1017, 0,
378 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 379 /* 0x23 - 1280x1024@60Hz */
a6b21831
TR		 380 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
381 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
382 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 383 /* 0x24 - 1280x1024@75Hz */
a6b21831
TR		 384 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
385 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
386 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 387 /* 0x25 - 1280x1024@85Hz */
a6b21831
TR		 388 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
389 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
390 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 391 /* 0x26 - 1280x1024@120Hz RB */
a6b21831
TR		 392 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
393 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
394 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 395 /* 0x27 - 1360x768@60Hz */
a6b21831
TR		 396 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
397 1536, 1792, 0, 768, 771, 777, 795, 0,
398 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 399 /* 0x28 - 1360x768@120Hz RB */
a6b21831
TR		 400 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
401 1440, 1520, 0, 768, 771, 776, 813, 0,
402 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 403 /* 0x51 - 1366x768@60Hz */
404 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
405 1579, 1792, 0, 768, 771, 774, 798, 0,
406 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
407 /* 0x56 - 1366x768@60Hz */
408 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
409 1436, 1500, 0, 768, 769, 772, 800, 0,
410 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 411 /* 0x29 - 1400x1050@60Hz RB */
a6b21831
TR		 412 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
413 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
414 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 415 /* 0x2a - 1400x1050@60Hz */
a6b21831
TR		 416 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
417 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
418 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 419 /* 0x2b - 1400x1050@75Hz */
a6b21831
TR		 420 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
421 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
422 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 423 /* 0x2c - 1400x1050@85Hz */
a6b21831
TR		 424 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
425 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
426 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 427 /* 0x2d - 1400x1050@120Hz RB */
a6b21831
TR		 428 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
429 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
430 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 431 /* 0x2e - 1440x900@60Hz RB */
a6b21831
TR		 432 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
433 1520, 1600, 0, 900, 903, 909, 926, 0,
434 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 435 /* 0x2f - 1440x900@60Hz */
a6b21831
TR		 436 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
437 1672, 1904, 0, 900, 903, 909, 934, 0,
438 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 439 /* 0x30 - 1440x900@75Hz */
a6b21831
TR		 440 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
441 1688, 1936, 0, 900, 903, 909, 942, 0,
442 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 443 /* 0x31 - 1440x900@85Hz */
a6b21831
TR		 444 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
445 1696, 1952, 0, 900, 903, 909, 948, 0,
446 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 447 /* 0x32 - 1440x900@120Hz RB */
a6b21831
TR		 448 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
449 1520, 1600, 0, 900, 903, 909, 953, 0,
450 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 451 /* 0x53 - 1600x900@60Hz */
452 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
453 1704, 1800, 0, 900, 901, 904, 1000, 0,
454 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 455 /* 0x33 - 1600x1200@60Hz */
a6b21831
TR		 456 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
457 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
458 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 459 /* 0x34 - 1600x1200@65Hz */
a6b21831
TR		 460 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
461 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
462 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 463 /* 0x35 - 1600x1200@70Hz */
a6b21831
TR		 464 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
465 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
466 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 467 /* 0x36 - 1600x1200@75Hz */
a6b21831
TR		 468 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
469 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
470 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 471 /* 0x37 - 1600x1200@85Hz */
a6b21831
TR		 472 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
473 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
474 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 475 /* 0x38 - 1600x1200@120Hz RB */
a6b21831
TR		 476 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
477 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
478 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 479 /* 0x39 - 1680x1050@60Hz RB */
a6b21831
TR		 480 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
481 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
482 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 483 /* 0x3a - 1680x1050@60Hz */
a6b21831
TR		 484 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
485 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
486 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 487 /* 0x3b - 1680x1050@75Hz */
a6b21831
TR		 488 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
489 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
490 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 491 /* 0x3c - 1680x1050@85Hz */
a6b21831
TR		 492 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
493 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
494 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 495 /* 0x3d - 1680x1050@120Hz RB */
a6b21831
TR		 496 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
497 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
498 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 499 /* 0x3e - 1792x1344@60Hz */
a6b21831
TR		 500 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
501 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
502 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 503 /* 0x3f - 1792x1344@75Hz */
a6b21831
TR		 504 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
505 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
506 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 507 /* 0x40 - 1792x1344@120Hz RB */
a6b21831
TR		 508 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
509 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
510 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 511 /* 0x41 - 1856x1392@60Hz */
a6b21831
TR		 512 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
513 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
514 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 515 /* 0x42 - 1856x1392@75Hz */
a6b21831 516 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
fcf22d05 517 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
a6b21831 518 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 519 /* 0x43 - 1856x1392@120Hz RB */
a6b21831
TR		 520 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
521 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
522 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 523 /* 0x52 - 1920x1080@60Hz */
524 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
525 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
526 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 527 /* 0x44 - 1920x1200@60Hz RB */
a6b21831
TR		 528 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
529 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
530 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 531 /* 0x45 - 1920x1200@60Hz */
a6b21831
TR		 532 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
533 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
534 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 535 /* 0x46 - 1920x1200@75Hz */
a6b21831
TR		 536 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
537 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
538 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 539 /* 0x47 - 1920x1200@85Hz */
a6b21831
TR		 540 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
541 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
542 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 543 /* 0x48 - 1920x1200@120Hz RB */
a6b21831
TR		 544 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
545 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
546 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 547 /* 0x49 - 1920x1440@60Hz */
a6b21831
TR		 548 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
549 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
550 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 551 /* 0x4a - 1920x1440@75Hz */
a6b21831
TR		 552 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
553 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
554 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 555 /* 0x4b - 1920x1440@120Hz RB */
a6b21831
TR		 556 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
557 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
558 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 559 /* 0x54 - 2048x1152@60Hz */
560 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
561 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
562 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 563 /* 0x4c - 2560x1600@60Hz RB */
a6b21831
TR		 564 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
565 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
566 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 567 /* 0x4d - 2560x1600@60Hz */
a6b21831
TR		 568 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
569 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
570 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 571 /* 0x4e - 2560x1600@75Hz */
a6b21831
TR		 572 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
573 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
574 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 575 /* 0x4f - 2560x1600@85Hz */
a6b21831
TR		 576 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
577 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
578 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 579 /* 0x50 - 2560x1600@120Hz RB */
a6b21831
TR		 580 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
581 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
582 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 583 /* 0x57 - 4096x2160@60Hz RB */
584 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
585 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
586 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
587 /* 0x58 - 4096x2160@59.94Hz RB */
588 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
589 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
590 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
a6b21831
TR		 591};
592
e7bfa5c4
VS		 593/*
594 * These more or less come from the DMT spec. The 720x400 modes are
595 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
596 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
597 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
598 * mode.
599 *
600 * The DMT modes have been fact-checked; the rest are mild guesses.
601 */
a6b21831
TR		 602static const struct drm_display_mode edid_est_modes[] = {
603 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
604 968, 1056, 0, 600, 601, 605, 628, 0,
605 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
606 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
607 896, 1024, 0, 600, 601, 603, 625, 0,
608 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
609 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
610 720, 840, 0, 480, 481, 484, 500, 0,
611 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
612 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
87707cfd 613 704, 832, 0, 480, 489, 492, 520, 0,
a6b21831
TR		 614 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
615 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
616 768, 864, 0, 480, 483, 486, 525, 0,
617 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
87707cfd 618 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
a6b21831
TR		 619 752, 800, 0, 480, 490, 492, 525, 0,
620 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
621 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
622 846, 900, 0, 400, 421, 423, 449, 0,
623 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
624 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
625 846, 900, 0, 400, 412, 414, 449, 0,
626 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
627 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
628 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
629 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
87707cfd 630 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
a6b21831
TR		 631 1136, 1312, 0, 768, 769, 772, 800, 0,
632 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
633 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
634 1184, 1328, 0, 768, 771, 777, 806, 0,
635 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
636 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
637 1184, 1344, 0, 768, 771, 777, 806, 0,
638 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
639 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
640 1208, 1264, 0, 768, 768, 776, 817, 0,
641 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
642 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
643 928, 1152, 0, 624, 625, 628, 667, 0,
644 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
645 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
646 896, 1056, 0, 600, 601, 604, 625, 0,
647 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
648 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
649 976, 1040, 0, 600, 637, 643, 666, 0,
650 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
651 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
652 1344, 1600, 0, 864, 865, 868, 900, 0,
653 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
654};
655
656struct minimode {
657 short w;
658 short h;
659 short r;
660 short rb;
661};
662
663static const struct minimode est3_modes[] = {
664 /* byte 6 */
665 { 640, 350, 85, 0 },
666 { 640, 400, 85, 0 },
667 { 720, 400, 85, 0 },
668 { 640, 480, 85, 0 },
669 { 848, 480, 60, 0 },
670 { 800, 600, 85, 0 },
671 { 1024, 768, 85, 0 },
672 { 1152, 864, 75, 0 },
673 /* byte 7 */
674 { 1280, 768, 60, 1 },
675 { 1280, 768, 60, 0 },
676 { 1280, 768, 75, 0 },
677 { 1280, 768, 85, 0 },
678 { 1280, 960, 60, 0 },
679 { 1280, 960, 85, 0 },
680 { 1280, 1024, 60, 0 },
681 { 1280, 1024, 85, 0 },
682 /* byte 8 */
683 { 1360, 768, 60, 0 },
684 { 1440, 900, 60, 1 },
685 { 1440, 900, 60, 0 },
686 { 1440, 900, 75, 0 },
687 { 1440, 900, 85, 0 },
688 { 1400, 1050, 60, 1 },
689 { 1400, 1050, 60, 0 },
690 { 1400, 1050, 75, 0 },
691 /* byte 9 */
692 { 1400, 1050, 85, 0 },
693 { 1680, 1050, 60, 1 },
694 { 1680, 1050, 60, 0 },
695 { 1680, 1050, 75, 0 },
696 { 1680, 1050, 85, 0 },
697 { 1600, 1200, 60, 0 },
698 { 1600, 1200, 65, 0 },
699 { 1600, 1200, 70, 0 },
700 /* byte 10 */
701 { 1600, 1200, 75, 0 },
702 { 1600, 1200, 85, 0 },
703 { 1792, 1344, 60, 0 },
c068b32a 704 { 1792, 1344, 75, 0 },
a6b21831
TR		 705 { 1856, 1392, 60, 0 },
706 { 1856, 1392, 75, 0 },
707 { 1920, 1200, 60, 1 },
708 { 1920, 1200, 60, 0 },
709 /* byte 11 */
710 { 1920, 1200, 75, 0 },
711 { 1920, 1200, 85, 0 },
712 { 1920, 1440, 60, 0 },
713 { 1920, 1440, 75, 0 },
714};
715
716static const struct minimode extra_modes[] = {
717 { 1024, 576, 60, 0 },
718 { 1366, 768, 60, 0 },
719 { 1600, 900, 60, 0 },
720 { 1680, 945, 60, 0 },
721 { 1920, 1080, 60, 0 },
722 { 2048, 1152, 60, 0 },
723 { 2048, 1536, 60, 0 },
724};
725
726/*
7befe621 727 * From CEA/CTA-861 spec.
d9278b4c 728 *
7befe621 729 * Do not access directly, instead always use cea_mode_for_vic().
a6b21831 730 */
8c1b2bd9 731static const struct drm_display_mode edid_cea_modes_1[] = {
78691960 732 /* 1 - 640x480@60Hz 4:3 */
a6b21831
TR		 733 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
734 752, 800, 0, 480, 490, 492, 525, 0,
ee7925bb 735 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 736 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 737 /* 2 - 720x480@60Hz 4:3 */
a6b21831
TR		 738 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
739 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 740 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 741 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 742 /* 3 - 720x480@60Hz 16:9 */
a6b21831
TR		 743 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
744 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 745 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 746 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 747 /* 4 - 1280x720@60Hz 16:9 */
a6b21831
TR		 748 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
749 1430, 1650, 0, 720, 725, 730, 750, 0,
ee7925bb 750 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 751 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 752 /* 5 - 1920x1080i@60Hz 16:9 */
a6b21831
TR		 753 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
754 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
755 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 756 DRM_MODE_FLAG_INTERLACE),
0425662f 757 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 758 /* 6 - 720(1440)x480i@60Hz 4:3 */
fb01d280
CT		 759 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
760 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 761 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 762 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 763 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 764 /* 7 - 720(1440)x480i@60Hz 16:9 */
fb01d280
CT		 765 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
766 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 767 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 768 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 769 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 770 /* 8 - 720(1440)x240@60Hz 4:3 */
fb01d280
CT		 771 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
772 801, 858, 0, 240, 244, 247, 262, 0,
a6b21831 773 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 774 DRM_MODE_FLAG_DBLCLK),
0425662f 775 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 776 /* 9 - 720(1440)x240@60Hz 16:9 */
fb01d280
CT		 777 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
778 801, 858, 0, 240, 244, 247, 262, 0,
a6b21831 779 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 780 DRM_MODE_FLAG_DBLCLK),
0425662f 781 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 782 /* 10 - 2880x480i@60Hz 4:3 */
a6b21831
TR		 783 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
784 3204, 3432, 0, 480, 488, 494, 525, 0,
785 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 786 DRM_MODE_FLAG_INTERLACE),
0425662f 787 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 788 /* 11 - 2880x480i@60Hz 16:9 */
a6b21831
TR		 789 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
790 3204, 3432, 0, 480, 488, 494, 525, 0,
791 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 792 DRM_MODE_FLAG_INTERLACE),
0425662f 793 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 794 /* 12 - 2880x240@60Hz 4:3 */
a6b21831
TR		 795 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
796 3204, 3432, 0, 240, 244, 247, 262, 0,
ee7925bb 797 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 798 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 799 /* 13 - 2880x240@60Hz 16:9 */
a6b21831
TR		 800 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
801 3204, 3432, 0, 240, 244, 247, 262, 0,
ee7925bb 802 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 803 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 804 /* 14 - 1440x480@60Hz 4:3 */
a6b21831
TR		 805 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
806 1596, 1716, 0, 480, 489, 495, 525, 0,
ee7925bb 807 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 808 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 809 /* 15 - 1440x480@60Hz 16:9 */
a6b21831
TR		 810 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
811 1596, 1716, 0, 480, 489, 495, 525, 0,
ee7925bb 812 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 813 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 814 /* 16 - 1920x1080@60Hz 16:9 */
a6b21831
TR		 815 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
816 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 817 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 818 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 819 /* 17 - 720x576@50Hz 4:3 */
a6b21831
TR		 820 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
821 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 822 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 823 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 824 /* 18 - 720x576@50Hz 16:9 */
a6b21831
TR		 825 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
826 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 827 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 828 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 829 /* 19 - 1280x720@50Hz 16:9 */
a6b21831
TR		 830 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
831 1760, 1980, 0, 720, 725, 730, 750, 0,
ee7925bb 832 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 833 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 834 /* 20 - 1920x1080i@50Hz 16:9 */
a6b21831
TR		 835 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
836 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
837 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 838 DRM_MODE_FLAG_INTERLACE),
0425662f 839 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 840 /* 21 - 720(1440)x576i@50Hz 4:3 */
fb01d280
CT		 841 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
842 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 843 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 844 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 845 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 846 /* 22 - 720(1440)x576i@50Hz 16:9 */
fb01d280
CT		 847 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
848 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 849 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 850 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 851 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 852 /* 23 - 720(1440)x288@50Hz 4:3 */
fb01d280
CT		 853 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
854 795, 864, 0, 288, 290, 293, 312, 0,
a6b21831 855 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 856 DRM_MODE_FLAG_DBLCLK),
0425662f 857 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 858 /* 24 - 720(1440)x288@50Hz 16:9 */
fb01d280
CT		 859 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
860 795, 864, 0, 288, 290, 293, 312, 0,
a6b21831 861 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 862 DRM_MODE_FLAG_DBLCLK),
0425662f 863 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 864 /* 25 - 2880x576i@50Hz 4:3 */
a6b21831
TR		 865 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
866 3180, 3456, 0, 576, 580, 586, 625, 0,
867 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 868 DRM_MODE_FLAG_INTERLACE),
0425662f 869 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 870 /* 26 - 2880x576i@50Hz 16:9 */
a6b21831
TR		 871 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
872 3180, 3456, 0, 576, 580, 586, 625, 0,
873 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 874 DRM_MODE_FLAG_INTERLACE),
0425662f 875 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 876 /* 27 - 2880x288@50Hz 4:3 */
a6b21831
TR		 877 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
878 3180, 3456, 0, 288, 290, 293, 312, 0,
ee7925bb 879 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 880 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 881 /* 28 - 2880x288@50Hz 16:9 */
a6b21831
TR		 882 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
883 3180, 3456, 0, 288, 290, 293, 312, 0,
ee7925bb 884 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 885 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 886 /* 29 - 1440x576@50Hz 4:3 */
a6b21831
TR		 887 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
888 1592, 1728, 0, 576, 581, 586, 625, 0,
ee7925bb 889 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 890 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 891 /* 30 - 1440x576@50Hz 16:9 */
a6b21831
TR		 892 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
893 1592, 1728, 0, 576, 581, 586, 625, 0,
ee7925bb 894 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 895 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 896 /* 31 - 1920x1080@50Hz 16:9 */
a6b21831
TR		 897 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
898 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 899 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 900 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 901 /* 32 - 1920x1080@24Hz 16:9 */
a6b21831
TR		 902 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
903 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 904 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 905 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 906 /* 33 - 1920x1080@25Hz 16:9 */
a6b21831
TR		 907 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
908 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 909 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 910 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 911 /* 34 - 1920x1080@30Hz 16:9 */
a6b21831
TR		 912 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
913 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 914 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 915 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 916 /* 35 - 2880x480@60Hz 4:3 */
a6b21831
TR		 917 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
918 3192, 3432, 0, 480, 489, 495, 525, 0,
ee7925bb 919 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 920 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 921 /* 36 - 2880x480@60Hz 16:9 */
a6b21831
TR		 922 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
923 3192, 3432, 0, 480, 489, 495, 525, 0,
ee7925bb 924 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 925 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 926 /* 37 - 2880x576@50Hz 4:3 */
a6b21831
TR		 927 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
928 3184, 3456, 0, 576, 581, 586, 625, 0,
ee7925bb 929 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 930 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 931 /* 38 - 2880x576@50Hz 16:9 */
a6b21831
TR		 932 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
933 3184, 3456, 0, 576, 581, 586, 625, 0,
ee7925bb 934 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 935 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 936 /* 39 - 1920x1080i@50Hz 16:9 */
a6b21831
TR		 937 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
938 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
939 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 940 DRM_MODE_FLAG_INTERLACE),
0425662f 941 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 942 /* 40 - 1920x1080i@100Hz 16:9 */
a6b21831
TR		 943 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
944 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
945 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 946 DRM_MODE_FLAG_INTERLACE),
0425662f 947 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 948 /* 41 - 1280x720@100Hz 16:9 */
a6b21831
TR		 949 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
950 1760, 1980, 0, 720, 725, 730, 750, 0,
ee7925bb 951 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 952 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 953 /* 42 - 720x576@100Hz 4:3 */
a6b21831
TR		 954 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
955 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 956 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 957 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 958 /* 43 - 720x576@100Hz 16:9 */
a6b21831
TR		 959 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
960 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 961 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 962 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 963 /* 44 - 720(1440)x576i@100Hz 4:3 */
fb01d280
CT		 964 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
965 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 966 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 967 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 968 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 969 /* 45 - 720(1440)x576i@100Hz 16:9 */
fb01d280
CT		 970 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
971 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 972 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 973 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 974 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 975 /* 46 - 1920x1080i@120Hz 16:9 */
a6b21831
TR		 976 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
977 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
978 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 979 DRM_MODE_FLAG_INTERLACE),
0425662f 980 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 981 /* 47 - 1280x720@120Hz 16:9 */
a6b21831
TR		 982 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
983 1430, 1650, 0, 720, 725, 730, 750, 0,
ee7925bb 984 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 985 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 986 /* 48 - 720x480@120Hz 4:3 */
a6b21831
TR		 987 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
988 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 989 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 990 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 991 /* 49 - 720x480@120Hz 16:9 */
a6b21831
TR		 992 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
993 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 994 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 995 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 996 /* 50 - 720(1440)x480i@120Hz 4:3 */
fb01d280
CT		 997 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
998 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 999 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1000 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1001 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1002 /* 51 - 720(1440)x480i@120Hz 16:9 */
fb01d280
CT		 1003 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
1004 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 1005 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1006 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1007 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1008 /* 52 - 720x576@200Hz 4:3 */
a6b21831
TR		 1009 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1010 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 1011 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 1012 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1013 /* 53 - 720x576@200Hz 16:9 */
a6b21831
TR		 1014 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1015 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 1016 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 1017 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1018 /* 54 - 720(1440)x576i@200Hz 4:3 */
fb01d280
CT		 1019 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1020 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 1021 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1022 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1023 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1024 /* 55 - 720(1440)x576i@200Hz 16:9 */
fb01d280
CT		 1025 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1026 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 1027 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1028 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1029 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1030 /* 56 - 720x480@240Hz 4:3 */
a6b21831
TR		 1031 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1032 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 1033 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 1034 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1035 /* 57 - 720x480@240Hz 16:9 */
a6b21831
TR		 1036 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1037 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 1038 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 1039 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1040 /* 58 - 720(1440)x480i@240Hz 4:3 */
fb01d280
CT		 1041 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1042 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 1043 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1044 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1045 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1046 /* 59 - 720(1440)x480i@240Hz 16:9 */
fb01d280
CT		 1047 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1048 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 1049 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1050 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1051 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1052 /* 60 - 1280x720@24Hz 16:9 */
a6b21831
TR		 1053 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1054 3080, 3300, 0, 720, 725, 730, 750, 0,
ee7925bb 1055 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1056 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1057 /* 61 - 1280x720@25Hz 16:9 */
a6b21831
TR		 1058 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1059 3740, 3960, 0, 720, 725, 730, 750, 0,
ee7925bb 1060 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1061 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1062 /* 62 - 1280x720@30Hz 16:9 */
a6b21831
TR		 1063 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1064 3080, 3300, 0, 720, 725, 730, 750, 0,
ee7925bb 1065 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1066 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1067 /* 63 - 1920x1080@120Hz 16:9 */
a6b21831
TR		 1068 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1069 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 1070 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1071 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1072 /* 64 - 1920x1080@100Hz 16:9 */
a6b21831 1073 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
8f0e4907 1074 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 1075 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1076 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1077 /* 65 - 1280x720@24Hz 64:27 */
8ec6e075
SS		 1078 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1079 3080, 3300, 0, 720, 725, 730, 750, 0,
1080 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1081 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1082 /* 66 - 1280x720@25Hz 64:27 */
8ec6e075
SS		 1083 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1084 3740, 3960, 0, 720, 725, 730, 750, 0,
1085 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1086 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1087 /* 67 - 1280x720@30Hz 64:27 */
8ec6e075
SS		 1088 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1089 3080, 3300, 0, 720, 725, 730, 750, 0,
1090 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1091 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1092 /* 68 - 1280x720@50Hz 64:27 */
8ec6e075
SS		 1093 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1094 1760, 1980, 0, 720, 725, 730, 750, 0,
1095 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1096 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1097 /* 69 - 1280x720@60Hz 64:27 */
8ec6e075
SS		 1098 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1099 1430, 1650, 0, 720, 725, 730, 750, 0,
1100 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1101 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1102 /* 70 - 1280x720@100Hz 64:27 */
8ec6e075
SS		 1103 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1104 1760, 1980, 0, 720, 725, 730, 750, 0,
1105 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1106 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1107 /* 71 - 1280x720@120Hz 64:27 */
8ec6e075
SS		 1108 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1109 1430, 1650, 0, 720, 725, 730, 750, 0,
1110 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1111 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1112 /* 72 - 1920x1080@24Hz 64:27 */
8ec6e075
SS		 1113 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1114 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1115 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1116 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1117 /* 73 - 1920x1080@25Hz 64:27 */
8ec6e075
SS		 1118 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1119 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1120 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1121 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1122 /* 74 - 1920x1080@30Hz 64:27 */
8ec6e075
SS		 1123 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1124 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1125 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1126 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1127 /* 75 - 1920x1080@50Hz 64:27 */
8ec6e075
SS		 1128 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1129 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1130 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1131 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1132 /* 76 - 1920x1080@60Hz 64:27 */
8ec6e075
SS		 1133 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1134 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1135 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1136 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1137 /* 77 - 1920x1080@100Hz 64:27 */
8ec6e075
SS		 1138 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1139 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1140 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1141 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1142 /* 78 - 1920x1080@120Hz 64:27 */
8ec6e075
SS		 1143 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1144 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1145 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1146 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1147 /* 79 - 1680x720@24Hz 64:27 */
8ec6e075
SS		 1148 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1149 3080, 3300, 0, 720, 725, 730, 750, 0,
1150 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1151 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1152 /* 80 - 1680x720@25Hz 64:27 */
8ec6e075
SS		 1153 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1154 2948, 3168, 0, 720, 725, 730, 750, 0,
1155 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1156 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1157 /* 81 - 1680x720@30Hz 64:27 */
8ec6e075
SS		 1158 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1159 2420, 2640, 0, 720, 725, 730, 750, 0,
1160 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1161 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1162 /* 82 - 1680x720@50Hz 64:27 */
8ec6e075
SS		 1163 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1164 1980, 2200, 0, 720, 725, 730, 750, 0,
1165 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1166 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1167 /* 83 - 1680x720@60Hz 64:27 */
8ec6e075
SS		 1168 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1169 1980, 2200, 0, 720, 725, 730, 750, 0,
1170 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1171 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1172 /* 84 - 1680x720@100Hz 64:27 */
8ec6e075
SS		 1173 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1174 1780, 2000, 0, 720, 725, 730, 825, 0,
1175 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1176 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1177 /* 85 - 1680x720@120Hz 64:27 */
8ec6e075
SS		 1178 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1179 1780, 2000, 0, 720, 725, 730, 825, 0,
1180 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1181 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1182 /* 86 - 2560x1080@24Hz 64:27 */
8ec6e075
SS		 1183 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1184 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1185 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1186 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1187 /* 87 - 2560x1080@25Hz 64:27 */
8ec6e075
SS		 1188 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1189 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1190 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1191 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1192 /* 88 - 2560x1080@30Hz 64:27 */
8ec6e075
SS		 1193 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1194 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1195 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1196 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1197 /* 89 - 2560x1080@50Hz 64:27 */
8ec6e075
SS		 1198 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1199 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1200 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1201 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1202 /* 90 - 2560x1080@60Hz 64:27 */
8ec6e075
SS		 1203 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1204 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1205 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1206 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1207 /* 91 - 2560x1080@100Hz 64:27 */
8ec6e075
SS		 1208 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1209 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1210 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1211 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1212 /* 92 - 2560x1080@120Hz 64:27 */
8ec6e075
SS		 1213 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1214 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1215 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1216 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1217 /* 93 - 3840x2160@24Hz 16:9 */
8ec6e075
SS		 1218 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1219 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1220 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1221 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1222 /* 94 - 3840x2160@25Hz 16:9 */
8ec6e075
SS		 1223 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1224 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1225 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1226 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1227 /* 95 - 3840x2160@30Hz 16:9 */
8ec6e075
SS		 1228 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1229 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1230 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1231 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1232 /* 96 - 3840x2160@50Hz 16:9 */
8ec6e075
SS		 1233 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1234 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1235 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1236 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1237 /* 97 - 3840x2160@60Hz 16:9 */
8ec6e075
SS		 1238 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1239 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1240 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1241 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1242 /* 98 - 4096x2160@24Hz 256:135 */
8ec6e075
SS		 1243 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1244 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1245 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1246 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1247 /* 99 - 4096x2160@25Hz 256:135 */
8ec6e075
SS		 1248 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1249 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1250 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1251 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1252 /* 100 - 4096x2160@30Hz 256:135 */
8ec6e075
SS		 1253 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1254 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1255 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1256 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1257 /* 101 - 4096x2160@50Hz 256:135 */
8ec6e075
SS		 1258 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1259 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1260 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1261 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1262 /* 102 - 4096x2160@60Hz 256:135 */
8ec6e075
SS		 1263 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1264 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1265 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1266 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1267 /* 103 - 3840x2160@24Hz 64:27 */
8ec6e075
SS		 1268 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1269 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1270 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1271 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1272 /* 104 - 3840x2160@25Hz 64:27 */
8ec6e075
SS		 1273 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1274 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1275 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1276 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1277 /* 105 - 3840x2160@30Hz 64:27 */
8ec6e075
SS		 1278 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1279 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1281 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1282 /* 106 - 3840x2160@50Hz 64:27 */
8ec6e075
SS		 1283 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1284 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1285 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1286 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1287 /* 107 - 3840x2160@60Hz 64:27 */
8ec6e075
SS		 1288 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1289 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1290 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1291 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1292 /* 108 - 1280x720@48Hz 16:9 */
1293 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1294 2280, 2500, 0, 720, 725, 730, 750, 0,
1295 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1296 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1297 /* 109 - 1280x720@48Hz 64:27 */
1298 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1299 2280, 2500, 0, 720, 725, 730, 750, 0,
1300 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1301 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1302 /* 110 - 1680x720@48Hz 64:27 */
1303 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490,
1304 2530, 2750, 0, 720, 725, 730, 750, 0,
1305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1306 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1307 /* 111 - 1920x1080@48Hz 16:9 */
1308 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1309 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1310 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1311 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1312 /* 112 - 1920x1080@48Hz 64:27 */
1313 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1314 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1315 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1316 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1317 /* 113 - 2560x1080@48Hz 64:27 */
1318 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558,
1319 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1320 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1321 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1322 /* 114 - 3840x2160@48Hz 16:9 */
1323 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1324 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1325 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1326 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1327 /* 115 - 4096x2160@48Hz 256:135 */
1328 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116,
1329 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1330 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1331 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
978f6b06
VS		 1332 /* 116 - 3840x2160@48Hz 64:27 */
1333 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1334 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1335 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1336 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1337 /* 117 - 3840x2160@100Hz 16:9 */
1338 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1339 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1340 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1341 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1342 /* 118 - 3840x2160@120Hz 16:9 */
1343 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1344 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1345 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1346 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1347 /* 119 - 3840x2160@100Hz 64:27 */
1348 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1349 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1350 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1351 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1352 /* 120 - 3840x2160@120Hz 64:27 */
1353 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1354 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1355 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1356 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1357 /* 121 - 5120x2160@24Hz 64:27 */
1358 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116,
1359 7204, 7500, 0, 2160, 2168, 2178, 2200, 0,
1360 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1361 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1362 /* 122 - 5120x2160@25Hz 64:27 */
1363 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816,
1364 6904, 7200, 0, 2160, 2168, 2178, 2200, 0,
1365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1366 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1367 /* 123 - 5120x2160@30Hz 64:27 */
1368 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784,
1369 5872, 6000, 0, 2160, 2168, 2178, 2200, 0,
1370 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1371 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1372 /* 124 - 5120x2160@48Hz 64:27 */
1373 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866,
1374 5954, 6250, 0, 2160, 2168, 2178, 2475, 0,
1375 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1376 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1377 /* 125 - 5120x2160@50Hz 64:27 */
1378 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216,
1379 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1380 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1381 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1382 /* 126 - 5120x2160@60Hz 64:27 */
1383 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284,
1384 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1386 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1387 /* 127 - 5120x2160@100Hz 64:27 */
1388 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216,
1389 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1390 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1391 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
a6b21831
TR		 1392};
1393
f7655d42
VS		 1394/*
1395 * From CEA/CTA-861 spec.
1396 *
1397 * Do not access directly, instead always use cea_mode_for_vic().
1398 */
1399static const struct drm_display_mode edid_cea_modes_193[] = {
1400 /* 193 - 5120x2160@120Hz 64:27 */
1401 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284,
1402 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1403 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1404 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1405 /* 194 - 7680x4320@24Hz 16:9 */
1406 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1407 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1408 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1409 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1410 /* 195 - 7680x4320@25Hz 16:9 */
1411 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1412 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1413 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1414 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1415 /* 196 - 7680x4320@30Hz 16:9 */
1416 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1417 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1418 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1419 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1420 /* 197 - 7680x4320@48Hz 16:9 */
1421 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1422 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1423 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1424 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1425 /* 198 - 7680x4320@50Hz 16:9 */
1426 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1427 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1428 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1429 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1430 /* 199 - 7680x4320@60Hz 16:9 */
1431 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1432 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1433 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1434 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1435 /* 200 - 7680x4320@100Hz 16:9 */
1436 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1437 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1438 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1439 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1440 /* 201 - 7680x4320@120Hz 16:9 */
1441 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1442 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1443 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1444 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1445 /* 202 - 7680x4320@24Hz 64:27 */
1446 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1447 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1448 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1449 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1450 /* 203 - 7680x4320@25Hz 64:27 */
1451 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1452 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1454 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1455 /* 204 - 7680x4320@30Hz 64:27 */
1456 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1457 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1458 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1459 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1460 /* 205 - 7680x4320@48Hz 64:27 */
1461 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1462 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1463 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1464 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1465 /* 206 - 7680x4320@50Hz 64:27 */
1466 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1467 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1468 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1469 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1470 /* 207 - 7680x4320@60Hz 64:27 */
1471 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1472 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1473 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1474 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1475 /* 208 - 7680x4320@100Hz 64:27 */
1476 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1477 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1478 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1479 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1480 /* 209 - 7680x4320@120Hz 64:27 */
1481 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1482 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1483 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1484 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1485 /* 210 - 10240x4320@24Hz 64:27 */
1486 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732,
1487 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1488 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1489 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1490 /* 211 - 10240x4320@25Hz 64:27 */
1491 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732,
1492 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1493 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1494 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1495 /* 212 - 10240x4320@30Hz 64:27 */
1496 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528,
1497 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1498 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1499 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1500 /* 213 - 10240x4320@48Hz 64:27 */
1501 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732,
1502 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1503 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1504 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1505 /* 214 - 10240x4320@50Hz 64:27 */
1506 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732,
1507 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1508 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1509 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1510 /* 215 - 10240x4320@60Hz 64:27 */
1511 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528,
1512 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1513 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1514 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1515 /* 216 - 10240x4320@100Hz 64:27 */
1516 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432,
1517 12608, 13200, 0, 4320, 4336, 4356, 4500, 0,
1518 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1519 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1520 /* 217 - 10240x4320@120Hz 64:27 */
1521 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528,
1522 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1523 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1524 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1525 /* 218 - 4096x2160@100Hz 256:135 */
1526 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896,
1527 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1528 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1529 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
f7655d42
VS		 1530 /* 219 - 4096x2160@120Hz 256:135 */
1531 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184,
1532 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1533 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1534 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
f7655d42
VS		 1535};
1536
7ebe1963 1537/*
d9278b4c 1538 * HDMI 1.4 4k modes. Index using the VIC.
7ebe1963
LD		 1539 */
1540static const struct drm_display_mode edid_4k_modes[] = {
d9278b4c
JN		 1541 /* 0 - dummy, VICs start at 1 */
1542 { },
7ebe1963
LD		 1543 /* 1 - 3840x2160@30Hz */
1544 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1545 3840, 4016, 4104, 4400, 0,
1546 2160, 2168, 2178, 2250, 0,
1547 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1548 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
7ebe1963
LD		 1549 /* 2 - 3840x2160@25Hz */
1550 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1551 3840, 4896, 4984, 5280, 0,
1552 2160, 2168, 2178, 2250, 0,
1553 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1554 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
7ebe1963
LD		 1555 /* 3 - 3840x2160@24Hz */
1556 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1557 3840, 5116, 5204, 5500, 0,
1558 2160, 2168, 2178, 2250, 0,
1559 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1560 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
7ebe1963
LD		 1561 /* 4 - 4096x2160@24Hz (SMPTE) */
1562 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1563 4096, 5116, 5204, 5500, 0,
1564 2160, 2168, 2178, 2250, 0,
1565 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1566 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
7ebe1963
LD		 1567};
1568
61e57a8d 1569/*** DDC fetch and block validation ***/
f453ba04 1570
083ae056
AJ		 1571static const u8 edid_header[] = {
1572 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1573};
f453ba04 1574
db6cf833
TR		 1575/**
1576 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1577 * @raw_edid: pointer to raw base EDID block
1578 *
1579 * Sanity check the header of the base EDID block.
1580 *
1581 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
051963d4
TR		 1582 */
1583int drm_edid_header_is_valid(const u8 *raw_edid)
1584{
1585 int i, score = 0;
1586
1587 for (i = 0; i < sizeof(edid_header); i++)
1588 if (raw_edid[i] == edid_header[i])
1589 score++;
1590
1591 return score;
1592}
1593EXPORT_SYMBOL(drm_edid_header_is_valid);
1594
47819ba2
AJ		 1595static int edid_fixup __read_mostly = 6;
1596module_param_named(edid_fixup, edid_fixup, int, 0400);
1597MODULE_PARM_DESC(edid_fixup,
1598 "Minimum number of valid EDID header bytes (0-8, default 6)");
051963d4 1599
c465bbc8
SB		 1600static int drm_edid_block_checksum(const u8 *raw_edid)
1601{
1602 int i;
e11f5bd8
JFZ		 1603 u8 csum = 0, crc = 0;
1604
1605 for (i = 0; i < EDID_LENGTH - 1; i++)
c465bbc8
SB		 1606 csum += raw_edid[i];
1607
e11f5bd8
JFZ		 1608 crc = 0x100 - csum;
1609
1610 return crc;
1611}
1612
1613static bool drm_edid_block_checksum_diff(const u8 *raw_edid, u8 real_checksum)
1614{
1615 if (raw_edid[EDID_LENGTH - 1] != real_checksum)
1616 return true;
1617 else
1618 return false;
c465bbc8
SB		 1619}
1620
d6885d65
SB		 1621static bool drm_edid_is_zero(const u8 *in_edid, int length)
1622{
1623 if (memchr_inv(in_edid, 0, length))
1624 return false;
1625
1626 return true;
1627}
1628
536faa45
SL		 1629/**
1630 * drm_edid_are_equal - compare two edid blobs.
1631 * @edid1: pointer to first blob
1632 * @edid2: pointer to second blob
1633 * This helper can be used during probing to determine if
1634 * edid had changed.
1635 */
1636bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2)
1637{
1638 int edid1_len, edid2_len;
1639 bool edid1_present = edid1 != NULL;
1640 bool edid2_present = edid2 != NULL;
1641
1642 if (edid1_present != edid2_present)
1643 return false;
1644
1645 if (edid1) {
536faa45
SL		 1646 edid1_len = EDID_LENGTH * (1 + edid1->extensions);
1647 edid2_len = EDID_LENGTH * (1 + edid2->extensions);
1648
1649 if (edid1_len != edid2_len)
1650 return false;
1651
1652 if (memcmp(edid1, edid2, edid1_len))
1653 return false;
1654 }
1655
1656 return true;
1657}
1658EXPORT_SYMBOL(drm_edid_are_equal);
1659
db6cf833
TR		 1660/**
1661 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1662 * @raw_edid: pointer to raw EDID block
1663 * @block: type of block to validate (0 for base, extension otherwise)
1664 * @print_bad_edid: if true, dump bad EDID blocks to the console
6ba2bd3d 1665 * @edid_corrupt: if true, the header or checksum is invalid
db6cf833
TR		 1666 *
1667 * Validate a base or extension EDID block and optionally dump bad blocks to
1668 * the console.
1669 *
1670 * Return: True if the block is valid, false otherwise.
f453ba04 1671 */
6ba2bd3d
TP		 1672bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
1673 bool *edid_corrupt)
f453ba04 1674{
c465bbc8 1675 u8 csum;
61e57a8d 1676 struct edid *edid = (struct edid *)raw_edid;
f453ba04 1677
fe2ef780
SWK		 1678 if (WARN_ON(!raw_edid))
1679 return false;
1680
47819ba2
AJ		 1681 if (edid_fixup > 8 || edid_fixup < 0)
1682 edid_fixup = 6;
1683
f89ec8a4 1684 if (block == 0) {
051963d4 1685 int score = drm_edid_header_is_valid(raw_edid);
948de842 1686
6ba2bd3d
TP		 1687 if (score == 8) {
1688 if (edid_corrupt)
ac6f2e29 1689 *edid_corrupt = false;
6ba2bd3d
TP		 1690 } else if (score >= edid_fixup) {
1691 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
1692 * The corrupt flag needs to be set here otherwise, the
1693 * fix-up code here will correct the problem, the
1694 * checksum is correct and the test fails
1695 */
1696 if (edid_corrupt)
ac6f2e29 1697 *edid_corrupt = true;
61e57a8d
AJ		 1698 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1699 memcpy(raw_edid, edid_header, sizeof(edid_header));
1700 } else {
6ba2bd3d 1701 if (edid_corrupt)
ac6f2e29 1702 *edid_corrupt = true;
61e57a8d
AJ		 1703 goto bad;
1704 }
1705 }
f453ba04 1706
c465bbc8 1707 csum = drm_edid_block_checksum(raw_edid);
e11f5bd8 1708 if (drm_edid_block_checksum_diff(raw_edid, csum)) {
6ba2bd3d 1709 if (edid_corrupt)
ac6f2e29 1710 *edid_corrupt = true;
6ba2bd3d 1711
4a638b4e 1712 /* allow CEA to slide through, switches mangle this */
82d75356
TV		 1713 if (raw_edid[0] == CEA_EXT) {
1714 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum);
1715 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n");
1716 } else {
1717 if (print_bad_edid)
813a7878 1718 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum);
82d75356 1719
4a638b4e 1720 goto bad;
82d75356 1721 }
f453ba04
DA		 1722 }
1723
61e57a8d
AJ		 1724 /* per-block-type checks */
1725 switch (raw_edid[0]) {
1726 case 0: /* base */
1727 if (edid->version != 1) {
813a7878 1728 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version);
61e57a8d
AJ		 1729 goto bad;
1730 }
862b89c0 1731
61e57a8d
AJ		 1732 if (edid->revision > 4)
1733 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1734 break;
862b89c0 1735
61e57a8d
AJ		 1736 default:
1737 break;
1738 }
47ee4ccf 1739
fe2ef780 1740 return true;
f453ba04
DA		 1741
1742bad:
fe2ef780 1743 if (print_bad_edid) {
da4c07b7 1744 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
499447db 1745 pr_notice("EDID block is all zeroes\n");
da4c07b7 1746 } else {
499447db 1747 pr_notice("Raw EDID:\n");
813a7878
CW		 1748 print_hex_dump(KERN_NOTICE,
1749 " \t", DUMP_PREFIX_NONE, 16, 1,
1750 raw_edid, EDID_LENGTH, false);
da4c07b7 1751 }
f453ba04 1752 }
fe2ef780 1753 return false;
f453ba04 1754}
da0df92b 1755EXPORT_SYMBOL(drm_edid_block_valid);
61e57a8d
AJ		 1756
1757/**
1758 * drm_edid_is_valid - sanity check EDID data
1759 * @edid: EDID data
1760 *
1761 * Sanity-check an entire EDID record (including extensions)
db6cf833
TR		 1762 *
1763 * Return: True if the EDID data is valid, false otherwise.
61e57a8d
AJ		 1764 */
1765bool drm_edid_is_valid(struct edid *edid)
1766{
1767 int i;
1768 u8 *raw = (u8 *)edid;
1769
1770 if (!edid)
1771 return false;
1772
1773 for (i = 0; i <= edid->extensions; i++)
6ba2bd3d 1774 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
61e57a8d
AJ		 1775 return false;
1776
1777 return true;
1778}
3c537889 1779EXPORT_SYMBOL(drm_edid_is_valid);
f453ba04 1780
61e57a8d
AJ		 1781#define DDC_SEGMENT_ADDR 0x30
1782/**
db6cf833 1783 * drm_do_probe_ddc_edid() - get EDID information via I2C
7c58e87e 1784 * @data: I2C device adapter
fc66811c
DV		 1785 * @buf: EDID data buffer to be filled
1786 * @block: 128 byte EDID block to start fetching from
1787 * @len: EDID data buffer length to fetch
1788 *
db6cf833 1789 * Try to fetch EDID information by calling I2C driver functions.
61e57a8d 1790 *
db6cf833 1791 * Return: 0 on success or -1 on failure.
61e57a8d
AJ		 1792 */
1793static int
18df89fe 1794drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
61e57a8d 1795{
18df89fe 1796 struct i2c_adapter *adapter = data;
61e57a8d 1797 unsigned char start = block * EDID_LENGTH;
cd004b3f
S		 1798 unsigned char segment = block >> 1;
1799 unsigned char xfers = segment ? 3 : 2;
4819d2e4
CW		 1800 int ret, retries = 5;
1801
db6cf833
TR		 1802 /*
1803 * The core I2C driver will automatically retry the transfer if the
4819d2e4
CW		 1804 * adapter reports EAGAIN. However, we find that bit-banging transfers
1805 * are susceptible to errors under a heavily loaded machine and
1806 * generate spurious NAKs and timeouts. Retrying the transfer
1807 * of the individual block a few times seems to overcome this.
1808 */
1809 do {
1810 struct i2c_msg msgs[] = {
1811 {
cd004b3f
S		 1812 .addr = DDC_SEGMENT_ADDR,
1813 .flags = 0,
1814 .len = 1,
1815 .buf = &segment,
1816 }, {
4819d2e4
CW		 1817 .addr = DDC_ADDR,
1818 .flags = 0,
1819 .len = 1,
1820 .buf = &start,
1821 }, {
1822 .addr = DDC_ADDR,
1823 .flags = I2C_M_RD,
1824 .len = len,
1825 .buf = buf,
1826 }
1827 };
cd004b3f 1828
db6cf833
TR		 1829 /*
1830 * Avoid sending the segment addr to not upset non-compliant
1831 * DDC monitors.
1832 */
cd004b3f
S		 1833 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1834
9292f37e
ED		 1835 if (ret == -ENXIO) {
1836 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1837 adapter->name);
1838 break;
1839 }
cd004b3f 1840 } while (ret != xfers && --retries);
4819d2e4 1841
cd004b3f 1842 return ret == xfers ? 0 : -1;
61e57a8d
AJ		 1843}
1844
14544d09
CW		 1845static void connector_bad_edid(struct drm_connector *connector,
1846 u8 *edid, int num_blocks)
1847{
1848 int i;
97794170
DA		 1849 u8 last_block;
1850
1851 /*
1852 * 0x7e in the EDID is the number of extension blocks. The EDID
1853 * is 1 (base block) + num_ext_blocks big. That means we can think
1854 * of 0x7e in the EDID of the _index_ of the last block in the
1855 * combined chunk of memory.
1856 */
1857 last_block = edid[0x7e];
e11f5bd8
JFZ		 1858
1859 /* Calculate real checksum for the last edid extension block data */
97794170
DA		 1860 if (last_block < num_blocks)
1861 connector->real_edid_checksum =
1862 drm_edid_block_checksum(edid + last_block * EDID_LENGTH);
14544d09 1863
f0a8f533 1864 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
14544d09
CW		 1865 return;
1866
fa3bfa35 1867 drm_dbg_kms(connector->dev, "%s: EDID is invalid:\n", connector->name);
14544d09
CW		 1868 for (i = 0; i < num_blocks; i++) {
1869 u8 *block = edid + i * EDID_LENGTH;
1870 char prefix[20];
1871
1872 if (drm_edid_is_zero(block, EDID_LENGTH))
1873 sprintf(prefix, "\t[%02x] ZERO ", i);
1874 else if (!drm_edid_block_valid(block, i, false, NULL))
1875 sprintf(prefix, "\t[%02x] BAD ", i);
1876 else
1877 sprintf(prefix, "\t[%02x] GOOD ", i);
1878
fa3bfa35 1879 print_hex_dump(KERN_DEBUG,
14544d09
CW		 1880 prefix, DUMP_PREFIX_NONE, 16, 1,
1881 block, EDID_LENGTH, false);
1882 }
1883}
1884
56a2b7f2
JN		 1885/* Get override or firmware EDID */
1886static struct edid *drm_get_override_edid(struct drm_connector *connector)
1887{
1888 struct edid *override = NULL;
1889
1890 if (connector->override_edid)
1891 override = drm_edid_duplicate(connector->edid_blob_ptr->data);
1892
1893 if (!override)
1894 override = drm_load_edid_firmware(connector);
1895
1896 return IS_ERR(override) ? NULL : override;
1897}
1898
48eaeb76
JN		 1899/**
1900 * drm_add_override_edid_modes - add modes from override/firmware EDID
1901 * @connector: connector we're probing
1902 *
1903 * Add modes from the override/firmware EDID, if available. Only to be used from
1904 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
1905 * failed during drm_get_edid() and caused the override/firmware EDID to be
1906 * skipped.
1907 *
1908 * Return: The number of modes added or 0 if we couldn't find any.
1909 */
1910int drm_add_override_edid_modes(struct drm_connector *connector)
1911{
1912 struct edid *override;
1913 int num_modes = 0;
1914
1915 override = drm_get_override_edid(connector);
1916 if (override) {
1917 drm_connector_update_edid_property(connector, override);
1918 num_modes = drm_add_edid_modes(connector, override);
1919 kfree(override);
1920
1921 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
1922 connector->base.id, connector->name, num_modes);
1923 }
1924
1925 return num_modes;
1926}
1927EXPORT_SYMBOL(drm_add_override_edid_modes);
1928
e7bd95a7 1929static struct edid *drm_do_get_edid_base_block(struct drm_connector *connector,
bac9c294
DA		 1930 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
1931 size_t len),
e7bd95a7 1932 void *data)
bac9c294 1933{
e7bd95a7
DA		 1934 int *null_edid_counter = connector ? &connector->null_edid_counter : NULL;
1935 bool *edid_corrupt = connector ? &connector->edid_corrupt : NULL;
bac9c294 1936 void *edid;
e7bd95a7 1937 int i;
bac9c294
DA		 1938
1939 edid = kmalloc(EDID_LENGTH, GFP_KERNEL);
1940 if (edid == NULL)
1941 return NULL;
1942
1943 /* base block fetch */
1944 for (i = 0; i < 4; i++) {
1945 if (get_edid_block(data, edid, 0, EDID_LENGTH))
1946 goto out;
1947 if (drm_edid_block_valid(edid, 0, false, edid_corrupt))
1948 break;
1949 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) {
1950 if (null_edid_counter)
1951 (*null_edid_counter)++;
1952 goto carp;
1953 }
1954 }
1955 if (i == 4)
1956 goto carp;
1957
1958 return edid;
1959
1960carp:
e7bd95a7
DA		 1961 if (connector)
1962 connector_bad_edid(connector, edid, 1);
bac9c294
DA		 1963out:
1964 kfree(edid);
1965 return NULL;
1966}
1967
18df89fe
LPC		 1968/**
1969 * drm_do_get_edid - get EDID data using a custom EDID block read function
1970 * @connector: connector we're probing
1971 * @get_edid_block: EDID block read function
1972 * @data: private data passed to the block read function
1973 *
1974 * When the I2C adapter connected to the DDC bus is hidden behind a device that
1975 * exposes a different interface to read EDID blocks this function can be used
1976 * to get EDID data using a custom block read function.
1977 *
1978 * As in the general case the DDC bus is accessible by the kernel at the I2C
1979 * level, drivers must make all reasonable efforts to expose it as an I2C
1980 * adapter and use drm_get_edid() instead of abusing this function.
1981 *
0ae865ef 1982 * The EDID may be overridden using debugfs override_edid or firmware EDID
53fd40a9
JN		 1983 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
1984 * order. Having either of them bypasses actual EDID reads.
1985 *
18df89fe
LPC		 1986 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1987 */
1988struct edid *drm_do_get_edid(struct drm_connector *connector,
1989 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
1990 size_t len),
1991 void *data)
61e57a8d 1992{
0ea75e23 1993 int i, j = 0, valid_extensions = 0;
f14f3686 1994 u8 *edid, *new;
56a2b7f2 1995 struct edid *override;
53fd40a9 1996
56a2b7f2
JN		 1997 override = drm_get_override_edid(connector);
1998 if (override)
53fd40a9 1999 return override;
61e57a8d 2000
e7bd95a7
DA		 2001 edid = (u8 *)drm_do_get_edid_base_block(connector, get_edid_block, data);
2002 if (!edid)
61e57a8d 2003 return NULL;
61e57a8d 2004
bac9c294 2005 /* if there's no extensions or no connector, we're done */
14544d09
CW		 2006 valid_extensions = edid[0x7e];
2007 if (valid_extensions == 0)
f14f3686 2008 return (struct edid *)edid;
61e57a8d 2009
14544d09 2010 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
61e57a8d
AJ		 2011 if (!new)
2012 goto out;
f14f3686 2013 edid = new;
61e57a8d 2014
f14f3686 2015 for (j = 1; j <= edid[0x7e]; j++) {
14544d09 2016 u8 *block = edid + j * EDID_LENGTH;
a28187cc 2017
61e57a8d 2018 for (i = 0; i < 4; i++) {
a28187cc 2019 if (get_edid_block(data, block, j, EDID_LENGTH))
61e57a8d 2020 goto out;
14544d09 2021 if (drm_edid_block_valid(block, j, false, NULL))
61e57a8d
AJ		 2022 break;
2023 }
f934ec8c 2024
14544d09
CW		 2025 if (i == 4)
2026 valid_extensions--;
0ea75e23
ST		 2027 }
2028
f14f3686 2029 if (valid_extensions != edid[0x7e]) {
14544d09
CW		 2030 u8 *base;
2031
2032 connector_bad_edid(connector, edid, edid[0x7e] + 1);
2033
f14f3686
CW		 2034 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions;
2035 edid[0x7e] = valid_extensions;
14544d09 2036
6da2ec56
KC		 2037 new = kmalloc_array(valid_extensions + 1, EDID_LENGTH,
2038 GFP_KERNEL);
0ea75e23
ST		 2039 if (!new)
2040 goto out;
14544d09
CW		 2041
2042 base = new;
2043 for (i = 0; i <= edid[0x7e]; i++) {
2044 u8 *block = edid + i * EDID_LENGTH;
2045
2046 if (!drm_edid_block_valid(block, i, false, NULL))
2047 continue;
2048
2049 memcpy(base, block, EDID_LENGTH);
2050 base += EDID_LENGTH;
2051 }
2052
2053 kfree(edid);
f14f3686 2054 edid = new;
61e57a8d
AJ		 2055 }
2056
f14f3686 2057 return (struct edid *)edid;
61e57a8d 2058
61e57a8d 2059out:
f14f3686 2060 kfree(edid);
61e57a8d
AJ		 2061 return NULL;
2062}
18df89fe 2063EXPORT_SYMBOL_GPL(drm_do_get_edid);
61e57a8d
AJ		 2064
2065/**
db6cf833
TR		 2066 * drm_probe_ddc() - probe DDC presence
2067 * @adapter: I2C adapter to probe
fc66811c 2068 *
db6cf833 2069 * Return: True on success, false on failure.
61e57a8d 2070 */
fbff4690 2071bool
61e57a8d
AJ		 2072drm_probe_ddc(struct i2c_adapter *adapter)
2073{
2074 unsigned char out;
2075
2076 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
2077}
fbff4690 2078EXPORT_SYMBOL(drm_probe_ddc);
61e57a8d
AJ		 2079
2080/**
2081 * drm_get_edid - get EDID data, if available
2082 * @connector: connector we're probing
db6cf833 2083 * @adapter: I2C adapter to use for DDC
61e57a8d 2084 *
db6cf833 2085 * Poke the given I2C channel to grab EDID data if possible. If found,
61e57a8d
AJ		 2086 * attach it to the connector.
2087 *
db6cf833 2088 * Return: Pointer to valid EDID or NULL if we couldn't find any.
61e57a8d
AJ		 2089 */
2090struct edid *drm_get_edid(struct drm_connector *connector,
2091 struct i2c_adapter *adapter)
2092{
5186421c
SL		 2093 struct edid *edid;
2094
15f080f0
JN		 2095 if (connector->force == DRM_FORCE_OFF)
2096 return NULL;
2097
2098 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
18df89fe 2099 return NULL;
61e57a8d 2100
5186421c
SL		 2101 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
2102 drm_connector_update_edid_property(connector, edid);
2103 return edid;
61e57a8d
AJ		 2104}
2105EXPORT_SYMBOL(drm_get_edid);
2106
d9f91a10
DA		 2107static u32 edid_extract_panel_id(const struct edid *edid)
2108{
2109 /*
e8de4d55
DA		 2110 * We represent the ID as a 32-bit number so it can easily be compared
2111 * with "==".
d9f91a10
DA		 2112 *
2113 * NOTE that we deal with endianness differently for the top half
2114 * of this ID than for the bottom half. The bottom half (the product
2115 * id) gets decoded as little endian by the EDID_PRODUCT_ID because
2116 * that's how everyone seems to interpret it. The top half (the mfg_id)
2117 * gets stored as big endian because that makes
2118 * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier
2119 * to write (it's easier to extract the ASCII). It doesn't really
2120 * matter, though, as long as the number here is unique.
2121 */
2122 return (u32)edid->mfg_id[0] << 24 |
2123 (u32)edid->mfg_id[1] << 16 |
2124 (u32)EDID_PRODUCT_ID(edid);
2125}
2126
2127/**
2128 * drm_edid_get_panel_id - Get a panel's ID through DDC
2129 * @adapter: I2C adapter to use for DDC
2130 *
2131 * This function reads the first block of the EDID of a panel and (assuming
2132 * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value
2133 * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's
2134 * supposed to be different for each different modem of panel.
2135 *
2136 * This function is intended to be used during early probing on devices where
2137 * more than one panel might be present. Because of its intended use it must
2138 * assume that the EDID of the panel is correct, at least as far as the ID
2139 * is concerned (in other words, we don't process any overrides here).
2140 *
2141 * NOTE: it's expected that this function and drm_do_get_edid() will both
2142 * be read the EDID, but there is no caching between them. Since we're only
2143 * reading the first block, hopefully this extra overhead won't be too big.
2144 *
2145 * Return: A 32-bit ID that should be different for each make/model of panel.
2146 * See the functions drm_edid_encode_panel_id() and
2147 * drm_edid_decode_panel_id() for some details on the structure of this
2148 * ID.
2149 */
2150
2151u32 drm_edid_get_panel_id(struct i2c_adapter *adapter)
2152{
2153 struct edid *edid;
2154 u32 panel_id;
2155
e7bd95a7 2156 edid = drm_do_get_edid_base_block(NULL, drm_do_probe_ddc_edid, adapter);
d9f91a10
DA		 2157
2158 /*
2159 * There are no manufacturer IDs of 0, so if there is a problem reading
2160 * the EDID then we'll just return 0.
2161 */
e7bd95a7 2162 if (!edid)
d9f91a10
DA		 2163 return 0;
2164
2165 panel_id = edid_extract_panel_id(edid);
2166 kfree(edid);
2167
2168 return panel_id;
2169}
2170EXPORT_SYMBOL(drm_edid_get_panel_id);
2171
5cb8eaa2
LW		 2172/**
2173 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
2174 * @connector: connector we're probing
2175 * @adapter: I2C adapter to use for DDC
2176 *
2177 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
2178 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
2179 * switch DDC to the GPU which is retrieving EDID.
2180 *
2181 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2182 */
2183struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
2184 struct i2c_adapter *adapter)
2185{
36b73b05
TZ		 2186 struct drm_device *dev = connector->dev;
2187 struct pci_dev *pdev = to_pci_dev(dev->dev);
5cb8eaa2
LW		 2188 struct edid *edid;
2189
36b73b05
TZ		 2190 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev)))
2191 return NULL;
2192
5cb8eaa2
LW		 2193 vga_switcheroo_lock_ddc(pdev);
2194 edid = drm_get_edid(connector, adapter);
2195 vga_switcheroo_unlock_ddc(pdev);
2196
2197 return edid;
2198}
2199EXPORT_SYMBOL(drm_get_edid_switcheroo);
2200
51f8da59
JN		 2201/**
2202 * drm_edid_duplicate - duplicate an EDID and the extensions
2203 * @edid: EDID to duplicate
2204 *
db6cf833 2205 * Return: Pointer to duplicated EDID or NULL on allocation failure.
51f8da59
JN		 2206 */
2207struct edid *drm_edid_duplicate(const struct edid *edid)
2208{
2209 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
2210}
2211EXPORT_SYMBOL(drm_edid_duplicate);
2212
61e57a8d
AJ		 2213/*** EDID parsing ***/
2214
f453ba04
DA		 2215/**
2216 * edid_get_quirks - return quirk flags for a given EDID
2217 * @edid: EDID to process
2218 *
2219 * This tells subsequent routines what fixes they need to apply.
2220 */
170178fe 2221static u32 edid_get_quirks(const struct edid *edid)
f453ba04 2222{
e8de4d55 2223 u32 panel_id = edid_extract_panel_id(edid);
23c4cfbd 2224 const struct edid_quirk *quirk;
f453ba04
DA		 2225 int i;
2226
2227 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
2228 quirk = &edid_quirk_list[i];
e8de4d55 2229 if (quirk->panel_id == panel_id)
f453ba04
DA		 2230 return quirk->quirks;
2231 }
2232
2233 return 0;
2234}
2235
2236#define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
339d202c 2237#define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
f453ba04 2238
f453ba04
DA		 2239/**
2240 * edid_fixup_preferred - set preferred modes based on quirk list
2241 * @connector: has mode list to fix up
2242 * @quirks: quirks list
2243 *
2244 * Walk the mode list for @connector, clearing the preferred status
2245 * on existing modes and setting it anew for the right mode ala @quirks.
2246 */
2247static void edid_fixup_preferred(struct drm_connector *connector,
2248 u32 quirks)
2249{
2250 struct drm_display_mode *t, *cur_mode, *preferred_mode;
f890607b 2251 int target_refresh = 0;
339d202c 2252 int cur_vrefresh, preferred_vrefresh;
f453ba04
DA		 2253
2254 if (list_empty(&connector->probed_modes))
2255 return;
2256
2257 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
2258 target_refresh = 60;
2259 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
2260 target_refresh = 75;
2261
2262 preferred_mode = list_first_entry(&connector->probed_modes,
2263 struct drm_display_mode, head);
2264
2265 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
2266 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
2267
2268 if (cur_mode == preferred_mode)
2269 continue;
2270
2271 /* Largest mode is preferred */
2272 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
2273 preferred_mode = cur_mode;
2274
0425662f
VS		 2275 cur_vrefresh = drm_mode_vrefresh(cur_mode);
2276 preferred_vrefresh = drm_mode_vrefresh(preferred_mode);
f453ba04
DA		 2277 /* At a given size, try to get closest to target refresh */
2278 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
339d202c
AD		 2279 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
2280 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
f453ba04
DA		 2281 preferred_mode = cur_mode;
2282 }
2283 }
2284
2285 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
2286}
2287
f6e252ba
AJ		 2288static bool
2289mode_is_rb(const struct drm_display_mode *mode)
2290{
2291 return (mode->htotal - mode->hdisplay == 160) &&
2292 (mode->hsync_end - mode->hdisplay == 80) &&
2293 (mode->hsync_end - mode->hsync_start == 32) &&
2294 (mode->vsync_start - mode->vdisplay == 3);
2295}
2296
33c7531d
AJ		 2297/*
2298 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
2299 * @dev: Device to duplicate against
2300 * @hsize: Mode width
2301 * @vsize: Mode height
2302 * @fresh: Mode refresh rate
f6e252ba 2303 * @rb: Mode reduced-blanking-ness
33c7531d
AJ		 2304 *
2305 * Walk the DMT mode list looking for a match for the given parameters.
db6cf833
TR		 2306 *
2307 * Return: A newly allocated copy of the mode, or NULL if not found.
33c7531d 2308 */
1d42bbc8 2309struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
f6e252ba
AJ		 2310 int hsize, int vsize, int fresh,
2311 bool rb)
559ee21d 2312{
07a5e632 2313 int i;
559ee21d 2314
a6b21831 2315 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
b1f559ec 2316 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
948de842 2317
f8b46a05
AJ		 2318 if (hsize != ptr->hdisplay)
2319 continue;
2320 if (vsize != ptr->vdisplay)
2321 continue;
2322 if (fresh != drm_mode_vrefresh(ptr))
2323 continue;
f6e252ba
AJ		 2324 if (rb != mode_is_rb(ptr))
2325 continue;
f8b46a05
AJ		 2326
2327 return drm_mode_duplicate(dev, ptr);
559ee21d 2328 }
f8b46a05
AJ		 2329
2330 return NULL;
559ee21d 2331}
1d42bbc8 2332EXPORT_SYMBOL(drm_mode_find_dmt);
23425cae 2333
a7a131ac
VS		 2334static bool is_display_descriptor(const u8 d[18], u8 tag)
2335{
2336 return d[0] == 0x00 && d[1] == 0x00 &&
2337 d[2] == 0x00 && d[3] == tag;
2338}
2339
f447dd1f
VS		 2340static bool is_detailed_timing_descriptor(const u8 d[18])
2341{
2342 return d[0] != 0x00 || d[1] != 0x00;
2343}
2344
d1ff6409
AJ		 2345typedef void detailed_cb(struct detailed_timing *timing, void *closure);
2346
4d76a221
AJ		 2347static void
2348cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
2349{
7304b981 2350 int i, n;
4966b2a9 2351 u8 d = ext[0x02];
4d76a221
AJ		 2352 u8 *det_base = ext + d;
2353
7304b981
VS		 2354 if (d < 4 || d > 127)
2355 return;
2356
4966b2a9 2357 n = (127 - d) / 18;
4d76a221
AJ		 2358 for (i = 0; i < n; i++)
2359 cb((struct detailed_timing *)(det_base + 18 * i), closure);
2360}
2361
cbba98f8
AJ		 2362static void
2363vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
2364{
2365 unsigned int i, n = min((int)ext[0x02], 6);
2366 u8 *det_base = ext + 5;
2367
2368 if (ext[0x01] != 1)
2369 return; /* unknown version */
2370
2371 for (i = 0; i < n; i++)
2372 cb((struct detailed_timing *)(det_base + 18 * i), closure);
2373}
2374
d1ff6409
AJ		 2375static void
2376drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
2377{
2378 int i;
2379 struct edid *edid = (struct edid *)raw_edid;
2380
2381 if (edid == NULL)
2382 return;
2383
2384 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
2385 cb(&(edid->detailed_timings[i]), closure);
2386
4d76a221
AJ		 2387 for (i = 1; i <= raw_edid[0x7e]; i++) {
2388 u8 *ext = raw_edid + (i * EDID_LENGTH);
948de842 2389
4d76a221
AJ		 2390 switch (*ext) {
2391 case CEA_EXT:
2392 cea_for_each_detailed_block(ext, cb, closure);
2393 break;
cbba98f8
AJ		 2394 case VTB_EXT:
2395 vtb_for_each_detailed_block(ext, cb, closure);
2396 break;
4d76a221
AJ		 2397 default:
2398 break;
2399 }
2400 }
d1ff6409
AJ		 2401}
2402
2403static void
2404is_rb(struct detailed_timing *t, void *data)
2405{
2406 u8 *r = (u8 *)t;
a7a131ac
VS		 2407
2408 if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE))
2409 return;
2410
2411 if (r[15] & 0x10)
2412 *(bool *)data = true;
d1ff6409
AJ		 2413}
2414
2415/* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
2416static bool
2417drm_monitor_supports_rb(struct edid *edid)
2418{
2419 if (edid->revision >= 4) {
b196a498 2420 bool ret = false;
948de842 2421
d1ff6409
AJ		 2422 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
2423 return ret;
2424 }
2425
2426 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
2427}
2428
7a374350
AJ		 2429static void
2430find_gtf2(struct detailed_timing *t, void *data)
2431{
2432 u8 *r = (u8 *)t;
a7a131ac
VS		 2433
2434 if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE))
2435 return;
2436
2437 if (r[10] == 0x02)
7a374350
AJ		 2438 *(u8 **)data = r;
2439}
2440
2441/* Secondary GTF curve kicks in above some break frequency */
2442static int
2443drm_gtf2_hbreak(struct edid *edid)
2444{
2445 u8 *r = NULL;
948de842 2446
7a374350
AJ		 2447 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2448 return r ? (r[12] * 2) : 0;
2449}
2450
2451static int
2452drm_gtf2_2c(struct edid *edid)
2453{
2454 u8 *r = NULL;
948de842 2455
7a374350
AJ		 2456 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2457 return r ? r[13] : 0;
2458}
2459
2460static int
2461drm_gtf2_m(struct edid *edid)
2462{
2463 u8 *r = NULL;
948de842 2464
7a374350
AJ		 2465 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2466 return r ? (r[15] << 8) + r[14] : 0;
2467}
2468
2469static int
2470drm_gtf2_k(struct edid *edid)
2471{
2472 u8 *r = NULL;
948de842 2473
7a374350
AJ		 2474 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2475 return r ? r[16] : 0;
2476}
2477
2478static int
2479drm_gtf2_2j(struct edid *edid)
2480{
2481 u8 *r = NULL;
948de842 2482
7a374350
AJ		 2483 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2484 return r ? r[17] : 0;
2485}
2486
2487/**
2488 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
2489 * @edid: EDID block to scan
2490 */
2491static int standard_timing_level(struct edid *edid)
2492{
2493 if (edid->revision >= 2) {
2494 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
2495 return LEVEL_CVT;
2496 if (drm_gtf2_hbreak(edid))
2497 return LEVEL_GTF2;
bfef04ad
LS		 2498 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
2499 return LEVEL_GTF;
7a374350
AJ		 2500 }
2501 return LEVEL_DMT;
2502}
2503
23425cae
AJ		 2504/*
2505 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
2506 * monitors fill with ascii space (0x20) instead.
2507 */
2508static int
2509bad_std_timing(u8 a, u8 b)
2510{
2511 return (a == 0x00 && b == 0x00) ||
2512 (a == 0x01 && b == 0x01) ||
2513 (a == 0x20 && b == 0x20);
2514}
2515
58911c24
VS		 2516static int drm_mode_hsync(const struct drm_display_mode *mode)
2517{
2518 if (mode->htotal <= 0)
2519 return 0;
2520
2521 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal);
2522}
2523
f453ba04
DA		 2524/**
2525 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
fc66811c
DV		 2526 * @connector: connector of for the EDID block
2527 * @edid: EDID block to scan
f453ba04
DA		 2528 * @t: standard timing params
2529 *
2530 * Take the standard timing params (in this case width, aspect, and refresh)
5c61259e 2531 * and convert them into a real mode using CVT/GTF/DMT.
f453ba04 2532 */
7ca6adb3 2533static struct drm_display_mode *
7a374350 2534drm_mode_std(struct drm_connector *connector, struct edid *edid,
464fdeca 2535 struct std_timing *t)
f453ba04 2536{
7ca6adb3
AJ		 2537 struct drm_device *dev = connector->dev;
2538 struct drm_display_mode *m, *mode = NULL;
5c61259e
ZY		 2539 int hsize, vsize;
2540 int vrefresh_rate;
0454beab
MD		 2541 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
2542 >> EDID_TIMING_ASPECT_SHIFT;
5c61259e
ZY		 2543 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
2544 >> EDID_TIMING_VFREQ_SHIFT;
7a374350 2545 int timing_level = standard_timing_level(edid);
5c61259e 2546
23425cae
AJ		 2547 if (bad_std_timing(t->hsize, t->vfreq_aspect))
2548 return NULL;
2549
5c61259e
ZY		 2550 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
2551 hsize = t->hsize * 8 + 248;
2552 /* vrefresh_rate = vfreq + 60 */
2553 vrefresh_rate = vfreq + 60;
2554 /* the vdisplay is calculated based on the aspect ratio */
f066a17d 2555 if (aspect_ratio == 0) {
464fdeca 2556 if (edid->revision < 3)
f066a17d
AJ		 2557 vsize = hsize;
2558 else
2559 vsize = (hsize * 10) / 16;
2560 } else if (aspect_ratio == 1)
f453ba04 2561 vsize = (hsize * 3) / 4;
0454beab 2562 else if (aspect_ratio == 2)
f453ba04
DA		 2563 vsize = (hsize * 4) / 5;
2564 else
2565 vsize = (hsize * 9) / 16;
a0910c8e
AJ		 2566
2567 /* HDTV hack, part 1 */
2568 if (vrefresh_rate == 60 &&
2569 ((hsize == 1360 && vsize == 765) ||
2570 (hsize == 1368 && vsize == 769))) {
2571 hsize = 1366;
2572 vsize = 768;
2573 }
2574
7ca6adb3
AJ		 2575 /*
2576 * If this connector already has a mode for this size and refresh
2577 * rate (because it came from detailed or CVT info), use that
2578 * instead. This way we don't have to guess at interlace or
2579 * reduced blanking.
2580 */
522032da 2581 list_for_each_entry(m, &connector->probed_modes, head)
7ca6adb3
AJ		 2582 if (m->hdisplay == hsize && m->vdisplay == vsize &&
2583 drm_mode_vrefresh(m) == vrefresh_rate)
2584 return NULL;
2585
a0910c8e
AJ		 2586 /* HDTV hack, part 2 */
2587 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
2588 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
d50ba256 2589 false);
a5ef6567
JM		 2590 if (!mode)
2591 return NULL;
559ee21d 2592 mode->hdisplay = 1366;
a4967de6
AJ		 2593 mode->hsync_start = mode->hsync_start - 1;
2594 mode->hsync_end = mode->hsync_end - 1;
559ee21d
ZY		 2595 return mode;
2596 }
a0910c8e 2597
559ee21d 2598 /* check whether it can be found in default mode table */
f6e252ba
AJ		 2599 if (drm_monitor_supports_rb(edid)) {
2600 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
2601 true);
2602 if (mode)
2603 return mode;
2604 }
2605 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
559ee21d
ZY		 2606 if (mode)
2607 return mode;
2608
f6e252ba 2609 /* okay, generate it */
5c61259e
ZY		 2610 switch (timing_level) {
2611 case LEVEL_DMT:
5c61259e
ZY		 2612 break;
2613 case LEVEL_GTF:
2614 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2615 break;
7a374350
AJ		 2616 case LEVEL_GTF2:
2617 /*
2618 * This is potentially wrong if there's ever a monitor with
2619 * more than one ranges section, each claiming a different
2620 * secondary GTF curve. Please don't do that.
2621 */
2622 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
fc48f169
TI		 2623 if (!mode)
2624 return NULL;
7a374350 2625 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
aefd330e 2626 drm_mode_destroy(dev, mode);
7a374350
AJ		 2627 mode = drm_gtf_mode_complex(dev, hsize, vsize,
2628 vrefresh_rate, 0, 0,
2629 drm_gtf2_m(edid),
2630 drm_gtf2_2c(edid),
2631 drm_gtf2_k(edid),
2632 drm_gtf2_2j(edid));
2633 }
2634 break;
5c61259e 2635 case LEVEL_CVT:
d50ba256
DA		 2636 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
2637 false);
5c61259e
ZY		 2638 break;
2639 }
f453ba04
DA		 2640 return mode;
2641}
2642
b58db2c6
AJ		 2643/*
2644 * EDID is delightfully ambiguous about how interlaced modes are to be
2645 * encoded. Our internal representation is of frame height, but some
2646 * HDTV detailed timings are encoded as field height.
2647 *
2648 * The format list here is from CEA, in frame size. Technically we
2649 * should be checking refresh rate too. Whatever.
2650 */
2651static void
2652drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
2653 struct detailed_pixel_timing *pt)
2654{
2655 int i;
2656 static const struct {
2657 int w, h;
2658 } cea_interlaced[] = {
2659 { 1920, 1080 },
2660 { 720, 480 },
2661 { 1440, 480 },
2662 { 2880, 480 },
2663 { 720, 576 },
2664 { 1440, 576 },
2665 { 2880, 576 },
2666 };
b58db2c6
AJ		 2667
2668 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
2669 return;
2670
3c581411 2671 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
b58db2c6
AJ		 2672 if ((mode->hdisplay == cea_interlaced[i].w) &&
2673 (mode->vdisplay == cea_interlaced[i].h / 2)) {
2674 mode->vdisplay *= 2;
2675 mode->vsync_start *= 2;
2676 mode->vsync_end *= 2;
2677 mode->vtotal *= 2;
2678 mode->vtotal |= 1;
2679 }
2680 }
2681
2682 mode->flags |= DRM_MODE_FLAG_INTERLACE;
2683}
2684
f453ba04
DA		 2685/**
2686 * drm_mode_detailed - create a new mode from an EDID detailed timing section
2687 * @dev: DRM device (needed to create new mode)
2688 * @edid: EDID block
2689 * @timing: EDID detailed timing info
2690 * @quirks: quirks to apply
2691 *
2692 * An EDID detailed timing block contains enough info for us to create and
2693 * return a new struct drm_display_mode.
2694 */
2695static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
2696 struct edid *edid,
2697 struct detailed_timing *timing,
2698 u32 quirks)
2699{
2700 struct drm_display_mode *mode;
2701 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
0454beab
MD		 2702 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
2703 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
2704 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
2705 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
e14cbee4
MD		 2706 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
2707 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
16dad1d7 2708 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
e14cbee4 2709 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
f453ba04 2710
fc438966 2711 /* ignore tiny modes */
0454beab 2712 if (hactive < 64 || vactive < 64)
fc438966
AJ		 2713 return NULL;
2714
0454beab 2715 if (pt->misc & DRM_EDID_PT_STEREO) {
c7d015f3 2716 DRM_DEBUG_KMS("stereo mode not supported\n");
f453ba04
DA		 2717 return NULL;
2718 }
0454beab 2719 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
c7d015f3 2720 DRM_DEBUG_KMS("composite sync not supported\n");
f453ba04
DA		 2721 }
2722
fcb45611
ZY		 2723 /* it is incorrect if hsync/vsync width is zero */
2724 if (!hsync_pulse_width || !vsync_pulse_width) {
2725 DRM_DEBUG_KMS("Incorrect Detailed timing. "
2726 "Wrong Hsync/Vsync pulse width\n");
2727 return NULL;
2728 }
bc42aabc
AJ		 2729
2730 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
2731 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
2732 if (!mode)
2733 return NULL;
2734
2735 goto set_size;
2736 }
2737
f453ba04
DA		 2738 mode = drm_mode_create(dev);
2739 if (!mode)
2740 return NULL;
2741
f453ba04 2742 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
0454beab
MD		 2743 timing->pixel_clock = cpu_to_le16(1088);
2744
2745 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
2746
2747 mode->hdisplay = hactive;
2748 mode->hsync_start = mode->hdisplay + hsync_offset;
2749 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
2750 mode->htotal = mode->hdisplay + hblank;
2751
2752 mode->vdisplay = vactive;
2753 mode->vsync_start = mode->vdisplay + vsync_offset;
2754 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
2755 mode->vtotal = mode->vdisplay + vblank;
f453ba04 2756
7064fef5
JB		 2757 /* Some EDIDs have bogus h/vtotal values */
2758 if (mode->hsync_end > mode->htotal)
2759 mode->htotal = mode->hsync_end + 1;
2760 if (mode->vsync_end > mode->vtotal)
2761 mode->vtotal = mode->vsync_end + 1;
2762
b58db2c6 2763 drm_mode_do_interlace_quirk(mode, pt);
f453ba04
DA		 2764
2765 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
0454beab 2766 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
f453ba04
DA		 2767 }
2768
0454beab
MD		 2769 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
2770 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
2771 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
2772 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
f453ba04 2773
bc42aabc 2774set_size:
e14cbee4
MD		 2775 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
2776 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
f453ba04
DA		 2777
2778 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
2779 mode->width_mm *= 10;
2780 mode->height_mm *= 10;
2781 }
2782
2783 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
2784 mode->width_mm = edid->width_cm * 10;
2785 mode->height_mm = edid->height_cm * 10;
2786 }
2787
bc42aabc
AJ		 2788 mode->type = DRM_MODE_TYPE_DRIVER;
2789 drm_mode_set_name(mode);
2790
f453ba04
DA		 2791 return mode;
2792}
2793
b17e52ef 2794static bool
b1f559ec
CW		 2795mode_in_hsync_range(const struct drm_display_mode *mode,
2796 struct edid *edid, u8 *t)
b17e52ef
AJ		 2797{
2798 int hsync, hmin, hmax;
2799
2800 hmin = t[7];
2801 if (edid->revision >= 4)
2802 hmin += ((t[4] & 0x04) ? 255 : 0);
2803 hmax = t[8];
2804 if (edid->revision >= 4)
2805 hmax += ((t[4] & 0x08) ? 255 : 0);
07a5e632 2806 hsync = drm_mode_hsync(mode);
07a5e632 2807
b17e52ef
AJ		 2808 return (hsync <= hmax && hsync >= hmin);
2809}
2810
2811static bool
b1f559ec
CW		 2812mode_in_vsync_range(const struct drm_display_mode *mode,
2813 struct edid *edid, u8 *t)
b17e52ef
AJ		 2814{
2815 int vsync, vmin, vmax;
2816
2817 vmin = t[5];
2818 if (edid->revision >= 4)
2819 vmin += ((t[4] & 0x01) ? 255 : 0);
2820 vmax = t[6];
2821 if (edid->revision >= 4)
2822 vmax += ((t[4] & 0x02) ? 255 : 0);
2823 vsync = drm_mode_vrefresh(mode);
2824
2825 return (vsync <= vmax && vsync >= vmin);
2826}
2827
2828static u32
2829range_pixel_clock(struct edid *edid, u8 *t)
2830{
2831 /* unspecified */
2832 if (t[9] == 0 || t[9] == 255)
2833 return 0;
2834
2835 /* 1.4 with CVT support gives us real precision, yay */
2836 if (edid->revision >= 4 && t[10] == 0x04)
2837 return (t[9] * 10000) - ((t[12] >> 2) * 250);
2838
2839 /* 1.3 is pathetic, so fuzz up a bit */
2840 return t[9] * 10000 + 5001;
2841}
2842
b17e52ef 2843static bool
b1f559ec 2844mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
b17e52ef
AJ		 2845 struct detailed_timing *timing)
2846{
2847 u32 max_clock;
2848 u8 *t = (u8 *)timing;
2849
2850 if (!mode_in_hsync_range(mode, edid, t))
07a5e632
AJ		 2851 return false;
2852
b17e52ef 2853 if (!mode_in_vsync_range(mode, edid, t))
07a5e632
AJ		 2854 return false;
2855
b17e52ef 2856 if ((max_clock = range_pixel_clock(edid, t)))
07a5e632
AJ		 2857 if (mode->clock > max_clock)
2858 return false;
b17e52ef
AJ		 2859
2860 /* 1.4 max horizontal check */
2861 if (edid->revision >= 4 && t[10] == 0x04)
2862 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
2863 return false;
2864
2865 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
2866 return false;
07a5e632
AJ		 2867
2868 return true;
2869}
2870
7b668ebe
TI		 2871static bool valid_inferred_mode(const struct drm_connector *connector,
2872 const struct drm_display_mode *mode)
2873{
85f8fcd6 2874 const struct drm_display_mode *m;
7b668ebe
TI		 2875 bool ok = false;
2876
2877 list_for_each_entry(m, &connector->probed_modes, head) {
2878 if (mode->hdisplay == m->hdisplay &&
2879 mode->vdisplay == m->vdisplay &&
2880 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
2881 return false; /* duplicated */
2882 if (mode->hdisplay <= m->hdisplay &&
2883 mode->vdisplay <= m->vdisplay)
2884 ok = true;
2885 }
2886 return ok;
2887}
2888
b17e52ef 2889static int
cd4cd3de 2890drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
b17e52ef 2891 struct detailed_timing *timing)
07a5e632
AJ		 2892{
2893 int i, modes = 0;
2894 struct drm_display_mode *newmode;
2895 struct drm_device *dev = connector->dev;
2896
a6b21831 2897 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
7b668ebe
TI		 2898 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
2899 valid_inferred_mode(connector, drm_dmt_modes + i)) {
07a5e632
AJ		 2900 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
2901 if (newmode) {
2902 drm_mode_probed_add(connector, newmode);
2903 modes++;
2904 }
2905 }
2906 }
2907
2908 return modes;
2909}
2910
c09dedb7
TI		 2911/* fix up 1366x768 mode from 1368x768;
2912 * GFT/CVT can't express 1366 width which isn't dividable by 8
2913 */
969218fe 2914void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
c09dedb7
TI		 2915{
2916 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
2917 mode->hdisplay = 1366;
2918 mode->hsync_start--;
2919 mode->hsync_end--;
2920 drm_mode_set_name(mode);
2921 }
2922}
2923
b309bd37
AJ		 2924static int
2925drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
2926 struct detailed_timing *timing)
2927{
2928 int i, modes = 0;
2929 struct drm_display_mode *newmode;
2930 struct drm_device *dev = connector->dev;
2931
a6b21831 2932 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
b309bd37 2933 const struct minimode *m = &extra_modes[i];
948de842 2934
b309bd37 2935 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
fc48f169
TI		 2936 if (!newmode)
2937 return modes;
b309bd37 2938
969218fe 2939 drm_mode_fixup_1366x768(newmode);
7b668ebe
TI		 2940 if (!mode_in_range(newmode, edid, timing) ||
2941 !valid_inferred_mode(connector, newmode)) {
b309bd37
AJ		 2942 drm_mode_destroy(dev, newmode);
2943 continue;
2944 }
2945
2946 drm_mode_probed_add(connector, newmode);
2947 modes++;
2948 }
2949
2950 return modes;
2951}
2952
2953static int
2954drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2955 struct detailed_timing *timing)
2956{
2957 int i, modes = 0;
2958 struct drm_display_mode *newmode;
2959 struct drm_device *dev = connector->dev;
2960 bool rb = drm_monitor_supports_rb(edid);
2961
a6b21831 2962 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
b309bd37 2963 const struct minimode *m = &extra_modes[i];
948de842 2964
b309bd37 2965 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
fc48f169
TI		 2966 if (!newmode)
2967 return modes;
b309bd37 2968
969218fe 2969 drm_mode_fixup_1366x768(newmode);
7b668ebe
TI		 2970 if (!mode_in_range(newmode, edid, timing) ||
2971 !valid_inferred_mode(connector, newmode)) {
b309bd37
AJ		 2972 drm_mode_destroy(dev, newmode);
2973 continue;
2974 }
2975
2976 drm_mode_probed_add(connector, newmode);
2977 modes++;
2978 }
2979
2980 return modes;
2981}
2982
13931579
AJ		 2983static void
2984do_inferred_modes(struct detailed_timing *timing, void *c)
9340d8cf 2985{
13931579
AJ		 2986 struct detailed_mode_closure *closure = c;
2987 struct detailed_non_pixel *data = &timing->data.other_data;
b309bd37 2988 struct detailed_data_monitor_range *range = &data->data.range;
9340d8cf 2989
a7a131ac 2990 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE))
cb21aafe
AJ		 2991 return;
2992
2993 closure->modes += drm_dmt_modes_for_range(closure->connector,
2994 closure->edid,
2995 timing);
4d23f484 2996
b309bd37
AJ		 2997 if (!version_greater(closure->edid, 1, 1))
2998 return; /* GTF not defined yet */
2999
3000 switch (range->flags) {
3001 case 0x02: /* secondary gtf, XXX could do more */
3002 case 0x00: /* default gtf */
3003 closure->modes += drm_gtf_modes_for_range(closure->connector,
3004 closure->edid,
3005 timing);
3006 break;
3007 case 0x04: /* cvt, only in 1.4+ */
3008 if (!version_greater(closure->edid, 1, 3))
3009 break;
3010
3011 closure->modes += drm_cvt_modes_for_range(closure->connector,
3012 closure->edid,
3013 timing);
3014 break;
3015 case 0x01: /* just the ranges, no formula */
3016 default:
3017 break;
3018 }
13931579 3019}
69da3015 3020
13931579
AJ		 3021static int
3022add_inferred_modes(struct drm_connector *connector, struct edid *edid)
3023{
3024 struct detailed_mode_closure closure = {
d456ea2e
JL		 3025 .connector = connector,
3026 .edid = edid,
13931579 3027 };
9340d8cf 3028
13931579
AJ		 3029 if (version_greater(edid, 1, 0))
3030 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
3031 &closure);
9340d8cf 3032
13931579 3033 return closure.modes;
9340d8cf
AJ		 3034}
3035
2255be14
AJ		 3036static int
3037drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
3038{
3039 int i, j, m, modes = 0;
3040 struct drm_display_mode *mode;
f3a32d74 3041 u8 *est = ((u8 *)timing) + 6;
2255be14
AJ		 3042
3043 for (i = 0; i < 6; i++) {
891a7469 3044 for (j = 7; j >= 0; j--) {
2255be14 3045 m = (i * 8) + (7 - j);
3c581411 3046 if (m >= ARRAY_SIZE(est3_modes))
2255be14
AJ		 3047 break;
3048 if (est[i] & (1 << j)) {
1d42bbc8
DA		 3049 mode = drm_mode_find_dmt(connector->dev,
3050 est3_modes[m].w,
3051 est3_modes[m].h,
f6e252ba
AJ		 3052 est3_modes[m].r,
3053 est3_modes[m].rb);
2255be14
AJ		 3054 if (mode) {
3055 drm_mode_probed_add(connector, mode);
3056 modes++;
3057 }
3058 }
3059 }
3060 }
3061
3062 return modes;
3063}
3064
13931579
AJ		 3065static void
3066do_established_modes(struct detailed_timing *timing, void *c)
9cf00977 3067{
13931579 3068 struct detailed_mode_closure *closure = c;
9cf00977 3069
a7a131ac
VS		 3070 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_EST_TIMINGS))
3071 return;
3072
3073 closure->modes += drm_est3_modes(closure->connector, timing);
13931579 3074}
9cf00977 3075
13931579
AJ		 3076/**
3077 * add_established_modes - get est. modes from EDID and add them
db6cf833 3078 * @connector: connector to add mode(s) to
13931579
AJ		 3079 * @edid: EDID block to scan
3080 *
3081 * Each EDID block contains a bitmap of the supported "established modes" list
3082 * (defined above). Tease them out and add them to the global modes list.
3083 */
3084static int
3085add_established_modes(struct drm_connector *connector, struct edid *edid)
3086{
3087 struct drm_device *dev = connector->dev;
3088 unsigned long est_bits = edid->established_timings.t1 |
3089 (edid->established_timings.t2 << 8) |
3090 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
3091 int i, modes = 0;
3092 struct detailed_mode_closure closure = {
d456ea2e
JL		 3093 .connector = connector,
3094 .edid = edid,
13931579 3095 };
9cf00977 3096
13931579
AJ		 3097 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
3098 if (est_bits & (1<<i)) {
3099 struct drm_display_mode *newmode;
948de842 3100
13931579
AJ		 3101 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
3102 if (newmode) {
3103 drm_mode_probed_add(connector, newmode);
3104 modes++;
3105 }
3106 }
9cf00977
AJ		 3107 }
3108
13931579
AJ		 3109 if (version_greater(edid, 1, 0))
3110 drm_for_each_detailed_block((u8 *)edid,
3111 do_established_modes, &closure);
3112
3113 return modes + closure.modes;
3114}
3115
3116static void
3117do_standard_modes(struct detailed_timing *timing, void *c)
3118{
3119 struct detailed_mode_closure *closure = c;
3120 struct detailed_non_pixel *data = &timing->data.other_data;
3121 struct drm_connector *connector = closure->connector;
3122 struct edid *edid = closure->edid;
a7a131ac 3123 int i;
13931579 3124
a7a131ac
VS		 3125 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_STD_MODES))
3126 return;
9cf00977 3127
a7a131ac
VS		 3128 for (i = 0; i < 6; i++) {
3129 struct std_timing *std = &data->data.timings[i];
3130 struct drm_display_mode *newmode;
3131
3132 newmode = drm_mode_std(connector, edid, std);
3133 if (newmode) {
3134 drm_mode_probed_add(connector, newmode);
3135 closure->modes++;
9cf00977 3136 }
9cf00977 3137 }
9cf00977
AJ		 3138}
3139
f453ba04 3140/**
13931579 3141 * add_standard_modes - get std. modes from EDID and add them
db6cf833 3142 * @connector: connector to add mode(s) to
f453ba04 3143 * @edid: EDID block to scan
f453ba04 3144 *
13931579
AJ		 3145 * Standard modes can be calculated using the appropriate standard (DMT,
3146 * GTF or CVT. Grab them from @edid and add them to the list.
f453ba04 3147 */
13931579
AJ		 3148static int
3149add_standard_modes(struct drm_connector *connector, struct edid *edid)
f453ba04 3150{
9cf00977 3151 int i, modes = 0;
13931579 3152 struct detailed_mode_closure closure = {
d456ea2e
JL		 3153 .connector = connector,
3154 .edid = edid,
13931579
AJ		 3155 };
3156
3157 for (i = 0; i < EDID_STD_TIMINGS; i++) {
3158 struct drm_display_mode *newmode;
3159
3160 newmode = drm_mode_std(connector, edid,
464fdeca 3161 &edid->standard_timings[i]);
13931579
AJ		 3162 if (newmode) {
3163 drm_mode_probed_add(connector, newmode);
3164 modes++;
3165 }
3166 }
3167
3168 if (version_greater(edid, 1, 0))
3169 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
3170 &closure);
3171
3172 /* XXX should also look for standard codes in VTB blocks */
3173
3174 return modes + closure.modes;
3175}
f453ba04 3176
13931579
AJ		 3177static int drm_cvt_modes(struct drm_connector *connector,
3178 struct detailed_timing *timing)
3179{
3180 int i, j, modes = 0;
3181 struct drm_display_mode *newmode;
3182 struct drm_device *dev = connector->dev;
3183 struct cvt_timing *cvt;
3184 const int rates[] = { 60, 85, 75, 60, 50 };
3185 const u8 empty[3] = { 0, 0, 0 };
a327f6b8 3186
13931579 3187 for (i = 0; i < 4; i++) {
3f649ab7 3188 int width, height;
948de842 3189
13931579 3190 cvt = &(timing->data.other_data.data.cvt[i]);
f453ba04 3191
13931579 3192 if (!memcmp(cvt->code, empty, 3))
9cf00977 3193 continue;
f453ba04 3194
13931579
AJ		 3195 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
3196 switch (cvt->code[1] & 0x0c) {
d652d5f1
LT		 3197 /* default - because compiler doesn't see that we've enumerated all cases */
3198 default:
13931579
AJ		 3199 case 0x00:
3200 width = height * 4 / 3;
3201 break;
3202 case 0x04:
3203 width = height * 16 / 9;
3204 break;
3205 case 0x08:
3206 width = height * 16 / 10;
3207 break;
3208 case 0x0c:
3209 width = height * 15 / 9;
3210 break;
3211 }
3212
3213 for (j = 1; j < 5; j++) {
3214 if (cvt->code[2] & (1 << j)) {
3215 newmode = drm_cvt_mode(dev, width, height,
3216 rates[j], j == 0,
3217 false, false);
3218 if (newmode) {
3219 drm_mode_probed_add(connector, newmode);
3220 modes++;
3221 }
3222 }
3223 }
f453ba04
DA		 3224 }
3225
3226 return modes;
3227}
9cf00977 3228
13931579
AJ		 3229static void
3230do_cvt_mode(struct detailed_timing *timing, void *c)
882f0219 3231{
13931579 3232 struct detailed_mode_closure *closure = c;
882f0219 3233
a7a131ac
VS		 3234 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_CVT_3BYTE))
3235 return;
3236
3237 closure->modes += drm_cvt_modes(closure->connector, timing);
13931579 3238}
882f0219 3239
13931579
AJ		 3240static int
3241add_cvt_modes(struct drm_connector *connector, struct edid *edid)
4d23f484 3242{
13931579 3243 struct detailed_mode_closure closure = {
d456ea2e
JL		 3244 .connector = connector,
3245 .edid = edid,
13931579 3246 };
882f0219 3247
13931579
AJ		 3248 if (version_greater(edid, 1, 2))
3249 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
882f0219 3250
13931579 3251 /* XXX should also look for CVT codes in VTB blocks */
882f0219 3252
13931579
AJ		 3253 return closure.modes;
3254}
3255
fa3a7340
VS		 3256static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
3257
13931579
AJ		 3258static void
3259do_detailed_mode(struct detailed_timing *timing, void *c)
3260{
3261 struct detailed_mode_closure *closure = c;
3262 struct drm_display_mode *newmode;
3263
f447dd1f
VS		 3264 if (!is_detailed_timing_descriptor((const u8 *)timing))
3265 return;
3266
3267 newmode = drm_mode_detailed(closure->connector->dev,
3268 closure->edid, timing,
3269 closure->quirks);
3270 if (!newmode)
3271 return;
13931579 3272
f447dd1f
VS		 3273 if (closure->preferred)
3274 newmode->type |= DRM_MODE_TYPE_PREFERRED;
13931579 3275
f447dd1f
VS		 3276 /*
3277 * Detailed modes are limited to 10kHz pixel clock resolution,
3278 * so fix up anything that looks like CEA/HDMI mode, but the clock
3279 * is just slightly off.
3280 */
3281 fixup_detailed_cea_mode_clock(newmode);
fa3a7340 3282
f447dd1f
VS		 3283 drm_mode_probed_add(closure->connector, newmode);
3284 closure->modes++;
3285 closure->preferred = false;
13931579 3286}
882f0219 3287
13931579
AJ		 3288/*
3289 * add_detailed_modes - Add modes from detailed timings
3290 * @connector: attached connector
3291 * @edid: EDID block to scan
3292 * @quirks: quirks to apply
3293 */
3294static int
3295add_detailed_modes(struct drm_connector *connector, struct edid *edid,
3296 u32 quirks)
3297{
3298 struct detailed_mode_closure closure = {
d456ea2e
JL		 3299 .connector = connector,
3300 .edid = edid,
c2925bde 3301 .preferred = true,
d456ea2e 3302 .quirks = quirks,
13931579
AJ		 3303 };
3304
3305 if (closure.preferred && !version_greater(edid, 1, 3))
3306 closure.preferred =
3307 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
3308
3309 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
3310
3311 return closure.modes;
882f0219 3312}
f453ba04 3313
8fe9790d 3314#define AUDIO_BLOCK 0x01
54ac76f8 3315#define VIDEO_BLOCK 0x02
f23c20c8 3316#define VENDOR_BLOCK 0x03
76adaa34 3317#define SPEAKER_BLOCK 0x04
e85959d6 3318#define HDR_STATIC_METADATA_BLOCK 0x6
87563fc0
SS		 3319#define USE_EXTENDED_TAG 0x07
3320#define EXT_VIDEO_CAPABILITY_BLOCK 0x00
832d4f2f
SS		 3321#define EXT_VIDEO_DATA_BLOCK_420 0x0E
3322#define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F
8fe9790d 3323#define EDID_BASIC_AUDIO (1 << 6)
a988bc72
LPC		 3324#define EDID_CEA_YCRCB444 (1 << 5)
3325#define EDID_CEA_YCRCB422 (1 << 4)
b1edd6a6 3326#define EDID_CEA_VCDB_QS (1 << 6)
8fe9790d 3327
d4e4a31d 3328/*
8fe9790d 3329 * Search EDID for CEA extension block.
f23c20c8 3330 */
4cc4f09e
JN		 3331const u8 *drm_find_edid_extension(const struct edid *edid,
3332 int ext_id, int *ext_index)
f23c20c8 3333{
43d16d84 3334 const u8 *edid_ext = NULL;
8fe9790d 3335 int i;
f23c20c8
ML		 3336
3337 /* No EDID or EDID extensions */
3338 if (edid == NULL || edid->extensions == 0)
8fe9790d 3339 return NULL;
f23c20c8 3340
f23c20c8 3341 /* Find CEA extension */
8873cfa3 3342 for (i = *ext_index; i < edid->extensions; i++) {
43d16d84 3343 edid_ext = (const u8 *)edid + EDID_LENGTH * (i + 1);
40d9b043 3344 if (edid_ext[0] == ext_id)
f23c20c8
ML		 3345 break;
3346 }
3347
8873cfa3 3348 if (i >= edid->extensions)
8fe9790d
ZW		 3349 return NULL;
3350
8873cfa3
VS		 3351 *ext_index = i + 1;
3352
8fe9790d
ZW		 3353 return edid_ext;
3354}
3355
43d16d84 3356static const u8 *drm_find_cea_extension(const struct edid *edid)
e28ad544 3357{
43d16d84 3358 const struct displayid_block *block;
1ba63caf 3359 struct displayid_iter iter;
43d16d84 3360 const u8 *cea;
1ba63caf 3361 int ext_index = 0;
e28ad544
AR		 3362
3363 /* Look for a top level CEA extension block */
7f261afd 3364 /* FIXME: make callers iterate through multiple CEA ext blocks? */
8873cfa3 3365 cea = drm_find_edid_extension(edid, CEA_EXT, &ext_index);
e28ad544
AR		 3366 if (cea)
3367 return cea;
3368
3369 /* CEA blocks can also be found embedded in a DisplayID block */
1ba63caf
JN		 3370 displayid_iter_edid_begin(edid, &iter);
3371 displayid_iter_for_each(block, &iter) {
3372 if (block->tag == DATA_BLOCK_CTA) {
3373 cea = (const u8 *)block;
3374 break;
e28ad544
AR		 3375 }
3376 }
1ba63caf 3377 displayid_iter_end(&iter);
e28ad544 3378
1ba63caf 3379 return cea;
e28ad544
AR		 3380}
3381
e1cf35b9 3382static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic)
7befe621 3383{
9212f8ee
VS		 3384 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127);
3385 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219);
3386
8c1b2bd9
VS		 3387 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1))
3388 return &edid_cea_modes_1[vic - 1];
f7655d42
VS		 3389 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193))
3390 return &edid_cea_modes_193[vic - 193];
7befe621
VS		 3391 return NULL;
3392}
3393
3394static u8 cea_num_vics(void)
3395{
f7655d42 3396 return 193 + ARRAY_SIZE(edid_cea_modes_193);
7befe621
VS		 3397}
3398
3399static u8 cea_next_vic(u8 vic)
3400{
8c1b2bd9 3401 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1))
f7655d42
VS		 3402 vic = 193;
3403 return vic;
7befe621
VS		 3404}
3405
e6e79209
VS		 3406/*
3407 * Calculate the alternate clock for the CEA mode
3408 * (60Hz vs. 59.94Hz etc.)
3409 */
3410static unsigned int
3411cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
3412{
3413 unsigned int clock = cea_mode->clock;
3414
0425662f 3415 if (drm_mode_vrefresh(cea_mode) % 6 != 0)
e6e79209
VS		 3416 return clock;
3417
3418 /*
3419 * edid_cea_modes contains the 59.94Hz
3420 * variant for 240 and 480 line modes,
3421 * and the 60Hz variant otherwise.
3422 */
3423 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
9afd808c 3424 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
e6e79209 3425 else
9afd808c 3426 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
e6e79209
VS		 3427
3428 return clock;
3429}
3430
c45a4e46
VS		 3431static bool
3432cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
3433{
3434 /*
3435 * For certain VICs the spec allows the vertical
3436 * front porch to vary by one or two lines.
3437 *
3438 * cea_modes[] stores the variant with the shortest
3439 * vertical front porch. We can adjust the mode to
3440 * get the other variants by simply increasing the
3441 * vertical front porch length.
3442 */
7befe621
VS		 3443 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 ||
3444 cea_mode_for_vic(9)->vtotal != 262 ||
3445 cea_mode_for_vic(12)->vtotal != 262 ||
3446 cea_mode_for_vic(13)->vtotal != 262 ||
3447 cea_mode_for_vic(23)->vtotal != 312 ||
3448 cea_mode_for_vic(24)->vtotal != 312 ||
3449 cea_mode_for_vic(27)->vtotal != 312 ||
3450 cea_mode_for_vic(28)->vtotal != 312);
c45a4e46
VS		 3451
3452 if (((vic == 8 || vic == 9 ||
3453 vic == 12 || vic == 13) && mode->vtotal < 263) ||
3454 ((vic == 23 || vic == 24 ||
3455 vic == 27 || vic == 28) && mode->vtotal < 314)) {
3456 mode->vsync_start++;
3457 mode->vsync_end++;
3458 mode->vtotal++;
3459
3460 return true;
3461 }
3462
3463 return false;
3464}
3465
4c6bcf44
VS		 3466static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
3467 unsigned int clock_tolerance)
3468{
357768cc 3469 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 3470 u8 vic;
4c6bcf44
VS		 3471
3472 if (!to_match->clock)
3473 return 0;
3474
357768cc
VS		 3475 if (to_match->picture_aspect_ratio)
3476 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3477
7befe621
VS		 3478 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
3479 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic);
4c6bcf44
VS		 3480 unsigned int clock1, clock2;
3481
3482 /* Check both 60Hz and 59.94Hz */
c45a4e46
VS		 3483 clock1 = cea_mode.clock;
3484 clock2 = cea_mode_alternate_clock(&cea_mode);
4c6bcf44
VS		 3485
3486 if (abs(to_match->clock - clock1) > clock_tolerance &&
3487 abs(to_match->clock - clock2) > clock_tolerance)
3488 continue;
3489
c45a4e46 3490 do {
357768cc 3491 if (drm_mode_match(to_match, &cea_mode, match_flags))
c45a4e46
VS		 3492 return vic;
3493 } while (cea_mode_alternate_timings(vic, &cea_mode));
4c6bcf44
VS		 3494 }
3495
3496 return 0;
3497}
3498
18316c8c
TR		 3499/**
3500 * drm_match_cea_mode - look for a CEA mode matching given mode
3501 * @to_match: display mode
3502 *
db6cf833 3503 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
18316c8c 3504 * mode.
a4799037 3505 */
18316c8c 3506u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
a4799037 3507{
357768cc 3508 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 3509 u8 vic;
a4799037 3510
a90b590e
VS		 3511 if (!to_match->clock)
3512 return 0;
3513
357768cc
VS		 3514 if (to_match->picture_aspect_ratio)
3515 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3516
7befe621
VS		 3517 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
3518 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic);
a90b590e
VS		 3519 unsigned int clock1, clock2;
3520
a90b590e 3521 /* Check both 60Hz and 59.94Hz */
c45a4e46
VS		 3522 clock1 = cea_mode.clock;
3523 clock2 = cea_mode_alternate_clock(&cea_mode);
a4799037 3524
c45a4e46
VS		 3525 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
3526 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
3527 continue;
3528
3529 do {
357768cc 3530 if (drm_mode_match(to_match, &cea_mode, match_flags))
c45a4e46
VS		 3531 return vic;
3532 } while (cea_mode_alternate_timings(vic, &cea_mode));
a4799037 3533 }
c45a4e46 3534
a4799037
SM		 3535 return 0;
3536}
3537EXPORT_SYMBOL(drm_match_cea_mode);
3538
d9278b4c
JN		 3539static bool drm_valid_cea_vic(u8 vic)
3540{
7befe621 3541 return cea_mode_for_vic(vic) != NULL;
d9278b4c
JN		 3542}
3543
28c03a44 3544static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
0967e6a5 3545{
7befe621
VS		 3546 const struct drm_display_mode *mode = cea_mode_for_vic(video_code);
3547
3548 if (mode)
3549 return mode->picture_aspect_ratio;
3550
3551 return HDMI_PICTURE_ASPECT_NONE;
0967e6a5 3552}
0967e6a5 3553
d2b43473
WL		 3554static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code)
3555{
3556 return edid_4k_modes[video_code].picture_aspect_ratio;
3557}
3558
3f2f6533
LD		 3559/*
3560 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
3561 * specific block).
3f2f6533
LD		 3562 */
3563static unsigned int
3564hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
3565{
3f2f6533
LD		 3566 return cea_mode_alternate_clock(hdmi_mode);
3567}
3568
4c6bcf44
VS		 3569static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
3570 unsigned int clock_tolerance)
3571{
357768cc 3572 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 3573 u8 vic;
4c6bcf44
VS		 3574
3575 if (!to_match->clock)
3576 return 0;
3577
d2b43473
WL		 3578 if (to_match->picture_aspect_ratio)
3579 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3580
d9278b4c
JN		 3581 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3582 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4c6bcf44
VS		 3583 unsigned int clock1, clock2;
3584
3585 /* Make sure to also match alternate clocks */
3586 clock1 = hdmi_mode->clock;
3587 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3588
3589 if (abs(to_match->clock - clock1) > clock_tolerance &&
3590 abs(to_match->clock - clock2) > clock_tolerance)
3591 continue;
3592
357768cc 3593 if (drm_mode_match(to_match, hdmi_mode, match_flags))
d9278b4c 3594 return vic;
4c6bcf44
VS		 3595 }
3596
3597 return 0;
3598}
3599
3f2f6533
LD		 3600/*
3601 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
3602 * @to_match: display mode
3603 *
3604 * An HDMI mode is one defined in the HDMI vendor specific block.
3605 *
3606 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
3607 */
3608static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
3609{
357768cc 3610 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 3611 u8 vic;
3f2f6533
LD		 3612
3613 if (!to_match->clock)
3614 return 0;
3615
d2b43473
WL		 3616 if (to_match->picture_aspect_ratio)
3617 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3618
d9278b4c
JN		 3619 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3620 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3f2f6533
LD		 3621 unsigned int clock1, clock2;
3622
3623 /* Make sure to also match alternate clocks */
3624 clock1 = hdmi_mode->clock;
3625 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3626
3627 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
3628 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
357768cc 3629 drm_mode_match(to_match, hdmi_mode, match_flags))
d9278b4c 3630 return vic;
3f2f6533
LD		 3631 }
3632 return 0;
3633}
3634
d9278b4c
JN		 3635static bool drm_valid_hdmi_vic(u8 vic)
3636{
3637 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
3638}
3639
e6e79209
VS		 3640static int
3641add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
3642{
3643 struct drm_device *dev = connector->dev;
3644 struct drm_display_mode *mode, *tmp;
3645 LIST_HEAD(list);
3646 int modes = 0;
3647
3648 /* Don't add CEA modes if the CEA extension block is missing */
3649 if (!drm_find_cea_extension(edid))
3650 return 0;
3651
3652 /*
3653 * Go through all probed modes and create a new mode
3654 * with the alternate clock for certain CEA modes.
3655 */
3656 list_for_each_entry(mode, &connector->probed_modes, head) {
3f2f6533 3657 const struct drm_display_mode *cea_mode = NULL;
e6e79209 3658 struct drm_display_mode *newmode;
d9278b4c 3659 u8 vic = drm_match_cea_mode(mode);
e6e79209
VS		 3660 unsigned int clock1, clock2;
3661
d9278b4c 3662 if (drm_valid_cea_vic(vic)) {
7befe621 3663 cea_mode = cea_mode_for_vic(vic);
3f2f6533
LD		 3664 clock2 = cea_mode_alternate_clock(cea_mode);
3665 } else {
d9278b4c
JN		 3666 vic = drm_match_hdmi_mode(mode);
3667 if (drm_valid_hdmi_vic(vic)) {
3668 cea_mode = &edid_4k_modes[vic];
3f2f6533
LD		 3669 clock2 = hdmi_mode_alternate_clock(cea_mode);
3670 }
3671 }
e6e79209 3672
3f2f6533
LD		 3673 if (!cea_mode)
3674 continue;
e6e79209
VS		 3675
3676 clock1 = cea_mode->clock;
e6e79209
VS		 3677
3678 if (clock1 == clock2)
3679 continue;
3680
3681 if (mode->clock != clock1 && mode->clock != clock2)
3682 continue;
3683
3684 newmode = drm_mode_duplicate(dev, cea_mode);
3685 if (!newmode)
3686 continue;
3687
27130212
DL		 3688 /* Carry over the stereo flags */
3689 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
3690
e6e79209
VS		 3691 /*
3692 * The current mode could be either variant. Make
3693 * sure to pick the "other" clock for the new mode.
3694 */
3695 if (mode->clock != clock1)
3696 newmode->clock = clock1;
3697 else
3698 newmode->clock = clock2;
3699
3700 list_add_tail(&newmode->head, &list);
3701 }
3702
3703 list_for_each_entry_safe(mode, tmp, &list, head) {
3704 list_del(&mode->head);
3705 drm_mode_probed_add(connector, mode);
3706 modes++;
3707 }
3708
3709 return modes;
3710}
a4799037 3711
8ec6e075
SS		 3712static u8 svd_to_vic(u8 svd)
3713{
3714 /* 0-6 bit vic, 7th bit native mode indicator */
3715 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
3716 return svd & 127;
3717
3718 return svd;
3719}
3720
aff04ace
TW		 3721static struct drm_display_mode *
3722drm_display_mode_from_vic_index(struct drm_connector *connector,
3723 const u8 *video_db, u8 video_len,
3724 u8 video_index)
54ac76f8
CS		 3725{
3726 struct drm_device *dev = connector->dev;
aff04ace 3727 struct drm_display_mode *newmode;
d9278b4c 3728 u8 vic;
54ac76f8 3729
aff04ace
TW		 3730 if (video_db == NULL || video_index >= video_len)
3731 return NULL;
3732
3733 /* CEA modes are numbered 1..127 */
8ec6e075 3734 vic = svd_to_vic(video_db[video_index]);
d9278b4c 3735 if (!drm_valid_cea_vic(vic))
aff04ace
TW		 3736 return NULL;
3737
7befe621 3738 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
409bbf1e
DL		 3739 if (!newmode)
3740 return NULL;
3741
aff04ace
TW		 3742 return newmode;
3743}
3744
832d4f2f
SS		 3745/*
3746 * do_y420vdb_modes - Parse YCBCR 420 only modes
3747 * @connector: connector corresponding to the HDMI sink
3748 * @svds: start of the data block of CEA YCBCR 420 VDB
3749 * @len: length of the CEA YCBCR 420 VDB
3750 *
3751 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
3752 * which contains modes which can be supported in YCBCR 420
3753 * output format only.
3754 */
3755static int do_y420vdb_modes(struct drm_connector *connector,
3756 const u8 *svds, u8 svds_len)
3757{
3758 int modes = 0, i;
3759 struct drm_device *dev = connector->dev;
3760 struct drm_display_info *info = &connector->display_info;
3761 struct drm_hdmi_info *hdmi = &info->hdmi;
3762
3763 for (i = 0; i < svds_len; i++) {
3764 u8 vic = svd_to_vic(svds[i]);
3765 struct drm_display_mode *newmode;
3766
3767 if (!drm_valid_cea_vic(vic))
3768 continue;
3769
7befe621 3770 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
832d4f2f
SS		 3771 if (!newmode)
3772 break;
3773 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
3774 drm_mode_probed_add(connector, newmode);
3775 modes++;
3776 }
3777
3778 if (modes > 0)
3779 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3780 return modes;
3781}
3782
3783/*
3784 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap
3785 * @connector: connector corresponding to the HDMI sink
3786 * @vic: CEA vic for the video mode to be added in the map
3787 *
3788 * Makes an entry for a videomode in the YCBCR 420 bitmap
3789 */
3790static void
3791drm_add_cmdb_modes(struct drm_connector *connector, u8 svd)
3792{
3793 u8 vic = svd_to_vic(svd);
3794 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3795
3796 if (!drm_valid_cea_vic(vic))
3797 return;
3798
3799 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
3800}
3801
7af655bc
VS		 3802/**
3803 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC
3804 * @dev: DRM device
8d7d8c0a 3805 * @video_code: CEA VIC of the mode
7af655bc
VS		 3806 *
3807 * Creates a new mode matching the specified CEA VIC.
3808 *
3809 * Returns: A new drm_display_mode on success or NULL on failure
3810 */
3811struct drm_display_mode *
3812drm_display_mode_from_cea_vic(struct drm_device *dev,
3813 u8 video_code)
3814{
3815 const struct drm_display_mode *cea_mode;
3816 struct drm_display_mode *newmode;
3817
3818 cea_mode = cea_mode_for_vic(video_code);
3819 if (!cea_mode)
3820 return NULL;
3821
3822 newmode = drm_mode_duplicate(dev, cea_mode);
3823 if (!newmode)
3824 return NULL;
3825
3826 return newmode;
3827}
3828EXPORT_SYMBOL(drm_display_mode_from_cea_vic);
3829
aff04ace
TW		 3830static int
3831do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
3832{
3833 int i, modes = 0;
832d4f2f 3834 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
aff04ace
TW		 3835
3836 for (i = 0; i < len; i++) {
3837 struct drm_display_mode *mode;
948de842 3838
aff04ace
TW		 3839 mode = drm_display_mode_from_vic_index(connector, db, len, i);
3840 if (mode) {
832d4f2f
SS		 3841 /*
3842 * YCBCR420 capability block contains a bitmap which
3843 * gives the index of CEA modes from CEA VDB, which
3844 * can support YCBCR 420 sampling output also (apart
3845 * from RGB/YCBCR444 etc).
3846 * For example, if the bit 0 in bitmap is set,
3847 * first mode in VDB can support YCBCR420 output too.
3848 * Add YCBCR420 modes only if sink is HDMI 2.0 capable.
3849 */
3850 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i))
3851 drm_add_cmdb_modes(connector, db[i]);
3852
aff04ace
TW		 3853 drm_mode_probed_add(connector, mode);
3854 modes++;
54ac76f8
CS		 3855 }
3856 }
3857
3858 return modes;
3859}
3860
c858cfca
DL		 3861struct stereo_mandatory_mode {
3862 int width, height, vrefresh;
3863 unsigned int flags;
3864};
3865
3866static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
f7e121b7
DL		 3867 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3868 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
c858cfca
DL		 3869 { 1920, 1080, 50,
3870 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3871 { 1920, 1080, 60,
3872 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
f7e121b7
DL		 3873 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3874 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
3875 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3876 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
c858cfca
DL		 3877};
3878
3879static bool
3880stereo_match_mandatory(const struct drm_display_mode *mode,
3881 const struct stereo_mandatory_mode *stereo_mode)
3882{
3883 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
3884
3885 return mode->hdisplay == stereo_mode->width &&
3886 mode->vdisplay == stereo_mode->height &&
3887 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
3888 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
3889}
3890
c858cfca
DL		 3891static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
3892{
3893 struct drm_device *dev = connector->dev;
3894 const struct drm_display_mode *mode;
3895 struct list_head stereo_modes;
f7e121b7 3896 int modes = 0, i;
c858cfca
DL		 3897
3898 INIT_LIST_HEAD(&stereo_modes);
3899
3900 list_for_each_entry(mode, &connector->probed_modes, head) {
f7e121b7
DL		 3901 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
3902 const struct stereo_mandatory_mode *mandatory;
c858cfca
DL		 3903 struct drm_display_mode *new_mode;
3904
f7e121b7
DL		 3905 if (!stereo_match_mandatory(mode,
3906 &stereo_mandatory_modes[i]))
3907 continue;
c858cfca 3908
f7e121b7 3909 mandatory = &stereo_mandatory_modes[i];
c858cfca
DL		 3910 new_mode = drm_mode_duplicate(dev, mode);
3911 if (!new_mode)
3912 continue;
3913
f7e121b7 3914 new_mode->flags |= mandatory->flags;
c858cfca
DL		 3915 list_add_tail(&new_mode->head, &stereo_modes);
3916 modes++;
f7e121b7 3917 }
c858cfca
DL		 3918 }
3919
3920 list_splice_tail(&stereo_modes, &connector->probed_modes);
3921
3922 return modes;
3923}
3924
1deee8d7
DL		 3925static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
3926{
3927 struct drm_device *dev = connector->dev;
3928 struct drm_display_mode *newmode;
3929
d9278b4c 3930 if (!drm_valid_hdmi_vic(vic)) {
1deee8d7
DL		 3931 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
3932 return 0;
3933 }
3934
3935 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
3936 if (!newmode)
3937 return 0;
3938
3939 drm_mode_probed_add(connector, newmode);
3940
3941 return 1;
3942}
3943
fbf46025
TW		 3944static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
3945 const u8 *video_db, u8 video_len, u8 video_index)
3946{
fbf46025
TW		 3947 struct drm_display_mode *newmode;
3948 int modes = 0;
fbf46025
TW		 3949
3950 if (structure & (1 << 0)) {
aff04ace
TW		 3951 newmode = drm_display_mode_from_vic_index(connector, video_db,
3952 video_len,
3953 video_index);
fbf46025
TW		 3954 if (newmode) {
3955 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
3956 drm_mode_probed_add(connector, newmode);
3957 modes++;
3958 }
3959 }
3960 if (structure & (1 << 6)) {
aff04ace
TW		 3961 newmode = drm_display_mode_from_vic_index(connector, video_db,
3962 video_len,
3963 video_index);
fbf46025
TW		 3964 if (newmode) {
3965 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3966 drm_mode_probed_add(connector, newmode);
3967 modes++;
3968 }
3969 }
3970 if (structure & (1 << 8)) {
aff04ace
TW		 3971 newmode = drm_display_mode_from_vic_index(connector, video_db,
3972 video_len,
3973 video_index);
fbf46025 3974 if (newmode) {
89570eeb 3975 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
fbf46025
TW		 3976 drm_mode_probed_add(connector, newmode);
3977 modes++;
3978 }
3979 }
3980
3981 return modes;
3982}
3983
7ebe1963
LD		 3984/*
3985 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
3986 * @connector: connector corresponding to the HDMI sink
3987 * @db: start of the CEA vendor specific block
3988 * @len: length of the CEA block payload, ie. one can access up to db[len]
3989 *
c858cfca
DL		 3990 * Parses the HDMI VSDB looking for modes to add to @connector. This function
3991 * also adds the stereo 3d modes when applicable.
7ebe1963
LD		 3992 */
3993static int
fbf46025
TW		 3994do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
3995 const u8 *video_db, u8 video_len)
7ebe1963 3996{
f1781e9b 3997 struct drm_display_info *info = &connector->display_info;
0e5083aa 3998 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
fbf46025
TW		 3999 u8 vic_len, hdmi_3d_len = 0;
4000 u16 mask;
4001 u16 structure_all;
7ebe1963
LD		 4002
4003 if (len < 8)
4004 goto out;
4005
4006 /* no HDMI_Video_Present */
4007 if (!(db[8] & (1 << 5)))
4008 goto out;
4009
4010 /* Latency_Fields_Present */
4011 if (db[8] & (1 << 7))
4012 offset += 2;
4013
4014 /* I_Latency_Fields_Present */
4015 if (db[8] & (1 << 6))
4016 offset += 2;
4017
4018 /* the declared length is not long enough for the 2 first bytes
4019 * of additional video format capabilities */
c858cfca 4020 if (len < (8 + offset + 2))
7ebe1963
LD		 4021 goto out;
4022
c858cfca
DL		 4023 /* 3D_Present */
4024 offset++;
fbf46025 4025 if (db[8 + offset] & (1 << 7)) {
c858cfca
DL		 4026 modes += add_hdmi_mandatory_stereo_modes(connector);
4027
fbf46025
TW		 4028 /* 3D_Multi_present */
4029 multi_present = (db[8 + offset] & 0x60) >> 5;
4030 }
4031
c858cfca 4032 offset++;
7ebe1963 4033 vic_len = db[8 + offset] >> 5;
fbf46025 4034 hdmi_3d_len = db[8 + offset] & 0x1f;
7ebe1963
LD		 4035
4036 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
7ebe1963
LD		 4037 u8 vic;
4038
4039 vic = db[9 + offset + i];
1deee8d7 4040 modes += add_hdmi_mode(connector, vic);
7ebe1963 4041 }
fbf46025
TW		 4042 offset += 1 + vic_len;
4043
0e5083aa
TW		 4044 if (multi_present == 1)
4045 multi_len = 2;
4046 else if (multi_present == 2)
4047 multi_len = 4;
4048 else
4049 multi_len = 0;
fbf46025 4050
0e5083aa 4051 if (len < (8 + offset + hdmi_3d_len - 1))
fbf46025
TW		 4052 goto out;
4053
0e5083aa 4054 if (hdmi_3d_len < multi_len)
fbf46025
TW		 4055 goto out;
4056
0e5083aa
TW		 4057 if (multi_present == 1 || multi_present == 2) {
4058 /* 3D_Structure_ALL */
4059 structure_all = (db[8 + offset] << 8) | db[9 + offset];
fbf46025 4060
0e5083aa
TW		 4061 /* check if 3D_MASK is present */
4062 if (multi_present == 2)
4063 mask = (db[10 + offset] << 8) | db[11 + offset];
4064 else
4065 mask = 0xffff;
4066
4067 for (i = 0; i < 16; i++) {
4068 if (mask & (1 << i))
4069 modes += add_3d_struct_modes(connector,
4070 structure_all,
4071 video_db,
4072 video_len, i);
4073 }
4074 }
4075
4076 offset += multi_len;
4077
4078 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
4079 int vic_index;
4080 struct drm_display_mode *newmode = NULL;
4081 unsigned int newflag = 0;
4082 bool detail_present;
4083
4084 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
4085
4086 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
4087 break;
4088
4089 /* 2D_VIC_order_X */
4090 vic_index = db[8 + offset + i] >> 4;
4091
4092 /* 3D_Structure_X */
4093 switch (db[8 + offset + i] & 0x0f) {
4094 case 0:
4095 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
4096 break;
4097 case 6:
4098 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4099 break;
4100 case 8:
4101 /* 3D_Detail_X */
4102 if ((db[9 + offset + i] >> 4) == 1)
4103 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4104 break;
4105 }
4106
4107 if (newflag != 0) {
4108 newmode = drm_display_mode_from_vic_index(connector,
4109 video_db,
4110 video_len,
4111 vic_index);
4112
4113 if (newmode) {
4114 newmode->flags |= newflag;
4115 drm_mode_probed_add(connector, newmode);
4116 modes++;
4117 }
4118 }
4119
4120 if (detail_present)
4121 i++;
fbf46025 4122 }
7ebe1963
LD		 4123
4124out:
f1781e9b
VS		 4125 if (modes > 0)
4126 info->has_hdmi_infoframe = true;
7ebe1963
LD		 4127 return modes;
4128}
4129
9e50b9d5
VS		 4130static int
4131cea_db_payload_len(const u8 *db)
4132{
4133 return db[0] & 0x1f;
4134}
4135
87563fc0
SS		 4136static int
4137cea_db_extended_tag(const u8 *db)
4138{
4139 return db[1];
4140}
4141
9e50b9d5
VS		 4142static int
4143cea_db_tag(const u8 *db)
4144{
4145 return db[0] >> 5;
4146}
4147
4148static int
4149cea_revision(const u8 *cea)
4150{
5036c0d0
VS		 4151 /*
4152 * FIXME is this correct for the DispID variant?
4153 * The DispID spec doesn't really specify whether
4154 * this is the revision of the CEA extension or
4155 * the DispID CEA data block. And the only value
4156 * given as an example is 0.
4157 */
9e50b9d5
VS		 4158 return cea[1];
4159}
4160
4161static int
4162cea_db_offsets(const u8 *cea, int *start, int *end)
4163{
e28ad544
AR		 4164 /* DisplayID CTA extension blocks and top-level CEA EDID
4165 * block header definitions differ in the following bytes:
4166 * 1) Byte 2 of the header specifies length differently,
4167 * 2) Byte 3 is only present in the CEA top level block.
4168 *
4169 * The different definitions for byte 2 follow.
4170 *
4171 * DisplayID CTA extension block defines byte 2 as:
4172 * Number of payload bytes
4173 *
4174 * CEA EDID block defines byte 2 as:
4175 * Byte number (decimal) within this block where the 18-byte
4176 * DTDs begin. If no non-DTD data is present in this extension
4177 * block, the value should be set to 04h (the byte after next).
4178 * If set to 00h, there are no DTDs present in this block and
4179 * no non-DTD data.
4180 */
4181 if (cea[0] == DATA_BLOCK_CTA) {
6e8a942b
VS		 4182 /*
4183 * for_each_displayid_db() has already verified
4184 * that these stay within expected bounds.
4185 */
e28ad544
AR		 4186 *start = 3;
4187 *end = *start + cea[2];
4188 } else if (cea[0] == CEA_EXT) {
4189 /* Data block offset in CEA extension block */
4190 *start = 4;
4191 *end = cea[2];
4192 if (*end == 0)
4193 *end = 127;
4194 if (*end < 4 || *end > 127)
4195 return -ERANGE;
4196 } else {
c7581a41 4197 return -EOPNOTSUPP;
e28ad544
AR		 4198 }
4199
9e50b9d5
VS		 4200 return 0;
4201}
4202
7ebe1963
LD		 4203static bool cea_db_is_hdmi_vsdb(const u8 *db)
4204{
7ebe1963
LD		 4205 if (cea_db_tag(db) != VENDOR_BLOCK)
4206 return false;
4207
4208 if (cea_db_payload_len(db) < 5)
4209 return false;
4210
37eab1fe 4211 return oui(db[3], db[2], db[1]) == HDMI_IEEE_OUI;
7ebe1963
LD		 4212}
4213
50dd1bd1
TR		 4214static bool cea_db_is_hdmi_forum_vsdb(const u8 *db)
4215{
50dd1bd1
TR		 4216 if (cea_db_tag(db) != VENDOR_BLOCK)
4217 return false;
4218
4219 if (cea_db_payload_len(db) < 7)
4220 return false;
4221
37eab1fe 4222 return oui(db[3], db[2], db[1]) == HDMI_FORUM_IEEE_OUI;
50dd1bd1
TR		 4223}
4224
2869f599
PZ		 4225static bool cea_db_is_microsoft_vsdb(const u8 *db)
4226{
4227 if (cea_db_tag(db) != VENDOR_BLOCK)
4228 return false;
4229
4230 if (cea_db_payload_len(db) != 21)
4231 return false;
4232
4233 return oui(db[3], db[2], db[1]) == MICROSOFT_IEEE_OUI;
4234}
4235
1581b2df
VS		 4236static bool cea_db_is_vcdb(const u8 *db)
4237{
4238 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4239 return false;
4240
4241 if (cea_db_payload_len(db) != 2)
4242 return false;
4243
4244 if (cea_db_extended_tag(db) != EXT_VIDEO_CAPABILITY_BLOCK)
4245 return false;
4246
4247 return true;
4248}
4249
832d4f2f
SS		 4250static bool cea_db_is_y420cmdb(const u8 *db)
4251{
4252 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4253 return false;
4254
4255 if (!cea_db_payload_len(db))
4256 return false;
4257
4258 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB)
4259 return false;
4260
4261 return true;
4262}
4263
4264static bool cea_db_is_y420vdb(const u8 *db)
4265{
4266 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4267 return false;
4268
4269 if (!cea_db_payload_len(db))
4270 return false;
4271
4272 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420)
4273 return false;
4274
4275 return true;
4276}
4277
9e50b9d5
VS		 4278#define for_each_cea_db(cea, i, start, end) \
4279 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
4280
832d4f2f
SS		 4281static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector,
4282 const u8 *db)
4283{
4284 struct drm_display_info *info = &connector->display_info;
4285 struct drm_hdmi_info *hdmi = &info->hdmi;
4286 u8 map_len = cea_db_payload_len(db) - 1;
4287 u8 count;
4288 u64 map = 0;
4289
4290 if (map_len == 0) {
4291 /* All CEA modes support ycbcr420 sampling also.*/
4292 hdmi->y420_cmdb_map = U64_MAX;
4293 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
4294 return;
4295 }
4296
4297 /*
4298 * This map indicates which of the existing CEA block modes
4299 * from VDB can support YCBCR420 output too. So if bit=0 is
4300 * set, first mode from VDB can support YCBCR420 output too.
4301 * We will parse and keep this map, before parsing VDB itself
4302 * to avoid going through the same block again and again.
4303 *
4304 * Spec is not clear about max possible size of this block.
4305 * Clamping max bitmap block size at 8 bytes. Every byte can
4306 * address 8 CEA modes, in this way this map can address
4307 * 8*8 = first 64 SVDs.
4308 */
4309 if (WARN_ON_ONCE(map_len > 8))
4310 map_len = 8;
4311
4312 for (count = 0; count < map_len; count++)
4313 map |= (u64)db[2 + count] << (8 * count);
4314
4315 if (map)
4316 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
4317
4318 hdmi->y420_cmdb_map = map;
4319}
4320
54ac76f8
CS		 4321static int
4322add_cea_modes(struct drm_connector *connector, struct edid *edid)
4323{
13ac3f55 4324 const u8 *cea = drm_find_cea_extension(edid);
fbf46025
TW		 4325 const u8 *db, *hdmi = NULL, *video = NULL;
4326 u8 dbl, hdmi_len, video_len = 0;
54ac76f8
CS		 4327 int modes = 0;
4328
9e50b9d5
VS		 4329 if (cea && cea_revision(cea) >= 3) {
4330 int i, start, end;
4331
4332 if (cea_db_offsets(cea, &start, &end))
4333 return 0;
4334
4335 for_each_cea_db(cea, i, start, end) {
4336 db = &cea[i];
4337 dbl = cea_db_payload_len(db);
4338
fbf46025
TW		 4339 if (cea_db_tag(db) == VIDEO_BLOCK) {
4340 video = db + 1;
4341 video_len = dbl;
4342 modes += do_cea_modes(connector, video, dbl);
832d4f2f 4343 } else if (cea_db_is_hdmi_vsdb(db)) {
c858cfca
DL		 4344 hdmi = db;
4345 hdmi_len = dbl;
832d4f2f
SS		 4346 } else if (cea_db_is_y420vdb(db)) {
4347 const u8 *vdb420 = &db[2];
4348
4349 /* Add 4:2:0(only) modes present in EDID */
4350 modes += do_y420vdb_modes(connector,
4351 vdb420,
4352 dbl - 1);
c858cfca 4353 }
54ac76f8
CS		 4354 }
4355 }
4356
c858cfca
DL		 4357 /*
4358 * We parse the HDMI VSDB after having added the cea modes as we will
4359 * be patching their flags when the sink supports stereo 3D.
4360 */
4361 if (hdmi)
fbf46025
TW		 4362 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
4363 video_len);
c858cfca 4364
54ac76f8
CS		 4365 return modes;
4366}
4367
fa3a7340
VS		 4368static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
4369{
4370 const struct drm_display_mode *cea_mode;
4371 int clock1, clock2, clock;
d9278b4c 4372 u8 vic;
fa3a7340
VS		 4373 const char *type;
4374
4c6bcf44
VS		 4375 /*
4376 * allow 5kHz clock difference either way to account for
4377 * the 10kHz clock resolution limit of detailed timings.
4378 */
d9278b4c
JN		 4379 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
4380 if (drm_valid_cea_vic(vic)) {
fa3a7340 4381 type = "CEA";
7befe621 4382 cea_mode = cea_mode_for_vic(vic);
fa3a7340
VS		 4383 clock1 = cea_mode->clock;
4384 clock2 = cea_mode_alternate_clock(cea_mode);
4385 } else {
d9278b4c
JN		 4386 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
4387 if (drm_valid_hdmi_vic(vic)) {
fa3a7340 4388 type = "HDMI";
d9278b4c 4389 cea_mode = &edid_4k_modes[vic];
fa3a7340
VS		 4390 clock1 = cea_mode->clock;
4391 clock2 = hdmi_mode_alternate_clock(cea_mode);
4392 } else {
4393 return;
4394 }
4395 }
4396
4397 /* pick whichever is closest */
4398 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
4399 clock = clock1;
4400 else
4401 clock = clock2;
4402
4403 if (mode->clock == clock)
4404 return;
4405
4406 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
d9278b4c 4407 type, vic, mode->clock, clock);
fa3a7340
VS		 4408 mode->clock = clock;
4409}
4410
e85959d6
US		 4411static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db)
4412{
4413 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4414 return false;
4415
4416 if (db[1] != HDR_STATIC_METADATA_BLOCK)
4417 return false;
4418
4419 if (cea_db_payload_len(db) < 3)
4420 return false;
4421
4422 return true;
4423}
4424
4425static uint8_t eotf_supported(const u8 *edid_ext)
4426{
4427 return edid_ext[2] &
4428 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
4429 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
b5e3eed1
VS		 4430 BIT(HDMI_EOTF_SMPTE_ST2084) |
4431 BIT(HDMI_EOTF_BT_2100_HLG));
e85959d6
US		 4432}
4433
4434static uint8_t hdr_metadata_type(const u8 *edid_ext)
4435{
4436 return edid_ext[3] &
4437 BIT(HDMI_STATIC_METADATA_TYPE1);
4438}
4439
4440static void
4441drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
4442{
4443 u16 len;
4444
4445 len = cea_db_payload_len(db);
4446
4447 connector->hdr_sink_metadata.hdmi_type1.eotf =
4448 eotf_supported(db);
4449 connector->hdr_sink_metadata.hdmi_type1.metadata_type =
4450 hdr_metadata_type(db);
4451
4452 if (len >= 4)
4453 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4];
4454 if (len >= 5)
4455 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5];
4456 if (len >= 6)
4457 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6];
4458}
4459
76adaa34 4460static void
23ebf8b9 4461drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
76adaa34 4462{
8504072a 4463 u8 len = cea_db_payload_len(db);
76adaa34 4464
f7da7785
JN		 4465 if (len >= 6 && (db[6] & (1 << 7)))
4466 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
8504072a
VS		 4467 if (len >= 8) {
4468 connector->latency_present[0] = db[8] >> 7;
4469 connector->latency_present[1] = (db[8] >> 6) & 1;
4470 }
4471 if (len >= 9)
4472 connector->video_latency[0] = db[9];
4473 if (len >= 10)
4474 connector->audio_latency[0] = db[10];
4475 if (len >= 11)
4476 connector->video_latency[1] = db[11];
4477 if (len >= 12)
4478 connector->audio_latency[1] = db[12];
76adaa34 4479
23ebf8b9
VS		 4480 DRM_DEBUG_KMS("HDMI: latency present %d %d, "
4481 "video latency %d %d, "
4482 "audio latency %d %d\n",
4483 connector->latency_present[0],
4484 connector->latency_present[1],
4485 connector->video_latency[0],
4486 connector->video_latency[1],
4487 connector->audio_latency[0],
4488 connector->audio_latency[1]);
76adaa34
WF		 4489}
4490
4491static void
4492monitor_name(struct detailed_timing *t, void *data)
4493{
a7a131ac
VS		 4494 if (!is_display_descriptor((const u8 *)t, EDID_DETAIL_MONITOR_NAME))
4495 return;
4496
4497 *(u8 **)data = t->data.other_data.data.str.str;
14f77fdd
VS		 4498}
4499
59f7c0fa
JB		 4500static int get_monitor_name(struct edid *edid, char name[13])
4501{
4502 char *edid_name = NULL;
4503 int mnl;
4504
4505 if (!edid || !name)
4506 return 0;
4507
4508 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name);
4509 for (mnl = 0; edid_name && mnl < 13; mnl++) {
4510 if (edid_name[mnl] == 0x0a)
4511 break;
4512
4513 name[mnl] = edid_name[mnl];
4514 }
4515
4516 return mnl;
4517}
4518
4519/**
4520 * drm_edid_get_monitor_name - fetch the monitor name from the edid
4521 * @edid: monitor EDID information
4522 * @name: pointer to a character array to hold the name of the monitor
4523 * @bufsize: The size of the name buffer (should be at least 14 chars.)
4524 *
4525 */
4526void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize)
4527{
4528 int name_length;
4529 char buf[13];
4d23f484 4530
59f7c0fa
JB		 4531 if (bufsize <= 0)
4532 return;
4533
4534 name_length = min(get_monitor_name(edid, buf), bufsize - 1);
4535 memcpy(name, buf, name_length);
4536 name[name_length] = '\0';
4537}
4538EXPORT_SYMBOL(drm_edid_get_monitor_name);
4539
42750d39
JN		 4540static void clear_eld(struct drm_connector *connector)
4541{
4542 memset(connector->eld, 0, sizeof(connector->eld));
4543
4544 connector->latency_present[0] = false;
4545 connector->latency_present[1] = false;
4546 connector->video_latency[0] = 0;
4547 connector->audio_latency[0] = 0;
4548 connector->video_latency[1] = 0;
4549 connector->audio_latency[1] = 0;
4550}
4551
79436a1c 4552/*
76adaa34
WF		 4553 * drm_edid_to_eld - build ELD from EDID
4554 * @connector: connector corresponding to the HDMI/DP sink
4555 * @edid: EDID to parse
4556 *
db6cf833 4557 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
1d1c3665 4558 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
76adaa34 4559 */
79436a1c 4560static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
76adaa34
WF		 4561{
4562 uint8_t *eld = connector->eld;
43d16d84
JN		 4563 const u8 *cea;
4564 const u8 *db;
7c018782 4565 int total_sad_count = 0;
76adaa34
WF		 4566 int mnl;
4567 int dbl;
4568
42750d39 4569 clear_eld(connector);
85c91580 4570
e9bd0b84
JN		 4571 if (!edid)
4572 return;
4573
76adaa34
WF		 4574 cea = drm_find_cea_extension(edid);
4575 if (!cea) {
4576 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
4577 return;
4578 }
4579
f7da7785
JN		 4580 mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
4581 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]);
59f7c0fa 4582
f7da7785
JN		 4583 eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT;
4584 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
76adaa34 4585
f7da7785 4586 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
76adaa34 4587
f7da7785
JN		 4588 eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0];
4589 eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1];
4590 eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0];
4591 eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1];
76adaa34 4592
9e50b9d5
VS		 4593 if (cea_revision(cea) >= 3) {
4594 int i, start, end;
deec222e 4595 int sad_count;
9e50b9d5
VS		 4596
4597 if (cea_db_offsets(cea, &start, &end)) {
4598 start = 0;
4599 end = 0;
4600 }
4601
4602 for_each_cea_db(cea, i, start, end) {
4603 db = &cea[i];
4604 dbl = cea_db_payload_len(db);
4605
4606 switch (cea_db_tag(db)) {
a0ab734d
CS		 4607 case AUDIO_BLOCK:
4608 /* Audio Data Block, contains SADs */
7c018782
VS		 4609 sad_count = min(dbl / 3, 15 - total_sad_count);
4610 if (sad_count >= 1)
f7da7785 4611 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
7c018782
VS		 4612 &db[1], sad_count * 3);
4613 total_sad_count += sad_count;
a0ab734d
CS		 4614 break;
4615 case SPEAKER_BLOCK:
9e50b9d5
VS		 4616 /* Speaker Allocation Data Block */
4617 if (dbl >= 1)
f7da7785 4618 eld[DRM_ELD_SPEAKER] = db[1];
a0ab734d
CS		 4619 break;
4620 case VENDOR_BLOCK:
4621 /* HDMI Vendor-Specific Data Block */
14f77fdd 4622 if (cea_db_is_hdmi_vsdb(db))
23ebf8b9 4623 drm_parse_hdmi_vsdb_audio(connector, db);
a0ab734d
CS		 4624 break;
4625 default:
4626 break;
4627 }
76adaa34 4628 }
9e50b9d5 4629 }
f7da7785 4630 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
76adaa34 4631
1d1c3665
JN		 4632 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
4633 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4634 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
4635 else
4636 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
76adaa34 4637
938fd8aa
JN		 4638 eld[DRM_ELD_BASELINE_ELD_LEN] =
4639 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
4640
4641 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
7c018782 4642 drm_eld_size(eld), total_sad_count);
76adaa34 4643}
76adaa34 4644
fe214163
RM		 4645/**
4646 * drm_edid_to_sad - extracts SADs from EDID
4647 * @edid: EDID to parse
4648 * @sads: pointer that will be set to the extracted SADs
4649 *
4650 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
fe214163 4651 *
db6cf833
TR		 4652 * Note: The returned pointer needs to be freed using kfree().
4653 *
4654 * Return: The number of found SADs or negative number on error.
fe214163
RM		 4655 */
4656int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
4657{
4658 int count = 0;
4659 int i, start, end, dbl;
43d16d84 4660 const u8 *cea;
fe214163
RM		 4661
4662 cea = drm_find_cea_extension(edid);
4663 if (!cea) {
4664 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
42908007 4665 return 0;
fe214163
RM		 4666 }
4667
4668 if (cea_revision(cea) < 3) {
4669 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
42908007 4670 return 0;
fe214163
RM		 4671 }
4672
4673 if (cea_db_offsets(cea, &start, &end)) {
4674 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4675 return -EPROTO;
4676 }
4677
4678 for_each_cea_db(cea, i, start, end) {
43d16d84 4679 const u8 *db = &cea[i];
fe214163
RM		 4680
4681 if (cea_db_tag(db) == AUDIO_BLOCK) {
4682 int j;
948de842 4683
fe214163
RM		 4684 dbl = cea_db_payload_len(db);
4685
4686 count = dbl / 3; /* SAD is 3B */
4687 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
4688 if (!*sads)
4689 return -ENOMEM;
4690 for (j = 0; j < count; j++) {
43d16d84 4691 const u8 *sad = &db[1 + j * 3];
fe214163
RM		 4692
4693 (*sads)[j].format = (sad[0] & 0x78) >> 3;
4694 (*sads)[j].channels = sad[0] & 0x7;
4695 (*sads)[j].freq = sad[1] & 0x7F;
4696 (*sads)[j].byte2 = sad[2];
4697 }
4698 break;
4699 }
4700 }
4701
4702 return count;
4703}
4704EXPORT_SYMBOL(drm_edid_to_sad);
4705
d105f476
AD		 4706/**
4707 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
4708 * @edid: EDID to parse
4709 * @sadb: pointer to the speaker block
4710 *
4711 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
d105f476 4712 *
db6cf833
TR		 4713 * Note: The returned pointer needs to be freed using kfree().
4714 *
4715 * Return: The number of found Speaker Allocation Blocks or negative number on
4716 * error.
d105f476
AD		 4717 */
4718int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
4719{
4720 int count = 0;
4721 int i, start, end, dbl;
4722 const u8 *cea;
4723
4724 cea = drm_find_cea_extension(edid);
4725 if (!cea) {
4726 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
42908007 4727 return 0;
d105f476
AD		 4728 }
4729
4730 if (cea_revision(cea) < 3) {
4731 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
42908007 4732 return 0;
d105f476
AD		 4733 }
4734
4735 if (cea_db_offsets(cea, &start, &end)) {
4736 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4737 return -EPROTO;
4738 }
4739
4740 for_each_cea_db(cea, i, start, end) {
4741 const u8 *db = &cea[i];
4742
4743 if (cea_db_tag(db) == SPEAKER_BLOCK) {
4744 dbl = cea_db_payload_len(db);
4745
4746 /* Speaker Allocation Data Block */
4747 if (dbl == 3) {
89086bca 4748 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
618e3776
AD		 4749 if (!*sadb)
4750 return -ENOMEM;
d105f476
AD		 4751 count = dbl;
4752 break;
4753 }
4754 }
4755 }
4756
4757 return count;
4758}
4759EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
4760
76adaa34 4761/**
db6cf833 4762 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
76adaa34
WF		 4763 * @connector: connector associated with the HDMI/DP sink
4764 * @mode: the display mode
db6cf833
TR		 4765 *
4766 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
4767 * the sink doesn't support audio or video.
76adaa34
WF		 4768 */
4769int drm_av_sync_delay(struct drm_connector *connector,
3a818d35 4770 const struct drm_display_mode *mode)
76adaa34
WF		 4771{
4772 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
4773 int a, v;
4774
4775 if (!connector->latency_present[0])
4776 return 0;
4777 if (!connector->latency_present[1])
4778 i = 0;
4779
4780 a = connector->audio_latency[i];
4781 v = connector->video_latency[i];
4782
4783 /*
4784 * HDMI/DP sink doesn't support audio or video?
4785 */
4786 if (a == 255 || v == 255)
4787 return 0;
4788
4789 /*
4790 * Convert raw EDID values to millisecond.
4791 * Treat unknown latency as 0ms.
4792 */
4793 if (a)
4794 a = min(2 * (a - 1), 500);
4795 if (v)
4796 v = min(2 * (v - 1), 500);
4797
4798 return max(v - a, 0);
4799}
4800EXPORT_SYMBOL(drm_av_sync_delay);
4801
8fe9790d 4802/**
db6cf833 4803 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
8fe9790d
ZW		 4804 * @edid: monitor EDID information
4805 *
4806 * Parse the CEA extension according to CEA-861-B.
db6cf833 4807 *
a92d083d
LP		 4808 * Drivers that have added the modes parsed from EDID to drm_display_info
4809 * should use &drm_display_info.is_hdmi instead of calling this function.
4810 *
db6cf833 4811 * Return: True if the monitor is HDMI, false if not or unknown.
8fe9790d
ZW		 4812 */
4813bool drm_detect_hdmi_monitor(struct edid *edid)
4814{
43d16d84 4815 const u8 *edid_ext;
14f77fdd 4816 int i;
8fe9790d 4817 int start_offset, end_offset;
8fe9790d
ZW		 4818
4819 edid_ext = drm_find_cea_extension(edid);
4820 if (!edid_ext)
14f77fdd 4821 return false;
f23c20c8 4822
9e50b9d5 4823 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
14f77fdd 4824 return false;
f23c20c8
ML		 4825
4826 /*
4827 * Because HDMI identifier is in Vendor Specific Block,
4828 * search it from all data blocks of CEA extension.
4829 */
9e50b9d5 4830 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
14f77fdd
VS		 4831 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
4832 return true;
f23c20c8
ML		 4833 }
4834
14f77fdd 4835 return false;
f23c20c8
ML		 4836}
4837EXPORT_SYMBOL(drm_detect_hdmi_monitor);
4838
8fe9790d
ZW		 4839/**
4840 * drm_detect_monitor_audio - check monitor audio capability
fc66811c 4841 * @edid: EDID block to scan
8fe9790d
ZW		 4842 *
4843 * Monitor should have CEA extension block.
4844 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
4845 * audio' only. If there is any audio extension block and supported
4846 * audio format, assume at least 'basic audio' support, even if 'basic
4847 * audio' is not defined in EDID.
4848 *
db6cf833 4849 * Return: True if the monitor supports audio, false otherwise.
8fe9790d
ZW		 4850 */
4851bool drm_detect_monitor_audio(struct edid *edid)
4852{
43d16d84 4853 const u8 *edid_ext;
8fe9790d
ZW		 4854 int i, j;
4855 bool has_audio = false;
4856 int start_offset, end_offset;
4857
4858 edid_ext = drm_find_cea_extension(edid);
4859 if (!edid_ext)
4860 goto end;
4861
4862 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
4863
4864 if (has_audio) {
4865 DRM_DEBUG_KMS("Monitor has basic audio support\n");
4866 goto end;
4867 }
4868
9e50b9d5
VS		 4869 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4870 goto end;
8fe9790d 4871
9e50b9d5
VS		 4872 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4873 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
8fe9790d 4874 has_audio = true;
9e50b9d5 4875 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
8fe9790d
ZW		 4876 DRM_DEBUG_KMS("CEA audio format %d\n",
4877 (edid_ext[i + j] >> 3) & 0xf);
4878 goto end;
4879 }
4880 }
4881end:
4882 return has_audio;
4883}
4884EXPORT_SYMBOL(drm_detect_monitor_audio);
4885
b1edd6a6 4886
c8127cf0
VS		 4887/**
4888 * drm_default_rgb_quant_range - default RGB quantization range
4889 * @mode: display mode
4890 *
4891 * Determine the default RGB quantization range for the mode,
4892 * as specified in CEA-861.
4893 *
4894 * Return: The default RGB quantization range for the mode
4895 */
4896enum hdmi_quantization_range
4897drm_default_rgb_quant_range(const struct drm_display_mode *mode)
4898{
4899 /* All CEA modes other than VIC 1 use limited quantization range. */
4900 return drm_match_cea_mode(mode) > 1 ?
4901 HDMI_QUANTIZATION_RANGE_LIMITED :
4902 HDMI_QUANTIZATION_RANGE_FULL;
4903}
4904EXPORT_SYMBOL(drm_default_rgb_quant_range);
4905
1581b2df
VS		 4906static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
4907{
4908 struct drm_display_info *info = &connector->display_info;
4909
4910 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]);
4911
4912 if (db[2] & EDID_CEA_VCDB_QS)
4913 info->rgb_quant_range_selectable = true;
4914}
4915
4499d488
SS		 4916static
4917void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane)
4918{
4919 switch (max_frl_rate) {
4920 case 1:
4921 *max_lanes = 3;
4922 *max_rate_per_lane = 3;
4923 break;
4924 case 2:
4925 *max_lanes = 3;
4926 *max_rate_per_lane = 6;
4927 break;
4928 case 3:
4929 *max_lanes = 4;
4930 *max_rate_per_lane = 6;
4931 break;
4932 case 4:
4933 *max_lanes = 4;
4934 *max_rate_per_lane = 8;
4935 break;
4936 case 5:
4937 *max_lanes = 4;
4938 *max_rate_per_lane = 10;
4939 break;
4940 case 6:
4941 *max_lanes = 4;
4942 *max_rate_per_lane = 12;
4943 break;
4944 case 0:
4945 default:
4946 *max_lanes = 0;
4947 *max_rate_per_lane = 0;
4948 }
4949}
4950
e6a9a2c3
SS		 4951static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
4952 const u8 *db)
4953{
4954 u8 dc_mask;
4955 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4956
4957 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
9068e02f 4958 hdmi->y420_dc_modes = dc_mask;
e6a9a2c3
SS		 4959}
4960
afa1c763
SS		 4961static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector,
4962 const u8 *hf_vsdb)
4963{
62c58af3
SS		 4964 struct drm_display_info *display = &connector->display_info;
4965 struct drm_hdmi_info *hdmi = &display->hdmi;
afa1c763 4966
f1781e9b
VS		 4967 display->has_hdmi_infoframe = true;
4968
afa1c763
SS		 4969 if (hf_vsdb[6] & 0x80) {
4970 hdmi->scdc.supported = true;
4971 if (hf_vsdb[6] & 0x40)
4972 hdmi->scdc.read_request = true;
4973 }
62c58af3
SS		 4974
4975 /*
4976 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
4977 * And as per the spec, three factors confirm this:
4978 * * Availability of a HF-VSDB block in EDID (check)
4979 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
4980 * * SCDC support available (let's check)
4981 * Lets check it out.
4982 */
4983
4984 if (hf_vsdb[5]) {
4985 /* max clock is 5000 KHz times block value */
4986 u32 max_tmds_clock = hf_vsdb[5] * 5000;
4987 struct drm_scdc *scdc = &hdmi->scdc;
4988
4989 if (max_tmds_clock > 340000) {
4990 display->max_tmds_clock = max_tmds_clock;
4991 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
4992 display->max_tmds_clock);
4993 }
4994
4995 if (scdc->supported) {
4996 scdc->scrambling.supported = true;
4997
dbe2d2bf 4998 /* Few sinks support scrambling for clocks < 340M */
62c58af3
SS		 4999 if ((hf_vsdb[6] & 0x8))
5000 scdc->scrambling.low_rates = true;
5001 }
5002 }
e6a9a2c3 5003
4499d488
SS		 5004 if (hf_vsdb[7]) {
5005 u8 max_frl_rate;
76ee7b90
AN		 5006 u8 dsc_max_frl_rate;
5007 u8 dsc_max_slices;
5008 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap;
4499d488
SS		 5009
5010 DRM_DEBUG_KMS("hdmi_21 sink detected. parsing edid\n");
5011 max_frl_rate = (hf_vsdb[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4;
5012 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes,
5013 &hdmi->max_frl_rate_per_lane);
76ee7b90
AN		 5014 hdmi_dsc->v_1p2 = hf_vsdb[11] & DRM_EDID_DSC_1P2;
5015
5016 if (hdmi_dsc->v_1p2) {
5017 hdmi_dsc->native_420 = hf_vsdb[11] & DRM_EDID_DSC_NATIVE_420;
5018 hdmi_dsc->all_bpp = hf_vsdb[11] & DRM_EDID_DSC_ALL_BPP;
5019
5020 if (hf_vsdb[11] & DRM_EDID_DSC_16BPC)
5021 hdmi_dsc->bpc_supported = 16;
5022 else if (hf_vsdb[11] & DRM_EDID_DSC_12BPC)
5023 hdmi_dsc->bpc_supported = 12;
5024 else if (hf_vsdb[11] & DRM_EDID_DSC_10BPC)
5025 hdmi_dsc->bpc_supported = 10;
5026 else
5027 hdmi_dsc->bpc_supported = 0;
5028
5029 dsc_max_frl_rate = (hf_vsdb[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4;
5030 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes,
5031 &hdmi_dsc->max_frl_rate_per_lane);
5032 hdmi_dsc->total_chunk_kbytes = hf_vsdb[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES;
5033
5034 dsc_max_slices = hf_vsdb[12] & DRM_EDID_DSC_MAX_SLICES;
5035 switch (dsc_max_slices) {
5036 case 1:
5037 hdmi_dsc->max_slices = 1;
5038 hdmi_dsc->clk_per_slice = 340;
5039 break;
5040 case 2:
5041 hdmi_dsc->max_slices = 2;
5042 hdmi_dsc->clk_per_slice = 340;
5043 break;
5044 case 3:
5045 hdmi_dsc->max_slices = 4;
5046 hdmi_dsc->clk_per_slice = 340;
5047 break;
5048 case 4:
5049 hdmi_dsc->max_slices = 8;
5050 hdmi_dsc->clk_per_slice = 340;
5051 break;
5052 case 5:
5053 hdmi_dsc->max_slices = 8;
5054 hdmi_dsc->clk_per_slice = 400;
5055 break;
5056 case 6:
5057 hdmi_dsc->max_slices = 12;
5058 hdmi_dsc->clk_per_slice = 400;
5059 break;
5060 case 7:
5061 hdmi_dsc->max_slices = 16;
5062 hdmi_dsc->clk_per_slice = 400;
5063 break;
5064 case 0:
5065 default:
5066 hdmi_dsc->max_slices = 0;
5067 hdmi_dsc->clk_per_slice = 0;
5068 }
5069 }
4499d488
SS		 5070 }
5071
e6a9a2c3 5072 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb);
afa1c763
SS		 5073}
5074
1cea146a
VS		 5075static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
5076 const u8 *hdmi)
d0c94692 5077{
1826750f 5078 struct drm_display_info *info = &connector->display_info;
d0c94692
MK		 5079 unsigned int dc_bpc = 0;
5080
1cea146a
VS		 5081 /* HDMI supports at least 8 bpc */
5082 info->bpc = 8;
d0c94692 5083
1cea146a
VS		 5084 if (cea_db_payload_len(hdmi) < 6)
5085 return;
5086
5087 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
5088 dc_bpc = 10;
5089 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
5090 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
5091 connector->name);
5092 }
5093
5094 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
5095 dc_bpc = 12;
5096 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
5097 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
5098 connector->name);
5099 }
5100
5101 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
5102 dc_bpc = 16;
5103 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
5104 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
5105 connector->name);
5106 }
5107
5108 if (dc_bpc == 0) {
5109 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
5110 connector->name);
5111 return;
5112 }
5113
5114 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
5115 connector->name, dc_bpc);
5116 info->bpc = dc_bpc;
d0c94692 5117
1cea146a
VS		 5118 /* YCRCB444 is optional according to spec. */
5119 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
1cea146a
VS		 5120 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
5121 connector->name);
5122 }
d0c94692 5123
1cea146a
VS		 5124 /*
5125 * Spec says that if any deep color mode is supported at all,
5126 * then deep color 36 bit must be supported.
5127 */
5128 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
5129 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
5130 connector->name);
5131 }
5132}
d0c94692 5133
23ebf8b9
VS		 5134static void
5135drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
5136{
5137 struct drm_display_info *info = &connector->display_info;
5138 u8 len = cea_db_payload_len(db);
5139
a92d083d
LP		 5140 info->is_hdmi = true;
5141
23ebf8b9
VS		 5142 if (len >= 6)
5143 info->dvi_dual = db[6] & 1;
5144 if (len >= 7)
5145 info->max_tmds_clock = db[7] * 5000;
5146
5147 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
5148 "max TMDS clock %d kHz\n",
5149 info->dvi_dual,
5150 info->max_tmds_clock);
5151
5152 drm_parse_hdmi_deep_color_info(connector, db);
5153}
5154
2869f599
PZ		 5155/*
5156 * See EDID extension for head-mounted and specialized monitors, specified at:
5157 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/specialized-monitors-edid-extension
5158 */
5159static void drm_parse_microsoft_vsdb(struct drm_connector *connector,
5160 const u8 *db)
5161{
5162 struct drm_display_info *info = &connector->display_info;
5163 u8 version = db[4];
5164 bool desktop_usage = db[5] & BIT(6);
5165
5166 /* Version 1 and 2 for HMDs, version 3 flags desktop usage explicitly */
5167 if (version == 1 || version == 2 || (version == 3 && !desktop_usage))
5168 info->non_desktop = true;
5169
5170 drm_dbg_kms(connector->dev, "HMD or specialized display VSDB version %u: 0x%02x\n",
5171 version, db[5]);
5172}
5173
1cea146a 5174static void drm_parse_cea_ext(struct drm_connector *connector,
170178fe 5175 const struct edid *edid)
1cea146a
VS		 5176{
5177 struct drm_display_info *info = &connector->display_info;
5178 const u8 *edid_ext;
5179 int i, start, end;
d0c94692 5180
1cea146a
VS		 5181 edid_ext = drm_find_cea_extension(edid);
5182 if (!edid_ext)
5183 return;
d0c94692 5184
1cea146a 5185 info->cea_rev = edid_ext[1];
d0c94692 5186
1cea146a
VS		 5187 /* The existence of a CEA block should imply RGB support */
5188 info->color_formats = DRM_COLOR_FORMAT_RGB444;
5189 if (edid_ext[3] & EDID_CEA_YCRCB444)
5190 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
5191 if (edid_ext[3] & EDID_CEA_YCRCB422)
5192 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
5193
5194 if (cea_db_offsets(edid_ext, &start, &end))
5195 return;
5196
5197 for_each_cea_db(edid_ext, i, start, end) {
5198 const u8 *db = &edid_ext[i];
5199
23ebf8b9
VS		 5200 if (cea_db_is_hdmi_vsdb(db))
5201 drm_parse_hdmi_vsdb_video(connector, db);
afa1c763
SS		 5202 if (cea_db_is_hdmi_forum_vsdb(db))
5203 drm_parse_hdmi_forum_vsdb(connector, db);
2869f599
PZ		 5204 if (cea_db_is_microsoft_vsdb(db))
5205 drm_parse_microsoft_vsdb(connector, db);
832d4f2f
SS		 5206 if (cea_db_is_y420cmdb(db))
5207 drm_parse_y420cmdb_bitmap(connector, db);
1581b2df
VS		 5208 if (cea_db_is_vcdb(db))
5209 drm_parse_vcdb(connector, db);
e85959d6
US		 5210 if (cea_db_is_hdmi_hdr_metadata_block(db))
5211 drm_parse_hdr_metadata_block(connector, db);
1cea146a 5212 }
d0c94692
MK		 5213}
5214
a1d11d1e
MN		 5215static
5216void get_monitor_range(struct detailed_timing *timing,
5217 void *info_monitor_range)
5218{
5219 struct drm_monitor_range_info *monitor_range = info_monitor_range;
5220 const struct detailed_non_pixel *data = &timing->data.other_data;
5221 const struct detailed_data_monitor_range *range = &data->data.range;
5222
5223 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE))
5224 return;
5225
5226 /*
5227 * Check for flag range limits only. If flag == 1 then
5228 * no additional timing information provided.
5229 * Default GTF, GTF Secondary curve and CVT are not
5230 * supported
5231 */
5232 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG)
5233 return;
5234
5235 monitor_range->min_vfreq = range->min_vfreq;
5236 monitor_range->max_vfreq = range->max_vfreq;
5237}
5238
5239static
5240void drm_get_monitor_range(struct drm_connector *connector,
5241 const struct edid *edid)
5242{
5243 struct drm_display_info *info = &connector->display_info;
5244
5245 if (!version_greater(edid, 1, 1))
5246 return;
5247
5248 drm_for_each_detailed_block((u8 *)edid, get_monitor_range,
5249 &info->monitor_range);
5250
5251 DRM_DEBUG_KMS("Supported Monitor Refresh rate range is %d Hz - %d Hz\n",
5252 info->monitor_range.min_vfreq,
5253 info->monitor_range.max_vfreq);
5254}
5255
18a9cbbe
JN		 5256static void drm_parse_vesa_mso_data(struct drm_connector *connector,
5257 const struct displayid_block *block)
5258{
5259 struct displayid_vesa_vendor_specific_block *vesa =
5260 (struct displayid_vesa_vendor_specific_block *)block;
5261 struct drm_display_info *info = &connector->display_info;
5262
5263 if (block->num_bytes < 3) {
5264 drm_dbg_kms(connector->dev, "Unexpected vendor block size %u\n",
5265 block->num_bytes);
5266 return;
5267 }
5268
5269 if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI)
5270 return;
5271
5272 if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
5273 drm_dbg_kms(connector->dev, "Unexpected VESA vendor block size\n");
5274 return;
5275 }
5276
5277 switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
5278 default:
5279 drm_dbg_kms(connector->dev, "Reserved MSO mode value\n");
5280 fallthrough;
5281 case 0:
5282 info->mso_stream_count = 0;
5283 break;
5284 case 1:
5285 info->mso_stream_count = 2; /* 2 or 4 links */
5286 break;
5287 case 2:
5288 info->mso_stream_count = 4; /* 4 links */
5289 break;
5290 }
5291
5292 if (!info->mso_stream_count) {
5293 info->mso_pixel_overlap = 0;
5294 return;
5295 }
5296
5297 info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
5298 if (info->mso_pixel_overlap > 8) {
5299 drm_dbg_kms(connector->dev, "Reserved MSO pixel overlap value %u\n",
5300 info->mso_pixel_overlap);
5301 info->mso_pixel_overlap = 8;
5302 }
5303
5304 drm_dbg_kms(connector->dev, "MSO stream count %u, pixel overlap %u\n",
5305 info->mso_stream_count, info->mso_pixel_overlap);
5306}
5307
5308static void drm_update_mso(struct drm_connector *connector, const struct edid *edid)
5309{
5310 const struct displayid_block *block;
5311 struct displayid_iter iter;
5312
5313 displayid_iter_edid_begin(edid, &iter);
5314 displayid_iter_for_each(block, &iter) {
5315 if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC)
5316 drm_parse_vesa_mso_data(connector, block);
5317 }
5318 displayid_iter_end(&iter);
5319}
5320
170178fe
KP		 5321/* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
5322 * all of the values which would have been set from EDID
5323 */
5324void
5325drm_reset_display_info(struct drm_connector *connector)
5326{
5327 struct drm_display_info *info = &connector->display_info;
5328
5329 info->width_mm = 0;
5330 info->height_mm = 0;
5331
5332 info->bpc = 0;
5333 info->color_formats = 0;
5334 info->cea_rev = 0;
5335 info->max_tmds_clock = 0;
5336 info->dvi_dual = false;
a92d083d 5337 info->is_hdmi = false;
170178fe 5338 info->has_hdmi_infoframe = false;
1581b2df 5339 info->rgb_quant_range_selectable = false;
1f6b8eef 5340 memset(&info->hdmi, 0, sizeof(info->hdmi));
170178fe
KP		 5341
5342 info->non_desktop = 0;
a1d11d1e 5343 memset(&info->monitor_range, 0, sizeof(info->monitor_range));
18a9cbbe
JN		 5344
5345 info->mso_stream_count = 0;
5346 info->mso_pixel_overlap = 0;
170178fe 5347}
170178fe
KP		 5348
5349u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid)
3b11228b 5350{
1826750f 5351 struct drm_display_info *info = &connector->display_info;
ebec9a7b 5352
170178fe
KP		 5353 u32 quirks = edid_get_quirks(edid);
5354
1f6b8eef
VS		 5355 drm_reset_display_info(connector);
5356
3b11228b
JB		 5357 info->width_mm = edid->width_cm * 10;
5358 info->height_mm = edid->height_cm * 10;
5359
a1d11d1e
MN		 5360 drm_get_monitor_range(connector, edid);
5361
a988bc72 5362 if (edid->revision < 3)
ce99534e 5363 goto out;
3b11228b
JB		 5364
5365 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
ce99534e 5366 goto out;
3b11228b 5367
1cea146a 5368 drm_parse_cea_ext(connector, edid);
d0c94692 5369
210a021d
MK		 5370 /*
5371 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
5372 *
5373 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
5374 * tells us to assume 8 bpc color depth if the EDID doesn't have
5375 * extensions which tell otherwise.
5376 */
3bde449f
VS		 5377 if (info->bpc == 0 && edid->revision == 3 &&
5378 edid->input & DRM_EDID_DIGITAL_DFP_1_X) {
210a021d
MK		 5379 info->bpc = 8;
5380 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
5381 connector->name, info->bpc);
5382 }
5383
a988bc72
LPC		 5384 /* Only defined for 1.4 with digital displays */
5385 if (edid->revision < 4)
ce99534e 5386 goto out;
a988bc72 5387
3b11228b
JB		 5388 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
5389 case DRM_EDID_DIGITAL_DEPTH_6:
5390 info->bpc = 6;
5391 break;
5392 case DRM_EDID_DIGITAL_DEPTH_8:
5393 info->bpc = 8;
5394 break;
5395 case DRM_EDID_DIGITAL_DEPTH_10:
5396 info->bpc = 10;
5397 break;
5398 case DRM_EDID_DIGITAL_DEPTH_12:
5399 info->bpc = 12;
5400 break;
5401 case DRM_EDID_DIGITAL_DEPTH_14:
5402 info->bpc = 14;
5403 break;
5404 case DRM_EDID_DIGITAL_DEPTH_16:
5405 info->bpc = 16;
5406 break;
5407 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
5408 default:
5409 info->bpc = 0;
5410 break;
5411 }
da05a5a7 5412
d0c94692 5413 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
25933820 5414 connector->name, info->bpc);
d0c94692 5415
a988bc72 5416 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
ee58808d
LPC		 5417 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
5418 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
5419 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
5420 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
18a9cbbe
JN		 5421
5422 drm_update_mso(connector, edid);
5423
ce99534e
JN		 5424out:
5425 if (quirks & EDID_QUIRK_NON_DESKTOP) {
5426 drm_dbg_kms(connector->dev, "Non-desktop display%s\n",
5427 info->non_desktop ? " (redundant quirk)" : "");
5428 info->non_desktop = true;
5429 }
5430
170178fe 5431 return quirks;
3b11228b
JB		 5432}
5433
a39ed680
DA		 5434static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
5435 struct displayid_detailed_timings_1 *timings)
5436{
5437 struct drm_display_mode *mode;
5438 unsigned pixel_clock = (timings->pixel_clock[0] |
5439 (timings->pixel_clock[1] << 8) |
6292b8ef 5440 (timings->pixel_clock[2] << 16)) + 1;
a39ed680
DA		 5441 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
5442 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
5443 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
5444 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
5445 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
5446 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
5447 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
5448 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
5449 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
5450 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
948de842 5451
a39ed680
DA		 5452 mode = drm_mode_create(dev);
5453 if (!mode)
5454 return NULL;
5455
5456 mode->clock = pixel_clock * 10;
5457 mode->hdisplay = hactive;
5458 mode->hsync_start = mode->hdisplay + hsync;
5459 mode->hsync_end = mode->hsync_start + hsync_width;
5460 mode->htotal = mode->hdisplay + hblank;
5461
5462 mode->vdisplay = vactive;
5463 mode->vsync_start = mode->vdisplay + vsync;
5464 mode->vsync_end = mode->vsync_start + vsync_width;
5465 mode->vtotal = mode->vdisplay + vblank;
5466
5467 mode->flags = 0;
5468 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
5469 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
5470 mode->type = DRM_MODE_TYPE_DRIVER;
5471
5472 if (timings->flags & 0x80)
5473 mode->type |= DRM_MODE_TYPE_PREFERRED;
a39ed680
DA		 5474 drm_mode_set_name(mode);
5475
5476 return mode;
5477}
5478
5479static int add_displayid_detailed_1_modes(struct drm_connector *connector,
43d16d84 5480 const struct displayid_block *block)
a39ed680
DA		 5481{
5482 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
5483 int i;
5484 int num_timings;
5485 struct drm_display_mode *newmode;
5486 int num_modes = 0;
5487 /* blocks must be multiple of 20 bytes length */
5488 if (block->num_bytes % 20)
5489 return 0;
5490
5491 num_timings = block->num_bytes / 20;
5492 for (i = 0; i < num_timings; i++) {
5493 struct displayid_detailed_timings_1 *timings = &det->timings[i];
5494
5495 newmode = drm_mode_displayid_detailed(connector->dev, timings);
5496 if (!newmode)
5497 continue;
5498
5499 drm_mode_probed_add(connector, newmode);
5500 num_modes++;
5501 }
5502 return num_modes;
5503}
5504
5505static int add_displayid_detailed_modes(struct drm_connector *connector,
5506 struct edid *edid)
5507{
43d16d84 5508 const struct displayid_block *block;
5ef88dc5 5509 struct displayid_iter iter;
a39ed680
DA		 5510 int num_modes = 0;
5511
5ef88dc5
JN		 5512 displayid_iter_edid_begin(edid, &iter);
5513 displayid_iter_for_each(block, &iter) {
5514 if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING)
5515 num_modes += add_displayid_detailed_1_modes(connector, block);
a39ed680 5516 }
5ef88dc5 5517 displayid_iter_end(&iter);
7f261afd 5518
a39ed680
DA		 5519 return num_modes;
5520}
5521
f453ba04
DA		 5522/**
5523 * drm_add_edid_modes - add modes from EDID data, if available
5524 * @connector: connector we're probing
db6cf833 5525 * @edid: EDID data
f453ba04 5526 *
b3c6c8bf 5527 * Add the specified modes to the connector's mode list. Also fills out the
c945b8c1
JN		 5528 * &drm_display_info structure and ELD in @connector with any information which
5529 * can be derived from the edid.
f453ba04 5530 *
db6cf833 5531 * Return: The number of modes added or 0 if we couldn't find any.
f453ba04
DA		 5532 */
5533int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
5534{
5535 int num_modes = 0;
5536 u32 quirks;
5537
5538 if (edid == NULL) {
c945b8c1 5539 clear_eld(connector);
f453ba04
DA		 5540 return 0;
5541 }
3c537889 5542 if (!drm_edid_is_valid(edid)) {
c945b8c1 5543 clear_eld(connector);
6d45fff5 5544 drm_warn(connector->dev, "%s: EDID invalid.\n",
25933820 5545 connector->name);
f453ba04
DA		 5546 return 0;
5547 }
5548
c945b8c1
JN		 5549 drm_edid_to_eld(connector, edid);
5550
0f0f8708
SS		 5551 /*
5552 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
5553 * To avoid multiple parsing of same block, lets parse that map
5554 * from sink info, before parsing CEA modes.
5555 */
170178fe 5556 quirks = drm_add_display_info(connector, edid);
0f0f8708 5557
c867df70
AJ		 5558 /*
5559 * EDID spec says modes should be preferred in this order:
5560 * - preferred detailed mode
5561 * - other detailed modes from base block
5562 * - detailed modes from extension blocks
5563 * - CVT 3-byte code modes
5564 * - standard timing codes
5565 * - established timing codes
5566 * - modes inferred from GTF or CVT range information
5567 *
13931579 5568 * We get this pretty much right.
c867df70
AJ		 5569 *
5570 * XXX order for additional mode types in extension blocks?
5571 */
13931579
AJ		 5572 num_modes += add_detailed_modes(connector, edid, quirks);
5573 num_modes += add_cvt_modes(connector, edid);
c867df70
AJ		 5574 num_modes += add_standard_modes(connector, edid);
5575 num_modes += add_established_modes(connector, edid);
54ac76f8 5576 num_modes += add_cea_modes(connector, edid);
e6e79209 5577 num_modes += add_alternate_cea_modes(connector, edid);
a39ed680 5578 num_modes += add_displayid_detailed_modes(connector, edid);
4d53dc0c
VS		 5579 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
5580 num_modes += add_inferred_modes(connector, edid);
f453ba04
DA		 5581
5582 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
5583 edid_fixup_preferred(connector, quirks);
5584
e10aec65
MK		 5585 if (quirks & EDID_QUIRK_FORCE_6BPC)
5586 connector->display_info.bpc = 6;
5587
49d45a31
RM		 5588 if (quirks & EDID_QUIRK_FORCE_8BPC)
5589 connector->display_info.bpc = 8;
5590
e345da82
MK		 5591 if (quirks & EDID_QUIRK_FORCE_10BPC)
5592 connector->display_info.bpc = 10;
5593
bc5b9641
MK		 5594 if (quirks & EDID_QUIRK_FORCE_12BPC)
5595 connector->display_info.bpc = 12;
5596
f453ba04
DA		 5597 return num_modes;
5598}
5599EXPORT_SYMBOL(drm_add_edid_modes);
f0fda0a4
ZY		 5600
5601/**
5602 * drm_add_modes_noedid - add modes for the connectors without EDID
5603 * @connector: connector we're probing
5604 * @hdisplay: the horizontal display limit
5605 * @vdisplay: the vertical display limit
5606 *
5607 * Add the specified modes to the connector's mode list. Only when the
5608 * hdisplay/vdisplay is not beyond the given limit, it will be added.
5609 *
db6cf833 5610 * Return: The number of modes added or 0 if we couldn't find any.
f0fda0a4
ZY		 5611 */
5612int drm_add_modes_noedid(struct drm_connector *connector,
5613 int hdisplay, int vdisplay)
5614{
5615 int i, count, num_modes = 0;
b1f559ec 5616 struct drm_display_mode *mode;
f0fda0a4
ZY		 5617 struct drm_device *dev = connector->dev;
5618
fbb40b28 5619 count = ARRAY_SIZE(drm_dmt_modes);
f0fda0a4
ZY		 5620 if (hdisplay < 0)
5621 hdisplay = 0;
5622 if (vdisplay < 0)
5623 vdisplay = 0;
5624
5625 for (i = 0; i < count; i++) {
b1f559ec 5626 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
948de842 5627
f0fda0a4
ZY		 5628 if (hdisplay && vdisplay) {
5629 /*
5630 * Only when two are valid, they will be used to check
5631 * whether the mode should be added to the mode list of
5632 * the connector.
5633 */
5634 if (ptr->hdisplay > hdisplay ||
5635 ptr->vdisplay > vdisplay)
5636 continue;
5637 }
f985dedb
AJ		 5638 if (drm_mode_vrefresh(ptr) > 61)
5639 continue;
f0fda0a4
ZY		 5640 mode = drm_mode_duplicate(dev, ptr);
5641 if (mode) {
5642 drm_mode_probed_add(connector, mode);
5643 num_modes++;
5644 }
5645 }
5646 return num_modes;
5647}
5648EXPORT_SYMBOL(drm_add_modes_noedid);
10a85120 5649
db6cf833
TR		 5650/**
5651 * drm_set_preferred_mode - Sets the preferred mode of a connector
5652 * @connector: connector whose mode list should be processed
5653 * @hpref: horizontal resolution of preferred mode
5654 * @vpref: vertical resolution of preferred mode
5655 *
5656 * Marks a mode as preferred if it matches the resolution specified by @hpref
5657 * and @vpref.
5658 */
3cf70daf
GH		 5659void drm_set_preferred_mode(struct drm_connector *connector,
5660 int hpref, int vpref)
5661{
5662 struct drm_display_mode *mode;
5663
5664 list_for_each_entry(mode, &connector->probed_modes, head) {
db6cf833 5665 if (mode->hdisplay == hpref &&
9d3de138 5666 mode->vdisplay == vpref)
3cf70daf
GH		 5667 mode->type |= DRM_MODE_TYPE_PREFERRED;
5668 }
5669}
5670EXPORT_SYMBOL(drm_set_preferred_mode);
5671
192a3aa0 5672static bool is_hdmi2_sink(const struct drm_connector *connector)
13d0add3
VS		 5673{
5674 /*
5675 * FIXME: sil-sii8620 doesn't have a connector around when
5676 * we need one, so we have to be prepared for a NULL connector.
5677 */
5678 if (!connector)
5679 return true;
5680
5681 return connector->display_info.hdmi.scdc.supported ||
5682 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420;
5683}
5684
2cdbfd66
US		 5685static inline bool is_eotf_supported(u8 output_eotf, u8 sink_eotf)
5686{
5687 return sink_eotf & BIT(output_eotf);
5688}
5689
5690/**
5691 * drm_hdmi_infoframe_set_hdr_metadata() - fill an HDMI DRM infoframe with
5692 * HDR metadata from userspace
5693 * @frame: HDMI DRM infoframe
6ac98829 5694 * @conn_state: Connector state containing HDR metadata
2cdbfd66
US		 5695 *
5696 * Return: 0 on success or a negative error code on failure.
5697 */
5698int
5699drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame,
5700 const struct drm_connector_state *conn_state)
5701{
5702 struct drm_connector *connector;
5703 struct hdr_output_metadata *hdr_metadata;
5704 int err;
5705
5706 if (!frame || !conn_state)
5707 return -EINVAL;
5708
5709 connector = conn_state->connector;
5710
5711 if (!conn_state->hdr_output_metadata)
5712 return -EINVAL;
5713
5714 hdr_metadata = conn_state->hdr_output_metadata->data;
5715
5716 if (!hdr_metadata || !connector)
5717 return -EINVAL;
5718
5719 /* Sink EOTF is Bit map while infoframe is absolute values */
5720 if (!is_eotf_supported(hdr_metadata->hdmi_metadata_type1.eotf,
5721 connector->hdr_sink_metadata.hdmi_type1.eotf)) {
5722 DRM_DEBUG_KMS("EOTF Not Supported\n");
5723 return -EINVAL;
5724 }
5725
5726 err = hdmi_drm_infoframe_init(frame);
5727 if (err < 0)
5728 return err;
5729
5730 frame->eotf = hdr_metadata->hdmi_metadata_type1.eotf;
5731 frame->metadata_type = hdr_metadata->hdmi_metadata_type1.metadata_type;
5732
5733 BUILD_BUG_ON(sizeof(frame->display_primaries) !=
5734 sizeof(hdr_metadata->hdmi_metadata_type1.display_primaries));
5735 BUILD_BUG_ON(sizeof(frame->white_point) !=
5736 sizeof(hdr_metadata->hdmi_metadata_type1.white_point));
5737
5738 memcpy(&frame->display_primaries,
5739 &hdr_metadata->hdmi_metadata_type1.display_primaries,
5740 sizeof(frame->display_primaries));
5741
5742 memcpy(&frame->white_point,
5743 &hdr_metadata->hdmi_metadata_type1.white_point,
5744 sizeof(frame->white_point));
5745
5746 frame->max_display_mastering_luminance =
5747 hdr_metadata->hdmi_metadata_type1.max_display_mastering_luminance;
5748 frame->min_display_mastering_luminance =
5749 hdr_metadata->hdmi_metadata_type1.min_display_mastering_luminance;
5750 frame->max_fall = hdr_metadata->hdmi_metadata_type1.max_fall;
5751 frame->max_cll = hdr_metadata->hdmi_metadata_type1.max_cll;
5752
5753 return 0;
5754}
5755EXPORT_SYMBOL(drm_hdmi_infoframe_set_hdr_metadata);
5756
192a3aa0 5757static u8 drm_mode_hdmi_vic(const struct drm_connector *connector,
949561eb
VS		 5758 const struct drm_display_mode *mode)
5759{
5760 bool has_hdmi_infoframe = connector ?
5761 connector->display_info.has_hdmi_infoframe : false;
5762
5763 if (!has_hdmi_infoframe)
5764 return 0;
5765
5766 /* No HDMI VIC when signalling 3D video format */
5767 if (mode->flags & DRM_MODE_FLAG_3D_MASK)
5768 return 0;
5769
5770 return drm_match_hdmi_mode(mode);
5771}
5772
192a3aa0 5773static u8 drm_mode_cea_vic(const struct drm_connector *connector,
cfd6f8c3
VS		 5774 const struct drm_display_mode *mode)
5775{
cfd6f8c3
VS		 5776 u8 vic;
5777
5778 /*
5779 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
5780 * we should send its VIC in vendor infoframes, else send the
5781 * VIC in AVI infoframes. Lets check if this mode is present in
5782 * HDMI 1.4b 4K modes
5783 */
949561eb 5784 if (drm_mode_hdmi_vic(connector, mode))
cfd6f8c3
VS		 5785 return 0;
5786
5787 vic = drm_match_cea_mode(mode);
5788
5789 /*
5790 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
5791 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
5792 * have to make sure we dont break HDMI 1.4 sinks.
5793 */
5794 if (!is_hdmi2_sink(connector) && vic > 64)
5795 return 0;
5796
5797 return vic;
5798}
5799
10a85120
TR		 5800/**
5801 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
5802 * data from a DRM display mode
5803 * @frame: HDMI AVI infoframe
13d0add3 5804 * @connector: the connector
10a85120
TR		 5805 * @mode: DRM display mode
5806 *
db6cf833 5807 * Return: 0 on success or a negative error code on failure.
10a85120
TR		 5808 */
5809int
5810drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
192a3aa0 5811 const struct drm_connector *connector,
13d0add3 5812 const struct drm_display_mode *mode)
10a85120 5813{
a9c266c2 5814 enum hdmi_picture_aspect picture_aspect;
d2b43473 5815 u8 vic, hdmi_vic;
10a85120
TR		 5816
5817 if (!frame || !mode)
5818 return -EINVAL;
5819
5ee0caf1 5820 hdmi_avi_infoframe_init(frame);
10a85120 5821
bf02db99
DL		 5822 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
5823 frame->pixel_repeat = 1;
5824
d2b43473
WL		 5825 vic = drm_mode_cea_vic(connector, mode);
5826 hdmi_vic = drm_mode_hdmi_vic(connector, mode);
0c1f528c 5827
10a85120 5828 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
0967e6a5 5829
50525c33
SL		 5830 /*
5831 * As some drivers don't support atomic, we can't use connector state.
5832 * So just initialize the frame with default values, just the same way
5833 * as it's done with other properties here.
5834 */
5835 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
5836 frame->itc = 0;
5837
69ab6d35
VK		 5838 /*
5839 * Populate picture aspect ratio from either
d2b43473 5840 * user input (if specified) or from the CEA/HDMI mode lists.
69ab6d35 5841 */
a9c266c2 5842 picture_aspect = mode->picture_aspect_ratio;
d2b43473
WL		 5843 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) {
5844 if (vic)
5845 picture_aspect = drm_get_cea_aspect_ratio(vic);
5846 else if (hdmi_vic)
5847 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic);
5848 }
0967e6a5 5849
a9c266c2
VS		 5850 /*
5851 * The infoframe can't convey anything but none, 4:3
5852 * and 16:9, so if the user has asked for anything else
5853 * we can only satisfy it by specifying the right VIC.
5854 */
5855 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
d2b43473
WL		 5856 if (vic) {
5857 if (picture_aspect != drm_get_cea_aspect_ratio(vic))
5858 return -EINVAL;
5859 } else if (hdmi_vic) {
5860 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic))
5861 return -EINVAL;
5862 } else {
a9c266c2 5863 return -EINVAL;
d2b43473
WL		 5864 }
5865
a9c266c2
VS		 5866 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
5867 }
5868
d2b43473 5869 frame->video_code = vic;
a9c266c2 5870 frame->picture_aspect = picture_aspect;
10a85120 5871 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
24d01805 5872 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
10a85120
TR		 5873
5874 return 0;
5875}
5876EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
83dd0008 5877
0d68b887
US		 5878/* HDMI Colorspace Spec Definitions */
5879#define FULL_COLORIMETRY_MASK 0x1FF
5880#define NORMAL_COLORIMETRY_MASK 0x3
5881#define EXTENDED_COLORIMETRY_MASK 0x7
5882#define EXTENDED_ACE_COLORIMETRY_MASK 0xF
5883
5884#define C(x) ((x) << 0)
5885#define EC(x) ((x) << 2)
5886#define ACE(x) ((x) << 5)
5887
5888#define HDMI_COLORIMETRY_NO_DATA 0x0
5889#define HDMI_COLORIMETRY_SMPTE_170M_YCC (C(1) | EC(0) | ACE(0))
5890#define HDMI_COLORIMETRY_BT709_YCC (C(2) | EC(0) | ACE(0))
5891#define HDMI_COLORIMETRY_XVYCC_601 (C(3) | EC(0) | ACE(0))
5892#define HDMI_COLORIMETRY_XVYCC_709 (C(3) | EC(1) | ACE(0))
5893#define HDMI_COLORIMETRY_SYCC_601 (C(3) | EC(2) | ACE(0))
5894#define HDMI_COLORIMETRY_OPYCC_601 (C(3) | EC(3) | ACE(0))
5895#define HDMI_COLORIMETRY_OPRGB (C(3) | EC(4) | ACE(0))
5896#define HDMI_COLORIMETRY_BT2020_CYCC (C(3) | EC(5) | ACE(0))
5897#define HDMI_COLORIMETRY_BT2020_RGB (C(3) | EC(6) | ACE(0))
5898#define HDMI_COLORIMETRY_BT2020_YCC (C(3) | EC(6) | ACE(0))
5899#define HDMI_COLORIMETRY_DCI_P3_RGB_D65 (C(3) | EC(7) | ACE(0))
5900#define HDMI_COLORIMETRY_DCI_P3_RGB_THEATER (C(3) | EC(7) | ACE(1))
5901
5902static const u32 hdmi_colorimetry_val[] = {
5903 [DRM_MODE_COLORIMETRY_NO_DATA] = HDMI_COLORIMETRY_NO_DATA,
5904 [DRM_MODE_COLORIMETRY_SMPTE_170M_YCC] = HDMI_COLORIMETRY_SMPTE_170M_YCC,
5905 [DRM_MODE_COLORIMETRY_BT709_YCC] = HDMI_COLORIMETRY_BT709_YCC,
5906 [DRM_MODE_COLORIMETRY_XVYCC_601] = HDMI_COLORIMETRY_XVYCC_601,
5907 [DRM_MODE_COLORIMETRY_XVYCC_709] = HDMI_COLORIMETRY_XVYCC_709,
5908 [DRM_MODE_COLORIMETRY_SYCC_601] = HDMI_COLORIMETRY_SYCC_601,
5909 [DRM_MODE_COLORIMETRY_OPYCC_601] = HDMI_COLORIMETRY_OPYCC_601,
5910 [DRM_MODE_COLORIMETRY_OPRGB] = HDMI_COLORIMETRY_OPRGB,
5911 [DRM_MODE_COLORIMETRY_BT2020_CYCC] = HDMI_COLORIMETRY_BT2020_CYCC,
5912 [DRM_MODE_COLORIMETRY_BT2020_RGB] = HDMI_COLORIMETRY_BT2020_RGB,
5913 [DRM_MODE_COLORIMETRY_BT2020_YCC] = HDMI_COLORIMETRY_BT2020_YCC,
5914};
5915
5916#undef C
5917#undef EC
5918#undef ACE
5919
5920/**
4a46e5d2
MR		 5921 * drm_hdmi_avi_infoframe_colorimetry() - fill the HDMI AVI infoframe
5922 * colorimetry information
0d68b887
US		 5923 * @frame: HDMI AVI infoframe
5924 * @conn_state: connector state
5925 */
5926void
4a46e5d2 5927drm_hdmi_avi_infoframe_colorimetry(struct hdmi_avi_infoframe *frame,
0d68b887
US		 5928 const struct drm_connector_state *conn_state)
5929{
5930 u32 colorimetry_val;
5931 u32 colorimetry_index = conn_state->colorspace & FULL_COLORIMETRY_MASK;
5932
5933 if (colorimetry_index >= ARRAY_SIZE(hdmi_colorimetry_val))
5934 colorimetry_val = HDMI_COLORIMETRY_NO_DATA;
5935 else
5936 colorimetry_val = hdmi_colorimetry_val[colorimetry_index];
5937
5938 frame->colorimetry = colorimetry_val & NORMAL_COLORIMETRY_MASK;
5939 /*
5940 * ToDo: Extend it for ACE formats as well. Modify the infoframe
5941 * structure and extend it in drivers/video/hdmi
5942 */
5943 frame->extended_colorimetry = (colorimetry_val >> 2) &
5944 EXTENDED_COLORIMETRY_MASK;
5945}
4a46e5d2 5946EXPORT_SYMBOL(drm_hdmi_avi_infoframe_colorimetry);
0d68b887 5947
a2ce26f8
VS		 5948/**
5949 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
5950 * quantization range information
5951 * @frame: HDMI AVI infoframe
13d0add3 5952 * @connector: the connector
779c4c28 5953 * @mode: DRM display mode
a2ce26f8 5954 * @rgb_quant_range: RGB quantization range (Q)
a2ce26f8
VS		 5955 */
5956void
5957drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
192a3aa0 5958 const struct drm_connector *connector,
779c4c28 5959 const struct drm_display_mode *mode,
1581b2df 5960 enum hdmi_quantization_range rgb_quant_range)
a2ce26f8 5961{
1581b2df
VS		 5962 const struct drm_display_info *info = &connector->display_info;
5963
a2ce26f8
VS		 5964 /*
5965 * CEA-861:
5966 * "A Source shall not send a non-zero Q value that does not correspond
5967 * to the default RGB Quantization Range for the transmitted Picture
5968 * unless the Sink indicates support for the Q bit in a Video
5969 * Capabilities Data Block."
779c4c28
VS		 5970 *
5971 * HDMI 2.0 recommends sending non-zero Q when it does match the
5972 * default RGB quantization range for the mode, even when QS=0.
a2ce26f8 5973 */
1581b2df 5974 if (info->rgb_quant_range_selectable ||
779c4c28 5975 rgb_quant_range == drm_default_rgb_quant_range(mode))
a2ce26f8
VS		 5976 frame->quantization_range = rgb_quant_range;
5977 else
5978 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
fcc8a22c
VS		 5979
5980 /*
5981 * CEA-861-F:
5982 * "When transmitting any RGB colorimetry, the Source should set the
5983 * YQ-field to match the RGB Quantization Range being transmitted
5984 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
5985 * set YQ=1) and the Sink shall ignore the YQ-field."
9271c0ca
VS		 5986 *
5987 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
5988 * by non-zero YQ when receiving RGB. There doesn't seem to be any
5989 * good way to tell which version of CEA-861 the sink supports, so
5990 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
5991 * on on CEA-861-F.
fcc8a22c 5992 */
13d0add3 5993 if (!is_hdmi2_sink(connector) ||
9271c0ca 5994 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
fcc8a22c
VS		 5995 frame->ycc_quantization_range =
5996 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
5997 else
5998 frame->ycc_quantization_range =
5999 HDMI_YCC_QUANTIZATION_RANGE_FULL;
a2ce26f8
VS		 6000}
6001EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
6002
076d9a5d
VS		 6003/**
6004 * drm_hdmi_avi_infoframe_bars() - fill the HDMI AVI infoframe
6005 * bar information
6006 * @frame: HDMI AVI infoframe
6007 * @conn_state: connector state
6008 */
6009void
6010drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe *frame,
6011 const struct drm_connector_state *conn_state)
6012{
6013 frame->right_bar = conn_state->tv.margins.right;
6014 frame->left_bar = conn_state->tv.margins.left;
6015 frame->top_bar = conn_state->tv.margins.top;
6016 frame->bottom_bar = conn_state->tv.margins.bottom;
6017}
6018EXPORT_SYMBOL(drm_hdmi_avi_infoframe_bars);
6019
4eed4a0a
DL		 6020static enum hdmi_3d_structure
6021s3d_structure_from_display_mode(const struct drm_display_mode *mode)
6022{
6023 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
6024
6025 switch (layout) {
6026 case DRM_MODE_FLAG_3D_FRAME_PACKING:
6027 return HDMI_3D_STRUCTURE_FRAME_PACKING;
6028 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
6029 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
6030 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
6031 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
6032 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
6033 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
6034 case DRM_MODE_FLAG_3D_L_DEPTH:
6035 return HDMI_3D_STRUCTURE_L_DEPTH;
6036 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
6037 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
6038 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
6039 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
6040 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
6041 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
6042 default:
6043 return HDMI_3D_STRUCTURE_INVALID;
6044 }
6045}
6046
83dd0008
LD		 6047/**
6048 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
6049 * data from a DRM display mode
6050 * @frame: HDMI vendor infoframe
f1781e9b 6051 * @connector: the connector
83dd0008
LD		 6052 * @mode: DRM display mode
6053 *
6054 * Note that there's is a need to send HDMI vendor infoframes only when using a
6055 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
6056 * function will return -EINVAL, error that can be safely ignored.
6057 *
db6cf833 6058 * Return: 0 on success or a negative error code on failure.
83dd0008
LD		 6059 */
6060int
6061drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
192a3aa0 6062 const struct drm_connector *connector,
83dd0008
LD		 6063 const struct drm_display_mode *mode)
6064{
f1781e9b
VS		 6065 /*
6066 * FIXME: sil-sii8620 doesn't have a connector around when
6067 * we need one, so we have to be prepared for a NULL connector.
6068 */
6069 bool has_hdmi_infoframe = connector ?
6070 connector->display_info.has_hdmi_infoframe : false;
83dd0008 6071 int err;
83dd0008
LD		 6072
6073 if (!frame || !mode)
6074 return -EINVAL;
6075
f1781e9b
VS		 6076 if (!has_hdmi_infoframe)
6077 return -EINVAL;
6078
949561eb
VS		 6079 err = hdmi_vendor_infoframe_init(frame);
6080 if (err < 0)
6081 return err;
4eed4a0a 6082
f1781e9b
VS		 6083 /*
6084 * Even if it's not absolutely necessary to send the infoframe
6085 * (ie.vic==0 and s3d_struct==0) we will still send it if we
6086 * know that the sink can handle it. This is based on a
6087 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
0ae865ef 6088 * have trouble realizing that they should switch from 3D to 2D
f1781e9b
VS		 6089 * mode if the source simply stops sending the infoframe when
6090 * it wants to switch from 3D to 2D.
6091 */
949561eb 6092 frame->vic = drm_mode_hdmi_vic(connector, mode);
f1781e9b 6093 frame->s3d_struct = s3d_structure_from_display_mode(mode);
83dd0008
LD		 6094
6095 return 0;
6096}
6097EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
40d9b043 6098
7f261afd
VS		 6099static void drm_parse_tiled_block(struct drm_connector *connector,
6100 const struct displayid_block *block)
5e546cd5 6101{
092c367a 6102 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
5e546cd5
DA		 6103 u16 w, h;
6104 u8 tile_v_loc, tile_h_loc;
6105 u8 num_v_tile, num_h_tile;
6106 struct drm_tile_group *tg;
6107
6108 w = tile->tile_size[0] | tile->tile_size[1] << 8;
6109 h = tile->tile_size[2] | tile->tile_size[3] << 8;
6110
6111 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
6112 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
6113 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
6114 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
6115
6116 connector->has_tile = true;
6117 if (tile->tile_cap & 0x80)
6118 connector->tile_is_single_monitor = true;
6119
6120 connector->num_h_tile = num_h_tile + 1;
6121 connector->num_v_tile = num_v_tile + 1;
6122 connector->tile_h_loc = tile_h_loc;
6123 connector->tile_v_loc = tile_v_loc;
6124 connector->tile_h_size = w + 1;
6125 connector->tile_v_size = h + 1;
6126
6127 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
6128 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
6129 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
6130 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
6131 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
6132
6133 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
392f9fcb 6134 if (!tg)
5e546cd5 6135 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
5e546cd5 6136 if (!tg)
7f261afd 6137 return;
5e546cd5
DA		 6138
6139 if (connector->tile_group != tg) {
6140 /* if we haven't got a pointer,
6141 take the reference, drop ref to old tile group */
392f9fcb 6142 if (connector->tile_group)
5e546cd5 6143 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5e546cd5 6144 connector->tile_group = tg;
392f9fcb 6145 } else {
5e546cd5
DA		 6146 /* if same tile group, then release the ref we just took. */
6147 drm_mode_put_tile_group(connector->dev, tg);
392f9fcb 6148 }
5e546cd5
DA		 6149}
6150
092c367a
VS		 6151void drm_update_tile_info(struct drm_connector *connector,
6152 const struct edid *edid)
40d9b043 6153{
bfd4e192
JN		 6154 const struct displayid_block *block;
6155 struct displayid_iter iter;
36881184 6156
40d9b043 6157 connector->has_tile = false;
7f261afd 6158
bfd4e192
JN		 6159 displayid_iter_edid_begin(edid, &iter);
6160 displayid_iter_for_each(block, &iter) {
6161 if (block->tag == DATA_BLOCK_TILED_DISPLAY)
6162 drm_parse_tiled_block(connector, block);
40d9b043 6163 }
bfd4e192 6164 displayid_iter_end(&iter);
40d9b043 6165
7f261afd 6166 if (!connector->has_tile && connector->tile_group) {
40d9b043
DA		 6167 drm_mode_put_tile_group(connector->dev, connector->tile_group);
6168 connector->tile_group = NULL;
6169 }
40d9b043 6170}
Linux 6.x block layer and io_uring tree(s)