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Merge tag 'mediatek-drm-fixes-5.15' of https://git.kernel.org/pub/scm/linux/kernel...
[linux-2.6-block.git] / drivers / gpu / drm / drm_edid.c
CommitLineData
f453ba04
DA		 1/*
2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
61e57a8d 5 * Copyright 2010 Red Hat, Inc.
f453ba04
DA		 6 *
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
8 * FB layer.
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 */
9c79edec 30
10a85120 31#include <linux/hdmi.h>
f453ba04 32#include <linux/i2c.h>
9c79edec 33#include <linux/kernel.h>
47819ba2 34#include <linux/module.h>
36b73b05 35#include <linux/pci.h>
9c79edec 36#include <linux/slab.h>
5cb8eaa2 37#include <linux/vga_switcheroo.h>
9c79edec
JN		 38
39#include <drm/drm_displayid.h>
40#include <drm/drm_drv.h>
760285e7 41#include <drm/drm_edid.h>
9338203c 42#include <drm/drm_encoder.h>
9c79edec 43#include <drm/drm_print.h>
62c58af3 44#include <drm/drm_scdc_helper.h>
f453ba04 45
969218fe
TI		 46#include "drm_crtc_internal.h"
47
13931579
AJ		 48#define version_greater(edid, maj, min) \
49 (((edid)->version > (maj)) || \
50 ((edid)->version == (maj) && (edid)->revision > (min)))
f453ba04 51
d1ff6409
AJ		 52#define EDID_EST_TIMINGS 16
53#define EDID_STD_TIMINGS 8
54#define EDID_DETAILED_TIMINGS 4
f453ba04
DA		 55
56/*
57 * EDID blocks out in the wild have a variety of bugs, try to collect
58 * them here (note that userspace may work around broken monitors first,
59 * but fixes should make their way here so that the kernel "just works"
60 * on as many displays as possible).
61 */
62
63/* First detailed mode wrong, use largest 60Hz mode */
64#define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
65/* Reported 135MHz pixel clock is too high, needs adjustment */
66#define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
67/* Prefer the largest mode at 75 Hz */
68#define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
69/* Detail timing is in cm not mm */
70#define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
71/* Detailed timing descriptors have bogus size values, so just take the
72 * maximum size and use that.
73 */
74#define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
f453ba04
DA		 75/* use +hsync +vsync for detailed mode */
76#define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
bc42aabc
AJ		 77/* Force reduced-blanking timings for detailed modes */
78#define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
49d45a31
RM		 79/* Force 8bpc */
80#define EDID_QUIRK_FORCE_8BPC (1 << 8)
bc5b9641
MK		 81/* Force 12bpc */
82#define EDID_QUIRK_FORCE_12BPC (1 << 9)
e10aec65
MK		 83/* Force 6bpc */
84#define EDID_QUIRK_FORCE_6BPC (1 << 10)
e345da82
MK		 85/* Force 10bpc */
86#define EDID_QUIRK_FORCE_10BPC (1 << 11)
66660d4c
DA		 87/* Non desktop display (i.e. HMD) */
88#define EDID_QUIRK_NON_DESKTOP (1 << 12)
3c537889 89
13931579
AJ		 90struct detailed_mode_closure {
91 struct drm_connector *connector;
92 struct edid *edid;
93 bool preferred;
94 u32 quirks;
95 int modes;
96};
f453ba04 97
5c61259e
ZY		 98#define LEVEL_DMT 0
99#define LEVEL_GTF 1
7a374350
AJ		 100#define LEVEL_GTF2 2
101#define LEVEL_CVT 3
5c61259e 102
23c4cfbd 103static const struct edid_quirk {
c51a3fd6 104 char vendor[4];
f453ba04
DA		 105 int product_id;
106 u32 quirks;
107} edid_quirk_list[] = {
108 /* Acer AL1706 */
109 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
110 /* Acer F51 */
111 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
f453ba04 112
e10aec65
MK		 113 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
114 { "AEO", 0, EDID_QUIRK_FORCE_6BPC },
115
0711a43b
KHF		 116 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
117 { "BOE", 0x78b, EDID_QUIRK_FORCE_6BPC },
118
06998a75
KHF		 119 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
120 { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC },
121
25da7504
KHF		 122 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
123 { "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC },
124
922dceff
LS		 125 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
126 { "BOE", 0x0771, EDID_QUIRK_FORCE_6BPC },
127
f453ba04
DA		 128 /* Belinea 10 15 55 */
129 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
130 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
131
132 /* Envision Peripherals, Inc. EN-7100e */
133 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
ba1163de
AJ		 134 /* Envision EN2028 */
135 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
f453ba04
DA		 136
137 /* Funai Electronics PM36B */
138 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
139 EDID_QUIRK_DETAILED_IN_CM },
140
e345da82
MK		 141 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
142 { "LGD", 764, EDID_QUIRK_FORCE_10BPC },
143
f453ba04
DA		 144 /* LG Philips LCD LP154W01-A5 */
145 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
146 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
147
f453ba04
DA		 148 /* Samsung SyncMaster 205BW. Note: irony */
149 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
150 /* Samsung SyncMaster 22[5-6]BW */
151 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
152 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
bc42aabc 153
bc5b9641
MK		 154 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
155 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
156
bc42aabc
AJ		 157 /* ViewSonic VA2026w */
158 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
118bdbd8
AD		 159
160 /* Medion MD 30217 PG */
161 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
49d45a31 162
11bcf5f7
KHF		 163 /* Lenovo G50 */
164 { "SDC", 18514, EDID_QUIRK_FORCE_6BPC },
165
49d45a31
RM		 166 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
167 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
36fc5797
TV		 168
169 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
170 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC },
acb1d8ee 171
30d62d44
AR		 172 /* Valve Index Headset */
173 { "VLV", 0x91a8, EDID_QUIRK_NON_DESKTOP },
174 { "VLV", 0x91b0, EDID_QUIRK_NON_DESKTOP },
175 { "VLV", 0x91b1, EDID_QUIRK_NON_DESKTOP },
176 { "VLV", 0x91b2, EDID_QUIRK_NON_DESKTOP },
177 { "VLV", 0x91b3, EDID_QUIRK_NON_DESKTOP },
178 { "VLV", 0x91b4, EDID_QUIRK_NON_DESKTOP },
179 { "VLV", 0x91b5, EDID_QUIRK_NON_DESKTOP },
180 { "VLV", 0x91b6, EDID_QUIRK_NON_DESKTOP },
181 { "VLV", 0x91b7, EDID_QUIRK_NON_DESKTOP },
182 { "VLV", 0x91b8, EDID_QUIRK_NON_DESKTOP },
183 { "VLV", 0x91b9, EDID_QUIRK_NON_DESKTOP },
184 { "VLV", 0x91ba, EDID_QUIRK_NON_DESKTOP },
185 { "VLV", 0x91bb, EDID_QUIRK_NON_DESKTOP },
186 { "VLV", 0x91bc, EDID_QUIRK_NON_DESKTOP },
187 { "VLV", 0x91bd, EDID_QUIRK_NON_DESKTOP },
188 { "VLV", 0x91be, EDID_QUIRK_NON_DESKTOP },
189 { "VLV", 0x91bf, EDID_QUIRK_NON_DESKTOP },
190
6931317c 191 /* HTC Vive and Vive Pro VR Headsets */
acb1d8ee 192 { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP },
6931317c 193 { "HVR", 0xaa02, EDID_QUIRK_NON_DESKTOP },
b3b12ea3 194
5a3f6108 195 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */
b3b12ea3
PZ		 196 { "OVR", 0x0001, EDID_QUIRK_NON_DESKTOP },
197 { "OVR", 0x0003, EDID_QUIRK_NON_DESKTOP },
198 { "OVR", 0x0004, EDID_QUIRK_NON_DESKTOP },
5a3f6108 199 { "OVR", 0x0012, EDID_QUIRK_NON_DESKTOP },
90eda8fc
PZ		 200
201 /* Windows Mixed Reality Headsets */
202 { "ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP },
203 { "HPN", 0x3515, EDID_QUIRK_NON_DESKTOP },
204 { "LEN", 0x0408, EDID_QUIRK_NON_DESKTOP },
205 { "LEN", 0xb800, EDID_QUIRK_NON_DESKTOP },
206 { "FUJ", 0x1970, EDID_QUIRK_NON_DESKTOP },
207 { "DEL", 0x7fce, EDID_QUIRK_NON_DESKTOP },
208 { "SEC", 0x144a, EDID_QUIRK_NON_DESKTOP },
209 { "AUS", 0xc102, EDID_QUIRK_NON_DESKTOP },
ccffc9eb
PZ		 210
211 /* Sony PlayStation VR Headset */
212 { "SNY", 0x0704, EDID_QUIRK_NON_DESKTOP },
29054230
RP		 213
214 /* Sensics VR Headsets */
215 { "SEN", 0x1019, EDID_QUIRK_NON_DESKTOP },
216
217 /* OSVR HDK and HDK2 VR Headsets */
218 { "SVR", 0x1019, EDID_QUIRK_NON_DESKTOP },
f453ba04
DA		 219};
220
a6b21831
TR		 221/*
222 * Autogenerated from the DMT spec.
223 * This table is copied from xfree86/modes/xf86EdidModes.c.
224 */
225static const struct drm_display_mode drm_dmt_modes[] = {
24b856b1 226 /* 0x01 - 640x350@85Hz */
a6b21831
TR		 227 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
228 736, 832, 0, 350, 382, 385, 445, 0,
229 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 230 /* 0x02 - 640x400@85Hz */
a6b21831
TR		 231 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
232 736, 832, 0, 400, 401, 404, 445, 0,
233 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 234 /* 0x03 - 720x400@85Hz */
a6b21831
TR		 235 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
236 828, 936, 0, 400, 401, 404, 446, 0,
237 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 238 /* 0x04 - 640x480@60Hz */
a6b21831 239 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
fcf22d05 240 752, 800, 0, 480, 490, 492, 525, 0,
a6b21831 241 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 242 /* 0x05 - 640x480@72Hz */
a6b21831
TR		 243 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
244 704, 832, 0, 480, 489, 492, 520, 0,
245 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 246 /* 0x06 - 640x480@75Hz */
a6b21831
TR		 247 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
248 720, 840, 0, 480, 481, 484, 500, 0,
249 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 250 /* 0x07 - 640x480@85Hz */
a6b21831
TR		 251 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
252 752, 832, 0, 480, 481, 484, 509, 0,
253 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 254 /* 0x08 - 800x600@56Hz */
a6b21831
TR		 255 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
256 896, 1024, 0, 600, 601, 603, 625, 0,
257 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 258 /* 0x09 - 800x600@60Hz */
a6b21831
TR		 259 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
260 968, 1056, 0, 600, 601, 605, 628, 0,
261 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 262 /* 0x0a - 800x600@72Hz */
a6b21831
TR		 263 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
264 976, 1040, 0, 600, 637, 643, 666, 0,
265 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 266 /* 0x0b - 800x600@75Hz */
a6b21831
TR		 267 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
268 896, 1056, 0, 600, 601, 604, 625, 0,
269 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 270 /* 0x0c - 800x600@85Hz */
a6b21831
TR		 271 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
272 896, 1048, 0, 600, 601, 604, 631, 0,
273 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 274 /* 0x0d - 800x600@120Hz RB */
a6b21831
TR		 275 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
276 880, 960, 0, 600, 603, 607, 636, 0,
277 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 278 /* 0x0e - 848x480@60Hz */
a6b21831
TR		 279 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
280 976, 1088, 0, 480, 486, 494, 517, 0,
281 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 282 /* 0x0f - 1024x768@43Hz, interlace */
a6b21831 283 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
735b100f 284 1208, 1264, 0, 768, 768, 776, 817, 0,
a6b21831 285 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
fcf22d05 286 DRM_MODE_FLAG_INTERLACE) },
24b856b1 287 /* 0x10 - 1024x768@60Hz */
a6b21831
TR		 288 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
289 1184, 1344, 0, 768, 771, 777, 806, 0,
290 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 291 /* 0x11 - 1024x768@70Hz */
a6b21831
TR		 292 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
293 1184, 1328, 0, 768, 771, 777, 806, 0,
294 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 295 /* 0x12 - 1024x768@75Hz */
a6b21831
TR		 296 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
297 1136, 1312, 0, 768, 769, 772, 800, 0,
298 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 299 /* 0x13 - 1024x768@85Hz */
a6b21831
TR		 300 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
301 1168, 1376, 0, 768, 769, 772, 808, 0,
302 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 303 /* 0x14 - 1024x768@120Hz RB */
a6b21831
TR		 304 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
305 1104, 1184, 0, 768, 771, 775, 813, 0,
306 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 307 /* 0x15 - 1152x864@75Hz */
a6b21831
TR		 308 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
309 1344, 1600, 0, 864, 865, 868, 900, 0,
310 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
bfcd74d2
VS		 311 /* 0x55 - 1280x720@60Hz */
312 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
313 1430, 1650, 0, 720, 725, 730, 750, 0,
314 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 315 /* 0x16 - 1280x768@60Hz RB */
a6b21831
TR		 316 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
317 1360, 1440, 0, 768, 771, 778, 790, 0,
318 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 319 /* 0x17 - 1280x768@60Hz */
a6b21831
TR		 320 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
321 1472, 1664, 0, 768, 771, 778, 798, 0,
322 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 323 /* 0x18 - 1280x768@75Hz */
a6b21831
TR		 324 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
325 1488, 1696, 0, 768, 771, 778, 805, 0,
fcf22d05 326 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 327 /* 0x19 - 1280x768@85Hz */
a6b21831
TR		 328 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
329 1496, 1712, 0, 768, 771, 778, 809, 0,
330 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 331 /* 0x1a - 1280x768@120Hz RB */
a6b21831
TR		 332 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
333 1360, 1440, 0, 768, 771, 778, 813, 0,
334 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 335 /* 0x1b - 1280x800@60Hz RB */
a6b21831
TR		 336 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
337 1360, 1440, 0, 800, 803, 809, 823, 0,
338 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 339 /* 0x1c - 1280x800@60Hz */
a6b21831
TR		 340 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
341 1480, 1680, 0, 800, 803, 809, 831, 0,
fcf22d05 342 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 343 /* 0x1d - 1280x800@75Hz */
a6b21831
TR		 344 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
345 1488, 1696, 0, 800, 803, 809, 838, 0,
346 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 347 /* 0x1e - 1280x800@85Hz */
a6b21831
TR		 348 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
349 1496, 1712, 0, 800, 803, 809, 843, 0,
350 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 351 /* 0x1f - 1280x800@120Hz RB */
a6b21831
TR		 352 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
353 1360, 1440, 0, 800, 803, 809, 847, 0,
354 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 355 /* 0x20 - 1280x960@60Hz */
a6b21831
TR		 356 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
357 1488, 1800, 0, 960, 961, 964, 1000, 0,
358 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 359 /* 0x21 - 1280x960@85Hz */
a6b21831
TR		 360 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
361 1504, 1728, 0, 960, 961, 964, 1011, 0,
362 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 363 /* 0x22 - 1280x960@120Hz RB */
a6b21831
TR		 364 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
365 1360, 1440, 0, 960, 963, 967, 1017, 0,
366 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 367 /* 0x23 - 1280x1024@60Hz */
a6b21831
TR		 368 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
369 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
370 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 371 /* 0x24 - 1280x1024@75Hz */
a6b21831
TR		 372 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
373 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
374 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 375 /* 0x25 - 1280x1024@85Hz */
a6b21831
TR		 376 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
377 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
378 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 379 /* 0x26 - 1280x1024@120Hz RB */
a6b21831
TR		 380 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
381 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
382 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 383 /* 0x27 - 1360x768@60Hz */
a6b21831
TR		 384 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
385 1536, 1792, 0, 768, 771, 777, 795, 0,
386 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 387 /* 0x28 - 1360x768@120Hz RB */
a6b21831
TR		 388 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
389 1440, 1520, 0, 768, 771, 776, 813, 0,
390 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 391 /* 0x51 - 1366x768@60Hz */
392 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
393 1579, 1792, 0, 768, 771, 774, 798, 0,
394 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
395 /* 0x56 - 1366x768@60Hz */
396 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
397 1436, 1500, 0, 768, 769, 772, 800, 0,
398 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 399 /* 0x29 - 1400x1050@60Hz RB */
a6b21831
TR		 400 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
401 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
402 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 403 /* 0x2a - 1400x1050@60Hz */
a6b21831
TR		 404 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
405 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
406 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 407 /* 0x2b - 1400x1050@75Hz */
a6b21831
TR		 408 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
409 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
410 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 411 /* 0x2c - 1400x1050@85Hz */
a6b21831
TR		 412 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
413 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
414 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 415 /* 0x2d - 1400x1050@120Hz RB */
a6b21831
TR		 416 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
417 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
418 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 419 /* 0x2e - 1440x900@60Hz RB */
a6b21831
TR		 420 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
421 1520, 1600, 0, 900, 903, 909, 926, 0,
422 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 423 /* 0x2f - 1440x900@60Hz */
a6b21831
TR		 424 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
425 1672, 1904, 0, 900, 903, 909, 934, 0,
426 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 427 /* 0x30 - 1440x900@75Hz */
a6b21831
TR		 428 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
429 1688, 1936, 0, 900, 903, 909, 942, 0,
430 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 431 /* 0x31 - 1440x900@85Hz */
a6b21831
TR		 432 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
433 1696, 1952, 0, 900, 903, 909, 948, 0,
434 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 435 /* 0x32 - 1440x900@120Hz RB */
a6b21831
TR		 436 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
437 1520, 1600, 0, 900, 903, 909, 953, 0,
438 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 439 /* 0x53 - 1600x900@60Hz */
440 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
441 1704, 1800, 0, 900, 901, 904, 1000, 0,
442 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 443 /* 0x33 - 1600x1200@60Hz */
a6b21831
TR		 444 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
445 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
446 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 447 /* 0x34 - 1600x1200@65Hz */
a6b21831
TR		 448 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
449 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
450 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 451 /* 0x35 - 1600x1200@70Hz */
a6b21831
TR		 452 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
453 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
454 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 455 /* 0x36 - 1600x1200@75Hz */
a6b21831
TR		 456 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
457 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
458 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 459 /* 0x37 - 1600x1200@85Hz */
a6b21831
TR		 460 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
461 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
462 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 463 /* 0x38 - 1600x1200@120Hz RB */
a6b21831
TR		 464 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
465 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
466 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 467 /* 0x39 - 1680x1050@60Hz RB */
a6b21831
TR		 468 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
469 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
470 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 471 /* 0x3a - 1680x1050@60Hz */
a6b21831
TR		 472 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
473 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
474 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 475 /* 0x3b - 1680x1050@75Hz */
a6b21831
TR		 476 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
477 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
478 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 479 /* 0x3c - 1680x1050@85Hz */
a6b21831
TR		 480 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
481 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
482 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 483 /* 0x3d - 1680x1050@120Hz RB */
a6b21831
TR		 484 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
485 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
486 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 487 /* 0x3e - 1792x1344@60Hz */
a6b21831
TR		 488 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
489 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
490 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 491 /* 0x3f - 1792x1344@75Hz */
a6b21831
TR		 492 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
493 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
494 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 495 /* 0x40 - 1792x1344@120Hz RB */
a6b21831
TR		 496 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
497 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
498 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 499 /* 0x41 - 1856x1392@60Hz */
a6b21831
TR		 500 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
501 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
502 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 503 /* 0x42 - 1856x1392@75Hz */
a6b21831 504 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
fcf22d05 505 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
a6b21831 506 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 507 /* 0x43 - 1856x1392@120Hz RB */
a6b21831
TR		 508 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
509 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
510 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 511 /* 0x52 - 1920x1080@60Hz */
512 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
513 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
514 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 515 /* 0x44 - 1920x1200@60Hz RB */
a6b21831
TR		 516 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
517 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
518 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 519 /* 0x45 - 1920x1200@60Hz */
a6b21831
TR		 520 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
521 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
522 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 523 /* 0x46 - 1920x1200@75Hz */
a6b21831
TR		 524 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
525 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
526 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 527 /* 0x47 - 1920x1200@85Hz */
a6b21831
TR		 528 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
529 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
530 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 531 /* 0x48 - 1920x1200@120Hz RB */
a6b21831
TR		 532 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
533 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
534 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 535 /* 0x49 - 1920x1440@60Hz */
a6b21831
TR		 536 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
537 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
538 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 539 /* 0x4a - 1920x1440@75Hz */
a6b21831
TR		 540 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
541 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
542 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 543 /* 0x4b - 1920x1440@120Hz RB */
a6b21831
TR		 544 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
545 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
546 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 547 /* 0x54 - 2048x1152@60Hz */
548 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
549 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
550 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 551 /* 0x4c - 2560x1600@60Hz RB */
a6b21831
TR		 552 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
553 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
554 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 555 /* 0x4d - 2560x1600@60Hz */
a6b21831
TR		 556 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
557 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
558 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 559 /* 0x4e - 2560x1600@75Hz */
a6b21831
TR		 560 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
561 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
562 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 563 /* 0x4f - 2560x1600@85Hz */
a6b21831
TR		 564 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
565 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
566 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 567 /* 0x50 - 2560x1600@120Hz RB */
a6b21831
TR		 568 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
569 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
570 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 571 /* 0x57 - 4096x2160@60Hz RB */
572 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
573 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
574 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
575 /* 0x58 - 4096x2160@59.94Hz RB */
576 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
577 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
578 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
a6b21831
TR		 579};
580
e7bfa5c4
VS		 581/*
582 * These more or less come from the DMT spec. The 720x400 modes are
583 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
584 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
585 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
586 * mode.
587 *
588 * The DMT modes have been fact-checked; the rest are mild guesses.
589 */
a6b21831
TR		 590static const struct drm_display_mode edid_est_modes[] = {
591 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
592 968, 1056, 0, 600, 601, 605, 628, 0,
593 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
594 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
595 896, 1024, 0, 600, 601, 603, 625, 0,
596 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
597 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
598 720, 840, 0, 480, 481, 484, 500, 0,
599 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
600 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
87707cfd 601 704, 832, 0, 480, 489, 492, 520, 0,
a6b21831
TR		 602 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
603 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
604 768, 864, 0, 480, 483, 486, 525, 0,
605 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
87707cfd 606 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
a6b21831
TR		 607 752, 800, 0, 480, 490, 492, 525, 0,
608 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
609 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
610 846, 900, 0, 400, 421, 423, 449, 0,
611 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
612 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
613 846, 900, 0, 400, 412, 414, 449, 0,
614 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
615 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
616 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
617 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
87707cfd 618 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
a6b21831
TR		 619 1136, 1312, 0, 768, 769, 772, 800, 0,
620 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
621 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
622 1184, 1328, 0, 768, 771, 777, 806, 0,
623 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
624 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
625 1184, 1344, 0, 768, 771, 777, 806, 0,
626 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
627 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
628 1208, 1264, 0, 768, 768, 776, 817, 0,
629 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
630 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
631 928, 1152, 0, 624, 625, 628, 667, 0,
632 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
633 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
634 896, 1056, 0, 600, 601, 604, 625, 0,
635 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
636 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
637 976, 1040, 0, 600, 637, 643, 666, 0,
638 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
639 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
640 1344, 1600, 0, 864, 865, 868, 900, 0,
641 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
642};
643
644struct minimode {
645 short w;
646 short h;
647 short r;
648 short rb;
649};
650
651static const struct minimode est3_modes[] = {
652 /* byte 6 */
653 { 640, 350, 85, 0 },
654 { 640, 400, 85, 0 },
655 { 720, 400, 85, 0 },
656 { 640, 480, 85, 0 },
657 { 848, 480, 60, 0 },
658 { 800, 600, 85, 0 },
659 { 1024, 768, 85, 0 },
660 { 1152, 864, 75, 0 },
661 /* byte 7 */
662 { 1280, 768, 60, 1 },
663 { 1280, 768, 60, 0 },
664 { 1280, 768, 75, 0 },
665 { 1280, 768, 85, 0 },
666 { 1280, 960, 60, 0 },
667 { 1280, 960, 85, 0 },
668 { 1280, 1024, 60, 0 },
669 { 1280, 1024, 85, 0 },
670 /* byte 8 */
671 { 1360, 768, 60, 0 },
672 { 1440, 900, 60, 1 },
673 { 1440, 900, 60, 0 },
674 { 1440, 900, 75, 0 },
675 { 1440, 900, 85, 0 },
676 { 1400, 1050, 60, 1 },
677 { 1400, 1050, 60, 0 },
678 { 1400, 1050, 75, 0 },
679 /* byte 9 */
680 { 1400, 1050, 85, 0 },
681 { 1680, 1050, 60, 1 },
682 { 1680, 1050, 60, 0 },
683 { 1680, 1050, 75, 0 },
684 { 1680, 1050, 85, 0 },
685 { 1600, 1200, 60, 0 },
686 { 1600, 1200, 65, 0 },
687 { 1600, 1200, 70, 0 },
688 /* byte 10 */
689 { 1600, 1200, 75, 0 },
690 { 1600, 1200, 85, 0 },
691 { 1792, 1344, 60, 0 },
c068b32a 692 { 1792, 1344, 75, 0 },
a6b21831
TR		 693 { 1856, 1392, 60, 0 },
694 { 1856, 1392, 75, 0 },
695 { 1920, 1200, 60, 1 },
696 { 1920, 1200, 60, 0 },
697 /* byte 11 */
698 { 1920, 1200, 75, 0 },
699 { 1920, 1200, 85, 0 },
700 { 1920, 1440, 60, 0 },
701 { 1920, 1440, 75, 0 },
702};
703
704static const struct minimode extra_modes[] = {
705 { 1024, 576, 60, 0 },
706 { 1366, 768, 60, 0 },
707 { 1600, 900, 60, 0 },
708 { 1680, 945, 60, 0 },
709 { 1920, 1080, 60, 0 },
710 { 2048, 1152, 60, 0 },
711 { 2048, 1536, 60, 0 },
712};
713
714/*
7befe621 715 * From CEA/CTA-861 spec.
d9278b4c 716 *
7befe621 717 * Do not access directly, instead always use cea_mode_for_vic().
a6b21831 718 */
8c1b2bd9 719static const struct drm_display_mode edid_cea_modes_1[] = {
78691960 720 /* 1 - 640x480@60Hz 4:3 */
a6b21831
TR		 721 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
722 752, 800, 0, 480, 490, 492, 525, 0,
ee7925bb 723 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 724 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 725 /* 2 - 720x480@60Hz 4:3 */
a6b21831
TR		 726 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
727 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 728 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 729 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 730 /* 3 - 720x480@60Hz 16:9 */
a6b21831
TR		 731 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
732 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 733 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 734 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 735 /* 4 - 1280x720@60Hz 16:9 */
a6b21831
TR		 736 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
737 1430, 1650, 0, 720, 725, 730, 750, 0,
ee7925bb 738 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 739 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 740 /* 5 - 1920x1080i@60Hz 16:9 */
a6b21831
TR		 741 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
742 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
743 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 744 DRM_MODE_FLAG_INTERLACE),
0425662f 745 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 746 /* 6 - 720(1440)x480i@60Hz 4:3 */
fb01d280
CT		 747 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
748 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 749 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 750 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 751 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 752 /* 7 - 720(1440)x480i@60Hz 16:9 */
fb01d280
CT		 753 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
754 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 755 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 756 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 757 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 758 /* 8 - 720(1440)x240@60Hz 4:3 */
fb01d280
CT		 759 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
760 801, 858, 0, 240, 244, 247, 262, 0,
a6b21831 761 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 762 DRM_MODE_FLAG_DBLCLK),
0425662f 763 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 764 /* 9 - 720(1440)x240@60Hz 16:9 */
fb01d280
CT		 765 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
766 801, 858, 0, 240, 244, 247, 262, 0,
a6b21831 767 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 768 DRM_MODE_FLAG_DBLCLK),
0425662f 769 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 770 /* 10 - 2880x480i@60Hz 4:3 */
a6b21831
TR		 771 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
772 3204, 3432, 0, 480, 488, 494, 525, 0,
773 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 774 DRM_MODE_FLAG_INTERLACE),
0425662f 775 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 776 /* 11 - 2880x480i@60Hz 16:9 */
a6b21831
TR		 777 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
778 3204, 3432, 0, 480, 488, 494, 525, 0,
779 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 780 DRM_MODE_FLAG_INTERLACE),
0425662f 781 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 782 /* 12 - 2880x240@60Hz 4:3 */
a6b21831
TR		 783 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
784 3204, 3432, 0, 240, 244, 247, 262, 0,
ee7925bb 785 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 786 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 787 /* 13 - 2880x240@60Hz 16:9 */
a6b21831
TR		 788 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
789 3204, 3432, 0, 240, 244, 247, 262, 0,
ee7925bb 790 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 791 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 792 /* 14 - 1440x480@60Hz 4:3 */
a6b21831
TR		 793 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
794 1596, 1716, 0, 480, 489, 495, 525, 0,
ee7925bb 795 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 796 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 797 /* 15 - 1440x480@60Hz 16:9 */
a6b21831
TR		 798 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
799 1596, 1716, 0, 480, 489, 495, 525, 0,
ee7925bb 800 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 801 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 802 /* 16 - 1920x1080@60Hz 16:9 */
a6b21831
TR		 803 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
804 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 805 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 806 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 807 /* 17 - 720x576@50Hz 4:3 */
a6b21831
TR		 808 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
809 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 810 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 811 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 812 /* 18 - 720x576@50Hz 16:9 */
a6b21831
TR		 813 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
814 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 815 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 816 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 817 /* 19 - 1280x720@50Hz 16:9 */
a6b21831
TR		 818 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
819 1760, 1980, 0, 720, 725, 730, 750, 0,
ee7925bb 820 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 821 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 822 /* 20 - 1920x1080i@50Hz 16:9 */
a6b21831
TR		 823 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
824 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
825 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 826 DRM_MODE_FLAG_INTERLACE),
0425662f 827 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 828 /* 21 - 720(1440)x576i@50Hz 4:3 */
fb01d280
CT		 829 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
830 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 831 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 832 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 833 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 834 /* 22 - 720(1440)x576i@50Hz 16:9 */
fb01d280
CT		 835 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
836 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 837 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 838 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 839 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 840 /* 23 - 720(1440)x288@50Hz 4:3 */
fb01d280
CT		 841 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
842 795, 864, 0, 288, 290, 293, 312, 0,
a6b21831 843 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 844 DRM_MODE_FLAG_DBLCLK),
0425662f 845 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 846 /* 24 - 720(1440)x288@50Hz 16:9 */
fb01d280
CT		 847 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
848 795, 864, 0, 288, 290, 293, 312, 0,
a6b21831 849 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 850 DRM_MODE_FLAG_DBLCLK),
0425662f 851 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 852 /* 25 - 2880x576i@50Hz 4:3 */
a6b21831
TR		 853 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
854 3180, 3456, 0, 576, 580, 586, 625, 0,
855 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 856 DRM_MODE_FLAG_INTERLACE),
0425662f 857 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 858 /* 26 - 2880x576i@50Hz 16:9 */
a6b21831
TR		 859 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
860 3180, 3456, 0, 576, 580, 586, 625, 0,
861 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 862 DRM_MODE_FLAG_INTERLACE),
0425662f 863 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 864 /* 27 - 2880x288@50Hz 4:3 */
a6b21831
TR		 865 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
866 3180, 3456, 0, 288, 290, 293, 312, 0,
ee7925bb 867 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 868 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 869 /* 28 - 2880x288@50Hz 16:9 */
a6b21831
TR		 870 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
871 3180, 3456, 0, 288, 290, 293, 312, 0,
ee7925bb 872 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 873 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 874 /* 29 - 1440x576@50Hz 4:3 */
a6b21831
TR		 875 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
876 1592, 1728, 0, 576, 581, 586, 625, 0,
ee7925bb 877 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 878 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 879 /* 30 - 1440x576@50Hz 16:9 */
a6b21831
TR		 880 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
881 1592, 1728, 0, 576, 581, 586, 625, 0,
ee7925bb 882 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 883 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 884 /* 31 - 1920x1080@50Hz 16:9 */
a6b21831
TR		 885 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
886 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 887 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 888 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 889 /* 32 - 1920x1080@24Hz 16:9 */
a6b21831
TR		 890 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
891 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 892 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 893 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 894 /* 33 - 1920x1080@25Hz 16:9 */
a6b21831
TR		 895 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
896 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 897 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 898 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 899 /* 34 - 1920x1080@30Hz 16:9 */
a6b21831
TR		 900 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
901 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 902 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 903 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 904 /* 35 - 2880x480@60Hz 4:3 */
a6b21831
TR		 905 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
906 3192, 3432, 0, 480, 489, 495, 525, 0,
ee7925bb 907 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 908 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 909 /* 36 - 2880x480@60Hz 16:9 */
a6b21831
TR		 910 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
911 3192, 3432, 0, 480, 489, 495, 525, 0,
ee7925bb 912 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 913 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 914 /* 37 - 2880x576@50Hz 4:3 */
a6b21831
TR		 915 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
916 3184, 3456, 0, 576, 581, 586, 625, 0,
ee7925bb 917 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 918 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 919 /* 38 - 2880x576@50Hz 16:9 */
a6b21831
TR		 920 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
921 3184, 3456, 0, 576, 581, 586, 625, 0,
ee7925bb 922 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 923 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 924 /* 39 - 1920x1080i@50Hz 16:9 */
a6b21831
TR		 925 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
926 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
927 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 928 DRM_MODE_FLAG_INTERLACE),
0425662f 929 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 930 /* 40 - 1920x1080i@100Hz 16:9 */
a6b21831
TR		 931 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
932 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
933 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 934 DRM_MODE_FLAG_INTERLACE),
0425662f 935 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 936 /* 41 - 1280x720@100Hz 16:9 */
a6b21831
TR		 937 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
938 1760, 1980, 0, 720, 725, 730, 750, 0,
ee7925bb 939 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 940 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 941 /* 42 - 720x576@100Hz 4:3 */
a6b21831
TR		 942 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
943 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 944 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 945 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 946 /* 43 - 720x576@100Hz 16:9 */
a6b21831
TR		 947 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
948 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 949 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 950 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 951 /* 44 - 720(1440)x576i@100Hz 4:3 */
fb01d280
CT		 952 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
953 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 954 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 955 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 956 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 957 /* 45 - 720(1440)x576i@100Hz 16:9 */
fb01d280
CT		 958 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
959 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 960 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 961 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 962 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 963 /* 46 - 1920x1080i@120Hz 16:9 */
a6b21831
TR		 964 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
965 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
966 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 967 DRM_MODE_FLAG_INTERLACE),
0425662f 968 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 969 /* 47 - 1280x720@120Hz 16:9 */
a6b21831
TR		 970 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
971 1430, 1650, 0, 720, 725, 730, 750, 0,
ee7925bb 972 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 973 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 974 /* 48 - 720x480@120Hz 4:3 */
a6b21831
TR		 975 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
976 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 977 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 978 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 979 /* 49 - 720x480@120Hz 16:9 */
a6b21831
TR		 980 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
981 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 982 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 983 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 984 /* 50 - 720(1440)x480i@120Hz 4:3 */
fb01d280
CT		 985 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
986 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 987 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 988 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 989 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 990 /* 51 - 720(1440)x480i@120Hz 16:9 */
fb01d280
CT		 991 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
992 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 993 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 994 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 995 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 996 /* 52 - 720x576@200Hz 4:3 */
a6b21831
TR		 997 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
998 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 999 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 1000 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1001 /* 53 - 720x576@200Hz 16:9 */
a6b21831
TR		 1002 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1003 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 1004 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 1005 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1006 /* 54 - 720(1440)x576i@200Hz 4:3 */
fb01d280
CT		 1007 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1008 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 1009 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1010 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1011 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1012 /* 55 - 720(1440)x576i@200Hz 16:9 */
fb01d280
CT		 1013 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1014 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 1015 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1016 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1017 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1018 /* 56 - 720x480@240Hz 4:3 */
a6b21831
TR		 1019 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1020 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 1021 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 1022 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1023 /* 57 - 720x480@240Hz 16:9 */
a6b21831
TR		 1024 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1025 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 1026 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 1027 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1028 /* 58 - 720(1440)x480i@240Hz 4:3 */
fb01d280
CT		 1029 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1030 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 1031 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1032 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1033 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1034 /* 59 - 720(1440)x480i@240Hz 16:9 */
fb01d280
CT		 1035 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1036 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 1037 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1038 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1039 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1040 /* 60 - 1280x720@24Hz 16:9 */
a6b21831
TR		 1041 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1042 3080, 3300, 0, 720, 725, 730, 750, 0,
ee7925bb 1043 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1044 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1045 /* 61 - 1280x720@25Hz 16:9 */
a6b21831
TR		 1046 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1047 3740, 3960, 0, 720, 725, 730, 750, 0,
ee7925bb 1048 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1049 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1050 /* 62 - 1280x720@30Hz 16:9 */
a6b21831
TR		 1051 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1052 3080, 3300, 0, 720, 725, 730, 750, 0,
ee7925bb 1053 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1054 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1055 /* 63 - 1920x1080@120Hz 16:9 */
a6b21831
TR		 1056 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1057 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 1058 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1059 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1060 /* 64 - 1920x1080@100Hz 16:9 */
a6b21831 1061 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
8f0e4907 1062 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 1063 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1064 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1065 /* 65 - 1280x720@24Hz 64:27 */
8ec6e075
SS		 1066 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1067 3080, 3300, 0, 720, 725, 730, 750, 0,
1068 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1069 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1070 /* 66 - 1280x720@25Hz 64:27 */
8ec6e075
SS		 1071 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1072 3740, 3960, 0, 720, 725, 730, 750, 0,
1073 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1074 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1075 /* 67 - 1280x720@30Hz 64:27 */
8ec6e075
SS		 1076 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1077 3080, 3300, 0, 720, 725, 730, 750, 0,
1078 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1079 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1080 /* 68 - 1280x720@50Hz 64:27 */
8ec6e075
SS		 1081 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1082 1760, 1980, 0, 720, 725, 730, 750, 0,
1083 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1084 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1085 /* 69 - 1280x720@60Hz 64:27 */
8ec6e075
SS		 1086 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1087 1430, 1650, 0, 720, 725, 730, 750, 0,
1088 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1089 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1090 /* 70 - 1280x720@100Hz 64:27 */
8ec6e075
SS		 1091 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1092 1760, 1980, 0, 720, 725, 730, 750, 0,
1093 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1094 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1095 /* 71 - 1280x720@120Hz 64:27 */
8ec6e075
SS		 1096 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1097 1430, 1650, 0, 720, 725, 730, 750, 0,
1098 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1099 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1100 /* 72 - 1920x1080@24Hz 64:27 */
8ec6e075
SS		 1101 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1102 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1103 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1104 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1105 /* 73 - 1920x1080@25Hz 64:27 */
8ec6e075
SS		 1106 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1107 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1108 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1109 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1110 /* 74 - 1920x1080@30Hz 64:27 */
8ec6e075
SS		 1111 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1112 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1113 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1114 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1115 /* 75 - 1920x1080@50Hz 64:27 */
8ec6e075
SS		 1116 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1117 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1118 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1119 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1120 /* 76 - 1920x1080@60Hz 64:27 */
8ec6e075
SS		 1121 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1122 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1123 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1124 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1125 /* 77 - 1920x1080@100Hz 64:27 */
8ec6e075
SS		 1126 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1127 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1128 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1129 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1130 /* 78 - 1920x1080@120Hz 64:27 */
8ec6e075
SS		 1131 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1132 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1133 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1134 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1135 /* 79 - 1680x720@24Hz 64:27 */
8ec6e075
SS		 1136 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1137 3080, 3300, 0, 720, 725, 730, 750, 0,
1138 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1139 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1140 /* 80 - 1680x720@25Hz 64:27 */
8ec6e075
SS		 1141 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1142 2948, 3168, 0, 720, 725, 730, 750, 0,
1143 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1144 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1145 /* 81 - 1680x720@30Hz 64:27 */
8ec6e075
SS		 1146 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1147 2420, 2640, 0, 720, 725, 730, 750, 0,
1148 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1149 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1150 /* 82 - 1680x720@50Hz 64:27 */
8ec6e075
SS		 1151 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1152 1980, 2200, 0, 720, 725, 730, 750, 0,
1153 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1154 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1155 /* 83 - 1680x720@60Hz 64:27 */
8ec6e075
SS		 1156 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1157 1980, 2200, 0, 720, 725, 730, 750, 0,
1158 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1159 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1160 /* 84 - 1680x720@100Hz 64:27 */
8ec6e075
SS		 1161 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1162 1780, 2000, 0, 720, 725, 730, 825, 0,
1163 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1164 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1165 /* 85 - 1680x720@120Hz 64:27 */
8ec6e075
SS		 1166 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1167 1780, 2000, 0, 720, 725, 730, 825, 0,
1168 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1169 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1170 /* 86 - 2560x1080@24Hz 64:27 */
8ec6e075
SS		 1171 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1172 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1173 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1174 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1175 /* 87 - 2560x1080@25Hz 64:27 */
8ec6e075
SS		 1176 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1177 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1178 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1179 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1180 /* 88 - 2560x1080@30Hz 64:27 */
8ec6e075
SS		 1181 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1182 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1183 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1184 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1185 /* 89 - 2560x1080@50Hz 64:27 */
8ec6e075
SS		 1186 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1187 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1188 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1189 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1190 /* 90 - 2560x1080@60Hz 64:27 */
8ec6e075
SS		 1191 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1192 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1193 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1194 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1195 /* 91 - 2560x1080@100Hz 64:27 */
8ec6e075
SS		 1196 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1197 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1198 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1199 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1200 /* 92 - 2560x1080@120Hz 64:27 */
8ec6e075
SS		 1201 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1202 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1203 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1204 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1205 /* 93 - 3840x2160@24Hz 16:9 */
8ec6e075
SS		 1206 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1207 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1208 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1209 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1210 /* 94 - 3840x2160@25Hz 16:9 */
8ec6e075
SS		 1211 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1212 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1213 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1214 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1215 /* 95 - 3840x2160@30Hz 16:9 */
8ec6e075
SS		 1216 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1217 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1218 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1219 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1220 /* 96 - 3840x2160@50Hz 16:9 */
8ec6e075
SS		 1221 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1222 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1223 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1224 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1225 /* 97 - 3840x2160@60Hz 16:9 */
8ec6e075
SS		 1226 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1227 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1228 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1229 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1230 /* 98 - 4096x2160@24Hz 256:135 */
8ec6e075
SS		 1231 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1232 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1233 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1234 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1235 /* 99 - 4096x2160@25Hz 256:135 */
8ec6e075
SS		 1236 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1237 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1238 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1239 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1240 /* 100 - 4096x2160@30Hz 256:135 */
8ec6e075
SS		 1241 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1242 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1243 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1244 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1245 /* 101 - 4096x2160@50Hz 256:135 */
8ec6e075
SS		 1246 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1247 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1248 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1249 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1250 /* 102 - 4096x2160@60Hz 256:135 */
8ec6e075
SS		 1251 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1252 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1253 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1254 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1255 /* 103 - 3840x2160@24Hz 64:27 */
8ec6e075
SS		 1256 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1257 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1258 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1259 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1260 /* 104 - 3840x2160@25Hz 64:27 */
8ec6e075
SS		 1261 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1262 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1263 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1264 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1265 /* 105 - 3840x2160@30Hz 64:27 */
8ec6e075
SS		 1266 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1267 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1269 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1270 /* 106 - 3840x2160@50Hz 64:27 */
8ec6e075
SS		 1271 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1272 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1273 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1274 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1275 /* 107 - 3840x2160@60Hz 64:27 */
8ec6e075
SS		 1276 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1277 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1278 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1279 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1280 /* 108 - 1280x720@48Hz 16:9 */
1281 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1282 2280, 2500, 0, 720, 725, 730, 750, 0,
1283 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1284 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1285 /* 109 - 1280x720@48Hz 64:27 */
1286 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1287 2280, 2500, 0, 720, 725, 730, 750, 0,
1288 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1289 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1290 /* 110 - 1680x720@48Hz 64:27 */
1291 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490,
1292 2530, 2750, 0, 720, 725, 730, 750, 0,
1293 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1294 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1295 /* 111 - 1920x1080@48Hz 16:9 */
1296 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1297 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1298 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1299 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1300 /* 112 - 1920x1080@48Hz 64:27 */
1301 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1302 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1303 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1304 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1305 /* 113 - 2560x1080@48Hz 64:27 */
1306 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558,
1307 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1308 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1309 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1310 /* 114 - 3840x2160@48Hz 16:9 */
1311 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1312 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1314 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1315 /* 115 - 4096x2160@48Hz 256:135 */
1316 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116,
1317 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1318 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1319 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
978f6b06
VS		 1320 /* 116 - 3840x2160@48Hz 64:27 */
1321 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1322 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1323 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1324 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1325 /* 117 - 3840x2160@100Hz 16:9 */
1326 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1327 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1328 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1329 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1330 /* 118 - 3840x2160@120Hz 16:9 */
1331 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1332 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1334 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1335 /* 119 - 3840x2160@100Hz 64:27 */
1336 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1337 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1338 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1339 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1340 /* 120 - 3840x2160@120Hz 64:27 */
1341 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1342 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1343 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1344 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1345 /* 121 - 5120x2160@24Hz 64:27 */
1346 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116,
1347 7204, 7500, 0, 2160, 2168, 2178, 2200, 0,
1348 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1349 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1350 /* 122 - 5120x2160@25Hz 64:27 */
1351 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816,
1352 6904, 7200, 0, 2160, 2168, 2178, 2200, 0,
1353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1354 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1355 /* 123 - 5120x2160@30Hz 64:27 */
1356 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784,
1357 5872, 6000, 0, 2160, 2168, 2178, 2200, 0,
1358 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1359 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1360 /* 124 - 5120x2160@48Hz 64:27 */
1361 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866,
1362 5954, 6250, 0, 2160, 2168, 2178, 2475, 0,
1363 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1364 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1365 /* 125 - 5120x2160@50Hz 64:27 */
1366 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216,
1367 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1369 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1370 /* 126 - 5120x2160@60Hz 64:27 */
1371 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284,
1372 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1374 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1375 /* 127 - 5120x2160@100Hz 64:27 */
1376 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216,
1377 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1378 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1379 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
a6b21831
TR		 1380};
1381
f7655d42
VS		 1382/*
1383 * From CEA/CTA-861 spec.
1384 *
1385 * Do not access directly, instead always use cea_mode_for_vic().
1386 */
1387static const struct drm_display_mode edid_cea_modes_193[] = {
1388 /* 193 - 5120x2160@120Hz 64:27 */
1389 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284,
1390 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1391 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1392 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1393 /* 194 - 7680x4320@24Hz 16:9 */
1394 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1395 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1396 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1397 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1398 /* 195 - 7680x4320@25Hz 16:9 */
1399 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1400 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1401 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1402 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1403 /* 196 - 7680x4320@30Hz 16:9 */
1404 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1405 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1406 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1407 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1408 /* 197 - 7680x4320@48Hz 16:9 */
1409 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1410 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1411 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1412 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1413 /* 198 - 7680x4320@50Hz 16:9 */
1414 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1415 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1416 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1417 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1418 /* 199 - 7680x4320@60Hz 16:9 */
1419 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1420 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1421 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1422 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1423 /* 200 - 7680x4320@100Hz 16:9 */
1424 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1425 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1426 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1427 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1428 /* 201 - 7680x4320@120Hz 16:9 */
1429 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1430 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1431 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1432 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1433 /* 202 - 7680x4320@24Hz 64:27 */
1434 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1435 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1436 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1437 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1438 /* 203 - 7680x4320@25Hz 64:27 */
1439 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1440 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1441 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1442 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1443 /* 204 - 7680x4320@30Hz 64:27 */
1444 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1445 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1446 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1447 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1448 /* 205 - 7680x4320@48Hz 64:27 */
1449 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1450 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1451 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1452 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1453 /* 206 - 7680x4320@50Hz 64:27 */
1454 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1455 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1456 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1457 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1458 /* 207 - 7680x4320@60Hz 64:27 */
1459 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1460 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1462 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1463 /* 208 - 7680x4320@100Hz 64:27 */
1464 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1465 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1466 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1467 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1468 /* 209 - 7680x4320@120Hz 64:27 */
1469 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1470 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1471 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1472 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1473 /* 210 - 10240x4320@24Hz 64:27 */
1474 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732,
1475 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1476 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1477 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1478 /* 211 - 10240x4320@25Hz 64:27 */
1479 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732,
1480 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1482 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1483 /* 212 - 10240x4320@30Hz 64:27 */
1484 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528,
1485 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1486 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1487 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1488 /* 213 - 10240x4320@48Hz 64:27 */
1489 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732,
1490 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1491 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1492 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1493 /* 214 - 10240x4320@50Hz 64:27 */
1494 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732,
1495 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1496 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1497 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1498 /* 215 - 10240x4320@60Hz 64:27 */
1499 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528,
1500 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1501 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1502 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1503 /* 216 - 10240x4320@100Hz 64:27 */
1504 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432,
1505 12608, 13200, 0, 4320, 4336, 4356, 4500, 0,
1506 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1507 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1508 /* 217 - 10240x4320@120Hz 64:27 */
1509 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528,
1510 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1511 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1512 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1513 /* 218 - 4096x2160@100Hz 256:135 */
1514 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896,
1515 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1516 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1517 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
f7655d42
VS		 1518 /* 219 - 4096x2160@120Hz 256:135 */
1519 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184,
1520 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1521 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1522 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
f7655d42
VS		 1523};
1524
7ebe1963 1525/*
d9278b4c 1526 * HDMI 1.4 4k modes. Index using the VIC.
7ebe1963
LD		 1527 */
1528static const struct drm_display_mode edid_4k_modes[] = {
d9278b4c
JN		 1529 /* 0 - dummy, VICs start at 1 */
1530 { },
7ebe1963
LD		 1531 /* 1 - 3840x2160@30Hz */
1532 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1533 3840, 4016, 4104, 4400, 0,
1534 2160, 2168, 2178, 2250, 0,
1535 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1536 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
7ebe1963
LD		 1537 /* 2 - 3840x2160@25Hz */
1538 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1539 3840, 4896, 4984, 5280, 0,
1540 2160, 2168, 2178, 2250, 0,
1541 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1542 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
7ebe1963
LD		 1543 /* 3 - 3840x2160@24Hz */
1544 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1545 3840, 5116, 5204, 5500, 0,
1546 2160, 2168, 2178, 2250, 0,
1547 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1548 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
7ebe1963
LD		 1549 /* 4 - 4096x2160@24Hz (SMPTE) */
1550 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1551 4096, 5116, 5204, 5500, 0,
1552 2160, 2168, 2178, 2250, 0,
1553 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1554 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
7ebe1963
LD		 1555};
1556
61e57a8d 1557/*** DDC fetch and block validation ***/
f453ba04 1558
083ae056
AJ		 1559static const u8 edid_header[] = {
1560 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1561};
f453ba04 1562
db6cf833
TR		 1563/**
1564 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1565 * @raw_edid: pointer to raw base EDID block
1566 *
1567 * Sanity check the header of the base EDID block.
1568 *
1569 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
051963d4
TR		 1570 */
1571int drm_edid_header_is_valid(const u8 *raw_edid)
1572{
1573 int i, score = 0;
1574
1575 for (i = 0; i < sizeof(edid_header); i++)
1576 if (raw_edid[i] == edid_header[i])
1577 score++;
1578
1579 return score;
1580}
1581EXPORT_SYMBOL(drm_edid_header_is_valid);
1582
47819ba2
AJ		 1583static int edid_fixup __read_mostly = 6;
1584module_param_named(edid_fixup, edid_fixup, int, 0400);
1585MODULE_PARM_DESC(edid_fixup,
1586 "Minimum number of valid EDID header bytes (0-8, default 6)");
051963d4 1587
c465bbc8
SB		 1588static int drm_edid_block_checksum(const u8 *raw_edid)
1589{
1590 int i;
e11f5bd8
JFZ		 1591 u8 csum = 0, crc = 0;
1592
1593 for (i = 0; i < EDID_LENGTH - 1; i++)
c465bbc8
SB		 1594 csum += raw_edid[i];
1595
e11f5bd8
JFZ		 1596 crc = 0x100 - csum;
1597
1598 return crc;
1599}
1600
1601static bool drm_edid_block_checksum_diff(const u8 *raw_edid, u8 real_checksum)
1602{
1603 if (raw_edid[EDID_LENGTH - 1] != real_checksum)
1604 return true;
1605 else
1606 return false;
c465bbc8
SB		 1607}
1608
d6885d65
SB		 1609static bool drm_edid_is_zero(const u8 *in_edid, int length)
1610{
1611 if (memchr_inv(in_edid, 0, length))
1612 return false;
1613
1614 return true;
1615}
1616
536faa45
SL		 1617/**
1618 * drm_edid_are_equal - compare two edid blobs.
1619 * @edid1: pointer to first blob
1620 * @edid2: pointer to second blob
1621 * This helper can be used during probing to determine if
1622 * edid had changed.
1623 */
1624bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2)
1625{
1626 int edid1_len, edid2_len;
1627 bool edid1_present = edid1 != NULL;
1628 bool edid2_present = edid2 != NULL;
1629
1630 if (edid1_present != edid2_present)
1631 return false;
1632
1633 if (edid1) {
536faa45
SL		 1634 edid1_len = EDID_LENGTH * (1 + edid1->extensions);
1635 edid2_len = EDID_LENGTH * (1 + edid2->extensions);
1636
1637 if (edid1_len != edid2_len)
1638 return false;
1639
1640 if (memcmp(edid1, edid2, edid1_len))
1641 return false;
1642 }
1643
1644 return true;
1645}
1646EXPORT_SYMBOL(drm_edid_are_equal);
1647
db6cf833
TR		 1648/**
1649 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1650 * @raw_edid: pointer to raw EDID block
1651 * @block: type of block to validate (0 for base, extension otherwise)
1652 * @print_bad_edid: if true, dump bad EDID blocks to the console
6ba2bd3d 1653 * @edid_corrupt: if true, the header or checksum is invalid
db6cf833
TR		 1654 *
1655 * Validate a base or extension EDID block and optionally dump bad blocks to
1656 * the console.
1657 *
1658 * Return: True if the block is valid, false otherwise.
f453ba04 1659 */
6ba2bd3d
TP		 1660bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
1661 bool *edid_corrupt)
f453ba04 1662{
c465bbc8 1663 u8 csum;
61e57a8d 1664 struct edid *edid = (struct edid *)raw_edid;
f453ba04 1665
fe2ef780
SWK		 1666 if (WARN_ON(!raw_edid))
1667 return false;
1668
47819ba2
AJ		 1669 if (edid_fixup > 8 || edid_fixup < 0)
1670 edid_fixup = 6;
1671
f89ec8a4 1672 if (block == 0) {
051963d4 1673 int score = drm_edid_header_is_valid(raw_edid);
948de842 1674
6ba2bd3d
TP		 1675 if (score == 8) {
1676 if (edid_corrupt)
ac6f2e29 1677 *edid_corrupt = false;
6ba2bd3d
TP		 1678 } else if (score >= edid_fixup) {
1679 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
1680 * The corrupt flag needs to be set here otherwise, the
1681 * fix-up code here will correct the problem, the
1682 * checksum is correct and the test fails
1683 */
1684 if (edid_corrupt)
ac6f2e29 1685 *edid_corrupt = true;
61e57a8d
AJ		 1686 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1687 memcpy(raw_edid, edid_header, sizeof(edid_header));
1688 } else {
6ba2bd3d 1689 if (edid_corrupt)
ac6f2e29 1690 *edid_corrupt = true;
61e57a8d
AJ		 1691 goto bad;
1692 }
1693 }
f453ba04 1694
c465bbc8 1695 csum = drm_edid_block_checksum(raw_edid);
e11f5bd8 1696 if (drm_edid_block_checksum_diff(raw_edid, csum)) {
6ba2bd3d 1697 if (edid_corrupt)
ac6f2e29 1698 *edid_corrupt = true;
6ba2bd3d 1699
4a638b4e 1700 /* allow CEA to slide through, switches mangle this */
82d75356
TV		 1701 if (raw_edid[0] == CEA_EXT) {
1702 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum);
1703 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n");
1704 } else {
1705 if (print_bad_edid)
813a7878 1706 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum);
82d75356 1707
4a638b4e 1708 goto bad;
82d75356 1709 }
f453ba04
DA		 1710 }
1711
61e57a8d
AJ		 1712 /* per-block-type checks */
1713 switch (raw_edid[0]) {
1714 case 0: /* base */
1715 if (edid->version != 1) {
813a7878 1716 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version);
61e57a8d
AJ		 1717 goto bad;
1718 }
862b89c0 1719
61e57a8d
AJ		 1720 if (edid->revision > 4)
1721 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1722 break;
862b89c0 1723
61e57a8d
AJ		 1724 default:
1725 break;
1726 }
47ee4ccf 1727
fe2ef780 1728 return true;
f453ba04
DA		 1729
1730bad:
fe2ef780 1731 if (print_bad_edid) {
da4c07b7 1732 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
499447db 1733 pr_notice("EDID block is all zeroes\n");
da4c07b7 1734 } else {
499447db 1735 pr_notice("Raw EDID:\n");
813a7878
CW		 1736 print_hex_dump(KERN_NOTICE,
1737 " \t", DUMP_PREFIX_NONE, 16, 1,
1738 raw_edid, EDID_LENGTH, false);
da4c07b7 1739 }
f453ba04 1740 }
fe2ef780 1741 return false;
f453ba04 1742}
da0df92b 1743EXPORT_SYMBOL(drm_edid_block_valid);
61e57a8d
AJ		 1744
1745/**
1746 * drm_edid_is_valid - sanity check EDID data
1747 * @edid: EDID data
1748 *
1749 * Sanity-check an entire EDID record (including extensions)
db6cf833
TR		 1750 *
1751 * Return: True if the EDID data is valid, false otherwise.
61e57a8d
AJ		 1752 */
1753bool drm_edid_is_valid(struct edid *edid)
1754{
1755 int i;
1756 u8 *raw = (u8 *)edid;
1757
1758 if (!edid)
1759 return false;
1760
1761 for (i = 0; i <= edid->extensions; i++)
6ba2bd3d 1762 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
61e57a8d
AJ		 1763 return false;
1764
1765 return true;
1766}
3c537889 1767EXPORT_SYMBOL(drm_edid_is_valid);
f453ba04 1768
61e57a8d
AJ		 1769#define DDC_SEGMENT_ADDR 0x30
1770/**
db6cf833 1771 * drm_do_probe_ddc_edid() - get EDID information via I2C
7c58e87e 1772 * @data: I2C device adapter
fc66811c
DV		 1773 * @buf: EDID data buffer to be filled
1774 * @block: 128 byte EDID block to start fetching from
1775 * @len: EDID data buffer length to fetch
1776 *
db6cf833 1777 * Try to fetch EDID information by calling I2C driver functions.
61e57a8d 1778 *
db6cf833 1779 * Return: 0 on success or -1 on failure.
61e57a8d
AJ		 1780 */
1781static int
18df89fe 1782drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
61e57a8d 1783{
18df89fe 1784 struct i2c_adapter *adapter = data;
61e57a8d 1785 unsigned char start = block * EDID_LENGTH;
cd004b3f
S		 1786 unsigned char segment = block >> 1;
1787 unsigned char xfers = segment ? 3 : 2;
4819d2e4
CW		 1788 int ret, retries = 5;
1789
db6cf833
TR		 1790 /*
1791 * The core I2C driver will automatically retry the transfer if the
4819d2e4
CW		 1792 * adapter reports EAGAIN. However, we find that bit-banging transfers
1793 * are susceptible to errors under a heavily loaded machine and
1794 * generate spurious NAKs and timeouts. Retrying the transfer
1795 * of the individual block a few times seems to overcome this.
1796 */
1797 do {
1798 struct i2c_msg msgs[] = {
1799 {
cd004b3f
S		 1800 .addr = DDC_SEGMENT_ADDR,
1801 .flags = 0,
1802 .len = 1,
1803 .buf = &segment,
1804 }, {
4819d2e4
CW		 1805 .addr = DDC_ADDR,
1806 .flags = 0,
1807 .len = 1,
1808 .buf = &start,
1809 }, {
1810 .addr = DDC_ADDR,
1811 .flags = I2C_M_RD,
1812 .len = len,
1813 .buf = buf,
1814 }
1815 };
cd004b3f 1816
db6cf833
TR		 1817 /*
1818 * Avoid sending the segment addr to not upset non-compliant
1819 * DDC monitors.
1820 */
cd004b3f
S		 1821 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1822
9292f37e
ED		 1823 if (ret == -ENXIO) {
1824 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1825 adapter->name);
1826 break;
1827 }
cd004b3f 1828 } while (ret != xfers && --retries);
4819d2e4 1829
cd004b3f 1830 return ret == xfers ? 0 : -1;
61e57a8d
AJ		 1831}
1832
14544d09
CW		 1833static void connector_bad_edid(struct drm_connector *connector,
1834 u8 *edid, int num_blocks)
1835{
1836 int i;
e11f5bd8
JFZ		 1837 u8 num_of_ext = edid[0x7e];
1838
1839 /* Calculate real checksum for the last edid extension block data */
1840 connector->real_edid_checksum =
1841 drm_edid_block_checksum(edid + num_of_ext * EDID_LENGTH);
14544d09 1842
f0a8f533 1843 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
14544d09
CW		 1844 return;
1845
fa3bfa35 1846 drm_dbg_kms(connector->dev, "%s: EDID is invalid:\n", connector->name);
14544d09
CW		 1847 for (i = 0; i < num_blocks; i++) {
1848 u8 *block = edid + i * EDID_LENGTH;
1849 char prefix[20];
1850
1851 if (drm_edid_is_zero(block, EDID_LENGTH))
1852 sprintf(prefix, "\t[%02x] ZERO ", i);
1853 else if (!drm_edid_block_valid(block, i, false, NULL))
1854 sprintf(prefix, "\t[%02x] BAD ", i);
1855 else
1856 sprintf(prefix, "\t[%02x] GOOD ", i);
1857
fa3bfa35 1858 print_hex_dump(KERN_DEBUG,
14544d09
CW		 1859 prefix, DUMP_PREFIX_NONE, 16, 1,
1860 block, EDID_LENGTH, false);
1861 }
1862}
1863
56a2b7f2
JN		 1864/* Get override or firmware EDID */
1865static struct edid *drm_get_override_edid(struct drm_connector *connector)
1866{
1867 struct edid *override = NULL;
1868
1869 if (connector->override_edid)
1870 override = drm_edid_duplicate(connector->edid_blob_ptr->data);
1871
1872 if (!override)
1873 override = drm_load_edid_firmware(connector);
1874
1875 return IS_ERR(override) ? NULL : override;
1876}
1877
48eaeb76
JN		 1878/**
1879 * drm_add_override_edid_modes - add modes from override/firmware EDID
1880 * @connector: connector we're probing
1881 *
1882 * Add modes from the override/firmware EDID, if available. Only to be used from
1883 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
1884 * failed during drm_get_edid() and caused the override/firmware EDID to be
1885 * skipped.
1886 *
1887 * Return: The number of modes added or 0 if we couldn't find any.
1888 */
1889int drm_add_override_edid_modes(struct drm_connector *connector)
1890{
1891 struct edid *override;
1892 int num_modes = 0;
1893
1894 override = drm_get_override_edid(connector);
1895 if (override) {
1896 drm_connector_update_edid_property(connector, override);
1897 num_modes = drm_add_edid_modes(connector, override);
1898 kfree(override);
1899
1900 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
1901 connector->base.id, connector->name, num_modes);
1902 }
1903
1904 return num_modes;
1905}
1906EXPORT_SYMBOL(drm_add_override_edid_modes);
1907
18df89fe
LPC		 1908/**
1909 * drm_do_get_edid - get EDID data using a custom EDID block read function
1910 * @connector: connector we're probing
1911 * @get_edid_block: EDID block read function
1912 * @data: private data passed to the block read function
1913 *
1914 * When the I2C adapter connected to the DDC bus is hidden behind a device that
1915 * exposes a different interface to read EDID blocks this function can be used
1916 * to get EDID data using a custom block read function.
1917 *
1918 * As in the general case the DDC bus is accessible by the kernel at the I2C
1919 * level, drivers must make all reasonable efforts to expose it as an I2C
1920 * adapter and use drm_get_edid() instead of abusing this function.
1921 *
0ae865ef 1922 * The EDID may be overridden using debugfs override_edid or firmware EDID
53fd40a9
JN		 1923 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
1924 * order. Having either of them bypasses actual EDID reads.
1925 *
18df89fe
LPC		 1926 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1927 */
1928struct edid *drm_do_get_edid(struct drm_connector *connector,
1929 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
1930 size_t len),
1931 void *data)
61e57a8d 1932{
0ea75e23 1933 int i, j = 0, valid_extensions = 0;
f14f3686 1934 u8 *edid, *new;
56a2b7f2 1935 struct edid *override;
53fd40a9 1936
56a2b7f2
JN		 1937 override = drm_get_override_edid(connector);
1938 if (override)
53fd40a9 1939 return override;
61e57a8d 1940
f14f3686 1941 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
61e57a8d
AJ		 1942 return NULL;
1943
1944 /* base block fetch */
1945 for (i = 0; i < 4; i++) {
f14f3686 1946 if (get_edid_block(data, edid, 0, EDID_LENGTH))
61e57a8d 1947 goto out;
14544d09 1948 if (drm_edid_block_valid(edid, 0, false,
6ba2bd3d 1949 &connector->edid_corrupt))
61e57a8d 1950 break;
f14f3686 1951 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) {
4a9a8b71
DA		 1952 connector->null_edid_counter++;
1953 goto carp;
1954 }
61e57a8d
AJ		 1955 }
1956 if (i == 4)
1957 goto carp;
1958
1959 /* if there's no extensions, we're done */
14544d09
CW		 1960 valid_extensions = edid[0x7e];
1961 if (valid_extensions == 0)
f14f3686 1962 return (struct edid *)edid;
61e57a8d 1963
14544d09 1964 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
61e57a8d
AJ		 1965 if (!new)
1966 goto out;
f14f3686 1967 edid = new;
61e57a8d 1968
f14f3686 1969 for (j = 1; j <= edid[0x7e]; j++) {
14544d09 1970 u8 *block = edid + j * EDID_LENGTH;
a28187cc 1971
61e57a8d 1972 for (i = 0; i < 4; i++) {
a28187cc 1973 if (get_edid_block(data, block, j, EDID_LENGTH))
61e57a8d 1974 goto out;
14544d09 1975 if (drm_edid_block_valid(block, j, false, NULL))
61e57a8d
AJ		 1976 break;
1977 }
f934ec8c 1978
14544d09
CW		 1979 if (i == 4)
1980 valid_extensions--;
0ea75e23
ST		 1981 }
1982
f14f3686 1983 if (valid_extensions != edid[0x7e]) {
14544d09
CW		 1984 u8 *base;
1985
1986 connector_bad_edid(connector, edid, edid[0x7e] + 1);
1987
f14f3686
CW		 1988 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions;
1989 edid[0x7e] = valid_extensions;
14544d09 1990
6da2ec56
KC		 1991 new = kmalloc_array(valid_extensions + 1, EDID_LENGTH,
1992 GFP_KERNEL);
0ea75e23
ST		 1993 if (!new)
1994 goto out;
14544d09
CW		 1995
1996 base = new;
1997 for (i = 0; i <= edid[0x7e]; i++) {
1998 u8 *block = edid + i * EDID_LENGTH;
1999
2000 if (!drm_edid_block_valid(block, i, false, NULL))
2001 continue;
2002
2003 memcpy(base, block, EDID_LENGTH);
2004 base += EDID_LENGTH;
2005 }
2006
2007 kfree(edid);
f14f3686 2008 edid = new;
61e57a8d
AJ		 2009 }
2010
f14f3686 2011 return (struct edid *)edid;
61e57a8d
AJ		 2012
2013carp:
14544d09 2014 connector_bad_edid(connector, edid, 1);
61e57a8d 2015out:
f14f3686 2016 kfree(edid);
61e57a8d
AJ		 2017 return NULL;
2018}
18df89fe 2019EXPORT_SYMBOL_GPL(drm_do_get_edid);
61e57a8d
AJ		 2020
2021/**
db6cf833
TR		 2022 * drm_probe_ddc() - probe DDC presence
2023 * @adapter: I2C adapter to probe
fc66811c 2024 *
db6cf833 2025 * Return: True on success, false on failure.
61e57a8d 2026 */
fbff4690 2027bool
61e57a8d
AJ		 2028drm_probe_ddc(struct i2c_adapter *adapter)
2029{
2030 unsigned char out;
2031
2032 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
2033}
fbff4690 2034EXPORT_SYMBOL(drm_probe_ddc);
61e57a8d
AJ		 2035
2036/**
2037 * drm_get_edid - get EDID data, if available
2038 * @connector: connector we're probing
db6cf833 2039 * @adapter: I2C adapter to use for DDC
61e57a8d 2040 *
db6cf833 2041 * Poke the given I2C channel to grab EDID data if possible. If found,
61e57a8d
AJ		 2042 * attach it to the connector.
2043 *
db6cf833 2044 * Return: Pointer to valid EDID or NULL if we couldn't find any.
61e57a8d
AJ		 2045 */
2046struct edid *drm_get_edid(struct drm_connector *connector,
2047 struct i2c_adapter *adapter)
2048{
5186421c
SL		 2049 struct edid *edid;
2050
15f080f0
JN		 2051 if (connector->force == DRM_FORCE_OFF)
2052 return NULL;
2053
2054 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
18df89fe 2055 return NULL;
61e57a8d 2056
5186421c
SL		 2057 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
2058 drm_connector_update_edid_property(connector, edid);
2059 return edid;
61e57a8d
AJ		 2060}
2061EXPORT_SYMBOL(drm_get_edid);
2062
5cb8eaa2
LW		 2063/**
2064 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
2065 * @connector: connector we're probing
2066 * @adapter: I2C adapter to use for DDC
2067 *
2068 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
2069 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
2070 * switch DDC to the GPU which is retrieving EDID.
2071 *
2072 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2073 */
2074struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
2075 struct i2c_adapter *adapter)
2076{
36b73b05
TZ		 2077 struct drm_device *dev = connector->dev;
2078 struct pci_dev *pdev = to_pci_dev(dev->dev);
5cb8eaa2
LW		 2079 struct edid *edid;
2080
36b73b05
TZ		 2081 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev)))
2082 return NULL;
2083
5cb8eaa2
LW		 2084 vga_switcheroo_lock_ddc(pdev);
2085 edid = drm_get_edid(connector, adapter);
2086 vga_switcheroo_unlock_ddc(pdev);
2087
2088 return edid;
2089}
2090EXPORT_SYMBOL(drm_get_edid_switcheroo);
2091
51f8da59
JN		 2092/**
2093 * drm_edid_duplicate - duplicate an EDID and the extensions
2094 * @edid: EDID to duplicate
2095 *
db6cf833 2096 * Return: Pointer to duplicated EDID or NULL on allocation failure.
51f8da59
JN		 2097 */
2098struct edid *drm_edid_duplicate(const struct edid *edid)
2099{
2100 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
2101}
2102EXPORT_SYMBOL(drm_edid_duplicate);
2103
61e57a8d
AJ		 2104/*** EDID parsing ***/
2105
f453ba04
DA		 2106/**
2107 * edid_vendor - match a string against EDID's obfuscated vendor field
2108 * @edid: EDID to match
2109 * @vendor: vendor string
2110 *
2111 * Returns true if @vendor is in @edid, false otherwise
2112 */
170178fe 2113static bool edid_vendor(const struct edid *edid, const char *vendor)
f453ba04
DA		 2114{
2115 char edid_vendor[3];
2116
2117 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
2118 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
2119 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
16456c87 2120 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
f453ba04
DA		 2121
2122 return !strncmp(edid_vendor, vendor, 3);
2123}
2124
2125/**
2126 * edid_get_quirks - return quirk flags for a given EDID
2127 * @edid: EDID to process
2128 *
2129 * This tells subsequent routines what fixes they need to apply.
2130 */
170178fe 2131static u32 edid_get_quirks(const struct edid *edid)
f453ba04 2132{
23c4cfbd 2133 const struct edid_quirk *quirk;
f453ba04
DA		 2134 int i;
2135
2136 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
2137 quirk = &edid_quirk_list[i];
2138
2139 if (edid_vendor(edid, quirk->vendor) &&
2140 (EDID_PRODUCT_ID(edid) == quirk->product_id))
2141 return quirk->quirks;
2142 }
2143
2144 return 0;
2145}
2146
2147#define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
339d202c 2148#define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
f453ba04 2149
f453ba04
DA		 2150/**
2151 * edid_fixup_preferred - set preferred modes based on quirk list
2152 * @connector: has mode list to fix up
2153 * @quirks: quirks list
2154 *
2155 * Walk the mode list for @connector, clearing the preferred status
2156 * on existing modes and setting it anew for the right mode ala @quirks.
2157 */
2158static void edid_fixup_preferred(struct drm_connector *connector,
2159 u32 quirks)
2160{
2161 struct drm_display_mode *t, *cur_mode, *preferred_mode;
f890607b 2162 int target_refresh = 0;
339d202c 2163 int cur_vrefresh, preferred_vrefresh;
f453ba04
DA		 2164
2165 if (list_empty(&connector->probed_modes))
2166 return;
2167
2168 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
2169 target_refresh = 60;
2170 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
2171 target_refresh = 75;
2172
2173 preferred_mode = list_first_entry(&connector->probed_modes,
2174 struct drm_display_mode, head);
2175
2176 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
2177 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
2178
2179 if (cur_mode == preferred_mode)
2180 continue;
2181
2182 /* Largest mode is preferred */
2183 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
2184 preferred_mode = cur_mode;
2185
0425662f
VS		 2186 cur_vrefresh = drm_mode_vrefresh(cur_mode);
2187 preferred_vrefresh = drm_mode_vrefresh(preferred_mode);
f453ba04
DA		 2188 /* At a given size, try to get closest to target refresh */
2189 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
339d202c
AD		 2190 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
2191 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
f453ba04
DA		 2192 preferred_mode = cur_mode;
2193 }
2194 }
2195
2196 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
2197}
2198
f6e252ba
AJ		 2199static bool
2200mode_is_rb(const struct drm_display_mode *mode)
2201{
2202 return (mode->htotal - mode->hdisplay == 160) &&
2203 (mode->hsync_end - mode->hdisplay == 80) &&
2204 (mode->hsync_end - mode->hsync_start == 32) &&
2205 (mode->vsync_start - mode->vdisplay == 3);
2206}
2207
33c7531d
AJ		 2208/*
2209 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
2210 * @dev: Device to duplicate against
2211 * @hsize: Mode width
2212 * @vsize: Mode height
2213 * @fresh: Mode refresh rate
f6e252ba 2214 * @rb: Mode reduced-blanking-ness
33c7531d
AJ		 2215 *
2216 * Walk the DMT mode list looking for a match for the given parameters.
db6cf833
TR		 2217 *
2218 * Return: A newly allocated copy of the mode, or NULL if not found.
33c7531d 2219 */
1d42bbc8 2220struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
f6e252ba
AJ		 2221 int hsize, int vsize, int fresh,
2222 bool rb)
559ee21d 2223{
07a5e632 2224 int i;
559ee21d 2225
a6b21831 2226 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
b1f559ec 2227 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
948de842 2228
f8b46a05
AJ		 2229 if (hsize != ptr->hdisplay)
2230 continue;
2231 if (vsize != ptr->vdisplay)
2232 continue;
2233 if (fresh != drm_mode_vrefresh(ptr))
2234 continue;
f6e252ba
AJ		 2235 if (rb != mode_is_rb(ptr))
2236 continue;
f8b46a05
AJ		 2237
2238 return drm_mode_duplicate(dev, ptr);
559ee21d 2239 }
f8b46a05
AJ		 2240
2241 return NULL;
559ee21d 2242}
1d42bbc8 2243EXPORT_SYMBOL(drm_mode_find_dmt);
23425cae 2244
a7a131ac
VS		 2245static bool is_display_descriptor(const u8 d[18], u8 tag)
2246{
2247 return d[0] == 0x00 && d[1] == 0x00 &&
2248 d[2] == 0x00 && d[3] == tag;
2249}
2250
f447dd1f
VS		 2251static bool is_detailed_timing_descriptor(const u8 d[18])
2252{
2253 return d[0] != 0x00 || d[1] != 0x00;
2254}
2255
d1ff6409
AJ		 2256typedef void detailed_cb(struct detailed_timing *timing, void *closure);
2257
4d76a221
AJ		 2258static void
2259cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
2260{
7304b981 2261 int i, n;
4966b2a9 2262 u8 d = ext[0x02];
4d76a221
AJ		 2263 u8 *det_base = ext + d;
2264
7304b981
VS		 2265 if (d < 4 || d > 127)
2266 return;
2267
4966b2a9 2268 n = (127 - d) / 18;
4d76a221
AJ		 2269 for (i = 0; i < n; i++)
2270 cb((struct detailed_timing *)(det_base + 18 * i), closure);
2271}
2272
cbba98f8
AJ		 2273static void
2274vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
2275{
2276 unsigned int i, n = min((int)ext[0x02], 6);
2277 u8 *det_base = ext + 5;
2278
2279 if (ext[0x01] != 1)
2280 return; /* unknown version */
2281
2282 for (i = 0; i < n; i++)
2283 cb((struct detailed_timing *)(det_base + 18 * i), closure);
2284}
2285
d1ff6409
AJ		 2286static void
2287drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
2288{
2289 int i;
2290 struct edid *edid = (struct edid *)raw_edid;
2291
2292 if (edid == NULL)
2293 return;
2294
2295 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
2296 cb(&(edid->detailed_timings[i]), closure);
2297
4d76a221
AJ		 2298 for (i = 1; i <= raw_edid[0x7e]; i++) {
2299 u8 *ext = raw_edid + (i * EDID_LENGTH);
948de842 2300
4d76a221
AJ		 2301 switch (*ext) {
2302 case CEA_EXT:
2303 cea_for_each_detailed_block(ext, cb, closure);
2304 break;
cbba98f8
AJ		 2305 case VTB_EXT:
2306 vtb_for_each_detailed_block(ext, cb, closure);
2307 break;
4d76a221
AJ		 2308 default:
2309 break;
2310 }
2311 }
d1ff6409
AJ		 2312}
2313
2314static void
2315is_rb(struct detailed_timing *t, void *data)
2316{
2317 u8 *r = (u8 *)t;
a7a131ac
VS		 2318
2319 if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE))
2320 return;
2321
2322 if (r[15] & 0x10)
2323 *(bool *)data = true;
d1ff6409
AJ		 2324}
2325
2326/* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
2327static bool
2328drm_monitor_supports_rb(struct edid *edid)
2329{
2330 if (edid->revision >= 4) {
b196a498 2331 bool ret = false;
948de842 2332
d1ff6409
AJ		 2333 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
2334 return ret;
2335 }
2336
2337 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
2338}
2339
7a374350
AJ		 2340static void
2341find_gtf2(struct detailed_timing *t, void *data)
2342{
2343 u8 *r = (u8 *)t;
a7a131ac
VS		 2344
2345 if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE))
2346 return;
2347
2348 if (r[10] == 0x02)
7a374350
AJ		 2349 *(u8 **)data = r;
2350}
2351
2352/* Secondary GTF curve kicks in above some break frequency */
2353static int
2354drm_gtf2_hbreak(struct edid *edid)
2355{
2356 u8 *r = NULL;
948de842 2357
7a374350
AJ		 2358 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2359 return r ? (r[12] * 2) : 0;
2360}
2361
2362static int
2363drm_gtf2_2c(struct edid *edid)
2364{
2365 u8 *r = NULL;
948de842 2366
7a374350
AJ		 2367 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2368 return r ? r[13] : 0;
2369}
2370
2371static int
2372drm_gtf2_m(struct edid *edid)
2373{
2374 u8 *r = NULL;
948de842 2375
7a374350
AJ		 2376 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2377 return r ? (r[15] << 8) + r[14] : 0;
2378}
2379
2380static int
2381drm_gtf2_k(struct edid *edid)
2382{
2383 u8 *r = NULL;
948de842 2384
7a374350
AJ		 2385 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2386 return r ? r[16] : 0;
2387}
2388
2389static int
2390drm_gtf2_2j(struct edid *edid)
2391{
2392 u8 *r = NULL;
948de842 2393
7a374350
AJ		 2394 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2395 return r ? r[17] : 0;
2396}
2397
2398/**
2399 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
2400 * @edid: EDID block to scan
2401 */
2402static int standard_timing_level(struct edid *edid)
2403{
2404 if (edid->revision >= 2) {
2405 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
2406 return LEVEL_CVT;
2407 if (drm_gtf2_hbreak(edid))
2408 return LEVEL_GTF2;
bfef04ad
LS		 2409 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
2410 return LEVEL_GTF;
7a374350
AJ		 2411 }
2412 return LEVEL_DMT;
2413}
2414
23425cae
AJ		 2415/*
2416 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
2417 * monitors fill with ascii space (0x20) instead.
2418 */
2419static int
2420bad_std_timing(u8 a, u8 b)
2421{
2422 return (a == 0x00 && b == 0x00) ||
2423 (a == 0x01 && b == 0x01) ||
2424 (a == 0x20 && b == 0x20);
2425}
2426
58911c24
VS		 2427static int drm_mode_hsync(const struct drm_display_mode *mode)
2428{
2429 if (mode->htotal <= 0)
2430 return 0;
2431
2432 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal);
2433}
2434
f453ba04
DA		 2435/**
2436 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
fc66811c
DV		 2437 * @connector: connector of for the EDID block
2438 * @edid: EDID block to scan
f453ba04
DA		 2439 * @t: standard timing params
2440 *
2441 * Take the standard timing params (in this case width, aspect, and refresh)
5c61259e 2442 * and convert them into a real mode using CVT/GTF/DMT.
f453ba04 2443 */
7ca6adb3 2444static struct drm_display_mode *
7a374350 2445drm_mode_std(struct drm_connector *connector, struct edid *edid,
464fdeca 2446 struct std_timing *t)
f453ba04 2447{
7ca6adb3
AJ		 2448 struct drm_device *dev = connector->dev;
2449 struct drm_display_mode *m, *mode = NULL;
5c61259e
ZY		 2450 int hsize, vsize;
2451 int vrefresh_rate;
0454beab
MD		 2452 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
2453 >> EDID_TIMING_ASPECT_SHIFT;
5c61259e
ZY		 2454 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
2455 >> EDID_TIMING_VFREQ_SHIFT;
7a374350 2456 int timing_level = standard_timing_level(edid);
5c61259e 2457
23425cae
AJ		 2458 if (bad_std_timing(t->hsize, t->vfreq_aspect))
2459 return NULL;
2460
5c61259e
ZY		 2461 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
2462 hsize = t->hsize * 8 + 248;
2463 /* vrefresh_rate = vfreq + 60 */
2464 vrefresh_rate = vfreq + 60;
2465 /* the vdisplay is calculated based on the aspect ratio */
f066a17d 2466 if (aspect_ratio == 0) {
464fdeca 2467 if (edid->revision < 3)
f066a17d
AJ		 2468 vsize = hsize;
2469 else
2470 vsize = (hsize * 10) / 16;
2471 } else if (aspect_ratio == 1)
f453ba04 2472 vsize = (hsize * 3) / 4;
0454beab 2473 else if (aspect_ratio == 2)
f453ba04
DA		 2474 vsize = (hsize * 4) / 5;
2475 else
2476 vsize = (hsize * 9) / 16;
a0910c8e
AJ		 2477
2478 /* HDTV hack, part 1 */
2479 if (vrefresh_rate == 60 &&
2480 ((hsize == 1360 && vsize == 765) ||
2481 (hsize == 1368 && vsize == 769))) {
2482 hsize = 1366;
2483 vsize = 768;
2484 }
2485
7ca6adb3
AJ		 2486 /*
2487 * If this connector already has a mode for this size and refresh
2488 * rate (because it came from detailed or CVT info), use that
2489 * instead. This way we don't have to guess at interlace or
2490 * reduced blanking.
2491 */
522032da 2492 list_for_each_entry(m, &connector->probed_modes, head)
7ca6adb3
AJ		 2493 if (m->hdisplay == hsize && m->vdisplay == vsize &&
2494 drm_mode_vrefresh(m) == vrefresh_rate)
2495 return NULL;
2496
a0910c8e
AJ		 2497 /* HDTV hack, part 2 */
2498 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
2499 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
d50ba256 2500 false);
a5ef6567
JM		 2501 if (!mode)
2502 return NULL;
559ee21d 2503 mode->hdisplay = 1366;
a4967de6
AJ		 2504 mode->hsync_start = mode->hsync_start - 1;
2505 mode->hsync_end = mode->hsync_end - 1;
559ee21d
ZY		 2506 return mode;
2507 }
a0910c8e 2508
559ee21d 2509 /* check whether it can be found in default mode table */
f6e252ba
AJ		 2510 if (drm_monitor_supports_rb(edid)) {
2511 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
2512 true);
2513 if (mode)
2514 return mode;
2515 }
2516 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
559ee21d
ZY		 2517 if (mode)
2518 return mode;
2519
f6e252ba 2520 /* okay, generate it */
5c61259e
ZY		 2521 switch (timing_level) {
2522 case LEVEL_DMT:
5c61259e
ZY		 2523 break;
2524 case LEVEL_GTF:
2525 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2526 break;
7a374350
AJ		 2527 case LEVEL_GTF2:
2528 /*
2529 * This is potentially wrong if there's ever a monitor with
2530 * more than one ranges section, each claiming a different
2531 * secondary GTF curve. Please don't do that.
2532 */
2533 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
fc48f169
TI		 2534 if (!mode)
2535 return NULL;
7a374350 2536 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
aefd330e 2537 drm_mode_destroy(dev, mode);
7a374350
AJ		 2538 mode = drm_gtf_mode_complex(dev, hsize, vsize,
2539 vrefresh_rate, 0, 0,
2540 drm_gtf2_m(edid),
2541 drm_gtf2_2c(edid),
2542 drm_gtf2_k(edid),
2543 drm_gtf2_2j(edid));
2544 }
2545 break;
5c61259e 2546 case LEVEL_CVT:
d50ba256
DA		 2547 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
2548 false);
5c61259e
ZY		 2549 break;
2550 }
f453ba04
DA		 2551 return mode;
2552}
2553
b58db2c6
AJ		 2554/*
2555 * EDID is delightfully ambiguous about how interlaced modes are to be
2556 * encoded. Our internal representation is of frame height, but some
2557 * HDTV detailed timings are encoded as field height.
2558 *
2559 * The format list here is from CEA, in frame size. Technically we
2560 * should be checking refresh rate too. Whatever.
2561 */
2562static void
2563drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
2564 struct detailed_pixel_timing *pt)
2565{
2566 int i;
2567 static const struct {
2568 int w, h;
2569 } cea_interlaced[] = {
2570 { 1920, 1080 },
2571 { 720, 480 },
2572 { 1440, 480 },
2573 { 2880, 480 },
2574 { 720, 576 },
2575 { 1440, 576 },
2576 { 2880, 576 },
2577 };
b58db2c6
AJ		 2578
2579 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
2580 return;
2581
3c581411 2582 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
b58db2c6
AJ		 2583 if ((mode->hdisplay == cea_interlaced[i].w) &&
2584 (mode->vdisplay == cea_interlaced[i].h / 2)) {
2585 mode->vdisplay *= 2;
2586 mode->vsync_start *= 2;
2587 mode->vsync_end *= 2;
2588 mode->vtotal *= 2;
2589 mode->vtotal |= 1;
2590 }
2591 }
2592
2593 mode->flags |= DRM_MODE_FLAG_INTERLACE;
2594}
2595
f453ba04
DA		 2596/**
2597 * drm_mode_detailed - create a new mode from an EDID detailed timing section
2598 * @dev: DRM device (needed to create new mode)
2599 * @edid: EDID block
2600 * @timing: EDID detailed timing info
2601 * @quirks: quirks to apply
2602 *
2603 * An EDID detailed timing block contains enough info for us to create and
2604 * return a new struct drm_display_mode.
2605 */
2606static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
2607 struct edid *edid,
2608 struct detailed_timing *timing,
2609 u32 quirks)
2610{
2611 struct drm_display_mode *mode;
2612 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
0454beab
MD		 2613 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
2614 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
2615 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
2616 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
e14cbee4
MD		 2617 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
2618 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
16dad1d7 2619 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
e14cbee4 2620 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
f453ba04 2621
fc438966 2622 /* ignore tiny modes */
0454beab 2623 if (hactive < 64 || vactive < 64)
fc438966
AJ		 2624 return NULL;
2625
0454beab 2626 if (pt->misc & DRM_EDID_PT_STEREO) {
c7d015f3 2627 DRM_DEBUG_KMS("stereo mode not supported\n");
f453ba04
DA		 2628 return NULL;
2629 }
0454beab 2630 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
c7d015f3 2631 DRM_DEBUG_KMS("composite sync not supported\n");
f453ba04
DA		 2632 }
2633
fcb45611
ZY		 2634 /* it is incorrect if hsync/vsync width is zero */
2635 if (!hsync_pulse_width || !vsync_pulse_width) {
2636 DRM_DEBUG_KMS("Incorrect Detailed timing. "
2637 "Wrong Hsync/Vsync pulse width\n");
2638 return NULL;
2639 }
bc42aabc
AJ		 2640
2641 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
2642 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
2643 if (!mode)
2644 return NULL;
2645
2646 goto set_size;
2647 }
2648
f453ba04
DA		 2649 mode = drm_mode_create(dev);
2650 if (!mode)
2651 return NULL;
2652
f453ba04 2653 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
0454beab
MD		 2654 timing->pixel_clock = cpu_to_le16(1088);
2655
2656 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
2657
2658 mode->hdisplay = hactive;
2659 mode->hsync_start = mode->hdisplay + hsync_offset;
2660 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
2661 mode->htotal = mode->hdisplay + hblank;
2662
2663 mode->vdisplay = vactive;
2664 mode->vsync_start = mode->vdisplay + vsync_offset;
2665 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
2666 mode->vtotal = mode->vdisplay + vblank;
f453ba04 2667
7064fef5
JB		 2668 /* Some EDIDs have bogus h/vtotal values */
2669 if (mode->hsync_end > mode->htotal)
2670 mode->htotal = mode->hsync_end + 1;
2671 if (mode->vsync_end > mode->vtotal)
2672 mode->vtotal = mode->vsync_end + 1;
2673
b58db2c6 2674 drm_mode_do_interlace_quirk(mode, pt);
f453ba04
DA		 2675
2676 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
0454beab 2677 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
f453ba04
DA		 2678 }
2679
0454beab
MD		 2680 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
2681 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
2682 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
2683 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
f453ba04 2684
bc42aabc 2685set_size:
e14cbee4
MD		 2686 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
2687 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
f453ba04
DA		 2688
2689 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
2690 mode->width_mm *= 10;
2691 mode->height_mm *= 10;
2692 }
2693
2694 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
2695 mode->width_mm = edid->width_cm * 10;
2696 mode->height_mm = edid->height_cm * 10;
2697 }
2698
bc42aabc
AJ		 2699 mode->type = DRM_MODE_TYPE_DRIVER;
2700 drm_mode_set_name(mode);
2701
f453ba04
DA		 2702 return mode;
2703}
2704
b17e52ef 2705static bool
b1f559ec
CW		 2706mode_in_hsync_range(const struct drm_display_mode *mode,
2707 struct edid *edid, u8 *t)
b17e52ef
AJ		 2708{
2709 int hsync, hmin, hmax;
2710
2711 hmin = t[7];
2712 if (edid->revision >= 4)
2713 hmin += ((t[4] & 0x04) ? 255 : 0);
2714 hmax = t[8];
2715 if (edid->revision >= 4)
2716 hmax += ((t[4] & 0x08) ? 255 : 0);
07a5e632 2717 hsync = drm_mode_hsync(mode);
07a5e632 2718
b17e52ef
AJ		 2719 return (hsync <= hmax && hsync >= hmin);
2720}
2721
2722static bool
b1f559ec
CW		 2723mode_in_vsync_range(const struct drm_display_mode *mode,
2724 struct edid *edid, u8 *t)
b17e52ef
AJ		 2725{
2726 int vsync, vmin, vmax;
2727
2728 vmin = t[5];
2729 if (edid->revision >= 4)
2730 vmin += ((t[4] & 0x01) ? 255 : 0);
2731 vmax = t[6];
2732 if (edid->revision >= 4)
2733 vmax += ((t[4] & 0x02) ? 255 : 0);
2734 vsync = drm_mode_vrefresh(mode);
2735
2736 return (vsync <= vmax && vsync >= vmin);
2737}
2738
2739static u32
2740range_pixel_clock(struct edid *edid, u8 *t)
2741{
2742 /* unspecified */
2743 if (t[9] == 0 || t[9] == 255)
2744 return 0;
2745
2746 /* 1.4 with CVT support gives us real precision, yay */
2747 if (edid->revision >= 4 && t[10] == 0x04)
2748 return (t[9] * 10000) - ((t[12] >> 2) * 250);
2749
2750 /* 1.3 is pathetic, so fuzz up a bit */
2751 return t[9] * 10000 + 5001;
2752}
2753
b17e52ef 2754static bool
b1f559ec 2755mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
b17e52ef
AJ		 2756 struct detailed_timing *timing)
2757{
2758 u32 max_clock;
2759 u8 *t = (u8 *)timing;
2760
2761 if (!mode_in_hsync_range(mode, edid, t))
07a5e632
AJ		 2762 return false;
2763
b17e52ef 2764 if (!mode_in_vsync_range(mode, edid, t))
07a5e632
AJ		 2765 return false;
2766
b17e52ef 2767 if ((max_clock = range_pixel_clock(edid, t)))
07a5e632
AJ		 2768 if (mode->clock > max_clock)
2769 return false;
b17e52ef
AJ		 2770
2771 /* 1.4 max horizontal check */
2772 if (edid->revision >= 4 && t[10] == 0x04)
2773 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
2774 return false;
2775
2776 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
2777 return false;
07a5e632
AJ		 2778
2779 return true;
2780}
2781
7b668ebe
TI		 2782static bool valid_inferred_mode(const struct drm_connector *connector,
2783 const struct drm_display_mode *mode)
2784{
85f8fcd6 2785 const struct drm_display_mode *m;
7b668ebe
TI		 2786 bool ok = false;
2787
2788 list_for_each_entry(m, &connector->probed_modes, head) {
2789 if (mode->hdisplay == m->hdisplay &&
2790 mode->vdisplay == m->vdisplay &&
2791 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
2792 return false; /* duplicated */
2793 if (mode->hdisplay <= m->hdisplay &&
2794 mode->vdisplay <= m->vdisplay)
2795 ok = true;
2796 }
2797 return ok;
2798}
2799
b17e52ef 2800static int
cd4cd3de 2801drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
b17e52ef 2802 struct detailed_timing *timing)
07a5e632
AJ		 2803{
2804 int i, modes = 0;
2805 struct drm_display_mode *newmode;
2806 struct drm_device *dev = connector->dev;
2807
a6b21831 2808 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
7b668ebe
TI		 2809 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
2810 valid_inferred_mode(connector, drm_dmt_modes + i)) {
07a5e632
AJ		 2811 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
2812 if (newmode) {
2813 drm_mode_probed_add(connector, newmode);
2814 modes++;
2815 }
2816 }
2817 }
2818
2819 return modes;
2820}
2821
c09dedb7
TI		 2822/* fix up 1366x768 mode from 1368x768;
2823 * GFT/CVT can't express 1366 width which isn't dividable by 8
2824 */
969218fe 2825void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
c09dedb7
TI		 2826{
2827 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
2828 mode->hdisplay = 1366;
2829 mode->hsync_start--;
2830 mode->hsync_end--;
2831 drm_mode_set_name(mode);
2832 }
2833}
2834
b309bd37
AJ		 2835static int
2836drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
2837 struct detailed_timing *timing)
2838{
2839 int i, modes = 0;
2840 struct drm_display_mode *newmode;
2841 struct drm_device *dev = connector->dev;
2842
a6b21831 2843 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
b309bd37 2844 const struct minimode *m = &extra_modes[i];
948de842 2845
b309bd37 2846 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
fc48f169
TI		 2847 if (!newmode)
2848 return modes;
b309bd37 2849
969218fe 2850 drm_mode_fixup_1366x768(newmode);
7b668ebe
TI		 2851 if (!mode_in_range(newmode, edid, timing) ||
2852 !valid_inferred_mode(connector, newmode)) {
b309bd37
AJ		 2853 drm_mode_destroy(dev, newmode);
2854 continue;
2855 }
2856
2857 drm_mode_probed_add(connector, newmode);
2858 modes++;
2859 }
2860
2861 return modes;
2862}
2863
2864static int
2865drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2866 struct detailed_timing *timing)
2867{
2868 int i, modes = 0;
2869 struct drm_display_mode *newmode;
2870 struct drm_device *dev = connector->dev;
2871 bool rb = drm_monitor_supports_rb(edid);
2872
a6b21831 2873 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
b309bd37 2874 const struct minimode *m = &extra_modes[i];
948de842 2875
b309bd37 2876 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
fc48f169
TI		 2877 if (!newmode)
2878 return modes;
b309bd37 2879
969218fe 2880 drm_mode_fixup_1366x768(newmode);
7b668ebe
TI		 2881 if (!mode_in_range(newmode, edid, timing) ||
2882 !valid_inferred_mode(connector, newmode)) {
b309bd37
AJ		 2883 drm_mode_destroy(dev, newmode);
2884 continue;
2885 }
2886
2887 drm_mode_probed_add(connector, newmode);
2888 modes++;
2889 }
2890
2891 return modes;
2892}
2893
13931579
AJ		 2894static void
2895do_inferred_modes(struct detailed_timing *timing, void *c)
9340d8cf 2896{
13931579
AJ		 2897 struct detailed_mode_closure *closure = c;
2898 struct detailed_non_pixel *data = &timing->data.other_data;
b309bd37 2899 struct detailed_data_monitor_range *range = &data->data.range;
9340d8cf 2900
a7a131ac 2901 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE))
cb21aafe
AJ		 2902 return;
2903
2904 closure->modes += drm_dmt_modes_for_range(closure->connector,
2905 closure->edid,
2906 timing);
4d23f484 2907
b309bd37
AJ		 2908 if (!version_greater(closure->edid, 1, 1))
2909 return; /* GTF not defined yet */
2910
2911 switch (range->flags) {
2912 case 0x02: /* secondary gtf, XXX could do more */
2913 case 0x00: /* default gtf */
2914 closure->modes += drm_gtf_modes_for_range(closure->connector,
2915 closure->edid,
2916 timing);
2917 break;
2918 case 0x04: /* cvt, only in 1.4+ */
2919 if (!version_greater(closure->edid, 1, 3))
2920 break;
2921
2922 closure->modes += drm_cvt_modes_for_range(closure->connector,
2923 closure->edid,
2924 timing);
2925 break;
2926 case 0x01: /* just the ranges, no formula */
2927 default:
2928 break;
2929 }
13931579 2930}
69da3015 2931
13931579
AJ		 2932static int
2933add_inferred_modes(struct drm_connector *connector, struct edid *edid)
2934{
2935 struct detailed_mode_closure closure = {
d456ea2e
JL		 2936 .connector = connector,
2937 .edid = edid,
13931579 2938 };
9340d8cf 2939
13931579
AJ		 2940 if (version_greater(edid, 1, 0))
2941 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
2942 &closure);
9340d8cf 2943
13931579 2944 return closure.modes;
9340d8cf
AJ		 2945}
2946
2255be14
AJ		 2947static int
2948drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
2949{
2950 int i, j, m, modes = 0;
2951 struct drm_display_mode *mode;
f3a32d74 2952 u8 *est = ((u8 *)timing) + 6;
2255be14
AJ		 2953
2954 for (i = 0; i < 6; i++) {
891a7469 2955 for (j = 7; j >= 0; j--) {
2255be14 2956 m = (i * 8) + (7 - j);
3c581411 2957 if (m >= ARRAY_SIZE(est3_modes))
2255be14
AJ		 2958 break;
2959 if (est[i] & (1 << j)) {
1d42bbc8
DA		 2960 mode = drm_mode_find_dmt(connector->dev,
2961 est3_modes[m].w,
2962 est3_modes[m].h,
f6e252ba
AJ		 2963 est3_modes[m].r,
2964 est3_modes[m].rb);
2255be14
AJ		 2965 if (mode) {
2966 drm_mode_probed_add(connector, mode);
2967 modes++;
2968 }
2969 }
2970 }
2971 }
2972
2973 return modes;
2974}
2975
13931579
AJ		 2976static void
2977do_established_modes(struct detailed_timing *timing, void *c)
9cf00977 2978{
13931579 2979 struct detailed_mode_closure *closure = c;
9cf00977 2980
a7a131ac
VS		 2981 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_EST_TIMINGS))
2982 return;
2983
2984 closure->modes += drm_est3_modes(closure->connector, timing);
13931579 2985}
9cf00977 2986
13931579
AJ		 2987/**
2988 * add_established_modes - get est. modes from EDID and add them
db6cf833 2989 * @connector: connector to add mode(s) to
13931579
AJ		 2990 * @edid: EDID block to scan
2991 *
2992 * Each EDID block contains a bitmap of the supported "established modes" list
2993 * (defined above). Tease them out and add them to the global modes list.
2994 */
2995static int
2996add_established_modes(struct drm_connector *connector, struct edid *edid)
2997{
2998 struct drm_device *dev = connector->dev;
2999 unsigned long est_bits = edid->established_timings.t1 |
3000 (edid->established_timings.t2 << 8) |
3001 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
3002 int i, modes = 0;
3003 struct detailed_mode_closure closure = {
d456ea2e
JL		 3004 .connector = connector,
3005 .edid = edid,
13931579 3006 };
9cf00977 3007
13931579
AJ		 3008 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
3009 if (est_bits & (1<<i)) {
3010 struct drm_display_mode *newmode;
948de842 3011
13931579
AJ		 3012 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
3013 if (newmode) {
3014 drm_mode_probed_add(connector, newmode);
3015 modes++;
3016 }
3017 }
9cf00977
AJ		 3018 }
3019
13931579
AJ		 3020 if (version_greater(edid, 1, 0))
3021 drm_for_each_detailed_block((u8 *)edid,
3022 do_established_modes, &closure);
3023
3024 return modes + closure.modes;
3025}
3026
3027static void
3028do_standard_modes(struct detailed_timing *timing, void *c)
3029{
3030 struct detailed_mode_closure *closure = c;
3031 struct detailed_non_pixel *data = &timing->data.other_data;
3032 struct drm_connector *connector = closure->connector;
3033 struct edid *edid = closure->edid;
a7a131ac 3034 int i;
13931579 3035
a7a131ac
VS		 3036 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_STD_MODES))
3037 return;
9cf00977 3038
a7a131ac
VS		 3039 for (i = 0; i < 6; i++) {
3040 struct std_timing *std = &data->data.timings[i];
3041 struct drm_display_mode *newmode;
3042
3043 newmode = drm_mode_std(connector, edid, std);
3044 if (newmode) {
3045 drm_mode_probed_add(connector, newmode);
3046 closure->modes++;
9cf00977 3047 }
9cf00977 3048 }
9cf00977
AJ		 3049}
3050
f453ba04 3051/**
13931579 3052 * add_standard_modes - get std. modes from EDID and add them
db6cf833 3053 * @connector: connector to add mode(s) to
f453ba04 3054 * @edid: EDID block to scan
f453ba04 3055 *
13931579
AJ		 3056 * Standard modes can be calculated using the appropriate standard (DMT,
3057 * GTF or CVT. Grab them from @edid and add them to the list.
f453ba04 3058 */
13931579
AJ		 3059static int
3060add_standard_modes(struct drm_connector *connector, struct edid *edid)
f453ba04 3061{
9cf00977 3062 int i, modes = 0;
13931579 3063 struct detailed_mode_closure closure = {
d456ea2e
JL		 3064 .connector = connector,
3065 .edid = edid,
13931579
AJ		 3066 };
3067
3068 for (i = 0; i < EDID_STD_TIMINGS; i++) {
3069 struct drm_display_mode *newmode;
3070
3071 newmode = drm_mode_std(connector, edid,
464fdeca 3072 &edid->standard_timings[i]);
13931579
AJ		 3073 if (newmode) {
3074 drm_mode_probed_add(connector, newmode);
3075 modes++;
3076 }
3077 }
3078
3079 if (version_greater(edid, 1, 0))
3080 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
3081 &closure);
3082
3083 /* XXX should also look for standard codes in VTB blocks */
3084
3085 return modes + closure.modes;
3086}
f453ba04 3087
13931579
AJ		 3088static int drm_cvt_modes(struct drm_connector *connector,
3089 struct detailed_timing *timing)
3090{
3091 int i, j, modes = 0;
3092 struct drm_display_mode *newmode;
3093 struct drm_device *dev = connector->dev;
3094 struct cvt_timing *cvt;
3095 const int rates[] = { 60, 85, 75, 60, 50 };
3096 const u8 empty[3] = { 0, 0, 0 };
a327f6b8 3097
13931579 3098 for (i = 0; i < 4; i++) {
3f649ab7 3099 int width, height;
948de842 3100
13931579 3101 cvt = &(timing->data.other_data.data.cvt[i]);
f453ba04 3102
13931579 3103 if (!memcmp(cvt->code, empty, 3))
9cf00977 3104 continue;
f453ba04 3105
13931579
AJ		 3106 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
3107 switch (cvt->code[1] & 0x0c) {
d652d5f1
LT		 3108 /* default - because compiler doesn't see that we've enumerated all cases */
3109 default:
13931579
AJ		 3110 case 0x00:
3111 width = height * 4 / 3;
3112 break;
3113 case 0x04:
3114 width = height * 16 / 9;
3115 break;
3116 case 0x08:
3117 width = height * 16 / 10;
3118 break;
3119 case 0x0c:
3120 width = height * 15 / 9;
3121 break;
3122 }
3123
3124 for (j = 1; j < 5; j++) {
3125 if (cvt->code[2] & (1 << j)) {
3126 newmode = drm_cvt_mode(dev, width, height,
3127 rates[j], j == 0,
3128 false, false);
3129 if (newmode) {
3130 drm_mode_probed_add(connector, newmode);
3131 modes++;
3132 }
3133 }
3134 }
f453ba04
DA		 3135 }
3136
3137 return modes;
3138}
9cf00977 3139
13931579
AJ		 3140static void
3141do_cvt_mode(struct detailed_timing *timing, void *c)
882f0219 3142{
13931579 3143 struct detailed_mode_closure *closure = c;
882f0219 3144
a7a131ac
VS		 3145 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_CVT_3BYTE))
3146 return;
3147
3148 closure->modes += drm_cvt_modes(closure->connector, timing);
13931579 3149}
882f0219 3150
13931579
AJ		 3151static int
3152add_cvt_modes(struct drm_connector *connector, struct edid *edid)
4d23f484 3153{
13931579 3154 struct detailed_mode_closure closure = {
d456ea2e
JL		 3155 .connector = connector,
3156 .edid = edid,
13931579 3157 };
882f0219 3158
13931579
AJ		 3159 if (version_greater(edid, 1, 2))
3160 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
882f0219 3161
13931579 3162 /* XXX should also look for CVT codes in VTB blocks */
882f0219 3163
13931579
AJ		 3164 return closure.modes;
3165}
3166
fa3a7340
VS		 3167static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
3168
13931579
AJ		 3169static void
3170do_detailed_mode(struct detailed_timing *timing, void *c)
3171{
3172 struct detailed_mode_closure *closure = c;
3173 struct drm_display_mode *newmode;
3174
f447dd1f
VS		 3175 if (!is_detailed_timing_descriptor((const u8 *)timing))
3176 return;
3177
3178 newmode = drm_mode_detailed(closure->connector->dev,
3179 closure->edid, timing,
3180 closure->quirks);
3181 if (!newmode)
3182 return;
13931579 3183
f447dd1f
VS		 3184 if (closure->preferred)
3185 newmode->type |= DRM_MODE_TYPE_PREFERRED;
13931579 3186
f447dd1f
VS		 3187 /*
3188 * Detailed modes are limited to 10kHz pixel clock resolution,
3189 * so fix up anything that looks like CEA/HDMI mode, but the clock
3190 * is just slightly off.
3191 */
3192 fixup_detailed_cea_mode_clock(newmode);
fa3a7340 3193
f447dd1f
VS		 3194 drm_mode_probed_add(closure->connector, newmode);
3195 closure->modes++;
3196 closure->preferred = false;
13931579 3197}
882f0219 3198
13931579
AJ		 3199/*
3200 * add_detailed_modes - Add modes from detailed timings
3201 * @connector: attached connector
3202 * @edid: EDID block to scan
3203 * @quirks: quirks to apply
3204 */
3205static int
3206add_detailed_modes(struct drm_connector *connector, struct edid *edid,
3207 u32 quirks)
3208{
3209 struct detailed_mode_closure closure = {
d456ea2e
JL		 3210 .connector = connector,
3211 .edid = edid,
c2925bde 3212 .preferred = true,
d456ea2e 3213 .quirks = quirks,
13931579
AJ		 3214 };
3215
3216 if (closure.preferred && !version_greater(edid, 1, 3))
3217 closure.preferred =
3218 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
3219
3220 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
3221
3222 return closure.modes;
882f0219 3223}
f453ba04 3224
8fe9790d 3225#define AUDIO_BLOCK 0x01
54ac76f8 3226#define VIDEO_BLOCK 0x02
f23c20c8 3227#define VENDOR_BLOCK 0x03
76adaa34 3228#define SPEAKER_BLOCK 0x04
e85959d6 3229#define HDR_STATIC_METADATA_BLOCK 0x6
87563fc0
SS		 3230#define USE_EXTENDED_TAG 0x07
3231#define EXT_VIDEO_CAPABILITY_BLOCK 0x00
832d4f2f
SS		 3232#define EXT_VIDEO_DATA_BLOCK_420 0x0E
3233#define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F
8fe9790d 3234#define EDID_BASIC_AUDIO (1 << 6)
a988bc72
LPC		 3235#define EDID_CEA_YCRCB444 (1 << 5)
3236#define EDID_CEA_YCRCB422 (1 << 4)
b1edd6a6 3237#define EDID_CEA_VCDB_QS (1 << 6)
8fe9790d 3238
d4e4a31d 3239/*
8fe9790d 3240 * Search EDID for CEA extension block.
f23c20c8 3241 */
4cc4f09e
JN		 3242const u8 *drm_find_edid_extension(const struct edid *edid,
3243 int ext_id, int *ext_index)
f23c20c8 3244{
43d16d84 3245 const u8 *edid_ext = NULL;
8fe9790d 3246 int i;
f23c20c8
ML		 3247
3248 /* No EDID or EDID extensions */
3249 if (edid == NULL || edid->extensions == 0)
8fe9790d 3250 return NULL;
f23c20c8 3251
f23c20c8 3252 /* Find CEA extension */
8873cfa3 3253 for (i = *ext_index; i < edid->extensions; i++) {
43d16d84 3254 edid_ext = (const u8 *)edid + EDID_LENGTH * (i + 1);
40d9b043 3255 if (edid_ext[0] == ext_id)
f23c20c8
ML		 3256 break;
3257 }
3258
8873cfa3 3259 if (i >= edid->extensions)
8fe9790d
ZW		 3260 return NULL;
3261
8873cfa3
VS		 3262 *ext_index = i + 1;
3263
8fe9790d
ZW		 3264 return edid_ext;
3265}
3266
43d16d84 3267static const u8 *drm_find_cea_extension(const struct edid *edid)
e28ad544 3268{
43d16d84 3269 const struct displayid_block *block;
1ba63caf 3270 struct displayid_iter iter;
43d16d84 3271 const u8 *cea;
1ba63caf 3272 int ext_index = 0;
e28ad544
AR		 3273
3274 /* Look for a top level CEA extension block */
7f261afd 3275 /* FIXME: make callers iterate through multiple CEA ext blocks? */
8873cfa3 3276 cea = drm_find_edid_extension(edid, CEA_EXT, &ext_index);
e28ad544
AR		 3277 if (cea)
3278 return cea;
3279
3280 /* CEA blocks can also be found embedded in a DisplayID block */
1ba63caf
JN		 3281 displayid_iter_edid_begin(edid, &iter);
3282 displayid_iter_for_each(block, &iter) {
3283 if (block->tag == DATA_BLOCK_CTA) {
3284 cea = (const u8 *)block;
3285 break;
e28ad544
AR		 3286 }
3287 }
1ba63caf 3288 displayid_iter_end(&iter);
e28ad544 3289
1ba63caf 3290 return cea;
e28ad544
AR		 3291}
3292
e1cf35b9 3293static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic)
7befe621 3294{
9212f8ee
VS		 3295 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127);
3296 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219);
3297
8c1b2bd9
VS		 3298 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1))
3299 return &edid_cea_modes_1[vic - 1];
f7655d42
VS		 3300 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193))
3301 return &edid_cea_modes_193[vic - 193];
7befe621
VS		 3302 return NULL;
3303}
3304
3305static u8 cea_num_vics(void)
3306{
f7655d42 3307 return 193 + ARRAY_SIZE(edid_cea_modes_193);
7befe621
VS		 3308}
3309
3310static u8 cea_next_vic(u8 vic)
3311{
8c1b2bd9 3312 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1))
f7655d42
VS		 3313 vic = 193;
3314 return vic;
7befe621
VS		 3315}
3316
e6e79209
VS		 3317/*
3318 * Calculate the alternate clock for the CEA mode
3319 * (60Hz vs. 59.94Hz etc.)
3320 */
3321static unsigned int
3322cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
3323{
3324 unsigned int clock = cea_mode->clock;
3325
0425662f 3326 if (drm_mode_vrefresh(cea_mode) % 6 != 0)
e6e79209
VS		 3327 return clock;
3328
3329 /*
3330 * edid_cea_modes contains the 59.94Hz
3331 * variant for 240 and 480 line modes,
3332 * and the 60Hz variant otherwise.
3333 */
3334 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
9afd808c 3335 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
e6e79209 3336 else
9afd808c 3337 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
e6e79209
VS		 3338
3339 return clock;
3340}
3341
c45a4e46
VS		 3342static bool
3343cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
3344{
3345 /*
3346 * For certain VICs the spec allows the vertical
3347 * front porch to vary by one or two lines.
3348 *
3349 * cea_modes[] stores the variant with the shortest
3350 * vertical front porch. We can adjust the mode to
3351 * get the other variants by simply increasing the
3352 * vertical front porch length.
3353 */
7befe621
VS		 3354 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 ||
3355 cea_mode_for_vic(9)->vtotal != 262 ||
3356 cea_mode_for_vic(12)->vtotal != 262 ||
3357 cea_mode_for_vic(13)->vtotal != 262 ||
3358 cea_mode_for_vic(23)->vtotal != 312 ||
3359 cea_mode_for_vic(24)->vtotal != 312 ||
3360 cea_mode_for_vic(27)->vtotal != 312 ||
3361 cea_mode_for_vic(28)->vtotal != 312);
c45a4e46
VS		 3362
3363 if (((vic == 8 || vic == 9 ||
3364 vic == 12 || vic == 13) && mode->vtotal < 263) ||
3365 ((vic == 23 || vic == 24 ||
3366 vic == 27 || vic == 28) && mode->vtotal < 314)) {
3367 mode->vsync_start++;
3368 mode->vsync_end++;
3369 mode->vtotal++;
3370
3371 return true;
3372 }
3373
3374 return false;
3375}
3376
4c6bcf44
VS		 3377static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
3378 unsigned int clock_tolerance)
3379{
357768cc 3380 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 3381 u8 vic;
4c6bcf44
VS		 3382
3383 if (!to_match->clock)
3384 return 0;
3385
357768cc
VS		 3386 if (to_match->picture_aspect_ratio)
3387 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3388
7befe621
VS		 3389 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
3390 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic);
4c6bcf44
VS		 3391 unsigned int clock1, clock2;
3392
3393 /* Check both 60Hz and 59.94Hz */
c45a4e46
VS		 3394 clock1 = cea_mode.clock;
3395 clock2 = cea_mode_alternate_clock(&cea_mode);
4c6bcf44
VS		 3396
3397 if (abs(to_match->clock - clock1) > clock_tolerance &&
3398 abs(to_match->clock - clock2) > clock_tolerance)
3399 continue;
3400
c45a4e46 3401 do {
357768cc 3402 if (drm_mode_match(to_match, &cea_mode, match_flags))
c45a4e46
VS		 3403 return vic;
3404 } while (cea_mode_alternate_timings(vic, &cea_mode));
4c6bcf44
VS		 3405 }
3406
3407 return 0;
3408}
3409
18316c8c
TR		 3410/**
3411 * drm_match_cea_mode - look for a CEA mode matching given mode
3412 * @to_match: display mode
3413 *
db6cf833 3414 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
18316c8c 3415 * mode.
a4799037 3416 */
18316c8c 3417u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
a4799037 3418{
357768cc 3419 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 3420 u8 vic;
a4799037 3421
a90b590e
VS		 3422 if (!to_match->clock)
3423 return 0;
3424
357768cc
VS		 3425 if (to_match->picture_aspect_ratio)
3426 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3427
7befe621
VS		 3428 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
3429 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic);
a90b590e
VS		 3430 unsigned int clock1, clock2;
3431
a90b590e 3432 /* Check both 60Hz and 59.94Hz */
c45a4e46
VS		 3433 clock1 = cea_mode.clock;
3434 clock2 = cea_mode_alternate_clock(&cea_mode);
a4799037 3435
c45a4e46
VS		 3436 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
3437 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
3438 continue;
3439
3440 do {
357768cc 3441 if (drm_mode_match(to_match, &cea_mode, match_flags))
c45a4e46
VS		 3442 return vic;
3443 } while (cea_mode_alternate_timings(vic, &cea_mode));
a4799037 3444 }
c45a4e46 3445
a4799037
SM		 3446 return 0;
3447}
3448EXPORT_SYMBOL(drm_match_cea_mode);
3449
d9278b4c
JN		 3450static bool drm_valid_cea_vic(u8 vic)
3451{
7befe621 3452 return cea_mode_for_vic(vic) != NULL;
d9278b4c
JN		 3453}
3454
28c03a44 3455static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
0967e6a5 3456{
7befe621
VS		 3457 const struct drm_display_mode *mode = cea_mode_for_vic(video_code);
3458
3459 if (mode)
3460 return mode->picture_aspect_ratio;
3461
3462 return HDMI_PICTURE_ASPECT_NONE;
0967e6a5 3463}
0967e6a5 3464
d2b43473
WL		 3465static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code)
3466{
3467 return edid_4k_modes[video_code].picture_aspect_ratio;
3468}
3469
3f2f6533
LD		 3470/*
3471 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
3472 * specific block).
3f2f6533
LD		 3473 */
3474static unsigned int
3475hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
3476{
3f2f6533
LD		 3477 return cea_mode_alternate_clock(hdmi_mode);
3478}
3479
4c6bcf44
VS		 3480static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
3481 unsigned int clock_tolerance)
3482{
357768cc 3483 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 3484 u8 vic;
4c6bcf44
VS		 3485
3486 if (!to_match->clock)
3487 return 0;
3488
d2b43473
WL		 3489 if (to_match->picture_aspect_ratio)
3490 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3491
d9278b4c
JN		 3492 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3493 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4c6bcf44
VS		 3494 unsigned int clock1, clock2;
3495
3496 /* Make sure to also match alternate clocks */
3497 clock1 = hdmi_mode->clock;
3498 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3499
3500 if (abs(to_match->clock - clock1) > clock_tolerance &&
3501 abs(to_match->clock - clock2) > clock_tolerance)
3502 continue;
3503
357768cc 3504 if (drm_mode_match(to_match, hdmi_mode, match_flags))
d9278b4c 3505 return vic;
4c6bcf44
VS		 3506 }
3507
3508 return 0;
3509}
3510
3f2f6533
LD		 3511/*
3512 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
3513 * @to_match: display mode
3514 *
3515 * An HDMI mode is one defined in the HDMI vendor specific block.
3516 *
3517 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
3518 */
3519static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
3520{
357768cc 3521 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 3522 u8 vic;
3f2f6533
LD		 3523
3524 if (!to_match->clock)
3525 return 0;
3526
d2b43473
WL		 3527 if (to_match->picture_aspect_ratio)
3528 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3529
d9278b4c
JN		 3530 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3531 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3f2f6533
LD		 3532 unsigned int clock1, clock2;
3533
3534 /* Make sure to also match alternate clocks */
3535 clock1 = hdmi_mode->clock;
3536 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3537
3538 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
3539 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
357768cc 3540 drm_mode_match(to_match, hdmi_mode, match_flags))
d9278b4c 3541 return vic;
3f2f6533
LD		 3542 }
3543 return 0;
3544}
3545
d9278b4c
JN		 3546static bool drm_valid_hdmi_vic(u8 vic)
3547{
3548 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
3549}
3550
e6e79209
VS		 3551static int
3552add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
3553{
3554 struct drm_device *dev = connector->dev;
3555 struct drm_display_mode *mode, *tmp;
3556 LIST_HEAD(list);
3557 int modes = 0;
3558
3559 /* Don't add CEA modes if the CEA extension block is missing */
3560 if (!drm_find_cea_extension(edid))
3561 return 0;
3562
3563 /*
3564 * Go through all probed modes and create a new mode
3565 * with the alternate clock for certain CEA modes.
3566 */
3567 list_for_each_entry(mode, &connector->probed_modes, head) {
3f2f6533 3568 const struct drm_display_mode *cea_mode = NULL;
e6e79209 3569 struct drm_display_mode *newmode;
d9278b4c 3570 u8 vic = drm_match_cea_mode(mode);
e6e79209
VS		 3571 unsigned int clock1, clock2;
3572
d9278b4c 3573 if (drm_valid_cea_vic(vic)) {
7befe621 3574 cea_mode = cea_mode_for_vic(vic);
3f2f6533
LD		 3575 clock2 = cea_mode_alternate_clock(cea_mode);
3576 } else {
d9278b4c
JN		 3577 vic = drm_match_hdmi_mode(mode);
3578 if (drm_valid_hdmi_vic(vic)) {
3579 cea_mode = &edid_4k_modes[vic];
3f2f6533
LD		 3580 clock2 = hdmi_mode_alternate_clock(cea_mode);
3581 }
3582 }
e6e79209 3583
3f2f6533
LD		 3584 if (!cea_mode)
3585 continue;
e6e79209
VS		 3586
3587 clock1 = cea_mode->clock;
e6e79209
VS		 3588
3589 if (clock1 == clock2)
3590 continue;
3591
3592 if (mode->clock != clock1 && mode->clock != clock2)
3593 continue;
3594
3595 newmode = drm_mode_duplicate(dev, cea_mode);
3596 if (!newmode)
3597 continue;
3598
27130212
DL		 3599 /* Carry over the stereo flags */
3600 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
3601
e6e79209
VS		 3602 /*
3603 * The current mode could be either variant. Make
3604 * sure to pick the "other" clock for the new mode.
3605 */
3606 if (mode->clock != clock1)
3607 newmode->clock = clock1;
3608 else
3609 newmode->clock = clock2;
3610
3611 list_add_tail(&newmode->head, &list);
3612 }
3613
3614 list_for_each_entry_safe(mode, tmp, &list, head) {
3615 list_del(&mode->head);
3616 drm_mode_probed_add(connector, mode);
3617 modes++;
3618 }
3619
3620 return modes;
3621}
a4799037 3622
8ec6e075
SS		 3623static u8 svd_to_vic(u8 svd)
3624{
3625 /* 0-6 bit vic, 7th bit native mode indicator */
3626 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
3627 return svd & 127;
3628
3629 return svd;
3630}
3631
aff04ace
TW		 3632static struct drm_display_mode *
3633drm_display_mode_from_vic_index(struct drm_connector *connector,
3634 const u8 *video_db, u8 video_len,
3635 u8 video_index)
54ac76f8
CS		 3636{
3637 struct drm_device *dev = connector->dev;
aff04ace 3638 struct drm_display_mode *newmode;
d9278b4c 3639 u8 vic;
54ac76f8 3640
aff04ace
TW		 3641 if (video_db == NULL || video_index >= video_len)
3642 return NULL;
3643
3644 /* CEA modes are numbered 1..127 */
8ec6e075 3645 vic = svd_to_vic(video_db[video_index]);
d9278b4c 3646 if (!drm_valid_cea_vic(vic))
aff04ace
TW		 3647 return NULL;
3648
7befe621 3649 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
409bbf1e
DL		 3650 if (!newmode)
3651 return NULL;
3652
aff04ace
TW		 3653 return newmode;
3654}
3655
832d4f2f
SS		 3656/*
3657 * do_y420vdb_modes - Parse YCBCR 420 only modes
3658 * @connector: connector corresponding to the HDMI sink
3659 * @svds: start of the data block of CEA YCBCR 420 VDB
3660 * @len: length of the CEA YCBCR 420 VDB
3661 *
3662 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
3663 * which contains modes which can be supported in YCBCR 420
3664 * output format only.
3665 */
3666static int do_y420vdb_modes(struct drm_connector *connector,
3667 const u8 *svds, u8 svds_len)
3668{
3669 int modes = 0, i;
3670 struct drm_device *dev = connector->dev;
3671 struct drm_display_info *info = &connector->display_info;
3672 struct drm_hdmi_info *hdmi = &info->hdmi;
3673
3674 for (i = 0; i < svds_len; i++) {
3675 u8 vic = svd_to_vic(svds[i]);
3676 struct drm_display_mode *newmode;
3677
3678 if (!drm_valid_cea_vic(vic))
3679 continue;
3680
7befe621 3681 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
832d4f2f
SS		 3682 if (!newmode)
3683 break;
3684 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
3685 drm_mode_probed_add(connector, newmode);
3686 modes++;
3687 }
3688
3689 if (modes > 0)
3690 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3691 return modes;
3692}
3693
3694/*
3695 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap
3696 * @connector: connector corresponding to the HDMI sink
3697 * @vic: CEA vic for the video mode to be added in the map
3698 *
3699 * Makes an entry for a videomode in the YCBCR 420 bitmap
3700 */
3701static void
3702drm_add_cmdb_modes(struct drm_connector *connector, u8 svd)
3703{
3704 u8 vic = svd_to_vic(svd);
3705 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3706
3707 if (!drm_valid_cea_vic(vic))
3708 return;
3709
3710 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
3711}
3712
7af655bc
VS		 3713/**
3714 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC
3715 * @dev: DRM device
8d7d8c0a 3716 * @video_code: CEA VIC of the mode
7af655bc
VS		 3717 *
3718 * Creates a new mode matching the specified CEA VIC.
3719 *
3720 * Returns: A new drm_display_mode on success or NULL on failure
3721 */
3722struct drm_display_mode *
3723drm_display_mode_from_cea_vic(struct drm_device *dev,
3724 u8 video_code)
3725{
3726 const struct drm_display_mode *cea_mode;
3727 struct drm_display_mode *newmode;
3728
3729 cea_mode = cea_mode_for_vic(video_code);
3730 if (!cea_mode)
3731 return NULL;
3732
3733 newmode = drm_mode_duplicate(dev, cea_mode);
3734 if (!newmode)
3735 return NULL;
3736
3737 return newmode;
3738}
3739EXPORT_SYMBOL(drm_display_mode_from_cea_vic);
3740
aff04ace
TW		 3741static int
3742do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
3743{
3744 int i, modes = 0;
832d4f2f 3745 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
aff04ace
TW		 3746
3747 for (i = 0; i < len; i++) {
3748 struct drm_display_mode *mode;
948de842 3749
aff04ace
TW		 3750 mode = drm_display_mode_from_vic_index(connector, db, len, i);
3751 if (mode) {
832d4f2f
SS		 3752 /*
3753 * YCBCR420 capability block contains a bitmap which
3754 * gives the index of CEA modes from CEA VDB, which
3755 * can support YCBCR 420 sampling output also (apart
3756 * from RGB/YCBCR444 etc).
3757 * For example, if the bit 0 in bitmap is set,
3758 * first mode in VDB can support YCBCR420 output too.
3759 * Add YCBCR420 modes only if sink is HDMI 2.0 capable.
3760 */
3761 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i))
3762 drm_add_cmdb_modes(connector, db[i]);
3763
aff04ace
TW		 3764 drm_mode_probed_add(connector, mode);
3765 modes++;
54ac76f8
CS		 3766 }
3767 }
3768
3769 return modes;
3770}
3771
c858cfca
DL		 3772struct stereo_mandatory_mode {
3773 int width, height, vrefresh;
3774 unsigned int flags;
3775};
3776
3777static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
f7e121b7
DL		 3778 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3779 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
c858cfca
DL		 3780 { 1920, 1080, 50,
3781 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3782 { 1920, 1080, 60,
3783 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
f7e121b7
DL		 3784 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3785 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
3786 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3787 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
c858cfca
DL		 3788};
3789
3790static bool
3791stereo_match_mandatory(const struct drm_display_mode *mode,
3792 const struct stereo_mandatory_mode *stereo_mode)
3793{
3794 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
3795
3796 return mode->hdisplay == stereo_mode->width &&
3797 mode->vdisplay == stereo_mode->height &&
3798 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
3799 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
3800}
3801
c858cfca
DL		 3802static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
3803{
3804 struct drm_device *dev = connector->dev;
3805 const struct drm_display_mode *mode;
3806 struct list_head stereo_modes;
f7e121b7 3807 int modes = 0, i;
c858cfca
DL		 3808
3809 INIT_LIST_HEAD(&stereo_modes);
3810
3811 list_for_each_entry(mode, &connector->probed_modes, head) {
f7e121b7
DL		 3812 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
3813 const struct stereo_mandatory_mode *mandatory;
c858cfca
DL		 3814 struct drm_display_mode *new_mode;
3815
f7e121b7
DL		 3816 if (!stereo_match_mandatory(mode,
3817 &stereo_mandatory_modes[i]))
3818 continue;
c858cfca 3819
f7e121b7 3820 mandatory = &stereo_mandatory_modes[i];
c858cfca
DL		 3821 new_mode = drm_mode_duplicate(dev, mode);
3822 if (!new_mode)
3823 continue;
3824
f7e121b7 3825 new_mode->flags |= mandatory->flags;
c858cfca
DL		 3826 list_add_tail(&new_mode->head, &stereo_modes);
3827 modes++;
f7e121b7 3828 }
c858cfca
DL		 3829 }
3830
3831 list_splice_tail(&stereo_modes, &connector->probed_modes);
3832
3833 return modes;
3834}
3835
1deee8d7
DL		 3836static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
3837{
3838 struct drm_device *dev = connector->dev;
3839 struct drm_display_mode *newmode;
3840
d9278b4c 3841 if (!drm_valid_hdmi_vic(vic)) {
1deee8d7
DL		 3842 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
3843 return 0;
3844 }
3845
3846 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
3847 if (!newmode)
3848 return 0;
3849
3850 drm_mode_probed_add(connector, newmode);
3851
3852 return 1;
3853}
3854
fbf46025
TW		 3855static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
3856 const u8 *video_db, u8 video_len, u8 video_index)
3857{
fbf46025
TW		 3858 struct drm_display_mode *newmode;
3859 int modes = 0;
fbf46025
TW		 3860
3861 if (structure & (1 << 0)) {
aff04ace
TW		 3862 newmode = drm_display_mode_from_vic_index(connector, video_db,
3863 video_len,
3864 video_index);
fbf46025
TW		 3865 if (newmode) {
3866 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
3867 drm_mode_probed_add(connector, newmode);
3868 modes++;
3869 }
3870 }
3871 if (structure & (1 << 6)) {
aff04ace
TW		 3872 newmode = drm_display_mode_from_vic_index(connector, video_db,
3873 video_len,
3874 video_index);
fbf46025
TW		 3875 if (newmode) {
3876 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3877 drm_mode_probed_add(connector, newmode);
3878 modes++;
3879 }
3880 }
3881 if (structure & (1 << 8)) {
aff04ace
TW		 3882 newmode = drm_display_mode_from_vic_index(connector, video_db,
3883 video_len,
3884 video_index);
fbf46025 3885 if (newmode) {
89570eeb 3886 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
fbf46025
TW		 3887 drm_mode_probed_add(connector, newmode);
3888 modes++;
3889 }
3890 }
3891
3892 return modes;
3893}
3894
7ebe1963
LD		 3895/*
3896 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
3897 * @connector: connector corresponding to the HDMI sink
3898 * @db: start of the CEA vendor specific block
3899 * @len: length of the CEA block payload, ie. one can access up to db[len]
3900 *
c858cfca
DL		 3901 * Parses the HDMI VSDB looking for modes to add to @connector. This function
3902 * also adds the stereo 3d modes when applicable.
7ebe1963
LD		 3903 */
3904static int
fbf46025
TW		 3905do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
3906 const u8 *video_db, u8 video_len)
7ebe1963 3907{
f1781e9b 3908 struct drm_display_info *info = &connector->display_info;
0e5083aa 3909 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
fbf46025
TW		 3910 u8 vic_len, hdmi_3d_len = 0;
3911 u16 mask;
3912 u16 structure_all;
7ebe1963
LD		 3913
3914 if (len < 8)
3915 goto out;
3916
3917 /* no HDMI_Video_Present */
3918 if (!(db[8] & (1 << 5)))
3919 goto out;
3920
3921 /* Latency_Fields_Present */
3922 if (db[8] & (1 << 7))
3923 offset += 2;
3924
3925 /* I_Latency_Fields_Present */
3926 if (db[8] & (1 << 6))
3927 offset += 2;
3928
3929 /* the declared length is not long enough for the 2 first bytes
3930 * of additional video format capabilities */
c858cfca 3931 if (len < (8 + offset + 2))
7ebe1963
LD		 3932 goto out;
3933
c858cfca
DL		 3934 /* 3D_Present */
3935 offset++;
fbf46025 3936 if (db[8 + offset] & (1 << 7)) {
c858cfca
DL		 3937 modes += add_hdmi_mandatory_stereo_modes(connector);
3938
fbf46025
TW		 3939 /* 3D_Multi_present */
3940 multi_present = (db[8 + offset] & 0x60) >> 5;
3941 }
3942
c858cfca 3943 offset++;
7ebe1963 3944 vic_len = db[8 + offset] >> 5;
fbf46025 3945 hdmi_3d_len = db[8 + offset] & 0x1f;
7ebe1963
LD		 3946
3947 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
7ebe1963
LD		 3948 u8 vic;
3949
3950 vic = db[9 + offset + i];
1deee8d7 3951 modes += add_hdmi_mode(connector, vic);
7ebe1963 3952 }
fbf46025
TW		 3953 offset += 1 + vic_len;
3954
0e5083aa
TW		 3955 if (multi_present == 1)
3956 multi_len = 2;
3957 else if (multi_present == 2)
3958 multi_len = 4;
3959 else
3960 multi_len = 0;
fbf46025 3961
0e5083aa 3962 if (len < (8 + offset + hdmi_3d_len - 1))
fbf46025
TW		 3963 goto out;
3964
0e5083aa 3965 if (hdmi_3d_len < multi_len)
fbf46025
TW		 3966 goto out;
3967
0e5083aa
TW		 3968 if (multi_present == 1 || multi_present == 2) {
3969 /* 3D_Structure_ALL */
3970 structure_all = (db[8 + offset] << 8) | db[9 + offset];
fbf46025 3971
0e5083aa
TW		 3972 /* check if 3D_MASK is present */
3973 if (multi_present == 2)
3974 mask = (db[10 + offset] << 8) | db[11 + offset];
3975 else
3976 mask = 0xffff;
3977
3978 for (i = 0; i < 16; i++) {
3979 if (mask & (1 << i))
3980 modes += add_3d_struct_modes(connector,
3981 structure_all,
3982 video_db,
3983 video_len, i);
3984 }
3985 }
3986
3987 offset += multi_len;
3988
3989 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
3990 int vic_index;
3991 struct drm_display_mode *newmode = NULL;
3992 unsigned int newflag = 0;
3993 bool detail_present;
3994
3995 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
3996
3997 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
3998 break;
3999
4000 /* 2D_VIC_order_X */
4001 vic_index = db[8 + offset + i] >> 4;
4002
4003 /* 3D_Structure_X */
4004 switch (db[8 + offset + i] & 0x0f) {
4005 case 0:
4006 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
4007 break;
4008 case 6:
4009 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4010 break;
4011 case 8:
4012 /* 3D_Detail_X */
4013 if ((db[9 + offset + i] >> 4) == 1)
4014 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4015 break;
4016 }
4017
4018 if (newflag != 0) {
4019 newmode = drm_display_mode_from_vic_index(connector,
4020 video_db,
4021 video_len,
4022 vic_index);
4023
4024 if (newmode) {
4025 newmode->flags |= newflag;
4026 drm_mode_probed_add(connector, newmode);
4027 modes++;
4028 }
4029 }
4030
4031 if (detail_present)
4032 i++;
fbf46025 4033 }
7ebe1963
LD		 4034
4035out:
f1781e9b
VS		 4036 if (modes > 0)
4037 info->has_hdmi_infoframe = true;
7ebe1963
LD		 4038 return modes;
4039}
4040
9e50b9d5
VS		 4041static int
4042cea_db_payload_len(const u8 *db)
4043{
4044 return db[0] & 0x1f;
4045}
4046
87563fc0
SS		 4047static int
4048cea_db_extended_tag(const u8 *db)
4049{
4050 return db[1];
4051}
4052
9e50b9d5
VS		 4053static int
4054cea_db_tag(const u8 *db)
4055{
4056 return db[0] >> 5;
4057}
4058
4059static int
4060cea_revision(const u8 *cea)
4061{
5036c0d0
VS		 4062 /*
4063 * FIXME is this correct for the DispID variant?
4064 * The DispID spec doesn't really specify whether
4065 * this is the revision of the CEA extension or
4066 * the DispID CEA data block. And the only value
4067 * given as an example is 0.
4068 */
9e50b9d5
VS		 4069 return cea[1];
4070}
4071
4072static int
4073cea_db_offsets(const u8 *cea, int *start, int *end)
4074{
e28ad544
AR		 4075 /* DisplayID CTA extension blocks and top-level CEA EDID
4076 * block header definitions differ in the following bytes:
4077 * 1) Byte 2 of the header specifies length differently,
4078 * 2) Byte 3 is only present in the CEA top level block.
4079 *
4080 * The different definitions for byte 2 follow.
4081 *
4082 * DisplayID CTA extension block defines byte 2 as:
4083 * Number of payload bytes
4084 *
4085 * CEA EDID block defines byte 2 as:
4086 * Byte number (decimal) within this block where the 18-byte
4087 * DTDs begin. If no non-DTD data is present in this extension
4088 * block, the value should be set to 04h (the byte after next).
4089 * If set to 00h, there are no DTDs present in this block and
4090 * no non-DTD data.
4091 */
4092 if (cea[0] == DATA_BLOCK_CTA) {
6e8a942b
VS		 4093 /*
4094 * for_each_displayid_db() has already verified
4095 * that these stay within expected bounds.
4096 */
e28ad544
AR		 4097 *start = 3;
4098 *end = *start + cea[2];
4099 } else if (cea[0] == CEA_EXT) {
4100 /* Data block offset in CEA extension block */
4101 *start = 4;
4102 *end = cea[2];
4103 if (*end == 0)
4104 *end = 127;
4105 if (*end < 4 || *end > 127)
4106 return -ERANGE;
4107 } else {
c7581a41 4108 return -EOPNOTSUPP;
e28ad544
AR		 4109 }
4110
9e50b9d5
VS		 4111 return 0;
4112}
4113
7ebe1963
LD		 4114static bool cea_db_is_hdmi_vsdb(const u8 *db)
4115{
4116 int hdmi_id;
4117
4118 if (cea_db_tag(db) != VENDOR_BLOCK)
4119 return false;
4120
4121 if (cea_db_payload_len(db) < 5)
4122 return false;
4123
4124 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
4125
6cb3b7f1 4126 return hdmi_id == HDMI_IEEE_OUI;
7ebe1963
LD		 4127}
4128
50dd1bd1
TR		 4129static bool cea_db_is_hdmi_forum_vsdb(const u8 *db)
4130{
4131 unsigned int oui;
4132
4133 if (cea_db_tag(db) != VENDOR_BLOCK)
4134 return false;
4135
4136 if (cea_db_payload_len(db) < 7)
4137 return false;
4138
4139 oui = db[3] << 16 | db[2] << 8 | db[1];
4140
4141 return oui == HDMI_FORUM_IEEE_OUI;
4142}
4143
1581b2df
VS		 4144static bool cea_db_is_vcdb(const u8 *db)
4145{
4146 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4147 return false;
4148
4149 if (cea_db_payload_len(db) != 2)
4150 return false;
4151
4152 if (cea_db_extended_tag(db) != EXT_VIDEO_CAPABILITY_BLOCK)
4153 return false;
4154
4155 return true;
4156}
4157
832d4f2f
SS		 4158static bool cea_db_is_y420cmdb(const u8 *db)
4159{
4160 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4161 return false;
4162
4163 if (!cea_db_payload_len(db))
4164 return false;
4165
4166 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB)
4167 return false;
4168
4169 return true;
4170}
4171
4172static bool cea_db_is_y420vdb(const u8 *db)
4173{
4174 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4175 return false;
4176
4177 if (!cea_db_payload_len(db))
4178 return false;
4179
4180 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420)
4181 return false;
4182
4183 return true;
4184}
4185
9e50b9d5
VS		 4186#define for_each_cea_db(cea, i, start, end) \
4187 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
4188
832d4f2f
SS		 4189static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector,
4190 const u8 *db)
4191{
4192 struct drm_display_info *info = &connector->display_info;
4193 struct drm_hdmi_info *hdmi = &info->hdmi;
4194 u8 map_len = cea_db_payload_len(db) - 1;
4195 u8 count;
4196 u64 map = 0;
4197
4198 if (map_len == 0) {
4199 /* All CEA modes support ycbcr420 sampling also.*/
4200 hdmi->y420_cmdb_map = U64_MAX;
4201 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
4202 return;
4203 }
4204
4205 /*
4206 * This map indicates which of the existing CEA block modes
4207 * from VDB can support YCBCR420 output too. So if bit=0 is
4208 * set, first mode from VDB can support YCBCR420 output too.
4209 * We will parse and keep this map, before parsing VDB itself
4210 * to avoid going through the same block again and again.
4211 *
4212 * Spec is not clear about max possible size of this block.
4213 * Clamping max bitmap block size at 8 bytes. Every byte can
4214 * address 8 CEA modes, in this way this map can address
4215 * 8*8 = first 64 SVDs.
4216 */
4217 if (WARN_ON_ONCE(map_len > 8))
4218 map_len = 8;
4219
4220 for (count = 0; count < map_len; count++)
4221 map |= (u64)db[2 + count] << (8 * count);
4222
4223 if (map)
4224 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
4225
4226 hdmi->y420_cmdb_map = map;
4227}
4228
54ac76f8
CS		 4229static int
4230add_cea_modes(struct drm_connector *connector, struct edid *edid)
4231{
13ac3f55 4232 const u8 *cea = drm_find_cea_extension(edid);
fbf46025
TW		 4233 const u8 *db, *hdmi = NULL, *video = NULL;
4234 u8 dbl, hdmi_len, video_len = 0;
54ac76f8
CS		 4235 int modes = 0;
4236
9e50b9d5
VS		 4237 if (cea && cea_revision(cea) >= 3) {
4238 int i, start, end;
4239
4240 if (cea_db_offsets(cea, &start, &end))
4241 return 0;
4242
4243 for_each_cea_db(cea, i, start, end) {
4244 db = &cea[i];
4245 dbl = cea_db_payload_len(db);
4246
fbf46025
TW		 4247 if (cea_db_tag(db) == VIDEO_BLOCK) {
4248 video = db + 1;
4249 video_len = dbl;
4250 modes += do_cea_modes(connector, video, dbl);
832d4f2f 4251 } else if (cea_db_is_hdmi_vsdb(db)) {
c858cfca
DL		 4252 hdmi = db;
4253 hdmi_len = dbl;
832d4f2f
SS		 4254 } else if (cea_db_is_y420vdb(db)) {
4255 const u8 *vdb420 = &db[2];
4256
4257 /* Add 4:2:0(only) modes present in EDID */
4258 modes += do_y420vdb_modes(connector,
4259 vdb420,
4260 dbl - 1);
c858cfca 4261 }
54ac76f8
CS		 4262 }
4263 }
4264
c858cfca
DL		 4265 /*
4266 * We parse the HDMI VSDB after having added the cea modes as we will
4267 * be patching their flags when the sink supports stereo 3D.
4268 */
4269 if (hdmi)
fbf46025
TW		 4270 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
4271 video_len);
c858cfca 4272
54ac76f8
CS		 4273 return modes;
4274}
4275
fa3a7340
VS		 4276static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
4277{
4278 const struct drm_display_mode *cea_mode;
4279 int clock1, clock2, clock;
d9278b4c 4280 u8 vic;
fa3a7340
VS		 4281 const char *type;
4282
4c6bcf44
VS		 4283 /*
4284 * allow 5kHz clock difference either way to account for
4285 * the 10kHz clock resolution limit of detailed timings.
4286 */
d9278b4c
JN		 4287 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
4288 if (drm_valid_cea_vic(vic)) {
fa3a7340 4289 type = "CEA";
7befe621 4290 cea_mode = cea_mode_for_vic(vic);
fa3a7340
VS		 4291 clock1 = cea_mode->clock;
4292 clock2 = cea_mode_alternate_clock(cea_mode);
4293 } else {
d9278b4c
JN		 4294 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
4295 if (drm_valid_hdmi_vic(vic)) {
fa3a7340 4296 type = "HDMI";
d9278b4c 4297 cea_mode = &edid_4k_modes[vic];
fa3a7340
VS		 4298 clock1 = cea_mode->clock;
4299 clock2 = hdmi_mode_alternate_clock(cea_mode);
4300 } else {
4301 return;
4302 }
4303 }
4304
4305 /* pick whichever is closest */
4306 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
4307 clock = clock1;
4308 else
4309 clock = clock2;
4310
4311 if (mode->clock == clock)
4312 return;
4313
4314 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
d9278b4c 4315 type, vic, mode->clock, clock);
fa3a7340
VS		 4316 mode->clock = clock;
4317}
4318
e85959d6
US		 4319static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db)
4320{
4321 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4322 return false;
4323
4324 if (db[1] != HDR_STATIC_METADATA_BLOCK)
4325 return false;
4326
4327 if (cea_db_payload_len(db) < 3)
4328 return false;
4329
4330 return true;
4331}
4332
4333static uint8_t eotf_supported(const u8 *edid_ext)
4334{
4335 return edid_ext[2] &
4336 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
4337 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
b5e3eed1
VS		 4338 BIT(HDMI_EOTF_SMPTE_ST2084) |
4339 BIT(HDMI_EOTF_BT_2100_HLG));
e85959d6
US		 4340}
4341
4342static uint8_t hdr_metadata_type(const u8 *edid_ext)
4343{
4344 return edid_ext[3] &
4345 BIT(HDMI_STATIC_METADATA_TYPE1);
4346}
4347
4348static void
4349drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
4350{
4351 u16 len;
4352
4353 len = cea_db_payload_len(db);
4354
4355 connector->hdr_sink_metadata.hdmi_type1.eotf =
4356 eotf_supported(db);
4357 connector->hdr_sink_metadata.hdmi_type1.metadata_type =
4358 hdr_metadata_type(db);
4359
4360 if (len >= 4)
4361 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4];
4362 if (len >= 5)
4363 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5];
4364 if (len >= 6)
4365 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6];
4366}
4367
76adaa34 4368static void
23ebf8b9 4369drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
76adaa34 4370{
8504072a 4371 u8 len = cea_db_payload_len(db);
76adaa34 4372
f7da7785
JN		 4373 if (len >= 6 && (db[6] & (1 << 7)))
4374 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
8504072a
VS		 4375 if (len >= 8) {
4376 connector->latency_present[0] = db[8] >> 7;
4377 connector->latency_present[1] = (db[8] >> 6) & 1;
4378 }
4379 if (len >= 9)
4380 connector->video_latency[0] = db[9];
4381 if (len >= 10)
4382 connector->audio_latency[0] = db[10];
4383 if (len >= 11)
4384 connector->video_latency[1] = db[11];
4385 if (len >= 12)
4386 connector->audio_latency[1] = db[12];
76adaa34 4387
23ebf8b9
VS		 4388 DRM_DEBUG_KMS("HDMI: latency present %d %d, "
4389 "video latency %d %d, "
4390 "audio latency %d %d\n",
4391 connector->latency_present[0],
4392 connector->latency_present[1],
4393 connector->video_latency[0],
4394 connector->video_latency[1],
4395 connector->audio_latency[0],
4396 connector->audio_latency[1]);
76adaa34
WF		 4397}
4398
4399static void
4400monitor_name(struct detailed_timing *t, void *data)
4401{
a7a131ac
VS		 4402 if (!is_display_descriptor((const u8 *)t, EDID_DETAIL_MONITOR_NAME))
4403 return;
4404
4405 *(u8 **)data = t->data.other_data.data.str.str;
14f77fdd
VS		 4406}
4407
59f7c0fa
JB		 4408static int get_monitor_name(struct edid *edid, char name[13])
4409{
4410 char *edid_name = NULL;
4411 int mnl;
4412
4413 if (!edid || !name)
4414 return 0;
4415
4416 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name);
4417 for (mnl = 0; edid_name && mnl < 13; mnl++) {
4418 if (edid_name[mnl] == 0x0a)
4419 break;
4420
4421 name[mnl] = edid_name[mnl];
4422 }
4423
4424 return mnl;
4425}
4426
4427/**
4428 * drm_edid_get_monitor_name - fetch the monitor name from the edid
4429 * @edid: monitor EDID information
4430 * @name: pointer to a character array to hold the name of the monitor
4431 * @bufsize: The size of the name buffer (should be at least 14 chars.)
4432 *
4433 */
4434void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize)
4435{
4436 int name_length;
4437 char buf[13];
4d23f484 4438
59f7c0fa
JB		 4439 if (bufsize <= 0)
4440 return;
4441
4442 name_length = min(get_monitor_name(edid, buf), bufsize - 1);
4443 memcpy(name, buf, name_length);
4444 name[name_length] = '\0';
4445}
4446EXPORT_SYMBOL(drm_edid_get_monitor_name);
4447
42750d39
JN		 4448static void clear_eld(struct drm_connector *connector)
4449{
4450 memset(connector->eld, 0, sizeof(connector->eld));
4451
4452 connector->latency_present[0] = false;
4453 connector->latency_present[1] = false;
4454 connector->video_latency[0] = 0;
4455 connector->audio_latency[0] = 0;
4456 connector->video_latency[1] = 0;
4457 connector->audio_latency[1] = 0;
4458}
4459
79436a1c 4460/*
76adaa34
WF		 4461 * drm_edid_to_eld - build ELD from EDID
4462 * @connector: connector corresponding to the HDMI/DP sink
4463 * @edid: EDID to parse
4464 *
db6cf833 4465 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
1d1c3665 4466 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
76adaa34 4467 */
79436a1c 4468static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
76adaa34
WF		 4469{
4470 uint8_t *eld = connector->eld;
43d16d84
JN		 4471 const u8 *cea;
4472 const u8 *db;
7c018782 4473 int total_sad_count = 0;
76adaa34
WF		 4474 int mnl;
4475 int dbl;
4476
42750d39 4477 clear_eld(connector);
85c91580 4478
e9bd0b84
JN		 4479 if (!edid)
4480 return;
4481
76adaa34
WF		 4482 cea = drm_find_cea_extension(edid);
4483 if (!cea) {
4484 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
4485 return;
4486 }
4487
f7da7785
JN		 4488 mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
4489 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]);
59f7c0fa 4490
f7da7785
JN		 4491 eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT;
4492 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
76adaa34 4493
f7da7785 4494 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
76adaa34 4495
f7da7785
JN		 4496 eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0];
4497 eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1];
4498 eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0];
4499 eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1];
76adaa34 4500
9e50b9d5
VS		 4501 if (cea_revision(cea) >= 3) {
4502 int i, start, end;
deec222e 4503 int sad_count;
9e50b9d5
VS		 4504
4505 if (cea_db_offsets(cea, &start, &end)) {
4506 start = 0;
4507 end = 0;
4508 }
4509
4510 for_each_cea_db(cea, i, start, end) {
4511 db = &cea[i];
4512 dbl = cea_db_payload_len(db);
4513
4514 switch (cea_db_tag(db)) {
a0ab734d
CS		 4515 case AUDIO_BLOCK:
4516 /* Audio Data Block, contains SADs */
7c018782
VS		 4517 sad_count = min(dbl / 3, 15 - total_sad_count);
4518 if (sad_count >= 1)
f7da7785 4519 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
7c018782
VS		 4520 &db[1], sad_count * 3);
4521 total_sad_count += sad_count;
a0ab734d
CS		 4522 break;
4523 case SPEAKER_BLOCK:
9e50b9d5
VS		 4524 /* Speaker Allocation Data Block */
4525 if (dbl >= 1)
f7da7785 4526 eld[DRM_ELD_SPEAKER] = db[1];
a0ab734d
CS		 4527 break;
4528 case VENDOR_BLOCK:
4529 /* HDMI Vendor-Specific Data Block */
14f77fdd 4530 if (cea_db_is_hdmi_vsdb(db))
23ebf8b9 4531 drm_parse_hdmi_vsdb_audio(connector, db);
a0ab734d
CS		 4532 break;
4533 default:
4534 break;
4535 }
76adaa34 4536 }
9e50b9d5 4537 }
f7da7785 4538 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
76adaa34 4539
1d1c3665
JN		 4540 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
4541 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4542 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
4543 else
4544 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
76adaa34 4545
938fd8aa
JN		 4546 eld[DRM_ELD_BASELINE_ELD_LEN] =
4547 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
4548
4549 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
7c018782 4550 drm_eld_size(eld), total_sad_count);
76adaa34 4551}
76adaa34 4552
fe214163
RM		 4553/**
4554 * drm_edid_to_sad - extracts SADs from EDID
4555 * @edid: EDID to parse
4556 * @sads: pointer that will be set to the extracted SADs
4557 *
4558 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
fe214163 4559 *
db6cf833
TR		 4560 * Note: The returned pointer needs to be freed using kfree().
4561 *
4562 * Return: The number of found SADs or negative number on error.
fe214163
RM		 4563 */
4564int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
4565{
4566 int count = 0;
4567 int i, start, end, dbl;
43d16d84 4568 const u8 *cea;
fe214163
RM		 4569
4570 cea = drm_find_cea_extension(edid);
4571 if (!cea) {
4572 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
42908007 4573 return 0;
fe214163
RM		 4574 }
4575
4576 if (cea_revision(cea) < 3) {
4577 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
42908007 4578 return 0;
fe214163
RM		 4579 }
4580
4581 if (cea_db_offsets(cea, &start, &end)) {
4582 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4583 return -EPROTO;
4584 }
4585
4586 for_each_cea_db(cea, i, start, end) {
43d16d84 4587 const u8 *db = &cea[i];
fe214163
RM		 4588
4589 if (cea_db_tag(db) == AUDIO_BLOCK) {
4590 int j;
948de842 4591
fe214163
RM		 4592 dbl = cea_db_payload_len(db);
4593
4594 count = dbl / 3; /* SAD is 3B */
4595 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
4596 if (!*sads)
4597 return -ENOMEM;
4598 for (j = 0; j < count; j++) {
43d16d84 4599 const u8 *sad = &db[1 + j * 3];
fe214163
RM		 4600
4601 (*sads)[j].format = (sad[0] & 0x78) >> 3;
4602 (*sads)[j].channels = sad[0] & 0x7;
4603 (*sads)[j].freq = sad[1] & 0x7F;
4604 (*sads)[j].byte2 = sad[2];
4605 }
4606 break;
4607 }
4608 }
4609
4610 return count;
4611}
4612EXPORT_SYMBOL(drm_edid_to_sad);
4613
d105f476
AD		 4614/**
4615 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
4616 * @edid: EDID to parse
4617 * @sadb: pointer to the speaker block
4618 *
4619 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
d105f476 4620 *
db6cf833
TR		 4621 * Note: The returned pointer needs to be freed using kfree().
4622 *
4623 * Return: The number of found Speaker Allocation Blocks or negative number on
4624 * error.
d105f476
AD		 4625 */
4626int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
4627{
4628 int count = 0;
4629 int i, start, end, dbl;
4630 const u8 *cea;
4631
4632 cea = drm_find_cea_extension(edid);
4633 if (!cea) {
4634 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
42908007 4635 return 0;
d105f476
AD		 4636 }
4637
4638 if (cea_revision(cea) < 3) {
4639 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
42908007 4640 return 0;
d105f476
AD		 4641 }
4642
4643 if (cea_db_offsets(cea, &start, &end)) {
4644 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4645 return -EPROTO;
4646 }
4647
4648 for_each_cea_db(cea, i, start, end) {
4649 const u8 *db = &cea[i];
4650
4651 if (cea_db_tag(db) == SPEAKER_BLOCK) {
4652 dbl = cea_db_payload_len(db);
4653
4654 /* Speaker Allocation Data Block */
4655 if (dbl == 3) {
89086bca 4656 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
618e3776
AD		 4657 if (!*sadb)
4658 return -ENOMEM;
d105f476
AD		 4659 count = dbl;
4660 break;
4661 }
4662 }
4663 }
4664
4665 return count;
4666}
4667EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
4668
76adaa34 4669/**
db6cf833 4670 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
76adaa34
WF		 4671 * @connector: connector associated with the HDMI/DP sink
4672 * @mode: the display mode
db6cf833
TR		 4673 *
4674 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
4675 * the sink doesn't support audio or video.
76adaa34
WF		 4676 */
4677int drm_av_sync_delay(struct drm_connector *connector,
3a818d35 4678 const struct drm_display_mode *mode)
76adaa34
WF		 4679{
4680 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
4681 int a, v;
4682
4683 if (!connector->latency_present[0])
4684 return 0;
4685 if (!connector->latency_present[1])
4686 i = 0;
4687
4688 a = connector->audio_latency[i];
4689 v = connector->video_latency[i];
4690
4691 /*
4692 * HDMI/DP sink doesn't support audio or video?
4693 */
4694 if (a == 255 || v == 255)
4695 return 0;
4696
4697 /*
4698 * Convert raw EDID values to millisecond.
4699 * Treat unknown latency as 0ms.
4700 */
4701 if (a)
4702 a = min(2 * (a - 1), 500);
4703 if (v)
4704 v = min(2 * (v - 1), 500);
4705
4706 return max(v - a, 0);
4707}
4708EXPORT_SYMBOL(drm_av_sync_delay);
4709
8fe9790d 4710/**
db6cf833 4711 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
8fe9790d
ZW		 4712 * @edid: monitor EDID information
4713 *
4714 * Parse the CEA extension according to CEA-861-B.
db6cf833 4715 *
a92d083d
LP		 4716 * Drivers that have added the modes parsed from EDID to drm_display_info
4717 * should use &drm_display_info.is_hdmi instead of calling this function.
4718 *
db6cf833 4719 * Return: True if the monitor is HDMI, false if not or unknown.
8fe9790d
ZW		 4720 */
4721bool drm_detect_hdmi_monitor(struct edid *edid)
4722{
43d16d84 4723 const u8 *edid_ext;
14f77fdd 4724 int i;
8fe9790d 4725 int start_offset, end_offset;
8fe9790d
ZW		 4726
4727 edid_ext = drm_find_cea_extension(edid);
4728 if (!edid_ext)
14f77fdd 4729 return false;
f23c20c8 4730
9e50b9d5 4731 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
14f77fdd 4732 return false;
f23c20c8
ML		 4733
4734 /*
4735 * Because HDMI identifier is in Vendor Specific Block,
4736 * search it from all data blocks of CEA extension.
4737 */
9e50b9d5 4738 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
14f77fdd
VS		 4739 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
4740 return true;
f23c20c8
ML		 4741 }
4742
14f77fdd 4743 return false;
f23c20c8
ML		 4744}
4745EXPORT_SYMBOL(drm_detect_hdmi_monitor);
4746
8fe9790d
ZW		 4747/**
4748 * drm_detect_monitor_audio - check monitor audio capability
fc66811c 4749 * @edid: EDID block to scan
8fe9790d
ZW		 4750 *
4751 * Monitor should have CEA extension block.
4752 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
4753 * audio' only. If there is any audio extension block and supported
4754 * audio format, assume at least 'basic audio' support, even if 'basic
4755 * audio' is not defined in EDID.
4756 *
db6cf833 4757 * Return: True if the monitor supports audio, false otherwise.
8fe9790d
ZW		 4758 */
4759bool drm_detect_monitor_audio(struct edid *edid)
4760{
43d16d84 4761 const u8 *edid_ext;
8fe9790d
ZW		 4762 int i, j;
4763 bool has_audio = false;
4764 int start_offset, end_offset;
4765
4766 edid_ext = drm_find_cea_extension(edid);
4767 if (!edid_ext)
4768 goto end;
4769
4770 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
4771
4772 if (has_audio) {
4773 DRM_DEBUG_KMS("Monitor has basic audio support\n");
4774 goto end;
4775 }
4776
9e50b9d5
VS		 4777 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4778 goto end;
8fe9790d 4779
9e50b9d5
VS		 4780 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4781 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
8fe9790d 4782 has_audio = true;
9e50b9d5 4783 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
8fe9790d
ZW		 4784 DRM_DEBUG_KMS("CEA audio format %d\n",
4785 (edid_ext[i + j] >> 3) & 0xf);
4786 goto end;
4787 }
4788 }
4789end:
4790 return has_audio;
4791}
4792EXPORT_SYMBOL(drm_detect_monitor_audio);
4793
b1edd6a6 4794
c8127cf0
VS		 4795/**
4796 * drm_default_rgb_quant_range - default RGB quantization range
4797 * @mode: display mode
4798 *
4799 * Determine the default RGB quantization range for the mode,
4800 * as specified in CEA-861.
4801 *
4802 * Return: The default RGB quantization range for the mode
4803 */
4804enum hdmi_quantization_range
4805drm_default_rgb_quant_range(const struct drm_display_mode *mode)
4806{
4807 /* All CEA modes other than VIC 1 use limited quantization range. */
4808 return drm_match_cea_mode(mode) > 1 ?
4809 HDMI_QUANTIZATION_RANGE_LIMITED :
4810 HDMI_QUANTIZATION_RANGE_FULL;
4811}
4812EXPORT_SYMBOL(drm_default_rgb_quant_range);
4813
1581b2df
VS		 4814static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
4815{
4816 struct drm_display_info *info = &connector->display_info;
4817
4818 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]);
4819
4820 if (db[2] & EDID_CEA_VCDB_QS)
4821 info->rgb_quant_range_selectable = true;
4822}
4823
4499d488
SS		 4824static
4825void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane)
4826{
4827 switch (max_frl_rate) {
4828 case 1:
4829 *max_lanes = 3;
4830 *max_rate_per_lane = 3;
4831 break;
4832 case 2:
4833 *max_lanes = 3;
4834 *max_rate_per_lane = 6;
4835 break;
4836 case 3:
4837 *max_lanes = 4;
4838 *max_rate_per_lane = 6;
4839 break;
4840 case 4:
4841 *max_lanes = 4;
4842 *max_rate_per_lane = 8;
4843 break;
4844 case 5:
4845 *max_lanes = 4;
4846 *max_rate_per_lane = 10;
4847 break;
4848 case 6:
4849 *max_lanes = 4;
4850 *max_rate_per_lane = 12;
4851 break;
4852 case 0:
4853 default:
4854 *max_lanes = 0;
4855 *max_rate_per_lane = 0;
4856 }
4857}
4858
e6a9a2c3
SS		 4859static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
4860 const u8 *db)
4861{
4862 u8 dc_mask;
4863 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4864
4865 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
9068e02f 4866 hdmi->y420_dc_modes = dc_mask;
e6a9a2c3
SS		 4867}
4868
afa1c763
SS		 4869static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector,
4870 const u8 *hf_vsdb)
4871{
62c58af3
SS		 4872 struct drm_display_info *display = &connector->display_info;
4873 struct drm_hdmi_info *hdmi = &display->hdmi;
afa1c763 4874
f1781e9b
VS		 4875 display->has_hdmi_infoframe = true;
4876
afa1c763
SS		 4877 if (hf_vsdb[6] & 0x80) {
4878 hdmi->scdc.supported = true;
4879 if (hf_vsdb[6] & 0x40)
4880 hdmi->scdc.read_request = true;
4881 }
62c58af3
SS		 4882
4883 /*
4884 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
4885 * And as per the spec, three factors confirm this:
4886 * * Availability of a HF-VSDB block in EDID (check)
4887 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
4888 * * SCDC support available (let's check)
4889 * Lets check it out.
4890 */
4891
4892 if (hf_vsdb[5]) {
4893 /* max clock is 5000 KHz times block value */
4894 u32 max_tmds_clock = hf_vsdb[5] * 5000;
4895 struct drm_scdc *scdc = &hdmi->scdc;
4896
4897 if (max_tmds_clock > 340000) {
4898 display->max_tmds_clock = max_tmds_clock;
4899 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
4900 display->max_tmds_clock);
4901 }
4902
4903 if (scdc->supported) {
4904 scdc->scrambling.supported = true;
4905
dbe2d2bf 4906 /* Few sinks support scrambling for clocks < 340M */
62c58af3
SS		 4907 if ((hf_vsdb[6] & 0x8))
4908 scdc->scrambling.low_rates = true;
4909 }
4910 }
e6a9a2c3 4911
4499d488
SS		 4912 if (hf_vsdb[7]) {
4913 u8 max_frl_rate;
76ee7b90
AN		 4914 u8 dsc_max_frl_rate;
4915 u8 dsc_max_slices;
4916 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap;
4499d488
SS		 4917
4918 DRM_DEBUG_KMS("hdmi_21 sink detected. parsing edid\n");
4919 max_frl_rate = (hf_vsdb[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4;
4920 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes,
4921 &hdmi->max_frl_rate_per_lane);
76ee7b90
AN		 4922 hdmi_dsc->v_1p2 = hf_vsdb[11] & DRM_EDID_DSC_1P2;
4923
4924 if (hdmi_dsc->v_1p2) {
4925 hdmi_dsc->native_420 = hf_vsdb[11] & DRM_EDID_DSC_NATIVE_420;
4926 hdmi_dsc->all_bpp = hf_vsdb[11] & DRM_EDID_DSC_ALL_BPP;
4927
4928 if (hf_vsdb[11] & DRM_EDID_DSC_16BPC)
4929 hdmi_dsc->bpc_supported = 16;
4930 else if (hf_vsdb[11] & DRM_EDID_DSC_12BPC)
4931 hdmi_dsc->bpc_supported = 12;
4932 else if (hf_vsdb[11] & DRM_EDID_DSC_10BPC)
4933 hdmi_dsc->bpc_supported = 10;
4934 else
4935 hdmi_dsc->bpc_supported = 0;
4936
4937 dsc_max_frl_rate = (hf_vsdb[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4;
4938 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes,
4939 &hdmi_dsc->max_frl_rate_per_lane);
4940 hdmi_dsc->total_chunk_kbytes = hf_vsdb[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES;
4941
4942 dsc_max_slices = hf_vsdb[12] & DRM_EDID_DSC_MAX_SLICES;
4943 switch (dsc_max_slices) {
4944 case 1:
4945 hdmi_dsc->max_slices = 1;
4946 hdmi_dsc->clk_per_slice = 340;
4947 break;
4948 case 2:
4949 hdmi_dsc->max_slices = 2;
4950 hdmi_dsc->clk_per_slice = 340;
4951 break;
4952 case 3:
4953 hdmi_dsc->max_slices = 4;
4954 hdmi_dsc->clk_per_slice = 340;
4955 break;
4956 case 4:
4957 hdmi_dsc->max_slices = 8;
4958 hdmi_dsc->clk_per_slice = 340;
4959 break;
4960 case 5:
4961 hdmi_dsc->max_slices = 8;
4962 hdmi_dsc->clk_per_slice = 400;
4963 break;
4964 case 6:
4965 hdmi_dsc->max_slices = 12;
4966 hdmi_dsc->clk_per_slice = 400;
4967 break;
4968 case 7:
4969 hdmi_dsc->max_slices = 16;
4970 hdmi_dsc->clk_per_slice = 400;
4971 break;
4972 case 0:
4973 default:
4974 hdmi_dsc->max_slices = 0;
4975 hdmi_dsc->clk_per_slice = 0;
4976 }
4977 }
4499d488
SS		 4978 }
4979
e6a9a2c3 4980 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb);
afa1c763
SS		 4981}
4982
1cea146a
VS		 4983static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
4984 const u8 *hdmi)
d0c94692 4985{
1826750f 4986 struct drm_display_info *info = &connector->display_info;
d0c94692
MK		 4987 unsigned int dc_bpc = 0;
4988
1cea146a
VS		 4989 /* HDMI supports at least 8 bpc */
4990 info->bpc = 8;
d0c94692 4991
1cea146a
VS		 4992 if (cea_db_payload_len(hdmi) < 6)
4993 return;
4994
4995 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
4996 dc_bpc = 10;
4997 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
4998 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
4999 connector->name);
5000 }
5001
5002 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
5003 dc_bpc = 12;
5004 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
5005 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
5006 connector->name);
5007 }
5008
5009 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
5010 dc_bpc = 16;
5011 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
5012 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
5013 connector->name);
5014 }
5015
5016 if (dc_bpc == 0) {
5017 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
5018 connector->name);
5019 return;
5020 }
5021
5022 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
5023 connector->name, dc_bpc);
5024 info->bpc = dc_bpc;
d0c94692
MK		 5025
5026 /*
1cea146a
VS		 5027 * Deep color support mandates RGB444 support for all video
5028 * modes and forbids YCRCB422 support for all video modes per
5029 * HDMI 1.3 spec.
d0c94692 5030 */
1cea146a 5031 info->color_formats = DRM_COLOR_FORMAT_RGB444;
d0c94692 5032
1cea146a
VS		 5033 /* YCRCB444 is optional according to spec. */
5034 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
5035 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
5036 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
5037 connector->name);
5038 }
d0c94692 5039
1cea146a
VS		 5040 /*
5041 * Spec says that if any deep color mode is supported at all,
5042 * then deep color 36 bit must be supported.
5043 */
5044 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
5045 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
5046 connector->name);
5047 }
5048}
d0c94692 5049
23ebf8b9
VS		 5050static void
5051drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
5052{
5053 struct drm_display_info *info = &connector->display_info;
5054 u8 len = cea_db_payload_len(db);
5055
a92d083d
LP		 5056 info->is_hdmi = true;
5057
23ebf8b9
VS		 5058 if (len >= 6)
5059 info->dvi_dual = db[6] & 1;
5060 if (len >= 7)
5061 info->max_tmds_clock = db[7] * 5000;
5062
5063 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
5064 "max TMDS clock %d kHz\n",
5065 info->dvi_dual,
5066 info->max_tmds_clock);
5067
5068 drm_parse_hdmi_deep_color_info(connector, db);
5069}
5070
1cea146a 5071static void drm_parse_cea_ext(struct drm_connector *connector,
170178fe 5072 const struct edid *edid)
1cea146a
VS		 5073{
5074 struct drm_display_info *info = &connector->display_info;
5075 const u8 *edid_ext;
5076 int i, start, end;
d0c94692 5077
1cea146a
VS		 5078 edid_ext = drm_find_cea_extension(edid);
5079 if (!edid_ext)
5080 return;
d0c94692 5081
1cea146a 5082 info->cea_rev = edid_ext[1];
d0c94692 5083
1cea146a
VS		 5084 /* The existence of a CEA block should imply RGB support */
5085 info->color_formats = DRM_COLOR_FORMAT_RGB444;
5086 if (edid_ext[3] & EDID_CEA_YCRCB444)
5087 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
5088 if (edid_ext[3] & EDID_CEA_YCRCB422)
5089 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
5090
5091 if (cea_db_offsets(edid_ext, &start, &end))
5092 return;
5093
5094 for_each_cea_db(edid_ext, i, start, end) {
5095 const u8 *db = &edid_ext[i];
5096
23ebf8b9
VS		 5097 if (cea_db_is_hdmi_vsdb(db))
5098 drm_parse_hdmi_vsdb_video(connector, db);
afa1c763
SS		 5099 if (cea_db_is_hdmi_forum_vsdb(db))
5100 drm_parse_hdmi_forum_vsdb(connector, db);
832d4f2f
SS		 5101 if (cea_db_is_y420cmdb(db))
5102 drm_parse_y420cmdb_bitmap(connector, db);
1581b2df
VS		 5103 if (cea_db_is_vcdb(db))
5104 drm_parse_vcdb(connector, db);
e85959d6
US		 5105 if (cea_db_is_hdmi_hdr_metadata_block(db))
5106 drm_parse_hdr_metadata_block(connector, db);
1cea146a 5107 }
d0c94692
MK		 5108}
5109
a1d11d1e
MN		 5110static
5111void get_monitor_range(struct detailed_timing *timing,
5112 void *info_monitor_range)
5113{
5114 struct drm_monitor_range_info *monitor_range = info_monitor_range;
5115 const struct detailed_non_pixel *data = &timing->data.other_data;
5116 const struct detailed_data_monitor_range *range = &data->data.range;
5117
5118 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE))
5119 return;
5120
5121 /*
5122 * Check for flag range limits only. If flag == 1 then
5123 * no additional timing information provided.
5124 * Default GTF, GTF Secondary curve and CVT are not
5125 * supported
5126 */
5127 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG)
5128 return;
5129
5130 monitor_range->min_vfreq = range->min_vfreq;
5131 monitor_range->max_vfreq = range->max_vfreq;
5132}
5133
5134static
5135void drm_get_monitor_range(struct drm_connector *connector,
5136 const struct edid *edid)
5137{
5138 struct drm_display_info *info = &connector->display_info;
5139
5140 if (!version_greater(edid, 1, 1))
5141 return;
5142
5143 drm_for_each_detailed_block((u8 *)edid, get_monitor_range,
5144 &info->monitor_range);
5145
5146 DRM_DEBUG_KMS("Supported Monitor Refresh rate range is %d Hz - %d Hz\n",
5147 info->monitor_range.min_vfreq,
5148 info->monitor_range.max_vfreq);
5149}
5150
170178fe
KP		 5151/* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
5152 * all of the values which would have been set from EDID
5153 */
5154void
5155drm_reset_display_info(struct drm_connector *connector)
5156{
5157 struct drm_display_info *info = &connector->display_info;
5158
5159 info->width_mm = 0;
5160 info->height_mm = 0;
5161
5162 info->bpc = 0;
5163 info->color_formats = 0;
5164 info->cea_rev = 0;
5165 info->max_tmds_clock = 0;
5166 info->dvi_dual = false;
a92d083d 5167 info->is_hdmi = false;
170178fe 5168 info->has_hdmi_infoframe = false;
1581b2df 5169 info->rgb_quant_range_selectable = false;
1f6b8eef 5170 memset(&info->hdmi, 0, sizeof(info->hdmi));
170178fe
KP		 5171
5172 info->non_desktop = 0;
a1d11d1e 5173 memset(&info->monitor_range, 0, sizeof(info->monitor_range));
170178fe 5174}
170178fe
KP		 5175
5176u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid)
3b11228b 5177{
1826750f 5178 struct drm_display_info *info = &connector->display_info;
ebec9a7b 5179
170178fe
KP		 5180 u32 quirks = edid_get_quirks(edid);
5181
1f6b8eef
VS		 5182 drm_reset_display_info(connector);
5183
3b11228b
JB		 5184 info->width_mm = edid->width_cm * 10;
5185 info->height_mm = edid->height_cm * 10;
5186
66660d4c
DA		 5187 info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP);
5188
a1d11d1e
MN		 5189 drm_get_monitor_range(connector, edid);
5190
170178fe
KP		 5191 DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop);
5192
a988bc72 5193 if (edid->revision < 3)
170178fe 5194 return quirks;
3b11228b
JB		 5195
5196 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
170178fe 5197 return quirks;
3b11228b 5198
1cea146a 5199 drm_parse_cea_ext(connector, edid);
d0c94692 5200
210a021d
MK		 5201 /*
5202 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
5203 *
5204 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
5205 * tells us to assume 8 bpc color depth if the EDID doesn't have
5206 * extensions which tell otherwise.
5207 */
3bde449f
VS		 5208 if (info->bpc == 0 && edid->revision == 3 &&
5209 edid->input & DRM_EDID_DIGITAL_DFP_1_X) {
210a021d
MK		 5210 info->bpc = 8;
5211 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
5212 connector->name, info->bpc);
5213 }
5214
a988bc72
LPC		 5215 /* Only defined for 1.4 with digital displays */
5216 if (edid->revision < 4)
170178fe 5217 return quirks;
a988bc72 5218
3b11228b
JB		 5219 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
5220 case DRM_EDID_DIGITAL_DEPTH_6:
5221 info->bpc = 6;
5222 break;
5223 case DRM_EDID_DIGITAL_DEPTH_8:
5224 info->bpc = 8;
5225 break;
5226 case DRM_EDID_DIGITAL_DEPTH_10:
5227 info->bpc = 10;
5228 break;
5229 case DRM_EDID_DIGITAL_DEPTH_12:
5230 info->bpc = 12;
5231 break;
5232 case DRM_EDID_DIGITAL_DEPTH_14:
5233 info->bpc = 14;
5234 break;
5235 case DRM_EDID_DIGITAL_DEPTH_16:
5236 info->bpc = 16;
5237 break;
5238 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
5239 default:
5240 info->bpc = 0;
5241 break;
5242 }
da05a5a7 5243
d0c94692 5244 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
25933820 5245 connector->name, info->bpc);
d0c94692 5246
a988bc72 5247 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
ee58808d
LPC		 5248 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
5249 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
5250 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
5251 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
170178fe 5252 return quirks;
3b11228b
JB		 5253}
5254
a39ed680
DA		 5255static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
5256 struct displayid_detailed_timings_1 *timings)
5257{
5258 struct drm_display_mode *mode;
5259 unsigned pixel_clock = (timings->pixel_clock[0] |
5260 (timings->pixel_clock[1] << 8) |
6292b8ef 5261 (timings->pixel_clock[2] << 16)) + 1;
a39ed680
DA		 5262 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
5263 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
5264 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
5265 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
5266 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
5267 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
5268 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
5269 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
5270 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
5271 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
948de842 5272
a39ed680
DA		 5273 mode = drm_mode_create(dev);
5274 if (!mode)
5275 return NULL;
5276
5277 mode->clock = pixel_clock * 10;
5278 mode->hdisplay = hactive;
5279 mode->hsync_start = mode->hdisplay + hsync;
5280 mode->hsync_end = mode->hsync_start + hsync_width;
5281 mode->htotal = mode->hdisplay + hblank;
5282
5283 mode->vdisplay = vactive;
5284 mode->vsync_start = mode->vdisplay + vsync;
5285 mode->vsync_end = mode->vsync_start + vsync_width;
5286 mode->vtotal = mode->vdisplay + vblank;
5287
5288 mode->flags = 0;
5289 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
5290 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
5291 mode->type = DRM_MODE_TYPE_DRIVER;
5292
5293 if (timings->flags & 0x80)
5294 mode->type |= DRM_MODE_TYPE_PREFERRED;
a39ed680
DA		 5295 drm_mode_set_name(mode);
5296
5297 return mode;
5298}
5299
5300static int add_displayid_detailed_1_modes(struct drm_connector *connector,
43d16d84 5301 const struct displayid_block *block)
a39ed680
DA		 5302{
5303 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
5304 int i;
5305 int num_timings;
5306 struct drm_display_mode *newmode;
5307 int num_modes = 0;
5308 /* blocks must be multiple of 20 bytes length */
5309 if (block->num_bytes % 20)
5310 return 0;
5311
5312 num_timings = block->num_bytes / 20;
5313 for (i = 0; i < num_timings; i++) {
5314 struct displayid_detailed_timings_1 *timings = &det->timings[i];
5315
5316 newmode = drm_mode_displayid_detailed(connector->dev, timings);
5317 if (!newmode)
5318 continue;
5319
5320 drm_mode_probed_add(connector, newmode);
5321 num_modes++;
5322 }
5323 return num_modes;
5324}
5325
5326static int add_displayid_detailed_modes(struct drm_connector *connector,
5327 struct edid *edid)
5328{
43d16d84 5329 const struct displayid_block *block;
5ef88dc5 5330 struct displayid_iter iter;
a39ed680
DA		 5331 int num_modes = 0;
5332
5ef88dc5
JN		 5333 displayid_iter_edid_begin(edid, &iter);
5334 displayid_iter_for_each(block, &iter) {
5335 if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING)
5336 num_modes += add_displayid_detailed_1_modes(connector, block);
a39ed680 5337 }
5ef88dc5 5338 displayid_iter_end(&iter);
7f261afd 5339
a39ed680
DA		 5340 return num_modes;
5341}
5342
f453ba04
DA		 5343/**
5344 * drm_add_edid_modes - add modes from EDID data, if available
5345 * @connector: connector we're probing
db6cf833 5346 * @edid: EDID data
f453ba04 5347 *
b3c6c8bf 5348 * Add the specified modes to the connector's mode list. Also fills out the
c945b8c1
JN		 5349 * &drm_display_info structure and ELD in @connector with any information which
5350 * can be derived from the edid.
f453ba04 5351 *
db6cf833 5352 * Return: The number of modes added or 0 if we couldn't find any.
f453ba04
DA		 5353 */
5354int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
5355{
5356 int num_modes = 0;
5357 u32 quirks;
5358
5359 if (edid == NULL) {
c945b8c1 5360 clear_eld(connector);
f453ba04
DA		 5361 return 0;
5362 }
3c537889 5363 if (!drm_edid_is_valid(edid)) {
c945b8c1 5364 clear_eld(connector);
6d45fff5 5365 drm_warn(connector->dev, "%s: EDID invalid.\n",
25933820 5366 connector->name);
f453ba04
DA		 5367 return 0;
5368 }
5369
c945b8c1
JN		 5370 drm_edid_to_eld(connector, edid);
5371
0f0f8708
SS		 5372 /*
5373 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
5374 * To avoid multiple parsing of same block, lets parse that map
5375 * from sink info, before parsing CEA modes.
5376 */
170178fe 5377 quirks = drm_add_display_info(connector, edid);
0f0f8708 5378
c867df70
AJ		 5379 /*
5380 * EDID spec says modes should be preferred in this order:
5381 * - preferred detailed mode
5382 * - other detailed modes from base block
5383 * - detailed modes from extension blocks
5384 * - CVT 3-byte code modes
5385 * - standard timing codes
5386 * - established timing codes
5387 * - modes inferred from GTF or CVT range information
5388 *
13931579 5389 * We get this pretty much right.
c867df70
AJ		 5390 *
5391 * XXX order for additional mode types in extension blocks?
5392 */
13931579
AJ		 5393 num_modes += add_detailed_modes(connector, edid, quirks);
5394 num_modes += add_cvt_modes(connector, edid);
c867df70
AJ		 5395 num_modes += add_standard_modes(connector, edid);
5396 num_modes += add_established_modes(connector, edid);
54ac76f8 5397 num_modes += add_cea_modes(connector, edid);
e6e79209 5398 num_modes += add_alternate_cea_modes(connector, edid);
a39ed680 5399 num_modes += add_displayid_detailed_modes(connector, edid);
4d53dc0c
VS		 5400 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
5401 num_modes += add_inferred_modes(connector, edid);
f453ba04
DA		 5402
5403 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
5404 edid_fixup_preferred(connector, quirks);
5405
e10aec65
MK		 5406 if (quirks & EDID_QUIRK_FORCE_6BPC)
5407 connector->display_info.bpc = 6;
5408
49d45a31
RM		 5409 if (quirks & EDID_QUIRK_FORCE_8BPC)
5410 connector->display_info.bpc = 8;
5411
e345da82
MK		 5412 if (quirks & EDID_QUIRK_FORCE_10BPC)
5413 connector->display_info.bpc = 10;
5414
bc5b9641
MK		 5415 if (quirks & EDID_QUIRK_FORCE_12BPC)
5416 connector->display_info.bpc = 12;
5417
f453ba04
DA		 5418 return num_modes;
5419}
5420EXPORT_SYMBOL(drm_add_edid_modes);
f0fda0a4
ZY		 5421
5422/**
5423 * drm_add_modes_noedid - add modes for the connectors without EDID
5424 * @connector: connector we're probing
5425 * @hdisplay: the horizontal display limit
5426 * @vdisplay: the vertical display limit
5427 *
5428 * Add the specified modes to the connector's mode list. Only when the
5429 * hdisplay/vdisplay is not beyond the given limit, it will be added.
5430 *
db6cf833 5431 * Return: The number of modes added or 0 if we couldn't find any.
f0fda0a4
ZY		 5432 */
5433int drm_add_modes_noedid(struct drm_connector *connector,
5434 int hdisplay, int vdisplay)
5435{
5436 int i, count, num_modes = 0;
b1f559ec 5437 struct drm_display_mode *mode;
f0fda0a4
ZY		 5438 struct drm_device *dev = connector->dev;
5439
fbb40b28 5440 count = ARRAY_SIZE(drm_dmt_modes);
f0fda0a4
ZY		 5441 if (hdisplay < 0)
5442 hdisplay = 0;
5443 if (vdisplay < 0)
5444 vdisplay = 0;
5445
5446 for (i = 0; i < count; i++) {
b1f559ec 5447 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
948de842 5448
f0fda0a4
ZY		 5449 if (hdisplay && vdisplay) {
5450 /*
5451 * Only when two are valid, they will be used to check
5452 * whether the mode should be added to the mode list of
5453 * the connector.
5454 */
5455 if (ptr->hdisplay > hdisplay ||
5456 ptr->vdisplay > vdisplay)
5457 continue;
5458 }
f985dedb
AJ		 5459 if (drm_mode_vrefresh(ptr) > 61)
5460 continue;
f0fda0a4
ZY		 5461 mode = drm_mode_duplicate(dev, ptr);
5462 if (mode) {
5463 drm_mode_probed_add(connector, mode);
5464 num_modes++;
5465 }
5466 }
5467 return num_modes;
5468}
5469EXPORT_SYMBOL(drm_add_modes_noedid);
10a85120 5470
db6cf833
TR		 5471/**
5472 * drm_set_preferred_mode - Sets the preferred mode of a connector
5473 * @connector: connector whose mode list should be processed
5474 * @hpref: horizontal resolution of preferred mode
5475 * @vpref: vertical resolution of preferred mode
5476 *
5477 * Marks a mode as preferred if it matches the resolution specified by @hpref
5478 * and @vpref.
5479 */
3cf70daf
GH		 5480void drm_set_preferred_mode(struct drm_connector *connector,
5481 int hpref, int vpref)
5482{
5483 struct drm_display_mode *mode;
5484
5485 list_for_each_entry(mode, &connector->probed_modes, head) {
db6cf833 5486 if (mode->hdisplay == hpref &&
9d3de138 5487 mode->vdisplay == vpref)
3cf70daf
GH		 5488 mode->type |= DRM_MODE_TYPE_PREFERRED;
5489 }
5490}
5491EXPORT_SYMBOL(drm_set_preferred_mode);
5492
192a3aa0 5493static bool is_hdmi2_sink(const struct drm_connector *connector)
13d0add3
VS		 5494{
5495 /*
5496 * FIXME: sil-sii8620 doesn't have a connector around when
5497 * we need one, so we have to be prepared for a NULL connector.
5498 */
5499 if (!connector)
5500 return true;
5501
5502 return connector->display_info.hdmi.scdc.supported ||
5503 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420;
5504}
5505
2cdbfd66
US		 5506static inline bool is_eotf_supported(u8 output_eotf, u8 sink_eotf)
5507{
5508 return sink_eotf & BIT(output_eotf);
5509}
5510
5511/**
5512 * drm_hdmi_infoframe_set_hdr_metadata() - fill an HDMI DRM infoframe with
5513 * HDR metadata from userspace
5514 * @frame: HDMI DRM infoframe
6ac98829 5515 * @conn_state: Connector state containing HDR metadata
2cdbfd66
US		 5516 *
5517 * Return: 0 on success or a negative error code on failure.
5518 */
5519int
5520drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame,
5521 const struct drm_connector_state *conn_state)
5522{
5523 struct drm_connector *connector;
5524 struct hdr_output_metadata *hdr_metadata;
5525 int err;
5526
5527 if (!frame || !conn_state)
5528 return -EINVAL;
5529
5530 connector = conn_state->connector;
5531
5532 if (!conn_state->hdr_output_metadata)
5533 return -EINVAL;
5534
5535 hdr_metadata = conn_state->hdr_output_metadata->data;
5536
5537 if (!hdr_metadata || !connector)
5538 return -EINVAL;
5539
5540 /* Sink EOTF is Bit map while infoframe is absolute values */
5541 if (!is_eotf_supported(hdr_metadata->hdmi_metadata_type1.eotf,
5542 connector->hdr_sink_metadata.hdmi_type1.eotf)) {
5543 DRM_DEBUG_KMS("EOTF Not Supported\n");
5544 return -EINVAL;
5545 }
5546
5547 err = hdmi_drm_infoframe_init(frame);
5548 if (err < 0)
5549 return err;
5550
5551 frame->eotf = hdr_metadata->hdmi_metadata_type1.eotf;
5552 frame->metadata_type = hdr_metadata->hdmi_metadata_type1.metadata_type;
5553
5554 BUILD_BUG_ON(sizeof(frame->display_primaries) !=
5555 sizeof(hdr_metadata->hdmi_metadata_type1.display_primaries));
5556 BUILD_BUG_ON(sizeof(frame->white_point) !=
5557 sizeof(hdr_metadata->hdmi_metadata_type1.white_point));
5558
5559 memcpy(&frame->display_primaries,
5560 &hdr_metadata->hdmi_metadata_type1.display_primaries,
5561 sizeof(frame->display_primaries));
5562
5563 memcpy(&frame->white_point,
5564 &hdr_metadata->hdmi_metadata_type1.white_point,
5565 sizeof(frame->white_point));
5566
5567 frame->max_display_mastering_luminance =
5568 hdr_metadata->hdmi_metadata_type1.max_display_mastering_luminance;
5569 frame->min_display_mastering_luminance =
5570 hdr_metadata->hdmi_metadata_type1.min_display_mastering_luminance;
5571 frame->max_fall = hdr_metadata->hdmi_metadata_type1.max_fall;
5572 frame->max_cll = hdr_metadata->hdmi_metadata_type1.max_cll;
5573
5574 return 0;
5575}
5576EXPORT_SYMBOL(drm_hdmi_infoframe_set_hdr_metadata);
5577
192a3aa0 5578static u8 drm_mode_hdmi_vic(const struct drm_connector *connector,
949561eb
VS		 5579 const struct drm_display_mode *mode)
5580{
5581 bool has_hdmi_infoframe = connector ?
5582 connector->display_info.has_hdmi_infoframe : false;
5583
5584 if (!has_hdmi_infoframe)
5585 return 0;
5586
5587 /* No HDMI VIC when signalling 3D video format */
5588 if (mode->flags & DRM_MODE_FLAG_3D_MASK)
5589 return 0;
5590
5591 return drm_match_hdmi_mode(mode);
5592}
5593
192a3aa0 5594static u8 drm_mode_cea_vic(const struct drm_connector *connector,
cfd6f8c3
VS		 5595 const struct drm_display_mode *mode)
5596{
cfd6f8c3
VS		 5597 u8 vic;
5598
5599 /*
5600 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
5601 * we should send its VIC in vendor infoframes, else send the
5602 * VIC in AVI infoframes. Lets check if this mode is present in
5603 * HDMI 1.4b 4K modes
5604 */
949561eb 5605 if (drm_mode_hdmi_vic(connector, mode))
cfd6f8c3
VS		 5606 return 0;
5607
5608 vic = drm_match_cea_mode(mode);
5609
5610 /*
5611 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
5612 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
5613 * have to make sure we dont break HDMI 1.4 sinks.
5614 */
5615 if (!is_hdmi2_sink(connector) && vic > 64)
5616 return 0;
5617
5618 return vic;
5619}
5620
10a85120
TR		 5621/**
5622 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
5623 * data from a DRM display mode
5624 * @frame: HDMI AVI infoframe
13d0add3 5625 * @connector: the connector
10a85120
TR		 5626 * @mode: DRM display mode
5627 *
db6cf833 5628 * Return: 0 on success or a negative error code on failure.
10a85120
TR		 5629 */
5630int
5631drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
192a3aa0 5632 const struct drm_connector *connector,
13d0add3 5633 const struct drm_display_mode *mode)
10a85120 5634{
a9c266c2 5635 enum hdmi_picture_aspect picture_aspect;
d2b43473 5636 u8 vic, hdmi_vic;
10a85120
TR		 5637
5638 if (!frame || !mode)
5639 return -EINVAL;
5640
5ee0caf1 5641 hdmi_avi_infoframe_init(frame);
10a85120 5642
bf02db99
DL		 5643 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
5644 frame->pixel_repeat = 1;
5645
d2b43473
WL		 5646 vic = drm_mode_cea_vic(connector, mode);
5647 hdmi_vic = drm_mode_hdmi_vic(connector, mode);
0c1f528c 5648
10a85120 5649 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
0967e6a5 5650
50525c33
SL		 5651 /*
5652 * As some drivers don't support atomic, we can't use connector state.
5653 * So just initialize the frame with default values, just the same way
5654 * as it's done with other properties here.
5655 */
5656 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
5657 frame->itc = 0;
5658
69ab6d35
VK		 5659 /*
5660 * Populate picture aspect ratio from either
d2b43473 5661 * user input (if specified) or from the CEA/HDMI mode lists.
69ab6d35 5662 */
a9c266c2 5663 picture_aspect = mode->picture_aspect_ratio;
d2b43473
WL		 5664 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) {
5665 if (vic)
5666 picture_aspect = drm_get_cea_aspect_ratio(vic);
5667 else if (hdmi_vic)
5668 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic);
5669 }
0967e6a5 5670
a9c266c2
VS		 5671 /*
5672 * The infoframe can't convey anything but none, 4:3
5673 * and 16:9, so if the user has asked for anything else
5674 * we can only satisfy it by specifying the right VIC.
5675 */
5676 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
d2b43473
WL		 5677 if (vic) {
5678 if (picture_aspect != drm_get_cea_aspect_ratio(vic))
5679 return -EINVAL;
5680 } else if (hdmi_vic) {
5681 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic))
5682 return -EINVAL;
5683 } else {
a9c266c2 5684 return -EINVAL;
d2b43473
WL		 5685 }
5686
a9c266c2
VS		 5687 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
5688 }
5689
d2b43473 5690 frame->video_code = vic;
a9c266c2 5691 frame->picture_aspect = picture_aspect;
10a85120 5692 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
24d01805 5693 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
10a85120
TR		 5694
5695 return 0;
5696}
5697EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
83dd0008 5698
0d68b887
US		 5699/* HDMI Colorspace Spec Definitions */
5700#define FULL_COLORIMETRY_MASK 0x1FF
5701#define NORMAL_COLORIMETRY_MASK 0x3
5702#define EXTENDED_COLORIMETRY_MASK 0x7
5703#define EXTENDED_ACE_COLORIMETRY_MASK 0xF
5704
5705#define C(x) ((x) << 0)
5706#define EC(x) ((x) << 2)
5707#define ACE(x) ((x) << 5)
5708
5709#define HDMI_COLORIMETRY_NO_DATA 0x0
5710#define HDMI_COLORIMETRY_SMPTE_170M_YCC (C(1) | EC(0) | ACE(0))
5711#define HDMI_COLORIMETRY_BT709_YCC (C(2) | EC(0) | ACE(0))
5712#define HDMI_COLORIMETRY_XVYCC_601 (C(3) | EC(0) | ACE(0))
5713#define HDMI_COLORIMETRY_XVYCC_709 (C(3) | EC(1) | ACE(0))
5714#define HDMI_COLORIMETRY_SYCC_601 (C(3) | EC(2) | ACE(0))
5715#define HDMI_COLORIMETRY_OPYCC_601 (C(3) | EC(3) | ACE(0))
5716#define HDMI_COLORIMETRY_OPRGB (C(3) | EC(4) | ACE(0))
5717#define HDMI_COLORIMETRY_BT2020_CYCC (C(3) | EC(5) | ACE(0))
5718#define HDMI_COLORIMETRY_BT2020_RGB (C(3) | EC(6) | ACE(0))
5719#define HDMI_COLORIMETRY_BT2020_YCC (C(3) | EC(6) | ACE(0))
5720#define HDMI_COLORIMETRY_DCI_P3_RGB_D65 (C(3) | EC(7) | ACE(0))
5721#define HDMI_COLORIMETRY_DCI_P3_RGB_THEATER (C(3) | EC(7) | ACE(1))
5722
5723static const u32 hdmi_colorimetry_val[] = {
5724 [DRM_MODE_COLORIMETRY_NO_DATA] = HDMI_COLORIMETRY_NO_DATA,
5725 [DRM_MODE_COLORIMETRY_SMPTE_170M_YCC] = HDMI_COLORIMETRY_SMPTE_170M_YCC,
5726 [DRM_MODE_COLORIMETRY_BT709_YCC] = HDMI_COLORIMETRY_BT709_YCC,
5727 [DRM_MODE_COLORIMETRY_XVYCC_601] = HDMI_COLORIMETRY_XVYCC_601,
5728 [DRM_MODE_COLORIMETRY_XVYCC_709] = HDMI_COLORIMETRY_XVYCC_709,
5729 [DRM_MODE_COLORIMETRY_SYCC_601] = HDMI_COLORIMETRY_SYCC_601,
5730 [DRM_MODE_COLORIMETRY_OPYCC_601] = HDMI_COLORIMETRY_OPYCC_601,
5731 [DRM_MODE_COLORIMETRY_OPRGB] = HDMI_COLORIMETRY_OPRGB,
5732 [DRM_MODE_COLORIMETRY_BT2020_CYCC] = HDMI_COLORIMETRY_BT2020_CYCC,
5733 [DRM_MODE_COLORIMETRY_BT2020_RGB] = HDMI_COLORIMETRY_BT2020_RGB,
5734 [DRM_MODE_COLORIMETRY_BT2020_YCC] = HDMI_COLORIMETRY_BT2020_YCC,
5735};
5736
5737#undef C
5738#undef EC
5739#undef ACE
5740
5741/**
5742 * drm_hdmi_avi_infoframe_colorspace() - fill the HDMI AVI infoframe
5743 * colorspace information
5744 * @frame: HDMI AVI infoframe
5745 * @conn_state: connector state
5746 */
5747void
5748drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame,
5749 const struct drm_connector_state *conn_state)
5750{
5751 u32 colorimetry_val;
5752 u32 colorimetry_index = conn_state->colorspace & FULL_COLORIMETRY_MASK;
5753
5754 if (colorimetry_index >= ARRAY_SIZE(hdmi_colorimetry_val))
5755 colorimetry_val = HDMI_COLORIMETRY_NO_DATA;
5756 else
5757 colorimetry_val = hdmi_colorimetry_val[colorimetry_index];
5758
5759 frame->colorimetry = colorimetry_val & NORMAL_COLORIMETRY_MASK;
5760 /*
5761 * ToDo: Extend it for ACE formats as well. Modify the infoframe
5762 * structure and extend it in drivers/video/hdmi
5763 */
5764 frame->extended_colorimetry = (colorimetry_val >> 2) &
5765 EXTENDED_COLORIMETRY_MASK;
5766}
5767EXPORT_SYMBOL(drm_hdmi_avi_infoframe_colorspace);
5768
a2ce26f8
VS		 5769/**
5770 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
5771 * quantization range information
5772 * @frame: HDMI AVI infoframe
13d0add3 5773 * @connector: the connector
779c4c28 5774 * @mode: DRM display mode
a2ce26f8 5775 * @rgb_quant_range: RGB quantization range (Q)
a2ce26f8
VS		 5776 */
5777void
5778drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
192a3aa0 5779 const struct drm_connector *connector,
779c4c28 5780 const struct drm_display_mode *mode,
1581b2df 5781 enum hdmi_quantization_range rgb_quant_range)
a2ce26f8 5782{
1581b2df
VS		 5783 const struct drm_display_info *info = &connector->display_info;
5784
a2ce26f8
VS		 5785 /*
5786 * CEA-861:
5787 * "A Source shall not send a non-zero Q value that does not correspond
5788 * to the default RGB Quantization Range for the transmitted Picture
5789 * unless the Sink indicates support for the Q bit in a Video
5790 * Capabilities Data Block."
779c4c28
VS		 5791 *
5792 * HDMI 2.0 recommends sending non-zero Q when it does match the
5793 * default RGB quantization range for the mode, even when QS=0.
a2ce26f8 5794 */
1581b2df 5795 if (info->rgb_quant_range_selectable ||
779c4c28 5796 rgb_quant_range == drm_default_rgb_quant_range(mode))
a2ce26f8
VS		 5797 frame->quantization_range = rgb_quant_range;
5798 else
5799 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
fcc8a22c
VS		 5800
5801 /*
5802 * CEA-861-F:
5803 * "When transmitting any RGB colorimetry, the Source should set the
5804 * YQ-field to match the RGB Quantization Range being transmitted
5805 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
5806 * set YQ=1) and the Sink shall ignore the YQ-field."
9271c0ca
VS		 5807 *
5808 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
5809 * by non-zero YQ when receiving RGB. There doesn't seem to be any
5810 * good way to tell which version of CEA-861 the sink supports, so
5811 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
5812 * on on CEA-861-F.
fcc8a22c 5813 */
13d0add3 5814 if (!is_hdmi2_sink(connector) ||
9271c0ca 5815 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
fcc8a22c
VS		 5816 frame->ycc_quantization_range =
5817 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
5818 else
5819 frame->ycc_quantization_range =
5820 HDMI_YCC_QUANTIZATION_RANGE_FULL;
a2ce26f8
VS		 5821}
5822EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
5823
076d9a5d
VS		 5824/**
5825 * drm_hdmi_avi_infoframe_bars() - fill the HDMI AVI infoframe
5826 * bar information
5827 * @frame: HDMI AVI infoframe
5828 * @conn_state: connector state
5829 */
5830void
5831drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe *frame,
5832 const struct drm_connector_state *conn_state)
5833{
5834 frame->right_bar = conn_state->tv.margins.right;
5835 frame->left_bar = conn_state->tv.margins.left;
5836 frame->top_bar = conn_state->tv.margins.top;
5837 frame->bottom_bar = conn_state->tv.margins.bottom;
5838}
5839EXPORT_SYMBOL(drm_hdmi_avi_infoframe_bars);
5840
4eed4a0a
DL		 5841static enum hdmi_3d_structure
5842s3d_structure_from_display_mode(const struct drm_display_mode *mode)
5843{
5844 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
5845
5846 switch (layout) {
5847 case DRM_MODE_FLAG_3D_FRAME_PACKING:
5848 return HDMI_3D_STRUCTURE_FRAME_PACKING;
5849 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
5850 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
5851 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
5852 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
5853 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
5854 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
5855 case DRM_MODE_FLAG_3D_L_DEPTH:
5856 return HDMI_3D_STRUCTURE_L_DEPTH;
5857 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
5858 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
5859 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
5860 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
5861 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
5862 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
5863 default:
5864 return HDMI_3D_STRUCTURE_INVALID;
5865 }
5866}
5867
83dd0008
LD		 5868/**
5869 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
5870 * data from a DRM display mode
5871 * @frame: HDMI vendor infoframe
f1781e9b 5872 * @connector: the connector
83dd0008
LD		 5873 * @mode: DRM display mode
5874 *
5875 * Note that there's is a need to send HDMI vendor infoframes only when using a
5876 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
5877 * function will return -EINVAL, error that can be safely ignored.
5878 *
db6cf833 5879 * Return: 0 on success or a negative error code on failure.
83dd0008
LD		 5880 */
5881int
5882drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
192a3aa0 5883 const struct drm_connector *connector,
83dd0008
LD		 5884 const struct drm_display_mode *mode)
5885{
f1781e9b
VS		 5886 /*
5887 * FIXME: sil-sii8620 doesn't have a connector around when
5888 * we need one, so we have to be prepared for a NULL connector.
5889 */
5890 bool has_hdmi_infoframe = connector ?
5891 connector->display_info.has_hdmi_infoframe : false;
83dd0008 5892 int err;
83dd0008
LD		 5893
5894 if (!frame || !mode)
5895 return -EINVAL;
5896
f1781e9b
VS		 5897 if (!has_hdmi_infoframe)
5898 return -EINVAL;
5899
949561eb
VS		 5900 err = hdmi_vendor_infoframe_init(frame);
5901 if (err < 0)
5902 return err;
4eed4a0a 5903
f1781e9b
VS		 5904 /*
5905 * Even if it's not absolutely necessary to send the infoframe
5906 * (ie.vic==0 and s3d_struct==0) we will still send it if we
5907 * know that the sink can handle it. This is based on a
5908 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
0ae865ef 5909 * have trouble realizing that they should switch from 3D to 2D
f1781e9b
VS		 5910 * mode if the source simply stops sending the infoframe when
5911 * it wants to switch from 3D to 2D.
5912 */
949561eb 5913 frame->vic = drm_mode_hdmi_vic(connector, mode);
f1781e9b 5914 frame->s3d_struct = s3d_structure_from_display_mode(mode);
83dd0008
LD		 5915
5916 return 0;
5917}
5918EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
40d9b043 5919
7f261afd
VS		 5920static void drm_parse_tiled_block(struct drm_connector *connector,
5921 const struct displayid_block *block)
5e546cd5 5922{
092c367a 5923 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
5e546cd5
DA		 5924 u16 w, h;
5925 u8 tile_v_loc, tile_h_loc;
5926 u8 num_v_tile, num_h_tile;
5927 struct drm_tile_group *tg;
5928
5929 w = tile->tile_size[0] | tile->tile_size[1] << 8;
5930 h = tile->tile_size[2] | tile->tile_size[3] << 8;
5931
5932 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
5933 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
5934 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
5935 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
5936
5937 connector->has_tile = true;
5938 if (tile->tile_cap & 0x80)
5939 connector->tile_is_single_monitor = true;
5940
5941 connector->num_h_tile = num_h_tile + 1;
5942 connector->num_v_tile = num_v_tile + 1;
5943 connector->tile_h_loc = tile_h_loc;
5944 connector->tile_v_loc = tile_v_loc;
5945 connector->tile_h_size = w + 1;
5946 connector->tile_v_size = h + 1;
5947
5948 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
5949 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
5950 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
5951 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
5952 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
5953
5954 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
392f9fcb 5955 if (!tg)
5e546cd5 5956 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
5e546cd5 5957 if (!tg)
7f261afd 5958 return;
5e546cd5
DA		 5959
5960 if (connector->tile_group != tg) {
5961 /* if we haven't got a pointer,
5962 take the reference, drop ref to old tile group */
392f9fcb 5963 if (connector->tile_group)
5e546cd5 5964 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5e546cd5 5965 connector->tile_group = tg;
392f9fcb 5966 } else {
5e546cd5
DA		 5967 /* if same tile group, then release the ref we just took. */
5968 drm_mode_put_tile_group(connector->dev, tg);
392f9fcb 5969 }
5e546cd5
DA		 5970}
5971
092c367a
VS		 5972void drm_update_tile_info(struct drm_connector *connector,
5973 const struct edid *edid)
40d9b043 5974{
bfd4e192
JN		 5975 const struct displayid_block *block;
5976 struct displayid_iter iter;
36881184 5977
40d9b043 5978 connector->has_tile = false;
7f261afd 5979
bfd4e192
JN		 5980 displayid_iter_edid_begin(edid, &iter);
5981 displayid_iter_for_each(block, &iter) {
5982 if (block->tag == DATA_BLOCK_TILED_DISPLAY)
5983 drm_parse_tiled_block(connector, block);
40d9b043 5984 }
bfd4e192 5985 displayid_iter_end(&iter);
40d9b043 5986
7f261afd 5987 if (!connector->has_tile && connector->tile_group) {
40d9b043
DA		 5988 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5989 connector->tile_group = NULL;
5990 }
40d9b043 5991}
Linux 6.x block layer and io_uring tree(s)