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f453ba04 DA |
1 | /* |
2 | * Copyright (c) 2006 Luc Verhaegen (quirks list) | |
3 | * Copyright (c) 2007-2008 Intel Corporation | |
4 | * Jesse Barnes <jesse.barnes@intel.com> | |
61e57a8d | 5 | * Copyright 2010 Red Hat, Inc. |
f453ba04 DA |
6 | * |
7 | * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from | |
8 | * FB layer. | |
9 | * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> | |
10 | * | |
11 | * Permission is hereby granted, free of charge, to any person obtaining a | |
12 | * copy of this software and associated documentation files (the "Software"), | |
13 | * to deal in the Software without restriction, including without limitation | |
14 | * the rights to use, copy, modify, merge, publish, distribute, sub license, | |
15 | * and/or sell copies of the Software, and to permit persons to whom the | |
16 | * Software is furnished to do so, subject to the following conditions: | |
17 | * | |
18 | * The above copyright notice and this permission notice (including the | |
19 | * next paragraph) shall be included in all copies or substantial portions | |
20 | * of the Software. | |
21 | * | |
22 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
23 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
24 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
25 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
26 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
27 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
28 | * DEALINGS IN THE SOFTWARE. | |
29 | */ | |
9c79edec | 30 | |
18a9cbbe | 31 | #include <linux/bitfield.h> |
10a85120 | 32 | #include <linux/hdmi.h> |
f453ba04 | 33 | #include <linux/i2c.h> |
9c79edec | 34 | #include <linux/kernel.h> |
47819ba2 | 35 | #include <linux/module.h> |
36b73b05 | 36 | #include <linux/pci.h> |
9c79edec | 37 | #include <linux/slab.h> |
5cb8eaa2 | 38 | #include <linux/vga_switcheroo.h> |
9c79edec JN |
39 | |
40 | #include <drm/drm_displayid.h> | |
41 | #include <drm/drm_drv.h> | |
760285e7 | 42 | #include <drm/drm_edid.h> |
9338203c | 43 | #include <drm/drm_encoder.h> |
9c79edec | 44 | #include <drm/drm_print.h> |
f453ba04 | 45 | |
969218fe TI |
46 | #include "drm_crtc_internal.h" |
47 | ||
13931579 AJ |
48 | #define version_greater(edid, maj, min) \ |
49 | (((edid)->version > (maj)) || \ | |
50 | ((edid)->version == (maj) && (edid)->revision > (min))) | |
f453ba04 | 51 | |
37eab1fe JN |
52 | static int oui(u8 first, u8 second, u8 third) |
53 | { | |
54 | return (first << 16) | (second << 8) | third; | |
55 | } | |
56 | ||
d1ff6409 AJ |
57 | #define EDID_EST_TIMINGS 16 |
58 | #define EDID_STD_TIMINGS 8 | |
59 | #define EDID_DETAILED_TIMINGS 4 | |
f453ba04 DA |
60 | |
61 | /* | |
62 | * EDID blocks out in the wild have a variety of bugs, try to collect | |
63 | * them here (note that userspace may work around broken monitors first, | |
64 | * but fixes should make their way here so that the kernel "just works" | |
65 | * on as many displays as possible). | |
66 | */ | |
67 | ||
68 | /* First detailed mode wrong, use largest 60Hz mode */ | |
69 | #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) | |
70 | /* Reported 135MHz pixel clock is too high, needs adjustment */ | |
71 | #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) | |
72 | /* Prefer the largest mode at 75 Hz */ | |
73 | #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) | |
74 | /* Detail timing is in cm not mm */ | |
75 | #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) | |
76 | /* Detailed timing descriptors have bogus size values, so just take the | |
77 | * maximum size and use that. | |
78 | */ | |
79 | #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) | |
f453ba04 DA |
80 | /* use +hsync +vsync for detailed mode */ |
81 | #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) | |
bc42aabc AJ |
82 | /* Force reduced-blanking timings for detailed modes */ |
83 | #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) | |
49d45a31 RM |
84 | /* Force 8bpc */ |
85 | #define EDID_QUIRK_FORCE_8BPC (1 << 8) | |
bc5b9641 MK |
86 | /* Force 12bpc */ |
87 | #define EDID_QUIRK_FORCE_12BPC (1 << 9) | |
e10aec65 MK |
88 | /* Force 6bpc */ |
89 | #define EDID_QUIRK_FORCE_6BPC (1 << 10) | |
e345da82 MK |
90 | /* Force 10bpc */ |
91 | #define EDID_QUIRK_FORCE_10BPC (1 << 11) | |
66660d4c DA |
92 | /* Non desktop display (i.e. HMD) */ |
93 | #define EDID_QUIRK_NON_DESKTOP (1 << 12) | |
3c537889 | 94 | |
2869f599 PZ |
95 | #define MICROSOFT_IEEE_OUI 0xca125c |
96 | ||
13931579 AJ |
97 | struct detailed_mode_closure { |
98 | struct drm_connector *connector; | |
c14e7241 | 99 | const struct edid *edid; |
13931579 AJ |
100 | bool preferred; |
101 | u32 quirks; | |
102 | int modes; | |
103 | }; | |
f453ba04 | 104 | |
5c61259e ZY |
105 | #define LEVEL_DMT 0 |
106 | #define LEVEL_GTF 1 | |
7a374350 AJ |
107 | #define LEVEL_GTF2 2 |
108 | #define LEVEL_CVT 3 | |
5c61259e | 109 | |
7d1be0a0 | 110 | #define EDID_QUIRK(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _quirks) \ |
e8de4d55 | 111 | { \ |
7d1be0a0 DA |
112 | .panel_id = drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, \ |
113 | product_id), \ | |
e8de4d55 DA |
114 | .quirks = _quirks \ |
115 | } | |
116 | ||
23c4cfbd | 117 | static const struct edid_quirk { |
e8de4d55 | 118 | u32 panel_id; |
f453ba04 DA |
119 | u32 quirks; |
120 | } edid_quirk_list[] = { | |
121 | /* Acer AL1706 */ | |
7d1be0a0 | 122 | EDID_QUIRK('A', 'C', 'R', 44358, EDID_QUIRK_PREFER_LARGE_60), |
f453ba04 | 123 | /* Acer F51 */ |
7d1be0a0 | 124 | EDID_QUIRK('A', 'P', 'I', 0x7602, EDID_QUIRK_PREFER_LARGE_60), |
f453ba04 | 125 | |
e10aec65 | 126 | /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ |
7d1be0a0 | 127 | EDID_QUIRK('A', 'E', 'O', 0, EDID_QUIRK_FORCE_6BPC), |
e10aec65 | 128 | |
0711a43b | 129 | /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */ |
7d1be0a0 | 130 | EDID_QUIRK('B', 'O', 'E', 0x78b, EDID_QUIRK_FORCE_6BPC), |
0711a43b | 131 | |
06998a75 | 132 | /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */ |
7d1be0a0 | 133 | EDID_QUIRK('C', 'P', 'T', 0x17df, EDID_QUIRK_FORCE_6BPC), |
06998a75 | 134 | |
25da7504 | 135 | /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */ |
7d1be0a0 | 136 | EDID_QUIRK('S', 'D', 'C', 0x3652, EDID_QUIRK_FORCE_6BPC), |
25da7504 | 137 | |
922dceff | 138 | /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */ |
7d1be0a0 | 139 | EDID_QUIRK('B', 'O', 'E', 0x0771, EDID_QUIRK_FORCE_6BPC), |
922dceff | 140 | |
f453ba04 | 141 | /* Belinea 10 15 55 */ |
7d1be0a0 DA |
142 | EDID_QUIRK('M', 'A', 'X', 1516, EDID_QUIRK_PREFER_LARGE_60), |
143 | EDID_QUIRK('M', 'A', 'X', 0x77e, EDID_QUIRK_PREFER_LARGE_60), | |
f453ba04 DA |
144 | |
145 | /* Envision Peripherals, Inc. EN-7100e */ | |
7d1be0a0 | 146 | EDID_QUIRK('E', 'P', 'I', 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH), |
ba1163de | 147 | /* Envision EN2028 */ |
7d1be0a0 | 148 | EDID_QUIRK('E', 'P', 'I', 8232, EDID_QUIRK_PREFER_LARGE_60), |
f453ba04 DA |
149 | |
150 | /* Funai Electronics PM36B */ | |
7d1be0a0 | 151 | EDID_QUIRK('F', 'C', 'M', 13600, EDID_QUIRK_PREFER_LARGE_75 | |
e8de4d55 | 152 | EDID_QUIRK_DETAILED_IN_CM), |
f453ba04 | 153 | |
e345da82 | 154 | /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ |
7d1be0a0 | 155 | EDID_QUIRK('L', 'G', 'D', 764, EDID_QUIRK_FORCE_10BPC), |
e345da82 | 156 | |
f453ba04 | 157 | /* LG Philips LCD LP154W01-A5 */ |
7d1be0a0 DA |
158 | EDID_QUIRK('L', 'P', 'L', 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE), |
159 | EDID_QUIRK('L', 'P', 'L', 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE), | |
f453ba04 | 160 | |
f453ba04 | 161 | /* Samsung SyncMaster 205BW. Note: irony */ |
7d1be0a0 | 162 | EDID_QUIRK('S', 'A', 'M', 541, EDID_QUIRK_DETAILED_SYNC_PP), |
f453ba04 | 163 | /* Samsung SyncMaster 22[5-6]BW */ |
7d1be0a0 DA |
164 | EDID_QUIRK('S', 'A', 'M', 596, EDID_QUIRK_PREFER_LARGE_60), |
165 | EDID_QUIRK('S', 'A', 'M', 638, EDID_QUIRK_PREFER_LARGE_60), | |
bc42aabc | 166 | |
bc5b9641 | 167 | /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ |
7d1be0a0 | 168 | EDID_QUIRK('S', 'N', 'Y', 0x2541, EDID_QUIRK_FORCE_12BPC), |
bc5b9641 | 169 | |
bc42aabc | 170 | /* ViewSonic VA2026w */ |
7d1be0a0 | 171 | EDID_QUIRK('V', 'S', 'C', 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING), |
118bdbd8 AD |
172 | |
173 | /* Medion MD 30217 PG */ | |
7d1be0a0 | 174 | EDID_QUIRK('M', 'E', 'D', 0x7b8, EDID_QUIRK_PREFER_LARGE_75), |
49d45a31 | 175 | |
11bcf5f7 | 176 | /* Lenovo G50 */ |
7d1be0a0 | 177 | EDID_QUIRK('S', 'D', 'C', 18514, EDID_QUIRK_FORCE_6BPC), |
11bcf5f7 | 178 | |
49d45a31 | 179 | /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ |
7d1be0a0 | 180 | EDID_QUIRK('S', 'E', 'C', 0xd033, EDID_QUIRK_FORCE_8BPC), |
36fc5797 TV |
181 | |
182 | /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ | |
7d1be0a0 | 183 | EDID_QUIRK('E', 'T', 'R', 13896, EDID_QUIRK_FORCE_8BPC), |
acb1d8ee | 184 | |
30d62d44 | 185 | /* Valve Index Headset */ |
7d1be0a0 DA |
186 | EDID_QUIRK('V', 'L', 'V', 0x91a8, EDID_QUIRK_NON_DESKTOP), |
187 | EDID_QUIRK('V', 'L', 'V', 0x91b0, EDID_QUIRK_NON_DESKTOP), | |
188 | EDID_QUIRK('V', 'L', 'V', 0x91b1, EDID_QUIRK_NON_DESKTOP), | |
189 | EDID_QUIRK('V', 'L', 'V', 0x91b2, EDID_QUIRK_NON_DESKTOP), | |
190 | EDID_QUIRK('V', 'L', 'V', 0x91b3, EDID_QUIRK_NON_DESKTOP), | |
191 | EDID_QUIRK('V', 'L', 'V', 0x91b4, EDID_QUIRK_NON_DESKTOP), | |
192 | EDID_QUIRK('V', 'L', 'V', 0x91b5, EDID_QUIRK_NON_DESKTOP), | |
193 | EDID_QUIRK('V', 'L', 'V', 0x91b6, EDID_QUIRK_NON_DESKTOP), | |
194 | EDID_QUIRK('V', 'L', 'V', 0x91b7, EDID_QUIRK_NON_DESKTOP), | |
195 | EDID_QUIRK('V', 'L', 'V', 0x91b8, EDID_QUIRK_NON_DESKTOP), | |
196 | EDID_QUIRK('V', 'L', 'V', 0x91b9, EDID_QUIRK_NON_DESKTOP), | |
197 | EDID_QUIRK('V', 'L', 'V', 0x91ba, EDID_QUIRK_NON_DESKTOP), | |
198 | EDID_QUIRK('V', 'L', 'V', 0x91bb, EDID_QUIRK_NON_DESKTOP), | |
199 | EDID_QUIRK('V', 'L', 'V', 0x91bc, EDID_QUIRK_NON_DESKTOP), | |
200 | EDID_QUIRK('V', 'L', 'V', 0x91bd, EDID_QUIRK_NON_DESKTOP), | |
201 | EDID_QUIRK('V', 'L', 'V', 0x91be, EDID_QUIRK_NON_DESKTOP), | |
202 | EDID_QUIRK('V', 'L', 'V', 0x91bf, EDID_QUIRK_NON_DESKTOP), | |
30d62d44 | 203 | |
6931317c | 204 | /* HTC Vive and Vive Pro VR Headsets */ |
7d1be0a0 DA |
205 | EDID_QUIRK('H', 'V', 'R', 0xaa01, EDID_QUIRK_NON_DESKTOP), |
206 | EDID_QUIRK('H', 'V', 'R', 0xaa02, EDID_QUIRK_NON_DESKTOP), | |
b3b12ea3 | 207 | |
5a3f6108 | 208 | /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */ |
7d1be0a0 DA |
209 | EDID_QUIRK('O', 'V', 'R', 0x0001, EDID_QUIRK_NON_DESKTOP), |
210 | EDID_QUIRK('O', 'V', 'R', 0x0003, EDID_QUIRK_NON_DESKTOP), | |
211 | EDID_QUIRK('O', 'V', 'R', 0x0004, EDID_QUIRK_NON_DESKTOP), | |
212 | EDID_QUIRK('O', 'V', 'R', 0x0012, EDID_QUIRK_NON_DESKTOP), | |
90eda8fc PZ |
213 | |
214 | /* Windows Mixed Reality Headsets */ | |
7d1be0a0 | 215 | EDID_QUIRK('A', 'C', 'R', 0x7fce, EDID_QUIRK_NON_DESKTOP), |
7d1be0a0 | 216 | EDID_QUIRK('L', 'E', 'N', 0x0408, EDID_QUIRK_NON_DESKTOP), |
7d1be0a0 DA |
217 | EDID_QUIRK('F', 'U', 'J', 0x1970, EDID_QUIRK_NON_DESKTOP), |
218 | EDID_QUIRK('D', 'E', 'L', 0x7fce, EDID_QUIRK_NON_DESKTOP), | |
219 | EDID_QUIRK('S', 'E', 'C', 0x144a, EDID_QUIRK_NON_DESKTOP), | |
220 | EDID_QUIRK('A', 'U', 'S', 0xc102, EDID_QUIRK_NON_DESKTOP), | |
ccffc9eb PZ |
221 | |
222 | /* Sony PlayStation VR Headset */ | |
7d1be0a0 | 223 | EDID_QUIRK('S', 'N', 'Y', 0x0704, EDID_QUIRK_NON_DESKTOP), |
29054230 RP |
224 | |
225 | /* Sensics VR Headsets */ | |
7d1be0a0 | 226 | EDID_QUIRK('S', 'E', 'N', 0x1019, EDID_QUIRK_NON_DESKTOP), |
29054230 RP |
227 | |
228 | /* OSVR HDK and HDK2 VR Headsets */ | |
7d1be0a0 | 229 | EDID_QUIRK('S', 'V', 'R', 0x1019, EDID_QUIRK_NON_DESKTOP), |
f453ba04 DA |
230 | }; |
231 | ||
a6b21831 TR |
232 | /* |
233 | * Autogenerated from the DMT spec. | |
234 | * This table is copied from xfree86/modes/xf86EdidModes.c. | |
235 | */ | |
236 | static const struct drm_display_mode drm_dmt_modes[] = { | |
24b856b1 | 237 | /* 0x01 - 640x350@85Hz */ |
a6b21831 TR |
238 | { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, |
239 | 736, 832, 0, 350, 382, 385, 445, 0, | |
240 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 241 | /* 0x02 - 640x400@85Hz */ |
a6b21831 TR |
242 | { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, |
243 | 736, 832, 0, 400, 401, 404, 445, 0, | |
244 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 245 | /* 0x03 - 720x400@85Hz */ |
a6b21831 TR |
246 | { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, |
247 | 828, 936, 0, 400, 401, 404, 446, 0, | |
248 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 249 | /* 0x04 - 640x480@60Hz */ |
a6b21831 | 250 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, |
fcf22d05 | 251 | 752, 800, 0, 480, 490, 492, 525, 0, |
a6b21831 | 252 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, |
24b856b1 | 253 | /* 0x05 - 640x480@72Hz */ |
a6b21831 TR |
254 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, |
255 | 704, 832, 0, 480, 489, 492, 520, 0, | |
256 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 257 | /* 0x06 - 640x480@75Hz */ |
a6b21831 TR |
258 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, |
259 | 720, 840, 0, 480, 481, 484, 500, 0, | |
260 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 261 | /* 0x07 - 640x480@85Hz */ |
a6b21831 TR |
262 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, |
263 | 752, 832, 0, 480, 481, 484, 509, 0, | |
264 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 265 | /* 0x08 - 800x600@56Hz */ |
a6b21831 TR |
266 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, |
267 | 896, 1024, 0, 600, 601, 603, 625, 0, | |
268 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 269 | /* 0x09 - 800x600@60Hz */ |
a6b21831 TR |
270 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, |
271 | 968, 1056, 0, 600, 601, 605, 628, 0, | |
272 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 273 | /* 0x0a - 800x600@72Hz */ |
a6b21831 TR |
274 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, |
275 | 976, 1040, 0, 600, 637, 643, 666, 0, | |
276 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 277 | /* 0x0b - 800x600@75Hz */ |
a6b21831 TR |
278 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, |
279 | 896, 1056, 0, 600, 601, 604, 625, 0, | |
280 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 281 | /* 0x0c - 800x600@85Hz */ |
a6b21831 TR |
282 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, |
283 | 896, 1048, 0, 600, 601, 604, 631, 0, | |
284 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 285 | /* 0x0d - 800x600@120Hz RB */ |
a6b21831 TR |
286 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, |
287 | 880, 960, 0, 600, 603, 607, 636, 0, | |
288 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 289 | /* 0x0e - 848x480@60Hz */ |
a6b21831 TR |
290 | { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, |
291 | 976, 1088, 0, 480, 486, 494, 517, 0, | |
292 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 293 | /* 0x0f - 1024x768@43Hz, interlace */ |
a6b21831 | 294 | { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, |
735b100f | 295 | 1208, 1264, 0, 768, 768, 776, 817, 0, |
a6b21831 | 296 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | |
fcf22d05 | 297 | DRM_MODE_FLAG_INTERLACE) }, |
24b856b1 | 298 | /* 0x10 - 1024x768@60Hz */ |
a6b21831 TR |
299 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, |
300 | 1184, 1344, 0, 768, 771, 777, 806, 0, | |
301 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 302 | /* 0x11 - 1024x768@70Hz */ |
a6b21831 TR |
303 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, |
304 | 1184, 1328, 0, 768, 771, 777, 806, 0, | |
305 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 306 | /* 0x12 - 1024x768@75Hz */ |
a6b21831 TR |
307 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, |
308 | 1136, 1312, 0, 768, 769, 772, 800, 0, | |
309 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 310 | /* 0x13 - 1024x768@85Hz */ |
a6b21831 TR |
311 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, |
312 | 1168, 1376, 0, 768, 769, 772, 808, 0, | |
313 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 314 | /* 0x14 - 1024x768@120Hz RB */ |
a6b21831 TR |
315 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, |
316 | 1104, 1184, 0, 768, 771, 775, 813, 0, | |
317 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 318 | /* 0x15 - 1152x864@75Hz */ |
a6b21831 TR |
319 | { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, |
320 | 1344, 1600, 0, 864, 865, 868, 900, 0, | |
321 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
bfcd74d2 VS |
322 | /* 0x55 - 1280x720@60Hz */ |
323 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, | |
324 | 1430, 1650, 0, 720, 725, 730, 750, 0, | |
325 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 326 | /* 0x16 - 1280x768@60Hz RB */ |
a6b21831 TR |
327 | { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, |
328 | 1360, 1440, 0, 768, 771, 778, 790, 0, | |
329 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 330 | /* 0x17 - 1280x768@60Hz */ |
a6b21831 TR |
331 | { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, |
332 | 1472, 1664, 0, 768, 771, 778, 798, 0, | |
333 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 334 | /* 0x18 - 1280x768@75Hz */ |
a6b21831 TR |
335 | { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, |
336 | 1488, 1696, 0, 768, 771, 778, 805, 0, | |
fcf22d05 | 337 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
24b856b1 | 338 | /* 0x19 - 1280x768@85Hz */ |
a6b21831 TR |
339 | { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, |
340 | 1496, 1712, 0, 768, 771, 778, 809, 0, | |
341 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 342 | /* 0x1a - 1280x768@120Hz RB */ |
a6b21831 TR |
343 | { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, |
344 | 1360, 1440, 0, 768, 771, 778, 813, 0, | |
345 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 346 | /* 0x1b - 1280x800@60Hz RB */ |
a6b21831 TR |
347 | { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, |
348 | 1360, 1440, 0, 800, 803, 809, 823, 0, | |
349 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 350 | /* 0x1c - 1280x800@60Hz */ |
a6b21831 TR |
351 | { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, |
352 | 1480, 1680, 0, 800, 803, 809, 831, 0, | |
fcf22d05 | 353 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
24b856b1 | 354 | /* 0x1d - 1280x800@75Hz */ |
a6b21831 TR |
355 | { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, |
356 | 1488, 1696, 0, 800, 803, 809, 838, 0, | |
357 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 358 | /* 0x1e - 1280x800@85Hz */ |
a6b21831 TR |
359 | { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, |
360 | 1496, 1712, 0, 800, 803, 809, 843, 0, | |
361 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 362 | /* 0x1f - 1280x800@120Hz RB */ |
a6b21831 TR |
363 | { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, |
364 | 1360, 1440, 0, 800, 803, 809, 847, 0, | |
365 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 366 | /* 0x20 - 1280x960@60Hz */ |
a6b21831 TR |
367 | { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, |
368 | 1488, 1800, 0, 960, 961, 964, 1000, 0, | |
369 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 370 | /* 0x21 - 1280x960@85Hz */ |
a6b21831 TR |
371 | { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, |
372 | 1504, 1728, 0, 960, 961, 964, 1011, 0, | |
373 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 374 | /* 0x22 - 1280x960@120Hz RB */ |
a6b21831 TR |
375 | { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, |
376 | 1360, 1440, 0, 960, 963, 967, 1017, 0, | |
377 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 378 | /* 0x23 - 1280x1024@60Hz */ |
a6b21831 TR |
379 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, |
380 | 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, | |
381 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 382 | /* 0x24 - 1280x1024@75Hz */ |
a6b21831 TR |
383 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, |
384 | 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, | |
385 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 386 | /* 0x25 - 1280x1024@85Hz */ |
a6b21831 TR |
387 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, |
388 | 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, | |
389 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 390 | /* 0x26 - 1280x1024@120Hz RB */ |
a6b21831 TR |
391 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, |
392 | 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, | |
393 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 394 | /* 0x27 - 1360x768@60Hz */ |
a6b21831 TR |
395 | { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, |
396 | 1536, 1792, 0, 768, 771, 777, 795, 0, | |
397 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 398 | /* 0x28 - 1360x768@120Hz RB */ |
a6b21831 TR |
399 | { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, |
400 | 1440, 1520, 0, 768, 771, 776, 813, 0, | |
401 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
bfcd74d2 VS |
402 | /* 0x51 - 1366x768@60Hz */ |
403 | { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, | |
404 | 1579, 1792, 0, 768, 771, 774, 798, 0, | |
405 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
406 | /* 0x56 - 1366x768@60Hz */ | |
407 | { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, | |
408 | 1436, 1500, 0, 768, 769, 772, 800, 0, | |
409 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 410 | /* 0x29 - 1400x1050@60Hz RB */ |
a6b21831 TR |
411 | { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, |
412 | 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, | |
413 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 414 | /* 0x2a - 1400x1050@60Hz */ |
a6b21831 TR |
415 | { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, |
416 | 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, | |
417 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 418 | /* 0x2b - 1400x1050@75Hz */ |
a6b21831 TR |
419 | { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, |
420 | 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, | |
421 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 422 | /* 0x2c - 1400x1050@85Hz */ |
a6b21831 TR |
423 | { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, |
424 | 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, | |
425 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 426 | /* 0x2d - 1400x1050@120Hz RB */ |
a6b21831 TR |
427 | { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, |
428 | 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, | |
429 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 430 | /* 0x2e - 1440x900@60Hz RB */ |
a6b21831 TR |
431 | { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, |
432 | 1520, 1600, 0, 900, 903, 909, 926, 0, | |
433 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 434 | /* 0x2f - 1440x900@60Hz */ |
a6b21831 TR |
435 | { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, |
436 | 1672, 1904, 0, 900, 903, 909, 934, 0, | |
437 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 438 | /* 0x30 - 1440x900@75Hz */ |
a6b21831 TR |
439 | { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, |
440 | 1688, 1936, 0, 900, 903, 909, 942, 0, | |
441 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 442 | /* 0x31 - 1440x900@85Hz */ |
a6b21831 TR |
443 | { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, |
444 | 1696, 1952, 0, 900, 903, 909, 948, 0, | |
445 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 446 | /* 0x32 - 1440x900@120Hz RB */ |
a6b21831 TR |
447 | { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, |
448 | 1520, 1600, 0, 900, 903, 909, 953, 0, | |
449 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
bfcd74d2 VS |
450 | /* 0x53 - 1600x900@60Hz */ |
451 | { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, | |
452 | 1704, 1800, 0, 900, 901, 904, 1000, 0, | |
453 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 454 | /* 0x33 - 1600x1200@60Hz */ |
a6b21831 TR |
455 | { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, |
456 | 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, | |
457 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 458 | /* 0x34 - 1600x1200@65Hz */ |
a6b21831 TR |
459 | { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, |
460 | 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, | |
461 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 462 | /* 0x35 - 1600x1200@70Hz */ |
a6b21831 TR |
463 | { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, |
464 | 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, | |
465 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 466 | /* 0x36 - 1600x1200@75Hz */ |
a6b21831 TR |
467 | { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, |
468 | 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, | |
469 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 470 | /* 0x37 - 1600x1200@85Hz */ |
a6b21831 TR |
471 | { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, |
472 | 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, | |
473 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 474 | /* 0x38 - 1600x1200@120Hz RB */ |
a6b21831 TR |
475 | { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, |
476 | 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, | |
477 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 478 | /* 0x39 - 1680x1050@60Hz RB */ |
a6b21831 TR |
479 | { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, |
480 | 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, | |
481 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 482 | /* 0x3a - 1680x1050@60Hz */ |
a6b21831 TR |
483 | { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, |
484 | 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, | |
485 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 486 | /* 0x3b - 1680x1050@75Hz */ |
a6b21831 TR |
487 | { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, |
488 | 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, | |
489 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 490 | /* 0x3c - 1680x1050@85Hz */ |
a6b21831 TR |
491 | { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, |
492 | 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, | |
493 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 494 | /* 0x3d - 1680x1050@120Hz RB */ |
a6b21831 TR |
495 | { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, |
496 | 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, | |
497 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 498 | /* 0x3e - 1792x1344@60Hz */ |
a6b21831 TR |
499 | { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, |
500 | 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, | |
501 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 502 | /* 0x3f - 1792x1344@75Hz */ |
a6b21831 TR |
503 | { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, |
504 | 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, | |
505 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 506 | /* 0x40 - 1792x1344@120Hz RB */ |
a6b21831 TR |
507 | { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, |
508 | 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, | |
509 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 510 | /* 0x41 - 1856x1392@60Hz */ |
a6b21831 TR |
511 | { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, |
512 | 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, | |
513 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 514 | /* 0x42 - 1856x1392@75Hz */ |
a6b21831 | 515 | { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, |
fcf22d05 | 516 | 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, |
a6b21831 | 517 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
24b856b1 | 518 | /* 0x43 - 1856x1392@120Hz RB */ |
a6b21831 TR |
519 | { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, |
520 | 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, | |
521 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
bfcd74d2 VS |
522 | /* 0x52 - 1920x1080@60Hz */ |
523 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, | |
524 | 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, | |
525 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 526 | /* 0x44 - 1920x1200@60Hz RB */ |
a6b21831 TR |
527 | { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, |
528 | 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, | |
529 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 530 | /* 0x45 - 1920x1200@60Hz */ |
a6b21831 TR |
531 | { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, |
532 | 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, | |
533 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 534 | /* 0x46 - 1920x1200@75Hz */ |
a6b21831 TR |
535 | { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, |
536 | 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, | |
537 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 538 | /* 0x47 - 1920x1200@85Hz */ |
a6b21831 TR |
539 | { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, |
540 | 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, | |
541 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 542 | /* 0x48 - 1920x1200@120Hz RB */ |
a6b21831 TR |
543 | { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, |
544 | 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, | |
545 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 546 | /* 0x49 - 1920x1440@60Hz */ |
a6b21831 TR |
547 | { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, |
548 | 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, | |
549 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 550 | /* 0x4a - 1920x1440@75Hz */ |
a6b21831 TR |
551 | { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, |
552 | 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, | |
553 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 554 | /* 0x4b - 1920x1440@120Hz RB */ |
a6b21831 TR |
555 | { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, |
556 | 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, | |
557 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
bfcd74d2 VS |
558 | /* 0x54 - 2048x1152@60Hz */ |
559 | { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, | |
560 | 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, | |
561 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 562 | /* 0x4c - 2560x1600@60Hz RB */ |
a6b21831 TR |
563 | { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, |
564 | 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, | |
565 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 566 | /* 0x4d - 2560x1600@60Hz */ |
a6b21831 TR |
567 | { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, |
568 | 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, | |
569 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 570 | /* 0x4e - 2560x1600@75Hz */ |
a6b21831 TR |
571 | { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, |
572 | 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, | |
573 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 574 | /* 0x4f - 2560x1600@85Hz */ |
a6b21831 TR |
575 | { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, |
576 | 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, | |
577 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 578 | /* 0x50 - 2560x1600@120Hz RB */ |
a6b21831 TR |
579 | { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, |
580 | 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, | |
581 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
bfcd74d2 VS |
582 | /* 0x57 - 4096x2160@60Hz RB */ |
583 | { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, | |
584 | 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, | |
585 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
586 | /* 0x58 - 4096x2160@59.94Hz RB */ | |
587 | { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, | |
588 | 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, | |
589 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
a6b21831 TR |
590 | }; |
591 | ||
e7bfa5c4 VS |
592 | /* |
593 | * These more or less come from the DMT spec. The 720x400 modes are | |
594 | * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 | |
595 | * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode | |
596 | * should be 1152x870, again for the Mac, but instead we use the x864 DMT | |
597 | * mode. | |
598 | * | |
599 | * The DMT modes have been fact-checked; the rest are mild guesses. | |
600 | */ | |
a6b21831 TR |
601 | static const struct drm_display_mode edid_est_modes[] = { |
602 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, | |
603 | 968, 1056, 0, 600, 601, 605, 628, 0, | |
604 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ | |
605 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, | |
606 | 896, 1024, 0, 600, 601, 603, 625, 0, | |
607 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ | |
608 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, | |
609 | 720, 840, 0, 480, 481, 484, 500, 0, | |
610 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ | |
611 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, | |
87707cfd | 612 | 704, 832, 0, 480, 489, 492, 520, 0, |
a6b21831 TR |
613 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ |
614 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, | |
615 | 768, 864, 0, 480, 483, 486, 525, 0, | |
616 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ | |
87707cfd | 617 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, |
a6b21831 TR |
618 | 752, 800, 0, 480, 490, 492, 525, 0, |
619 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ | |
620 | { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, | |
621 | 846, 900, 0, 400, 421, 423, 449, 0, | |
622 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ | |
623 | { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, | |
624 | 846, 900, 0, 400, 412, 414, 449, 0, | |
625 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ | |
626 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, | |
627 | 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, | |
628 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ | |
87707cfd | 629 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, |
a6b21831 TR |
630 | 1136, 1312, 0, 768, 769, 772, 800, 0, |
631 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ | |
632 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, | |
633 | 1184, 1328, 0, 768, 771, 777, 806, 0, | |
634 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ | |
635 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, | |
636 | 1184, 1344, 0, 768, 771, 777, 806, 0, | |
637 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ | |
638 | { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, | |
639 | 1208, 1264, 0, 768, 768, 776, 817, 0, | |
640 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ | |
641 | { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, | |
642 | 928, 1152, 0, 624, 625, 628, 667, 0, | |
643 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ | |
644 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, | |
645 | 896, 1056, 0, 600, 601, 604, 625, 0, | |
646 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ | |
647 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, | |
648 | 976, 1040, 0, 600, 637, 643, 666, 0, | |
649 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ | |
650 | { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, | |
651 | 1344, 1600, 0, 864, 865, 868, 900, 0, | |
652 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ | |
653 | }; | |
654 | ||
655 | struct minimode { | |
656 | short w; | |
657 | short h; | |
658 | short r; | |
659 | short rb; | |
660 | }; | |
661 | ||
662 | static const struct minimode est3_modes[] = { | |
663 | /* byte 6 */ | |
664 | { 640, 350, 85, 0 }, | |
665 | { 640, 400, 85, 0 }, | |
666 | { 720, 400, 85, 0 }, | |
667 | { 640, 480, 85, 0 }, | |
668 | { 848, 480, 60, 0 }, | |
669 | { 800, 600, 85, 0 }, | |
670 | { 1024, 768, 85, 0 }, | |
671 | { 1152, 864, 75, 0 }, | |
672 | /* byte 7 */ | |
673 | { 1280, 768, 60, 1 }, | |
674 | { 1280, 768, 60, 0 }, | |
675 | { 1280, 768, 75, 0 }, | |
676 | { 1280, 768, 85, 0 }, | |
677 | { 1280, 960, 60, 0 }, | |
678 | { 1280, 960, 85, 0 }, | |
679 | { 1280, 1024, 60, 0 }, | |
680 | { 1280, 1024, 85, 0 }, | |
681 | /* byte 8 */ | |
682 | { 1360, 768, 60, 0 }, | |
683 | { 1440, 900, 60, 1 }, | |
684 | { 1440, 900, 60, 0 }, | |
685 | { 1440, 900, 75, 0 }, | |
686 | { 1440, 900, 85, 0 }, | |
687 | { 1400, 1050, 60, 1 }, | |
688 | { 1400, 1050, 60, 0 }, | |
689 | { 1400, 1050, 75, 0 }, | |
690 | /* byte 9 */ | |
691 | { 1400, 1050, 85, 0 }, | |
692 | { 1680, 1050, 60, 1 }, | |
693 | { 1680, 1050, 60, 0 }, | |
694 | { 1680, 1050, 75, 0 }, | |
695 | { 1680, 1050, 85, 0 }, | |
696 | { 1600, 1200, 60, 0 }, | |
697 | { 1600, 1200, 65, 0 }, | |
698 | { 1600, 1200, 70, 0 }, | |
699 | /* byte 10 */ | |
700 | { 1600, 1200, 75, 0 }, | |
701 | { 1600, 1200, 85, 0 }, | |
702 | { 1792, 1344, 60, 0 }, | |
c068b32a | 703 | { 1792, 1344, 75, 0 }, |
a6b21831 TR |
704 | { 1856, 1392, 60, 0 }, |
705 | { 1856, 1392, 75, 0 }, | |
706 | { 1920, 1200, 60, 1 }, | |
707 | { 1920, 1200, 60, 0 }, | |
708 | /* byte 11 */ | |
709 | { 1920, 1200, 75, 0 }, | |
710 | { 1920, 1200, 85, 0 }, | |
711 | { 1920, 1440, 60, 0 }, | |
712 | { 1920, 1440, 75, 0 }, | |
713 | }; | |
714 | ||
715 | static const struct minimode extra_modes[] = { | |
716 | { 1024, 576, 60, 0 }, | |
717 | { 1366, 768, 60, 0 }, | |
718 | { 1600, 900, 60, 0 }, | |
719 | { 1680, 945, 60, 0 }, | |
720 | { 1920, 1080, 60, 0 }, | |
721 | { 2048, 1152, 60, 0 }, | |
722 | { 2048, 1536, 60, 0 }, | |
723 | }; | |
724 | ||
725 | /* | |
7befe621 | 726 | * From CEA/CTA-861 spec. |
d9278b4c | 727 | * |
7befe621 | 728 | * Do not access directly, instead always use cea_mode_for_vic(). |
a6b21831 | 729 | */ |
8c1b2bd9 | 730 | static const struct drm_display_mode edid_cea_modes_1[] = { |
78691960 | 731 | /* 1 - 640x480@60Hz 4:3 */ |
a6b21831 TR |
732 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, |
733 | 752, 800, 0, 480, 490, 492, 525, 0, | |
ee7925bb | 734 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
0425662f | 735 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
78691960 | 736 | /* 2 - 720x480@60Hz 4:3 */ |
a6b21831 TR |
737 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, |
738 | 798, 858, 0, 480, 489, 495, 525, 0, | |
ee7925bb | 739 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
0425662f | 740 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
78691960 | 741 | /* 3 - 720x480@60Hz 16:9 */ |
a6b21831 TR |
742 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, |
743 | 798, 858, 0, 480, 489, 495, 525, 0, | |
ee7925bb | 744 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
0425662f | 745 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
78691960 | 746 | /* 4 - 1280x720@60Hz 16:9 */ |
a6b21831 TR |
747 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, |
748 | 1430, 1650, 0, 720, 725, 730, 750, 0, | |
ee7925bb | 749 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
0425662f | 750 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
78691960 | 751 | /* 5 - 1920x1080i@60Hz 16:9 */ |
a6b21831 TR |
752 | { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, |
753 | 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, | |
754 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | | |
78691960 | 755 | DRM_MODE_FLAG_INTERLACE), |
0425662f | 756 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
78691960 | 757 | /* 6 - 720(1440)x480i@60Hz 4:3 */ |
fb01d280 CT |
758 | { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, |
759 | 801, 858, 0, 480, 488, 494, 525, 0, | |
a6b21831 | 760 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | |
78691960 | 761 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
0425662f | 762 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
78691960 | 763 | /* 7 - 720(1440)x480i@60Hz 16:9 */ |
fb01d280 CT |
764 | { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, |
765 | 801, 858, 0, 480, 488, 494, 525, 0, | |
a6b21831 | 766 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | |
78691960 | 767 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
0425662f | 768 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
78691960 | 769 | /* 8 - 720(1440)x240@60Hz 4:3 */ |
fb01d280 CT |
770 | { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, |
771 | 801, 858, 0, 240, 244, 247, 262, 0, | |
a6b21831 | 772 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | |
78691960 | 773 | DRM_MODE_FLAG_DBLCLK), |
0425662f | 774 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
78691960 | 775 | /* 9 - 720(1440)x240@60Hz 16:9 */ |
fb01d280 CT |
776 | { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, |
777 | 801, 858, 0, 240, 244, 247, 262, 0, | |
a6b21831 | 778 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | |
78691960 | 779 | DRM_MODE_FLAG_DBLCLK), |
0425662f | 780 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
78691960 | 781 | /* 10 - 2880x480i@60Hz 4:3 */ |
a6b21831 TR |
782 | { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, |
783 | 3204, 3432, 0, 480, 488, 494, 525, 0, | |
784 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | | |
78691960 | 785 | DRM_MODE_FLAG_INTERLACE), |
0425662f | 786 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
78691960 | 787 | /* 11 - 2880x480i@60Hz 16:9 */ |
a6b21831 TR |
788 | { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, |
789 | 3204, 3432, 0, 480, 488, 494, 525, 0, | |
790 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | | |
78691960 | 791 | DRM_MODE_FLAG_INTERLACE), |
0425662f | 792 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
78691960 | 793 | /* 12 - 2880x240@60Hz 4:3 */ |
a6b21831 TR |
794 | { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, |
795 | 3204, 3432, 0, 240, 244, 247, 262, 0, | |
ee7925bb | 796 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
0425662f | 797 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
78691960 | 798 | /* 13 - 2880x240@60Hz 16:9 */ |
a6b21831 TR |
799 | { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, |
800 | 3204, 3432, 0, 240, 244, 247, 262, 0, | |
ee7925bb | 801 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
0425662f | 802 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
78691960 | 803 | /* 14 - 1440x480@60Hz 4:3 */ |
a6b21831 TR |
804 | { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, |
805 | 1596, 1716, 0, 480, 489, 495, 525, 0, | |
ee7925bb | 806 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
0425662f | 807 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
78691960 | 808 | /* 15 - 1440x480@60Hz 16:9 */ |
a6b21831 TR |
809 | { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, |
810 | 1596, 1716, 0, 480, 489, 495, 525, 0, | |
ee7925bb | 811 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
0425662f | 812 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
78691960 | 813 | /* 16 - 1920x1080@60Hz 16:9 */ |
a6b21831 TR |
814 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, |
815 | 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, | |
ee7925bb | 816 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
0425662f | 817 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
78691960 | 818 | /* 17 - 720x576@50Hz 4:3 */ |
a6b21831 TR |
819 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, |
820 | 796, 864, 0, 576, 581, 586, 625, 0, | |
ee7925bb | 821 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
0425662f | 822 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
78691960 | 823 | /* 18 - 720x576@50Hz 16:9 */ |
a6b21831 TR |
824 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, |
825 | 796, 864, 0, 576, 581, 586, 625, 0, | |
ee7925bb | 826 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
0425662f | 827 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
78691960 | 828 | /* 19 - 1280x720@50Hz 16:9 */ |
a6b21831 TR |
829 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, |
830 | 1760, 1980, 0, 720, 725, 730, 750, 0, | |
ee7925bb | 831 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
0425662f | 832 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
78691960 | 833 | /* 20 - 1920x1080i@50Hz 16:9 */ |
a6b21831 TR |
834 | { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, |
835 | 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, | |
836 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | | |
78691960 | 837 | DRM_MODE_FLAG_INTERLACE), |
0425662f | 838 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
78691960 | 839 | /* 21 - 720(1440)x576i@50Hz 4:3 */ |
fb01d280 CT |
840 | { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, |
841 | 795, 864, 0, 576, 580, 586, 625, 0, | |
a6b21831 | 842 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | |
78691960 | 843 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
0425662f | 844 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
78691960 | 845 | /* 22 - 720(1440)x576i@50Hz 16:9 */ |
fb01d280 CT |
846 | { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, |
847 | 795, 864, 0, 576, 580, 586, 625, 0, | |
a6b21831 | 848 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | |
78691960 | 849 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
0425662f | 850 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
78691960 | 851 | /* 23 - 720(1440)x288@50Hz 4:3 */ |
fb01d280 CT |
852 | { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, |
853 | 795, 864, 0, 288, 290, 293, 312, 0, | |
a6b21831 | 854 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | |
78691960 | 855 | DRM_MODE_FLAG_DBLCLK), |
0425662f | 856 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
78691960 | 857 | /* 24 - 720(1440)x288@50Hz 16:9 */ |
fb01d280 CT |
858 | { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, |
859 | 795, 864, 0, 288, 290, 293, 312, 0, | |
a6b21831 | 860 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | |
78691960 | 861 | DRM_MODE_FLAG_DBLCLK), |
0425662f | 862 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
78691960 | 863 | /* 25 - 2880x576i@50Hz 4:3 */ |
a6b21831 TR |
864 | { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, |
865 | 3180, 3456, 0, 576, 580, 586, 625, 0, | |
866 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | | |
78691960 | 867 | DRM_MODE_FLAG_INTERLACE), |
0425662f | 868 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
78691960 | 869 | /* 26 - 2880x576i@50Hz 16:9 */ |
a6b21831 TR |
870 | { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, |
871 | 3180, 3456, 0, 576, 580, 586, 625, 0, | |
872 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | | |
78691960 | 873 | DRM_MODE_FLAG_INTERLACE), |
0425662f | 874 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
78691960 | 875 | /* 27 - 2880x288@50Hz 4:3 */ |
a6b21831 TR |
876 | { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, |
877 | 3180, 3456, 0, 288, 290, 293, 312, 0, | |
ee7925bb | 878 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
0425662f | 879 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
78691960 | 880 | /* 28 - 2880x288@50Hz 16:9 */ |
a6b21831 TR |
881 | { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, |
882 | 3180, 3456, 0, 288, 290, 293, 312, 0, | |
ee7925bb | 883 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
0425662f | 884 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
78691960 | 885 | /* 29 - 1440x576@50Hz 4:3 */ |
a6b21831 TR |
886 | { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, |
887 | 1592, 1728, 0, 576, 581, 586, 625, 0, | |
ee7925bb | 888 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
0425662f | 889 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
78691960 | 890 | /* 30 - 1440x576@50Hz 16:9 */ |
a6b21831 TR |
891 | { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, |
892 | 1592, 1728, 0, 576, 581, 586, 625, 0, | |
ee7925bb | 893 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
0425662f | 894 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
78691960 | 895 | /* 31 - 1920x1080@50Hz 16:9 */ |
a6b21831 TR |
896 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, |
897 | 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, | |
ee7925bb | 898 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
0425662f | 899 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
78691960 | 900 | /* 32 - 1920x1080@24Hz 16:9 */ |
a6b21831 TR |
901 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, |
902 | 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, | |
ee7925bb | 903 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
0425662f | 904 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
78691960 | 905 | /* 33 - 1920x1080@25Hz 16:9 */ |
a6b21831 TR |
906 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, |
907 | 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, | |
ee7925bb | 908 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
0425662f | 909 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
78691960 | 910 | /* 34 - 1920x1080@30Hz 16:9 */ |
a6b21831 TR |
911 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, |
912 | 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, | |
ee7925bb | 913 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
0425662f | 914 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
78691960 | 915 | /* 35 - 2880x480@60Hz 4:3 */ |
a6b21831 TR |
916 | { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, |
917 | 3192, 3432, 0, 480, 489, 495, 525, 0, | |
ee7925bb | 918 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
0425662f | 919 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
78691960 | 920 | /* 36 - 2880x480@60Hz 16:9 */ |
a6b21831 TR |
921 | { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, |
922 | 3192, 3432, 0, 480, 489, 495, 525, 0, | |
ee7925bb | 923 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
0425662f | 924 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
78691960 | 925 | /* 37 - 2880x576@50Hz 4:3 */ |
a6b21831 TR |
926 | { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, |
927 | 3184, 3456, 0, 576, 581, 586, 625, 0, | |
ee7925bb | 928 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
0425662f | 929 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
78691960 | 930 | /* 38 - 2880x576@50Hz 16:9 */ |
a6b21831 TR |
931 | { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, |
932 | 3184, 3456, 0, 576, 581, 586, 625, 0, | |
ee7925bb | 933 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
0425662f | 934 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
78691960 | 935 | /* 39 - 1920x1080i@50Hz 16:9 */ |
a6b21831 TR |
936 | { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, |
937 | 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, | |
938 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | | |
78691960 | 939 | DRM_MODE_FLAG_INTERLACE), |
0425662f | 940 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
78691960 | 941 | /* 40 - 1920x1080i@100Hz 16:9 */ |
a6b21831 TR |
942 | { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, |
943 | 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, | |
944 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | | |
78691960 | 945 | DRM_MODE_FLAG_INTERLACE), |
0425662f | 946 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
78691960 | 947 | /* 41 - 1280x720@100Hz 16:9 */ |
a6b21831 TR |
948 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, |
949 | 1760, 1980, 0, 720, 725, 730, 750, 0, | |
ee7925bb | 950 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
0425662f | 951 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
78691960 | 952 | /* 42 - 720x576@100Hz 4:3 */ |
a6b21831 TR |
953 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, |
954 | 796, 864, 0, 576, 581, 586, 625, 0, | |
ee7925bb | 955 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
0425662f | 956 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
78691960 | 957 | /* 43 - 720x576@100Hz 16:9 */ |
a6b21831 TR |
958 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, |
959 | 796, 864, 0, 576, 581, 586, 625, 0, | |
ee7925bb | 960 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
0425662f | 961 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
78691960 | 962 | /* 44 - 720(1440)x576i@100Hz 4:3 */ |
fb01d280 CT |
963 | { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, |
964 | 795, 864, 0, 576, 580, 586, 625, 0, | |
a6b21831 | 965 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | |
78691960 | 966 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
0425662f | 967 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
78691960 | 968 | /* 45 - 720(1440)x576i@100Hz 16:9 */ |
fb01d280 CT |
969 | { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, |
970 | 795, 864, 0, 576, 580, 586, 625, 0, | |
a6b21831 | 971 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | |
78691960 | 972 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
0425662f | 973 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
78691960 | 974 | /* 46 - 1920x1080i@120Hz 16:9 */ |
a6b21831 TR |
975 | { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, |
976 | 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, | |
977 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | | |
78691960 | 978 | DRM_MODE_FLAG_INTERLACE), |
0425662f | 979 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
78691960 | 980 | /* 47 - 1280x720@120Hz 16:9 */ |
a6b21831 TR |
981 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, |
982 | 1430, 1650, 0, 720, 725, 730, 750, 0, | |
ee7925bb | 983 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
0425662f | 984 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
78691960 | 985 | /* 48 - 720x480@120Hz 4:3 */ |
a6b21831 TR |
986 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, |
987 | 798, 858, 0, 480, 489, 495, 525, 0, | |
ee7925bb | 988 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
0425662f | 989 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
78691960 | 990 | /* 49 - 720x480@120Hz 16:9 */ |
a6b21831 TR |
991 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, |
992 | 798, 858, 0, 480, 489, 495, 525, 0, | |
ee7925bb | 993 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
0425662f | 994 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
78691960 | 995 | /* 50 - 720(1440)x480i@120Hz 4:3 */ |
fb01d280 CT |
996 | { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, |
997 | 801, 858, 0, 480, 488, 494, 525, 0, | |
a6b21831 | 998 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | |
78691960 | 999 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
0425662f | 1000 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
78691960 | 1001 | /* 51 - 720(1440)x480i@120Hz 16:9 */ |
fb01d280 CT |
1002 | { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, |
1003 | 801, 858, 0, 480, 488, 494, 525, 0, | |
a6b21831 | 1004 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | |
78691960 | 1005 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
0425662f | 1006 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
78691960 | 1007 | /* 52 - 720x576@200Hz 4:3 */ |
a6b21831 TR |
1008 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, |
1009 | 796, 864, 0, 576, 581, 586, 625, 0, | |
ee7925bb | 1010 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
0425662f | 1011 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
78691960 | 1012 | /* 53 - 720x576@200Hz 16:9 */ |
a6b21831 TR |
1013 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, |
1014 | 796, 864, 0, 576, 581, 586, 625, 0, | |
ee7925bb | 1015 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
0425662f | 1016 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
78691960 | 1017 | /* 54 - 720(1440)x576i@200Hz 4:3 */ |
fb01d280 CT |
1018 | { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, |
1019 | 795, 864, 0, 576, 580, 586, 625, 0, | |
a6b21831 | 1020 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | |
78691960 | 1021 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
0425662f | 1022 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
78691960 | 1023 | /* 55 - 720(1440)x576i@200Hz 16:9 */ |
fb01d280 CT |
1024 | { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, |
1025 | 795, 864, 0, 576, 580, 586, 625, 0, | |
a6b21831 | 1026 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | |
78691960 | 1027 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
0425662f | 1028 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
78691960 | 1029 | /* 56 - 720x480@240Hz 4:3 */ |
a6b21831 TR |
1030 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, |
1031 | 798, 858, 0, 480, 489, 495, 525, 0, | |
ee7925bb | 1032 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
0425662f | 1033 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
78691960 | 1034 | /* 57 - 720x480@240Hz 16:9 */ |
a6b21831 TR |
1035 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, |
1036 | 798, 858, 0, 480, 489, 495, 525, 0, | |
ee7925bb | 1037 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
0425662f | 1038 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
78691960 | 1039 | /* 58 - 720(1440)x480i@240Hz 4:3 */ |
fb01d280 CT |
1040 | { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, |
1041 | 801, 858, 0, 480, 488, 494, 525, 0, | |
a6b21831 | 1042 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | |
78691960 | 1043 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
0425662f | 1044 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
78691960 | 1045 | /* 59 - 720(1440)x480i@240Hz 16:9 */ |
fb01d280 CT |
1046 | { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, |
1047 | 801, 858, 0, 480, 488, 494, 525, 0, | |
a6b21831 | 1048 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | |
78691960 | 1049 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
0425662f | 1050 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
78691960 | 1051 | /* 60 - 1280x720@24Hz 16:9 */ |
a6b21831 TR |
1052 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, |
1053 | 3080, 3300, 0, 720, 725, 730, 750, 0, | |
ee7925bb | 1054 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
0425662f | 1055 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
78691960 | 1056 | /* 61 - 1280x720@25Hz 16:9 */ |
a6b21831 TR |
1057 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, |
1058 | 3740, 3960, 0, 720, 725, 730, 750, 0, | |
ee7925bb | 1059 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
0425662f | 1060 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
78691960 | 1061 | /* 62 - 1280x720@30Hz 16:9 */ |
a6b21831 TR |
1062 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, |
1063 | 3080, 3300, 0, 720, 725, 730, 750, 0, | |
ee7925bb | 1064 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
0425662f | 1065 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
78691960 | 1066 | /* 63 - 1920x1080@120Hz 16:9 */ |
a6b21831 TR |
1067 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, |
1068 | 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, | |
ee7925bb | 1069 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
0425662f | 1070 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
78691960 | 1071 | /* 64 - 1920x1080@100Hz 16:9 */ |
a6b21831 | 1072 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, |
8f0e4907 | 1073 | 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, |
ee7925bb | 1074 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
0425662f | 1075 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
78691960 | 1076 | /* 65 - 1280x720@24Hz 64:27 */ |
8ec6e075 SS |
1077 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, |
1078 | 3080, 3300, 0, 720, 725, 730, 750, 0, | |
1079 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1080 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
78691960 | 1081 | /* 66 - 1280x720@25Hz 64:27 */ |
8ec6e075 SS |
1082 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, |
1083 | 3740, 3960, 0, 720, 725, 730, 750, 0, | |
1084 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1085 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
78691960 | 1086 | /* 67 - 1280x720@30Hz 64:27 */ |
8ec6e075 SS |
1087 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, |
1088 | 3080, 3300, 0, 720, 725, 730, 750, 0, | |
1089 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1090 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
78691960 | 1091 | /* 68 - 1280x720@50Hz 64:27 */ |
8ec6e075 SS |
1092 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, |
1093 | 1760, 1980, 0, 720, 725, 730, 750, 0, | |
1094 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1095 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
78691960 | 1096 | /* 69 - 1280x720@60Hz 64:27 */ |
8ec6e075 SS |
1097 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, |
1098 | 1430, 1650, 0, 720, 725, 730, 750, 0, | |
1099 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1100 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
78691960 | 1101 | /* 70 - 1280x720@100Hz 64:27 */ |
8ec6e075 SS |
1102 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, |
1103 | 1760, 1980, 0, 720, 725, 730, 750, 0, | |
1104 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1105 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
78691960 | 1106 | /* 71 - 1280x720@120Hz 64:27 */ |
8ec6e075 SS |
1107 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, |
1108 | 1430, 1650, 0, 720, 725, 730, 750, 0, | |
1109 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1110 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
78691960 | 1111 | /* 72 - 1920x1080@24Hz 64:27 */ |
8ec6e075 SS |
1112 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, |
1113 | 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, | |
1114 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1115 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
78691960 | 1116 | /* 73 - 1920x1080@25Hz 64:27 */ |
8ec6e075 SS |
1117 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, |
1118 | 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, | |
1119 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1120 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
78691960 | 1121 | /* 74 - 1920x1080@30Hz 64:27 */ |
8ec6e075 SS |
1122 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, |
1123 | 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, | |
1124 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1125 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
78691960 | 1126 | /* 75 - 1920x1080@50Hz 64:27 */ |
8ec6e075 SS |
1127 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, |
1128 | 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, | |
1129 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1130 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
78691960 | 1131 | /* 76 - 1920x1080@60Hz 64:27 */ |
8ec6e075 SS |
1132 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, |
1133 | 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, | |
1134 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1135 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
78691960 | 1136 | /* 77 - 1920x1080@100Hz 64:27 */ |
8ec6e075 SS |
1137 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, |
1138 | 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, | |
1139 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1140 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
78691960 | 1141 | /* 78 - 1920x1080@120Hz 64:27 */ |
8ec6e075 SS |
1142 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, |
1143 | 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, | |
1144 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1145 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
78691960 | 1146 | /* 79 - 1680x720@24Hz 64:27 */ |
8ec6e075 SS |
1147 | { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, |
1148 | 3080, 3300, 0, 720, 725, 730, 750, 0, | |
1149 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1150 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
78691960 | 1151 | /* 80 - 1680x720@25Hz 64:27 */ |
8ec6e075 SS |
1152 | { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, |
1153 | 2948, 3168, 0, 720, 725, 730, 750, 0, | |
1154 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1155 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
78691960 | 1156 | /* 81 - 1680x720@30Hz 64:27 */ |
8ec6e075 SS |
1157 | { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, |
1158 | 2420, 2640, 0, 720, 725, 730, 750, 0, | |
1159 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1160 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
78691960 | 1161 | /* 82 - 1680x720@50Hz 64:27 */ |
8ec6e075 SS |
1162 | { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, |
1163 | 1980, 2200, 0, 720, 725, 730, 750, 0, | |
1164 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1165 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
78691960 | 1166 | /* 83 - 1680x720@60Hz 64:27 */ |
8ec6e075 SS |
1167 | { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, |
1168 | 1980, 2200, 0, 720, 725, 730, 750, 0, | |
1169 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1170 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
78691960 | 1171 | /* 84 - 1680x720@100Hz 64:27 */ |
8ec6e075 SS |
1172 | { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, |
1173 | 1780, 2000, 0, 720, 725, 730, 825, 0, | |
1174 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1175 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
78691960 | 1176 | /* 85 - 1680x720@120Hz 64:27 */ |
8ec6e075 SS |
1177 | { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, |
1178 | 1780, 2000, 0, 720, 725, 730, 825, 0, | |
1179 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1180 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
78691960 | 1181 | /* 86 - 2560x1080@24Hz 64:27 */ |
8ec6e075 SS |
1182 | { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, |
1183 | 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, | |
1184 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1185 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
78691960 | 1186 | /* 87 - 2560x1080@25Hz 64:27 */ |
8ec6e075 SS |
1187 | { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, |
1188 | 3052, 3200, 0, 1080, 1084, 1089, 1125, 0, | |
1189 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1190 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
78691960 | 1191 | /* 88 - 2560x1080@30Hz 64:27 */ |
8ec6e075 SS |
1192 | { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, |
1193 | 3372, 3520, 0, 1080, 1084, 1089, 1125, 0, | |
1194 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1195 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
78691960 | 1196 | /* 89 - 2560x1080@50Hz 64:27 */ |
8ec6e075 SS |
1197 | { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, |
1198 | 3152, 3300, 0, 1080, 1084, 1089, 1125, 0, | |
1199 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1200 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
78691960 | 1201 | /* 90 - 2560x1080@60Hz 64:27 */ |
8ec6e075 SS |
1202 | { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, |
1203 | 2852, 3000, 0, 1080, 1084, 1089, 1100, 0, | |
1204 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1205 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
78691960 | 1206 | /* 91 - 2560x1080@100Hz 64:27 */ |
8ec6e075 SS |
1207 | { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, |
1208 | 2822, 2970, 0, 1080, 1084, 1089, 1250, 0, | |
1209 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1210 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
78691960 | 1211 | /* 92 - 2560x1080@120Hz 64:27 */ |
8ec6e075 SS |
1212 | { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, |
1213 | 3152, 3300, 0, 1080, 1084, 1089, 1250, 0, | |
1214 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1215 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
78691960 | 1216 | /* 93 - 3840x2160@24Hz 16:9 */ |
8ec6e075 SS |
1217 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, |
1218 | 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, | |
1219 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1220 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
78691960 | 1221 | /* 94 - 3840x2160@25Hz 16:9 */ |
8ec6e075 SS |
1222 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, |
1223 | 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, | |
1224 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1225 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
78691960 | 1226 | /* 95 - 3840x2160@30Hz 16:9 */ |
8ec6e075 SS |
1227 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, |
1228 | 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, | |
1229 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1230 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
78691960 | 1231 | /* 96 - 3840x2160@50Hz 16:9 */ |
8ec6e075 SS |
1232 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, |
1233 | 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, | |
1234 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1235 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
78691960 | 1236 | /* 97 - 3840x2160@60Hz 16:9 */ |
8ec6e075 SS |
1237 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, |
1238 | 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, | |
1239 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1240 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
78691960 | 1241 | /* 98 - 4096x2160@24Hz 256:135 */ |
8ec6e075 SS |
1242 | { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, |
1243 | 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, | |
1244 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1245 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, |
78691960 | 1246 | /* 99 - 4096x2160@25Hz 256:135 */ |
8ec6e075 SS |
1247 | { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, |
1248 | 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, | |
1249 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1250 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, |
78691960 | 1251 | /* 100 - 4096x2160@30Hz 256:135 */ |
8ec6e075 SS |
1252 | { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, |
1253 | 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, | |
1254 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1255 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, |
78691960 | 1256 | /* 101 - 4096x2160@50Hz 256:135 */ |
8ec6e075 SS |
1257 | { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, |
1258 | 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, | |
1259 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1260 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, |
78691960 | 1261 | /* 102 - 4096x2160@60Hz 256:135 */ |
8ec6e075 SS |
1262 | { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, |
1263 | 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, | |
1264 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1265 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, |
78691960 | 1266 | /* 103 - 3840x2160@24Hz 64:27 */ |
8ec6e075 SS |
1267 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, |
1268 | 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, | |
1269 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1270 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
78691960 | 1271 | /* 104 - 3840x2160@25Hz 64:27 */ |
8ec6e075 SS |
1272 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, |
1273 | 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, | |
1274 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1275 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
78691960 | 1276 | /* 105 - 3840x2160@30Hz 64:27 */ |
8ec6e075 SS |
1277 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, |
1278 | 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, | |
1279 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1280 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
78691960 | 1281 | /* 106 - 3840x2160@50Hz 64:27 */ |
8ec6e075 SS |
1282 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, |
1283 | 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, | |
1284 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1285 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
78691960 | 1286 | /* 107 - 3840x2160@60Hz 64:27 */ |
8ec6e075 SS |
1287 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, |
1288 | 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, | |
1289 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1290 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
978f6b06 VS |
1291 | /* 108 - 1280x720@48Hz 16:9 */ |
1292 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, | |
1293 | 2280, 2500, 0, 720, 725, 730, 750, 0, | |
1294 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1295 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
978f6b06 VS |
1296 | /* 109 - 1280x720@48Hz 64:27 */ |
1297 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, | |
1298 | 2280, 2500, 0, 720, 725, 730, 750, 0, | |
1299 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1300 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
978f6b06 VS |
1301 | /* 110 - 1680x720@48Hz 64:27 */ |
1302 | { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490, | |
1303 | 2530, 2750, 0, 720, 725, 730, 750, 0, | |
1304 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1305 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
978f6b06 VS |
1306 | /* 111 - 1920x1080@48Hz 16:9 */ |
1307 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, | |
1308 | 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, | |
1309 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1310 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
978f6b06 VS |
1311 | /* 112 - 1920x1080@48Hz 64:27 */ |
1312 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, | |
1313 | 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, | |
1314 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1315 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
978f6b06 VS |
1316 | /* 113 - 2560x1080@48Hz 64:27 */ |
1317 | { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558, | |
1318 | 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, | |
1319 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1320 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
978f6b06 VS |
1321 | /* 114 - 3840x2160@48Hz 16:9 */ |
1322 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, | |
1323 | 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, | |
1324 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1325 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
978f6b06 VS |
1326 | /* 115 - 4096x2160@48Hz 256:135 */ |
1327 | { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116, | |
1328 | 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, | |
1329 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1330 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, |
978f6b06 VS |
1331 | /* 116 - 3840x2160@48Hz 64:27 */ |
1332 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, | |
1333 | 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, | |
1334 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1335 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
978f6b06 VS |
1336 | /* 117 - 3840x2160@100Hz 16:9 */ |
1337 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, | |
1338 | 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, | |
1339 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1340 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
978f6b06 VS |
1341 | /* 118 - 3840x2160@120Hz 16:9 */ |
1342 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, | |
1343 | 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, | |
1344 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1345 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
978f6b06 VS |
1346 | /* 119 - 3840x2160@100Hz 64:27 */ |
1347 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, | |
1348 | 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, | |
1349 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1350 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
978f6b06 VS |
1351 | /* 120 - 3840x2160@120Hz 64:27 */ |
1352 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, | |
1353 | 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, | |
1354 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1355 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
978f6b06 VS |
1356 | /* 121 - 5120x2160@24Hz 64:27 */ |
1357 | { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116, | |
1358 | 7204, 7500, 0, 2160, 2168, 2178, 2200, 0, | |
1359 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1360 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
978f6b06 VS |
1361 | /* 122 - 5120x2160@25Hz 64:27 */ |
1362 | { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816, | |
1363 | 6904, 7200, 0, 2160, 2168, 2178, 2200, 0, | |
1364 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1365 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
978f6b06 VS |
1366 | /* 123 - 5120x2160@30Hz 64:27 */ |
1367 | { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784, | |
1368 | 5872, 6000, 0, 2160, 2168, 2178, 2200, 0, | |
1369 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1370 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
978f6b06 VS |
1371 | /* 124 - 5120x2160@48Hz 64:27 */ |
1372 | { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866, | |
1373 | 5954, 6250, 0, 2160, 2168, 2178, 2475, 0, | |
1374 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1375 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
978f6b06 VS |
1376 | /* 125 - 5120x2160@50Hz 64:27 */ |
1377 | { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216, | |
1378 | 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, | |
1379 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1380 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
978f6b06 VS |
1381 | /* 126 - 5120x2160@60Hz 64:27 */ |
1382 | { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284, | |
1383 | 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, | |
1384 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1385 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
978f6b06 VS |
1386 | /* 127 - 5120x2160@100Hz 64:27 */ |
1387 | { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216, | |
1388 | 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, | |
1389 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1390 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
a6b21831 TR |
1391 | }; |
1392 | ||
f7655d42 VS |
1393 | /* |
1394 | * From CEA/CTA-861 spec. | |
1395 | * | |
1396 | * Do not access directly, instead always use cea_mode_for_vic(). | |
1397 | */ | |
1398 | static const struct drm_display_mode edid_cea_modes_193[] = { | |
1399 | /* 193 - 5120x2160@120Hz 64:27 */ | |
1400 | { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284, | |
1401 | 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, | |
1402 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1403 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
f7655d42 VS |
1404 | /* 194 - 7680x4320@24Hz 16:9 */ |
1405 | { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, | |
1406 | 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, | |
1407 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1408 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
f7655d42 VS |
1409 | /* 195 - 7680x4320@25Hz 16:9 */ |
1410 | { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, | |
1411 | 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, | |
1412 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1413 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
f7655d42 VS |
1414 | /* 196 - 7680x4320@30Hz 16:9 */ |
1415 | { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, | |
1416 | 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, | |
1417 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1418 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
f7655d42 VS |
1419 | /* 197 - 7680x4320@48Hz 16:9 */ |
1420 | { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, | |
1421 | 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, | |
1422 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1423 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
f7655d42 VS |
1424 | /* 198 - 7680x4320@50Hz 16:9 */ |
1425 | { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, | |
1426 | 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, | |
1427 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1428 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
f7655d42 VS |
1429 | /* 199 - 7680x4320@60Hz 16:9 */ |
1430 | { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, | |
1431 | 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, | |
1432 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1433 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
f7655d42 VS |
1434 | /* 200 - 7680x4320@100Hz 16:9 */ |
1435 | { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, | |
1436 | 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, | |
1437 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1438 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
f7655d42 VS |
1439 | /* 201 - 7680x4320@120Hz 16:9 */ |
1440 | { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, | |
1441 | 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, | |
1442 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1443 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
f7655d42 VS |
1444 | /* 202 - 7680x4320@24Hz 64:27 */ |
1445 | { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, | |
1446 | 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, | |
1447 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1448 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
f7655d42 VS |
1449 | /* 203 - 7680x4320@25Hz 64:27 */ |
1450 | { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, | |
1451 | 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, | |
1452 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1453 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
f7655d42 VS |
1454 | /* 204 - 7680x4320@30Hz 64:27 */ |
1455 | { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, | |
1456 | 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, | |
1457 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1458 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
f7655d42 VS |
1459 | /* 205 - 7680x4320@48Hz 64:27 */ |
1460 | { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, | |
1461 | 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, | |
1462 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1463 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
f7655d42 VS |
1464 | /* 206 - 7680x4320@50Hz 64:27 */ |
1465 | { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, | |
1466 | 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, | |
1467 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1468 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
f7655d42 VS |
1469 | /* 207 - 7680x4320@60Hz 64:27 */ |
1470 | { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, | |
1471 | 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, | |
1472 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1473 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
f7655d42 VS |
1474 | /* 208 - 7680x4320@100Hz 64:27 */ |
1475 | { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, | |
1476 | 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, | |
1477 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1478 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
f7655d42 VS |
1479 | /* 209 - 7680x4320@120Hz 64:27 */ |
1480 | { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, | |
1481 | 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, | |
1482 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1483 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
f7655d42 VS |
1484 | /* 210 - 10240x4320@24Hz 64:27 */ |
1485 | { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732, | |
1486 | 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, | |
1487 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1488 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
f7655d42 VS |
1489 | /* 211 - 10240x4320@25Hz 64:27 */ |
1490 | { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732, | |
1491 | 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, | |
1492 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1493 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
f7655d42 VS |
1494 | /* 212 - 10240x4320@30Hz 64:27 */ |
1495 | { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528, | |
1496 | 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, | |
1497 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1498 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
f7655d42 VS |
1499 | /* 213 - 10240x4320@48Hz 64:27 */ |
1500 | { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732, | |
1501 | 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, | |
1502 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1503 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
f7655d42 VS |
1504 | /* 214 - 10240x4320@50Hz 64:27 */ |
1505 | { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732, | |
1506 | 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, | |
1507 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1508 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
f7655d42 VS |
1509 | /* 215 - 10240x4320@60Hz 64:27 */ |
1510 | { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528, | |
1511 | 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, | |
1512 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1513 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
f7655d42 VS |
1514 | /* 216 - 10240x4320@100Hz 64:27 */ |
1515 | { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432, | |
1516 | 12608, 13200, 0, 4320, 4336, 4356, 4500, 0, | |
1517 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1518 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
f7655d42 VS |
1519 | /* 217 - 10240x4320@120Hz 64:27 */ |
1520 | { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528, | |
1521 | 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, | |
1522 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1523 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, |
f7655d42 VS |
1524 | /* 218 - 4096x2160@100Hz 256:135 */ |
1525 | { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896, | |
1526 | 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, | |
1527 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1528 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, |
f7655d42 VS |
1529 | /* 219 - 4096x2160@120Hz 256:135 */ |
1530 | { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184, | |
1531 | 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, | |
1532 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1533 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, |
f7655d42 VS |
1534 | }; |
1535 | ||
7ebe1963 | 1536 | /* |
d9278b4c | 1537 | * HDMI 1.4 4k modes. Index using the VIC. |
7ebe1963 LD |
1538 | */ |
1539 | static const struct drm_display_mode edid_4k_modes[] = { | |
d9278b4c JN |
1540 | /* 0 - dummy, VICs start at 1 */ |
1541 | { }, | |
7ebe1963 LD |
1542 | /* 1 - 3840x2160@30Hz */ |
1543 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, | |
1544 | 3840, 4016, 4104, 4400, 0, | |
1545 | 2160, 2168, 2178, 2250, 0, | |
1546 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1547 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
7ebe1963 LD |
1548 | /* 2 - 3840x2160@25Hz */ |
1549 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, | |
1550 | 3840, 4896, 4984, 5280, 0, | |
1551 | 2160, 2168, 2178, 2250, 0, | |
1552 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1553 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
7ebe1963 LD |
1554 | /* 3 - 3840x2160@24Hz */ |
1555 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, | |
1556 | 3840, 5116, 5204, 5500, 0, | |
1557 | 2160, 2168, 2178, 2250, 0, | |
1558 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1559 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
7ebe1963 LD |
1560 | /* 4 - 4096x2160@24Hz (SMPTE) */ |
1561 | { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, | |
1562 | 4096, 5116, 5204, 5500, 0, | |
1563 | 2160, 2168, 2178, 2250, 0, | |
1564 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
0425662f | 1565 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, |
7ebe1963 LD |
1566 | }; |
1567 | ||
61e57a8d | 1568 | /*** DDC fetch and block validation ***/ |
f453ba04 | 1569 | |
f1e4c916 JN |
1570 | static int edid_extension_block_count(const struct edid *edid) |
1571 | { | |
1572 | return edid->extensions; | |
1573 | } | |
1574 | ||
1575 | static int edid_block_count(const struct edid *edid) | |
1576 | { | |
1577 | return edid_extension_block_count(edid) + 1; | |
1578 | } | |
1579 | ||
1580 | static int edid_size_by_blocks(int num_blocks) | |
1581 | { | |
1582 | return num_blocks * EDID_LENGTH; | |
1583 | } | |
1584 | ||
1585 | static int edid_size(const struct edid *edid) | |
1586 | { | |
1587 | return edid_size_by_blocks(edid_block_count(edid)); | |
1588 | } | |
1589 | ||
1590 | static const void *edid_block_data(const struct edid *edid, int index) | |
1591 | { | |
1592 | BUILD_BUG_ON(sizeof(*edid) != EDID_LENGTH); | |
1593 | ||
1594 | return edid + index; | |
1595 | } | |
1596 | ||
1597 | static const void *edid_extension_block_data(const struct edid *edid, int index) | |
1598 | { | |
1599 | return edid_block_data(edid, index + 1); | |
1600 | } | |
1601 | ||
083ae056 AJ |
1602 | static const u8 edid_header[] = { |
1603 | 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 | |
1604 | }; | |
f453ba04 | 1605 | |
0a612bbd JN |
1606 | static void edid_header_fix(void *edid) |
1607 | { | |
1608 | memcpy(edid, edid_header, sizeof(edid_header)); | |
1609 | } | |
1610 | ||
db6cf833 TR |
1611 | /** |
1612 | * drm_edid_header_is_valid - sanity check the header of the base EDID block | |
5d96fc9c | 1613 | * @_edid: pointer to raw base EDID block |
db6cf833 TR |
1614 | * |
1615 | * Sanity check the header of the base EDID block. | |
1616 | * | |
1617 | * Return: 8 if the header is perfect, down to 0 if it's totally wrong. | |
051963d4 | 1618 | */ |
6d987ddd | 1619 | int drm_edid_header_is_valid(const void *_edid) |
051963d4 | 1620 | { |
6d987ddd | 1621 | const struct edid *edid = _edid; |
051963d4 TR |
1622 | int i, score = 0; |
1623 | ||
6d987ddd JN |
1624 | for (i = 0; i < sizeof(edid_header); i++) { |
1625 | if (edid->header[i] == edid_header[i]) | |
051963d4 | 1626 | score++; |
6d987ddd | 1627 | } |
051963d4 TR |
1628 | |
1629 | return score; | |
1630 | } | |
1631 | EXPORT_SYMBOL(drm_edid_header_is_valid); | |
1632 | ||
47819ba2 AJ |
1633 | static int edid_fixup __read_mostly = 6; |
1634 | module_param_named(edid_fixup, edid_fixup, int, 0400); | |
1635 | MODULE_PARM_DESC(edid_fixup, | |
1636 | "Minimum number of valid EDID header bytes (0-8, default 6)"); | |
051963d4 | 1637 | |
70e49ebe | 1638 | static int edid_block_compute_checksum(const void *_block) |
c465bbc8 | 1639 | { |
70e49ebe | 1640 | const u8 *block = _block; |
c465bbc8 | 1641 | int i; |
e11f5bd8 JFZ |
1642 | u8 csum = 0, crc = 0; |
1643 | ||
1644 | for (i = 0; i < EDID_LENGTH - 1; i++) | |
70e49ebe | 1645 | csum += block[i]; |
c465bbc8 | 1646 | |
e11f5bd8 JFZ |
1647 | crc = 0x100 - csum; |
1648 | ||
1649 | return crc; | |
1650 | } | |
1651 | ||
70e49ebe | 1652 | static int edid_block_get_checksum(const void *_block) |
e11f5bd8 | 1653 | { |
70e49ebe JN |
1654 | const struct edid *block = _block; |
1655 | ||
1656 | return block->checksum; | |
c465bbc8 SB |
1657 | } |
1658 | ||
4ba0f53c JN |
1659 | static int edid_block_tag(const void *_block) |
1660 | { | |
1661 | const u8 *block = _block; | |
1662 | ||
1663 | return block[0]; | |
1664 | } | |
1665 | ||
8baccb27 | 1666 | static bool edid_block_is_zero(const void *edid) |
d6885d65 | 1667 | { |
8baccb27 | 1668 | return !memchr_inv(edid, 0, EDID_LENGTH); |
d6885d65 SB |
1669 | } |
1670 | ||
536faa45 SL |
1671 | /** |
1672 | * drm_edid_are_equal - compare two edid blobs. | |
1673 | * @edid1: pointer to first blob | |
1674 | * @edid2: pointer to second blob | |
1675 | * This helper can be used during probing to determine if | |
1676 | * edid had changed. | |
1677 | */ | |
1678 | bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2) | |
1679 | { | |
1680 | int edid1_len, edid2_len; | |
1681 | bool edid1_present = edid1 != NULL; | |
1682 | bool edid2_present = edid2 != NULL; | |
1683 | ||
1684 | if (edid1_present != edid2_present) | |
1685 | return false; | |
1686 | ||
1687 | if (edid1) { | |
f1e4c916 JN |
1688 | edid1_len = edid_size(edid1); |
1689 | edid2_len = edid_size(edid2); | |
536faa45 SL |
1690 | |
1691 | if (edid1_len != edid2_len) | |
1692 | return false; | |
1693 | ||
1694 | if (memcmp(edid1, edid2, edid1_len)) | |
1695 | return false; | |
1696 | } | |
1697 | ||
1698 | return true; | |
1699 | } | |
1700 | EXPORT_SYMBOL(drm_edid_are_equal); | |
1701 | ||
1f221284 JN |
1702 | enum edid_block_status { |
1703 | EDID_BLOCK_OK = 0, | |
2deaf1c2 | 1704 | EDID_BLOCK_READ_FAIL, |
1f221284 | 1705 | EDID_BLOCK_NULL, |
49dc0558 | 1706 | EDID_BLOCK_ZERO, |
1f221284 JN |
1707 | EDID_BLOCK_HEADER_CORRUPT, |
1708 | EDID_BLOCK_HEADER_REPAIR, | |
1709 | EDID_BLOCK_HEADER_FIXED, | |
1710 | EDID_BLOCK_CHECKSUM, | |
1711 | EDID_BLOCK_VERSION, | |
1712 | }; | |
1713 | ||
1714 | static enum edid_block_status edid_block_check(const void *_block, | |
1715 | bool is_base_block) | |
1716 | { | |
1717 | const struct edid *block = _block; | |
1718 | ||
1719 | if (!block) | |
1720 | return EDID_BLOCK_NULL; | |
1721 | ||
1722 | if (is_base_block) { | |
1723 | int score = drm_edid_header_is_valid(block); | |
1724 | ||
49dc0558 JN |
1725 | if (score < clamp(edid_fixup, 0, 8)) { |
1726 | if (edid_block_is_zero(block)) | |
1727 | return EDID_BLOCK_ZERO; | |
1728 | else | |
1729 | return EDID_BLOCK_HEADER_CORRUPT; | |
1730 | } | |
1f221284 JN |
1731 | |
1732 | if (score < 8) | |
1733 | return EDID_BLOCK_HEADER_REPAIR; | |
1734 | } | |
1735 | ||
49dc0558 JN |
1736 | if (edid_block_compute_checksum(block) != edid_block_get_checksum(block)) { |
1737 | if (edid_block_is_zero(block)) | |
1738 | return EDID_BLOCK_ZERO; | |
1739 | else | |
1740 | return EDID_BLOCK_CHECKSUM; | |
1741 | } | |
1f221284 JN |
1742 | |
1743 | if (is_base_block) { | |
1744 | if (block->version != 1) | |
1745 | return EDID_BLOCK_VERSION; | |
1746 | } | |
1747 | ||
1748 | return EDID_BLOCK_OK; | |
1749 | } | |
1750 | ||
1751 | static bool edid_block_status_valid(enum edid_block_status status, int tag) | |
1752 | { | |
1753 | return status == EDID_BLOCK_OK || | |
1754 | status == EDID_BLOCK_HEADER_FIXED || | |
1755 | (status == EDID_BLOCK_CHECKSUM && tag == CEA_EXT); | |
1756 | } | |
1757 | ||
23e38d7b JN |
1758 | static bool edid_block_valid(const void *block, bool base) |
1759 | { | |
1760 | return edid_block_status_valid(edid_block_check(block, base), | |
1761 | edid_block_tag(block)); | |
1762 | } | |
1763 | ||
cee2ce1a JN |
1764 | static void edid_block_status_print(enum edid_block_status status, |
1765 | const struct edid *block, | |
1766 | int block_num) | |
1767 | { | |
1768 | switch (status) { | |
1769 | case EDID_BLOCK_OK: | |
1770 | break; | |
2deaf1c2 JN |
1771 | case EDID_BLOCK_READ_FAIL: |
1772 | pr_debug("EDID block %d read failed\n", block_num); | |
1773 | break; | |
cee2ce1a JN |
1774 | case EDID_BLOCK_NULL: |
1775 | pr_debug("EDID block %d pointer is NULL\n", block_num); | |
1776 | break; | |
1777 | case EDID_BLOCK_ZERO: | |
1778 | pr_notice("EDID block %d is all zeroes\n", block_num); | |
1779 | break; | |
1780 | case EDID_BLOCK_HEADER_CORRUPT: | |
1781 | pr_notice("EDID has corrupt header\n"); | |
1782 | break; | |
1783 | case EDID_BLOCK_HEADER_REPAIR: | |
1784 | pr_debug("EDID corrupt header needs repair\n"); | |
1785 | break; | |
1786 | case EDID_BLOCK_HEADER_FIXED: | |
1787 | pr_debug("EDID corrupt header fixed\n"); | |
1788 | break; | |
1789 | case EDID_BLOCK_CHECKSUM: | |
1790 | if (edid_block_status_valid(status, edid_block_tag(block))) { | |
1791 | pr_debug("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d, ignoring\n", | |
1792 | block_num, edid_block_tag(block), | |
1793 | edid_block_compute_checksum(block)); | |
1794 | } else { | |
1795 | pr_notice("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d\n", | |
1796 | block_num, edid_block_tag(block), | |
1797 | edid_block_compute_checksum(block)); | |
1798 | } | |
1799 | break; | |
1800 | case EDID_BLOCK_VERSION: | |
1801 | pr_notice("EDID has major version %d, instead of 1\n", | |
1802 | block->version); | |
1803 | break; | |
1804 | default: | |
1805 | WARN(1, "EDID block %d unknown edid block status code %d\n", | |
1806 | block_num, status); | |
1807 | break; | |
1808 | } | |
1809 | } | |
1810 | ||
9c7345de JN |
1811 | static void edid_block_dump(const char *level, const void *block, int block_num) |
1812 | { | |
1813 | enum edid_block_status status; | |
1814 | char prefix[20]; | |
1815 | ||
1816 | status = edid_block_check(block, block_num == 0); | |
1817 | if (status == EDID_BLOCK_ZERO) | |
1818 | sprintf(prefix, "\t[%02x] ZERO ", block_num); | |
1819 | else if (!edid_block_status_valid(status, edid_block_tag(block))) | |
1820 | sprintf(prefix, "\t[%02x] BAD ", block_num); | |
1821 | else | |
1822 | sprintf(prefix, "\t[%02x] GOOD ", block_num); | |
1823 | ||
1824 | print_hex_dump(level, prefix, DUMP_PREFIX_NONE, 16, 1, | |
1825 | block, EDID_LENGTH, false); | |
1826 | } | |
1827 | ||
db6cf833 TR |
1828 | /** |
1829 | * drm_edid_block_valid - Sanity check the EDID block (base or extension) | |
5d96fc9c | 1830 | * @_block: pointer to raw EDID block |
1f221284 | 1831 | * @block_num: type of block to validate (0 for base, extension otherwise) |
db6cf833 | 1832 | * @print_bad_edid: if true, dump bad EDID blocks to the console |
6ba2bd3d | 1833 | * @edid_corrupt: if true, the header or checksum is invalid |
db6cf833 TR |
1834 | * |
1835 | * Validate a base or extension EDID block and optionally dump bad blocks to | |
1836 | * the console. | |
1837 | * | |
1838 | * Return: True if the block is valid, false otherwise. | |
f453ba04 | 1839 | */ |
1f221284 | 1840 | bool drm_edid_block_valid(u8 *_block, int block_num, bool print_bad_edid, |
6ba2bd3d | 1841 | bool *edid_corrupt) |
f453ba04 | 1842 | { |
1f221284 JN |
1843 | struct edid *block = (struct edid *)_block; |
1844 | enum edid_block_status status; | |
1845 | bool is_base_block = block_num == 0; | |
1846 | bool valid; | |
f453ba04 | 1847 | |
1f221284 | 1848 | if (WARN_ON(!block)) |
fe2ef780 SWK |
1849 | return false; |
1850 | ||
1f221284 JN |
1851 | status = edid_block_check(block, is_base_block); |
1852 | if (status == EDID_BLOCK_HEADER_REPAIR) { | |
1853 | DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); | |
1854 | edid_header_fix(block); | |
1855 | ||
1856 | /* Retry with fixed header, update status if that worked. */ | |
1857 | status = edid_block_check(block, is_base_block); | |
1858 | if (status == EDID_BLOCK_OK) | |
1859 | status = EDID_BLOCK_HEADER_FIXED; | |
61e57a8d | 1860 | } |
f453ba04 | 1861 | |
1f221284 JN |
1862 | if (edid_corrupt) { |
1863 | /* | |
1864 | * Unknown major version isn't corrupt but we can't use it. Only | |
1865 | * the base block can reset edid_corrupt to false. | |
1866 | */ | |
1867 | if (is_base_block && | |
1868 | (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION)) | |
1869 | *edid_corrupt = false; | |
1870 | else if (status != EDID_BLOCK_OK) | |
ac6f2e29 | 1871 | *edid_corrupt = true; |
f453ba04 DA |
1872 | } |
1873 | ||
cee2ce1a JN |
1874 | edid_block_status_print(status, block, block_num); |
1875 | ||
1f221284 JN |
1876 | /* Determine whether we can use this block with this status. */ |
1877 | valid = edid_block_status_valid(status, edid_block_tag(block)); | |
1878 | ||
cee2ce1a JN |
1879 | if (!valid && print_bad_edid && status != EDID_BLOCK_ZERO) { |
1880 | pr_notice("Raw EDID:\n"); | |
9c7345de | 1881 | edid_block_dump(KERN_NOTICE, block, block_num); |
f453ba04 | 1882 | } |
1f221284 JN |
1883 | |
1884 | return valid; | |
f453ba04 | 1885 | } |
da0df92b | 1886 | EXPORT_SYMBOL(drm_edid_block_valid); |
61e57a8d AJ |
1887 | |
1888 | /** | |
1889 | * drm_edid_is_valid - sanity check EDID data | |
1890 | * @edid: EDID data | |
1891 | * | |
1892 | * Sanity-check an entire EDID record (including extensions) | |
db6cf833 TR |
1893 | * |
1894 | * Return: True if the EDID data is valid, false otherwise. | |
61e57a8d AJ |
1895 | */ |
1896 | bool drm_edid_is_valid(struct edid *edid) | |
1897 | { | |
1898 | int i; | |
61e57a8d AJ |
1899 | |
1900 | if (!edid) | |
1901 | return false; | |
1902 | ||
f1e4c916 JN |
1903 | for (i = 0; i < edid_block_count(edid); i++) { |
1904 | void *block = (void *)edid_block_data(edid, i); | |
1905 | ||
1906 | if (!drm_edid_block_valid(block, i, true, NULL)) | |
61e57a8d | 1907 | return false; |
f1e4c916 | 1908 | } |
61e57a8d AJ |
1909 | |
1910 | return true; | |
1911 | } | |
3c537889 | 1912 | EXPORT_SYMBOL(drm_edid_is_valid); |
f453ba04 | 1913 | |
4ec53461 | 1914 | static struct edid *edid_filter_invalid_blocks(const struct edid *edid, |
ccc97def | 1915 | int invalid_blocks) |
4ec53461 JN |
1916 | { |
1917 | struct edid *new, *dest_block; | |
ccc97def | 1918 | int valid_extensions = edid->extensions - invalid_blocks; |
4ec53461 JN |
1919 | int i; |
1920 | ||
f1e4c916 | 1921 | new = kmalloc(edid_size_by_blocks(valid_extensions + 1), GFP_KERNEL); |
4ec53461 JN |
1922 | if (!new) |
1923 | goto out; | |
1924 | ||
1925 | dest_block = new; | |
f1e4c916 JN |
1926 | for (i = 0; i < edid_block_count(edid); i++) { |
1927 | const void *block = edid_block_data(edid, i); | |
4ec53461 JN |
1928 | |
1929 | if (edid_block_valid(block, i == 0)) | |
1930 | memcpy(dest_block++, block, EDID_LENGTH); | |
1931 | } | |
1932 | ||
4ec53461 | 1933 | new->extensions = valid_extensions; |
ab0609a5 | 1934 | new->checksum = edid_block_compute_checksum(new); |
4ec53461 JN |
1935 | |
1936 | out: | |
1937 | kfree(edid); | |
1938 | ||
1939 | return new; | |
1940 | } | |
1941 | ||
61e57a8d AJ |
1942 | #define DDC_SEGMENT_ADDR 0x30 |
1943 | /** | |
db6cf833 | 1944 | * drm_do_probe_ddc_edid() - get EDID information via I2C |
7c58e87e | 1945 | * @data: I2C device adapter |
fc66811c DV |
1946 | * @buf: EDID data buffer to be filled |
1947 | * @block: 128 byte EDID block to start fetching from | |
1948 | * @len: EDID data buffer length to fetch | |
1949 | * | |
db6cf833 | 1950 | * Try to fetch EDID information by calling I2C driver functions. |
61e57a8d | 1951 | * |
db6cf833 | 1952 | * Return: 0 on success or -1 on failure. |
61e57a8d AJ |
1953 | */ |
1954 | static int | |
18df89fe | 1955 | drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) |
61e57a8d | 1956 | { |
18df89fe | 1957 | struct i2c_adapter *adapter = data; |
61e57a8d | 1958 | unsigned char start = block * EDID_LENGTH; |
cd004b3f S |
1959 | unsigned char segment = block >> 1; |
1960 | unsigned char xfers = segment ? 3 : 2; | |
4819d2e4 CW |
1961 | int ret, retries = 5; |
1962 | ||
db6cf833 TR |
1963 | /* |
1964 | * The core I2C driver will automatically retry the transfer if the | |
4819d2e4 CW |
1965 | * adapter reports EAGAIN. However, we find that bit-banging transfers |
1966 | * are susceptible to errors under a heavily loaded machine and | |
1967 | * generate spurious NAKs and timeouts. Retrying the transfer | |
1968 | * of the individual block a few times seems to overcome this. | |
1969 | */ | |
1970 | do { | |
1971 | struct i2c_msg msgs[] = { | |
1972 | { | |
cd004b3f S |
1973 | .addr = DDC_SEGMENT_ADDR, |
1974 | .flags = 0, | |
1975 | .len = 1, | |
1976 | .buf = &segment, | |
1977 | }, { | |
4819d2e4 CW |
1978 | .addr = DDC_ADDR, |
1979 | .flags = 0, | |
1980 | .len = 1, | |
1981 | .buf = &start, | |
1982 | }, { | |
1983 | .addr = DDC_ADDR, | |
1984 | .flags = I2C_M_RD, | |
1985 | .len = len, | |
1986 | .buf = buf, | |
1987 | } | |
1988 | }; | |
cd004b3f | 1989 | |
db6cf833 TR |
1990 | /* |
1991 | * Avoid sending the segment addr to not upset non-compliant | |
1992 | * DDC monitors. | |
1993 | */ | |
cd004b3f S |
1994 | ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); |
1995 | ||
9292f37e ED |
1996 | if (ret == -ENXIO) { |
1997 | DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", | |
1998 | adapter->name); | |
1999 | break; | |
2000 | } | |
cd004b3f | 2001 | } while (ret != xfers && --retries); |
4819d2e4 | 2002 | |
cd004b3f | 2003 | return ret == xfers ? 0 : -1; |
61e57a8d AJ |
2004 | } |
2005 | ||
14544d09 | 2006 | static void connector_bad_edid(struct drm_connector *connector, |
63cae081 | 2007 | const struct edid *edid, int num_blocks) |
14544d09 CW |
2008 | { |
2009 | int i; | |
97794170 DA |
2010 | u8 last_block; |
2011 | ||
2012 | /* | |
2013 | * 0x7e in the EDID is the number of extension blocks. The EDID | |
2014 | * is 1 (base block) + num_ext_blocks big. That means we can think | |
2015 | * of 0x7e in the EDID of the _index_ of the last block in the | |
2016 | * combined chunk of memory. | |
2017 | */ | |
63cae081 | 2018 | last_block = edid->extensions; |
e11f5bd8 JFZ |
2019 | |
2020 | /* Calculate real checksum for the last edid extension block data */ | |
97794170 DA |
2021 | if (last_block < num_blocks) |
2022 | connector->real_edid_checksum = | |
63cae081 | 2023 | edid_block_compute_checksum(edid + last_block); |
14544d09 | 2024 | |
f0a8f533 | 2025 | if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS)) |
14544d09 CW |
2026 | return; |
2027 | ||
fa3bfa35 | 2028 | drm_dbg_kms(connector->dev, "%s: EDID is invalid:\n", connector->name); |
63cae081 JN |
2029 | for (i = 0; i < num_blocks; i++) |
2030 | edid_block_dump(KERN_DEBUG, edid + i, i); | |
14544d09 CW |
2031 | } |
2032 | ||
56a2b7f2 JN |
2033 | /* Get override or firmware EDID */ |
2034 | static struct edid *drm_get_override_edid(struct drm_connector *connector) | |
2035 | { | |
2036 | struct edid *override = NULL; | |
2037 | ||
2038 | if (connector->override_edid) | |
2039 | override = drm_edid_duplicate(connector->edid_blob_ptr->data); | |
2040 | ||
2041 | if (!override) | |
2042 | override = drm_load_edid_firmware(connector); | |
2043 | ||
2044 | return IS_ERR(override) ? NULL : override; | |
2045 | } | |
2046 | ||
48eaeb76 JN |
2047 | /** |
2048 | * drm_add_override_edid_modes - add modes from override/firmware EDID | |
2049 | * @connector: connector we're probing | |
2050 | * | |
2051 | * Add modes from the override/firmware EDID, if available. Only to be used from | |
2052 | * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe | |
2053 | * failed during drm_get_edid() and caused the override/firmware EDID to be | |
2054 | * skipped. | |
2055 | * | |
2056 | * Return: The number of modes added or 0 if we couldn't find any. | |
2057 | */ | |
2058 | int drm_add_override_edid_modes(struct drm_connector *connector) | |
2059 | { | |
2060 | struct edid *override; | |
2061 | int num_modes = 0; | |
2062 | ||
2063 | override = drm_get_override_edid(connector); | |
2064 | if (override) { | |
2065 | drm_connector_update_edid_property(connector, override); | |
2066 | num_modes = drm_add_edid_modes(connector, override); | |
2067 | kfree(override); | |
2068 | ||
2069 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n", | |
2070 | connector->base.id, connector->name, num_modes); | |
2071 | } | |
2072 | ||
2073 | return num_modes; | |
2074 | } | |
2075 | EXPORT_SYMBOL(drm_add_override_edid_modes); | |
2076 | ||
89fb7536 JN |
2077 | typedef int read_block_fn(void *context, u8 *buf, unsigned int block, size_t len); |
2078 | ||
2deaf1c2 JN |
2079 | static enum edid_block_status edid_block_read(void *block, unsigned int block_num, |
2080 | read_block_fn read_block, | |
2081 | void *context) | |
2082 | { | |
2083 | enum edid_block_status status; | |
2084 | bool is_base_block = block_num == 0; | |
2085 | int try; | |
2086 | ||
2087 | for (try = 0; try < 4; try++) { | |
2088 | if (read_block(context, block, block_num, EDID_LENGTH)) | |
2089 | return EDID_BLOCK_READ_FAIL; | |
2090 | ||
2091 | status = edid_block_check(block, is_base_block); | |
2092 | if (status == EDID_BLOCK_HEADER_REPAIR) { | |
2093 | edid_header_fix(block); | |
2094 | ||
2095 | /* Retry with fixed header, update status if that worked. */ | |
2096 | status = edid_block_check(block, is_base_block); | |
2097 | if (status == EDID_BLOCK_OK) | |
2098 | status = EDID_BLOCK_HEADER_FIXED; | |
2099 | } | |
2100 | ||
2101 | if (edid_block_status_valid(status, edid_block_tag(block))) | |
2102 | break; | |
2103 | ||
2104 | /* Fail early for unrepairable base block all zeros. */ | |
2105 | if (try == 0 && is_base_block && status == EDID_BLOCK_ZERO) | |
2106 | break; | |
2107 | } | |
2108 | ||
2109 | return status; | |
2110 | } | |
2111 | ||
18df89fe LPC |
2112 | /** |
2113 | * drm_do_get_edid - get EDID data using a custom EDID block read function | |
2114 | * @connector: connector we're probing | |
5d96fc9c JN |
2115 | * @read_block: EDID block read function |
2116 | * @context: private data passed to the block read function | |
18df89fe LPC |
2117 | * |
2118 | * When the I2C adapter connected to the DDC bus is hidden behind a device that | |
2119 | * exposes a different interface to read EDID blocks this function can be used | |
2120 | * to get EDID data using a custom block read function. | |
2121 | * | |
2122 | * As in the general case the DDC bus is accessible by the kernel at the I2C | |
2123 | * level, drivers must make all reasonable efforts to expose it as an I2C | |
2124 | * adapter and use drm_get_edid() instead of abusing this function. | |
2125 | * | |
0ae865ef | 2126 | * The EDID may be overridden using debugfs override_edid or firmware EDID |
53fd40a9 JN |
2127 | * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority |
2128 | * order. Having either of them bypasses actual EDID reads. | |
2129 | * | |
18df89fe LPC |
2130 | * Return: Pointer to valid EDID or NULL if we couldn't find any. |
2131 | */ | |
2132 | struct edid *drm_do_get_edid(struct drm_connector *connector, | |
89fb7536 JN |
2133 | read_block_fn read_block, |
2134 | void *context) | |
61e57a8d | 2135 | { |
c12561ce | 2136 | enum edid_block_status status; |
f1e4c916 | 2137 | int i, invalid_blocks = 0; |
b3eb97b6 | 2138 | struct edid *edid, *new; |
53fd40a9 | 2139 | |
b3eb97b6 JN |
2140 | edid = drm_get_override_edid(connector); |
2141 | if (edid) | |
1c788f69 | 2142 | goto ok; |
61e57a8d | 2143 | |
c12561ce | 2144 | edid = kmalloc(EDID_LENGTH, GFP_KERNEL); |
e7bd95a7 | 2145 | if (!edid) |
61e57a8d | 2146 | return NULL; |
61e57a8d | 2147 | |
c12561ce JN |
2148 | status = edid_block_read(edid, 0, read_block, context); |
2149 | ||
2150 | edid_block_status_print(status, edid, 0); | |
2151 | ||
2152 | if (status == EDID_BLOCK_READ_FAIL) | |
1c788f69 | 2153 | goto fail; |
c12561ce JN |
2154 | |
2155 | /* FIXME: Clarify what a corrupt EDID actually means. */ | |
2156 | if (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION) | |
2157 | connector->edid_corrupt = false; | |
2158 | else | |
2159 | connector->edid_corrupt = true; | |
2160 | ||
2161 | if (!edid_block_status_valid(status, edid_block_tag(edid))) { | |
2162 | if (status == EDID_BLOCK_ZERO) | |
2163 | connector->null_edid_counter++; | |
2164 | ||
2165 | connector_bad_edid(connector, edid, 1); | |
1c788f69 | 2166 | goto fail; |
c12561ce JN |
2167 | } |
2168 | ||
f1e4c916 | 2169 | if (!edid_extension_block_count(edid)) |
1c788f69 | 2170 | goto ok; |
61e57a8d | 2171 | |
f1e4c916 | 2172 | new = krealloc(edid, edid_size(edid), GFP_KERNEL); |
61e57a8d | 2173 | if (!new) |
1c788f69 | 2174 | goto fail; |
f14f3686 | 2175 | edid = new; |
61e57a8d | 2176 | |
f1e4c916 JN |
2177 | for (i = 1; i < edid_block_count(edid); i++) { |
2178 | void *block = (void *)edid_block_data(edid, i); | |
a28187cc | 2179 | |
f1e4c916 | 2180 | status = edid_block_read(block, i, read_block, context); |
d3da3f40 | 2181 | |
f1e4c916 | 2182 | edid_block_status_print(status, block, i); |
f934ec8c | 2183 | |
d3da3f40 JN |
2184 | if (!edid_block_status_valid(status, edid_block_tag(block))) { |
2185 | if (status == EDID_BLOCK_READ_FAIL) | |
1c788f69 | 2186 | goto fail; |
ccc97def | 2187 | invalid_blocks++; |
d3da3f40 | 2188 | } |
0ea75e23 ST |
2189 | } |
2190 | ||
ccc97def | 2191 | if (invalid_blocks) { |
f1e4c916 | 2192 | connector_bad_edid(connector, edid, edid_block_count(edid)); |
14544d09 | 2193 | |
ccc97def | 2194 | edid = edid_filter_invalid_blocks(edid, invalid_blocks); |
61e57a8d AJ |
2195 | } |
2196 | ||
1c788f69 | 2197 | ok: |
e9a9e076 | 2198 | return edid; |
61e57a8d | 2199 | |
1c788f69 | 2200 | fail: |
f14f3686 | 2201 | kfree(edid); |
61e57a8d AJ |
2202 | return NULL; |
2203 | } | |
18df89fe | 2204 | EXPORT_SYMBOL_GPL(drm_do_get_edid); |
61e57a8d AJ |
2205 | |
2206 | /** | |
db6cf833 TR |
2207 | * drm_probe_ddc() - probe DDC presence |
2208 | * @adapter: I2C adapter to probe | |
fc66811c | 2209 | * |
db6cf833 | 2210 | * Return: True on success, false on failure. |
61e57a8d | 2211 | */ |
fbff4690 | 2212 | bool |
61e57a8d AJ |
2213 | drm_probe_ddc(struct i2c_adapter *adapter) |
2214 | { | |
2215 | unsigned char out; | |
2216 | ||
2217 | return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); | |
2218 | } | |
fbff4690 | 2219 | EXPORT_SYMBOL(drm_probe_ddc); |
61e57a8d AJ |
2220 | |
2221 | /** | |
2222 | * drm_get_edid - get EDID data, if available | |
2223 | * @connector: connector we're probing | |
db6cf833 | 2224 | * @adapter: I2C adapter to use for DDC |
61e57a8d | 2225 | * |
db6cf833 | 2226 | * Poke the given I2C channel to grab EDID data if possible. If found, |
61e57a8d AJ |
2227 | * attach it to the connector. |
2228 | * | |
db6cf833 | 2229 | * Return: Pointer to valid EDID or NULL if we couldn't find any. |
61e57a8d AJ |
2230 | */ |
2231 | struct edid *drm_get_edid(struct drm_connector *connector, | |
2232 | struct i2c_adapter *adapter) | |
2233 | { | |
5186421c SL |
2234 | struct edid *edid; |
2235 | ||
15f080f0 JN |
2236 | if (connector->force == DRM_FORCE_OFF) |
2237 | return NULL; | |
2238 | ||
2239 | if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) | |
18df89fe | 2240 | return NULL; |
61e57a8d | 2241 | |
5186421c SL |
2242 | edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter); |
2243 | drm_connector_update_edid_property(connector, edid); | |
2244 | return edid; | |
61e57a8d AJ |
2245 | } |
2246 | EXPORT_SYMBOL(drm_get_edid); | |
2247 | ||
d9f91a10 DA |
2248 | static u32 edid_extract_panel_id(const struct edid *edid) |
2249 | { | |
2250 | /* | |
e8de4d55 DA |
2251 | * We represent the ID as a 32-bit number so it can easily be compared |
2252 | * with "==". | |
d9f91a10 DA |
2253 | * |
2254 | * NOTE that we deal with endianness differently for the top half | |
2255 | * of this ID than for the bottom half. The bottom half (the product | |
2256 | * id) gets decoded as little endian by the EDID_PRODUCT_ID because | |
2257 | * that's how everyone seems to interpret it. The top half (the mfg_id) | |
2258 | * gets stored as big endian because that makes | |
2259 | * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier | |
2260 | * to write (it's easier to extract the ASCII). It doesn't really | |
2261 | * matter, though, as long as the number here is unique. | |
2262 | */ | |
2263 | return (u32)edid->mfg_id[0] << 24 | | |
2264 | (u32)edid->mfg_id[1] << 16 | | |
2265 | (u32)EDID_PRODUCT_ID(edid); | |
2266 | } | |
2267 | ||
2268 | /** | |
2269 | * drm_edid_get_panel_id - Get a panel's ID through DDC | |
2270 | * @adapter: I2C adapter to use for DDC | |
2271 | * | |
2272 | * This function reads the first block of the EDID of a panel and (assuming | |
2273 | * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value | |
2274 | * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's | |
2275 | * supposed to be different for each different modem of panel. | |
2276 | * | |
2277 | * This function is intended to be used during early probing on devices where | |
2278 | * more than one panel might be present. Because of its intended use it must | |
2279 | * assume that the EDID of the panel is correct, at least as far as the ID | |
2280 | * is concerned (in other words, we don't process any overrides here). | |
2281 | * | |
2282 | * NOTE: it's expected that this function and drm_do_get_edid() will both | |
2283 | * be read the EDID, but there is no caching between them. Since we're only | |
2284 | * reading the first block, hopefully this extra overhead won't be too big. | |
2285 | * | |
2286 | * Return: A 32-bit ID that should be different for each make/model of panel. | |
2287 | * See the functions drm_edid_encode_panel_id() and | |
2288 | * drm_edid_decode_panel_id() for some details on the structure of this | |
2289 | * ID. | |
2290 | */ | |
2291 | ||
2292 | u32 drm_edid_get_panel_id(struct i2c_adapter *adapter) | |
2293 | { | |
2deaf1c2 JN |
2294 | enum edid_block_status status; |
2295 | void *base_block; | |
2296 | u32 panel_id = 0; | |
d9f91a10 DA |
2297 | |
2298 | /* | |
2299 | * There are no manufacturer IDs of 0, so if there is a problem reading | |
2300 | * the EDID then we'll just return 0. | |
2301 | */ | |
2deaf1c2 JN |
2302 | |
2303 | base_block = kmalloc(EDID_LENGTH, GFP_KERNEL); | |
2304 | if (!base_block) | |
d9f91a10 DA |
2305 | return 0; |
2306 | ||
2deaf1c2 JN |
2307 | status = edid_block_read(base_block, 0, drm_do_probe_ddc_edid, adapter); |
2308 | ||
2309 | edid_block_status_print(status, base_block, 0); | |
2310 | ||
2311 | if (edid_block_status_valid(status, edid_block_tag(base_block))) | |
2312 | panel_id = edid_extract_panel_id(base_block); | |
2313 | ||
2314 | kfree(base_block); | |
d9f91a10 DA |
2315 | |
2316 | return panel_id; | |
2317 | } | |
2318 | EXPORT_SYMBOL(drm_edid_get_panel_id); | |
2319 | ||
5cb8eaa2 LW |
2320 | /** |
2321 | * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output | |
2322 | * @connector: connector we're probing | |
2323 | * @adapter: I2C adapter to use for DDC | |
2324 | * | |
2325 | * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of | |
2326 | * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily | |
2327 | * switch DDC to the GPU which is retrieving EDID. | |
2328 | * | |
2329 | * Return: Pointer to valid EDID or %NULL if we couldn't find any. | |
2330 | */ | |
2331 | struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, | |
2332 | struct i2c_adapter *adapter) | |
2333 | { | |
36b73b05 TZ |
2334 | struct drm_device *dev = connector->dev; |
2335 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
5cb8eaa2 LW |
2336 | struct edid *edid; |
2337 | ||
36b73b05 TZ |
2338 | if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev))) |
2339 | return NULL; | |
2340 | ||
5cb8eaa2 LW |
2341 | vga_switcheroo_lock_ddc(pdev); |
2342 | edid = drm_get_edid(connector, adapter); | |
2343 | vga_switcheroo_unlock_ddc(pdev); | |
2344 | ||
2345 | return edid; | |
2346 | } | |
2347 | EXPORT_SYMBOL(drm_get_edid_switcheroo); | |
2348 | ||
51f8da59 JN |
2349 | /** |
2350 | * drm_edid_duplicate - duplicate an EDID and the extensions | |
2351 | * @edid: EDID to duplicate | |
2352 | * | |
db6cf833 | 2353 | * Return: Pointer to duplicated EDID or NULL on allocation failure. |
51f8da59 JN |
2354 | */ |
2355 | struct edid *drm_edid_duplicate(const struct edid *edid) | |
2356 | { | |
f1e4c916 | 2357 | return kmemdup(edid, edid_size(edid), GFP_KERNEL); |
51f8da59 JN |
2358 | } |
2359 | EXPORT_SYMBOL(drm_edid_duplicate); | |
2360 | ||
61e57a8d AJ |
2361 | /*** EDID parsing ***/ |
2362 | ||
f453ba04 DA |
2363 | /** |
2364 | * edid_get_quirks - return quirk flags for a given EDID | |
2365 | * @edid: EDID to process | |
2366 | * | |
2367 | * This tells subsequent routines what fixes they need to apply. | |
2368 | */ | |
170178fe | 2369 | static u32 edid_get_quirks(const struct edid *edid) |
f453ba04 | 2370 | { |
e8de4d55 | 2371 | u32 panel_id = edid_extract_panel_id(edid); |
23c4cfbd | 2372 | const struct edid_quirk *quirk; |
f453ba04 DA |
2373 | int i; |
2374 | ||
2375 | for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { | |
2376 | quirk = &edid_quirk_list[i]; | |
e8de4d55 | 2377 | if (quirk->panel_id == panel_id) |
f453ba04 DA |
2378 | return quirk->quirks; |
2379 | } | |
2380 | ||
2381 | return 0; | |
2382 | } | |
2383 | ||
2384 | #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) | |
339d202c | 2385 | #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) |
f453ba04 | 2386 | |
f453ba04 DA |
2387 | /** |
2388 | * edid_fixup_preferred - set preferred modes based on quirk list | |
2389 | * @connector: has mode list to fix up | |
2390 | * @quirks: quirks list | |
2391 | * | |
2392 | * Walk the mode list for @connector, clearing the preferred status | |
2393 | * on existing modes and setting it anew for the right mode ala @quirks. | |
2394 | */ | |
2395 | static void edid_fixup_preferred(struct drm_connector *connector, | |
2396 | u32 quirks) | |
2397 | { | |
2398 | struct drm_display_mode *t, *cur_mode, *preferred_mode; | |
f890607b | 2399 | int target_refresh = 0; |
339d202c | 2400 | int cur_vrefresh, preferred_vrefresh; |
f453ba04 DA |
2401 | |
2402 | if (list_empty(&connector->probed_modes)) | |
2403 | return; | |
2404 | ||
2405 | if (quirks & EDID_QUIRK_PREFER_LARGE_60) | |
2406 | target_refresh = 60; | |
2407 | if (quirks & EDID_QUIRK_PREFER_LARGE_75) | |
2408 | target_refresh = 75; | |
2409 | ||
2410 | preferred_mode = list_first_entry(&connector->probed_modes, | |
2411 | struct drm_display_mode, head); | |
2412 | ||
2413 | list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { | |
2414 | cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; | |
2415 | ||
2416 | if (cur_mode == preferred_mode) | |
2417 | continue; | |
2418 | ||
2419 | /* Largest mode is preferred */ | |
2420 | if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) | |
2421 | preferred_mode = cur_mode; | |
2422 | ||
0425662f VS |
2423 | cur_vrefresh = drm_mode_vrefresh(cur_mode); |
2424 | preferred_vrefresh = drm_mode_vrefresh(preferred_mode); | |
f453ba04 DA |
2425 | /* At a given size, try to get closest to target refresh */ |
2426 | if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && | |
339d202c AD |
2427 | MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < |
2428 | MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { | |
f453ba04 DA |
2429 | preferred_mode = cur_mode; |
2430 | } | |
2431 | } | |
2432 | ||
2433 | preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; | |
2434 | } | |
2435 | ||
f6e252ba AJ |
2436 | static bool |
2437 | mode_is_rb(const struct drm_display_mode *mode) | |
2438 | { | |
2439 | return (mode->htotal - mode->hdisplay == 160) && | |
2440 | (mode->hsync_end - mode->hdisplay == 80) && | |
2441 | (mode->hsync_end - mode->hsync_start == 32) && | |
2442 | (mode->vsync_start - mode->vdisplay == 3); | |
2443 | } | |
2444 | ||
33c7531d AJ |
2445 | /* |
2446 | * drm_mode_find_dmt - Create a copy of a mode if present in DMT | |
2447 | * @dev: Device to duplicate against | |
2448 | * @hsize: Mode width | |
2449 | * @vsize: Mode height | |
2450 | * @fresh: Mode refresh rate | |
f6e252ba | 2451 | * @rb: Mode reduced-blanking-ness |
33c7531d AJ |
2452 | * |
2453 | * Walk the DMT mode list looking for a match for the given parameters. | |
db6cf833 TR |
2454 | * |
2455 | * Return: A newly allocated copy of the mode, or NULL if not found. | |
33c7531d | 2456 | */ |
1d42bbc8 | 2457 | struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, |
f6e252ba AJ |
2458 | int hsize, int vsize, int fresh, |
2459 | bool rb) | |
559ee21d | 2460 | { |
07a5e632 | 2461 | int i; |
559ee21d | 2462 | |
a6b21831 | 2463 | for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { |
b1f559ec | 2464 | const struct drm_display_mode *ptr = &drm_dmt_modes[i]; |
948de842 | 2465 | |
f8b46a05 AJ |
2466 | if (hsize != ptr->hdisplay) |
2467 | continue; | |
2468 | if (vsize != ptr->vdisplay) | |
2469 | continue; | |
2470 | if (fresh != drm_mode_vrefresh(ptr)) | |
2471 | continue; | |
f6e252ba AJ |
2472 | if (rb != mode_is_rb(ptr)) |
2473 | continue; | |
f8b46a05 AJ |
2474 | |
2475 | return drm_mode_duplicate(dev, ptr); | |
559ee21d | 2476 | } |
f8b46a05 AJ |
2477 | |
2478 | return NULL; | |
559ee21d | 2479 | } |
1d42bbc8 | 2480 | EXPORT_SYMBOL(drm_mode_find_dmt); |
23425cae | 2481 | |
e379814b | 2482 | static bool is_display_descriptor(const struct detailed_timing *descriptor, u8 type) |
a7a131ac | 2483 | { |
e379814b JN |
2484 | BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0); |
2485 | BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.pad1) != 2); | |
2486 | BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.type) != 3); | |
2487 | ||
2488 | return descriptor->pixel_clock == 0 && | |
2489 | descriptor->data.other_data.pad1 == 0 && | |
2490 | descriptor->data.other_data.type == type; | |
a7a131ac VS |
2491 | } |
2492 | ||
a9b1f15f | 2493 | static bool is_detailed_timing_descriptor(const struct detailed_timing *descriptor) |
f447dd1f | 2494 | { |
a9b1f15f JN |
2495 | BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0); |
2496 | ||
2497 | return descriptor->pixel_clock != 0; | |
f447dd1f VS |
2498 | } |
2499 | ||
4194442d | 2500 | typedef void detailed_cb(const struct detailed_timing *timing, void *closure); |
d1ff6409 | 2501 | |
4d76a221 | 2502 | static void |
eed628f1 | 2503 | cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure) |
4d76a221 | 2504 | { |
7304b981 | 2505 | int i, n; |
4966b2a9 | 2506 | u8 d = ext[0x02]; |
eed628f1 | 2507 | const u8 *det_base = ext + d; |
4d76a221 | 2508 | |
7304b981 VS |
2509 | if (d < 4 || d > 127) |
2510 | return; | |
2511 | ||
4966b2a9 | 2512 | n = (127 - d) / 18; |
4d76a221 | 2513 | for (i = 0; i < n; i++) |
eed628f1 | 2514 | cb((const struct detailed_timing *)(det_base + 18 * i), closure); |
4d76a221 AJ |
2515 | } |
2516 | ||
cbba98f8 | 2517 | static void |
eed628f1 | 2518 | vtb_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure) |
cbba98f8 AJ |
2519 | { |
2520 | unsigned int i, n = min((int)ext[0x02], 6); | |
eed628f1 | 2521 | const u8 *det_base = ext + 5; |
cbba98f8 AJ |
2522 | |
2523 | if (ext[0x01] != 1) | |
2524 | return; /* unknown version */ | |
2525 | ||
2526 | for (i = 0; i < n; i++) | |
eed628f1 | 2527 | cb((const struct detailed_timing *)(det_base + 18 * i), closure); |
cbba98f8 AJ |
2528 | } |
2529 | ||
d1ff6409 | 2530 | static void |
eed628f1 | 2531 | drm_for_each_detailed_block(const struct edid *edid, detailed_cb *cb, void *closure) |
d1ff6409 AJ |
2532 | { |
2533 | int i; | |
d1ff6409 AJ |
2534 | |
2535 | if (edid == NULL) | |
2536 | return; | |
2537 | ||
2538 | for (i = 0; i < EDID_DETAILED_TIMINGS; i++) | |
2539 | cb(&(edid->detailed_timings[i]), closure); | |
2540 | ||
f1e4c916 JN |
2541 | for (i = 0; i < edid_extension_block_count(edid); i++) { |
2542 | const u8 *ext = edid_extension_block_data(edid, i); | |
948de842 | 2543 | |
4d76a221 AJ |
2544 | switch (*ext) { |
2545 | case CEA_EXT: | |
2546 | cea_for_each_detailed_block(ext, cb, closure); | |
2547 | break; | |
cbba98f8 AJ |
2548 | case VTB_EXT: |
2549 | vtb_for_each_detailed_block(ext, cb, closure); | |
2550 | break; | |
4d76a221 AJ |
2551 | default: |
2552 | break; | |
2553 | } | |
2554 | } | |
d1ff6409 AJ |
2555 | } |
2556 | ||
2557 | static void | |
4194442d | 2558 | is_rb(const struct detailed_timing *descriptor, void *data) |
d1ff6409 | 2559 | { |
90fd588f | 2560 | bool *res = data; |
a7a131ac | 2561 | |
90fd588f | 2562 | if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE)) |
a7a131ac VS |
2563 | return; |
2564 | ||
90fd588f JN |
2565 | BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10); |
2566 | BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.cvt.flags) != 15); | |
2567 | ||
2568 | if (descriptor->data.other_data.data.range.flags == DRM_EDID_CVT_SUPPORT_FLAG && | |
2569 | descriptor->data.other_data.data.range.formula.cvt.flags & 0x10) | |
2570 | *res = true; | |
d1ff6409 AJ |
2571 | } |
2572 | ||
2573 | /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ | |
2574 | static bool | |
c14e7241 | 2575 | drm_monitor_supports_rb(const struct edid *edid) |
d1ff6409 AJ |
2576 | { |
2577 | if (edid->revision >= 4) { | |
b196a498 | 2578 | bool ret = false; |
948de842 | 2579 | |
eed628f1 | 2580 | drm_for_each_detailed_block(edid, is_rb, &ret); |
d1ff6409 AJ |
2581 | return ret; |
2582 | } | |
2583 | ||
2584 | return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); | |
2585 | } | |
2586 | ||
7a374350 | 2587 | static void |
4194442d | 2588 | find_gtf2(const struct detailed_timing *descriptor, void *data) |
7a374350 | 2589 | { |
4194442d | 2590 | const struct detailed_timing **res = data; |
a7a131ac | 2591 | |
c8a4beba | 2592 | if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE)) |
a7a131ac VS |
2593 | return; |
2594 | ||
c8a4beba JN |
2595 | BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10); |
2596 | ||
2597 | if (descriptor->data.other_data.data.range.flags == 0x02) | |
2598 | *res = descriptor; | |
7a374350 AJ |
2599 | } |
2600 | ||
2601 | /* Secondary GTF curve kicks in above some break frequency */ | |
2602 | static int | |
c14e7241 | 2603 | drm_gtf2_hbreak(const struct edid *edid) |
7a374350 | 2604 | { |
4194442d | 2605 | const struct detailed_timing *descriptor = NULL; |
c8a4beba | 2606 | |
eed628f1 | 2607 | drm_for_each_detailed_block(edid, find_gtf2, &descriptor); |
948de842 | 2608 | |
c8a4beba JN |
2609 | BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12); |
2610 | ||
2611 | return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.hfreq_start_khz * 2 : 0; | |
7a374350 AJ |
2612 | } |
2613 | ||
2614 | static int | |
c14e7241 | 2615 | drm_gtf2_2c(const struct edid *edid) |
7a374350 | 2616 | { |
4194442d | 2617 | const struct detailed_timing *descriptor = NULL; |
c8a4beba | 2618 | |
eed628f1 | 2619 | drm_for_each_detailed_block(edid, find_gtf2, &descriptor); |
c8a4beba JN |
2620 | |
2621 | BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.c) != 13); | |
948de842 | 2622 | |
c8a4beba | 2623 | return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.c : 0; |
7a374350 AJ |
2624 | } |
2625 | ||
2626 | static int | |
c14e7241 | 2627 | drm_gtf2_m(const struct edid *edid) |
7a374350 | 2628 | { |
4194442d | 2629 | const struct detailed_timing *descriptor = NULL; |
948de842 | 2630 | |
eed628f1 | 2631 | drm_for_each_detailed_block(edid, find_gtf2, &descriptor); |
c8a4beba JN |
2632 | |
2633 | BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.m) != 14); | |
2634 | ||
2635 | return descriptor ? le16_to_cpu(descriptor->data.other_data.data.range.formula.gtf2.m) : 0; | |
7a374350 AJ |
2636 | } |
2637 | ||
2638 | static int | |
c14e7241 | 2639 | drm_gtf2_k(const struct edid *edid) |
7a374350 | 2640 | { |
4194442d | 2641 | const struct detailed_timing *descriptor = NULL; |
c8a4beba | 2642 | |
eed628f1 | 2643 | drm_for_each_detailed_block(edid, find_gtf2, &descriptor); |
948de842 | 2644 | |
c8a4beba JN |
2645 | BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.k) != 16); |
2646 | ||
2647 | return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.k : 0; | |
7a374350 AJ |
2648 | } |
2649 | ||
2650 | static int | |
c14e7241 | 2651 | drm_gtf2_2j(const struct edid *edid) |
7a374350 | 2652 | { |
4194442d | 2653 | const struct detailed_timing *descriptor = NULL; |
c8a4beba | 2654 | |
eed628f1 | 2655 | drm_for_each_detailed_block(edid, find_gtf2, &descriptor); |
c8a4beba JN |
2656 | |
2657 | BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.j) != 17); | |
948de842 | 2658 | |
c8a4beba | 2659 | return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.j : 0; |
7a374350 AJ |
2660 | } |
2661 | ||
2662 | /** | |
2663 | * standard_timing_level - get std. timing level(CVT/GTF/DMT) | |
2664 | * @edid: EDID block to scan | |
2665 | */ | |
c14e7241 | 2666 | static int standard_timing_level(const struct edid *edid) |
7a374350 AJ |
2667 | { |
2668 | if (edid->revision >= 2) { | |
2669 | if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) | |
2670 | return LEVEL_CVT; | |
2671 | if (drm_gtf2_hbreak(edid)) | |
2672 | return LEVEL_GTF2; | |
bfef04ad LS |
2673 | if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) |
2674 | return LEVEL_GTF; | |
7a374350 AJ |
2675 | } |
2676 | return LEVEL_DMT; | |
2677 | } | |
2678 | ||
23425cae AJ |
2679 | /* |
2680 | * 0 is reserved. The spec says 0x01 fill for unused timings. Some old | |
2681 | * monitors fill with ascii space (0x20) instead. | |
2682 | */ | |
2683 | static int | |
2684 | bad_std_timing(u8 a, u8 b) | |
2685 | { | |
2686 | return (a == 0x00 && b == 0x00) || | |
2687 | (a == 0x01 && b == 0x01) || | |
2688 | (a == 0x20 && b == 0x20); | |
2689 | } | |
2690 | ||
58911c24 VS |
2691 | static int drm_mode_hsync(const struct drm_display_mode *mode) |
2692 | { | |
2693 | if (mode->htotal <= 0) | |
2694 | return 0; | |
2695 | ||
2696 | return DIV_ROUND_CLOSEST(mode->clock, mode->htotal); | |
2697 | } | |
2698 | ||
f453ba04 DA |
2699 | /** |
2700 | * drm_mode_std - convert standard mode info (width, height, refresh) into mode | |
fc66811c DV |
2701 | * @connector: connector of for the EDID block |
2702 | * @edid: EDID block to scan | |
f453ba04 DA |
2703 | * @t: standard timing params |
2704 | * | |
2705 | * Take the standard timing params (in this case width, aspect, and refresh) | |
5c61259e | 2706 | * and convert them into a real mode using CVT/GTF/DMT. |
f453ba04 | 2707 | */ |
7ca6adb3 | 2708 | static struct drm_display_mode * |
c14e7241 | 2709 | drm_mode_std(struct drm_connector *connector, const struct edid *edid, |
fcfb2ea1 | 2710 | const struct std_timing *t) |
f453ba04 | 2711 | { |
7ca6adb3 AJ |
2712 | struct drm_device *dev = connector->dev; |
2713 | struct drm_display_mode *m, *mode = NULL; | |
5c61259e ZY |
2714 | int hsize, vsize; |
2715 | int vrefresh_rate; | |
0454beab MD |
2716 | unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) |
2717 | >> EDID_TIMING_ASPECT_SHIFT; | |
5c61259e ZY |
2718 | unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) |
2719 | >> EDID_TIMING_VFREQ_SHIFT; | |
7a374350 | 2720 | int timing_level = standard_timing_level(edid); |
5c61259e | 2721 | |
23425cae AJ |
2722 | if (bad_std_timing(t->hsize, t->vfreq_aspect)) |
2723 | return NULL; | |
2724 | ||
5c61259e ZY |
2725 | /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ |
2726 | hsize = t->hsize * 8 + 248; | |
2727 | /* vrefresh_rate = vfreq + 60 */ | |
2728 | vrefresh_rate = vfreq + 60; | |
2729 | /* the vdisplay is calculated based on the aspect ratio */ | |
f066a17d | 2730 | if (aspect_ratio == 0) { |
464fdeca | 2731 | if (edid->revision < 3) |
f066a17d AJ |
2732 | vsize = hsize; |
2733 | else | |
2734 | vsize = (hsize * 10) / 16; | |
2735 | } else if (aspect_ratio == 1) | |
f453ba04 | 2736 | vsize = (hsize * 3) / 4; |
0454beab | 2737 | else if (aspect_ratio == 2) |
f453ba04 DA |
2738 | vsize = (hsize * 4) / 5; |
2739 | else | |
2740 | vsize = (hsize * 9) / 16; | |
a0910c8e AJ |
2741 | |
2742 | /* HDTV hack, part 1 */ | |
2743 | if (vrefresh_rate == 60 && | |
2744 | ((hsize == 1360 && vsize == 765) || | |
2745 | (hsize == 1368 && vsize == 769))) { | |
2746 | hsize = 1366; | |
2747 | vsize = 768; | |
2748 | } | |
2749 | ||
7ca6adb3 AJ |
2750 | /* |
2751 | * If this connector already has a mode for this size and refresh | |
2752 | * rate (because it came from detailed or CVT info), use that | |
2753 | * instead. This way we don't have to guess at interlace or | |
2754 | * reduced blanking. | |
2755 | */ | |
522032da | 2756 | list_for_each_entry(m, &connector->probed_modes, head) |
7ca6adb3 AJ |
2757 | if (m->hdisplay == hsize && m->vdisplay == vsize && |
2758 | drm_mode_vrefresh(m) == vrefresh_rate) | |
2759 | return NULL; | |
2760 | ||
a0910c8e AJ |
2761 | /* HDTV hack, part 2 */ |
2762 | if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { | |
2763 | mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, | |
d50ba256 | 2764 | false); |
a5ef6567 JM |
2765 | if (!mode) |
2766 | return NULL; | |
559ee21d | 2767 | mode->hdisplay = 1366; |
a4967de6 AJ |
2768 | mode->hsync_start = mode->hsync_start - 1; |
2769 | mode->hsync_end = mode->hsync_end - 1; | |
559ee21d ZY |
2770 | return mode; |
2771 | } | |
a0910c8e | 2772 | |
559ee21d | 2773 | /* check whether it can be found in default mode table */ |
f6e252ba AJ |
2774 | if (drm_monitor_supports_rb(edid)) { |
2775 | mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, | |
2776 | true); | |
2777 | if (mode) | |
2778 | return mode; | |
2779 | } | |
2780 | mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); | |
559ee21d ZY |
2781 | if (mode) |
2782 | return mode; | |
2783 | ||
f6e252ba | 2784 | /* okay, generate it */ |
5c61259e ZY |
2785 | switch (timing_level) { |
2786 | case LEVEL_DMT: | |
5c61259e ZY |
2787 | break; |
2788 | case LEVEL_GTF: | |
2789 | mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); | |
2790 | break; | |
7a374350 AJ |
2791 | case LEVEL_GTF2: |
2792 | /* | |
2793 | * This is potentially wrong if there's ever a monitor with | |
2794 | * more than one ranges section, each claiming a different | |
2795 | * secondary GTF curve. Please don't do that. | |
2796 | */ | |
2797 | mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); | |
fc48f169 TI |
2798 | if (!mode) |
2799 | return NULL; | |
7a374350 | 2800 | if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { |
aefd330e | 2801 | drm_mode_destroy(dev, mode); |
7a374350 AJ |
2802 | mode = drm_gtf_mode_complex(dev, hsize, vsize, |
2803 | vrefresh_rate, 0, 0, | |
2804 | drm_gtf2_m(edid), | |
2805 | drm_gtf2_2c(edid), | |
2806 | drm_gtf2_k(edid), | |
2807 | drm_gtf2_2j(edid)); | |
2808 | } | |
2809 | break; | |
5c61259e | 2810 | case LEVEL_CVT: |
d50ba256 DA |
2811 | mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, |
2812 | false); | |
5c61259e ZY |
2813 | break; |
2814 | } | |
f453ba04 DA |
2815 | return mode; |
2816 | } | |
2817 | ||
b58db2c6 AJ |
2818 | /* |
2819 | * EDID is delightfully ambiguous about how interlaced modes are to be | |
2820 | * encoded. Our internal representation is of frame height, but some | |
2821 | * HDTV detailed timings are encoded as field height. | |
2822 | * | |
2823 | * The format list here is from CEA, in frame size. Technically we | |
2824 | * should be checking refresh rate too. Whatever. | |
2825 | */ | |
2826 | static void | |
2827 | drm_mode_do_interlace_quirk(struct drm_display_mode *mode, | |
fcfb2ea1 | 2828 | const struct detailed_pixel_timing *pt) |
b58db2c6 AJ |
2829 | { |
2830 | int i; | |
2831 | static const struct { | |
2832 | int w, h; | |
2833 | } cea_interlaced[] = { | |
2834 | { 1920, 1080 }, | |
2835 | { 720, 480 }, | |
2836 | { 1440, 480 }, | |
2837 | { 2880, 480 }, | |
2838 | { 720, 576 }, | |
2839 | { 1440, 576 }, | |
2840 | { 2880, 576 }, | |
2841 | }; | |
b58db2c6 AJ |
2842 | |
2843 | if (!(pt->misc & DRM_EDID_PT_INTERLACED)) | |
2844 | return; | |
2845 | ||
3c581411 | 2846 | for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { |
b58db2c6 AJ |
2847 | if ((mode->hdisplay == cea_interlaced[i].w) && |
2848 | (mode->vdisplay == cea_interlaced[i].h / 2)) { | |
2849 | mode->vdisplay *= 2; | |
2850 | mode->vsync_start *= 2; | |
2851 | mode->vsync_end *= 2; | |
2852 | mode->vtotal *= 2; | |
2853 | mode->vtotal |= 1; | |
2854 | } | |
2855 | } | |
2856 | ||
2857 | mode->flags |= DRM_MODE_FLAG_INTERLACE; | |
2858 | } | |
2859 | ||
f453ba04 DA |
2860 | /** |
2861 | * drm_mode_detailed - create a new mode from an EDID detailed timing section | |
2862 | * @dev: DRM device (needed to create new mode) | |
2863 | * @edid: EDID block | |
2864 | * @timing: EDID detailed timing info | |
2865 | * @quirks: quirks to apply | |
2866 | * | |
2867 | * An EDID detailed timing block contains enough info for us to create and | |
2868 | * return a new struct drm_display_mode. | |
2869 | */ | |
2870 | static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, | |
c14e7241 | 2871 | const struct edid *edid, |
fcfb2ea1 | 2872 | const struct detailed_timing *timing, |
f453ba04 DA |
2873 | u32 quirks) |
2874 | { | |
2875 | struct drm_display_mode *mode; | |
fcfb2ea1 | 2876 | const struct detailed_pixel_timing *pt = &timing->data.pixel_data; |
0454beab MD |
2877 | unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; |
2878 | unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; | |
2879 | unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; | |
2880 | unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; | |
e14cbee4 MD |
2881 | unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; |
2882 | unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; | |
16dad1d7 | 2883 | unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; |
e14cbee4 | 2884 | unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); |
f453ba04 | 2885 | |
fc438966 | 2886 | /* ignore tiny modes */ |
0454beab | 2887 | if (hactive < 64 || vactive < 64) |
fc438966 AJ |
2888 | return NULL; |
2889 | ||
0454beab | 2890 | if (pt->misc & DRM_EDID_PT_STEREO) { |
c7d015f3 | 2891 | DRM_DEBUG_KMS("stereo mode not supported\n"); |
f453ba04 DA |
2892 | return NULL; |
2893 | } | |
0454beab | 2894 | if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { |
c7d015f3 | 2895 | DRM_DEBUG_KMS("composite sync not supported\n"); |
f453ba04 DA |
2896 | } |
2897 | ||
fcb45611 ZY |
2898 | /* it is incorrect if hsync/vsync width is zero */ |
2899 | if (!hsync_pulse_width || !vsync_pulse_width) { | |
2900 | DRM_DEBUG_KMS("Incorrect Detailed timing. " | |
2901 | "Wrong Hsync/Vsync pulse width\n"); | |
2902 | return NULL; | |
2903 | } | |
bc42aabc AJ |
2904 | |
2905 | if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { | |
2906 | mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); | |
2907 | if (!mode) | |
2908 | return NULL; | |
2909 | ||
2910 | goto set_size; | |
2911 | } | |
2912 | ||
f453ba04 DA |
2913 | mode = drm_mode_create(dev); |
2914 | if (!mode) | |
2915 | return NULL; | |
2916 | ||
f453ba04 | 2917 | if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) |
faacff8e JN |
2918 | mode->clock = 1088 * 10; |
2919 | else | |
2920 | mode->clock = le16_to_cpu(timing->pixel_clock) * 10; | |
0454beab MD |
2921 | |
2922 | mode->hdisplay = hactive; | |
2923 | mode->hsync_start = mode->hdisplay + hsync_offset; | |
2924 | mode->hsync_end = mode->hsync_start + hsync_pulse_width; | |
2925 | mode->htotal = mode->hdisplay + hblank; | |
2926 | ||
2927 | mode->vdisplay = vactive; | |
2928 | mode->vsync_start = mode->vdisplay + vsync_offset; | |
2929 | mode->vsync_end = mode->vsync_start + vsync_pulse_width; | |
2930 | mode->vtotal = mode->vdisplay + vblank; | |
f453ba04 | 2931 | |
7064fef5 JB |
2932 | /* Some EDIDs have bogus h/vtotal values */ |
2933 | if (mode->hsync_end > mode->htotal) | |
2934 | mode->htotal = mode->hsync_end + 1; | |
2935 | if (mode->vsync_end > mode->vtotal) | |
2936 | mode->vtotal = mode->vsync_end + 1; | |
2937 | ||
b58db2c6 | 2938 | drm_mode_do_interlace_quirk(mode, pt); |
f453ba04 DA |
2939 | |
2940 | if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { | |
faacff8e JN |
2941 | mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC; |
2942 | } else { | |
2943 | mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? | |
2944 | DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; | |
2945 | mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? | |
2946 | DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; | |
f453ba04 DA |
2947 | } |
2948 | ||
bc42aabc | 2949 | set_size: |
e14cbee4 MD |
2950 | mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; |
2951 | mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; | |
f453ba04 DA |
2952 | |
2953 | if (quirks & EDID_QUIRK_DETAILED_IN_CM) { | |
2954 | mode->width_mm *= 10; | |
2955 | mode->height_mm *= 10; | |
2956 | } | |
2957 | ||
2958 | if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { | |
2959 | mode->width_mm = edid->width_cm * 10; | |
2960 | mode->height_mm = edid->height_cm * 10; | |
2961 | } | |
2962 | ||
bc42aabc AJ |
2963 | mode->type = DRM_MODE_TYPE_DRIVER; |
2964 | drm_mode_set_name(mode); | |
2965 | ||
f453ba04 DA |
2966 | return mode; |
2967 | } | |
2968 | ||
b17e52ef | 2969 | static bool |
b1f559ec | 2970 | mode_in_hsync_range(const struct drm_display_mode *mode, |
c14e7241 | 2971 | const struct edid *edid, const u8 *t) |
b17e52ef AJ |
2972 | { |
2973 | int hsync, hmin, hmax; | |
2974 | ||
2975 | hmin = t[7]; | |
2976 | if (edid->revision >= 4) | |
2977 | hmin += ((t[4] & 0x04) ? 255 : 0); | |
2978 | hmax = t[8]; | |
2979 | if (edid->revision >= 4) | |
2980 | hmax += ((t[4] & 0x08) ? 255 : 0); | |
07a5e632 | 2981 | hsync = drm_mode_hsync(mode); |
07a5e632 | 2982 | |
b17e52ef AJ |
2983 | return (hsync <= hmax && hsync >= hmin); |
2984 | } | |
2985 | ||
2986 | static bool | |
b1f559ec | 2987 | mode_in_vsync_range(const struct drm_display_mode *mode, |
c14e7241 | 2988 | const struct edid *edid, const u8 *t) |
b17e52ef AJ |
2989 | { |
2990 | int vsync, vmin, vmax; | |
2991 | ||
2992 | vmin = t[5]; | |
2993 | if (edid->revision >= 4) | |
2994 | vmin += ((t[4] & 0x01) ? 255 : 0); | |
2995 | vmax = t[6]; | |
2996 | if (edid->revision >= 4) | |
2997 | vmax += ((t[4] & 0x02) ? 255 : 0); | |
2998 | vsync = drm_mode_vrefresh(mode); | |
2999 | ||
3000 | return (vsync <= vmax && vsync >= vmin); | |
3001 | } | |
3002 | ||
3003 | static u32 | |
c14e7241 | 3004 | range_pixel_clock(const struct edid *edid, const u8 *t) |
b17e52ef AJ |
3005 | { |
3006 | /* unspecified */ | |
3007 | if (t[9] == 0 || t[9] == 255) | |
3008 | return 0; | |
3009 | ||
3010 | /* 1.4 with CVT support gives us real precision, yay */ | |
3011 | if (edid->revision >= 4 && t[10] == 0x04) | |
3012 | return (t[9] * 10000) - ((t[12] >> 2) * 250); | |
3013 | ||
3014 | /* 1.3 is pathetic, so fuzz up a bit */ | |
3015 | return t[9] * 10000 + 5001; | |
3016 | } | |
3017 | ||
b17e52ef | 3018 | static bool |
c14e7241 | 3019 | mode_in_range(const struct drm_display_mode *mode, const struct edid *edid, |
fcfb2ea1 | 3020 | const struct detailed_timing *timing) |
b17e52ef AJ |
3021 | { |
3022 | u32 max_clock; | |
fcfb2ea1 | 3023 | const u8 *t = (const u8 *)timing; |
b17e52ef AJ |
3024 | |
3025 | if (!mode_in_hsync_range(mode, edid, t)) | |
07a5e632 AJ |
3026 | return false; |
3027 | ||
b17e52ef | 3028 | if (!mode_in_vsync_range(mode, edid, t)) |
07a5e632 AJ |
3029 | return false; |
3030 | ||
b17e52ef | 3031 | if ((max_clock = range_pixel_clock(edid, t))) |
07a5e632 AJ |
3032 | if (mode->clock > max_clock) |
3033 | return false; | |
b17e52ef AJ |
3034 | |
3035 | /* 1.4 max horizontal check */ | |
3036 | if (edid->revision >= 4 && t[10] == 0x04) | |
3037 | if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) | |
3038 | return false; | |
3039 | ||
3040 | if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) | |
3041 | return false; | |
07a5e632 AJ |
3042 | |
3043 | return true; | |
3044 | } | |
3045 | ||
7b668ebe TI |
3046 | static bool valid_inferred_mode(const struct drm_connector *connector, |
3047 | const struct drm_display_mode *mode) | |
3048 | { | |
85f8fcd6 | 3049 | const struct drm_display_mode *m; |
7b668ebe TI |
3050 | bool ok = false; |
3051 | ||
3052 | list_for_each_entry(m, &connector->probed_modes, head) { | |
3053 | if (mode->hdisplay == m->hdisplay && | |
3054 | mode->vdisplay == m->vdisplay && | |
3055 | drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) | |
3056 | return false; /* duplicated */ | |
3057 | if (mode->hdisplay <= m->hdisplay && | |
3058 | mode->vdisplay <= m->vdisplay) | |
3059 | ok = true; | |
3060 | } | |
3061 | return ok; | |
3062 | } | |
3063 | ||
b17e52ef | 3064 | static int |
c14e7241 | 3065 | drm_dmt_modes_for_range(struct drm_connector *connector, const struct edid *edid, |
fcfb2ea1 | 3066 | const struct detailed_timing *timing) |
07a5e632 AJ |
3067 | { |
3068 | int i, modes = 0; | |
3069 | struct drm_display_mode *newmode; | |
3070 | struct drm_device *dev = connector->dev; | |
3071 | ||
a6b21831 | 3072 | for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { |
7b668ebe TI |
3073 | if (mode_in_range(drm_dmt_modes + i, edid, timing) && |
3074 | valid_inferred_mode(connector, drm_dmt_modes + i)) { | |
07a5e632 AJ |
3075 | newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); |
3076 | if (newmode) { | |
3077 | drm_mode_probed_add(connector, newmode); | |
3078 | modes++; | |
3079 | } | |
3080 | } | |
3081 | } | |
3082 | ||
3083 | return modes; | |
3084 | } | |
3085 | ||
c09dedb7 TI |
3086 | /* fix up 1366x768 mode from 1368x768; |
3087 | * GFT/CVT can't express 1366 width which isn't dividable by 8 | |
3088 | */ | |
969218fe | 3089 | void drm_mode_fixup_1366x768(struct drm_display_mode *mode) |
c09dedb7 TI |
3090 | { |
3091 | if (mode->hdisplay == 1368 && mode->vdisplay == 768) { | |
3092 | mode->hdisplay = 1366; | |
3093 | mode->hsync_start--; | |
3094 | mode->hsync_end--; | |
3095 | drm_mode_set_name(mode); | |
3096 | } | |
3097 | } | |
3098 | ||
b309bd37 | 3099 | static int |
c14e7241 | 3100 | drm_gtf_modes_for_range(struct drm_connector *connector, const struct edid *edid, |
fcfb2ea1 | 3101 | const struct detailed_timing *timing) |
b309bd37 AJ |
3102 | { |
3103 | int i, modes = 0; | |
3104 | struct drm_display_mode *newmode; | |
3105 | struct drm_device *dev = connector->dev; | |
3106 | ||
a6b21831 | 3107 | for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { |
b309bd37 | 3108 | const struct minimode *m = &extra_modes[i]; |
948de842 | 3109 | |
b309bd37 | 3110 | newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); |
fc48f169 TI |
3111 | if (!newmode) |
3112 | return modes; | |
b309bd37 | 3113 | |
969218fe | 3114 | drm_mode_fixup_1366x768(newmode); |
7b668ebe TI |
3115 | if (!mode_in_range(newmode, edid, timing) || |
3116 | !valid_inferred_mode(connector, newmode)) { | |
b309bd37 AJ |
3117 | drm_mode_destroy(dev, newmode); |
3118 | continue; | |
3119 | } | |
3120 | ||
3121 | drm_mode_probed_add(connector, newmode); | |
3122 | modes++; | |
3123 | } | |
3124 | ||
3125 | return modes; | |
3126 | } | |
3127 | ||
3128 | static int | |
c14e7241 | 3129 | drm_cvt_modes_for_range(struct drm_connector *connector, const struct edid *edid, |
fcfb2ea1 | 3130 | const struct detailed_timing *timing) |
b309bd37 AJ |
3131 | { |
3132 | int i, modes = 0; | |
3133 | struct drm_display_mode *newmode; | |
3134 | struct drm_device *dev = connector->dev; | |
3135 | bool rb = drm_monitor_supports_rb(edid); | |
3136 | ||
a6b21831 | 3137 | for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { |
b309bd37 | 3138 | const struct minimode *m = &extra_modes[i]; |
948de842 | 3139 | |
b309bd37 | 3140 | newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); |
fc48f169 TI |
3141 | if (!newmode) |
3142 | return modes; | |
b309bd37 | 3143 | |
969218fe | 3144 | drm_mode_fixup_1366x768(newmode); |
7b668ebe TI |
3145 | if (!mode_in_range(newmode, edid, timing) || |
3146 | !valid_inferred_mode(connector, newmode)) { | |
b309bd37 AJ |
3147 | drm_mode_destroy(dev, newmode); |
3148 | continue; | |
3149 | } | |
3150 | ||
3151 | drm_mode_probed_add(connector, newmode); | |
3152 | modes++; | |
3153 | } | |
3154 | ||
3155 | return modes; | |
3156 | } | |
3157 | ||
13931579 | 3158 | static void |
4194442d | 3159 | do_inferred_modes(const struct detailed_timing *timing, void *c) |
9340d8cf | 3160 | { |
13931579 | 3161 | struct detailed_mode_closure *closure = c; |
fcfb2ea1 JN |
3162 | const struct detailed_non_pixel *data = &timing->data.other_data; |
3163 | const struct detailed_data_monitor_range *range = &data->data.range; | |
9340d8cf | 3164 | |
e379814b | 3165 | if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE)) |
cb21aafe AJ |
3166 | return; |
3167 | ||
3168 | closure->modes += drm_dmt_modes_for_range(closure->connector, | |
3169 | closure->edid, | |
3170 | timing); | |
4d23f484 | 3171 | |
b309bd37 AJ |
3172 | if (!version_greater(closure->edid, 1, 1)) |
3173 | return; /* GTF not defined yet */ | |
3174 | ||
3175 | switch (range->flags) { | |
3176 | case 0x02: /* secondary gtf, XXX could do more */ | |
3177 | case 0x00: /* default gtf */ | |
3178 | closure->modes += drm_gtf_modes_for_range(closure->connector, | |
3179 | closure->edid, | |
3180 | timing); | |
3181 | break; | |
3182 | case 0x04: /* cvt, only in 1.4+ */ | |
3183 | if (!version_greater(closure->edid, 1, 3)) | |
3184 | break; | |
3185 | ||
3186 | closure->modes += drm_cvt_modes_for_range(closure->connector, | |
3187 | closure->edid, | |
3188 | timing); | |
3189 | break; | |
3190 | case 0x01: /* just the ranges, no formula */ | |
3191 | default: | |
3192 | break; | |
3193 | } | |
13931579 | 3194 | } |
69da3015 | 3195 | |
13931579 | 3196 | static int |
c14e7241 | 3197 | add_inferred_modes(struct drm_connector *connector, const struct edid *edid) |
13931579 AJ |
3198 | { |
3199 | struct detailed_mode_closure closure = { | |
d456ea2e JL |
3200 | .connector = connector, |
3201 | .edid = edid, | |
13931579 | 3202 | }; |
9340d8cf | 3203 | |
13931579 | 3204 | if (version_greater(edid, 1, 0)) |
eed628f1 | 3205 | drm_for_each_detailed_block(edid, do_inferred_modes, &closure); |
9340d8cf | 3206 | |
13931579 | 3207 | return closure.modes; |
9340d8cf AJ |
3208 | } |
3209 | ||
2255be14 | 3210 | static int |
fcfb2ea1 | 3211 | drm_est3_modes(struct drm_connector *connector, const struct detailed_timing *timing) |
2255be14 AJ |
3212 | { |
3213 | int i, j, m, modes = 0; | |
3214 | struct drm_display_mode *mode; | |
fcfb2ea1 | 3215 | const u8 *est = ((const u8 *)timing) + 6; |
2255be14 AJ |
3216 | |
3217 | for (i = 0; i < 6; i++) { | |
891a7469 | 3218 | for (j = 7; j >= 0; j--) { |
2255be14 | 3219 | m = (i * 8) + (7 - j); |
3c581411 | 3220 | if (m >= ARRAY_SIZE(est3_modes)) |
2255be14 AJ |
3221 | break; |
3222 | if (est[i] & (1 << j)) { | |
1d42bbc8 DA |
3223 | mode = drm_mode_find_dmt(connector->dev, |
3224 | est3_modes[m].w, | |
3225 | est3_modes[m].h, | |
f6e252ba AJ |
3226 | est3_modes[m].r, |
3227 | est3_modes[m].rb); | |
2255be14 AJ |
3228 | if (mode) { |
3229 | drm_mode_probed_add(connector, mode); | |
3230 | modes++; | |
3231 | } | |
3232 | } | |
3233 | } | |
3234 | } | |
3235 | ||
3236 | return modes; | |
3237 | } | |
3238 | ||
13931579 | 3239 | static void |
4194442d | 3240 | do_established_modes(const struct detailed_timing *timing, void *c) |
9cf00977 | 3241 | { |
13931579 | 3242 | struct detailed_mode_closure *closure = c; |
9cf00977 | 3243 | |
e379814b | 3244 | if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS)) |
a7a131ac VS |
3245 | return; |
3246 | ||
3247 | closure->modes += drm_est3_modes(closure->connector, timing); | |
13931579 | 3248 | } |
9cf00977 | 3249 | |
13931579 AJ |
3250 | /** |
3251 | * add_established_modes - get est. modes from EDID and add them | |
db6cf833 | 3252 | * @connector: connector to add mode(s) to |
13931579 AJ |
3253 | * @edid: EDID block to scan |
3254 | * | |
3255 | * Each EDID block contains a bitmap of the supported "established modes" list | |
3256 | * (defined above). Tease them out and add them to the global modes list. | |
3257 | */ | |
3258 | static int | |
c14e7241 | 3259 | add_established_modes(struct drm_connector *connector, const struct edid *edid) |
13931579 AJ |
3260 | { |
3261 | struct drm_device *dev = connector->dev; | |
3262 | unsigned long est_bits = edid->established_timings.t1 | | |
3263 | (edid->established_timings.t2 << 8) | | |
3264 | ((edid->established_timings.mfg_rsvd & 0x80) << 9); | |
3265 | int i, modes = 0; | |
3266 | struct detailed_mode_closure closure = { | |
d456ea2e JL |
3267 | .connector = connector, |
3268 | .edid = edid, | |
13931579 | 3269 | }; |
9cf00977 | 3270 | |
13931579 AJ |
3271 | for (i = 0; i <= EDID_EST_TIMINGS; i++) { |
3272 | if (est_bits & (1<<i)) { | |
3273 | struct drm_display_mode *newmode; | |
948de842 | 3274 | |
13931579 AJ |
3275 | newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); |
3276 | if (newmode) { | |
3277 | drm_mode_probed_add(connector, newmode); | |
3278 | modes++; | |
3279 | } | |
3280 | } | |
9cf00977 AJ |
3281 | } |
3282 | ||
13931579 | 3283 | if (version_greater(edid, 1, 0)) |
eed628f1 JN |
3284 | drm_for_each_detailed_block(edid, do_established_modes, |
3285 | &closure); | |
13931579 AJ |
3286 | |
3287 | return modes + closure.modes; | |
3288 | } | |
3289 | ||
3290 | static void | |
4194442d | 3291 | do_standard_modes(const struct detailed_timing *timing, void *c) |
13931579 AJ |
3292 | { |
3293 | struct detailed_mode_closure *closure = c; | |
fcfb2ea1 | 3294 | const struct detailed_non_pixel *data = &timing->data.other_data; |
13931579 | 3295 | struct drm_connector *connector = closure->connector; |
c14e7241 | 3296 | const struct edid *edid = closure->edid; |
a7a131ac | 3297 | int i; |
13931579 | 3298 | |
e379814b | 3299 | if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES)) |
a7a131ac | 3300 | return; |
9cf00977 | 3301 | |
a7a131ac | 3302 | for (i = 0; i < 6; i++) { |
fcfb2ea1 | 3303 | const struct std_timing *std = &data->data.timings[i]; |
a7a131ac VS |
3304 | struct drm_display_mode *newmode; |
3305 | ||
3306 | newmode = drm_mode_std(connector, edid, std); | |
3307 | if (newmode) { | |
3308 | drm_mode_probed_add(connector, newmode); | |
3309 | closure->modes++; | |
9cf00977 | 3310 | } |
9cf00977 | 3311 | } |
9cf00977 AJ |
3312 | } |
3313 | ||
f453ba04 | 3314 | /** |
13931579 | 3315 | * add_standard_modes - get std. modes from EDID and add them |
db6cf833 | 3316 | * @connector: connector to add mode(s) to |
f453ba04 | 3317 | * @edid: EDID block to scan |
f453ba04 | 3318 | * |
13931579 AJ |
3319 | * Standard modes can be calculated using the appropriate standard (DMT, |
3320 | * GTF or CVT. Grab them from @edid and add them to the list. | |
f453ba04 | 3321 | */ |
13931579 | 3322 | static int |
c14e7241 | 3323 | add_standard_modes(struct drm_connector *connector, const struct edid *edid) |
f453ba04 | 3324 | { |
9cf00977 | 3325 | int i, modes = 0; |
13931579 | 3326 | struct detailed_mode_closure closure = { |
d456ea2e JL |
3327 | .connector = connector, |
3328 | .edid = edid, | |
13931579 AJ |
3329 | }; |
3330 | ||
3331 | for (i = 0; i < EDID_STD_TIMINGS; i++) { | |
3332 | struct drm_display_mode *newmode; | |
3333 | ||
3334 | newmode = drm_mode_std(connector, edid, | |
464fdeca | 3335 | &edid->standard_timings[i]); |
13931579 AJ |
3336 | if (newmode) { |
3337 | drm_mode_probed_add(connector, newmode); | |
3338 | modes++; | |
3339 | } | |
3340 | } | |
3341 | ||
3342 | if (version_greater(edid, 1, 0)) | |
eed628f1 | 3343 | drm_for_each_detailed_block(edid, do_standard_modes, |
13931579 AJ |
3344 | &closure); |
3345 | ||
3346 | /* XXX should also look for standard codes in VTB blocks */ | |
3347 | ||
3348 | return modes + closure.modes; | |
3349 | } | |
f453ba04 | 3350 | |
13931579 | 3351 | static int drm_cvt_modes(struct drm_connector *connector, |
fcfb2ea1 | 3352 | const struct detailed_timing *timing) |
13931579 AJ |
3353 | { |
3354 | int i, j, modes = 0; | |
3355 | struct drm_display_mode *newmode; | |
3356 | struct drm_device *dev = connector->dev; | |
fcfb2ea1 | 3357 | const struct cvt_timing *cvt; |
13931579 AJ |
3358 | const int rates[] = { 60, 85, 75, 60, 50 }; |
3359 | const u8 empty[3] = { 0, 0, 0 }; | |
a327f6b8 | 3360 | |
13931579 | 3361 | for (i = 0; i < 4; i++) { |
3f649ab7 | 3362 | int width, height; |
948de842 | 3363 | |
13931579 | 3364 | cvt = &(timing->data.other_data.data.cvt[i]); |
f453ba04 | 3365 | |
13931579 | 3366 | if (!memcmp(cvt->code, empty, 3)) |
9cf00977 | 3367 | continue; |
f453ba04 | 3368 | |
13931579 AJ |
3369 | height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; |
3370 | switch (cvt->code[1] & 0x0c) { | |
d652d5f1 LT |
3371 | /* default - because compiler doesn't see that we've enumerated all cases */ |
3372 | default: | |
13931579 AJ |
3373 | case 0x00: |
3374 | width = height * 4 / 3; | |
3375 | break; | |
3376 | case 0x04: | |
3377 | width = height * 16 / 9; | |
3378 | break; | |
3379 | case 0x08: | |
3380 | width = height * 16 / 10; | |
3381 | break; | |
3382 | case 0x0c: | |
3383 | width = height * 15 / 9; | |
3384 | break; | |
3385 | } | |
3386 | ||
3387 | for (j = 1; j < 5; j++) { | |
3388 | if (cvt->code[2] & (1 << j)) { | |
3389 | newmode = drm_cvt_mode(dev, width, height, | |
3390 | rates[j], j == 0, | |
3391 | false, false); | |
3392 | if (newmode) { | |
3393 | drm_mode_probed_add(connector, newmode); | |
3394 | modes++; | |
3395 | } | |
3396 | } | |
3397 | } | |
f453ba04 DA |
3398 | } |
3399 | ||
3400 | return modes; | |
3401 | } | |
9cf00977 | 3402 | |
13931579 | 3403 | static void |
4194442d | 3404 | do_cvt_mode(const struct detailed_timing *timing, void *c) |
882f0219 | 3405 | { |
13931579 | 3406 | struct detailed_mode_closure *closure = c; |
882f0219 | 3407 | |
e379814b | 3408 | if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE)) |
a7a131ac VS |
3409 | return; |
3410 | ||
3411 | closure->modes += drm_cvt_modes(closure->connector, timing); | |
13931579 | 3412 | } |
882f0219 | 3413 | |
13931579 | 3414 | static int |
c14e7241 | 3415 | add_cvt_modes(struct drm_connector *connector, const struct edid *edid) |
4d23f484 | 3416 | { |
13931579 | 3417 | struct detailed_mode_closure closure = { |
d456ea2e JL |
3418 | .connector = connector, |
3419 | .edid = edid, | |
13931579 | 3420 | }; |
882f0219 | 3421 | |
13931579 | 3422 | if (version_greater(edid, 1, 2)) |
eed628f1 | 3423 | drm_for_each_detailed_block(edid, do_cvt_mode, &closure); |
882f0219 | 3424 | |
13931579 | 3425 | /* XXX should also look for CVT codes in VTB blocks */ |
882f0219 | 3426 | |
13931579 AJ |
3427 | return closure.modes; |
3428 | } | |
3429 | ||
fa3a7340 VS |
3430 | static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode); |
3431 | ||
13931579 | 3432 | static void |
4194442d | 3433 | do_detailed_mode(const struct detailed_timing *timing, void *c) |
13931579 AJ |
3434 | { |
3435 | struct detailed_mode_closure *closure = c; | |
3436 | struct drm_display_mode *newmode; | |
3437 | ||
a9b1f15f | 3438 | if (!is_detailed_timing_descriptor(timing)) |
f447dd1f VS |
3439 | return; |
3440 | ||
3441 | newmode = drm_mode_detailed(closure->connector->dev, | |
3442 | closure->edid, timing, | |
3443 | closure->quirks); | |
3444 | if (!newmode) | |
3445 | return; | |
13931579 | 3446 | |
f447dd1f VS |
3447 | if (closure->preferred) |
3448 | newmode->type |= DRM_MODE_TYPE_PREFERRED; | |
13931579 | 3449 | |
f447dd1f VS |
3450 | /* |
3451 | * Detailed modes are limited to 10kHz pixel clock resolution, | |
3452 | * so fix up anything that looks like CEA/HDMI mode, but the clock | |
3453 | * is just slightly off. | |
3454 | */ | |
3455 | fixup_detailed_cea_mode_clock(newmode); | |
fa3a7340 | 3456 | |
f447dd1f VS |
3457 | drm_mode_probed_add(closure->connector, newmode); |
3458 | closure->modes++; | |
3459 | closure->preferred = false; | |
13931579 | 3460 | } |
882f0219 | 3461 | |
13931579 AJ |
3462 | /* |
3463 | * add_detailed_modes - Add modes from detailed timings | |
3464 | * @connector: attached connector | |
3465 | * @edid: EDID block to scan | |
3466 | * @quirks: quirks to apply | |
3467 | */ | |
3468 | static int | |
c14e7241 | 3469 | add_detailed_modes(struct drm_connector *connector, const struct edid *edid, |
13931579 AJ |
3470 | u32 quirks) |
3471 | { | |
3472 | struct detailed_mode_closure closure = { | |
d456ea2e JL |
3473 | .connector = connector, |
3474 | .edid = edid, | |
c2925bde | 3475 | .preferred = true, |
d456ea2e | 3476 | .quirks = quirks, |
13931579 AJ |
3477 | }; |
3478 | ||
3479 | if (closure.preferred && !version_greater(edid, 1, 3)) | |
3480 | closure.preferred = | |
3481 | (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); | |
3482 | ||
eed628f1 | 3483 | drm_for_each_detailed_block(edid, do_detailed_mode, &closure); |
13931579 AJ |
3484 | |
3485 | return closure.modes; | |
882f0219 | 3486 | } |
f453ba04 | 3487 | |
8fe9790d | 3488 | #define AUDIO_BLOCK 0x01 |
54ac76f8 | 3489 | #define VIDEO_BLOCK 0x02 |
f23c20c8 | 3490 | #define VENDOR_BLOCK 0x03 |
76adaa34 | 3491 | #define SPEAKER_BLOCK 0x04 |
e85959d6 | 3492 | #define HDR_STATIC_METADATA_BLOCK 0x6 |
87563fc0 SS |
3493 | #define USE_EXTENDED_TAG 0x07 |
3494 | #define EXT_VIDEO_CAPABILITY_BLOCK 0x00 | |
832d4f2f SS |
3495 | #define EXT_VIDEO_DATA_BLOCK_420 0x0E |
3496 | #define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F | |
8fe9790d | 3497 | #define EDID_BASIC_AUDIO (1 << 6) |
a988bc72 LPC |
3498 | #define EDID_CEA_YCRCB444 (1 << 5) |
3499 | #define EDID_CEA_YCRCB422 (1 << 4) | |
b1edd6a6 | 3500 | #define EDID_CEA_VCDB_QS (1 << 6) |
8fe9790d | 3501 | |
d4e4a31d | 3502 | /* |
8fe9790d | 3503 | * Search EDID for CEA extension block. |
f23c20c8 | 3504 | */ |
4cc4f09e JN |
3505 | const u8 *drm_find_edid_extension(const struct edid *edid, |
3506 | int ext_id, int *ext_index) | |
f23c20c8 | 3507 | { |
43d16d84 | 3508 | const u8 *edid_ext = NULL; |
8fe9790d | 3509 | int i; |
f23c20c8 ML |
3510 | |
3511 | /* No EDID or EDID extensions */ | |
f1e4c916 | 3512 | if (!edid || !edid_extension_block_count(edid)) |
8fe9790d | 3513 | return NULL; |
f23c20c8 | 3514 | |
f23c20c8 | 3515 | /* Find CEA extension */ |
f1e4c916 JN |
3516 | for (i = *ext_index; i < edid_extension_block_count(edid); i++) { |
3517 | edid_ext = edid_extension_block_data(edid, i); | |
4ba0f53c | 3518 | if (edid_block_tag(edid_ext) == ext_id) |
f23c20c8 ML |
3519 | break; |
3520 | } | |
3521 | ||
f1e4c916 | 3522 | if (i >= edid_extension_block_count(edid)) |
8fe9790d ZW |
3523 | return NULL; |
3524 | ||
8873cfa3 VS |
3525 | *ext_index = i + 1; |
3526 | ||
8fe9790d ZW |
3527 | return edid_ext; |
3528 | } | |
3529 | ||
43d16d84 | 3530 | static const u8 *drm_find_cea_extension(const struct edid *edid) |
e28ad544 | 3531 | { |
43d16d84 | 3532 | const struct displayid_block *block; |
1ba63caf | 3533 | struct displayid_iter iter; |
43d16d84 | 3534 | const u8 *cea; |
1ba63caf | 3535 | int ext_index = 0; |
e28ad544 AR |
3536 | |
3537 | /* Look for a top level CEA extension block */ | |
7f261afd | 3538 | /* FIXME: make callers iterate through multiple CEA ext blocks? */ |
8873cfa3 | 3539 | cea = drm_find_edid_extension(edid, CEA_EXT, &ext_index); |
e28ad544 AR |
3540 | if (cea) |
3541 | return cea; | |
3542 | ||
3543 | /* CEA blocks can also be found embedded in a DisplayID block */ | |
1ba63caf JN |
3544 | displayid_iter_edid_begin(edid, &iter); |
3545 | displayid_iter_for_each(block, &iter) { | |
3546 | if (block->tag == DATA_BLOCK_CTA) { | |
3547 | cea = (const u8 *)block; | |
3548 | break; | |
e28ad544 AR |
3549 | } |
3550 | } | |
1ba63caf | 3551 | displayid_iter_end(&iter); |
e28ad544 | 3552 | |
1ba63caf | 3553 | return cea; |
e28ad544 AR |
3554 | } |
3555 | ||
e1cf35b9 | 3556 | static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic) |
7befe621 | 3557 | { |
9212f8ee VS |
3558 | BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127); |
3559 | BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219); | |
3560 | ||
8c1b2bd9 VS |
3561 | if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1)) |
3562 | return &edid_cea_modes_1[vic - 1]; | |
f7655d42 VS |
3563 | if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193)) |
3564 | return &edid_cea_modes_193[vic - 193]; | |
7befe621 VS |
3565 | return NULL; |
3566 | } | |
3567 | ||
3568 | static u8 cea_num_vics(void) | |
3569 | { | |
f7655d42 | 3570 | return 193 + ARRAY_SIZE(edid_cea_modes_193); |
7befe621 VS |
3571 | } |
3572 | ||
3573 | static u8 cea_next_vic(u8 vic) | |
3574 | { | |
8c1b2bd9 | 3575 | if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1)) |
f7655d42 VS |
3576 | vic = 193; |
3577 | return vic; | |
7befe621 VS |
3578 | } |
3579 | ||
e6e79209 VS |
3580 | /* |
3581 | * Calculate the alternate clock for the CEA mode | |
3582 | * (60Hz vs. 59.94Hz etc.) | |
3583 | */ | |
3584 | static unsigned int | |
3585 | cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) | |
3586 | { | |
3587 | unsigned int clock = cea_mode->clock; | |
3588 | ||
0425662f | 3589 | if (drm_mode_vrefresh(cea_mode) % 6 != 0) |
e6e79209 VS |
3590 | return clock; |
3591 | ||
3592 | /* | |
3593 | * edid_cea_modes contains the 59.94Hz | |
3594 | * variant for 240 and 480 line modes, | |
3595 | * and the 60Hz variant otherwise. | |
3596 | */ | |
3597 | if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) | |
9afd808c | 3598 | clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); |
e6e79209 | 3599 | else |
9afd808c | 3600 | clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); |
e6e79209 VS |
3601 | |
3602 | return clock; | |
3603 | } | |
3604 | ||
c45a4e46 VS |
3605 | static bool |
3606 | cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode) | |
3607 | { | |
3608 | /* | |
3609 | * For certain VICs the spec allows the vertical | |
3610 | * front porch to vary by one or two lines. | |
3611 | * | |
3612 | * cea_modes[] stores the variant with the shortest | |
3613 | * vertical front porch. We can adjust the mode to | |
3614 | * get the other variants by simply increasing the | |
3615 | * vertical front porch length. | |
3616 | */ | |
7befe621 VS |
3617 | BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 || |
3618 | cea_mode_for_vic(9)->vtotal != 262 || | |
3619 | cea_mode_for_vic(12)->vtotal != 262 || | |
3620 | cea_mode_for_vic(13)->vtotal != 262 || | |
3621 | cea_mode_for_vic(23)->vtotal != 312 || | |
3622 | cea_mode_for_vic(24)->vtotal != 312 || | |
3623 | cea_mode_for_vic(27)->vtotal != 312 || | |
3624 | cea_mode_for_vic(28)->vtotal != 312); | |
c45a4e46 VS |
3625 | |
3626 | if (((vic == 8 || vic == 9 || | |
3627 | vic == 12 || vic == 13) && mode->vtotal < 263) || | |
3628 | ((vic == 23 || vic == 24 || | |
3629 | vic == 27 || vic == 28) && mode->vtotal < 314)) { | |
3630 | mode->vsync_start++; | |
3631 | mode->vsync_end++; | |
3632 | mode->vtotal++; | |
3633 | ||
3634 | return true; | |
3635 | } | |
3636 | ||
3637 | return false; | |
3638 | } | |
3639 | ||
4c6bcf44 VS |
3640 | static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, |
3641 | unsigned int clock_tolerance) | |
3642 | { | |
357768cc | 3643 | unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; |
d9278b4c | 3644 | u8 vic; |
4c6bcf44 VS |
3645 | |
3646 | if (!to_match->clock) | |
3647 | return 0; | |
3648 | ||
357768cc VS |
3649 | if (to_match->picture_aspect_ratio) |
3650 | match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; | |
3651 | ||
7befe621 | 3652 | for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { |
563c4a75 | 3653 | struct drm_display_mode cea_mode; |
4c6bcf44 VS |
3654 | unsigned int clock1, clock2; |
3655 | ||
563c4a75 VS |
3656 | drm_mode_init(&cea_mode, cea_mode_for_vic(vic)); |
3657 | ||
4c6bcf44 | 3658 | /* Check both 60Hz and 59.94Hz */ |
c45a4e46 VS |
3659 | clock1 = cea_mode.clock; |
3660 | clock2 = cea_mode_alternate_clock(&cea_mode); | |
4c6bcf44 VS |
3661 | |
3662 | if (abs(to_match->clock - clock1) > clock_tolerance && | |
3663 | abs(to_match->clock - clock2) > clock_tolerance) | |
3664 | continue; | |
3665 | ||
c45a4e46 | 3666 | do { |
357768cc | 3667 | if (drm_mode_match(to_match, &cea_mode, match_flags)) |
c45a4e46 VS |
3668 | return vic; |
3669 | } while (cea_mode_alternate_timings(vic, &cea_mode)); | |
4c6bcf44 VS |
3670 | } |
3671 | ||
3672 | return 0; | |
3673 | } | |
3674 | ||
18316c8c TR |
3675 | /** |
3676 | * drm_match_cea_mode - look for a CEA mode matching given mode | |
3677 | * @to_match: display mode | |
3678 | * | |
db6cf833 | 3679 | * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 |
18316c8c | 3680 | * mode. |
a4799037 | 3681 | */ |
18316c8c | 3682 | u8 drm_match_cea_mode(const struct drm_display_mode *to_match) |
a4799037 | 3683 | { |
357768cc | 3684 | unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; |
d9278b4c | 3685 | u8 vic; |
a4799037 | 3686 | |
a90b590e VS |
3687 | if (!to_match->clock) |
3688 | return 0; | |
3689 | ||
357768cc VS |
3690 | if (to_match->picture_aspect_ratio) |
3691 | match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; | |
3692 | ||
7befe621 | 3693 | for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { |
563c4a75 | 3694 | struct drm_display_mode cea_mode; |
a90b590e VS |
3695 | unsigned int clock1, clock2; |
3696 | ||
563c4a75 VS |
3697 | drm_mode_init(&cea_mode, cea_mode_for_vic(vic)); |
3698 | ||
a90b590e | 3699 | /* Check both 60Hz and 59.94Hz */ |
c45a4e46 VS |
3700 | clock1 = cea_mode.clock; |
3701 | clock2 = cea_mode_alternate_clock(&cea_mode); | |
a4799037 | 3702 | |
c45a4e46 VS |
3703 | if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) && |
3704 | KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2)) | |
3705 | continue; | |
3706 | ||
3707 | do { | |
357768cc | 3708 | if (drm_mode_match(to_match, &cea_mode, match_flags)) |
c45a4e46 VS |
3709 | return vic; |
3710 | } while (cea_mode_alternate_timings(vic, &cea_mode)); | |
a4799037 | 3711 | } |
c45a4e46 | 3712 | |
a4799037 SM |
3713 | return 0; |
3714 | } | |
3715 | EXPORT_SYMBOL(drm_match_cea_mode); | |
3716 | ||
d9278b4c JN |
3717 | static bool drm_valid_cea_vic(u8 vic) |
3718 | { | |
7befe621 | 3719 | return cea_mode_for_vic(vic) != NULL; |
d9278b4c JN |
3720 | } |
3721 | ||
28c03a44 | 3722 | static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) |
0967e6a5 | 3723 | { |
7befe621 VS |
3724 | const struct drm_display_mode *mode = cea_mode_for_vic(video_code); |
3725 | ||
3726 | if (mode) | |
3727 | return mode->picture_aspect_ratio; | |
3728 | ||
3729 | return HDMI_PICTURE_ASPECT_NONE; | |
0967e6a5 | 3730 | } |
0967e6a5 | 3731 | |
d2b43473 WL |
3732 | static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code) |
3733 | { | |
3734 | return edid_4k_modes[video_code].picture_aspect_ratio; | |
3735 | } | |
3736 | ||
3f2f6533 LD |
3737 | /* |
3738 | * Calculate the alternate clock for HDMI modes (those from the HDMI vendor | |
3739 | * specific block). | |
3f2f6533 LD |
3740 | */ |
3741 | static unsigned int | |
3742 | hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) | |
3743 | { | |
3f2f6533 LD |
3744 | return cea_mode_alternate_clock(hdmi_mode); |
3745 | } | |
3746 | ||
4c6bcf44 VS |
3747 | static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, |
3748 | unsigned int clock_tolerance) | |
3749 | { | |
357768cc | 3750 | unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; |
d9278b4c | 3751 | u8 vic; |
4c6bcf44 VS |
3752 | |
3753 | if (!to_match->clock) | |
3754 | return 0; | |
3755 | ||
d2b43473 WL |
3756 | if (to_match->picture_aspect_ratio) |
3757 | match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; | |
3758 | ||
d9278b4c JN |
3759 | for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { |
3760 | const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; | |
4c6bcf44 VS |
3761 | unsigned int clock1, clock2; |
3762 | ||
3763 | /* Make sure to also match alternate clocks */ | |
3764 | clock1 = hdmi_mode->clock; | |
3765 | clock2 = hdmi_mode_alternate_clock(hdmi_mode); | |
3766 | ||
3767 | if (abs(to_match->clock - clock1) > clock_tolerance && | |
3768 | abs(to_match->clock - clock2) > clock_tolerance) | |
3769 | continue; | |
3770 | ||
357768cc | 3771 | if (drm_mode_match(to_match, hdmi_mode, match_flags)) |
d9278b4c | 3772 | return vic; |
4c6bcf44 VS |
3773 | } |
3774 | ||
3775 | return 0; | |
3776 | } | |
3777 | ||
3f2f6533 LD |
3778 | /* |
3779 | * drm_match_hdmi_mode - look for a HDMI mode matching given mode | |
3780 | * @to_match: display mode | |
3781 | * | |
3782 | * An HDMI mode is one defined in the HDMI vendor specific block. | |
3783 | * | |
3784 | * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. | |
3785 | */ | |
3786 | static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) | |
3787 | { | |
357768cc | 3788 | unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; |
d9278b4c | 3789 | u8 vic; |
3f2f6533 LD |
3790 | |
3791 | if (!to_match->clock) | |
3792 | return 0; | |
3793 | ||
d2b43473 WL |
3794 | if (to_match->picture_aspect_ratio) |
3795 | match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; | |
3796 | ||
d9278b4c JN |
3797 | for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { |
3798 | const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; | |
3f2f6533 LD |
3799 | unsigned int clock1, clock2; |
3800 | ||
3801 | /* Make sure to also match alternate clocks */ | |
3802 | clock1 = hdmi_mode->clock; | |
3803 | clock2 = hdmi_mode_alternate_clock(hdmi_mode); | |
3804 | ||
3805 | if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || | |
3806 | KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && | |
357768cc | 3807 | drm_mode_match(to_match, hdmi_mode, match_flags)) |
d9278b4c | 3808 | return vic; |
3f2f6533 LD |
3809 | } |
3810 | return 0; | |
3811 | } | |
3812 | ||
d9278b4c JN |
3813 | static bool drm_valid_hdmi_vic(u8 vic) |
3814 | { | |
3815 | return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); | |
3816 | } | |
3817 | ||
e6e79209 | 3818 | static int |
f4e558ec | 3819 | add_alternate_cea_modes(struct drm_connector *connector, const struct edid *edid) |
e6e79209 VS |
3820 | { |
3821 | struct drm_device *dev = connector->dev; | |
3822 | struct drm_display_mode *mode, *tmp; | |
3823 | LIST_HEAD(list); | |
3824 | int modes = 0; | |
3825 | ||
3826 | /* Don't add CEA modes if the CEA extension block is missing */ | |
3827 | if (!drm_find_cea_extension(edid)) | |
3828 | return 0; | |
3829 | ||
3830 | /* | |
3831 | * Go through all probed modes and create a new mode | |
3832 | * with the alternate clock for certain CEA modes. | |
3833 | */ | |
3834 | list_for_each_entry(mode, &connector->probed_modes, head) { | |
3f2f6533 | 3835 | const struct drm_display_mode *cea_mode = NULL; |
e6e79209 | 3836 | struct drm_display_mode *newmode; |
d9278b4c | 3837 | u8 vic = drm_match_cea_mode(mode); |
e6e79209 VS |
3838 | unsigned int clock1, clock2; |
3839 | ||
d9278b4c | 3840 | if (drm_valid_cea_vic(vic)) { |
7befe621 | 3841 | cea_mode = cea_mode_for_vic(vic); |
3f2f6533 LD |
3842 | clock2 = cea_mode_alternate_clock(cea_mode); |
3843 | } else { | |
d9278b4c JN |
3844 | vic = drm_match_hdmi_mode(mode); |
3845 | if (drm_valid_hdmi_vic(vic)) { | |
3846 | cea_mode = &edid_4k_modes[vic]; | |
3f2f6533 LD |
3847 | clock2 = hdmi_mode_alternate_clock(cea_mode); |
3848 | } | |
3849 | } | |
e6e79209 | 3850 | |
3f2f6533 LD |
3851 | if (!cea_mode) |
3852 | continue; | |
e6e79209 VS |
3853 | |
3854 | clock1 = cea_mode->clock; | |
e6e79209 VS |
3855 | |
3856 | if (clock1 == clock2) | |
3857 | continue; | |
3858 | ||
3859 | if (mode->clock != clock1 && mode->clock != clock2) | |
3860 | continue; | |
3861 | ||
3862 | newmode = drm_mode_duplicate(dev, cea_mode); | |
3863 | if (!newmode) | |
3864 | continue; | |
3865 | ||
27130212 DL |
3866 | /* Carry over the stereo flags */ |
3867 | newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; | |
3868 | ||
e6e79209 VS |
3869 | /* |
3870 | * The current mode could be either variant. Make | |
3871 | * sure to pick the "other" clock for the new mode. | |
3872 | */ | |
3873 | if (mode->clock != clock1) | |
3874 | newmode->clock = clock1; | |
3875 | else | |
3876 | newmode->clock = clock2; | |
3877 | ||
3878 | list_add_tail(&newmode->head, &list); | |
3879 | } | |
3880 | ||
3881 | list_for_each_entry_safe(mode, tmp, &list, head) { | |
3882 | list_del(&mode->head); | |
3883 | drm_mode_probed_add(connector, mode); | |
3884 | modes++; | |
3885 | } | |
3886 | ||
3887 | return modes; | |
3888 | } | |
a4799037 | 3889 | |
8ec6e075 SS |
3890 | static u8 svd_to_vic(u8 svd) |
3891 | { | |
3892 | /* 0-6 bit vic, 7th bit native mode indicator */ | |
3893 | if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) | |
3894 | return svd & 127; | |
3895 | ||
3896 | return svd; | |
3897 | } | |
3898 | ||
aff04ace TW |
3899 | static struct drm_display_mode * |
3900 | drm_display_mode_from_vic_index(struct drm_connector *connector, | |
3901 | const u8 *video_db, u8 video_len, | |
3902 | u8 video_index) | |
54ac76f8 CS |
3903 | { |
3904 | struct drm_device *dev = connector->dev; | |
aff04ace | 3905 | struct drm_display_mode *newmode; |
d9278b4c | 3906 | u8 vic; |
54ac76f8 | 3907 | |
aff04ace TW |
3908 | if (video_db == NULL || video_index >= video_len) |
3909 | return NULL; | |
3910 | ||
3911 | /* CEA modes are numbered 1..127 */ | |
8ec6e075 | 3912 | vic = svd_to_vic(video_db[video_index]); |
d9278b4c | 3913 | if (!drm_valid_cea_vic(vic)) |
aff04ace TW |
3914 | return NULL; |
3915 | ||
7befe621 | 3916 | newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); |
409bbf1e DL |
3917 | if (!newmode) |
3918 | return NULL; | |
3919 | ||
aff04ace TW |
3920 | return newmode; |
3921 | } | |
3922 | ||
832d4f2f SS |
3923 | /* |
3924 | * do_y420vdb_modes - Parse YCBCR 420 only modes | |
3925 | * @connector: connector corresponding to the HDMI sink | |
3926 | * @svds: start of the data block of CEA YCBCR 420 VDB | |
3927 | * @len: length of the CEA YCBCR 420 VDB | |
3928 | * | |
3929 | * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) | |
3930 | * which contains modes which can be supported in YCBCR 420 | |
3931 | * output format only. | |
3932 | */ | |
3933 | static int do_y420vdb_modes(struct drm_connector *connector, | |
3934 | const u8 *svds, u8 svds_len) | |
3935 | { | |
3936 | int modes = 0, i; | |
3937 | struct drm_device *dev = connector->dev; | |
3938 | struct drm_display_info *info = &connector->display_info; | |
3939 | struct drm_hdmi_info *hdmi = &info->hdmi; | |
3940 | ||
3941 | for (i = 0; i < svds_len; i++) { | |
3942 | u8 vic = svd_to_vic(svds[i]); | |
3943 | struct drm_display_mode *newmode; | |
3944 | ||
3945 | if (!drm_valid_cea_vic(vic)) | |
3946 | continue; | |
3947 | ||
7befe621 | 3948 | newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); |
832d4f2f SS |
3949 | if (!newmode) |
3950 | break; | |
3951 | bitmap_set(hdmi->y420_vdb_modes, vic, 1); | |
3952 | drm_mode_probed_add(connector, newmode); | |
3953 | modes++; | |
3954 | } | |
3955 | ||
3956 | if (modes > 0) | |
c03d0b52 | 3957 | info->color_formats |= DRM_COLOR_FORMAT_YCBCR420; |
832d4f2f SS |
3958 | return modes; |
3959 | } | |
3960 | ||
3961 | /* | |
3962 | * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap | |
3963 | * @connector: connector corresponding to the HDMI sink | |
3964 | * @vic: CEA vic for the video mode to be added in the map | |
3965 | * | |
3966 | * Makes an entry for a videomode in the YCBCR 420 bitmap | |
3967 | */ | |
3968 | static void | |
3969 | drm_add_cmdb_modes(struct drm_connector *connector, u8 svd) | |
3970 | { | |
3971 | u8 vic = svd_to_vic(svd); | |
3972 | struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; | |
3973 | ||
3974 | if (!drm_valid_cea_vic(vic)) | |
3975 | return; | |
3976 | ||
3977 | bitmap_set(hdmi->y420_cmdb_modes, vic, 1); | |
3978 | } | |
3979 | ||
7af655bc VS |
3980 | /** |
3981 | * drm_display_mode_from_cea_vic() - return a mode for CEA VIC | |
3982 | * @dev: DRM device | |
8d7d8c0a | 3983 | * @video_code: CEA VIC of the mode |
7af655bc VS |
3984 | * |
3985 | * Creates a new mode matching the specified CEA VIC. | |
3986 | * | |
3987 | * Returns: A new drm_display_mode on success or NULL on failure | |
3988 | */ | |
3989 | struct drm_display_mode * | |
3990 | drm_display_mode_from_cea_vic(struct drm_device *dev, | |
3991 | u8 video_code) | |
3992 | { | |
3993 | const struct drm_display_mode *cea_mode; | |
3994 | struct drm_display_mode *newmode; | |
3995 | ||
3996 | cea_mode = cea_mode_for_vic(video_code); | |
3997 | if (!cea_mode) | |
3998 | return NULL; | |
3999 | ||
4000 | newmode = drm_mode_duplicate(dev, cea_mode); | |
4001 | if (!newmode) | |
4002 | return NULL; | |
4003 | ||
4004 | return newmode; | |
4005 | } | |
4006 | EXPORT_SYMBOL(drm_display_mode_from_cea_vic); | |
4007 | ||
aff04ace TW |
4008 | static int |
4009 | do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) | |
4010 | { | |
4011 | int i, modes = 0; | |
832d4f2f | 4012 | struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; |
aff04ace TW |
4013 | |
4014 | for (i = 0; i < len; i++) { | |
4015 | struct drm_display_mode *mode; | |
948de842 | 4016 | |
aff04ace TW |
4017 | mode = drm_display_mode_from_vic_index(connector, db, len, i); |
4018 | if (mode) { | |
832d4f2f SS |
4019 | /* |
4020 | * YCBCR420 capability block contains a bitmap which | |
4021 | * gives the index of CEA modes from CEA VDB, which | |
4022 | * can support YCBCR 420 sampling output also (apart | |
4023 | * from RGB/YCBCR444 etc). | |
4024 | * For example, if the bit 0 in bitmap is set, | |
4025 | * first mode in VDB can support YCBCR420 output too. | |
4026 | * Add YCBCR420 modes only if sink is HDMI 2.0 capable. | |
4027 | */ | |
4028 | if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i)) | |
4029 | drm_add_cmdb_modes(connector, db[i]); | |
4030 | ||
aff04ace TW |
4031 | drm_mode_probed_add(connector, mode); |
4032 | modes++; | |
54ac76f8 CS |
4033 | } |
4034 | } | |
4035 | ||
4036 | return modes; | |
4037 | } | |
4038 | ||
c858cfca DL |
4039 | struct stereo_mandatory_mode { |
4040 | int width, height, vrefresh; | |
4041 | unsigned int flags; | |
4042 | }; | |
4043 | ||
4044 | static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { | |
f7e121b7 DL |
4045 | { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, |
4046 | { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, | |
c858cfca DL |
4047 | { 1920, 1080, 50, |
4048 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, | |
4049 | { 1920, 1080, 60, | |
4050 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, | |
f7e121b7 DL |
4051 | { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, |
4052 | { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, | |
4053 | { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, | |
4054 | { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } | |
c858cfca DL |
4055 | }; |
4056 | ||
4057 | static bool | |
4058 | stereo_match_mandatory(const struct drm_display_mode *mode, | |
4059 | const struct stereo_mandatory_mode *stereo_mode) | |
4060 | { | |
4061 | unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; | |
4062 | ||
4063 | return mode->hdisplay == stereo_mode->width && | |
4064 | mode->vdisplay == stereo_mode->height && | |
4065 | interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && | |
4066 | drm_mode_vrefresh(mode) == stereo_mode->vrefresh; | |
4067 | } | |
4068 | ||
c858cfca DL |
4069 | static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) |
4070 | { | |
4071 | struct drm_device *dev = connector->dev; | |
4072 | const struct drm_display_mode *mode; | |
4073 | struct list_head stereo_modes; | |
f7e121b7 | 4074 | int modes = 0, i; |
c858cfca DL |
4075 | |
4076 | INIT_LIST_HEAD(&stereo_modes); | |
4077 | ||
4078 | list_for_each_entry(mode, &connector->probed_modes, head) { | |
f7e121b7 DL |
4079 | for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { |
4080 | const struct stereo_mandatory_mode *mandatory; | |
c858cfca DL |
4081 | struct drm_display_mode *new_mode; |
4082 | ||
f7e121b7 DL |
4083 | if (!stereo_match_mandatory(mode, |
4084 | &stereo_mandatory_modes[i])) | |
4085 | continue; | |
c858cfca | 4086 | |
f7e121b7 | 4087 | mandatory = &stereo_mandatory_modes[i]; |
c858cfca DL |
4088 | new_mode = drm_mode_duplicate(dev, mode); |
4089 | if (!new_mode) | |
4090 | continue; | |
4091 | ||
f7e121b7 | 4092 | new_mode->flags |= mandatory->flags; |
c858cfca DL |
4093 | list_add_tail(&new_mode->head, &stereo_modes); |
4094 | modes++; | |
f7e121b7 | 4095 | } |
c858cfca DL |
4096 | } |
4097 | ||
4098 | list_splice_tail(&stereo_modes, &connector->probed_modes); | |
4099 | ||
4100 | return modes; | |
4101 | } | |
4102 | ||
1deee8d7 DL |
4103 | static int add_hdmi_mode(struct drm_connector *connector, u8 vic) |
4104 | { | |
4105 | struct drm_device *dev = connector->dev; | |
4106 | struct drm_display_mode *newmode; | |
4107 | ||
d9278b4c | 4108 | if (!drm_valid_hdmi_vic(vic)) { |
1deee8d7 DL |
4109 | DRM_ERROR("Unknown HDMI VIC: %d\n", vic); |
4110 | return 0; | |
4111 | } | |
4112 | ||
4113 | newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); | |
4114 | if (!newmode) | |
4115 | return 0; | |
4116 | ||
4117 | drm_mode_probed_add(connector, newmode); | |
4118 | ||
4119 | return 1; | |
4120 | } | |
4121 | ||
fbf46025 TW |
4122 | static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, |
4123 | const u8 *video_db, u8 video_len, u8 video_index) | |
4124 | { | |
fbf46025 TW |
4125 | struct drm_display_mode *newmode; |
4126 | int modes = 0; | |
fbf46025 TW |
4127 | |
4128 | if (structure & (1 << 0)) { | |
aff04ace TW |
4129 | newmode = drm_display_mode_from_vic_index(connector, video_db, |
4130 | video_len, | |
4131 | video_index); | |
fbf46025 TW |
4132 | if (newmode) { |
4133 | newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; | |
4134 | drm_mode_probed_add(connector, newmode); | |
4135 | modes++; | |
4136 | } | |
4137 | } | |
4138 | if (structure & (1 << 6)) { | |
aff04ace TW |
4139 | newmode = drm_display_mode_from_vic_index(connector, video_db, |
4140 | video_len, | |
4141 | video_index); | |
fbf46025 TW |
4142 | if (newmode) { |
4143 | newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; | |
4144 | drm_mode_probed_add(connector, newmode); | |
4145 | modes++; | |
4146 | } | |
4147 | } | |
4148 | if (structure & (1 << 8)) { | |
aff04ace TW |
4149 | newmode = drm_display_mode_from_vic_index(connector, video_db, |
4150 | video_len, | |
4151 | video_index); | |
fbf46025 | 4152 | if (newmode) { |
89570eeb | 4153 | newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; |
fbf46025 TW |
4154 | drm_mode_probed_add(connector, newmode); |
4155 | modes++; | |
4156 | } | |
4157 | } | |
4158 | ||
4159 | return modes; | |
4160 | } | |
4161 | ||
7ebe1963 LD |
4162 | /* |
4163 | * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block | |
4164 | * @connector: connector corresponding to the HDMI sink | |
4165 | * @db: start of the CEA vendor specific block | |
4166 | * @len: length of the CEA block payload, ie. one can access up to db[len] | |
4167 | * | |
c858cfca DL |
4168 | * Parses the HDMI VSDB looking for modes to add to @connector. This function |
4169 | * also adds the stereo 3d modes when applicable. | |
7ebe1963 LD |
4170 | */ |
4171 | static int | |
fbf46025 TW |
4172 | do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, |
4173 | const u8 *video_db, u8 video_len) | |
7ebe1963 | 4174 | { |
f1781e9b | 4175 | struct drm_display_info *info = &connector->display_info; |
0e5083aa | 4176 | int modes = 0, offset = 0, i, multi_present = 0, multi_len; |
fbf46025 TW |
4177 | u8 vic_len, hdmi_3d_len = 0; |
4178 | u16 mask; | |
4179 | u16 structure_all; | |
7ebe1963 LD |
4180 | |
4181 | if (len < 8) | |
4182 | goto out; | |
4183 | ||
4184 | /* no HDMI_Video_Present */ | |
4185 | if (!(db[8] & (1 << 5))) | |
4186 | goto out; | |
4187 | ||
4188 | /* Latency_Fields_Present */ | |
4189 | if (db[8] & (1 << 7)) | |
4190 | offset += 2; | |
4191 | ||
4192 | /* I_Latency_Fields_Present */ | |
4193 | if (db[8] & (1 << 6)) | |
4194 | offset += 2; | |
4195 | ||
4196 | /* the declared length is not long enough for the 2 first bytes | |
4197 | * of additional video format capabilities */ | |
c858cfca | 4198 | if (len < (8 + offset + 2)) |
7ebe1963 LD |
4199 | goto out; |
4200 | ||
c858cfca DL |
4201 | /* 3D_Present */ |
4202 | offset++; | |
fbf46025 | 4203 | if (db[8 + offset] & (1 << 7)) { |
c858cfca DL |
4204 | modes += add_hdmi_mandatory_stereo_modes(connector); |
4205 | ||
fbf46025 TW |
4206 | /* 3D_Multi_present */ |
4207 | multi_present = (db[8 + offset] & 0x60) >> 5; | |
4208 | } | |
4209 | ||
c858cfca | 4210 | offset++; |
7ebe1963 | 4211 | vic_len = db[8 + offset] >> 5; |
fbf46025 | 4212 | hdmi_3d_len = db[8 + offset] & 0x1f; |
7ebe1963 LD |
4213 | |
4214 | for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { | |
7ebe1963 LD |
4215 | u8 vic; |
4216 | ||
4217 | vic = db[9 + offset + i]; | |
1deee8d7 | 4218 | modes += add_hdmi_mode(connector, vic); |
7ebe1963 | 4219 | } |
fbf46025 TW |
4220 | offset += 1 + vic_len; |
4221 | ||
0e5083aa TW |
4222 | if (multi_present == 1) |
4223 | multi_len = 2; | |
4224 | else if (multi_present == 2) | |
4225 | multi_len = 4; | |
4226 | else | |
4227 | multi_len = 0; | |
fbf46025 | 4228 | |
0e5083aa | 4229 | if (len < (8 + offset + hdmi_3d_len - 1)) |
fbf46025 TW |
4230 | goto out; |
4231 | ||
0e5083aa | 4232 | if (hdmi_3d_len < multi_len) |
fbf46025 TW |
4233 | goto out; |
4234 | ||
0e5083aa TW |
4235 | if (multi_present == 1 || multi_present == 2) { |
4236 | /* 3D_Structure_ALL */ | |
4237 | structure_all = (db[8 + offset] << 8) | db[9 + offset]; | |
fbf46025 | 4238 | |
0e5083aa TW |
4239 | /* check if 3D_MASK is present */ |
4240 | if (multi_present == 2) | |
4241 | mask = (db[10 + offset] << 8) | db[11 + offset]; | |
4242 | else | |
4243 | mask = 0xffff; | |
4244 | ||
4245 | for (i = 0; i < 16; i++) { | |
4246 | if (mask & (1 << i)) | |
4247 | modes += add_3d_struct_modes(connector, | |
4248 | structure_all, | |
4249 | video_db, | |
4250 | video_len, i); | |
4251 | } | |
4252 | } | |
4253 | ||
4254 | offset += multi_len; | |
4255 | ||
4256 | for (i = 0; i < (hdmi_3d_len - multi_len); i++) { | |
4257 | int vic_index; | |
4258 | struct drm_display_mode *newmode = NULL; | |
4259 | unsigned int newflag = 0; | |
4260 | bool detail_present; | |
4261 | ||
4262 | detail_present = ((db[8 + offset + i] & 0x0f) > 7); | |
4263 | ||
4264 | if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) | |
4265 | break; | |
4266 | ||
4267 | /* 2D_VIC_order_X */ | |
4268 | vic_index = db[8 + offset + i] >> 4; | |
4269 | ||
4270 | /* 3D_Structure_X */ | |
4271 | switch (db[8 + offset + i] & 0x0f) { | |
4272 | case 0: | |
4273 | newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; | |
4274 | break; | |
4275 | case 6: | |
4276 | newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; | |
4277 | break; | |
4278 | case 8: | |
4279 | /* 3D_Detail_X */ | |
4280 | if ((db[9 + offset + i] >> 4) == 1) | |
4281 | newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; | |
4282 | break; | |
4283 | } | |
4284 | ||
4285 | if (newflag != 0) { | |
4286 | newmode = drm_display_mode_from_vic_index(connector, | |
4287 | video_db, | |
4288 | video_len, | |
4289 | vic_index); | |
4290 | ||
4291 | if (newmode) { | |
4292 | newmode->flags |= newflag; | |
4293 | drm_mode_probed_add(connector, newmode); | |
4294 | modes++; | |
4295 | } | |
4296 | } | |
4297 | ||
4298 | if (detail_present) | |
4299 | i++; | |
fbf46025 | 4300 | } |
7ebe1963 LD |
4301 | |
4302 | out: | |
f1781e9b VS |
4303 | if (modes > 0) |
4304 | info->has_hdmi_infoframe = true; | |
7ebe1963 LD |
4305 | return modes; |
4306 | } | |
4307 | ||
9e50b9d5 VS |
4308 | static int |
4309 | cea_db_payload_len(const u8 *db) | |
4310 | { | |
4311 | return db[0] & 0x1f; | |
4312 | } | |
4313 | ||
87563fc0 SS |
4314 | static int |
4315 | cea_db_extended_tag(const u8 *db) | |
4316 | { | |
4317 | return db[1]; | |
4318 | } | |
4319 | ||
9e50b9d5 VS |
4320 | static int |
4321 | cea_db_tag(const u8 *db) | |
4322 | { | |
4323 | return db[0] >> 5; | |
4324 | } | |
4325 | ||
4326 | static int | |
4327 | cea_revision(const u8 *cea) | |
4328 | { | |
5036c0d0 VS |
4329 | /* |
4330 | * FIXME is this correct for the DispID variant? | |
4331 | * The DispID spec doesn't really specify whether | |
4332 | * this is the revision of the CEA extension or | |
4333 | * the DispID CEA data block. And the only value | |
4334 | * given as an example is 0. | |
4335 | */ | |
9e50b9d5 VS |
4336 | return cea[1]; |
4337 | } | |
4338 | ||
4339 | static int | |
4340 | cea_db_offsets(const u8 *cea, int *start, int *end) | |
4341 | { | |
e28ad544 AR |
4342 | /* DisplayID CTA extension blocks and top-level CEA EDID |
4343 | * block header definitions differ in the following bytes: | |
4344 | * 1) Byte 2 of the header specifies length differently, | |
4345 | * 2) Byte 3 is only present in the CEA top level block. | |
4346 | * | |
4347 | * The different definitions for byte 2 follow. | |
4348 | * | |
4349 | * DisplayID CTA extension block defines byte 2 as: | |
4350 | * Number of payload bytes | |
4351 | * | |
4352 | * CEA EDID block defines byte 2 as: | |
4353 | * Byte number (decimal) within this block where the 18-byte | |
4354 | * DTDs begin. If no non-DTD data is present in this extension | |
4355 | * block, the value should be set to 04h (the byte after next). | |
4356 | * If set to 00h, there are no DTDs present in this block and | |
4357 | * no non-DTD data. | |
4358 | */ | |
4359 | if (cea[0] == DATA_BLOCK_CTA) { | |
6e8a942b VS |
4360 | /* |
4361 | * for_each_displayid_db() has already verified | |
4362 | * that these stay within expected bounds. | |
4363 | */ | |
e28ad544 AR |
4364 | *start = 3; |
4365 | *end = *start + cea[2]; | |
4366 | } else if (cea[0] == CEA_EXT) { | |
4367 | /* Data block offset in CEA extension block */ | |
4368 | *start = 4; | |
4369 | *end = cea[2]; | |
4370 | if (*end == 0) | |
4371 | *end = 127; | |
4372 | if (*end < 4 || *end > 127) | |
4373 | return -ERANGE; | |
4374 | } else { | |
c7581a41 | 4375 | return -EOPNOTSUPP; |
e28ad544 AR |
4376 | } |
4377 | ||
9e50b9d5 VS |
4378 | return 0; |
4379 | } | |
4380 | ||
7ebe1963 LD |
4381 | static bool cea_db_is_hdmi_vsdb(const u8 *db) |
4382 | { | |
7ebe1963 LD |
4383 | if (cea_db_tag(db) != VENDOR_BLOCK) |
4384 | return false; | |
4385 | ||
4386 | if (cea_db_payload_len(db) < 5) | |
4387 | return false; | |
4388 | ||
37eab1fe | 4389 | return oui(db[3], db[2], db[1]) == HDMI_IEEE_OUI; |
7ebe1963 LD |
4390 | } |
4391 | ||
50dd1bd1 TR |
4392 | static bool cea_db_is_hdmi_forum_vsdb(const u8 *db) |
4393 | { | |
50dd1bd1 TR |
4394 | if (cea_db_tag(db) != VENDOR_BLOCK) |
4395 | return false; | |
4396 | ||
4397 | if (cea_db_payload_len(db) < 7) | |
4398 | return false; | |
4399 | ||
37eab1fe | 4400 | return oui(db[3], db[2], db[1]) == HDMI_FORUM_IEEE_OUI; |
50dd1bd1 TR |
4401 | } |
4402 | ||
2869f599 PZ |
4403 | static bool cea_db_is_microsoft_vsdb(const u8 *db) |
4404 | { | |
4405 | if (cea_db_tag(db) != VENDOR_BLOCK) | |
4406 | return false; | |
4407 | ||
4408 | if (cea_db_payload_len(db) != 21) | |
4409 | return false; | |
4410 | ||
4411 | return oui(db[3], db[2], db[1]) == MICROSOFT_IEEE_OUI; | |
4412 | } | |
4413 | ||
1581b2df VS |
4414 | static bool cea_db_is_vcdb(const u8 *db) |
4415 | { | |
4416 | if (cea_db_tag(db) != USE_EXTENDED_TAG) | |
4417 | return false; | |
4418 | ||
4419 | if (cea_db_payload_len(db) != 2) | |
4420 | return false; | |
4421 | ||
4422 | if (cea_db_extended_tag(db) != EXT_VIDEO_CAPABILITY_BLOCK) | |
4423 | return false; | |
4424 | ||
4425 | return true; | |
4426 | } | |
4427 | ||
832d4f2f SS |
4428 | static bool cea_db_is_y420cmdb(const u8 *db) |
4429 | { | |
4430 | if (cea_db_tag(db) != USE_EXTENDED_TAG) | |
4431 | return false; | |
4432 | ||
4433 | if (!cea_db_payload_len(db)) | |
4434 | return false; | |
4435 | ||
4436 | if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB) | |
4437 | return false; | |
4438 | ||
4439 | return true; | |
4440 | } | |
4441 | ||
4442 | static bool cea_db_is_y420vdb(const u8 *db) | |
4443 | { | |
4444 | if (cea_db_tag(db) != USE_EXTENDED_TAG) | |
4445 | return false; | |
4446 | ||
4447 | if (!cea_db_payload_len(db)) | |
4448 | return false; | |
4449 | ||
4450 | if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420) | |
4451 | return false; | |
4452 | ||
4453 | return true; | |
4454 | } | |
4455 | ||
9e50b9d5 VS |
4456 | #define for_each_cea_db(cea, i, start, end) \ |
4457 | for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) | |
4458 | ||
832d4f2f SS |
4459 | static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector, |
4460 | const u8 *db) | |
4461 | { | |
4462 | struct drm_display_info *info = &connector->display_info; | |
4463 | struct drm_hdmi_info *hdmi = &info->hdmi; | |
4464 | u8 map_len = cea_db_payload_len(db) - 1; | |
4465 | u8 count; | |
4466 | u64 map = 0; | |
4467 | ||
4468 | if (map_len == 0) { | |
4469 | /* All CEA modes support ycbcr420 sampling also.*/ | |
4470 | hdmi->y420_cmdb_map = U64_MAX; | |
c03d0b52 | 4471 | info->color_formats |= DRM_COLOR_FORMAT_YCBCR420; |
832d4f2f SS |
4472 | return; |
4473 | } | |
4474 | ||
4475 | /* | |
4476 | * This map indicates which of the existing CEA block modes | |
4477 | * from VDB can support YCBCR420 output too. So if bit=0 is | |
4478 | * set, first mode from VDB can support YCBCR420 output too. | |
4479 | * We will parse and keep this map, before parsing VDB itself | |
4480 | * to avoid going through the same block again and again. | |
4481 | * | |
4482 | * Spec is not clear about max possible size of this block. | |
4483 | * Clamping max bitmap block size at 8 bytes. Every byte can | |
4484 | * address 8 CEA modes, in this way this map can address | |
4485 | * 8*8 = first 64 SVDs. | |
4486 | */ | |
4487 | if (WARN_ON_ONCE(map_len > 8)) | |
4488 | map_len = 8; | |
4489 | ||
4490 | for (count = 0; count < map_len; count++) | |
4491 | map |= (u64)db[2 + count] << (8 * count); | |
4492 | ||
4493 | if (map) | |
c03d0b52 | 4494 | info->color_formats |= DRM_COLOR_FORMAT_YCBCR420; |
832d4f2f SS |
4495 | |
4496 | hdmi->y420_cmdb_map = map; | |
4497 | } | |
4498 | ||
54ac76f8 | 4499 | static int |
f4e558ec | 4500 | add_cea_modes(struct drm_connector *connector, const struct edid *edid) |
54ac76f8 | 4501 | { |
13ac3f55 | 4502 | const u8 *cea = drm_find_cea_extension(edid); |
fbf46025 TW |
4503 | const u8 *db, *hdmi = NULL, *video = NULL; |
4504 | u8 dbl, hdmi_len, video_len = 0; | |
54ac76f8 CS |
4505 | int modes = 0; |
4506 | ||
9e50b9d5 VS |
4507 | if (cea && cea_revision(cea) >= 3) { |
4508 | int i, start, end; | |
4509 | ||
4510 | if (cea_db_offsets(cea, &start, &end)) | |
4511 | return 0; | |
4512 | ||
4513 | for_each_cea_db(cea, i, start, end) { | |
4514 | db = &cea[i]; | |
4515 | dbl = cea_db_payload_len(db); | |
4516 | ||
fbf46025 TW |
4517 | if (cea_db_tag(db) == VIDEO_BLOCK) { |
4518 | video = db + 1; | |
4519 | video_len = dbl; | |
4520 | modes += do_cea_modes(connector, video, dbl); | |
832d4f2f | 4521 | } else if (cea_db_is_hdmi_vsdb(db)) { |
c858cfca DL |
4522 | hdmi = db; |
4523 | hdmi_len = dbl; | |
832d4f2f SS |
4524 | } else if (cea_db_is_y420vdb(db)) { |
4525 | const u8 *vdb420 = &db[2]; | |
4526 | ||
4527 | /* Add 4:2:0(only) modes present in EDID */ | |
4528 | modes += do_y420vdb_modes(connector, | |
4529 | vdb420, | |
4530 | dbl - 1); | |
c858cfca | 4531 | } |
54ac76f8 CS |
4532 | } |
4533 | } | |
4534 | ||
c858cfca DL |
4535 | /* |
4536 | * We parse the HDMI VSDB after having added the cea modes as we will | |
4537 | * be patching their flags when the sink supports stereo 3D. | |
4538 | */ | |
4539 | if (hdmi) | |
fbf46025 TW |
4540 | modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video, |
4541 | video_len); | |
c858cfca | 4542 | |
54ac76f8 CS |
4543 | return modes; |
4544 | } | |
4545 | ||
fa3a7340 VS |
4546 | static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) |
4547 | { | |
4548 | const struct drm_display_mode *cea_mode; | |
4549 | int clock1, clock2, clock; | |
d9278b4c | 4550 | u8 vic; |
fa3a7340 VS |
4551 | const char *type; |
4552 | ||
4c6bcf44 VS |
4553 | /* |
4554 | * allow 5kHz clock difference either way to account for | |
4555 | * the 10kHz clock resolution limit of detailed timings. | |
4556 | */ | |
d9278b4c JN |
4557 | vic = drm_match_cea_mode_clock_tolerance(mode, 5); |
4558 | if (drm_valid_cea_vic(vic)) { | |
fa3a7340 | 4559 | type = "CEA"; |
7befe621 | 4560 | cea_mode = cea_mode_for_vic(vic); |
fa3a7340 VS |
4561 | clock1 = cea_mode->clock; |
4562 | clock2 = cea_mode_alternate_clock(cea_mode); | |
4563 | } else { | |
d9278b4c JN |
4564 | vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); |
4565 | if (drm_valid_hdmi_vic(vic)) { | |
fa3a7340 | 4566 | type = "HDMI"; |
d9278b4c | 4567 | cea_mode = &edid_4k_modes[vic]; |
fa3a7340 VS |
4568 | clock1 = cea_mode->clock; |
4569 | clock2 = hdmi_mode_alternate_clock(cea_mode); | |
4570 | } else { | |
4571 | return; | |
4572 | } | |
4573 | } | |
4574 | ||
4575 | /* pick whichever is closest */ | |
4576 | if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) | |
4577 | clock = clock1; | |
4578 | else | |
4579 | clock = clock2; | |
4580 | ||
4581 | if (mode->clock == clock) | |
4582 | return; | |
4583 | ||
4584 | DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", | |
d9278b4c | 4585 | type, vic, mode->clock, clock); |
fa3a7340 VS |
4586 | mode->clock = clock; |
4587 | } | |
4588 | ||
e85959d6 US |
4589 | static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db) |
4590 | { | |
4591 | if (cea_db_tag(db) != USE_EXTENDED_TAG) | |
4592 | return false; | |
4593 | ||
4594 | if (db[1] != HDR_STATIC_METADATA_BLOCK) | |
4595 | return false; | |
4596 | ||
4597 | if (cea_db_payload_len(db) < 3) | |
4598 | return false; | |
4599 | ||
4600 | return true; | |
4601 | } | |
4602 | ||
4603 | static uint8_t eotf_supported(const u8 *edid_ext) | |
4604 | { | |
4605 | return edid_ext[2] & | |
4606 | (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) | | |
4607 | BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) | | |
b5e3eed1 VS |
4608 | BIT(HDMI_EOTF_SMPTE_ST2084) | |
4609 | BIT(HDMI_EOTF_BT_2100_HLG)); | |
e85959d6 US |
4610 | } |
4611 | ||
4612 | static uint8_t hdr_metadata_type(const u8 *edid_ext) | |
4613 | { | |
4614 | return edid_ext[3] & | |
4615 | BIT(HDMI_STATIC_METADATA_TYPE1); | |
4616 | } | |
4617 | ||
4618 | static void | |
4619 | drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db) | |
4620 | { | |
4621 | u16 len; | |
4622 | ||
4623 | len = cea_db_payload_len(db); | |
4624 | ||
4625 | connector->hdr_sink_metadata.hdmi_type1.eotf = | |
4626 | eotf_supported(db); | |
4627 | connector->hdr_sink_metadata.hdmi_type1.metadata_type = | |
4628 | hdr_metadata_type(db); | |
4629 | ||
4630 | if (len >= 4) | |
4631 | connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4]; | |
4632 | if (len >= 5) | |
4633 | connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5]; | |
4634 | if (len >= 6) | |
4635 | connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6]; | |
4636 | } | |
4637 | ||
76adaa34 | 4638 | static void |
23ebf8b9 | 4639 | drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db) |
76adaa34 | 4640 | { |
8504072a | 4641 | u8 len = cea_db_payload_len(db); |
76adaa34 | 4642 | |
f7da7785 JN |
4643 | if (len >= 6 && (db[6] & (1 << 7))) |
4644 | connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI; | |
8504072a VS |
4645 | if (len >= 8) { |
4646 | connector->latency_present[0] = db[8] >> 7; | |
4647 | connector->latency_present[1] = (db[8] >> 6) & 1; | |
4648 | } | |
4649 | if (len >= 9) | |
4650 | connector->video_latency[0] = db[9]; | |
4651 | if (len >= 10) | |
4652 | connector->audio_latency[0] = db[10]; | |
4653 | if (len >= 11) | |
4654 | connector->video_latency[1] = db[11]; | |
4655 | if (len >= 12) | |
4656 | connector->audio_latency[1] = db[12]; | |
76adaa34 | 4657 | |
23ebf8b9 VS |
4658 | DRM_DEBUG_KMS("HDMI: latency present %d %d, " |
4659 | "video latency %d %d, " | |
4660 | "audio latency %d %d\n", | |
4661 | connector->latency_present[0], | |
4662 | connector->latency_present[1], | |
4663 | connector->video_latency[0], | |
4664 | connector->video_latency[1], | |
4665 | connector->audio_latency[0], | |
4666 | connector->audio_latency[1]); | |
76adaa34 WF |
4667 | } |
4668 | ||
4669 | static void | |
4194442d | 4670 | monitor_name(const struct detailed_timing *timing, void *data) |
76adaa34 | 4671 | { |
4194442d JN |
4672 | const char **res = data; |
4673 | ||
4674 | if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME)) | |
a7a131ac VS |
4675 | return; |
4676 | ||
4194442d | 4677 | *res = timing->data.other_data.data.str.str; |
14f77fdd VS |
4678 | } |
4679 | ||
c14e7241 | 4680 | static int get_monitor_name(const struct edid *edid, char name[13]) |
59f7c0fa | 4681 | { |
4194442d | 4682 | const char *edid_name = NULL; |
59f7c0fa JB |
4683 | int mnl; |
4684 | ||
4685 | if (!edid || !name) | |
4686 | return 0; | |
4687 | ||
eed628f1 | 4688 | drm_for_each_detailed_block(edid, monitor_name, &edid_name); |
59f7c0fa JB |
4689 | for (mnl = 0; edid_name && mnl < 13; mnl++) { |
4690 | if (edid_name[mnl] == 0x0a) | |
4691 | break; | |
4692 | ||
4693 | name[mnl] = edid_name[mnl]; | |
4694 | } | |
4695 | ||
4696 | return mnl; | |
4697 | } | |
4698 | ||
4699 | /** | |
4700 | * drm_edid_get_monitor_name - fetch the monitor name from the edid | |
4701 | * @edid: monitor EDID information | |
4702 | * @name: pointer to a character array to hold the name of the monitor | |
4703 | * @bufsize: The size of the name buffer (should be at least 14 chars.) | |
4704 | * | |
4705 | */ | |
f4e558ec | 4706 | void drm_edid_get_monitor_name(const struct edid *edid, char *name, int bufsize) |
59f7c0fa JB |
4707 | { |
4708 | int name_length; | |
4709 | char buf[13]; | |
4d23f484 | 4710 | |
59f7c0fa JB |
4711 | if (bufsize <= 0) |
4712 | return; | |
4713 | ||
4714 | name_length = min(get_monitor_name(edid, buf), bufsize - 1); | |
4715 | memcpy(name, buf, name_length); | |
4716 | name[name_length] = '\0'; | |
4717 | } | |
4718 | EXPORT_SYMBOL(drm_edid_get_monitor_name); | |
4719 | ||
42750d39 JN |
4720 | static void clear_eld(struct drm_connector *connector) |
4721 | { | |
4722 | memset(connector->eld, 0, sizeof(connector->eld)); | |
4723 | ||
4724 | connector->latency_present[0] = false; | |
4725 | connector->latency_present[1] = false; | |
4726 | connector->video_latency[0] = 0; | |
4727 | connector->audio_latency[0] = 0; | |
4728 | connector->video_latency[1] = 0; | |
4729 | connector->audio_latency[1] = 0; | |
4730 | } | |
4731 | ||
79436a1c | 4732 | /* |
76adaa34 WF |
4733 | * drm_edid_to_eld - build ELD from EDID |
4734 | * @connector: connector corresponding to the HDMI/DP sink | |
4735 | * @edid: EDID to parse | |
4736 | * | |
db6cf833 | 4737 | * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The |
1d1c3665 | 4738 | * HDCP and Port_ID ELD fields are left for the graphics driver to fill in. |
76adaa34 | 4739 | */ |
f4e558ec JN |
4740 | static void drm_edid_to_eld(struct drm_connector *connector, |
4741 | const struct edid *edid) | |
76adaa34 WF |
4742 | { |
4743 | uint8_t *eld = connector->eld; | |
43d16d84 JN |
4744 | const u8 *cea; |
4745 | const u8 *db; | |
7c018782 | 4746 | int total_sad_count = 0; |
76adaa34 WF |
4747 | int mnl; |
4748 | int dbl; | |
4749 | ||
42750d39 | 4750 | clear_eld(connector); |
85c91580 | 4751 | |
e9bd0b84 JN |
4752 | if (!edid) |
4753 | return; | |
4754 | ||
76adaa34 WF |
4755 | cea = drm_find_cea_extension(edid); |
4756 | if (!cea) { | |
4757 | DRM_DEBUG_KMS("ELD: no CEA Extension found\n"); | |
4758 | return; | |
4759 | } | |
4760 | ||
f7da7785 JN |
4761 | mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]); |
4762 | DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]); | |
59f7c0fa | 4763 | |
f7da7785 JN |
4764 | eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT; |
4765 | eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl; | |
76adaa34 | 4766 | |
f7da7785 | 4767 | eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D; |
76adaa34 | 4768 | |
f7da7785 JN |
4769 | eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0]; |
4770 | eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1]; | |
4771 | eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0]; | |
4772 | eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1]; | |
76adaa34 | 4773 | |
9e50b9d5 VS |
4774 | if (cea_revision(cea) >= 3) { |
4775 | int i, start, end; | |
deec222e | 4776 | int sad_count; |
9e50b9d5 VS |
4777 | |
4778 | if (cea_db_offsets(cea, &start, &end)) { | |
4779 | start = 0; | |
4780 | end = 0; | |
4781 | } | |
4782 | ||
4783 | for_each_cea_db(cea, i, start, end) { | |
4784 | db = &cea[i]; | |
4785 | dbl = cea_db_payload_len(db); | |
4786 | ||
4787 | switch (cea_db_tag(db)) { | |
a0ab734d CS |
4788 | case AUDIO_BLOCK: |
4789 | /* Audio Data Block, contains SADs */ | |
7c018782 VS |
4790 | sad_count = min(dbl / 3, 15 - total_sad_count); |
4791 | if (sad_count >= 1) | |
f7da7785 | 4792 | memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)], |
7c018782 VS |
4793 | &db[1], sad_count * 3); |
4794 | total_sad_count += sad_count; | |
a0ab734d CS |
4795 | break; |
4796 | case SPEAKER_BLOCK: | |
9e50b9d5 VS |
4797 | /* Speaker Allocation Data Block */ |
4798 | if (dbl >= 1) | |
f7da7785 | 4799 | eld[DRM_ELD_SPEAKER] = db[1]; |
a0ab734d CS |
4800 | break; |
4801 | case VENDOR_BLOCK: | |
4802 | /* HDMI Vendor-Specific Data Block */ | |
14f77fdd | 4803 | if (cea_db_is_hdmi_vsdb(db)) |
23ebf8b9 | 4804 | drm_parse_hdmi_vsdb_audio(connector, db); |
a0ab734d CS |
4805 | break; |
4806 | default: | |
4807 | break; | |
4808 | } | |
76adaa34 | 4809 | } |
9e50b9d5 | 4810 | } |
f7da7785 | 4811 | eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT; |
76adaa34 | 4812 | |
1d1c3665 JN |
4813 | if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || |
4814 | connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
4815 | eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP; | |
4816 | else | |
4817 | eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI; | |
76adaa34 | 4818 | |
938fd8aa JN |
4819 | eld[DRM_ELD_BASELINE_ELD_LEN] = |
4820 | DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); | |
4821 | ||
4822 | DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", | |
7c018782 | 4823 | drm_eld_size(eld), total_sad_count); |
76adaa34 | 4824 | } |
76adaa34 | 4825 | |
fe214163 RM |
4826 | /** |
4827 | * drm_edid_to_sad - extracts SADs from EDID | |
4828 | * @edid: EDID to parse | |
4829 | * @sads: pointer that will be set to the extracted SADs | |
4830 | * | |
4831 | * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. | |
fe214163 | 4832 | * |
db6cf833 TR |
4833 | * Note: The returned pointer needs to be freed using kfree(). |
4834 | * | |
4835 | * Return: The number of found SADs or negative number on error. | |
fe214163 | 4836 | */ |
f4e558ec | 4837 | int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads) |
fe214163 RM |
4838 | { |
4839 | int count = 0; | |
4840 | int i, start, end, dbl; | |
43d16d84 | 4841 | const u8 *cea; |
fe214163 RM |
4842 | |
4843 | cea = drm_find_cea_extension(edid); | |
4844 | if (!cea) { | |
4845 | DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); | |
42908007 | 4846 | return 0; |
fe214163 RM |
4847 | } |
4848 | ||
4849 | if (cea_revision(cea) < 3) { | |
4850 | DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); | |
42908007 | 4851 | return 0; |
fe214163 RM |
4852 | } |
4853 | ||
4854 | if (cea_db_offsets(cea, &start, &end)) { | |
4855 | DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); | |
4856 | return -EPROTO; | |
4857 | } | |
4858 | ||
4859 | for_each_cea_db(cea, i, start, end) { | |
43d16d84 | 4860 | const u8 *db = &cea[i]; |
fe214163 RM |
4861 | |
4862 | if (cea_db_tag(db) == AUDIO_BLOCK) { | |
4863 | int j; | |
948de842 | 4864 | |
fe214163 RM |
4865 | dbl = cea_db_payload_len(db); |
4866 | ||
4867 | count = dbl / 3; /* SAD is 3B */ | |
4868 | *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); | |
4869 | if (!*sads) | |
4870 | return -ENOMEM; | |
4871 | for (j = 0; j < count; j++) { | |
43d16d84 | 4872 | const u8 *sad = &db[1 + j * 3]; |
fe214163 RM |
4873 | |
4874 | (*sads)[j].format = (sad[0] & 0x78) >> 3; | |
4875 | (*sads)[j].channels = sad[0] & 0x7; | |
4876 | (*sads)[j].freq = sad[1] & 0x7F; | |
4877 | (*sads)[j].byte2 = sad[2]; | |
4878 | } | |
4879 | break; | |
4880 | } | |
4881 | } | |
4882 | ||
4883 | return count; | |
4884 | } | |
4885 | EXPORT_SYMBOL(drm_edid_to_sad); | |
4886 | ||
d105f476 AD |
4887 | /** |
4888 | * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID | |
4889 | * @edid: EDID to parse | |
4890 | * @sadb: pointer to the speaker block | |
4891 | * | |
4892 | * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. | |
d105f476 | 4893 | * |
db6cf833 TR |
4894 | * Note: The returned pointer needs to be freed using kfree(). |
4895 | * | |
4896 | * Return: The number of found Speaker Allocation Blocks or negative number on | |
4897 | * error. | |
d105f476 | 4898 | */ |
f4e558ec | 4899 | int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb) |
d105f476 AD |
4900 | { |
4901 | int count = 0; | |
4902 | int i, start, end, dbl; | |
4903 | const u8 *cea; | |
4904 | ||
4905 | cea = drm_find_cea_extension(edid); | |
4906 | if (!cea) { | |
4907 | DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); | |
42908007 | 4908 | return 0; |
d105f476 AD |
4909 | } |
4910 | ||
4911 | if (cea_revision(cea) < 3) { | |
4912 | DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); | |
42908007 | 4913 | return 0; |
d105f476 AD |
4914 | } |
4915 | ||
4916 | if (cea_db_offsets(cea, &start, &end)) { | |
4917 | DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); | |
4918 | return -EPROTO; | |
4919 | } | |
4920 | ||
4921 | for_each_cea_db(cea, i, start, end) { | |
4922 | const u8 *db = &cea[i]; | |
4923 | ||
4924 | if (cea_db_tag(db) == SPEAKER_BLOCK) { | |
4925 | dbl = cea_db_payload_len(db); | |
4926 | ||
4927 | /* Speaker Allocation Data Block */ | |
4928 | if (dbl == 3) { | |
89086bca | 4929 | *sadb = kmemdup(&db[1], dbl, GFP_KERNEL); |
618e3776 AD |
4930 | if (!*sadb) |
4931 | return -ENOMEM; | |
d105f476 AD |
4932 | count = dbl; |
4933 | break; | |
4934 | } | |
4935 | } | |
4936 | } | |
4937 | ||
4938 | return count; | |
4939 | } | |
4940 | EXPORT_SYMBOL(drm_edid_to_speaker_allocation); | |
4941 | ||
76adaa34 | 4942 | /** |
db6cf833 | 4943 | * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay |
76adaa34 WF |
4944 | * @connector: connector associated with the HDMI/DP sink |
4945 | * @mode: the display mode | |
db6cf833 TR |
4946 | * |
4947 | * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if | |
4948 | * the sink doesn't support audio or video. | |
76adaa34 WF |
4949 | */ |
4950 | int drm_av_sync_delay(struct drm_connector *connector, | |
3a818d35 | 4951 | const struct drm_display_mode *mode) |
76adaa34 WF |
4952 | { |
4953 | int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); | |
4954 | int a, v; | |
4955 | ||
4956 | if (!connector->latency_present[0]) | |
4957 | return 0; | |
4958 | if (!connector->latency_present[1]) | |
4959 | i = 0; | |
4960 | ||
4961 | a = connector->audio_latency[i]; | |
4962 | v = connector->video_latency[i]; | |
4963 | ||
4964 | /* | |
4965 | * HDMI/DP sink doesn't support audio or video? | |
4966 | */ | |
4967 | if (a == 255 || v == 255) | |
4968 | return 0; | |
4969 | ||
4970 | /* | |
4971 | * Convert raw EDID values to millisecond. | |
4972 | * Treat unknown latency as 0ms. | |
4973 | */ | |
4974 | if (a) | |
4975 | a = min(2 * (a - 1), 500); | |
4976 | if (v) | |
4977 | v = min(2 * (v - 1), 500); | |
4978 | ||
4979 | return max(v - a, 0); | |
4980 | } | |
4981 | EXPORT_SYMBOL(drm_av_sync_delay); | |
4982 | ||
8fe9790d | 4983 | /** |
db6cf833 | 4984 | * drm_detect_hdmi_monitor - detect whether monitor is HDMI |
8fe9790d ZW |
4985 | * @edid: monitor EDID information |
4986 | * | |
4987 | * Parse the CEA extension according to CEA-861-B. | |
db6cf833 | 4988 | * |
a92d083d LP |
4989 | * Drivers that have added the modes parsed from EDID to drm_display_info |
4990 | * should use &drm_display_info.is_hdmi instead of calling this function. | |
4991 | * | |
db6cf833 | 4992 | * Return: True if the monitor is HDMI, false if not or unknown. |
8fe9790d | 4993 | */ |
f4e558ec | 4994 | bool drm_detect_hdmi_monitor(const struct edid *edid) |
8fe9790d | 4995 | { |
43d16d84 | 4996 | const u8 *edid_ext; |
14f77fdd | 4997 | int i; |
8fe9790d | 4998 | int start_offset, end_offset; |
8fe9790d ZW |
4999 | |
5000 | edid_ext = drm_find_cea_extension(edid); | |
5001 | if (!edid_ext) | |
14f77fdd | 5002 | return false; |
f23c20c8 | 5003 | |
9e50b9d5 | 5004 | if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) |
14f77fdd | 5005 | return false; |
f23c20c8 ML |
5006 | |
5007 | /* | |
5008 | * Because HDMI identifier is in Vendor Specific Block, | |
5009 | * search it from all data blocks of CEA extension. | |
5010 | */ | |
9e50b9d5 | 5011 | for_each_cea_db(edid_ext, i, start_offset, end_offset) { |
14f77fdd VS |
5012 | if (cea_db_is_hdmi_vsdb(&edid_ext[i])) |
5013 | return true; | |
f23c20c8 ML |
5014 | } |
5015 | ||
14f77fdd | 5016 | return false; |
f23c20c8 ML |
5017 | } |
5018 | EXPORT_SYMBOL(drm_detect_hdmi_monitor); | |
5019 | ||
8fe9790d ZW |
5020 | /** |
5021 | * drm_detect_monitor_audio - check monitor audio capability | |
fc66811c | 5022 | * @edid: EDID block to scan |
8fe9790d ZW |
5023 | * |
5024 | * Monitor should have CEA extension block. | |
5025 | * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic | |
5026 | * audio' only. If there is any audio extension block and supported | |
5027 | * audio format, assume at least 'basic audio' support, even if 'basic | |
5028 | * audio' is not defined in EDID. | |
5029 | * | |
db6cf833 | 5030 | * Return: True if the monitor supports audio, false otherwise. |
8fe9790d | 5031 | */ |
f4e558ec | 5032 | bool drm_detect_monitor_audio(const struct edid *edid) |
8fe9790d | 5033 | { |
43d16d84 | 5034 | const u8 *edid_ext; |
8fe9790d ZW |
5035 | int i, j; |
5036 | bool has_audio = false; | |
5037 | int start_offset, end_offset; | |
5038 | ||
5039 | edid_ext = drm_find_cea_extension(edid); | |
5040 | if (!edid_ext) | |
5041 | goto end; | |
5042 | ||
5662abf6 CC |
5043 | has_audio = (edid_ext[0] == CEA_EXT && |
5044 | (edid_ext[3] & EDID_BASIC_AUDIO) != 0); | |
8fe9790d ZW |
5045 | |
5046 | if (has_audio) { | |
5047 | DRM_DEBUG_KMS("Monitor has basic audio support\n"); | |
5048 | goto end; | |
5049 | } | |
5050 | ||
9e50b9d5 VS |
5051 | if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) |
5052 | goto end; | |
8fe9790d | 5053 | |
9e50b9d5 VS |
5054 | for_each_cea_db(edid_ext, i, start_offset, end_offset) { |
5055 | if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { | |
8fe9790d | 5056 | has_audio = true; |
9e50b9d5 | 5057 | for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3) |
8fe9790d ZW |
5058 | DRM_DEBUG_KMS("CEA audio format %d\n", |
5059 | (edid_ext[i + j] >> 3) & 0xf); | |
5060 | goto end; | |
5061 | } | |
5062 | } | |
5063 | end: | |
5064 | return has_audio; | |
5065 | } | |
5066 | EXPORT_SYMBOL(drm_detect_monitor_audio); | |
5067 | ||
b1edd6a6 | 5068 | |
c8127cf0 VS |
5069 | /** |
5070 | * drm_default_rgb_quant_range - default RGB quantization range | |
5071 | * @mode: display mode | |
5072 | * | |
5073 | * Determine the default RGB quantization range for the mode, | |
5074 | * as specified in CEA-861. | |
5075 | * | |
5076 | * Return: The default RGB quantization range for the mode | |
5077 | */ | |
5078 | enum hdmi_quantization_range | |
5079 | drm_default_rgb_quant_range(const struct drm_display_mode *mode) | |
5080 | { | |
5081 | /* All CEA modes other than VIC 1 use limited quantization range. */ | |
5082 | return drm_match_cea_mode(mode) > 1 ? | |
5083 | HDMI_QUANTIZATION_RANGE_LIMITED : | |
5084 | HDMI_QUANTIZATION_RANGE_FULL; | |
5085 | } | |
5086 | EXPORT_SYMBOL(drm_default_rgb_quant_range); | |
5087 | ||
1581b2df VS |
5088 | static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db) |
5089 | { | |
5090 | struct drm_display_info *info = &connector->display_info; | |
5091 | ||
5092 | DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]); | |
5093 | ||
5094 | if (db[2] & EDID_CEA_VCDB_QS) | |
5095 | info->rgb_quant_range_selectable = true; | |
5096 | } | |
5097 | ||
4499d488 SS |
5098 | static |
5099 | void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane) | |
5100 | { | |
5101 | switch (max_frl_rate) { | |
5102 | case 1: | |
5103 | *max_lanes = 3; | |
5104 | *max_rate_per_lane = 3; | |
5105 | break; | |
5106 | case 2: | |
5107 | *max_lanes = 3; | |
5108 | *max_rate_per_lane = 6; | |
5109 | break; | |
5110 | case 3: | |
5111 | *max_lanes = 4; | |
5112 | *max_rate_per_lane = 6; | |
5113 | break; | |
5114 | case 4: | |
5115 | *max_lanes = 4; | |
5116 | *max_rate_per_lane = 8; | |
5117 | break; | |
5118 | case 5: | |
5119 | *max_lanes = 4; | |
5120 | *max_rate_per_lane = 10; | |
5121 | break; | |
5122 | case 6: | |
5123 | *max_lanes = 4; | |
5124 | *max_rate_per_lane = 12; | |
5125 | break; | |
5126 | case 0: | |
5127 | default: | |
5128 | *max_lanes = 0; | |
5129 | *max_rate_per_lane = 0; | |
5130 | } | |
5131 | } | |
5132 | ||
e6a9a2c3 SS |
5133 | static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector, |
5134 | const u8 *db) | |
5135 | { | |
5136 | u8 dc_mask; | |
5137 | struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; | |
5138 | ||
5139 | dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; | |
9068e02f | 5140 | hdmi->y420_dc_modes = dc_mask; |
e6a9a2c3 SS |
5141 | } |
5142 | ||
afa1c763 SS |
5143 | static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector, |
5144 | const u8 *hf_vsdb) | |
5145 | { | |
62c58af3 SS |
5146 | struct drm_display_info *display = &connector->display_info; |
5147 | struct drm_hdmi_info *hdmi = &display->hdmi; | |
afa1c763 | 5148 | |
f1781e9b VS |
5149 | display->has_hdmi_infoframe = true; |
5150 | ||
afa1c763 SS |
5151 | if (hf_vsdb[6] & 0x80) { |
5152 | hdmi->scdc.supported = true; | |
5153 | if (hf_vsdb[6] & 0x40) | |
5154 | hdmi->scdc.read_request = true; | |
5155 | } | |
62c58af3 SS |
5156 | |
5157 | /* | |
5158 | * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. | |
5159 | * And as per the spec, three factors confirm this: | |
5160 | * * Availability of a HF-VSDB block in EDID (check) | |
5161 | * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) | |
5162 | * * SCDC support available (let's check) | |
5163 | * Lets check it out. | |
5164 | */ | |
5165 | ||
5166 | if (hf_vsdb[5]) { | |
5167 | /* max clock is 5000 KHz times block value */ | |
5168 | u32 max_tmds_clock = hf_vsdb[5] * 5000; | |
5169 | struct drm_scdc *scdc = &hdmi->scdc; | |
5170 | ||
5171 | if (max_tmds_clock > 340000) { | |
5172 | display->max_tmds_clock = max_tmds_clock; | |
5173 | DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n", | |
5174 | display->max_tmds_clock); | |
5175 | } | |
5176 | ||
5177 | if (scdc->supported) { | |
5178 | scdc->scrambling.supported = true; | |
5179 | ||
dbe2d2bf | 5180 | /* Few sinks support scrambling for clocks < 340M */ |
62c58af3 SS |
5181 | if ((hf_vsdb[6] & 0x8)) |
5182 | scdc->scrambling.low_rates = true; | |
5183 | } | |
5184 | } | |
e6a9a2c3 | 5185 | |
4499d488 SS |
5186 | if (hf_vsdb[7]) { |
5187 | u8 max_frl_rate; | |
76ee7b90 AN |
5188 | u8 dsc_max_frl_rate; |
5189 | u8 dsc_max_slices; | |
5190 | struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap; | |
4499d488 SS |
5191 | |
5192 | DRM_DEBUG_KMS("hdmi_21 sink detected. parsing edid\n"); | |
5193 | max_frl_rate = (hf_vsdb[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4; | |
5194 | drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes, | |
5195 | &hdmi->max_frl_rate_per_lane); | |
76ee7b90 AN |
5196 | hdmi_dsc->v_1p2 = hf_vsdb[11] & DRM_EDID_DSC_1P2; |
5197 | ||
5198 | if (hdmi_dsc->v_1p2) { | |
5199 | hdmi_dsc->native_420 = hf_vsdb[11] & DRM_EDID_DSC_NATIVE_420; | |
5200 | hdmi_dsc->all_bpp = hf_vsdb[11] & DRM_EDID_DSC_ALL_BPP; | |
5201 | ||
5202 | if (hf_vsdb[11] & DRM_EDID_DSC_16BPC) | |
5203 | hdmi_dsc->bpc_supported = 16; | |
5204 | else if (hf_vsdb[11] & DRM_EDID_DSC_12BPC) | |
5205 | hdmi_dsc->bpc_supported = 12; | |
5206 | else if (hf_vsdb[11] & DRM_EDID_DSC_10BPC) | |
5207 | hdmi_dsc->bpc_supported = 10; | |
5208 | else | |
5209 | hdmi_dsc->bpc_supported = 0; | |
5210 | ||
5211 | dsc_max_frl_rate = (hf_vsdb[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4; | |
5212 | drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes, | |
5213 | &hdmi_dsc->max_frl_rate_per_lane); | |
5214 | hdmi_dsc->total_chunk_kbytes = hf_vsdb[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES; | |
5215 | ||
5216 | dsc_max_slices = hf_vsdb[12] & DRM_EDID_DSC_MAX_SLICES; | |
5217 | switch (dsc_max_slices) { | |
5218 | case 1: | |
5219 | hdmi_dsc->max_slices = 1; | |
5220 | hdmi_dsc->clk_per_slice = 340; | |
5221 | break; | |
5222 | case 2: | |
5223 | hdmi_dsc->max_slices = 2; | |
5224 | hdmi_dsc->clk_per_slice = 340; | |
5225 | break; | |
5226 | case 3: | |
5227 | hdmi_dsc->max_slices = 4; | |
5228 | hdmi_dsc->clk_per_slice = 340; | |
5229 | break; | |
5230 | case 4: | |
5231 | hdmi_dsc->max_slices = 8; | |
5232 | hdmi_dsc->clk_per_slice = 340; | |
5233 | break; | |
5234 | case 5: | |
5235 | hdmi_dsc->max_slices = 8; | |
5236 | hdmi_dsc->clk_per_slice = 400; | |
5237 | break; | |
5238 | case 6: | |
5239 | hdmi_dsc->max_slices = 12; | |
5240 | hdmi_dsc->clk_per_slice = 400; | |
5241 | break; | |
5242 | case 7: | |
5243 | hdmi_dsc->max_slices = 16; | |
5244 | hdmi_dsc->clk_per_slice = 400; | |
5245 | break; | |
5246 | case 0: | |
5247 | default: | |
5248 | hdmi_dsc->max_slices = 0; | |
5249 | hdmi_dsc->clk_per_slice = 0; | |
5250 | } | |
5251 | } | |
4499d488 SS |
5252 | } |
5253 | ||
e6a9a2c3 | 5254 | drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb); |
afa1c763 SS |
5255 | } |
5256 | ||
1cea146a VS |
5257 | static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, |
5258 | const u8 *hdmi) | |
d0c94692 | 5259 | { |
1826750f | 5260 | struct drm_display_info *info = &connector->display_info; |
d0c94692 MK |
5261 | unsigned int dc_bpc = 0; |
5262 | ||
1cea146a VS |
5263 | /* HDMI supports at least 8 bpc */ |
5264 | info->bpc = 8; | |
d0c94692 | 5265 | |
1cea146a VS |
5266 | if (cea_db_payload_len(hdmi) < 6) |
5267 | return; | |
5268 | ||
5269 | if (hdmi[6] & DRM_EDID_HDMI_DC_30) { | |
5270 | dc_bpc = 10; | |
4adc33f3 | 5271 | info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_30; |
1cea146a VS |
5272 | DRM_DEBUG("%s: HDMI sink does deep color 30.\n", |
5273 | connector->name); | |
5274 | } | |
5275 | ||
5276 | if (hdmi[6] & DRM_EDID_HDMI_DC_36) { | |
5277 | dc_bpc = 12; | |
4adc33f3 | 5278 | info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_36; |
1cea146a VS |
5279 | DRM_DEBUG("%s: HDMI sink does deep color 36.\n", |
5280 | connector->name); | |
5281 | } | |
5282 | ||
5283 | if (hdmi[6] & DRM_EDID_HDMI_DC_48) { | |
5284 | dc_bpc = 16; | |
4adc33f3 | 5285 | info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_48; |
1cea146a VS |
5286 | DRM_DEBUG("%s: HDMI sink does deep color 48.\n", |
5287 | connector->name); | |
5288 | } | |
5289 | ||
5290 | if (dc_bpc == 0) { | |
5291 | DRM_DEBUG("%s: No deep color support on this HDMI sink.\n", | |
5292 | connector->name); | |
5293 | return; | |
5294 | } | |
5295 | ||
5296 | DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n", | |
5297 | connector->name, dc_bpc); | |
5298 | info->bpc = dc_bpc; | |
d0c94692 | 5299 | |
1cea146a VS |
5300 | /* YCRCB444 is optional according to spec. */ |
5301 | if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { | |
4adc33f3 | 5302 | info->edid_hdmi_ycbcr444_dc_modes = info->edid_hdmi_rgb444_dc_modes; |
1cea146a VS |
5303 | DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n", |
5304 | connector->name); | |
5305 | } | |
d0c94692 | 5306 | |
1cea146a VS |
5307 | /* |
5308 | * Spec says that if any deep color mode is supported at all, | |
5309 | * then deep color 36 bit must be supported. | |
5310 | */ | |
5311 | if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { | |
5312 | DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n", | |
5313 | connector->name); | |
5314 | } | |
5315 | } | |
d0c94692 | 5316 | |
23ebf8b9 VS |
5317 | static void |
5318 | drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db) | |
5319 | { | |
5320 | struct drm_display_info *info = &connector->display_info; | |
5321 | u8 len = cea_db_payload_len(db); | |
5322 | ||
a92d083d LP |
5323 | info->is_hdmi = true; |
5324 | ||
23ebf8b9 VS |
5325 | if (len >= 6) |
5326 | info->dvi_dual = db[6] & 1; | |
5327 | if (len >= 7) | |
5328 | info->max_tmds_clock = db[7] * 5000; | |
5329 | ||
5330 | DRM_DEBUG_KMS("HDMI: DVI dual %d, " | |
5331 | "max TMDS clock %d kHz\n", | |
5332 | info->dvi_dual, | |
5333 | info->max_tmds_clock); | |
5334 | ||
5335 | drm_parse_hdmi_deep_color_info(connector, db); | |
5336 | } | |
5337 | ||
2869f599 PZ |
5338 | /* |
5339 | * See EDID extension for head-mounted and specialized monitors, specified at: | |
5340 | * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/specialized-monitors-edid-extension | |
5341 | */ | |
5342 | static void drm_parse_microsoft_vsdb(struct drm_connector *connector, | |
5343 | const u8 *db) | |
5344 | { | |
5345 | struct drm_display_info *info = &connector->display_info; | |
5346 | u8 version = db[4]; | |
5347 | bool desktop_usage = db[5] & BIT(6); | |
5348 | ||
5349 | /* Version 1 and 2 for HMDs, version 3 flags desktop usage explicitly */ | |
5350 | if (version == 1 || version == 2 || (version == 3 && !desktop_usage)) | |
5351 | info->non_desktop = true; | |
5352 | ||
5353 | drm_dbg_kms(connector->dev, "HMD or specialized display VSDB version %u: 0x%02x\n", | |
5354 | version, db[5]); | |
5355 | } | |
5356 | ||
1cea146a | 5357 | static void drm_parse_cea_ext(struct drm_connector *connector, |
170178fe | 5358 | const struct edid *edid) |
1cea146a VS |
5359 | { |
5360 | struct drm_display_info *info = &connector->display_info; | |
5361 | const u8 *edid_ext; | |
5362 | int i, start, end; | |
d0c94692 | 5363 | |
1cea146a VS |
5364 | edid_ext = drm_find_cea_extension(edid); |
5365 | if (!edid_ext) | |
5366 | return; | |
d0c94692 | 5367 | |
1cea146a | 5368 | info->cea_rev = edid_ext[1]; |
d0c94692 | 5369 | |
1cea146a VS |
5370 | /* The existence of a CEA block should imply RGB support */ |
5371 | info->color_formats = DRM_COLOR_FORMAT_RGB444; | |
7344bad7 JN |
5372 | |
5373 | /* CTA DisplayID Data Block does not have byte #3 */ | |
5374 | if (edid_ext[0] == CEA_EXT) { | |
5375 | if (edid_ext[3] & EDID_CEA_YCRCB444) | |
5376 | info->color_formats |= DRM_COLOR_FORMAT_YCBCR444; | |
5377 | if (edid_ext[3] & EDID_CEA_YCRCB422) | |
5378 | info->color_formats |= DRM_COLOR_FORMAT_YCBCR422; | |
5379 | } | |
1cea146a VS |
5380 | |
5381 | if (cea_db_offsets(edid_ext, &start, &end)) | |
5382 | return; | |
5383 | ||
5384 | for_each_cea_db(edid_ext, i, start, end) { | |
5385 | const u8 *db = &edid_ext[i]; | |
5386 | ||
23ebf8b9 VS |
5387 | if (cea_db_is_hdmi_vsdb(db)) |
5388 | drm_parse_hdmi_vsdb_video(connector, db); | |
afa1c763 SS |
5389 | if (cea_db_is_hdmi_forum_vsdb(db)) |
5390 | drm_parse_hdmi_forum_vsdb(connector, db); | |
2869f599 PZ |
5391 | if (cea_db_is_microsoft_vsdb(db)) |
5392 | drm_parse_microsoft_vsdb(connector, db); | |
832d4f2f SS |
5393 | if (cea_db_is_y420cmdb(db)) |
5394 | drm_parse_y420cmdb_bitmap(connector, db); | |
1581b2df VS |
5395 | if (cea_db_is_vcdb(db)) |
5396 | drm_parse_vcdb(connector, db); | |
e85959d6 US |
5397 | if (cea_db_is_hdmi_hdr_metadata_block(db)) |
5398 | drm_parse_hdr_metadata_block(connector, db); | |
1cea146a | 5399 | } |
d0c94692 MK |
5400 | } |
5401 | ||
a1d11d1e | 5402 | static |
4194442d | 5403 | void get_monitor_range(const struct detailed_timing *timing, |
a1d11d1e MN |
5404 | void *info_monitor_range) |
5405 | { | |
5406 | struct drm_monitor_range_info *monitor_range = info_monitor_range; | |
5407 | const struct detailed_non_pixel *data = &timing->data.other_data; | |
5408 | const struct detailed_data_monitor_range *range = &data->data.range; | |
5409 | ||
e379814b | 5410 | if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE)) |
a1d11d1e MN |
5411 | return; |
5412 | ||
5413 | /* | |
5414 | * Check for flag range limits only. If flag == 1 then | |
5415 | * no additional timing information provided. | |
5416 | * Default GTF, GTF Secondary curve and CVT are not | |
5417 | * supported | |
5418 | */ | |
5419 | if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG) | |
5420 | return; | |
5421 | ||
5422 | monitor_range->min_vfreq = range->min_vfreq; | |
5423 | monitor_range->max_vfreq = range->max_vfreq; | |
5424 | } | |
5425 | ||
5426 | static | |
5427 | void drm_get_monitor_range(struct drm_connector *connector, | |
5428 | const struct edid *edid) | |
5429 | { | |
5430 | struct drm_display_info *info = &connector->display_info; | |
5431 | ||
5432 | if (!version_greater(edid, 1, 1)) | |
5433 | return; | |
5434 | ||
eed628f1 | 5435 | drm_for_each_detailed_block(edid, get_monitor_range, |
a1d11d1e MN |
5436 | &info->monitor_range); |
5437 | ||
5438 | DRM_DEBUG_KMS("Supported Monitor Refresh rate range is %d Hz - %d Hz\n", | |
5439 | info->monitor_range.min_vfreq, | |
5440 | info->monitor_range.max_vfreq); | |
5441 | } | |
5442 | ||
18a9cbbe JN |
5443 | static void drm_parse_vesa_mso_data(struct drm_connector *connector, |
5444 | const struct displayid_block *block) | |
5445 | { | |
5446 | struct displayid_vesa_vendor_specific_block *vesa = | |
5447 | (struct displayid_vesa_vendor_specific_block *)block; | |
5448 | struct drm_display_info *info = &connector->display_info; | |
5449 | ||
5450 | if (block->num_bytes < 3) { | |
5451 | drm_dbg_kms(connector->dev, "Unexpected vendor block size %u\n", | |
5452 | block->num_bytes); | |
5453 | return; | |
5454 | } | |
5455 | ||
5456 | if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI) | |
5457 | return; | |
5458 | ||
5459 | if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) { | |
5460 | drm_dbg_kms(connector->dev, "Unexpected VESA vendor block size\n"); | |
5461 | return; | |
5462 | } | |
5463 | ||
5464 | switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) { | |
5465 | default: | |
5466 | drm_dbg_kms(connector->dev, "Reserved MSO mode value\n"); | |
5467 | fallthrough; | |
5468 | case 0: | |
5469 | info->mso_stream_count = 0; | |
5470 | break; | |
5471 | case 1: | |
5472 | info->mso_stream_count = 2; /* 2 or 4 links */ | |
5473 | break; | |
5474 | case 2: | |
5475 | info->mso_stream_count = 4; /* 4 links */ | |
5476 | break; | |
5477 | } | |
5478 | ||
5479 | if (!info->mso_stream_count) { | |
5480 | info->mso_pixel_overlap = 0; | |
5481 | return; | |
5482 | } | |
5483 | ||
5484 | info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso); | |
5485 | if (info->mso_pixel_overlap > 8) { | |
5486 | drm_dbg_kms(connector->dev, "Reserved MSO pixel overlap value %u\n", | |
5487 | info->mso_pixel_overlap); | |
5488 | info->mso_pixel_overlap = 8; | |
5489 | } | |
5490 | ||
5491 | drm_dbg_kms(connector->dev, "MSO stream count %u, pixel overlap %u\n", | |
5492 | info->mso_stream_count, info->mso_pixel_overlap); | |
5493 | } | |
5494 | ||
5495 | static void drm_update_mso(struct drm_connector *connector, const struct edid *edid) | |
5496 | { | |
5497 | const struct displayid_block *block; | |
5498 | struct displayid_iter iter; | |
5499 | ||
5500 | displayid_iter_edid_begin(edid, &iter); | |
5501 | displayid_iter_for_each(block, &iter) { | |
5502 | if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC) | |
5503 | drm_parse_vesa_mso_data(connector, block); | |
5504 | } | |
5505 | displayid_iter_end(&iter); | |
5506 | } | |
5507 | ||
170178fe KP |
5508 | /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset |
5509 | * all of the values which would have been set from EDID | |
5510 | */ | |
5511 | void | |
5512 | drm_reset_display_info(struct drm_connector *connector) | |
5513 | { | |
5514 | struct drm_display_info *info = &connector->display_info; | |
5515 | ||
5516 | info->width_mm = 0; | |
5517 | info->height_mm = 0; | |
5518 | ||
5519 | info->bpc = 0; | |
5520 | info->color_formats = 0; | |
5521 | info->cea_rev = 0; | |
5522 | info->max_tmds_clock = 0; | |
5523 | info->dvi_dual = false; | |
a92d083d | 5524 | info->is_hdmi = false; |
170178fe | 5525 | info->has_hdmi_infoframe = false; |
1581b2df | 5526 | info->rgb_quant_range_selectable = false; |
1f6b8eef | 5527 | memset(&info->hdmi, 0, sizeof(info->hdmi)); |
170178fe | 5528 | |
70c0b80d MR |
5529 | info->edid_hdmi_rgb444_dc_modes = 0; |
5530 | info->edid_hdmi_ycbcr444_dc_modes = 0; | |
5531 | ||
170178fe | 5532 | info->non_desktop = 0; |
a1d11d1e | 5533 | memset(&info->monitor_range, 0, sizeof(info->monitor_range)); |
18a9cbbe JN |
5534 | |
5535 | info->mso_stream_count = 0; | |
5536 | info->mso_pixel_overlap = 0; | |
170178fe | 5537 | } |
170178fe KP |
5538 | |
5539 | u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid) | |
3b11228b | 5540 | { |
1826750f | 5541 | struct drm_display_info *info = &connector->display_info; |
ebec9a7b | 5542 | |
170178fe KP |
5543 | u32 quirks = edid_get_quirks(edid); |
5544 | ||
1f6b8eef VS |
5545 | drm_reset_display_info(connector); |
5546 | ||
3b11228b JB |
5547 | info->width_mm = edid->width_cm * 10; |
5548 | info->height_mm = edid->height_cm * 10; | |
5549 | ||
a1d11d1e MN |
5550 | drm_get_monitor_range(connector, edid); |
5551 | ||
a988bc72 | 5552 | if (edid->revision < 3) |
ce99534e | 5553 | goto out; |
3b11228b JB |
5554 | |
5555 | if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) | |
ce99534e | 5556 | goto out; |
3b11228b | 5557 | |
ecbd4912 | 5558 | info->color_formats |= DRM_COLOR_FORMAT_RGB444; |
1cea146a | 5559 | drm_parse_cea_ext(connector, edid); |
d0c94692 | 5560 | |
210a021d MK |
5561 | /* |
5562 | * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? | |
5563 | * | |
5564 | * For such displays, the DFP spec 1.0, section 3.10 "EDID support" | |
5565 | * tells us to assume 8 bpc color depth if the EDID doesn't have | |
5566 | * extensions which tell otherwise. | |
5567 | */ | |
3bde449f VS |
5568 | if (info->bpc == 0 && edid->revision == 3 && |
5569 | edid->input & DRM_EDID_DIGITAL_DFP_1_X) { | |
210a021d MK |
5570 | info->bpc = 8; |
5571 | DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n", | |
5572 | connector->name, info->bpc); | |
5573 | } | |
5574 | ||
a988bc72 LPC |
5575 | /* Only defined for 1.4 with digital displays */ |
5576 | if (edid->revision < 4) | |
ce99534e | 5577 | goto out; |
a988bc72 | 5578 | |
3b11228b JB |
5579 | switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { |
5580 | case DRM_EDID_DIGITAL_DEPTH_6: | |
5581 | info->bpc = 6; | |
5582 | break; | |
5583 | case DRM_EDID_DIGITAL_DEPTH_8: | |
5584 | info->bpc = 8; | |
5585 | break; | |
5586 | case DRM_EDID_DIGITAL_DEPTH_10: | |
5587 | info->bpc = 10; | |
5588 | break; | |
5589 | case DRM_EDID_DIGITAL_DEPTH_12: | |
5590 | info->bpc = 12; | |
5591 | break; | |
5592 | case DRM_EDID_DIGITAL_DEPTH_14: | |
5593 | info->bpc = 14; | |
5594 | break; | |
5595 | case DRM_EDID_DIGITAL_DEPTH_16: | |
5596 | info->bpc = 16; | |
5597 | break; | |
5598 | case DRM_EDID_DIGITAL_DEPTH_UNDEF: | |
5599 | default: | |
5600 | info->bpc = 0; | |
5601 | break; | |
5602 | } | |
da05a5a7 | 5603 | |
d0c94692 | 5604 | DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n", |
25933820 | 5605 | connector->name, info->bpc); |
d0c94692 | 5606 | |
ee58808d | 5607 | if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) |
c03d0b52 | 5608 | info->color_formats |= DRM_COLOR_FORMAT_YCBCR444; |
ee58808d | 5609 | if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) |
c03d0b52 | 5610 | info->color_formats |= DRM_COLOR_FORMAT_YCBCR422; |
18a9cbbe JN |
5611 | |
5612 | drm_update_mso(connector, edid); | |
5613 | ||
ce99534e JN |
5614 | out: |
5615 | if (quirks & EDID_QUIRK_NON_DESKTOP) { | |
5616 | drm_dbg_kms(connector->dev, "Non-desktop display%s\n", | |
5617 | info->non_desktop ? " (redundant quirk)" : ""); | |
5618 | info->non_desktop = true; | |
5619 | } | |
5620 | ||
170178fe | 5621 | return quirks; |
3b11228b JB |
5622 | } |
5623 | ||
a39ed680 | 5624 | static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, |
80ecb5d7 YB |
5625 | struct displayid_detailed_timings_1 *timings, |
5626 | bool type_7) | |
a39ed680 DA |
5627 | { |
5628 | struct drm_display_mode *mode; | |
5629 | unsigned pixel_clock = (timings->pixel_clock[0] | | |
5630 | (timings->pixel_clock[1] << 8) | | |
6292b8ef | 5631 | (timings->pixel_clock[2] << 16)) + 1; |
a39ed680 DA |
5632 | unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; |
5633 | unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; | |
5634 | unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1; | |
5635 | unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; | |
5636 | unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1; | |
5637 | unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; | |
5638 | unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1; | |
5639 | unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; | |
5640 | bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; | |
5641 | bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; | |
948de842 | 5642 | |
a39ed680 DA |
5643 | mode = drm_mode_create(dev); |
5644 | if (!mode) | |
5645 | return NULL; | |
5646 | ||
80ecb5d7 YB |
5647 | /* resolution is kHz for type VII, and 10 kHz for type I */ |
5648 | mode->clock = type_7 ? pixel_clock : pixel_clock * 10; | |
a39ed680 DA |
5649 | mode->hdisplay = hactive; |
5650 | mode->hsync_start = mode->hdisplay + hsync; | |
5651 | mode->hsync_end = mode->hsync_start + hsync_width; | |
5652 | mode->htotal = mode->hdisplay + hblank; | |
5653 | ||
5654 | mode->vdisplay = vactive; | |
5655 | mode->vsync_start = mode->vdisplay + vsync; | |
5656 | mode->vsync_end = mode->vsync_start + vsync_width; | |
5657 | mode->vtotal = mode->vdisplay + vblank; | |
5658 | ||
5659 | mode->flags = 0; | |
5660 | mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; | |
5661 | mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; | |
5662 | mode->type = DRM_MODE_TYPE_DRIVER; | |
5663 | ||
5664 | if (timings->flags & 0x80) | |
5665 | mode->type |= DRM_MODE_TYPE_PREFERRED; | |
a39ed680 DA |
5666 | drm_mode_set_name(mode); |
5667 | ||
5668 | return mode; | |
5669 | } | |
5670 | ||
5671 | static int add_displayid_detailed_1_modes(struct drm_connector *connector, | |
43d16d84 | 5672 | const struct displayid_block *block) |
a39ed680 DA |
5673 | { |
5674 | struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block; | |
5675 | int i; | |
5676 | int num_timings; | |
5677 | struct drm_display_mode *newmode; | |
5678 | int num_modes = 0; | |
80ecb5d7 | 5679 | bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING; |
a39ed680 DA |
5680 | /* blocks must be multiple of 20 bytes length */ |
5681 | if (block->num_bytes % 20) | |
5682 | return 0; | |
5683 | ||
5684 | num_timings = block->num_bytes / 20; | |
5685 | for (i = 0; i < num_timings; i++) { | |
5686 | struct displayid_detailed_timings_1 *timings = &det->timings[i]; | |
5687 | ||
80ecb5d7 | 5688 | newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7); |
a39ed680 DA |
5689 | if (!newmode) |
5690 | continue; | |
5691 | ||
5692 | drm_mode_probed_add(connector, newmode); | |
5693 | num_modes++; | |
5694 | } | |
5695 | return num_modes; | |
5696 | } | |
5697 | ||
5698 | static int add_displayid_detailed_modes(struct drm_connector *connector, | |
f4e558ec | 5699 | const struct edid *edid) |
a39ed680 | 5700 | { |
43d16d84 | 5701 | const struct displayid_block *block; |
5ef88dc5 | 5702 | struct displayid_iter iter; |
a39ed680 DA |
5703 | int num_modes = 0; |
5704 | ||
5ef88dc5 JN |
5705 | displayid_iter_edid_begin(edid, &iter); |
5706 | displayid_iter_for_each(block, &iter) { | |
80ecb5d7 YB |
5707 | if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING || |
5708 | block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING) | |
5ef88dc5 | 5709 | num_modes += add_displayid_detailed_1_modes(connector, block); |
a39ed680 | 5710 | } |
5ef88dc5 | 5711 | displayid_iter_end(&iter); |
7f261afd | 5712 | |
a39ed680 DA |
5713 | return num_modes; |
5714 | } | |
5715 | ||
f40ab034 JN |
5716 | static int drm_edid_connector_update(struct drm_connector *connector, |
5717 | const struct edid *edid) | |
f453ba04 DA |
5718 | { |
5719 | int num_modes = 0; | |
5720 | u32 quirks; | |
5721 | ||
5722 | if (edid == NULL) { | |
c945b8c1 | 5723 | clear_eld(connector); |
f453ba04 DA |
5724 | return 0; |
5725 | } | |
f453ba04 | 5726 | |
c945b8c1 JN |
5727 | drm_edid_to_eld(connector, edid); |
5728 | ||
0f0f8708 SS |
5729 | /* |
5730 | * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks. | |
5731 | * To avoid multiple parsing of same block, lets parse that map | |
5732 | * from sink info, before parsing CEA modes. | |
5733 | */ | |
170178fe | 5734 | quirks = drm_add_display_info(connector, edid); |
0f0f8708 | 5735 | |
c867df70 AJ |
5736 | /* |
5737 | * EDID spec says modes should be preferred in this order: | |
5738 | * - preferred detailed mode | |
5739 | * - other detailed modes from base block | |
5740 | * - detailed modes from extension blocks | |
5741 | * - CVT 3-byte code modes | |
5742 | * - standard timing codes | |
5743 | * - established timing codes | |
5744 | * - modes inferred from GTF or CVT range information | |
5745 | * | |
13931579 | 5746 | * We get this pretty much right. |
c867df70 AJ |
5747 | * |
5748 | * XXX order for additional mode types in extension blocks? | |
5749 | */ | |
13931579 AJ |
5750 | num_modes += add_detailed_modes(connector, edid, quirks); |
5751 | num_modes += add_cvt_modes(connector, edid); | |
c867df70 AJ |
5752 | num_modes += add_standard_modes(connector, edid); |
5753 | num_modes += add_established_modes(connector, edid); | |
54ac76f8 | 5754 | num_modes += add_cea_modes(connector, edid); |
e6e79209 | 5755 | num_modes += add_alternate_cea_modes(connector, edid); |
a39ed680 | 5756 | num_modes += add_displayid_detailed_modes(connector, edid); |
4d53dc0c VS |
5757 | if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) |
5758 | num_modes += add_inferred_modes(connector, edid); | |
f453ba04 DA |
5759 | |
5760 | if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) | |
5761 | edid_fixup_preferred(connector, quirks); | |
5762 | ||
e10aec65 MK |
5763 | if (quirks & EDID_QUIRK_FORCE_6BPC) |
5764 | connector->display_info.bpc = 6; | |
5765 | ||
49d45a31 RM |
5766 | if (quirks & EDID_QUIRK_FORCE_8BPC) |
5767 | connector->display_info.bpc = 8; | |
5768 | ||
e345da82 MK |
5769 | if (quirks & EDID_QUIRK_FORCE_10BPC) |
5770 | connector->display_info.bpc = 10; | |
5771 | ||
bc5b9641 MK |
5772 | if (quirks & EDID_QUIRK_FORCE_12BPC) |
5773 | connector->display_info.bpc = 12; | |
5774 | ||
f453ba04 DA |
5775 | return num_modes; |
5776 | } | |
f40ab034 JN |
5777 | |
5778 | /** | |
5779 | * drm_add_edid_modes - add modes from EDID data, if available | |
5780 | * @connector: connector we're probing | |
5781 | * @edid: EDID data | |
5782 | * | |
5783 | * Add the specified modes to the connector's mode list. Also fills out the | |
5784 | * &drm_display_info structure and ELD in @connector with any information which | |
5785 | * can be derived from the edid. | |
5786 | * | |
5787 | * Return: The number of modes added or 0 if we couldn't find any. | |
5788 | */ | |
5789 | int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) | |
5790 | { | |
5791 | if (edid && !drm_edid_is_valid(edid)) { | |
5792 | drm_warn(connector->dev, "%s: EDID invalid.\n", | |
5793 | connector->name); | |
5794 | edid = NULL; | |
5795 | } | |
5796 | ||
5797 | return drm_edid_connector_update(connector, edid); | |
5798 | } | |
f453ba04 | 5799 | EXPORT_SYMBOL(drm_add_edid_modes); |
f0fda0a4 ZY |
5800 | |
5801 | /** | |
5802 | * drm_add_modes_noedid - add modes for the connectors without EDID | |
5803 | * @connector: connector we're probing | |
5804 | * @hdisplay: the horizontal display limit | |
5805 | * @vdisplay: the vertical display limit | |
5806 | * | |
5807 | * Add the specified modes to the connector's mode list. Only when the | |
5808 | * hdisplay/vdisplay is not beyond the given limit, it will be added. | |
5809 | * | |
db6cf833 | 5810 | * Return: The number of modes added or 0 if we couldn't find any. |
f0fda0a4 ZY |
5811 | */ |
5812 | int drm_add_modes_noedid(struct drm_connector *connector, | |
5813 | int hdisplay, int vdisplay) | |
5814 | { | |
5815 | int i, count, num_modes = 0; | |
b1f559ec | 5816 | struct drm_display_mode *mode; |
f0fda0a4 ZY |
5817 | struct drm_device *dev = connector->dev; |
5818 | ||
fbb40b28 | 5819 | count = ARRAY_SIZE(drm_dmt_modes); |
f0fda0a4 ZY |
5820 | if (hdisplay < 0) |
5821 | hdisplay = 0; | |
5822 | if (vdisplay < 0) | |
5823 | vdisplay = 0; | |
5824 | ||
5825 | for (i = 0; i < count; i++) { | |
b1f559ec | 5826 | const struct drm_display_mode *ptr = &drm_dmt_modes[i]; |
948de842 | 5827 | |
f0fda0a4 ZY |
5828 | if (hdisplay && vdisplay) { |
5829 | /* | |
5830 | * Only when two are valid, they will be used to check | |
5831 | * whether the mode should be added to the mode list of | |
5832 | * the connector. | |
5833 | */ | |
5834 | if (ptr->hdisplay > hdisplay || | |
5835 | ptr->vdisplay > vdisplay) | |
5836 | continue; | |
5837 | } | |
f985dedb AJ |
5838 | if (drm_mode_vrefresh(ptr) > 61) |
5839 | continue; | |
f0fda0a4 ZY |
5840 | mode = drm_mode_duplicate(dev, ptr); |
5841 | if (mode) { | |
5842 | drm_mode_probed_add(connector, mode); | |
5843 | num_modes++; | |
5844 | } | |
5845 | } | |
5846 | return num_modes; | |
5847 | } | |
5848 | EXPORT_SYMBOL(drm_add_modes_noedid); | |
10a85120 | 5849 | |
db6cf833 TR |
5850 | /** |
5851 | * drm_set_preferred_mode - Sets the preferred mode of a connector | |
5852 | * @connector: connector whose mode list should be processed | |
5853 | * @hpref: horizontal resolution of preferred mode | |
5854 | * @vpref: vertical resolution of preferred mode | |
5855 | * | |
5856 | * Marks a mode as preferred if it matches the resolution specified by @hpref | |
5857 | * and @vpref. | |
5858 | */ | |
3cf70daf GH |
5859 | void drm_set_preferred_mode(struct drm_connector *connector, |
5860 | int hpref, int vpref) | |
5861 | { | |
5862 | struct drm_display_mode *mode; | |
5863 | ||
5864 | list_for_each_entry(mode, &connector->probed_modes, head) { | |
db6cf833 | 5865 | if (mode->hdisplay == hpref && |
9d3de138 | 5866 | mode->vdisplay == vpref) |
3cf70daf GH |
5867 | mode->type |= DRM_MODE_TYPE_PREFERRED; |
5868 | } | |
5869 | } | |
5870 | EXPORT_SYMBOL(drm_set_preferred_mode); | |
5871 | ||
192a3aa0 | 5872 | static bool is_hdmi2_sink(const struct drm_connector *connector) |
13d0add3 VS |
5873 | { |
5874 | /* | |
5875 | * FIXME: sil-sii8620 doesn't have a connector around when | |
5876 | * we need one, so we have to be prepared for a NULL connector. | |
5877 | */ | |
5878 | if (!connector) | |
5879 | return true; | |
5880 | ||
5881 | return connector->display_info.hdmi.scdc.supported || | |
c03d0b52 | 5882 | connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR420; |
13d0add3 VS |
5883 | } |
5884 | ||
192a3aa0 | 5885 | static u8 drm_mode_hdmi_vic(const struct drm_connector *connector, |
949561eb VS |
5886 | const struct drm_display_mode *mode) |
5887 | { | |
5888 | bool has_hdmi_infoframe = connector ? | |
5889 | connector->display_info.has_hdmi_infoframe : false; | |
5890 | ||
5891 | if (!has_hdmi_infoframe) | |
5892 | return 0; | |
5893 | ||
5894 | /* No HDMI VIC when signalling 3D video format */ | |
5895 | if (mode->flags & DRM_MODE_FLAG_3D_MASK) | |
5896 | return 0; | |
5897 | ||
5898 | return drm_match_hdmi_mode(mode); | |
5899 | } | |
5900 | ||
192a3aa0 | 5901 | static u8 drm_mode_cea_vic(const struct drm_connector *connector, |
cfd6f8c3 VS |
5902 | const struct drm_display_mode *mode) |
5903 | { | |
cfd6f8c3 VS |
5904 | u8 vic; |
5905 | ||
5906 | /* | |
5907 | * HDMI spec says if a mode is found in HDMI 1.4b 4K modes | |
5908 | * we should send its VIC in vendor infoframes, else send the | |
5909 | * VIC in AVI infoframes. Lets check if this mode is present in | |
5910 | * HDMI 1.4b 4K modes | |
5911 | */ | |
949561eb | 5912 | if (drm_mode_hdmi_vic(connector, mode)) |
cfd6f8c3 VS |
5913 | return 0; |
5914 | ||
5915 | vic = drm_match_cea_mode(mode); | |
5916 | ||
5917 | /* | |
5918 | * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but | |
5919 | * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we | |
5920 | * have to make sure we dont break HDMI 1.4 sinks. | |
5921 | */ | |
5922 | if (!is_hdmi2_sink(connector) && vic > 64) | |
5923 | return 0; | |
5924 | ||
5925 | return vic; | |
5926 | } | |
5927 | ||
10a85120 TR |
5928 | /** |
5929 | * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with | |
5930 | * data from a DRM display mode | |
5931 | * @frame: HDMI AVI infoframe | |
13d0add3 | 5932 | * @connector: the connector |
10a85120 TR |
5933 | * @mode: DRM display mode |
5934 | * | |
db6cf833 | 5935 | * Return: 0 on success or a negative error code on failure. |
10a85120 TR |
5936 | */ |
5937 | int | |
5938 | drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, | |
192a3aa0 | 5939 | const struct drm_connector *connector, |
13d0add3 | 5940 | const struct drm_display_mode *mode) |
10a85120 | 5941 | { |
a9c266c2 | 5942 | enum hdmi_picture_aspect picture_aspect; |
d2b43473 | 5943 | u8 vic, hdmi_vic; |
10a85120 TR |
5944 | |
5945 | if (!frame || !mode) | |
5946 | return -EINVAL; | |
5947 | ||
5ee0caf1 | 5948 | hdmi_avi_infoframe_init(frame); |
10a85120 | 5949 | |
bf02db99 DL |
5950 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
5951 | frame->pixel_repeat = 1; | |
5952 | ||
d2b43473 WL |
5953 | vic = drm_mode_cea_vic(connector, mode); |
5954 | hdmi_vic = drm_mode_hdmi_vic(connector, mode); | |
0c1f528c | 5955 | |
10a85120 | 5956 | frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; |
0967e6a5 | 5957 | |
50525c33 SL |
5958 | /* |
5959 | * As some drivers don't support atomic, we can't use connector state. | |
5960 | * So just initialize the frame with default values, just the same way | |
5961 | * as it's done with other properties here. | |
5962 | */ | |
5963 | frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS; | |
5964 | frame->itc = 0; | |
5965 | ||
69ab6d35 VK |
5966 | /* |
5967 | * Populate picture aspect ratio from either | |
d2b43473 | 5968 | * user input (if specified) or from the CEA/HDMI mode lists. |
69ab6d35 | 5969 | */ |
a9c266c2 | 5970 | picture_aspect = mode->picture_aspect_ratio; |
d2b43473 WL |
5971 | if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) { |
5972 | if (vic) | |
5973 | picture_aspect = drm_get_cea_aspect_ratio(vic); | |
5974 | else if (hdmi_vic) | |
5975 | picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic); | |
5976 | } | |
0967e6a5 | 5977 | |
a9c266c2 VS |
5978 | /* |
5979 | * The infoframe can't convey anything but none, 4:3 | |
5980 | * and 16:9, so if the user has asked for anything else | |
5981 | * we can only satisfy it by specifying the right VIC. | |
5982 | */ | |
5983 | if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) { | |
d2b43473 WL |
5984 | if (vic) { |
5985 | if (picture_aspect != drm_get_cea_aspect_ratio(vic)) | |
5986 | return -EINVAL; | |
5987 | } else if (hdmi_vic) { | |
5988 | if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic)) | |
5989 | return -EINVAL; | |
5990 | } else { | |
a9c266c2 | 5991 | return -EINVAL; |
d2b43473 WL |
5992 | } |
5993 | ||
a9c266c2 VS |
5994 | picture_aspect = HDMI_PICTURE_ASPECT_NONE; |
5995 | } | |
5996 | ||
d2b43473 | 5997 | frame->video_code = vic; |
a9c266c2 | 5998 | frame->picture_aspect = picture_aspect; |
10a85120 | 5999 | frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; |
24d01805 | 6000 | frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; |
10a85120 TR |
6001 | |
6002 | return 0; | |
6003 | } | |
6004 | EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); | |
83dd0008 | 6005 | |
a2ce26f8 VS |
6006 | /** |
6007 | * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe | |
6008 | * quantization range information | |
6009 | * @frame: HDMI AVI infoframe | |
13d0add3 | 6010 | * @connector: the connector |
779c4c28 | 6011 | * @mode: DRM display mode |
a2ce26f8 | 6012 | * @rgb_quant_range: RGB quantization range (Q) |
a2ce26f8 VS |
6013 | */ |
6014 | void | |
6015 | drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, | |
192a3aa0 | 6016 | const struct drm_connector *connector, |
779c4c28 | 6017 | const struct drm_display_mode *mode, |
1581b2df | 6018 | enum hdmi_quantization_range rgb_quant_range) |
a2ce26f8 | 6019 | { |
1581b2df VS |
6020 | const struct drm_display_info *info = &connector->display_info; |
6021 | ||
a2ce26f8 VS |
6022 | /* |
6023 | * CEA-861: | |
6024 | * "A Source shall not send a non-zero Q value that does not correspond | |
6025 | * to the default RGB Quantization Range for the transmitted Picture | |
6026 | * unless the Sink indicates support for the Q bit in a Video | |
6027 | * Capabilities Data Block." | |
779c4c28 VS |
6028 | * |
6029 | * HDMI 2.0 recommends sending non-zero Q when it does match the | |
6030 | * default RGB quantization range for the mode, even when QS=0. | |
a2ce26f8 | 6031 | */ |
1581b2df | 6032 | if (info->rgb_quant_range_selectable || |
779c4c28 | 6033 | rgb_quant_range == drm_default_rgb_quant_range(mode)) |
a2ce26f8 VS |
6034 | frame->quantization_range = rgb_quant_range; |
6035 | else | |
6036 | frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; | |
fcc8a22c VS |
6037 | |
6038 | /* | |
6039 | * CEA-861-F: | |
6040 | * "When transmitting any RGB colorimetry, the Source should set the | |
6041 | * YQ-field to match the RGB Quantization Range being transmitted | |
6042 | * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, | |
6043 | * set YQ=1) and the Sink shall ignore the YQ-field." | |
9271c0ca VS |
6044 | * |
6045 | * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused | |
6046 | * by non-zero YQ when receiving RGB. There doesn't seem to be any | |
6047 | * good way to tell which version of CEA-861 the sink supports, so | |
6048 | * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based | |
6049 | * on on CEA-861-F. | |
fcc8a22c | 6050 | */ |
13d0add3 | 6051 | if (!is_hdmi2_sink(connector) || |
9271c0ca | 6052 | rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) |
fcc8a22c VS |
6053 | frame->ycc_quantization_range = |
6054 | HDMI_YCC_QUANTIZATION_RANGE_LIMITED; | |
6055 | else | |
6056 | frame->ycc_quantization_range = | |
6057 | HDMI_YCC_QUANTIZATION_RANGE_FULL; | |
a2ce26f8 VS |
6058 | } |
6059 | EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range); | |
6060 | ||
4eed4a0a DL |
6061 | static enum hdmi_3d_structure |
6062 | s3d_structure_from_display_mode(const struct drm_display_mode *mode) | |
6063 | { | |
6064 | u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; | |
6065 | ||
6066 | switch (layout) { | |
6067 | case DRM_MODE_FLAG_3D_FRAME_PACKING: | |
6068 | return HDMI_3D_STRUCTURE_FRAME_PACKING; | |
6069 | case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: | |
6070 | return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; | |
6071 | case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: | |
6072 | return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; | |
6073 | case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: | |
6074 | return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; | |
6075 | case DRM_MODE_FLAG_3D_L_DEPTH: | |
6076 | return HDMI_3D_STRUCTURE_L_DEPTH; | |
6077 | case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: | |
6078 | return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; | |
6079 | case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: | |
6080 | return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; | |
6081 | case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: | |
6082 | return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; | |
6083 | default: | |
6084 | return HDMI_3D_STRUCTURE_INVALID; | |
6085 | } | |
6086 | } | |
6087 | ||
83dd0008 LD |
6088 | /** |
6089 | * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with | |
6090 | * data from a DRM display mode | |
6091 | * @frame: HDMI vendor infoframe | |
f1781e9b | 6092 | * @connector: the connector |
83dd0008 LD |
6093 | * @mode: DRM display mode |
6094 | * | |
6095 | * Note that there's is a need to send HDMI vendor infoframes only when using a | |
6096 | * 4k or stereoscopic 3D mode. So when giving any other mode as input this | |
6097 | * function will return -EINVAL, error that can be safely ignored. | |
6098 | * | |
db6cf833 | 6099 | * Return: 0 on success or a negative error code on failure. |
83dd0008 LD |
6100 | */ |
6101 | int | |
6102 | drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, | |
192a3aa0 | 6103 | const struct drm_connector *connector, |
83dd0008 LD |
6104 | const struct drm_display_mode *mode) |
6105 | { | |
f1781e9b VS |
6106 | /* |
6107 | * FIXME: sil-sii8620 doesn't have a connector around when | |
6108 | * we need one, so we have to be prepared for a NULL connector. | |
6109 | */ | |
6110 | bool has_hdmi_infoframe = connector ? | |
6111 | connector->display_info.has_hdmi_infoframe : false; | |
83dd0008 | 6112 | int err; |
83dd0008 LD |
6113 | |
6114 | if (!frame || !mode) | |
6115 | return -EINVAL; | |
6116 | ||
f1781e9b VS |
6117 | if (!has_hdmi_infoframe) |
6118 | return -EINVAL; | |
6119 | ||
949561eb VS |
6120 | err = hdmi_vendor_infoframe_init(frame); |
6121 | if (err < 0) | |
6122 | return err; | |
4eed4a0a | 6123 | |
f1781e9b VS |
6124 | /* |
6125 | * Even if it's not absolutely necessary to send the infoframe | |
6126 | * (ie.vic==0 and s3d_struct==0) we will still send it if we | |
6127 | * know that the sink can handle it. This is based on a | |
6128 | * suggestion in HDMI 2.0 Appendix F. Apparently some sinks | |
0ae865ef | 6129 | * have trouble realizing that they should switch from 3D to 2D |
f1781e9b VS |
6130 | * mode if the source simply stops sending the infoframe when |
6131 | * it wants to switch from 3D to 2D. | |
6132 | */ | |
949561eb | 6133 | frame->vic = drm_mode_hdmi_vic(connector, mode); |
f1781e9b | 6134 | frame->s3d_struct = s3d_structure_from_display_mode(mode); |
83dd0008 LD |
6135 | |
6136 | return 0; | |
6137 | } | |
6138 | EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); | |
40d9b043 | 6139 | |
7f261afd VS |
6140 | static void drm_parse_tiled_block(struct drm_connector *connector, |
6141 | const struct displayid_block *block) | |
5e546cd5 | 6142 | { |
092c367a | 6143 | const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; |
5e546cd5 DA |
6144 | u16 w, h; |
6145 | u8 tile_v_loc, tile_h_loc; | |
6146 | u8 num_v_tile, num_h_tile; | |
6147 | struct drm_tile_group *tg; | |
6148 | ||
6149 | w = tile->tile_size[0] | tile->tile_size[1] << 8; | |
6150 | h = tile->tile_size[2] | tile->tile_size[3] << 8; | |
6151 | ||
6152 | num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); | |
6153 | num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); | |
6154 | tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); | |
6155 | tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); | |
6156 | ||
6157 | connector->has_tile = true; | |
6158 | if (tile->tile_cap & 0x80) | |
6159 | connector->tile_is_single_monitor = true; | |
6160 | ||
6161 | connector->num_h_tile = num_h_tile + 1; | |
6162 | connector->num_v_tile = num_v_tile + 1; | |
6163 | connector->tile_h_loc = tile_h_loc; | |
6164 | connector->tile_v_loc = tile_v_loc; | |
6165 | connector->tile_h_size = w + 1; | |
6166 | connector->tile_v_size = h + 1; | |
6167 | ||
6168 | DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap); | |
6169 | DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1); | |
6170 | DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n", | |
6171 | num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc); | |
6172 | DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); | |
6173 | ||
6174 | tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); | |
392f9fcb | 6175 | if (!tg) |
5e546cd5 | 6176 | tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); |
5e546cd5 | 6177 | if (!tg) |
7f261afd | 6178 | return; |
5e546cd5 DA |
6179 | |
6180 | if (connector->tile_group != tg) { | |
6181 | /* if we haven't got a pointer, | |
6182 | take the reference, drop ref to old tile group */ | |
392f9fcb | 6183 | if (connector->tile_group) |
5e546cd5 | 6184 | drm_mode_put_tile_group(connector->dev, connector->tile_group); |
5e546cd5 | 6185 | connector->tile_group = tg; |
392f9fcb | 6186 | } else { |
5e546cd5 DA |
6187 | /* if same tile group, then release the ref we just took. */ |
6188 | drm_mode_put_tile_group(connector->dev, tg); | |
392f9fcb | 6189 | } |
5e546cd5 DA |
6190 | } |
6191 | ||
092c367a VS |
6192 | void drm_update_tile_info(struct drm_connector *connector, |
6193 | const struct edid *edid) | |
40d9b043 | 6194 | { |
bfd4e192 JN |
6195 | const struct displayid_block *block; |
6196 | struct displayid_iter iter; | |
36881184 | 6197 | |
40d9b043 | 6198 | connector->has_tile = false; |
7f261afd | 6199 | |
bfd4e192 JN |
6200 | displayid_iter_edid_begin(edid, &iter); |
6201 | displayid_iter_for_each(block, &iter) { | |
6202 | if (block->tag == DATA_BLOCK_TILED_DISPLAY) | |
6203 | drm_parse_tiled_block(connector, block); | |
40d9b043 | 6204 | } |
bfd4e192 | 6205 | displayid_iter_end(&iter); |
40d9b043 | 6206 | |
7f261afd | 6207 | if (!connector->has_tile && connector->tile_group) { |
40d9b043 DA |
6208 | drm_mode_put_tile_group(connector->dev, connector->tile_group); |
6209 | connector->tile_group = NULL; | |
6210 | } | |
40d9b043 | 6211 | } |