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drm: Add helper to compare edids.
[linux-2.6-block.git] / drivers / gpu / drm / drm_edid.c
CommitLineData
f453ba04
DA		 1/*
2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
61e57a8d 5 * Copyright 2010 Red Hat, Inc.
f453ba04
DA		 6 *
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
8 * FB layer.
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 */
9c79edec 30
10a85120 31#include <linux/hdmi.h>
f453ba04 32#include <linux/i2c.h>
9c79edec 33#include <linux/kernel.h>
47819ba2 34#include <linux/module.h>
9c79edec 35#include <linux/slab.h>
5cb8eaa2 36#include <linux/vga_switcheroo.h>
9c79edec
JN		 37
38#include <drm/drm_displayid.h>
39#include <drm/drm_drv.h>
760285e7 40#include <drm/drm_edid.h>
9338203c 41#include <drm/drm_encoder.h>
9c79edec 42#include <drm/drm_print.h>
62c58af3 43#include <drm/drm_scdc_helper.h>
f453ba04 44
969218fe
TI		 45#include "drm_crtc_internal.h"
46
13931579
AJ		 47#define version_greater(edid, maj, min) \
48 (((edid)->version > (maj)) || \
49 ((edid)->version == (maj) && (edid)->revision > (min)))
f453ba04 50
d1ff6409
AJ		 51#define EDID_EST_TIMINGS 16
52#define EDID_STD_TIMINGS 8
53#define EDID_DETAILED_TIMINGS 4
f453ba04
DA		 54
55/*
56 * EDID blocks out in the wild have a variety of bugs, try to collect
57 * them here (note that userspace may work around broken monitors first,
58 * but fixes should make their way here so that the kernel "just works"
59 * on as many displays as possible).
60 */
61
62/* First detailed mode wrong, use largest 60Hz mode */
63#define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
64/* Reported 135MHz pixel clock is too high, needs adjustment */
65#define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
66/* Prefer the largest mode at 75 Hz */
67#define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
68/* Detail timing is in cm not mm */
69#define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
70/* Detailed timing descriptors have bogus size values, so just take the
71 * maximum size and use that.
72 */
73#define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
f453ba04
DA		 74/* use +hsync +vsync for detailed mode */
75#define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
bc42aabc
AJ		 76/* Force reduced-blanking timings for detailed modes */
77#define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
49d45a31
RM		 78/* Force 8bpc */
79#define EDID_QUIRK_FORCE_8BPC (1 << 8)
bc5b9641
MK		 80/* Force 12bpc */
81#define EDID_QUIRK_FORCE_12BPC (1 << 9)
e10aec65
MK		 82/* Force 6bpc */
83#define EDID_QUIRK_FORCE_6BPC (1 << 10)
e345da82
MK		 84/* Force 10bpc */
85#define EDID_QUIRK_FORCE_10BPC (1 << 11)
66660d4c
DA		 86/* Non desktop display (i.e. HMD) */
87#define EDID_QUIRK_NON_DESKTOP (1 << 12)
3c537889 88
13931579
AJ		 89struct detailed_mode_closure {
90 struct drm_connector *connector;
91 struct edid *edid;
92 bool preferred;
93 u32 quirks;
94 int modes;
95};
f453ba04 96
5c61259e
ZY		 97#define LEVEL_DMT 0
98#define LEVEL_GTF 1
7a374350
AJ		 99#define LEVEL_GTF2 2
100#define LEVEL_CVT 3
5c61259e 101
23c4cfbd 102static const struct edid_quirk {
c51a3fd6 103 char vendor[4];
f453ba04
DA		 104 int product_id;
105 u32 quirks;
106} edid_quirk_list[] = {
107 /* Acer AL1706 */
108 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
109 /* Acer F51 */
110 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
f453ba04 111
e10aec65
MK		 112 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
113 { "AEO", 0, EDID_QUIRK_FORCE_6BPC },
114
0711a43b
KHF		 115 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
116 { "BOE", 0x78b, EDID_QUIRK_FORCE_6BPC },
117
06998a75
KHF		 118 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
119 { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC },
120
25da7504
KHF		 121 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
122 { "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC },
123
922dceff
LS		 124 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
125 { "BOE", 0x0771, EDID_QUIRK_FORCE_6BPC },
126
f453ba04
DA		 127 /* Belinea 10 15 55 */
128 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
129 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
130
131 /* Envision Peripherals, Inc. EN-7100e */
132 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
ba1163de
AJ		 133 /* Envision EN2028 */
134 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
f453ba04
DA		 135
136 /* Funai Electronics PM36B */
137 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
138 EDID_QUIRK_DETAILED_IN_CM },
139
e345da82
MK		 140 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
141 { "LGD", 764, EDID_QUIRK_FORCE_10BPC },
142
f453ba04
DA		 143 /* LG Philips LCD LP154W01-A5 */
144 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
145 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
146
f453ba04
DA		 147 /* Samsung SyncMaster 205BW. Note: irony */
148 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
149 /* Samsung SyncMaster 22[5-6]BW */
150 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
151 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
bc42aabc 152
bc5b9641
MK		 153 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
154 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
155
bc42aabc
AJ		 156 /* ViewSonic VA2026w */
157 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
118bdbd8
AD		 158
159 /* Medion MD 30217 PG */
160 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
49d45a31 161
11bcf5f7
KHF		 162 /* Lenovo G50 */
163 { "SDC", 18514, EDID_QUIRK_FORCE_6BPC },
164
49d45a31
RM		 165 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
166 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
36fc5797
TV		 167
168 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
169 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC },
acb1d8ee 170
30d62d44
AR		 171 /* Valve Index Headset */
172 { "VLV", 0x91a8, EDID_QUIRK_NON_DESKTOP },
173 { "VLV", 0x91b0, EDID_QUIRK_NON_DESKTOP },
174 { "VLV", 0x91b1, EDID_QUIRK_NON_DESKTOP },
175 { "VLV", 0x91b2, EDID_QUIRK_NON_DESKTOP },
176 { "VLV", 0x91b3, EDID_QUIRK_NON_DESKTOP },
177 { "VLV", 0x91b4, EDID_QUIRK_NON_DESKTOP },
178 { "VLV", 0x91b5, EDID_QUIRK_NON_DESKTOP },
179 { "VLV", 0x91b6, EDID_QUIRK_NON_DESKTOP },
180 { "VLV", 0x91b7, EDID_QUIRK_NON_DESKTOP },
181 { "VLV", 0x91b8, EDID_QUIRK_NON_DESKTOP },
182 { "VLV", 0x91b9, EDID_QUIRK_NON_DESKTOP },
183 { "VLV", 0x91ba, EDID_QUIRK_NON_DESKTOP },
184 { "VLV", 0x91bb, EDID_QUIRK_NON_DESKTOP },
185 { "VLV", 0x91bc, EDID_QUIRK_NON_DESKTOP },
186 { "VLV", 0x91bd, EDID_QUIRK_NON_DESKTOP },
187 { "VLV", 0x91be, EDID_QUIRK_NON_DESKTOP },
188 { "VLV", 0x91bf, EDID_QUIRK_NON_DESKTOP },
189
6931317c 190 /* HTC Vive and Vive Pro VR Headsets */
acb1d8ee 191 { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP },
6931317c 192 { "HVR", 0xaa02, EDID_QUIRK_NON_DESKTOP },
b3b12ea3 193
5a3f6108 194 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */
b3b12ea3
PZ		 195 { "OVR", 0x0001, EDID_QUIRK_NON_DESKTOP },
196 { "OVR", 0x0003, EDID_QUIRK_NON_DESKTOP },
197 { "OVR", 0x0004, EDID_QUIRK_NON_DESKTOP },
5a3f6108 198 { "OVR", 0x0012, EDID_QUIRK_NON_DESKTOP },
90eda8fc
PZ		 199
200 /* Windows Mixed Reality Headsets */
201 { "ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP },
202 { "HPN", 0x3515, EDID_QUIRK_NON_DESKTOP },
203 { "LEN", 0x0408, EDID_QUIRK_NON_DESKTOP },
204 { "LEN", 0xb800, EDID_QUIRK_NON_DESKTOP },
205 { "FUJ", 0x1970, EDID_QUIRK_NON_DESKTOP },
206 { "DEL", 0x7fce, EDID_QUIRK_NON_DESKTOP },
207 { "SEC", 0x144a, EDID_QUIRK_NON_DESKTOP },
208 { "AUS", 0xc102, EDID_QUIRK_NON_DESKTOP },
ccffc9eb
PZ		 209
210 /* Sony PlayStation VR Headset */
211 { "SNY", 0x0704, EDID_QUIRK_NON_DESKTOP },
29054230
RP		 212
213 /* Sensics VR Headsets */
214 { "SEN", 0x1019, EDID_QUIRK_NON_DESKTOP },
215
216 /* OSVR HDK and HDK2 VR Headsets */
217 { "SVR", 0x1019, EDID_QUIRK_NON_DESKTOP },
f453ba04
DA		 218};
219
a6b21831
TR		 220/*
221 * Autogenerated from the DMT spec.
222 * This table is copied from xfree86/modes/xf86EdidModes.c.
223 */
224static const struct drm_display_mode drm_dmt_modes[] = {
24b856b1 225 /* 0x01 - 640x350@85Hz */
a6b21831
TR		 226 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
227 736, 832, 0, 350, 382, 385, 445, 0,
228 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 229 /* 0x02 - 640x400@85Hz */
a6b21831
TR		 230 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
231 736, 832, 0, 400, 401, 404, 445, 0,
232 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 233 /* 0x03 - 720x400@85Hz */
a6b21831
TR		 234 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
235 828, 936, 0, 400, 401, 404, 446, 0,
236 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 237 /* 0x04 - 640x480@60Hz */
a6b21831 238 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
fcf22d05 239 752, 800, 0, 480, 490, 492, 525, 0,
a6b21831 240 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 241 /* 0x05 - 640x480@72Hz */
a6b21831
TR		 242 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
243 704, 832, 0, 480, 489, 492, 520, 0,
244 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 245 /* 0x06 - 640x480@75Hz */
a6b21831
TR		 246 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
247 720, 840, 0, 480, 481, 484, 500, 0,
248 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 249 /* 0x07 - 640x480@85Hz */
a6b21831
TR		 250 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
251 752, 832, 0, 480, 481, 484, 509, 0,
252 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 253 /* 0x08 - 800x600@56Hz */
a6b21831
TR		 254 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
255 896, 1024, 0, 600, 601, 603, 625, 0,
256 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 257 /* 0x09 - 800x600@60Hz */
a6b21831
TR		 258 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
259 968, 1056, 0, 600, 601, 605, 628, 0,
260 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 261 /* 0x0a - 800x600@72Hz */
a6b21831
TR		 262 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
263 976, 1040, 0, 600, 637, 643, 666, 0,
264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 265 /* 0x0b - 800x600@75Hz */
a6b21831
TR		 266 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
267 896, 1056, 0, 600, 601, 604, 625, 0,
268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 269 /* 0x0c - 800x600@85Hz */
a6b21831
TR		 270 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
271 896, 1048, 0, 600, 601, 604, 631, 0,
272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 273 /* 0x0d - 800x600@120Hz RB */
a6b21831
TR		 274 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
275 880, 960, 0, 600, 603, 607, 636, 0,
276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 277 /* 0x0e - 848x480@60Hz */
a6b21831
TR		 278 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
279 976, 1088, 0, 480, 486, 494, 517, 0,
280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 281 /* 0x0f - 1024x768@43Hz, interlace */
a6b21831 282 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
735b100f 283 1208, 1264, 0, 768, 768, 776, 817, 0,
a6b21831 284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
fcf22d05 285 DRM_MODE_FLAG_INTERLACE) },
24b856b1 286 /* 0x10 - 1024x768@60Hz */
a6b21831
TR		 287 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
288 1184, 1344, 0, 768, 771, 777, 806, 0,
289 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 290 /* 0x11 - 1024x768@70Hz */
a6b21831
TR		 291 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
292 1184, 1328, 0, 768, 771, 777, 806, 0,
293 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 294 /* 0x12 - 1024x768@75Hz */
a6b21831
TR		 295 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
296 1136, 1312, 0, 768, 769, 772, 800, 0,
297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 298 /* 0x13 - 1024x768@85Hz */
a6b21831
TR		 299 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
300 1168, 1376, 0, 768, 769, 772, 808, 0,
301 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 302 /* 0x14 - 1024x768@120Hz RB */
a6b21831
TR		 303 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
304 1104, 1184, 0, 768, 771, 775, 813, 0,
305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 306 /* 0x15 - 1152x864@75Hz */
a6b21831
TR		 307 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
308 1344, 1600, 0, 864, 865, 868, 900, 0,
309 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
bfcd74d2
VS		 310 /* 0x55 - 1280x720@60Hz */
311 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
312 1430, 1650, 0, 720, 725, 730, 750, 0,
313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 314 /* 0x16 - 1280x768@60Hz RB */
a6b21831
TR		 315 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
316 1360, 1440, 0, 768, 771, 778, 790, 0,
317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 318 /* 0x17 - 1280x768@60Hz */
a6b21831
TR		 319 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
320 1472, 1664, 0, 768, 771, 778, 798, 0,
321 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 322 /* 0x18 - 1280x768@75Hz */
a6b21831
TR		 323 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
324 1488, 1696, 0, 768, 771, 778, 805, 0,
fcf22d05 325 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 326 /* 0x19 - 1280x768@85Hz */
a6b21831
TR		 327 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
328 1496, 1712, 0, 768, 771, 778, 809, 0,
329 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 330 /* 0x1a - 1280x768@120Hz RB */
a6b21831
TR		 331 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
332 1360, 1440, 0, 768, 771, 778, 813, 0,
333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 334 /* 0x1b - 1280x800@60Hz RB */
a6b21831
TR		 335 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
336 1360, 1440, 0, 800, 803, 809, 823, 0,
337 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 338 /* 0x1c - 1280x800@60Hz */
a6b21831
TR		 339 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
340 1480, 1680, 0, 800, 803, 809, 831, 0,
fcf22d05 341 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 342 /* 0x1d - 1280x800@75Hz */
a6b21831
TR		 343 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
344 1488, 1696, 0, 800, 803, 809, 838, 0,
345 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 346 /* 0x1e - 1280x800@85Hz */
a6b21831
TR		 347 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
348 1496, 1712, 0, 800, 803, 809, 843, 0,
349 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 350 /* 0x1f - 1280x800@120Hz RB */
a6b21831
TR		 351 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
352 1360, 1440, 0, 800, 803, 809, 847, 0,
353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 354 /* 0x20 - 1280x960@60Hz */
a6b21831
TR		 355 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
356 1488, 1800, 0, 960, 961, 964, 1000, 0,
357 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 358 /* 0x21 - 1280x960@85Hz */
a6b21831
TR		 359 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
360 1504, 1728, 0, 960, 961, 964, 1011, 0,
361 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 362 /* 0x22 - 1280x960@120Hz RB */
a6b21831
TR		 363 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
364 1360, 1440, 0, 960, 963, 967, 1017, 0,
365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 366 /* 0x23 - 1280x1024@60Hz */
a6b21831
TR		 367 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
368 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 370 /* 0x24 - 1280x1024@75Hz */
a6b21831
TR		 371 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
372 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 374 /* 0x25 - 1280x1024@85Hz */
a6b21831
TR		 375 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
376 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 378 /* 0x26 - 1280x1024@120Hz RB */
a6b21831
TR		 379 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
380 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
381 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 382 /* 0x27 - 1360x768@60Hz */
a6b21831
TR		 383 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
384 1536, 1792, 0, 768, 771, 777, 795, 0,
385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 386 /* 0x28 - 1360x768@120Hz RB */
a6b21831
TR		 387 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
388 1440, 1520, 0, 768, 771, 776, 813, 0,
389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 390 /* 0x51 - 1366x768@60Hz */
391 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
392 1579, 1792, 0, 768, 771, 774, 798, 0,
393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
394 /* 0x56 - 1366x768@60Hz */
395 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
396 1436, 1500, 0, 768, 769, 772, 800, 0,
397 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 398 /* 0x29 - 1400x1050@60Hz RB */
a6b21831
TR		 399 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
400 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
401 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 402 /* 0x2a - 1400x1050@60Hz */
a6b21831
TR		 403 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
404 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
405 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 406 /* 0x2b - 1400x1050@75Hz */
a6b21831
TR		 407 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
408 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
409 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 410 /* 0x2c - 1400x1050@85Hz */
a6b21831
TR		 411 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
412 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
413 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 414 /* 0x2d - 1400x1050@120Hz RB */
a6b21831
TR		 415 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
416 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
417 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 418 /* 0x2e - 1440x900@60Hz RB */
a6b21831
TR		 419 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
420 1520, 1600, 0, 900, 903, 909, 926, 0,
421 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 422 /* 0x2f - 1440x900@60Hz */
a6b21831
TR		 423 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
424 1672, 1904, 0, 900, 903, 909, 934, 0,
425 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 426 /* 0x30 - 1440x900@75Hz */
a6b21831
TR		 427 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
428 1688, 1936, 0, 900, 903, 909, 942, 0,
429 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 430 /* 0x31 - 1440x900@85Hz */
a6b21831
TR		 431 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
432 1696, 1952, 0, 900, 903, 909, 948, 0,
433 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 434 /* 0x32 - 1440x900@120Hz RB */
a6b21831
TR		 435 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
436 1520, 1600, 0, 900, 903, 909, 953, 0,
437 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 438 /* 0x53 - 1600x900@60Hz */
439 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
440 1704, 1800, 0, 900, 901, 904, 1000, 0,
441 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 442 /* 0x33 - 1600x1200@60Hz */
a6b21831
TR		 443 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
444 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
445 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 446 /* 0x34 - 1600x1200@65Hz */
a6b21831
TR		 447 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
448 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
449 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 450 /* 0x35 - 1600x1200@70Hz */
a6b21831
TR		 451 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
452 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 454 /* 0x36 - 1600x1200@75Hz */
a6b21831
TR		 455 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
456 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 458 /* 0x37 - 1600x1200@85Hz */
a6b21831
TR		 459 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
460 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 462 /* 0x38 - 1600x1200@120Hz RB */
a6b21831
TR		 463 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
464 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 466 /* 0x39 - 1680x1050@60Hz RB */
a6b21831
TR		 467 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
468 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 470 /* 0x3a - 1680x1050@60Hz */
a6b21831
TR		 471 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
472 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
473 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 474 /* 0x3b - 1680x1050@75Hz */
a6b21831
TR		 475 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
476 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
477 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 478 /* 0x3c - 1680x1050@85Hz */
a6b21831
TR		 479 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
480 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
481 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 482 /* 0x3d - 1680x1050@120Hz RB */
a6b21831
TR		 483 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
484 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
485 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 486 /* 0x3e - 1792x1344@60Hz */
a6b21831
TR		 487 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
488 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
489 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 490 /* 0x3f - 1792x1344@75Hz */
a6b21831
TR		 491 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
492 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
493 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 494 /* 0x40 - 1792x1344@120Hz RB */
a6b21831
TR		 495 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
496 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
497 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 498 /* 0x41 - 1856x1392@60Hz */
a6b21831
TR		 499 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
500 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
501 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 502 /* 0x42 - 1856x1392@75Hz */
a6b21831 503 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
fcf22d05 504 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
a6b21831 505 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 506 /* 0x43 - 1856x1392@120Hz RB */
a6b21831
TR		 507 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
508 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
509 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 510 /* 0x52 - 1920x1080@60Hz */
511 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
512 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
513 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 514 /* 0x44 - 1920x1200@60Hz RB */
a6b21831
TR		 515 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
516 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
517 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 518 /* 0x45 - 1920x1200@60Hz */
a6b21831
TR		 519 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
520 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
521 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 522 /* 0x46 - 1920x1200@75Hz */
a6b21831
TR		 523 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
524 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
525 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 526 /* 0x47 - 1920x1200@85Hz */
a6b21831
TR		 527 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
528 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
529 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 530 /* 0x48 - 1920x1200@120Hz RB */
a6b21831
TR		 531 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
532 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
533 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 534 /* 0x49 - 1920x1440@60Hz */
a6b21831
TR		 535 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
536 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
537 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 538 /* 0x4a - 1920x1440@75Hz */
a6b21831
TR		 539 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
540 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
541 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 542 /* 0x4b - 1920x1440@120Hz RB */
a6b21831
TR		 543 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
544 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
545 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 546 /* 0x54 - 2048x1152@60Hz */
547 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
548 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
549 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 550 /* 0x4c - 2560x1600@60Hz RB */
a6b21831
TR		 551 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
552 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
553 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 554 /* 0x4d - 2560x1600@60Hz */
a6b21831
TR		 555 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
556 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
557 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 558 /* 0x4e - 2560x1600@75Hz */
a6b21831
TR		 559 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
560 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
561 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 562 /* 0x4f - 2560x1600@85Hz */
a6b21831
TR		 563 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
564 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
565 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 566 /* 0x50 - 2560x1600@120Hz RB */
a6b21831
TR		 567 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
568 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
569 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 570 /* 0x57 - 4096x2160@60Hz RB */
571 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
572 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
573 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
574 /* 0x58 - 4096x2160@59.94Hz RB */
575 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
576 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
577 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
a6b21831
TR		 578};
579
e7bfa5c4
VS		 580/*
581 * These more or less come from the DMT spec. The 720x400 modes are
582 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
583 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
584 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
585 * mode.
586 *
587 * The DMT modes have been fact-checked; the rest are mild guesses.
588 */
a6b21831
TR		 589static const struct drm_display_mode edid_est_modes[] = {
590 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
591 968, 1056, 0, 600, 601, 605, 628, 0,
592 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
593 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
594 896, 1024, 0, 600, 601, 603, 625, 0,
595 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
596 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
597 720, 840, 0, 480, 481, 484, 500, 0,
598 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
599 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
87707cfd 600 704, 832, 0, 480, 489, 492, 520, 0,
a6b21831
TR		 601 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
602 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
603 768, 864, 0, 480, 483, 486, 525, 0,
604 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
87707cfd 605 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
a6b21831
TR		 606 752, 800, 0, 480, 490, 492, 525, 0,
607 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
608 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
609 846, 900, 0, 400, 421, 423, 449, 0,
610 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
611 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
612 846, 900, 0, 400, 412, 414, 449, 0,
613 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
614 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
615 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
616 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
87707cfd 617 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
a6b21831
TR		 618 1136, 1312, 0, 768, 769, 772, 800, 0,
619 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
620 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
621 1184, 1328, 0, 768, 771, 777, 806, 0,
622 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
623 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
624 1184, 1344, 0, 768, 771, 777, 806, 0,
625 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
626 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
627 1208, 1264, 0, 768, 768, 776, 817, 0,
628 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
629 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
630 928, 1152, 0, 624, 625, 628, 667, 0,
631 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
632 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
633 896, 1056, 0, 600, 601, 604, 625, 0,
634 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
635 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
636 976, 1040, 0, 600, 637, 643, 666, 0,
637 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
638 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
639 1344, 1600, 0, 864, 865, 868, 900, 0,
640 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
641};
642
643struct minimode {
644 short w;
645 short h;
646 short r;
647 short rb;
648};
649
650static const struct minimode est3_modes[] = {
651 /* byte 6 */
652 { 640, 350, 85, 0 },
653 { 640, 400, 85, 0 },
654 { 720, 400, 85, 0 },
655 { 640, 480, 85, 0 },
656 { 848, 480, 60, 0 },
657 { 800, 600, 85, 0 },
658 { 1024, 768, 85, 0 },
659 { 1152, 864, 75, 0 },
660 /* byte 7 */
661 { 1280, 768, 60, 1 },
662 { 1280, 768, 60, 0 },
663 { 1280, 768, 75, 0 },
664 { 1280, 768, 85, 0 },
665 { 1280, 960, 60, 0 },
666 { 1280, 960, 85, 0 },
667 { 1280, 1024, 60, 0 },
668 { 1280, 1024, 85, 0 },
669 /* byte 8 */
670 { 1360, 768, 60, 0 },
671 { 1440, 900, 60, 1 },
672 { 1440, 900, 60, 0 },
673 { 1440, 900, 75, 0 },
674 { 1440, 900, 85, 0 },
675 { 1400, 1050, 60, 1 },
676 { 1400, 1050, 60, 0 },
677 { 1400, 1050, 75, 0 },
678 /* byte 9 */
679 { 1400, 1050, 85, 0 },
680 { 1680, 1050, 60, 1 },
681 { 1680, 1050, 60, 0 },
682 { 1680, 1050, 75, 0 },
683 { 1680, 1050, 85, 0 },
684 { 1600, 1200, 60, 0 },
685 { 1600, 1200, 65, 0 },
686 { 1600, 1200, 70, 0 },
687 /* byte 10 */
688 { 1600, 1200, 75, 0 },
689 { 1600, 1200, 85, 0 },
690 { 1792, 1344, 60, 0 },
c068b32a 691 { 1792, 1344, 75, 0 },
a6b21831
TR		 692 { 1856, 1392, 60, 0 },
693 { 1856, 1392, 75, 0 },
694 { 1920, 1200, 60, 1 },
695 { 1920, 1200, 60, 0 },
696 /* byte 11 */
697 { 1920, 1200, 75, 0 },
698 { 1920, 1200, 85, 0 },
699 { 1920, 1440, 60, 0 },
700 { 1920, 1440, 75, 0 },
701};
702
703static const struct minimode extra_modes[] = {
704 { 1024, 576, 60, 0 },
705 { 1366, 768, 60, 0 },
706 { 1600, 900, 60, 0 },
707 { 1680, 945, 60, 0 },
708 { 1920, 1080, 60, 0 },
709 { 2048, 1152, 60, 0 },
710 { 2048, 1536, 60, 0 },
711};
712
713/*
7befe621 714 * From CEA/CTA-861 spec.
d9278b4c 715 *
7befe621 716 * Do not access directly, instead always use cea_mode_for_vic().
a6b21831 717 */
8c1b2bd9 718static const struct drm_display_mode edid_cea_modes_1[] = {
78691960 719 /* 1 - 640x480@60Hz 4:3 */
a6b21831
TR		 720 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
721 752, 800, 0, 480, 490, 492, 525, 0,
ee7925bb 722 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 723 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 724 /* 2 - 720x480@60Hz 4:3 */
a6b21831
TR		 725 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
726 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 727 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 728 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 729 /* 3 - 720x480@60Hz 16:9 */
a6b21831
TR		 730 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
731 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 732 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 733 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 734 /* 4 - 1280x720@60Hz 16:9 */
a6b21831
TR		 735 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
736 1430, 1650, 0, 720, 725, 730, 750, 0,
ee7925bb 737 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 738 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 739 /* 5 - 1920x1080i@60Hz 16:9 */
a6b21831
TR		 740 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
741 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
742 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 743 DRM_MODE_FLAG_INTERLACE),
0425662f 744 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 745 /* 6 - 720(1440)x480i@60Hz 4:3 */
fb01d280
CT		 746 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
747 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 748 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 749 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 750 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 751 /* 7 - 720(1440)x480i@60Hz 16:9 */
fb01d280
CT		 752 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
753 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 754 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 755 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 756 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 757 /* 8 - 720(1440)x240@60Hz 4:3 */
fb01d280
CT		 758 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
759 801, 858, 0, 240, 244, 247, 262, 0,
a6b21831 760 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 761 DRM_MODE_FLAG_DBLCLK),
0425662f 762 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 763 /* 9 - 720(1440)x240@60Hz 16:9 */
fb01d280
CT		 764 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
765 801, 858, 0, 240, 244, 247, 262, 0,
a6b21831 766 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 767 DRM_MODE_FLAG_DBLCLK),
0425662f 768 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 769 /* 10 - 2880x480i@60Hz 4:3 */
a6b21831
TR		 770 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
771 3204, 3432, 0, 480, 488, 494, 525, 0,
772 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 773 DRM_MODE_FLAG_INTERLACE),
0425662f 774 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 775 /* 11 - 2880x480i@60Hz 16:9 */
a6b21831
TR		 776 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
777 3204, 3432, 0, 480, 488, 494, 525, 0,
778 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 779 DRM_MODE_FLAG_INTERLACE),
0425662f 780 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 781 /* 12 - 2880x240@60Hz 4:3 */
a6b21831
TR		 782 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
783 3204, 3432, 0, 240, 244, 247, 262, 0,
ee7925bb 784 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 785 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 786 /* 13 - 2880x240@60Hz 16:9 */
a6b21831
TR		 787 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
788 3204, 3432, 0, 240, 244, 247, 262, 0,
ee7925bb 789 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 790 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 791 /* 14 - 1440x480@60Hz 4:3 */
a6b21831
TR		 792 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
793 1596, 1716, 0, 480, 489, 495, 525, 0,
ee7925bb 794 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 795 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 796 /* 15 - 1440x480@60Hz 16:9 */
a6b21831
TR		 797 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
798 1596, 1716, 0, 480, 489, 495, 525, 0,
ee7925bb 799 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 800 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 801 /* 16 - 1920x1080@60Hz 16:9 */
a6b21831
TR		 802 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
803 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 804 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 805 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 806 /* 17 - 720x576@50Hz 4:3 */
a6b21831
TR		 807 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
808 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 809 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 810 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 811 /* 18 - 720x576@50Hz 16:9 */
a6b21831
TR		 812 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
813 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 814 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 815 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 816 /* 19 - 1280x720@50Hz 16:9 */
a6b21831
TR		 817 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
818 1760, 1980, 0, 720, 725, 730, 750, 0,
ee7925bb 819 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 820 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 821 /* 20 - 1920x1080i@50Hz 16:9 */
a6b21831
TR		 822 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
823 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
824 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 825 DRM_MODE_FLAG_INTERLACE),
0425662f 826 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 827 /* 21 - 720(1440)x576i@50Hz 4:3 */
fb01d280
CT		 828 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
829 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 830 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 831 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 832 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 833 /* 22 - 720(1440)x576i@50Hz 16:9 */
fb01d280
CT		 834 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
835 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 836 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 837 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 838 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 839 /* 23 - 720(1440)x288@50Hz 4:3 */
fb01d280
CT		 840 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
841 795, 864, 0, 288, 290, 293, 312, 0,
a6b21831 842 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 843 DRM_MODE_FLAG_DBLCLK),
0425662f 844 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 845 /* 24 - 720(1440)x288@50Hz 16:9 */
fb01d280
CT		 846 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
847 795, 864, 0, 288, 290, 293, 312, 0,
a6b21831 848 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 849 DRM_MODE_FLAG_DBLCLK),
0425662f 850 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 851 /* 25 - 2880x576i@50Hz 4:3 */
a6b21831
TR		 852 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
853 3180, 3456, 0, 576, 580, 586, 625, 0,
854 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 855 DRM_MODE_FLAG_INTERLACE),
0425662f 856 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 857 /* 26 - 2880x576i@50Hz 16:9 */
a6b21831
TR		 858 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
859 3180, 3456, 0, 576, 580, 586, 625, 0,
860 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 861 DRM_MODE_FLAG_INTERLACE),
0425662f 862 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 863 /* 27 - 2880x288@50Hz 4:3 */
a6b21831
TR		 864 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
865 3180, 3456, 0, 288, 290, 293, 312, 0,
ee7925bb 866 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 867 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 868 /* 28 - 2880x288@50Hz 16:9 */
a6b21831
TR		 869 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
870 3180, 3456, 0, 288, 290, 293, 312, 0,
ee7925bb 871 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 872 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 873 /* 29 - 1440x576@50Hz 4:3 */
a6b21831
TR		 874 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
875 1592, 1728, 0, 576, 581, 586, 625, 0,
ee7925bb 876 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 877 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 878 /* 30 - 1440x576@50Hz 16:9 */
a6b21831
TR		 879 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
880 1592, 1728, 0, 576, 581, 586, 625, 0,
ee7925bb 881 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 882 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 883 /* 31 - 1920x1080@50Hz 16:9 */
a6b21831
TR		 884 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
885 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 886 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 887 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 888 /* 32 - 1920x1080@24Hz 16:9 */
a6b21831
TR		 889 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
890 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 891 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 892 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 893 /* 33 - 1920x1080@25Hz 16:9 */
a6b21831
TR		 894 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
895 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 896 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 897 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 898 /* 34 - 1920x1080@30Hz 16:9 */
a6b21831
TR		 899 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
900 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 901 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 902 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 903 /* 35 - 2880x480@60Hz 4:3 */
a6b21831
TR		 904 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
905 3192, 3432, 0, 480, 489, 495, 525, 0,
ee7925bb 906 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 907 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 908 /* 36 - 2880x480@60Hz 16:9 */
a6b21831
TR		 909 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
910 3192, 3432, 0, 480, 489, 495, 525, 0,
ee7925bb 911 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 912 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 913 /* 37 - 2880x576@50Hz 4:3 */
a6b21831
TR		 914 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
915 3184, 3456, 0, 576, 581, 586, 625, 0,
ee7925bb 916 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 917 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 918 /* 38 - 2880x576@50Hz 16:9 */
a6b21831
TR		 919 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
920 3184, 3456, 0, 576, 581, 586, 625, 0,
ee7925bb 921 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 922 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 923 /* 39 - 1920x1080i@50Hz 16:9 */
a6b21831
TR		 924 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
925 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
926 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 927 DRM_MODE_FLAG_INTERLACE),
0425662f 928 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 929 /* 40 - 1920x1080i@100Hz 16:9 */
a6b21831
TR		 930 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
931 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
932 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 933 DRM_MODE_FLAG_INTERLACE),
0425662f 934 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 935 /* 41 - 1280x720@100Hz 16:9 */
a6b21831
TR		 936 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
937 1760, 1980, 0, 720, 725, 730, 750, 0,
ee7925bb 938 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 939 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 940 /* 42 - 720x576@100Hz 4:3 */
a6b21831
TR		 941 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
942 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 943 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 944 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 945 /* 43 - 720x576@100Hz 16:9 */
a6b21831
TR		 946 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
947 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 948 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 949 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 950 /* 44 - 720(1440)x576i@100Hz 4:3 */
fb01d280
CT		 951 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
952 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 953 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 954 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 955 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 956 /* 45 - 720(1440)x576i@100Hz 16:9 */
fb01d280
CT		 957 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
958 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 959 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 960 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 961 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 962 /* 46 - 1920x1080i@120Hz 16:9 */
a6b21831
TR		 963 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
964 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
965 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 966 DRM_MODE_FLAG_INTERLACE),
0425662f 967 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 968 /* 47 - 1280x720@120Hz 16:9 */
a6b21831
TR		 969 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
970 1430, 1650, 0, 720, 725, 730, 750, 0,
ee7925bb 971 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 972 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 973 /* 48 - 720x480@120Hz 4:3 */
a6b21831
TR		 974 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
975 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 976 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 977 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 978 /* 49 - 720x480@120Hz 16:9 */
a6b21831
TR		 979 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
980 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 981 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 982 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 983 /* 50 - 720(1440)x480i@120Hz 4:3 */
fb01d280
CT		 984 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
985 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 986 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 987 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 988 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 989 /* 51 - 720(1440)x480i@120Hz 16:9 */
fb01d280
CT		 990 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
991 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 992 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 993 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 994 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 995 /* 52 - 720x576@200Hz 4:3 */
a6b21831
TR		 996 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
997 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 998 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 999 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1000 /* 53 - 720x576@200Hz 16:9 */
a6b21831
TR		 1001 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1002 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 1003 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 1004 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1005 /* 54 - 720(1440)x576i@200Hz 4:3 */
fb01d280
CT		 1006 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1007 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 1008 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1009 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1010 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1011 /* 55 - 720(1440)x576i@200Hz 16:9 */
fb01d280
CT		 1012 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1013 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 1014 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1015 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1016 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1017 /* 56 - 720x480@240Hz 4:3 */
a6b21831
TR		 1018 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1019 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 1020 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 1021 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1022 /* 57 - 720x480@240Hz 16:9 */
a6b21831
TR		 1023 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1024 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 1025 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 1026 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1027 /* 58 - 720(1440)x480i@240Hz 4:3 */
fb01d280
CT		 1028 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1029 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 1030 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1031 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1032 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1033 /* 59 - 720(1440)x480i@240Hz 16:9 */
fb01d280
CT		 1034 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1035 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 1036 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1037 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1038 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1039 /* 60 - 1280x720@24Hz 16:9 */
a6b21831
TR		 1040 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1041 3080, 3300, 0, 720, 725, 730, 750, 0,
ee7925bb 1042 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1043 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1044 /* 61 - 1280x720@25Hz 16:9 */
a6b21831
TR		 1045 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1046 3740, 3960, 0, 720, 725, 730, 750, 0,
ee7925bb 1047 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1048 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1049 /* 62 - 1280x720@30Hz 16:9 */
a6b21831
TR		 1050 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1051 3080, 3300, 0, 720, 725, 730, 750, 0,
ee7925bb 1052 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1053 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1054 /* 63 - 1920x1080@120Hz 16:9 */
a6b21831
TR		 1055 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1056 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 1057 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1058 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1059 /* 64 - 1920x1080@100Hz 16:9 */
a6b21831 1060 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
8f0e4907 1061 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 1062 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1063 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1064 /* 65 - 1280x720@24Hz 64:27 */
8ec6e075
SS		 1065 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1066 3080, 3300, 0, 720, 725, 730, 750, 0,
1067 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1068 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1069 /* 66 - 1280x720@25Hz 64:27 */
8ec6e075
SS		 1070 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1071 3740, 3960, 0, 720, 725, 730, 750, 0,
1072 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1073 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1074 /* 67 - 1280x720@30Hz 64:27 */
8ec6e075
SS		 1075 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1076 3080, 3300, 0, 720, 725, 730, 750, 0,
1077 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1078 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1079 /* 68 - 1280x720@50Hz 64:27 */
8ec6e075
SS		 1080 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1081 1760, 1980, 0, 720, 725, 730, 750, 0,
1082 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1083 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1084 /* 69 - 1280x720@60Hz 64:27 */
8ec6e075
SS		 1085 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1086 1430, 1650, 0, 720, 725, 730, 750, 0,
1087 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1088 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1089 /* 70 - 1280x720@100Hz 64:27 */
8ec6e075
SS		 1090 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1091 1760, 1980, 0, 720, 725, 730, 750, 0,
1092 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1093 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1094 /* 71 - 1280x720@120Hz 64:27 */
8ec6e075
SS		 1095 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1096 1430, 1650, 0, 720, 725, 730, 750, 0,
1097 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1098 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1099 /* 72 - 1920x1080@24Hz 64:27 */
8ec6e075
SS		 1100 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1101 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1102 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1103 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1104 /* 73 - 1920x1080@25Hz 64:27 */
8ec6e075
SS		 1105 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1106 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1107 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1108 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1109 /* 74 - 1920x1080@30Hz 64:27 */
8ec6e075
SS		 1110 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1111 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1112 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1113 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1114 /* 75 - 1920x1080@50Hz 64:27 */
8ec6e075
SS		 1115 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1116 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1117 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1118 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1119 /* 76 - 1920x1080@60Hz 64:27 */
8ec6e075
SS		 1120 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1121 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1122 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1123 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1124 /* 77 - 1920x1080@100Hz 64:27 */
8ec6e075
SS		 1125 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1126 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1127 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1128 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1129 /* 78 - 1920x1080@120Hz 64:27 */
8ec6e075
SS		 1130 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1131 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1132 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1133 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1134 /* 79 - 1680x720@24Hz 64:27 */
8ec6e075
SS		 1135 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1136 3080, 3300, 0, 720, 725, 730, 750, 0,
1137 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1138 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1139 /* 80 - 1680x720@25Hz 64:27 */
8ec6e075
SS		 1140 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1141 2948, 3168, 0, 720, 725, 730, 750, 0,
1142 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1143 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1144 /* 81 - 1680x720@30Hz 64:27 */
8ec6e075
SS		 1145 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1146 2420, 2640, 0, 720, 725, 730, 750, 0,
1147 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1148 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1149 /* 82 - 1680x720@50Hz 64:27 */
8ec6e075
SS		 1150 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1151 1980, 2200, 0, 720, 725, 730, 750, 0,
1152 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1153 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1154 /* 83 - 1680x720@60Hz 64:27 */
8ec6e075
SS		 1155 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1156 1980, 2200, 0, 720, 725, 730, 750, 0,
1157 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1158 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1159 /* 84 - 1680x720@100Hz 64:27 */
8ec6e075
SS		 1160 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1161 1780, 2000, 0, 720, 725, 730, 825, 0,
1162 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1163 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1164 /* 85 - 1680x720@120Hz 64:27 */
8ec6e075
SS		 1165 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1166 1780, 2000, 0, 720, 725, 730, 825, 0,
1167 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1168 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1169 /* 86 - 2560x1080@24Hz 64:27 */
8ec6e075
SS		 1170 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1171 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1172 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1173 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1174 /* 87 - 2560x1080@25Hz 64:27 */
8ec6e075
SS		 1175 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1176 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1177 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1178 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1179 /* 88 - 2560x1080@30Hz 64:27 */
8ec6e075
SS		 1180 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1181 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1182 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1183 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1184 /* 89 - 2560x1080@50Hz 64:27 */
8ec6e075
SS		 1185 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1186 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1187 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1188 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1189 /* 90 - 2560x1080@60Hz 64:27 */
8ec6e075
SS		 1190 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1191 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1192 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1193 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1194 /* 91 - 2560x1080@100Hz 64:27 */
8ec6e075
SS		 1195 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1196 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1197 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1198 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1199 /* 92 - 2560x1080@120Hz 64:27 */
8ec6e075
SS		 1200 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1201 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1202 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1203 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1204 /* 93 - 3840x2160@24Hz 16:9 */
8ec6e075
SS		 1205 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1206 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1207 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1208 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1209 /* 94 - 3840x2160@25Hz 16:9 */
8ec6e075
SS		 1210 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1211 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1212 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1213 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1214 /* 95 - 3840x2160@30Hz 16:9 */
8ec6e075
SS		 1215 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1216 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1217 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1218 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1219 /* 96 - 3840x2160@50Hz 16:9 */
8ec6e075
SS		 1220 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1221 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1222 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1223 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1224 /* 97 - 3840x2160@60Hz 16:9 */
8ec6e075
SS		 1225 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1226 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1227 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1228 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1229 /* 98 - 4096x2160@24Hz 256:135 */
8ec6e075
SS		 1230 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1231 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1232 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1233 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1234 /* 99 - 4096x2160@25Hz 256:135 */
8ec6e075
SS		 1235 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1236 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1237 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1238 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1239 /* 100 - 4096x2160@30Hz 256:135 */
8ec6e075
SS		 1240 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1241 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1242 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1243 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1244 /* 101 - 4096x2160@50Hz 256:135 */
8ec6e075
SS		 1245 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1246 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1247 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1248 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1249 /* 102 - 4096x2160@60Hz 256:135 */
8ec6e075
SS		 1250 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1251 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1252 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1253 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1254 /* 103 - 3840x2160@24Hz 64:27 */
8ec6e075
SS		 1255 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1256 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1257 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1258 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1259 /* 104 - 3840x2160@25Hz 64:27 */
8ec6e075
SS		 1260 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1261 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1262 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1263 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1264 /* 105 - 3840x2160@30Hz 64:27 */
8ec6e075
SS		 1265 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1266 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1267 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1268 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1269 /* 106 - 3840x2160@50Hz 64:27 */
8ec6e075
SS		 1270 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1271 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1273 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1274 /* 107 - 3840x2160@60Hz 64:27 */
8ec6e075
SS		 1275 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1276 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1277 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1278 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1279 /* 108 - 1280x720@48Hz 16:9 */
1280 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1281 2280, 2500, 0, 720, 725, 730, 750, 0,
1282 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1283 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1284 /* 109 - 1280x720@48Hz 64:27 */
1285 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1286 2280, 2500, 0, 720, 725, 730, 750, 0,
1287 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1288 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1289 /* 110 - 1680x720@48Hz 64:27 */
1290 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490,
1291 2530, 2750, 0, 720, 725, 730, 750, 0,
1292 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1293 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1294 /* 111 - 1920x1080@48Hz 16:9 */
1295 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1296 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1298 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1299 /* 112 - 1920x1080@48Hz 64:27 */
1300 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1301 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1302 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1303 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1304 /* 113 - 2560x1080@48Hz 64:27 */
1305 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558,
1306 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1307 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1308 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1309 /* 114 - 3840x2160@48Hz 16:9 */
1310 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1311 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1312 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1313 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1314 /* 115 - 4096x2160@48Hz 256:135 */
1315 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116,
1316 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1318 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
978f6b06
VS		 1319 /* 116 - 3840x2160@48Hz 64:27 */
1320 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1321 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1322 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1323 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1324 /* 117 - 3840x2160@100Hz 16:9 */
1325 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1326 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1327 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1328 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1329 /* 118 - 3840x2160@120Hz 16:9 */
1330 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1331 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1332 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1333 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1334 /* 119 - 3840x2160@100Hz 64:27 */
1335 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1336 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1337 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1338 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1339 /* 120 - 3840x2160@120Hz 64:27 */
1340 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1341 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1342 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1343 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1344 /* 121 - 5120x2160@24Hz 64:27 */
1345 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116,
1346 7204, 7500, 0, 2160, 2168, 2178, 2200, 0,
1347 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1348 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1349 /* 122 - 5120x2160@25Hz 64:27 */
1350 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816,
1351 6904, 7200, 0, 2160, 2168, 2178, 2200, 0,
1352 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1353 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1354 /* 123 - 5120x2160@30Hz 64:27 */
1355 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784,
1356 5872, 6000, 0, 2160, 2168, 2178, 2200, 0,
1357 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1358 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1359 /* 124 - 5120x2160@48Hz 64:27 */
1360 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866,
1361 5954, 6250, 0, 2160, 2168, 2178, 2475, 0,
1362 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1363 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1364 /* 125 - 5120x2160@50Hz 64:27 */
1365 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216,
1366 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1367 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1368 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1369 /* 126 - 5120x2160@60Hz 64:27 */
1370 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284,
1371 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1372 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1373 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1374 /* 127 - 5120x2160@100Hz 64:27 */
1375 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216,
1376 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1378 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
a6b21831
TR		 1379};
1380
f7655d42
VS		 1381/*
1382 * From CEA/CTA-861 spec.
1383 *
1384 * Do not access directly, instead always use cea_mode_for_vic().
1385 */
1386static const struct drm_display_mode edid_cea_modes_193[] = {
1387 /* 193 - 5120x2160@120Hz 64:27 */
1388 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284,
1389 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1390 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1391 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1392 /* 194 - 7680x4320@24Hz 16:9 */
1393 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1394 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1395 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1396 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1397 /* 195 - 7680x4320@25Hz 16:9 */
1398 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1399 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1400 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1401 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1402 /* 196 - 7680x4320@30Hz 16:9 */
1403 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1404 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1405 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1406 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1407 /* 197 - 7680x4320@48Hz 16:9 */
1408 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1409 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1410 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1411 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1412 /* 198 - 7680x4320@50Hz 16:9 */
1413 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1414 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1415 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1416 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1417 /* 199 - 7680x4320@60Hz 16:9 */
1418 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1419 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1420 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1421 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1422 /* 200 - 7680x4320@100Hz 16:9 */
1423 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1424 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1425 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1426 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1427 /* 201 - 7680x4320@120Hz 16:9 */
1428 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1429 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1430 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1431 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1432 /* 202 - 7680x4320@24Hz 64:27 */
1433 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1434 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1435 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1436 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1437 /* 203 - 7680x4320@25Hz 64:27 */
1438 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1439 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1440 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1441 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1442 /* 204 - 7680x4320@30Hz 64:27 */
1443 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1444 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1445 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1446 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1447 /* 205 - 7680x4320@48Hz 64:27 */
1448 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1449 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1450 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1451 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1452 /* 206 - 7680x4320@50Hz 64:27 */
1453 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1454 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1455 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1456 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1457 /* 207 - 7680x4320@60Hz 64:27 */
1458 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1459 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1460 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1461 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1462 /* 208 - 7680x4320@100Hz 64:27 */
1463 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1464 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1466 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1467 /* 209 - 7680x4320@120Hz 64:27 */
1468 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1469 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1470 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1471 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1472 /* 210 - 10240x4320@24Hz 64:27 */
1473 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732,
1474 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1475 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1476 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1477 /* 211 - 10240x4320@25Hz 64:27 */
1478 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732,
1479 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1480 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1481 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1482 /* 212 - 10240x4320@30Hz 64:27 */
1483 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528,
1484 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1485 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1486 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1487 /* 213 - 10240x4320@48Hz 64:27 */
1488 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732,
1489 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1490 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1491 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1492 /* 214 - 10240x4320@50Hz 64:27 */
1493 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732,
1494 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1495 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1496 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1497 /* 215 - 10240x4320@60Hz 64:27 */
1498 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528,
1499 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1500 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1501 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1502 /* 216 - 10240x4320@100Hz 64:27 */
1503 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432,
1504 12608, 13200, 0, 4320, 4336, 4356, 4500, 0,
1505 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1506 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1507 /* 217 - 10240x4320@120Hz 64:27 */
1508 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528,
1509 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1510 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1511 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1512 /* 218 - 4096x2160@100Hz 256:135 */
1513 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896,
1514 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1515 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1516 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
f7655d42
VS		 1517 /* 219 - 4096x2160@120Hz 256:135 */
1518 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184,
1519 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1520 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1521 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
f7655d42
VS		 1522};
1523
7ebe1963 1524/*
d9278b4c 1525 * HDMI 1.4 4k modes. Index using the VIC.
7ebe1963
LD		 1526 */
1527static const struct drm_display_mode edid_4k_modes[] = {
d9278b4c
JN		 1528 /* 0 - dummy, VICs start at 1 */
1529 { },
7ebe1963
LD		 1530 /* 1 - 3840x2160@30Hz */
1531 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1532 3840, 4016, 4104, 4400, 0,
1533 2160, 2168, 2178, 2250, 0,
1534 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1535 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
7ebe1963
LD		 1536 /* 2 - 3840x2160@25Hz */
1537 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1538 3840, 4896, 4984, 5280, 0,
1539 2160, 2168, 2178, 2250, 0,
1540 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1541 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
7ebe1963
LD		 1542 /* 3 - 3840x2160@24Hz */
1543 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1544 3840, 5116, 5204, 5500, 0,
1545 2160, 2168, 2178, 2250, 0,
1546 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1547 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
7ebe1963
LD		 1548 /* 4 - 4096x2160@24Hz (SMPTE) */
1549 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1550 4096, 5116, 5204, 5500, 0,
1551 2160, 2168, 2178, 2250, 0,
1552 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1553 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
7ebe1963
LD		 1554};
1555
61e57a8d 1556/*** DDC fetch and block validation ***/
f453ba04 1557
083ae056
AJ		 1558static const u8 edid_header[] = {
1559 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1560};
f453ba04 1561
db6cf833
TR		 1562/**
1563 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1564 * @raw_edid: pointer to raw base EDID block
1565 *
1566 * Sanity check the header of the base EDID block.
1567 *
1568 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
051963d4
TR		 1569 */
1570int drm_edid_header_is_valid(const u8 *raw_edid)
1571{
1572 int i, score = 0;
1573
1574 for (i = 0; i < sizeof(edid_header); i++)
1575 if (raw_edid[i] == edid_header[i])
1576 score++;
1577
1578 return score;
1579}
1580EXPORT_SYMBOL(drm_edid_header_is_valid);
1581
47819ba2
AJ		 1582static int edid_fixup __read_mostly = 6;
1583module_param_named(edid_fixup, edid_fixup, int, 0400);
1584MODULE_PARM_DESC(edid_fixup,
1585 "Minimum number of valid EDID header bytes (0-8, default 6)");
051963d4 1586
e28ad544 1587static int validate_displayid(u8 *displayid, int length, int idx);
da9df2f4 1588
c465bbc8
SB		 1589static int drm_edid_block_checksum(const u8 *raw_edid)
1590{
1591 int i;
e11f5bd8
JFZ		 1592 u8 csum = 0, crc = 0;
1593
1594 for (i = 0; i < EDID_LENGTH - 1; i++)
c465bbc8
SB		 1595 csum += raw_edid[i];
1596
e11f5bd8
JFZ		 1597 crc = 0x100 - csum;
1598
1599 return crc;
1600}
1601
1602static bool drm_edid_block_checksum_diff(const u8 *raw_edid, u8 real_checksum)
1603{
1604 if (raw_edid[EDID_LENGTH - 1] != real_checksum)
1605 return true;
1606 else
1607 return false;
c465bbc8
SB		 1608}
1609
d6885d65
SB		 1610static bool drm_edid_is_zero(const u8 *in_edid, int length)
1611{
1612 if (memchr_inv(in_edid, 0, length))
1613 return false;
1614
1615 return true;
1616}
1617
536faa45
SL		 1618/**
1619 * drm_edid_are_equal - compare two edid blobs.
1620 * @edid1: pointer to first blob
1621 * @edid2: pointer to second blob
1622 * This helper can be used during probing to determine if
1623 * edid had changed.
1624 */
1625bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2)
1626{
1627 int edid1_len, edid2_len;
1628 bool edid1_present = edid1 != NULL;
1629 bool edid2_present = edid2 != NULL;
1630
1631 if (edid1_present != edid2_present)
1632 return false;
1633
1634 if (edid1) {
1635
1636 edid1_len = EDID_LENGTH * (1 + edid1->extensions);
1637 edid2_len = EDID_LENGTH * (1 + edid2->extensions);
1638
1639 if (edid1_len != edid2_len)
1640 return false;
1641
1642 if (memcmp(edid1, edid2, edid1_len))
1643 return false;
1644 }
1645
1646 return true;
1647}
1648EXPORT_SYMBOL(drm_edid_are_equal);
1649
1650
db6cf833
TR		 1651/**
1652 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1653 * @raw_edid: pointer to raw EDID block
1654 * @block: type of block to validate (0 for base, extension otherwise)
1655 * @print_bad_edid: if true, dump bad EDID blocks to the console
6ba2bd3d 1656 * @edid_corrupt: if true, the header or checksum is invalid
db6cf833
TR		 1657 *
1658 * Validate a base or extension EDID block and optionally dump bad blocks to
1659 * the console.
1660 *
1661 * Return: True if the block is valid, false otherwise.
f453ba04 1662 */
6ba2bd3d
TP		 1663bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
1664 bool *edid_corrupt)
f453ba04 1665{
c465bbc8 1666 u8 csum;
61e57a8d 1667 struct edid *edid = (struct edid *)raw_edid;
f453ba04 1668
fe2ef780
SWK		 1669 if (WARN_ON(!raw_edid))
1670 return false;
1671
47819ba2
AJ		 1672 if (edid_fixup > 8 || edid_fixup < 0)
1673 edid_fixup = 6;
1674
f89ec8a4 1675 if (block == 0) {
051963d4 1676 int score = drm_edid_header_is_valid(raw_edid);
6ba2bd3d
TP		 1677 if (score == 8) {
1678 if (edid_corrupt)
ac6f2e29 1679 *edid_corrupt = false;
6ba2bd3d
TP		 1680 } else if (score >= edid_fixup) {
1681 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
1682 * The corrupt flag needs to be set here otherwise, the
1683 * fix-up code here will correct the problem, the
1684 * checksum is correct and the test fails
1685 */
1686 if (edid_corrupt)
ac6f2e29 1687 *edid_corrupt = true;
61e57a8d
AJ		 1688 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1689 memcpy(raw_edid, edid_header, sizeof(edid_header));
1690 } else {
6ba2bd3d 1691 if (edid_corrupt)
ac6f2e29 1692 *edid_corrupt = true;
61e57a8d
AJ		 1693 goto bad;
1694 }
1695 }
f453ba04 1696
c465bbc8 1697 csum = drm_edid_block_checksum(raw_edid);
e11f5bd8 1698 if (drm_edid_block_checksum_diff(raw_edid, csum)) {
6ba2bd3d 1699 if (edid_corrupt)
ac6f2e29 1700 *edid_corrupt = true;
6ba2bd3d 1701
4a638b4e 1702 /* allow CEA to slide through, switches mangle this */
82d75356
TV		 1703 if (raw_edid[0] == CEA_EXT) {
1704 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum);
1705 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n");
1706 } else {
1707 if (print_bad_edid)
813a7878 1708 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum);
82d75356 1709
4a638b4e 1710 goto bad;
82d75356 1711 }
f453ba04
DA		 1712 }
1713
61e57a8d
AJ		 1714 /* per-block-type checks */
1715 switch (raw_edid[0]) {
1716 case 0: /* base */
1717 if (edid->version != 1) {
813a7878 1718 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version);
61e57a8d
AJ		 1719 goto bad;
1720 }
862b89c0 1721
61e57a8d
AJ		 1722 if (edid->revision > 4)
1723 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1724 break;
862b89c0 1725
61e57a8d
AJ		 1726 default:
1727 break;
1728 }
47ee4ccf 1729
fe2ef780 1730 return true;
f453ba04
DA		 1731
1732bad:
fe2ef780 1733 if (print_bad_edid) {
da4c07b7 1734 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
499447db 1735 pr_notice("EDID block is all zeroes\n");
da4c07b7 1736 } else {
499447db 1737 pr_notice("Raw EDID:\n");
813a7878
CW		 1738 print_hex_dump(KERN_NOTICE,
1739 " \t", DUMP_PREFIX_NONE, 16, 1,
1740 raw_edid, EDID_LENGTH, false);
da4c07b7 1741 }
f453ba04 1742 }
fe2ef780 1743 return false;
f453ba04 1744}
da0df92b 1745EXPORT_SYMBOL(drm_edid_block_valid);
61e57a8d
AJ		 1746
1747/**
1748 * drm_edid_is_valid - sanity check EDID data
1749 * @edid: EDID data
1750 *
1751 * Sanity-check an entire EDID record (including extensions)
db6cf833
TR		 1752 *
1753 * Return: True if the EDID data is valid, false otherwise.
61e57a8d
AJ		 1754 */
1755bool drm_edid_is_valid(struct edid *edid)
1756{
1757 int i;
1758 u8 *raw = (u8 *)edid;
1759
1760 if (!edid)
1761 return false;
1762
1763 for (i = 0; i <= edid->extensions; i++)
6ba2bd3d 1764 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
61e57a8d
AJ		 1765 return false;
1766
1767 return true;
1768}
3c537889 1769EXPORT_SYMBOL(drm_edid_is_valid);
f453ba04 1770
61e57a8d
AJ		 1771#define DDC_SEGMENT_ADDR 0x30
1772/**
db6cf833 1773 * drm_do_probe_ddc_edid() - get EDID information via I2C
7c58e87e 1774 * @data: I2C device adapter
fc66811c
DV		 1775 * @buf: EDID data buffer to be filled
1776 * @block: 128 byte EDID block to start fetching from
1777 * @len: EDID data buffer length to fetch
1778 *
db6cf833 1779 * Try to fetch EDID information by calling I2C driver functions.
61e57a8d 1780 *
db6cf833 1781 * Return: 0 on success or -1 on failure.
61e57a8d
AJ		 1782 */
1783static int
18df89fe 1784drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
61e57a8d 1785{
18df89fe 1786 struct i2c_adapter *adapter = data;
61e57a8d 1787 unsigned char start = block * EDID_LENGTH;
cd004b3f
S		 1788 unsigned char segment = block >> 1;
1789 unsigned char xfers = segment ? 3 : 2;
4819d2e4
CW		 1790 int ret, retries = 5;
1791
db6cf833
TR		 1792 /*
1793 * The core I2C driver will automatically retry the transfer if the
4819d2e4
CW		 1794 * adapter reports EAGAIN. However, we find that bit-banging transfers
1795 * are susceptible to errors under a heavily loaded machine and
1796 * generate spurious NAKs and timeouts. Retrying the transfer
1797 * of the individual block a few times seems to overcome this.
1798 */
1799 do {
1800 struct i2c_msg msgs[] = {
1801 {
cd004b3f
S		 1802 .addr = DDC_SEGMENT_ADDR,
1803 .flags = 0,
1804 .len = 1,
1805 .buf = &segment,
1806 }, {
4819d2e4
CW		 1807 .addr = DDC_ADDR,
1808 .flags = 0,
1809 .len = 1,
1810 .buf = &start,
1811 }, {
1812 .addr = DDC_ADDR,
1813 .flags = I2C_M_RD,
1814 .len = len,
1815 .buf = buf,
1816 }
1817 };
cd004b3f 1818
db6cf833
TR		 1819 /*
1820 * Avoid sending the segment addr to not upset non-compliant
1821 * DDC monitors.
1822 */
cd004b3f
S		 1823 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1824
9292f37e
ED		 1825 if (ret == -ENXIO) {
1826 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1827 adapter->name);
1828 break;
1829 }
cd004b3f 1830 } while (ret != xfers && --retries);
4819d2e4 1831
cd004b3f 1832 return ret == xfers ? 0 : -1;
61e57a8d
AJ		 1833}
1834
14544d09
CW		 1835static void connector_bad_edid(struct drm_connector *connector,
1836 u8 *edid, int num_blocks)
1837{
1838 int i;
e11f5bd8
JFZ		 1839 u8 num_of_ext = edid[0x7e];
1840
1841 /* Calculate real checksum for the last edid extension block data */
1842 connector->real_edid_checksum =
1843 drm_edid_block_checksum(edid + num_of_ext * EDID_LENGTH);
14544d09 1844
f0a8f533 1845 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
14544d09
CW		 1846 return;
1847
1848 dev_warn(connector->dev->dev,
1849 "%s: EDID is invalid:\n",
1850 connector->name);
1851 for (i = 0; i < num_blocks; i++) {
1852 u8 *block = edid + i * EDID_LENGTH;
1853 char prefix[20];
1854
1855 if (drm_edid_is_zero(block, EDID_LENGTH))
1856 sprintf(prefix, "\t[%02x] ZERO ", i);
1857 else if (!drm_edid_block_valid(block, i, false, NULL))
1858 sprintf(prefix, "\t[%02x] BAD ", i);
1859 else
1860 sprintf(prefix, "\t[%02x] GOOD ", i);
1861
1862 print_hex_dump(KERN_WARNING,
1863 prefix, DUMP_PREFIX_NONE, 16, 1,
1864 block, EDID_LENGTH, false);
1865 }
1866}
1867
56a2b7f2
JN		 1868/* Get override or firmware EDID */
1869static struct edid *drm_get_override_edid(struct drm_connector *connector)
1870{
1871 struct edid *override = NULL;
1872
1873 if (connector->override_edid)
1874 override = drm_edid_duplicate(connector->edid_blob_ptr->data);
1875
1876 if (!override)
1877 override = drm_load_edid_firmware(connector);
1878
1879 return IS_ERR(override) ? NULL : override;
1880}
1881
48eaeb76
JN		 1882/**
1883 * drm_add_override_edid_modes - add modes from override/firmware EDID
1884 * @connector: connector we're probing
1885 *
1886 * Add modes from the override/firmware EDID, if available. Only to be used from
1887 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
1888 * failed during drm_get_edid() and caused the override/firmware EDID to be
1889 * skipped.
1890 *
1891 * Return: The number of modes added or 0 if we couldn't find any.
1892 */
1893int drm_add_override_edid_modes(struct drm_connector *connector)
1894{
1895 struct edid *override;
1896 int num_modes = 0;
1897
1898 override = drm_get_override_edid(connector);
1899 if (override) {
1900 drm_connector_update_edid_property(connector, override);
1901 num_modes = drm_add_edid_modes(connector, override);
1902 kfree(override);
1903
1904 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
1905 connector->base.id, connector->name, num_modes);
1906 }
1907
1908 return num_modes;
1909}
1910EXPORT_SYMBOL(drm_add_override_edid_modes);
1911
18df89fe
LPC		 1912/**
1913 * drm_do_get_edid - get EDID data using a custom EDID block read function
1914 * @connector: connector we're probing
1915 * @get_edid_block: EDID block read function
1916 * @data: private data passed to the block read function
1917 *
1918 * When the I2C adapter connected to the DDC bus is hidden behind a device that
1919 * exposes a different interface to read EDID blocks this function can be used
1920 * to get EDID data using a custom block read function.
1921 *
1922 * As in the general case the DDC bus is accessible by the kernel at the I2C
1923 * level, drivers must make all reasonable efforts to expose it as an I2C
1924 * adapter and use drm_get_edid() instead of abusing this function.
1925 *
53fd40a9
JN		 1926 * The EDID may be overridden using debugfs override_edid or firmare EDID
1927 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
1928 * order. Having either of them bypasses actual EDID reads.
1929 *
18df89fe
LPC		 1930 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1931 */
1932struct edid *drm_do_get_edid(struct drm_connector *connector,
1933 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
1934 size_t len),
1935 void *data)
61e57a8d 1936{
0ea75e23 1937 int i, j = 0, valid_extensions = 0;
f14f3686 1938 u8 *edid, *new;
56a2b7f2 1939 struct edid *override;
53fd40a9 1940
56a2b7f2
JN		 1941 override = drm_get_override_edid(connector);
1942 if (override)
53fd40a9 1943 return override;
61e57a8d 1944
f14f3686 1945 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
61e57a8d
AJ		 1946 return NULL;
1947
1948 /* base block fetch */
1949 for (i = 0; i < 4; i++) {
f14f3686 1950 if (get_edid_block(data, edid, 0, EDID_LENGTH))
61e57a8d 1951 goto out;
14544d09 1952 if (drm_edid_block_valid(edid, 0, false,
6ba2bd3d 1953 &connector->edid_corrupt))
61e57a8d 1954 break;
f14f3686 1955 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) {
4a9a8b71
DA		 1956 connector->null_edid_counter++;
1957 goto carp;
1958 }
61e57a8d
AJ		 1959 }
1960 if (i == 4)
1961 goto carp;
1962
1963 /* if there's no extensions, we're done */
14544d09
CW		 1964 valid_extensions = edid[0x7e];
1965 if (valid_extensions == 0)
f14f3686 1966 return (struct edid *)edid;
61e57a8d 1967
14544d09 1968 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
61e57a8d
AJ		 1969 if (!new)
1970 goto out;
f14f3686 1971 edid = new;
61e57a8d 1972
f14f3686 1973 for (j = 1; j <= edid[0x7e]; j++) {
14544d09 1974 u8 *block = edid + j * EDID_LENGTH;
a28187cc 1975
61e57a8d 1976 for (i = 0; i < 4; i++) {
a28187cc 1977 if (get_edid_block(data, block, j, EDID_LENGTH))
61e57a8d 1978 goto out;
14544d09 1979 if (drm_edid_block_valid(block, j, false, NULL))
61e57a8d
AJ		 1980 break;
1981 }
f934ec8c 1982
14544d09
CW		 1983 if (i == 4)
1984 valid_extensions--;
0ea75e23
ST		 1985 }
1986
f14f3686 1987 if (valid_extensions != edid[0x7e]) {
14544d09
CW		 1988 u8 *base;
1989
1990 connector_bad_edid(connector, edid, edid[0x7e] + 1);
1991
f14f3686
CW		 1992 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions;
1993 edid[0x7e] = valid_extensions;
14544d09 1994
6da2ec56
KC		 1995 new = kmalloc_array(valid_extensions + 1, EDID_LENGTH,
1996 GFP_KERNEL);
0ea75e23
ST		 1997 if (!new)
1998 goto out;
14544d09
CW		 1999
2000 base = new;
2001 for (i = 0; i <= edid[0x7e]; i++) {
2002 u8 *block = edid + i * EDID_LENGTH;
2003
2004 if (!drm_edid_block_valid(block, i, false, NULL))
2005 continue;
2006
2007 memcpy(base, block, EDID_LENGTH);
2008 base += EDID_LENGTH;
2009 }
2010
2011 kfree(edid);
f14f3686 2012 edid = new;
61e57a8d
AJ		 2013 }
2014
f14f3686 2015 return (struct edid *)edid;
61e57a8d
AJ		 2016
2017carp:
14544d09 2018 connector_bad_edid(connector, edid, 1);
61e57a8d 2019out:
f14f3686 2020 kfree(edid);
61e57a8d
AJ		 2021 return NULL;
2022}
18df89fe 2023EXPORT_SYMBOL_GPL(drm_do_get_edid);
61e57a8d
AJ		 2024
2025/**
db6cf833
TR		 2026 * drm_probe_ddc() - probe DDC presence
2027 * @adapter: I2C adapter to probe
fc66811c 2028 *
db6cf833 2029 * Return: True on success, false on failure.
61e57a8d 2030 */
fbff4690 2031bool
61e57a8d
AJ		 2032drm_probe_ddc(struct i2c_adapter *adapter)
2033{
2034 unsigned char out;
2035
2036 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
2037}
fbff4690 2038EXPORT_SYMBOL(drm_probe_ddc);
61e57a8d
AJ		 2039
2040/**
2041 * drm_get_edid - get EDID data, if available
2042 * @connector: connector we're probing
db6cf833 2043 * @adapter: I2C adapter to use for DDC
61e57a8d 2044 *
db6cf833 2045 * Poke the given I2C channel to grab EDID data if possible. If found,
61e57a8d
AJ		 2046 * attach it to the connector.
2047 *
db6cf833 2048 * Return: Pointer to valid EDID or NULL if we couldn't find any.
61e57a8d
AJ		 2049 */
2050struct edid *drm_get_edid(struct drm_connector *connector,
2051 struct i2c_adapter *adapter)
2052{
15f080f0
JN		 2053 if (connector->force == DRM_FORCE_OFF)
2054 return NULL;
2055
2056 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
18df89fe 2057 return NULL;
61e57a8d 2058
092c367a 2059 return drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
61e57a8d
AJ		 2060}
2061EXPORT_SYMBOL(drm_get_edid);
2062
5cb8eaa2
LW		 2063/**
2064 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
2065 * @connector: connector we're probing
2066 * @adapter: I2C adapter to use for DDC
2067 *
2068 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
2069 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
2070 * switch DDC to the GPU which is retrieving EDID.
2071 *
2072 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2073 */
2074struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
2075 struct i2c_adapter *adapter)
2076{
2077 struct pci_dev *pdev = connector->dev->pdev;
2078 struct edid *edid;
2079
2080 vga_switcheroo_lock_ddc(pdev);
2081 edid = drm_get_edid(connector, adapter);
2082 vga_switcheroo_unlock_ddc(pdev);
2083
2084 return edid;
2085}
2086EXPORT_SYMBOL(drm_get_edid_switcheroo);
2087
51f8da59
JN		 2088/**
2089 * drm_edid_duplicate - duplicate an EDID and the extensions
2090 * @edid: EDID to duplicate
2091 *
db6cf833 2092 * Return: Pointer to duplicated EDID or NULL on allocation failure.
51f8da59
JN		 2093 */
2094struct edid *drm_edid_duplicate(const struct edid *edid)
2095{
2096 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
2097}
2098EXPORT_SYMBOL(drm_edid_duplicate);
2099
61e57a8d
AJ		 2100/*** EDID parsing ***/
2101
f453ba04
DA		 2102/**
2103 * edid_vendor - match a string against EDID's obfuscated vendor field
2104 * @edid: EDID to match
2105 * @vendor: vendor string
2106 *
2107 * Returns true if @vendor is in @edid, false otherwise
2108 */
170178fe 2109static bool edid_vendor(const struct edid *edid, const char *vendor)
f453ba04
DA		 2110{
2111 char edid_vendor[3];
2112
2113 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
2114 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
2115 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
16456c87 2116 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
f453ba04
DA		 2117
2118 return !strncmp(edid_vendor, vendor, 3);
2119}
2120
2121/**
2122 * edid_get_quirks - return quirk flags for a given EDID
2123 * @edid: EDID to process
2124 *
2125 * This tells subsequent routines what fixes they need to apply.
2126 */
170178fe 2127static u32 edid_get_quirks(const struct edid *edid)
f453ba04 2128{
23c4cfbd 2129 const struct edid_quirk *quirk;
f453ba04
DA		 2130 int i;
2131
2132 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
2133 quirk = &edid_quirk_list[i];
2134
2135 if (edid_vendor(edid, quirk->vendor) &&
2136 (EDID_PRODUCT_ID(edid) == quirk->product_id))
2137 return quirk->quirks;
2138 }
2139
2140 return 0;
2141}
2142
2143#define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
339d202c 2144#define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
f453ba04 2145
f453ba04
DA		 2146/**
2147 * edid_fixup_preferred - set preferred modes based on quirk list
2148 * @connector: has mode list to fix up
2149 * @quirks: quirks list
2150 *
2151 * Walk the mode list for @connector, clearing the preferred status
2152 * on existing modes and setting it anew for the right mode ala @quirks.
2153 */
2154static void edid_fixup_preferred(struct drm_connector *connector,
2155 u32 quirks)
2156{
2157 struct drm_display_mode *t, *cur_mode, *preferred_mode;
f890607b 2158 int target_refresh = 0;
339d202c 2159 int cur_vrefresh, preferred_vrefresh;
f453ba04
DA		 2160
2161 if (list_empty(&connector->probed_modes))
2162 return;
2163
2164 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
2165 target_refresh = 60;
2166 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
2167 target_refresh = 75;
2168
2169 preferred_mode = list_first_entry(&connector->probed_modes,
2170 struct drm_display_mode, head);
2171
2172 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
2173 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
2174
2175 if (cur_mode == preferred_mode)
2176 continue;
2177
2178 /* Largest mode is preferred */
2179 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
2180 preferred_mode = cur_mode;
2181
0425662f
VS		 2182 cur_vrefresh = drm_mode_vrefresh(cur_mode);
2183 preferred_vrefresh = drm_mode_vrefresh(preferred_mode);
f453ba04
DA		 2184 /* At a given size, try to get closest to target refresh */
2185 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
339d202c
AD		 2186 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
2187 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
f453ba04
DA		 2188 preferred_mode = cur_mode;
2189 }
2190 }
2191
2192 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
2193}
2194
f6e252ba
AJ		 2195static bool
2196mode_is_rb(const struct drm_display_mode *mode)
2197{
2198 return (mode->htotal - mode->hdisplay == 160) &&
2199 (mode->hsync_end - mode->hdisplay == 80) &&
2200 (mode->hsync_end - mode->hsync_start == 32) &&
2201 (mode->vsync_start - mode->vdisplay == 3);
2202}
2203
33c7531d
AJ		 2204/*
2205 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
2206 * @dev: Device to duplicate against
2207 * @hsize: Mode width
2208 * @vsize: Mode height
2209 * @fresh: Mode refresh rate
f6e252ba 2210 * @rb: Mode reduced-blanking-ness
33c7531d
AJ		 2211 *
2212 * Walk the DMT mode list looking for a match for the given parameters.
db6cf833
TR		 2213 *
2214 * Return: A newly allocated copy of the mode, or NULL if not found.
33c7531d 2215 */
1d42bbc8 2216struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
f6e252ba
AJ		 2217 int hsize, int vsize, int fresh,
2218 bool rb)
559ee21d 2219{
07a5e632 2220 int i;
559ee21d 2221
a6b21831 2222 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
b1f559ec 2223 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
f8b46a05
AJ		 2224 if (hsize != ptr->hdisplay)
2225 continue;
2226 if (vsize != ptr->vdisplay)
2227 continue;
2228 if (fresh != drm_mode_vrefresh(ptr))
2229 continue;
f6e252ba
AJ		 2230 if (rb != mode_is_rb(ptr))
2231 continue;
f8b46a05
AJ		 2232
2233 return drm_mode_duplicate(dev, ptr);
559ee21d 2234 }
f8b46a05
AJ		 2235
2236 return NULL;
559ee21d 2237}
1d42bbc8 2238EXPORT_SYMBOL(drm_mode_find_dmt);
23425cae 2239
a7a131ac
VS		 2240static bool is_display_descriptor(const u8 d[18], u8 tag)
2241{
2242 return d[0] == 0x00 && d[1] == 0x00 &&
2243 d[2] == 0x00 && d[3] == tag;
2244}
2245
f447dd1f
VS		 2246static bool is_detailed_timing_descriptor(const u8 d[18])
2247{
2248 return d[0] != 0x00 || d[1] != 0x00;
2249}
2250
d1ff6409
AJ		 2251typedef void detailed_cb(struct detailed_timing *timing, void *closure);
2252
4d76a221
AJ		 2253static void
2254cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
2255{
7304b981 2256 int i, n;
4966b2a9 2257 u8 d = ext[0x02];
4d76a221
AJ		 2258 u8 *det_base = ext + d;
2259
7304b981
VS		 2260 if (d < 4 || d > 127)
2261 return;
2262
4966b2a9 2263 n = (127 - d) / 18;
4d76a221
AJ		 2264 for (i = 0; i < n; i++)
2265 cb((struct detailed_timing *)(det_base + 18 * i), closure);
2266}
2267
cbba98f8
AJ		 2268static void
2269vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
2270{
2271 unsigned int i, n = min((int)ext[0x02], 6);
2272 u8 *det_base = ext + 5;
2273
2274 if (ext[0x01] != 1)
2275 return; /* unknown version */
2276
2277 for (i = 0; i < n; i++)
2278 cb((struct detailed_timing *)(det_base + 18 * i), closure);
2279}
2280
d1ff6409
AJ		 2281static void
2282drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
2283{
2284 int i;
2285 struct edid *edid = (struct edid *)raw_edid;
2286
2287 if (edid == NULL)
2288 return;
2289
2290 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
2291 cb(&(edid->detailed_timings[i]), closure);
2292
4d76a221
AJ		 2293 for (i = 1; i <= raw_edid[0x7e]; i++) {
2294 u8 *ext = raw_edid + (i * EDID_LENGTH);
2295 switch (*ext) {
2296 case CEA_EXT:
2297 cea_for_each_detailed_block(ext, cb, closure);
2298 break;
cbba98f8
AJ		 2299 case VTB_EXT:
2300 vtb_for_each_detailed_block(ext, cb, closure);
2301 break;
4d76a221
AJ		 2302 default:
2303 break;
2304 }
2305 }
d1ff6409
AJ		 2306}
2307
2308static void
2309is_rb(struct detailed_timing *t, void *data)
2310{
2311 u8 *r = (u8 *)t;
a7a131ac
VS		 2312
2313 if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE))
2314 return;
2315
2316 if (r[15] & 0x10)
2317 *(bool *)data = true;
d1ff6409
AJ		 2318}
2319
2320/* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
2321static bool
2322drm_monitor_supports_rb(struct edid *edid)
2323{
2324 if (edid->revision >= 4) {
b196a498 2325 bool ret = false;
d1ff6409
AJ		 2326 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
2327 return ret;
2328 }
2329
2330 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
2331}
2332
7a374350
AJ		 2333static void
2334find_gtf2(struct detailed_timing *t, void *data)
2335{
2336 u8 *r = (u8 *)t;
a7a131ac
VS		 2337
2338 if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE))
2339 return;
2340
2341 if (r[10] == 0x02)
7a374350
AJ		 2342 *(u8 **)data = r;
2343}
2344
2345/* Secondary GTF curve kicks in above some break frequency */
2346static int
2347drm_gtf2_hbreak(struct edid *edid)
2348{
2349 u8 *r = NULL;
2350 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2351 return r ? (r[12] * 2) : 0;
2352}
2353
2354static int
2355drm_gtf2_2c(struct edid *edid)
2356{
2357 u8 *r = NULL;
2358 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2359 return r ? r[13] : 0;
2360}
2361
2362static int
2363drm_gtf2_m(struct edid *edid)
2364{
2365 u8 *r = NULL;
2366 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2367 return r ? (r[15] << 8) + r[14] : 0;
2368}
2369
2370static int
2371drm_gtf2_k(struct edid *edid)
2372{
2373 u8 *r = NULL;
2374 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2375 return r ? r[16] : 0;
2376}
2377
2378static int
2379drm_gtf2_2j(struct edid *edid)
2380{
2381 u8 *r = NULL;
2382 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2383 return r ? r[17] : 0;
2384}
2385
2386/**
2387 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
2388 * @edid: EDID block to scan
2389 */
2390static int standard_timing_level(struct edid *edid)
2391{
2392 if (edid->revision >= 2) {
2393 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
2394 return LEVEL_CVT;
2395 if (drm_gtf2_hbreak(edid))
2396 return LEVEL_GTF2;
bfef04ad
LS		 2397 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
2398 return LEVEL_GTF;
7a374350
AJ		 2399 }
2400 return LEVEL_DMT;
2401}
2402
23425cae
AJ		 2403/*
2404 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
2405 * monitors fill with ascii space (0x20) instead.
2406 */
2407static int
2408bad_std_timing(u8 a, u8 b)
2409{
2410 return (a == 0x00 && b == 0x00) ||
2411 (a == 0x01 && b == 0x01) ||
2412 (a == 0x20 && b == 0x20);
2413}
2414
58911c24
VS		 2415static int drm_mode_hsync(const struct drm_display_mode *mode)
2416{
2417 if (mode->htotal <= 0)
2418 return 0;
2419
2420 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal);
2421}
2422
f453ba04
DA		 2423/**
2424 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
fc66811c
DV		 2425 * @connector: connector of for the EDID block
2426 * @edid: EDID block to scan
f453ba04
DA		 2427 * @t: standard timing params
2428 *
2429 * Take the standard timing params (in this case width, aspect, and refresh)
5c61259e 2430 * and convert them into a real mode using CVT/GTF/DMT.
f453ba04 2431 */
7ca6adb3 2432static struct drm_display_mode *
7a374350 2433drm_mode_std(struct drm_connector *connector, struct edid *edid,
464fdeca 2434 struct std_timing *t)
f453ba04 2435{
7ca6adb3
AJ		 2436 struct drm_device *dev = connector->dev;
2437 struct drm_display_mode *m, *mode = NULL;
5c61259e
ZY		 2438 int hsize, vsize;
2439 int vrefresh_rate;
0454beab
MD		 2440 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
2441 >> EDID_TIMING_ASPECT_SHIFT;
5c61259e
ZY		 2442 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
2443 >> EDID_TIMING_VFREQ_SHIFT;
7a374350 2444 int timing_level = standard_timing_level(edid);
5c61259e 2445
23425cae
AJ		 2446 if (bad_std_timing(t->hsize, t->vfreq_aspect))
2447 return NULL;
2448
5c61259e
ZY		 2449 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
2450 hsize = t->hsize * 8 + 248;
2451 /* vrefresh_rate = vfreq + 60 */
2452 vrefresh_rate = vfreq + 60;
2453 /* the vdisplay is calculated based on the aspect ratio */
f066a17d 2454 if (aspect_ratio == 0) {
464fdeca 2455 if (edid->revision < 3)
f066a17d
AJ		 2456 vsize = hsize;
2457 else
2458 vsize = (hsize * 10) / 16;
2459 } else if (aspect_ratio == 1)
f453ba04 2460 vsize = (hsize * 3) / 4;
0454beab 2461 else if (aspect_ratio == 2)
f453ba04
DA		 2462 vsize = (hsize * 4) / 5;
2463 else
2464 vsize = (hsize * 9) / 16;
a0910c8e
AJ		 2465
2466 /* HDTV hack, part 1 */
2467 if (vrefresh_rate == 60 &&
2468 ((hsize == 1360 && vsize == 765) ||
2469 (hsize == 1368 && vsize == 769))) {
2470 hsize = 1366;
2471 vsize = 768;
2472 }
2473
7ca6adb3
AJ		 2474 /*
2475 * If this connector already has a mode for this size and refresh
2476 * rate (because it came from detailed or CVT info), use that
2477 * instead. This way we don't have to guess at interlace or
2478 * reduced blanking.
2479 */
522032da 2480 list_for_each_entry(m, &connector->probed_modes, head)
7ca6adb3
AJ		 2481 if (m->hdisplay == hsize && m->vdisplay == vsize &&
2482 drm_mode_vrefresh(m) == vrefresh_rate)
2483 return NULL;
2484
a0910c8e
AJ		 2485 /* HDTV hack, part 2 */
2486 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
2487 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
d50ba256 2488 false);
a5ef6567
JM		 2489 if (!mode)
2490 return NULL;
559ee21d 2491 mode->hdisplay = 1366;
a4967de6
AJ		 2492 mode->hsync_start = mode->hsync_start - 1;
2493 mode->hsync_end = mode->hsync_end - 1;
559ee21d
ZY		 2494 return mode;
2495 }
a0910c8e 2496
559ee21d 2497 /* check whether it can be found in default mode table */
f6e252ba
AJ		 2498 if (drm_monitor_supports_rb(edid)) {
2499 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
2500 true);
2501 if (mode)
2502 return mode;
2503 }
2504 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
559ee21d
ZY		 2505 if (mode)
2506 return mode;
2507
f6e252ba 2508 /* okay, generate it */
5c61259e
ZY		 2509 switch (timing_level) {
2510 case LEVEL_DMT:
5c61259e
ZY		 2511 break;
2512 case LEVEL_GTF:
2513 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2514 break;
7a374350
AJ		 2515 case LEVEL_GTF2:
2516 /*
2517 * This is potentially wrong if there's ever a monitor with
2518 * more than one ranges section, each claiming a different
2519 * secondary GTF curve. Please don't do that.
2520 */
2521 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
fc48f169
TI		 2522 if (!mode)
2523 return NULL;
7a374350 2524 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
aefd330e 2525 drm_mode_destroy(dev, mode);
7a374350
AJ		 2526 mode = drm_gtf_mode_complex(dev, hsize, vsize,
2527 vrefresh_rate, 0, 0,
2528 drm_gtf2_m(edid),
2529 drm_gtf2_2c(edid),
2530 drm_gtf2_k(edid),
2531 drm_gtf2_2j(edid));
2532 }
2533 break;
5c61259e 2534 case LEVEL_CVT:
d50ba256
DA		 2535 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
2536 false);
5c61259e
ZY		 2537 break;
2538 }
f453ba04
DA		 2539 return mode;
2540}
2541
b58db2c6
AJ		 2542/*
2543 * EDID is delightfully ambiguous about how interlaced modes are to be
2544 * encoded. Our internal representation is of frame height, but some
2545 * HDTV detailed timings are encoded as field height.
2546 *
2547 * The format list here is from CEA, in frame size. Technically we
2548 * should be checking refresh rate too. Whatever.
2549 */
2550static void
2551drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
2552 struct detailed_pixel_timing *pt)
2553{
2554 int i;
2555 static const struct {
2556 int w, h;
2557 } cea_interlaced[] = {
2558 { 1920, 1080 },
2559 { 720, 480 },
2560 { 1440, 480 },
2561 { 2880, 480 },
2562 { 720, 576 },
2563 { 1440, 576 },
2564 { 2880, 576 },
2565 };
b58db2c6
AJ		 2566
2567 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
2568 return;
2569
3c581411 2570 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
b58db2c6
AJ		 2571 if ((mode->hdisplay == cea_interlaced[i].w) &&
2572 (mode->vdisplay == cea_interlaced[i].h / 2)) {
2573 mode->vdisplay *= 2;
2574 mode->vsync_start *= 2;
2575 mode->vsync_end *= 2;
2576 mode->vtotal *= 2;
2577 mode->vtotal |= 1;
2578 }
2579 }
2580
2581 mode->flags |= DRM_MODE_FLAG_INTERLACE;
2582}
2583
f453ba04
DA		 2584/**
2585 * drm_mode_detailed - create a new mode from an EDID detailed timing section
2586 * @dev: DRM device (needed to create new mode)
2587 * @edid: EDID block
2588 * @timing: EDID detailed timing info
2589 * @quirks: quirks to apply
2590 *
2591 * An EDID detailed timing block contains enough info for us to create and
2592 * return a new struct drm_display_mode.
2593 */
2594static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
2595 struct edid *edid,
2596 struct detailed_timing *timing,
2597 u32 quirks)
2598{
2599 struct drm_display_mode *mode;
2600 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
0454beab
MD		 2601 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
2602 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
2603 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
2604 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
e14cbee4
MD		 2605 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
2606 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
16dad1d7 2607 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
e14cbee4 2608 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
f453ba04 2609
fc438966 2610 /* ignore tiny modes */
0454beab 2611 if (hactive < 64 || vactive < 64)
fc438966
AJ		 2612 return NULL;
2613
0454beab 2614 if (pt->misc & DRM_EDID_PT_STEREO) {
c7d015f3 2615 DRM_DEBUG_KMS("stereo mode not supported\n");
f453ba04
DA		 2616 return NULL;
2617 }
0454beab 2618 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
c7d015f3 2619 DRM_DEBUG_KMS("composite sync not supported\n");
f453ba04
DA		 2620 }
2621
fcb45611
ZY		 2622 /* it is incorrect if hsync/vsync width is zero */
2623 if (!hsync_pulse_width || !vsync_pulse_width) {
2624 DRM_DEBUG_KMS("Incorrect Detailed timing. "
2625 "Wrong Hsync/Vsync pulse width\n");
2626 return NULL;
2627 }
bc42aabc
AJ		 2628
2629 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
2630 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
2631 if (!mode)
2632 return NULL;
2633
2634 goto set_size;
2635 }
2636
f453ba04
DA		 2637 mode = drm_mode_create(dev);
2638 if (!mode)
2639 return NULL;
2640
f453ba04 2641 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
0454beab
MD		 2642 timing->pixel_clock = cpu_to_le16(1088);
2643
2644 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
2645
2646 mode->hdisplay = hactive;
2647 mode->hsync_start = mode->hdisplay + hsync_offset;
2648 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
2649 mode->htotal = mode->hdisplay + hblank;
2650
2651 mode->vdisplay = vactive;
2652 mode->vsync_start = mode->vdisplay + vsync_offset;
2653 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
2654 mode->vtotal = mode->vdisplay + vblank;
f453ba04 2655
7064fef5
JB		 2656 /* Some EDIDs have bogus h/vtotal values */
2657 if (mode->hsync_end > mode->htotal)
2658 mode->htotal = mode->hsync_end + 1;
2659 if (mode->vsync_end > mode->vtotal)
2660 mode->vtotal = mode->vsync_end + 1;
2661
b58db2c6 2662 drm_mode_do_interlace_quirk(mode, pt);
f453ba04
DA		 2663
2664 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
0454beab 2665 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
f453ba04
DA		 2666 }
2667
0454beab
MD		 2668 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
2669 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
2670 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
2671 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
f453ba04 2672
bc42aabc 2673set_size:
e14cbee4
MD		 2674 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
2675 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
f453ba04
DA		 2676
2677 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
2678 mode->width_mm *= 10;
2679 mode->height_mm *= 10;
2680 }
2681
2682 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
2683 mode->width_mm = edid->width_cm * 10;
2684 mode->height_mm = edid->height_cm * 10;
2685 }
2686
bc42aabc
AJ		 2687 mode->type = DRM_MODE_TYPE_DRIVER;
2688 drm_mode_set_name(mode);
2689
f453ba04
DA		 2690 return mode;
2691}
2692
b17e52ef 2693static bool
b1f559ec
CW		 2694mode_in_hsync_range(const struct drm_display_mode *mode,
2695 struct edid *edid, u8 *t)
b17e52ef
AJ		 2696{
2697 int hsync, hmin, hmax;
2698
2699 hmin = t[7];
2700 if (edid->revision >= 4)
2701 hmin += ((t[4] & 0x04) ? 255 : 0);
2702 hmax = t[8];
2703 if (edid->revision >= 4)
2704 hmax += ((t[4] & 0x08) ? 255 : 0);
07a5e632 2705 hsync = drm_mode_hsync(mode);
07a5e632 2706
b17e52ef
AJ		 2707 return (hsync <= hmax && hsync >= hmin);
2708}
2709
2710static bool
b1f559ec
CW		 2711mode_in_vsync_range(const struct drm_display_mode *mode,
2712 struct edid *edid, u8 *t)
b17e52ef
AJ		 2713{
2714 int vsync, vmin, vmax;
2715
2716 vmin = t[5];
2717 if (edid->revision >= 4)
2718 vmin += ((t[4] & 0x01) ? 255 : 0);
2719 vmax = t[6];
2720 if (edid->revision >= 4)
2721 vmax += ((t[4] & 0x02) ? 255 : 0);
2722 vsync = drm_mode_vrefresh(mode);
2723
2724 return (vsync <= vmax && vsync >= vmin);
2725}
2726
2727static u32
2728range_pixel_clock(struct edid *edid, u8 *t)
2729{
2730 /* unspecified */
2731 if (t[9] == 0 || t[9] == 255)
2732 return 0;
2733
2734 /* 1.4 with CVT support gives us real precision, yay */
2735 if (edid->revision >= 4 && t[10] == 0x04)
2736 return (t[9] * 10000) - ((t[12] >> 2) * 250);
2737
2738 /* 1.3 is pathetic, so fuzz up a bit */
2739 return t[9] * 10000 + 5001;
2740}
2741
b17e52ef 2742static bool
b1f559ec 2743mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
b17e52ef
AJ		 2744 struct detailed_timing *timing)
2745{
2746 u32 max_clock;
2747 u8 *t = (u8 *)timing;
2748
2749 if (!mode_in_hsync_range(mode, edid, t))
07a5e632
AJ		 2750 return false;
2751
b17e52ef 2752 if (!mode_in_vsync_range(mode, edid, t))
07a5e632
AJ		 2753 return false;
2754
b17e52ef 2755 if ((max_clock = range_pixel_clock(edid, t)))
07a5e632
AJ		 2756 if (mode->clock > max_clock)
2757 return false;
b17e52ef
AJ		 2758
2759 /* 1.4 max horizontal check */
2760 if (edid->revision >= 4 && t[10] == 0x04)
2761 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
2762 return false;
2763
2764 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
2765 return false;
07a5e632
AJ		 2766
2767 return true;
2768}
2769
7b668ebe
TI		 2770static bool valid_inferred_mode(const struct drm_connector *connector,
2771 const struct drm_display_mode *mode)
2772{
85f8fcd6 2773 const struct drm_display_mode *m;
7b668ebe
TI		 2774 bool ok = false;
2775
2776 list_for_each_entry(m, &connector->probed_modes, head) {
2777 if (mode->hdisplay == m->hdisplay &&
2778 mode->vdisplay == m->vdisplay &&
2779 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
2780 return false; /* duplicated */
2781 if (mode->hdisplay <= m->hdisplay &&
2782 mode->vdisplay <= m->vdisplay)
2783 ok = true;
2784 }
2785 return ok;
2786}
2787
b17e52ef 2788static int
cd4cd3de 2789drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
b17e52ef 2790 struct detailed_timing *timing)
07a5e632
AJ		 2791{
2792 int i, modes = 0;
2793 struct drm_display_mode *newmode;
2794 struct drm_device *dev = connector->dev;
2795
a6b21831 2796 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
7b668ebe
TI		 2797 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
2798 valid_inferred_mode(connector, drm_dmt_modes + i)) {
07a5e632
AJ		 2799 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
2800 if (newmode) {
2801 drm_mode_probed_add(connector, newmode);
2802 modes++;
2803 }
2804 }
2805 }
2806
2807 return modes;
2808}
2809
c09dedb7
TI		 2810/* fix up 1366x768 mode from 1368x768;
2811 * GFT/CVT can't express 1366 width which isn't dividable by 8
2812 */
969218fe 2813void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
c09dedb7
TI		 2814{
2815 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
2816 mode->hdisplay = 1366;
2817 mode->hsync_start--;
2818 mode->hsync_end--;
2819 drm_mode_set_name(mode);
2820 }
2821}
2822
b309bd37
AJ		 2823static int
2824drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
2825 struct detailed_timing *timing)
2826{
2827 int i, modes = 0;
2828 struct drm_display_mode *newmode;
2829 struct drm_device *dev = connector->dev;
2830
a6b21831 2831 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
b309bd37
AJ		 2832 const struct minimode *m = &extra_modes[i];
2833 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
fc48f169
TI		 2834 if (!newmode)
2835 return modes;
b309bd37 2836
969218fe 2837 drm_mode_fixup_1366x768(newmode);
7b668ebe
TI		 2838 if (!mode_in_range(newmode, edid, timing) ||
2839 !valid_inferred_mode(connector, newmode)) {
b309bd37
AJ		 2840 drm_mode_destroy(dev, newmode);
2841 continue;
2842 }
2843
2844 drm_mode_probed_add(connector, newmode);
2845 modes++;
2846 }
2847
2848 return modes;
2849}
2850
2851static int
2852drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2853 struct detailed_timing *timing)
2854{
2855 int i, modes = 0;
2856 struct drm_display_mode *newmode;
2857 struct drm_device *dev = connector->dev;
2858 bool rb = drm_monitor_supports_rb(edid);
2859
a6b21831 2860 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
b309bd37
AJ		 2861 const struct minimode *m = &extra_modes[i];
2862 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
fc48f169
TI		 2863 if (!newmode)
2864 return modes;
b309bd37 2865
969218fe 2866 drm_mode_fixup_1366x768(newmode);
7b668ebe
TI		 2867 if (!mode_in_range(newmode, edid, timing) ||
2868 !valid_inferred_mode(connector, newmode)) {
b309bd37
AJ		 2869 drm_mode_destroy(dev, newmode);
2870 continue;
2871 }
2872
2873 drm_mode_probed_add(connector, newmode);
2874 modes++;
2875 }
2876
2877 return modes;
2878}
2879
13931579
AJ		 2880static void
2881do_inferred_modes(struct detailed_timing *timing, void *c)
9340d8cf 2882{
13931579
AJ		 2883 struct detailed_mode_closure *closure = c;
2884 struct detailed_non_pixel *data = &timing->data.other_data;
b309bd37 2885 struct detailed_data_monitor_range *range = &data->data.range;
9340d8cf 2886
a7a131ac 2887 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE))
cb21aafe
AJ		 2888 return;
2889
2890 closure->modes += drm_dmt_modes_for_range(closure->connector,
2891 closure->edid,
2892 timing);
4d23f484 2893
b309bd37
AJ		 2894 if (!version_greater(closure->edid, 1, 1))
2895 return; /* GTF not defined yet */
2896
2897 switch (range->flags) {
2898 case 0x02: /* secondary gtf, XXX could do more */
2899 case 0x00: /* default gtf */
2900 closure->modes += drm_gtf_modes_for_range(closure->connector,
2901 closure->edid,
2902 timing);
2903 break;
2904 case 0x04: /* cvt, only in 1.4+ */
2905 if (!version_greater(closure->edid, 1, 3))
2906 break;
2907
2908 closure->modes += drm_cvt_modes_for_range(closure->connector,
2909 closure->edid,
2910 timing);
2911 break;
2912 case 0x01: /* just the ranges, no formula */
2913 default:
2914 break;
2915 }
13931579 2916}
69da3015 2917
13931579
AJ		 2918static int
2919add_inferred_modes(struct drm_connector *connector, struct edid *edid)
2920{
2921 struct detailed_mode_closure closure = {
d456ea2e
JL		 2922 .connector = connector,
2923 .edid = edid,
13931579 2924 };
9340d8cf 2925
13931579
AJ		 2926 if (version_greater(edid, 1, 0))
2927 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
2928 &closure);
9340d8cf 2929
13931579 2930 return closure.modes;
9340d8cf
AJ		 2931}
2932
2255be14
AJ		 2933static int
2934drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
2935{
2936 int i, j, m, modes = 0;
2937 struct drm_display_mode *mode;
f3a32d74 2938 u8 *est = ((u8 *)timing) + 6;
2255be14
AJ		 2939
2940 for (i = 0; i < 6; i++) {
891a7469 2941 for (j = 7; j >= 0; j--) {
2255be14 2942 m = (i * 8) + (7 - j);
3c581411 2943 if (m >= ARRAY_SIZE(est3_modes))
2255be14
AJ		 2944 break;
2945 if (est[i] & (1 << j)) {
1d42bbc8
DA		 2946 mode = drm_mode_find_dmt(connector->dev,
2947 est3_modes[m].w,
2948 est3_modes[m].h,
f6e252ba
AJ		 2949 est3_modes[m].r,
2950 est3_modes[m].rb);
2255be14
AJ		 2951 if (mode) {
2952 drm_mode_probed_add(connector, mode);
2953 modes++;
2954 }
2955 }
2956 }
2957 }
2958
2959 return modes;
2960}
2961
13931579
AJ		 2962static void
2963do_established_modes(struct detailed_timing *timing, void *c)
9cf00977 2964{
13931579 2965 struct detailed_mode_closure *closure = c;
9cf00977 2966
a7a131ac
VS		 2967 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_EST_TIMINGS))
2968 return;
2969
2970 closure->modes += drm_est3_modes(closure->connector, timing);
13931579 2971}
9cf00977 2972
13931579
AJ		 2973/**
2974 * add_established_modes - get est. modes from EDID and add them
db6cf833 2975 * @connector: connector to add mode(s) to
13931579
AJ		 2976 * @edid: EDID block to scan
2977 *
2978 * Each EDID block contains a bitmap of the supported "established modes" list
2979 * (defined above). Tease them out and add them to the global modes list.
2980 */
2981static int
2982add_established_modes(struct drm_connector *connector, struct edid *edid)
2983{
2984 struct drm_device *dev = connector->dev;
2985 unsigned long est_bits = edid->established_timings.t1 |
2986 (edid->established_timings.t2 << 8) |
2987 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
2988 int i, modes = 0;
2989 struct detailed_mode_closure closure = {
d456ea2e
JL		 2990 .connector = connector,
2991 .edid = edid,
13931579 2992 };
9cf00977 2993
13931579
AJ		 2994 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
2995 if (est_bits & (1<<i)) {
2996 struct drm_display_mode *newmode;
2997 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
2998 if (newmode) {
2999 drm_mode_probed_add(connector, newmode);
3000 modes++;
3001 }
3002 }
9cf00977
AJ		 3003 }
3004
13931579
AJ		 3005 if (version_greater(edid, 1, 0))
3006 drm_for_each_detailed_block((u8 *)edid,
3007 do_established_modes, &closure);
3008
3009 return modes + closure.modes;
3010}
3011
3012static void
3013do_standard_modes(struct detailed_timing *timing, void *c)
3014{
3015 struct detailed_mode_closure *closure = c;
3016 struct detailed_non_pixel *data = &timing->data.other_data;
3017 struct drm_connector *connector = closure->connector;
3018 struct edid *edid = closure->edid;
a7a131ac 3019 int i;
13931579 3020
a7a131ac
VS		 3021 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_STD_MODES))
3022 return;
9cf00977 3023
a7a131ac
VS		 3024 for (i = 0; i < 6; i++) {
3025 struct std_timing *std = &data->data.timings[i];
3026 struct drm_display_mode *newmode;
3027
3028 newmode = drm_mode_std(connector, edid, std);
3029 if (newmode) {
3030 drm_mode_probed_add(connector, newmode);
3031 closure->modes++;
9cf00977 3032 }
9cf00977 3033 }
9cf00977
AJ		 3034}
3035
f453ba04 3036/**
13931579 3037 * add_standard_modes - get std. modes from EDID and add them
db6cf833 3038 * @connector: connector to add mode(s) to
f453ba04 3039 * @edid: EDID block to scan
f453ba04 3040 *
13931579
AJ		 3041 * Standard modes can be calculated using the appropriate standard (DMT,
3042 * GTF or CVT. Grab them from @edid and add them to the list.
f453ba04 3043 */
13931579
AJ		 3044static int
3045add_standard_modes(struct drm_connector *connector, struct edid *edid)
f453ba04 3046{
9cf00977 3047 int i, modes = 0;
13931579 3048 struct detailed_mode_closure closure = {
d456ea2e
JL		 3049 .connector = connector,
3050 .edid = edid,
13931579
AJ		 3051 };
3052
3053 for (i = 0; i < EDID_STD_TIMINGS; i++) {
3054 struct drm_display_mode *newmode;
3055
3056 newmode = drm_mode_std(connector, edid,
464fdeca 3057 &edid->standard_timings[i]);
13931579
AJ		 3058 if (newmode) {
3059 drm_mode_probed_add(connector, newmode);
3060 modes++;
3061 }
3062 }
3063
3064 if (version_greater(edid, 1, 0))
3065 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
3066 &closure);
3067
3068 /* XXX should also look for standard codes in VTB blocks */
3069
3070 return modes + closure.modes;
3071}
f453ba04 3072
13931579
AJ		 3073static int drm_cvt_modes(struct drm_connector *connector,
3074 struct detailed_timing *timing)
3075{
3076 int i, j, modes = 0;
3077 struct drm_display_mode *newmode;
3078 struct drm_device *dev = connector->dev;
3079 struct cvt_timing *cvt;
3080 const int rates[] = { 60, 85, 75, 60, 50 };
3081 const u8 empty[3] = { 0, 0, 0 };
a327f6b8 3082
13931579
AJ		 3083 for (i = 0; i < 4; i++) {
3084 int uninitialized_var(width), height;
3085 cvt = &(timing->data.other_data.data.cvt[i]);
f453ba04 3086
13931579 3087 if (!memcmp(cvt->code, empty, 3))
9cf00977 3088 continue;
f453ba04 3089
13931579
AJ		 3090 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
3091 switch (cvt->code[1] & 0x0c) {
3092 case 0x00:
3093 width = height * 4 / 3;
3094 break;
3095 case 0x04:
3096 width = height * 16 / 9;
3097 break;
3098 case 0x08:
3099 width = height * 16 / 10;
3100 break;
3101 case 0x0c:
3102 width = height * 15 / 9;
3103 break;
3104 }
3105
3106 for (j = 1; j < 5; j++) {
3107 if (cvt->code[2] & (1 << j)) {
3108 newmode = drm_cvt_mode(dev, width, height,
3109 rates[j], j == 0,
3110 false, false);
3111 if (newmode) {
3112 drm_mode_probed_add(connector, newmode);
3113 modes++;
3114 }
3115 }
3116 }
f453ba04
DA		 3117 }
3118
3119 return modes;
3120}
9cf00977 3121
13931579
AJ		 3122static void
3123do_cvt_mode(struct detailed_timing *timing, void *c)
882f0219 3124{
13931579 3125 struct detailed_mode_closure *closure = c;
882f0219 3126
a7a131ac
VS		 3127 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_CVT_3BYTE))
3128 return;
3129
3130 closure->modes += drm_cvt_modes(closure->connector, timing);
13931579 3131}
882f0219 3132
13931579
AJ		 3133static int
3134add_cvt_modes(struct drm_connector *connector, struct edid *edid)
4d23f484 3135{
13931579 3136 struct detailed_mode_closure closure = {
d456ea2e
JL		 3137 .connector = connector,
3138 .edid = edid,
13931579 3139 };
882f0219 3140
13931579
AJ		 3141 if (version_greater(edid, 1, 2))
3142 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
882f0219 3143
13931579 3144 /* XXX should also look for CVT codes in VTB blocks */
882f0219 3145
13931579
AJ		 3146 return closure.modes;
3147}
3148
fa3a7340
VS		 3149static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
3150
13931579
AJ		 3151static void
3152do_detailed_mode(struct detailed_timing *timing, void *c)
3153{
3154 struct detailed_mode_closure *closure = c;
3155 struct drm_display_mode *newmode;
3156
f447dd1f
VS		 3157 if (!is_detailed_timing_descriptor((const u8 *)timing))
3158 return;
3159
3160 newmode = drm_mode_detailed(closure->connector->dev,
3161 closure->edid, timing,
3162 closure->quirks);
3163 if (!newmode)
3164 return;
13931579 3165
f447dd1f
VS		 3166 if (closure->preferred)
3167 newmode->type |= DRM_MODE_TYPE_PREFERRED;
13931579 3168
f447dd1f
VS		 3169 /*
3170 * Detailed modes are limited to 10kHz pixel clock resolution,
3171 * so fix up anything that looks like CEA/HDMI mode, but the clock
3172 * is just slightly off.
3173 */
3174 fixup_detailed_cea_mode_clock(newmode);
fa3a7340 3175
f447dd1f
VS		 3176 drm_mode_probed_add(closure->connector, newmode);
3177 closure->modes++;
3178 closure->preferred = false;
13931579 3179}
882f0219 3180
13931579
AJ		 3181/*
3182 * add_detailed_modes - Add modes from detailed timings
3183 * @connector: attached connector
3184 * @edid: EDID block to scan
3185 * @quirks: quirks to apply
3186 */
3187static int
3188add_detailed_modes(struct drm_connector *connector, struct edid *edid,
3189 u32 quirks)
3190{
3191 struct detailed_mode_closure closure = {
d456ea2e
JL		 3192 .connector = connector,
3193 .edid = edid,
c2925bde 3194 .preferred = true,
d456ea2e 3195 .quirks = quirks,
13931579
AJ		 3196 };
3197
3198 if (closure.preferred && !version_greater(edid, 1, 3))
3199 closure.preferred =
3200 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
3201
3202 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
3203
3204 return closure.modes;
882f0219 3205}
f453ba04 3206
8fe9790d 3207#define AUDIO_BLOCK 0x01
54ac76f8 3208#define VIDEO_BLOCK 0x02
f23c20c8 3209#define VENDOR_BLOCK 0x03
76adaa34 3210#define SPEAKER_BLOCK 0x04
e85959d6 3211#define HDR_STATIC_METADATA_BLOCK 0x6
87563fc0
SS		 3212#define USE_EXTENDED_TAG 0x07
3213#define EXT_VIDEO_CAPABILITY_BLOCK 0x00
832d4f2f
SS		 3214#define EXT_VIDEO_DATA_BLOCK_420 0x0E
3215#define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F
8fe9790d 3216#define EDID_BASIC_AUDIO (1 << 6)
a988bc72
LPC		 3217#define EDID_CEA_YCRCB444 (1 << 5)
3218#define EDID_CEA_YCRCB422 (1 << 4)
b1edd6a6 3219#define EDID_CEA_VCDB_QS (1 << 6)
8fe9790d 3220
d4e4a31d 3221/*
8fe9790d 3222 * Search EDID for CEA extension block.
f23c20c8 3223 */
170178fe 3224static u8 *drm_find_edid_extension(const struct edid *edid, int ext_id)
f23c20c8 3225{
8fe9790d
ZW		 3226 u8 *edid_ext = NULL;
3227 int i;
f23c20c8
ML		 3228
3229 /* No EDID or EDID extensions */
3230 if (edid == NULL || edid->extensions == 0)
8fe9790d 3231 return NULL;
f23c20c8 3232
f23c20c8 3233 /* Find CEA extension */
7466f4cc 3234 for (i = 0; i < edid->extensions; i++) {
8fe9790d 3235 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
40d9b043 3236 if (edid_ext[0] == ext_id)
f23c20c8
ML		 3237 break;
3238 }
3239
7466f4cc 3240 if (i == edid->extensions)
8fe9790d
ZW		 3241 return NULL;
3242
3243 return edid_ext;
3244}
3245
40d9b043 3246
23b03867
VS		 3247static u8 *drm_find_displayid_extension(const struct edid *edid,
3248 int *length, int *idx)
40d9b043 3249{
36881184 3250 u8 *displayid = drm_find_edid_extension(edid, DISPLAYID_EXT);
8e88c752 3251 struct displayid_hdr *base;
ea0aa608 3252 int ret;
36881184
VS		 3253
3254 if (!displayid)
3255 return NULL;
3256
5f706b4a
VS		 3257 /* EDID extensions block checksum isn't for us */
3258 *length = EDID_LENGTH - 1;
36881184
VS		 3259 *idx = 1;
3260
ea0aa608
VS		 3261 ret = validate_displayid(displayid, *length, *idx);
3262 if (ret)
3263 return NULL;
3264
8e88c752
VS		 3265 base = (struct displayid_hdr *)&displayid[*idx];
3266 *length = *idx + sizeof(*base) + base->bytes;
3267
36881184 3268 return displayid;
40d9b043
DA		 3269}
3270
e28ad544
AR		 3271static u8 *drm_find_cea_extension(const struct edid *edid)
3272{
23b03867 3273 int length, idx;
e28ad544
AR		 3274 struct displayid_block *block;
3275 u8 *cea;
3276 u8 *displayid;
3277
3278 /* Look for a top level CEA extension block */
3279 cea = drm_find_edid_extension(edid, CEA_EXT);
3280 if (cea)
3281 return cea;
3282
3283 /* CEA blocks can also be found embedded in a DisplayID block */
23b03867 3284 displayid = drm_find_displayid_extension(edid, &length, &idx);
e28ad544
AR		 3285 if (!displayid)
3286 return NULL;
3287
e28ad544
AR		 3288 idx += sizeof(struct displayid_hdr);
3289 for_each_displayid_db(displayid, block, idx, length) {
3290 if (block->tag == DATA_BLOCK_CTA) {
3291 cea = (u8 *)block;
3292 break;
3293 }
3294 }
3295
3296 return cea;
3297}
3298
e1cf35b9 3299static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic)
7befe621 3300{
9212f8ee
VS		 3301 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127);
3302 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219);
3303
8c1b2bd9
VS		 3304 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1))
3305 return &edid_cea_modes_1[vic - 1];
f7655d42
VS		 3306 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193))
3307 return &edid_cea_modes_193[vic - 193];
7befe621
VS		 3308 return NULL;
3309}
3310
3311static u8 cea_num_vics(void)
3312{
f7655d42 3313 return 193 + ARRAY_SIZE(edid_cea_modes_193);
7befe621
VS		 3314}
3315
3316static u8 cea_next_vic(u8 vic)
3317{
8c1b2bd9 3318 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1))
f7655d42
VS		 3319 vic = 193;
3320 return vic;
7befe621
VS		 3321}
3322
e6e79209
VS		 3323/*
3324 * Calculate the alternate clock for the CEA mode
3325 * (60Hz vs. 59.94Hz etc.)
3326 */
3327static unsigned int
3328cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
3329{
3330 unsigned int clock = cea_mode->clock;
3331
0425662f 3332 if (drm_mode_vrefresh(cea_mode) % 6 != 0)
e6e79209
VS		 3333 return clock;
3334
3335 /*
3336 * edid_cea_modes contains the 59.94Hz
3337 * variant for 240 and 480 line modes,
3338 * and the 60Hz variant otherwise.
3339 */
3340 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
9afd808c 3341 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
e6e79209 3342 else
9afd808c 3343 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
e6e79209
VS		 3344
3345 return clock;
3346}
3347
c45a4e46
VS		 3348static bool
3349cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
3350{
3351 /*
3352 * For certain VICs the spec allows the vertical
3353 * front porch to vary by one or two lines.
3354 *
3355 * cea_modes[] stores the variant with the shortest
3356 * vertical front porch. We can adjust the mode to
3357 * get the other variants by simply increasing the
3358 * vertical front porch length.
3359 */
7befe621
VS		 3360 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 ||
3361 cea_mode_for_vic(9)->vtotal != 262 ||
3362 cea_mode_for_vic(12)->vtotal != 262 ||
3363 cea_mode_for_vic(13)->vtotal != 262 ||
3364 cea_mode_for_vic(23)->vtotal != 312 ||
3365 cea_mode_for_vic(24)->vtotal != 312 ||
3366 cea_mode_for_vic(27)->vtotal != 312 ||
3367 cea_mode_for_vic(28)->vtotal != 312);
c45a4e46
VS		 3368
3369 if (((vic == 8 || vic == 9 ||
3370 vic == 12 || vic == 13) && mode->vtotal < 263) ||
3371 ((vic == 23 || vic == 24 ||
3372 vic == 27 || vic == 28) && mode->vtotal < 314)) {
3373 mode->vsync_start++;
3374 mode->vsync_end++;
3375 mode->vtotal++;
3376
3377 return true;
3378 }
3379
3380 return false;
3381}
3382
4c6bcf44
VS		 3383static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
3384 unsigned int clock_tolerance)
3385{
357768cc 3386 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 3387 u8 vic;
4c6bcf44
VS		 3388
3389 if (!to_match->clock)
3390 return 0;
3391
357768cc
VS		 3392 if (to_match->picture_aspect_ratio)
3393 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3394
7befe621
VS		 3395 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
3396 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic);
4c6bcf44
VS		 3397 unsigned int clock1, clock2;
3398
3399 /* Check both 60Hz and 59.94Hz */
c45a4e46
VS		 3400 clock1 = cea_mode.clock;
3401 clock2 = cea_mode_alternate_clock(&cea_mode);
4c6bcf44
VS		 3402
3403 if (abs(to_match->clock - clock1) > clock_tolerance &&
3404 abs(to_match->clock - clock2) > clock_tolerance)
3405 continue;
3406
c45a4e46 3407 do {
357768cc 3408 if (drm_mode_match(to_match, &cea_mode, match_flags))
c45a4e46
VS		 3409 return vic;
3410 } while (cea_mode_alternate_timings(vic, &cea_mode));
4c6bcf44
VS		 3411 }
3412
3413 return 0;
3414}
3415
18316c8c
TR		 3416/**
3417 * drm_match_cea_mode - look for a CEA mode matching given mode
3418 * @to_match: display mode
3419 *
db6cf833 3420 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
18316c8c 3421 * mode.
a4799037 3422 */
18316c8c 3423u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
a4799037 3424{
357768cc 3425 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 3426 u8 vic;
a4799037 3427
a90b590e
VS		 3428 if (!to_match->clock)
3429 return 0;
3430
357768cc
VS		 3431 if (to_match->picture_aspect_ratio)
3432 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3433
7befe621
VS		 3434 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
3435 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic);
a90b590e
VS		 3436 unsigned int clock1, clock2;
3437
a90b590e 3438 /* Check both 60Hz and 59.94Hz */
c45a4e46
VS		 3439 clock1 = cea_mode.clock;
3440 clock2 = cea_mode_alternate_clock(&cea_mode);
a4799037 3441
c45a4e46
VS		 3442 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
3443 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
3444 continue;
3445
3446 do {
357768cc 3447 if (drm_mode_match(to_match, &cea_mode, match_flags))
c45a4e46
VS		 3448 return vic;
3449 } while (cea_mode_alternate_timings(vic, &cea_mode));
a4799037 3450 }
c45a4e46 3451
a4799037
SM		 3452 return 0;
3453}
3454EXPORT_SYMBOL(drm_match_cea_mode);
3455
d9278b4c
JN		 3456static bool drm_valid_cea_vic(u8 vic)
3457{
7befe621 3458 return cea_mode_for_vic(vic) != NULL;
d9278b4c
JN		 3459}
3460
28c03a44 3461static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
0967e6a5 3462{
7befe621
VS		 3463 const struct drm_display_mode *mode = cea_mode_for_vic(video_code);
3464
3465 if (mode)
3466 return mode->picture_aspect_ratio;
3467
3468 return HDMI_PICTURE_ASPECT_NONE;
0967e6a5 3469}
0967e6a5 3470
d2b43473
WL		 3471static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code)
3472{
3473 return edid_4k_modes[video_code].picture_aspect_ratio;
3474}
3475
3f2f6533
LD		 3476/*
3477 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
3478 * specific block).
3f2f6533
LD		 3479 */
3480static unsigned int
3481hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
3482{
3f2f6533
LD		 3483 return cea_mode_alternate_clock(hdmi_mode);
3484}
3485
4c6bcf44
VS		 3486static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
3487 unsigned int clock_tolerance)
3488{
357768cc 3489 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 3490 u8 vic;
4c6bcf44
VS		 3491
3492 if (!to_match->clock)
3493 return 0;
3494
d2b43473
WL		 3495 if (to_match->picture_aspect_ratio)
3496 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3497
d9278b4c
JN		 3498 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3499 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4c6bcf44
VS		 3500 unsigned int clock1, clock2;
3501
3502 /* Make sure to also match alternate clocks */
3503 clock1 = hdmi_mode->clock;
3504 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3505
3506 if (abs(to_match->clock - clock1) > clock_tolerance &&
3507 abs(to_match->clock - clock2) > clock_tolerance)
3508 continue;
3509
357768cc 3510 if (drm_mode_match(to_match, hdmi_mode, match_flags))
d9278b4c 3511 return vic;
4c6bcf44
VS		 3512 }
3513
3514 return 0;
3515}
3516
3f2f6533
LD		 3517/*
3518 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
3519 * @to_match: display mode
3520 *
3521 * An HDMI mode is one defined in the HDMI vendor specific block.
3522 *
3523 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
3524 */
3525static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
3526{
357768cc 3527 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 3528 u8 vic;
3f2f6533
LD		 3529
3530 if (!to_match->clock)
3531 return 0;
3532
d2b43473
WL		 3533 if (to_match->picture_aspect_ratio)
3534 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3535
d9278b4c
JN		 3536 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3537 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3f2f6533
LD		 3538 unsigned int clock1, clock2;
3539
3540 /* Make sure to also match alternate clocks */
3541 clock1 = hdmi_mode->clock;
3542 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3543
3544 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
3545 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
357768cc 3546 drm_mode_match(to_match, hdmi_mode, match_flags))
d9278b4c 3547 return vic;
3f2f6533
LD		 3548 }
3549 return 0;
3550}
3551
d9278b4c
JN		 3552static bool drm_valid_hdmi_vic(u8 vic)
3553{
3554 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
3555}
3556
e6e79209
VS		 3557static int
3558add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
3559{
3560 struct drm_device *dev = connector->dev;
3561 struct drm_display_mode *mode, *tmp;
3562 LIST_HEAD(list);
3563 int modes = 0;
3564
3565 /* Don't add CEA modes if the CEA extension block is missing */
3566 if (!drm_find_cea_extension(edid))
3567 return 0;
3568
3569 /*
3570 * Go through all probed modes and create a new mode
3571 * with the alternate clock for certain CEA modes.
3572 */
3573 list_for_each_entry(mode, &connector->probed_modes, head) {
3f2f6533 3574 const struct drm_display_mode *cea_mode = NULL;
e6e79209 3575 struct drm_display_mode *newmode;
d9278b4c 3576 u8 vic = drm_match_cea_mode(mode);
e6e79209
VS		 3577 unsigned int clock1, clock2;
3578
d9278b4c 3579 if (drm_valid_cea_vic(vic)) {
7befe621 3580 cea_mode = cea_mode_for_vic(vic);
3f2f6533
LD		 3581 clock2 = cea_mode_alternate_clock(cea_mode);
3582 } else {
d9278b4c
JN		 3583 vic = drm_match_hdmi_mode(mode);
3584 if (drm_valid_hdmi_vic(vic)) {
3585 cea_mode = &edid_4k_modes[vic];
3f2f6533
LD		 3586 clock2 = hdmi_mode_alternate_clock(cea_mode);
3587 }
3588 }
e6e79209 3589
3f2f6533
LD		 3590 if (!cea_mode)
3591 continue;
e6e79209
VS		 3592
3593 clock1 = cea_mode->clock;
e6e79209
VS		 3594
3595 if (clock1 == clock2)
3596 continue;
3597
3598 if (mode->clock != clock1 && mode->clock != clock2)
3599 continue;
3600
3601 newmode = drm_mode_duplicate(dev, cea_mode);
3602 if (!newmode)
3603 continue;
3604
27130212
DL		 3605 /* Carry over the stereo flags */
3606 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
3607
e6e79209
VS		 3608 /*
3609 * The current mode could be either variant. Make
3610 * sure to pick the "other" clock for the new mode.
3611 */
3612 if (mode->clock != clock1)
3613 newmode->clock = clock1;
3614 else
3615 newmode->clock = clock2;
3616
3617 list_add_tail(&newmode->head, &list);
3618 }
3619
3620 list_for_each_entry_safe(mode, tmp, &list, head) {
3621 list_del(&mode->head);
3622 drm_mode_probed_add(connector, mode);
3623 modes++;
3624 }
3625
3626 return modes;
3627}
a4799037 3628
8ec6e075
SS		 3629static u8 svd_to_vic(u8 svd)
3630{
3631 /* 0-6 bit vic, 7th bit native mode indicator */
3632 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
3633 return svd & 127;
3634
3635 return svd;
3636}
3637
aff04ace
TW		 3638static struct drm_display_mode *
3639drm_display_mode_from_vic_index(struct drm_connector *connector,
3640 const u8 *video_db, u8 video_len,
3641 u8 video_index)
54ac76f8
CS		 3642{
3643 struct drm_device *dev = connector->dev;
aff04ace 3644 struct drm_display_mode *newmode;
d9278b4c 3645 u8 vic;
54ac76f8 3646
aff04ace
TW		 3647 if (video_db == NULL || video_index >= video_len)
3648 return NULL;
3649
3650 /* CEA modes are numbered 1..127 */
8ec6e075 3651 vic = svd_to_vic(video_db[video_index]);
d9278b4c 3652 if (!drm_valid_cea_vic(vic))
aff04ace
TW		 3653 return NULL;
3654
7befe621 3655 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
409bbf1e
DL		 3656 if (!newmode)
3657 return NULL;
3658
aff04ace
TW		 3659 return newmode;
3660}
3661
832d4f2f
SS		 3662/*
3663 * do_y420vdb_modes - Parse YCBCR 420 only modes
3664 * @connector: connector corresponding to the HDMI sink
3665 * @svds: start of the data block of CEA YCBCR 420 VDB
3666 * @len: length of the CEA YCBCR 420 VDB
3667 *
3668 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
3669 * which contains modes which can be supported in YCBCR 420
3670 * output format only.
3671 */
3672static int do_y420vdb_modes(struct drm_connector *connector,
3673 const u8 *svds, u8 svds_len)
3674{
3675 int modes = 0, i;
3676 struct drm_device *dev = connector->dev;
3677 struct drm_display_info *info = &connector->display_info;
3678 struct drm_hdmi_info *hdmi = &info->hdmi;
3679
3680 for (i = 0; i < svds_len; i++) {
3681 u8 vic = svd_to_vic(svds[i]);
3682 struct drm_display_mode *newmode;
3683
3684 if (!drm_valid_cea_vic(vic))
3685 continue;
3686
7befe621 3687 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
832d4f2f
SS		 3688 if (!newmode)
3689 break;
3690 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
3691 drm_mode_probed_add(connector, newmode);
3692 modes++;
3693 }
3694
3695 if (modes > 0)
3696 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3697 return modes;
3698}
3699
3700/*
3701 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap
3702 * @connector: connector corresponding to the HDMI sink
3703 * @vic: CEA vic for the video mode to be added in the map
3704 *
3705 * Makes an entry for a videomode in the YCBCR 420 bitmap
3706 */
3707static void
3708drm_add_cmdb_modes(struct drm_connector *connector, u8 svd)
3709{
3710 u8 vic = svd_to_vic(svd);
3711 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3712
3713 if (!drm_valid_cea_vic(vic))
3714 return;
3715
3716 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
3717}
3718
aff04ace
TW		 3719static int
3720do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
3721{
3722 int i, modes = 0;
832d4f2f 3723 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
aff04ace
TW		 3724
3725 for (i = 0; i < len; i++) {
3726 struct drm_display_mode *mode;
3727 mode = drm_display_mode_from_vic_index(connector, db, len, i);
3728 if (mode) {
832d4f2f
SS		 3729 /*
3730 * YCBCR420 capability block contains a bitmap which
3731 * gives the index of CEA modes from CEA VDB, which
3732 * can support YCBCR 420 sampling output also (apart
3733 * from RGB/YCBCR444 etc).
3734 * For example, if the bit 0 in bitmap is set,
3735 * first mode in VDB can support YCBCR420 output too.
3736 * Add YCBCR420 modes only if sink is HDMI 2.0 capable.
3737 */
3738 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i))
3739 drm_add_cmdb_modes(connector, db[i]);
3740
aff04ace
TW		 3741 drm_mode_probed_add(connector, mode);
3742 modes++;
54ac76f8
CS		 3743 }
3744 }
3745
3746 return modes;
3747}
3748
c858cfca
DL		 3749struct stereo_mandatory_mode {
3750 int width, height, vrefresh;
3751 unsigned int flags;
3752};
3753
3754static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
f7e121b7
DL		 3755 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3756 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
c858cfca
DL		 3757 { 1920, 1080, 50,
3758 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3759 { 1920, 1080, 60,
3760 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
f7e121b7
DL		 3761 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3762 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
3763 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3764 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
c858cfca
DL		 3765};
3766
3767static bool
3768stereo_match_mandatory(const struct drm_display_mode *mode,
3769 const struct stereo_mandatory_mode *stereo_mode)
3770{
3771 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
3772
3773 return mode->hdisplay == stereo_mode->width &&
3774 mode->vdisplay == stereo_mode->height &&
3775 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
3776 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
3777}
3778
c858cfca
DL		 3779static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
3780{
3781 struct drm_device *dev = connector->dev;
3782 const struct drm_display_mode *mode;
3783 struct list_head stereo_modes;
f7e121b7 3784 int modes = 0, i;
c858cfca
DL		 3785
3786 INIT_LIST_HEAD(&stereo_modes);
3787
3788 list_for_each_entry(mode, &connector->probed_modes, head) {
f7e121b7
DL		 3789 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
3790 const struct stereo_mandatory_mode *mandatory;
c858cfca
DL		 3791 struct drm_display_mode *new_mode;
3792
f7e121b7
DL		 3793 if (!stereo_match_mandatory(mode,
3794 &stereo_mandatory_modes[i]))
3795 continue;
c858cfca 3796
f7e121b7 3797 mandatory = &stereo_mandatory_modes[i];
c858cfca
DL		 3798 new_mode = drm_mode_duplicate(dev, mode);
3799 if (!new_mode)
3800 continue;
3801
f7e121b7 3802 new_mode->flags |= mandatory->flags;
c858cfca
DL		 3803 list_add_tail(&new_mode->head, &stereo_modes);
3804 modes++;
f7e121b7 3805 }
c858cfca
DL		 3806 }
3807
3808 list_splice_tail(&stereo_modes, &connector->probed_modes);
3809
3810 return modes;
3811}
3812
1deee8d7
DL		 3813static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
3814{
3815 struct drm_device *dev = connector->dev;
3816 struct drm_display_mode *newmode;
3817
d9278b4c 3818 if (!drm_valid_hdmi_vic(vic)) {
1deee8d7
DL		 3819 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
3820 return 0;
3821 }
3822
3823 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
3824 if (!newmode)
3825 return 0;
3826
3827 drm_mode_probed_add(connector, newmode);
3828
3829 return 1;
3830}
3831
fbf46025
TW		 3832static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
3833 const u8 *video_db, u8 video_len, u8 video_index)
3834{
fbf46025
TW		 3835 struct drm_display_mode *newmode;
3836 int modes = 0;
fbf46025
TW		 3837
3838 if (structure & (1 << 0)) {
aff04ace
TW		 3839 newmode = drm_display_mode_from_vic_index(connector, video_db,
3840 video_len,
3841 video_index);
fbf46025
TW		 3842 if (newmode) {
3843 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
3844 drm_mode_probed_add(connector, newmode);
3845 modes++;
3846 }
3847 }
3848 if (structure & (1 << 6)) {
aff04ace
TW		 3849 newmode = drm_display_mode_from_vic_index(connector, video_db,
3850 video_len,
3851 video_index);
fbf46025
TW		 3852 if (newmode) {
3853 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3854 drm_mode_probed_add(connector, newmode);
3855 modes++;
3856 }
3857 }
3858 if (structure & (1 << 8)) {
aff04ace
TW		 3859 newmode = drm_display_mode_from_vic_index(connector, video_db,
3860 video_len,
3861 video_index);
fbf46025 3862 if (newmode) {
89570eeb 3863 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
fbf46025
TW		 3864 drm_mode_probed_add(connector, newmode);
3865 modes++;
3866 }
3867 }
3868
3869 return modes;
3870}
3871
7ebe1963
LD		 3872/*
3873 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
3874 * @connector: connector corresponding to the HDMI sink
3875 * @db: start of the CEA vendor specific block
3876 * @len: length of the CEA block payload, ie. one can access up to db[len]
3877 *
c858cfca
DL		 3878 * Parses the HDMI VSDB looking for modes to add to @connector. This function
3879 * also adds the stereo 3d modes when applicable.
7ebe1963
LD		 3880 */
3881static int
fbf46025
TW		 3882do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
3883 const u8 *video_db, u8 video_len)
7ebe1963 3884{
f1781e9b 3885 struct drm_display_info *info = &connector->display_info;
0e5083aa 3886 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
fbf46025
TW		 3887 u8 vic_len, hdmi_3d_len = 0;
3888 u16 mask;
3889 u16 structure_all;
7ebe1963
LD		 3890
3891 if (len < 8)
3892 goto out;
3893
3894 /* no HDMI_Video_Present */
3895 if (!(db[8] & (1 << 5)))
3896 goto out;
3897
3898 /* Latency_Fields_Present */
3899 if (db[8] & (1 << 7))
3900 offset += 2;
3901
3902 /* I_Latency_Fields_Present */
3903 if (db[8] & (1 << 6))
3904 offset += 2;
3905
3906 /* the declared length is not long enough for the 2 first bytes
3907 * of additional video format capabilities */
c858cfca 3908 if (len < (8 + offset + 2))
7ebe1963
LD		 3909 goto out;
3910
c858cfca
DL		 3911 /* 3D_Present */
3912 offset++;
fbf46025 3913 if (db[8 + offset] & (1 << 7)) {
c858cfca
DL		 3914 modes += add_hdmi_mandatory_stereo_modes(connector);
3915
fbf46025
TW		 3916 /* 3D_Multi_present */
3917 multi_present = (db[8 + offset] & 0x60) >> 5;
3918 }
3919
c858cfca 3920 offset++;
7ebe1963 3921 vic_len = db[8 + offset] >> 5;
fbf46025 3922 hdmi_3d_len = db[8 + offset] & 0x1f;
7ebe1963
LD		 3923
3924 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
7ebe1963
LD		 3925 u8 vic;
3926
3927 vic = db[9 + offset + i];
1deee8d7 3928 modes += add_hdmi_mode(connector, vic);
7ebe1963 3929 }
fbf46025
TW		 3930 offset += 1 + vic_len;
3931
0e5083aa
TW		 3932 if (multi_present == 1)
3933 multi_len = 2;
3934 else if (multi_present == 2)
3935 multi_len = 4;
3936 else
3937 multi_len = 0;
fbf46025 3938
0e5083aa 3939 if (len < (8 + offset + hdmi_3d_len - 1))
fbf46025
TW		 3940 goto out;
3941
0e5083aa 3942 if (hdmi_3d_len < multi_len)
fbf46025
TW		 3943 goto out;
3944
0e5083aa
TW		 3945 if (multi_present == 1 || multi_present == 2) {
3946 /* 3D_Structure_ALL */
3947 structure_all = (db[8 + offset] << 8) | db[9 + offset];
fbf46025 3948
0e5083aa
TW		 3949 /* check if 3D_MASK is present */
3950 if (multi_present == 2)
3951 mask = (db[10 + offset] << 8) | db[11 + offset];
3952 else
3953 mask = 0xffff;
3954
3955 for (i = 0; i < 16; i++) {
3956 if (mask & (1 << i))
3957 modes += add_3d_struct_modes(connector,
3958 structure_all,
3959 video_db,
3960 video_len, i);
3961 }
3962 }
3963
3964 offset += multi_len;
3965
3966 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
3967 int vic_index;
3968 struct drm_display_mode *newmode = NULL;
3969 unsigned int newflag = 0;
3970 bool detail_present;
3971
3972 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
3973
3974 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
3975 break;
3976
3977 /* 2D_VIC_order_X */
3978 vic_index = db[8 + offset + i] >> 4;
3979
3980 /* 3D_Structure_X */
3981 switch (db[8 + offset + i] & 0x0f) {
3982 case 0:
3983 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
3984 break;
3985 case 6:
3986 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3987 break;
3988 case 8:
3989 /* 3D_Detail_X */
3990 if ((db[9 + offset + i] >> 4) == 1)
3991 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3992 break;
3993 }
3994
3995 if (newflag != 0) {
3996 newmode = drm_display_mode_from_vic_index(connector,
3997 video_db,
3998 video_len,
3999 vic_index);
4000
4001 if (newmode) {
4002 newmode->flags |= newflag;
4003 drm_mode_probed_add(connector, newmode);
4004 modes++;
4005 }
4006 }
4007
4008 if (detail_present)
4009 i++;
fbf46025 4010 }
7ebe1963
LD		 4011
4012out:
f1781e9b
VS		 4013 if (modes > 0)
4014 info->has_hdmi_infoframe = true;
7ebe1963
LD		 4015 return modes;
4016}
4017
9e50b9d5
VS		 4018static int
4019cea_db_payload_len(const u8 *db)
4020{
4021 return db[0] & 0x1f;
4022}
4023
87563fc0
SS		 4024static int
4025cea_db_extended_tag(const u8 *db)
4026{
4027 return db[1];
4028}
4029
9e50b9d5
VS		 4030static int
4031cea_db_tag(const u8 *db)
4032{
4033 return db[0] >> 5;
4034}
4035
4036static int
4037cea_revision(const u8 *cea)
4038{
5036c0d0
VS		 4039 /*
4040 * FIXME is this correct for the DispID variant?
4041 * The DispID spec doesn't really specify whether
4042 * this is the revision of the CEA extension or
4043 * the DispID CEA data block. And the only value
4044 * given as an example is 0.
4045 */
9e50b9d5
VS		 4046 return cea[1];
4047}
4048
4049static int
4050cea_db_offsets(const u8 *cea, int *start, int *end)
4051{
e28ad544
AR		 4052 /* DisplayID CTA extension blocks and top-level CEA EDID
4053 * block header definitions differ in the following bytes:
4054 * 1) Byte 2 of the header specifies length differently,
4055 * 2) Byte 3 is only present in the CEA top level block.
4056 *
4057 * The different definitions for byte 2 follow.
4058 *
4059 * DisplayID CTA extension block defines byte 2 as:
4060 * Number of payload bytes
4061 *
4062 * CEA EDID block defines byte 2 as:
4063 * Byte number (decimal) within this block where the 18-byte
4064 * DTDs begin. If no non-DTD data is present in this extension
4065 * block, the value should be set to 04h (the byte after next).
4066 * If set to 00h, there are no DTDs present in this block and
4067 * no non-DTD data.
4068 */
4069 if (cea[0] == DATA_BLOCK_CTA) {
6e8a942b
VS		 4070 /*
4071 * for_each_displayid_db() has already verified
4072 * that these stay within expected bounds.
4073 */
e28ad544
AR		 4074 *start = 3;
4075 *end = *start + cea[2];
4076 } else if (cea[0] == CEA_EXT) {
4077 /* Data block offset in CEA extension block */
4078 *start = 4;
4079 *end = cea[2];
4080 if (*end == 0)
4081 *end = 127;
4082 if (*end < 4 || *end > 127)
4083 return -ERANGE;
4084 } else {
c7581a41 4085 return -EOPNOTSUPP;
e28ad544
AR		 4086 }
4087
9e50b9d5
VS		 4088 return 0;
4089}
4090
7ebe1963
LD		 4091static bool cea_db_is_hdmi_vsdb(const u8 *db)
4092{
4093 int hdmi_id;
4094
4095 if (cea_db_tag(db) != VENDOR_BLOCK)
4096 return false;
4097
4098 if (cea_db_payload_len(db) < 5)
4099 return false;
4100
4101 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
4102
6cb3b7f1 4103 return hdmi_id == HDMI_IEEE_OUI;
7ebe1963
LD		 4104}
4105
50dd1bd1
TR		 4106static bool cea_db_is_hdmi_forum_vsdb(const u8 *db)
4107{
4108 unsigned int oui;
4109
4110 if (cea_db_tag(db) != VENDOR_BLOCK)
4111 return false;
4112
4113 if (cea_db_payload_len(db) < 7)
4114 return false;
4115
4116 oui = db[3] << 16 | db[2] << 8 | db[1];
4117
4118 return oui == HDMI_FORUM_IEEE_OUI;
4119}
4120
1581b2df
VS		 4121static bool cea_db_is_vcdb(const u8 *db)
4122{
4123 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4124 return false;
4125
4126 if (cea_db_payload_len(db) != 2)
4127 return false;
4128
4129 if (cea_db_extended_tag(db) != EXT_VIDEO_CAPABILITY_BLOCK)
4130 return false;
4131
4132 return true;
4133}
4134
832d4f2f
SS		 4135static bool cea_db_is_y420cmdb(const u8 *db)
4136{
4137 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4138 return false;
4139
4140 if (!cea_db_payload_len(db))
4141 return false;
4142
4143 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB)
4144 return false;
4145
4146 return true;
4147}
4148
4149static bool cea_db_is_y420vdb(const u8 *db)
4150{
4151 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4152 return false;
4153
4154 if (!cea_db_payload_len(db))
4155 return false;
4156
4157 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420)
4158 return false;
4159
4160 return true;
4161}
4162
9e50b9d5
VS		 4163#define for_each_cea_db(cea, i, start, end) \
4164 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
4165
832d4f2f
SS		 4166static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector,
4167 const u8 *db)
4168{
4169 struct drm_display_info *info = &connector->display_info;
4170 struct drm_hdmi_info *hdmi = &info->hdmi;
4171 u8 map_len = cea_db_payload_len(db) - 1;
4172 u8 count;
4173 u64 map = 0;
4174
4175 if (map_len == 0) {
4176 /* All CEA modes support ycbcr420 sampling also.*/
4177 hdmi->y420_cmdb_map = U64_MAX;
4178 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
4179 return;
4180 }
4181
4182 /*
4183 * This map indicates which of the existing CEA block modes
4184 * from VDB can support YCBCR420 output too. So if bit=0 is
4185 * set, first mode from VDB can support YCBCR420 output too.
4186 * We will parse and keep this map, before parsing VDB itself
4187 * to avoid going through the same block again and again.
4188 *
4189 * Spec is not clear about max possible size of this block.
4190 * Clamping max bitmap block size at 8 bytes. Every byte can
4191 * address 8 CEA modes, in this way this map can address
4192 * 8*8 = first 64 SVDs.
4193 */
4194 if (WARN_ON_ONCE(map_len > 8))
4195 map_len = 8;
4196
4197 for (count = 0; count < map_len; count++)
4198 map |= (u64)db[2 + count] << (8 * count);
4199
4200 if (map)
4201 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
4202
4203 hdmi->y420_cmdb_map = map;
4204}
4205
54ac76f8
CS		 4206static int
4207add_cea_modes(struct drm_connector *connector, struct edid *edid)
4208{
13ac3f55 4209 const u8 *cea = drm_find_cea_extension(edid);
fbf46025
TW		 4210 const u8 *db, *hdmi = NULL, *video = NULL;
4211 u8 dbl, hdmi_len, video_len = 0;
54ac76f8
CS		 4212 int modes = 0;
4213
9e50b9d5
VS		 4214 if (cea && cea_revision(cea) >= 3) {
4215 int i, start, end;
4216
4217 if (cea_db_offsets(cea, &start, &end))
4218 return 0;
4219
4220 for_each_cea_db(cea, i, start, end) {
4221 db = &cea[i];
4222 dbl = cea_db_payload_len(db);
4223
fbf46025
TW		 4224 if (cea_db_tag(db) == VIDEO_BLOCK) {
4225 video = db + 1;
4226 video_len = dbl;
4227 modes += do_cea_modes(connector, video, dbl);
832d4f2f 4228 } else if (cea_db_is_hdmi_vsdb(db)) {
c858cfca
DL		 4229 hdmi = db;
4230 hdmi_len = dbl;
832d4f2f
SS		 4231 } else if (cea_db_is_y420vdb(db)) {
4232 const u8 *vdb420 = &db[2];
4233
4234 /* Add 4:2:0(only) modes present in EDID */
4235 modes += do_y420vdb_modes(connector,
4236 vdb420,
4237 dbl - 1);
c858cfca 4238 }
54ac76f8
CS		 4239 }
4240 }
4241
c858cfca
DL		 4242 /*
4243 * We parse the HDMI VSDB after having added the cea modes as we will
4244 * be patching their flags when the sink supports stereo 3D.
4245 */
4246 if (hdmi)
fbf46025
TW		 4247 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
4248 video_len);
c858cfca 4249
54ac76f8
CS		 4250 return modes;
4251}
4252
fa3a7340
VS		 4253static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
4254{
4255 const struct drm_display_mode *cea_mode;
4256 int clock1, clock2, clock;
d9278b4c 4257 u8 vic;
fa3a7340
VS		 4258 const char *type;
4259
4c6bcf44
VS		 4260 /*
4261 * allow 5kHz clock difference either way to account for
4262 * the 10kHz clock resolution limit of detailed timings.
4263 */
d9278b4c
JN		 4264 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
4265 if (drm_valid_cea_vic(vic)) {
fa3a7340 4266 type = "CEA";
7befe621 4267 cea_mode = cea_mode_for_vic(vic);
fa3a7340
VS		 4268 clock1 = cea_mode->clock;
4269 clock2 = cea_mode_alternate_clock(cea_mode);
4270 } else {
d9278b4c
JN		 4271 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
4272 if (drm_valid_hdmi_vic(vic)) {
fa3a7340 4273 type = "HDMI";
d9278b4c 4274 cea_mode = &edid_4k_modes[vic];
fa3a7340
VS		 4275 clock1 = cea_mode->clock;
4276 clock2 = hdmi_mode_alternate_clock(cea_mode);
4277 } else {
4278 return;
4279 }
4280 }
4281
4282 /* pick whichever is closest */
4283 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
4284 clock = clock1;
4285 else
4286 clock = clock2;
4287
4288 if (mode->clock == clock)
4289 return;
4290
4291 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
d9278b4c 4292 type, vic, mode->clock, clock);
fa3a7340
VS		 4293 mode->clock = clock;
4294}
4295
e85959d6
US		 4296static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db)
4297{
4298 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4299 return false;
4300
4301 if (db[1] != HDR_STATIC_METADATA_BLOCK)
4302 return false;
4303
4304 if (cea_db_payload_len(db) < 3)
4305 return false;
4306
4307 return true;
4308}
4309
4310static uint8_t eotf_supported(const u8 *edid_ext)
4311{
4312 return edid_ext[2] &
4313 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
4314 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
b5e3eed1
VS		 4315 BIT(HDMI_EOTF_SMPTE_ST2084) |
4316 BIT(HDMI_EOTF_BT_2100_HLG));
e85959d6
US		 4317}
4318
4319static uint8_t hdr_metadata_type(const u8 *edid_ext)
4320{
4321 return edid_ext[3] &
4322 BIT(HDMI_STATIC_METADATA_TYPE1);
4323}
4324
4325static void
4326drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
4327{
4328 u16 len;
4329
4330 len = cea_db_payload_len(db);
4331
4332 connector->hdr_sink_metadata.hdmi_type1.eotf =
4333 eotf_supported(db);
4334 connector->hdr_sink_metadata.hdmi_type1.metadata_type =
4335 hdr_metadata_type(db);
4336
4337 if (len >= 4)
4338 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4];
4339 if (len >= 5)
4340 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5];
4341 if (len >= 6)
4342 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6];
4343}
4344
76adaa34 4345static void
23ebf8b9 4346drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
76adaa34 4347{
8504072a 4348 u8 len = cea_db_payload_len(db);
76adaa34 4349
f7da7785
JN		 4350 if (len >= 6 && (db[6] & (1 << 7)))
4351 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
8504072a
VS		 4352 if (len >= 8) {
4353 connector->latency_present[0] = db[8] >> 7;
4354 connector->latency_present[1] = (db[8] >> 6) & 1;
4355 }
4356 if (len >= 9)
4357 connector->video_latency[0] = db[9];
4358 if (len >= 10)
4359 connector->audio_latency[0] = db[10];
4360 if (len >= 11)
4361 connector->video_latency[1] = db[11];
4362 if (len >= 12)
4363 connector->audio_latency[1] = db[12];
76adaa34 4364
23ebf8b9
VS		 4365 DRM_DEBUG_KMS("HDMI: latency present %d %d, "
4366 "video latency %d %d, "
4367 "audio latency %d %d\n",
4368 connector->latency_present[0],
4369 connector->latency_present[1],
4370 connector->video_latency[0],
4371 connector->video_latency[1],
4372 connector->audio_latency[0],
4373 connector->audio_latency[1]);
76adaa34
WF		 4374}
4375
4376static void
4377monitor_name(struct detailed_timing *t, void *data)
4378{
a7a131ac
VS		 4379 if (!is_display_descriptor((const u8 *)t, EDID_DETAIL_MONITOR_NAME))
4380 return;
4381
4382 *(u8 **)data = t->data.other_data.data.str.str;
14f77fdd
VS		 4383}
4384
59f7c0fa
JB		 4385static int get_monitor_name(struct edid *edid, char name[13])
4386{
4387 char *edid_name = NULL;
4388 int mnl;
4389
4390 if (!edid || !name)
4391 return 0;
4392
4393 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name);
4394 for (mnl = 0; edid_name && mnl < 13; mnl++) {
4395 if (edid_name[mnl] == 0x0a)
4396 break;
4397
4398 name[mnl] = edid_name[mnl];
4399 }
4400
4401 return mnl;
4402}
4403
4404/**
4405 * drm_edid_get_monitor_name - fetch the monitor name from the edid
4406 * @edid: monitor EDID information
4407 * @name: pointer to a character array to hold the name of the monitor
4408 * @bufsize: The size of the name buffer (should be at least 14 chars.)
4409 *
4410 */
4411void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize)
4412{
4413 int name_length;
4414 char buf[13];
4d23f484 4415
59f7c0fa
JB		 4416 if (bufsize <= 0)
4417 return;
4418
4419 name_length = min(get_monitor_name(edid, buf), bufsize - 1);
4420 memcpy(name, buf, name_length);
4421 name[name_length] = '\0';
4422}
4423EXPORT_SYMBOL(drm_edid_get_monitor_name);
4424
42750d39
JN		 4425static void clear_eld(struct drm_connector *connector)
4426{
4427 memset(connector->eld, 0, sizeof(connector->eld));
4428
4429 connector->latency_present[0] = false;
4430 connector->latency_present[1] = false;
4431 connector->video_latency[0] = 0;
4432 connector->audio_latency[0] = 0;
4433 connector->video_latency[1] = 0;
4434 connector->audio_latency[1] = 0;
4435}
4436
79436a1c 4437/*
76adaa34
WF		 4438 * drm_edid_to_eld - build ELD from EDID
4439 * @connector: connector corresponding to the HDMI/DP sink
4440 * @edid: EDID to parse
4441 *
db6cf833 4442 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
1d1c3665 4443 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
76adaa34 4444 */
79436a1c 4445static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
76adaa34
WF		 4446{
4447 uint8_t *eld = connector->eld;
4448 u8 *cea;
76adaa34 4449 u8 *db;
7c018782 4450 int total_sad_count = 0;
76adaa34
WF		 4451 int mnl;
4452 int dbl;
4453
42750d39 4454 clear_eld(connector);
85c91580 4455
e9bd0b84
JN		 4456 if (!edid)
4457 return;
4458
76adaa34
WF		 4459 cea = drm_find_cea_extension(edid);
4460 if (!cea) {
4461 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
4462 return;
4463 }
4464
f7da7785
JN		 4465 mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
4466 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]);
59f7c0fa 4467
f7da7785
JN		 4468 eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT;
4469 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
76adaa34 4470
f7da7785 4471 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
76adaa34 4472
f7da7785
JN		 4473 eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0];
4474 eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1];
4475 eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0];
4476 eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1];
76adaa34 4477
9e50b9d5
VS		 4478 if (cea_revision(cea) >= 3) {
4479 int i, start, end;
deec222e 4480 int sad_count;
9e50b9d5
VS		 4481
4482 if (cea_db_offsets(cea, &start, &end)) {
4483 start = 0;
4484 end = 0;
4485 }
4486
4487 for_each_cea_db(cea, i, start, end) {
4488 db = &cea[i];
4489 dbl = cea_db_payload_len(db);
4490
4491 switch (cea_db_tag(db)) {
a0ab734d
CS		 4492 case AUDIO_BLOCK:
4493 /* Audio Data Block, contains SADs */
7c018782
VS		 4494 sad_count = min(dbl / 3, 15 - total_sad_count);
4495 if (sad_count >= 1)
f7da7785 4496 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
7c018782
VS		 4497 &db[1], sad_count * 3);
4498 total_sad_count += sad_count;
a0ab734d
CS		 4499 break;
4500 case SPEAKER_BLOCK:
9e50b9d5
VS		 4501 /* Speaker Allocation Data Block */
4502 if (dbl >= 1)
f7da7785 4503 eld[DRM_ELD_SPEAKER] = db[1];
a0ab734d
CS		 4504 break;
4505 case VENDOR_BLOCK:
4506 /* HDMI Vendor-Specific Data Block */
14f77fdd 4507 if (cea_db_is_hdmi_vsdb(db))
23ebf8b9 4508 drm_parse_hdmi_vsdb_audio(connector, db);
a0ab734d
CS		 4509 break;
4510 default:
4511 break;
4512 }
76adaa34 4513 }
9e50b9d5 4514 }
f7da7785 4515 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
76adaa34 4516
1d1c3665
JN		 4517 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
4518 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4519 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
4520 else
4521 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
76adaa34 4522
938fd8aa
JN		 4523 eld[DRM_ELD_BASELINE_ELD_LEN] =
4524 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
4525
4526 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
7c018782 4527 drm_eld_size(eld), total_sad_count);
76adaa34 4528}
76adaa34 4529
fe214163
RM		 4530/**
4531 * drm_edid_to_sad - extracts SADs from EDID
4532 * @edid: EDID to parse
4533 * @sads: pointer that will be set to the extracted SADs
4534 *
4535 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
fe214163 4536 *
db6cf833
TR		 4537 * Note: The returned pointer needs to be freed using kfree().
4538 *
4539 * Return: The number of found SADs or negative number on error.
fe214163
RM		 4540 */
4541int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
4542{
4543 int count = 0;
4544 int i, start, end, dbl;
4545 u8 *cea;
4546
4547 cea = drm_find_cea_extension(edid);
4548 if (!cea) {
4549 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
42908007 4550 return 0;
fe214163
RM		 4551 }
4552
4553 if (cea_revision(cea) < 3) {
4554 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
42908007 4555 return 0;
fe214163
RM		 4556 }
4557
4558 if (cea_db_offsets(cea, &start, &end)) {
4559 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4560 return -EPROTO;
4561 }
4562
4563 for_each_cea_db(cea, i, start, end) {
4564 u8 *db = &cea[i];
4565
4566 if (cea_db_tag(db) == AUDIO_BLOCK) {
4567 int j;
4568 dbl = cea_db_payload_len(db);
4569
4570 count = dbl / 3; /* SAD is 3B */
4571 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
4572 if (!*sads)
4573 return -ENOMEM;
4574 for (j = 0; j < count; j++) {
4575 u8 *sad = &db[1 + j * 3];
4576
4577 (*sads)[j].format = (sad[0] & 0x78) >> 3;
4578 (*sads)[j].channels = sad[0] & 0x7;
4579 (*sads)[j].freq = sad[1] & 0x7F;
4580 (*sads)[j].byte2 = sad[2];
4581 }
4582 break;
4583 }
4584 }
4585
4586 return count;
4587}
4588EXPORT_SYMBOL(drm_edid_to_sad);
4589
d105f476
AD		 4590/**
4591 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
4592 * @edid: EDID to parse
4593 * @sadb: pointer to the speaker block
4594 *
4595 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
d105f476 4596 *
db6cf833
TR		 4597 * Note: The returned pointer needs to be freed using kfree().
4598 *
4599 * Return: The number of found Speaker Allocation Blocks or negative number on
4600 * error.
d105f476
AD		 4601 */
4602int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
4603{
4604 int count = 0;
4605 int i, start, end, dbl;
4606 const u8 *cea;
4607
4608 cea = drm_find_cea_extension(edid);
4609 if (!cea) {
4610 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
42908007 4611 return 0;
d105f476
AD		 4612 }
4613
4614 if (cea_revision(cea) < 3) {
4615 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
42908007 4616 return 0;
d105f476
AD		 4617 }
4618
4619 if (cea_db_offsets(cea, &start, &end)) {
4620 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4621 return -EPROTO;
4622 }
4623
4624 for_each_cea_db(cea, i, start, end) {
4625 const u8 *db = &cea[i];
4626
4627 if (cea_db_tag(db) == SPEAKER_BLOCK) {
4628 dbl = cea_db_payload_len(db);
4629
4630 /* Speaker Allocation Data Block */
4631 if (dbl == 3) {
89086bca 4632 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
618e3776
AD		 4633 if (!*sadb)
4634 return -ENOMEM;
d105f476
AD		 4635 count = dbl;
4636 break;
4637 }
4638 }
4639 }
4640
4641 return count;
4642}
4643EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
4644
76adaa34 4645/**
db6cf833 4646 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
76adaa34
WF		 4647 * @connector: connector associated with the HDMI/DP sink
4648 * @mode: the display mode
db6cf833
TR		 4649 *
4650 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
4651 * the sink doesn't support audio or video.
76adaa34
WF		 4652 */
4653int drm_av_sync_delay(struct drm_connector *connector,
3a818d35 4654 const struct drm_display_mode *mode)
76adaa34
WF		 4655{
4656 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
4657 int a, v;
4658
4659 if (!connector->latency_present[0])
4660 return 0;
4661 if (!connector->latency_present[1])
4662 i = 0;
4663
4664 a = connector->audio_latency[i];
4665 v = connector->video_latency[i];
4666
4667 /*
4668 * HDMI/DP sink doesn't support audio or video?
4669 */
4670 if (a == 255 || v == 255)
4671 return 0;
4672
4673 /*
4674 * Convert raw EDID values to millisecond.
4675 * Treat unknown latency as 0ms.
4676 */
4677 if (a)
4678 a = min(2 * (a - 1), 500);
4679 if (v)
4680 v = min(2 * (v - 1), 500);
4681
4682 return max(v - a, 0);
4683}
4684EXPORT_SYMBOL(drm_av_sync_delay);
4685
8fe9790d 4686/**
db6cf833 4687 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
8fe9790d
ZW		 4688 * @edid: monitor EDID information
4689 *
4690 * Parse the CEA extension according to CEA-861-B.
db6cf833 4691 *
a92d083d
LP		 4692 * Drivers that have added the modes parsed from EDID to drm_display_info
4693 * should use &drm_display_info.is_hdmi instead of calling this function.
4694 *
db6cf833 4695 * Return: True if the monitor is HDMI, false if not or unknown.
8fe9790d
ZW		 4696 */
4697bool drm_detect_hdmi_monitor(struct edid *edid)
4698{
4699 u8 *edid_ext;
14f77fdd 4700 int i;
8fe9790d 4701 int start_offset, end_offset;
8fe9790d
ZW		 4702
4703 edid_ext = drm_find_cea_extension(edid);
4704 if (!edid_ext)
14f77fdd 4705 return false;
f23c20c8 4706
9e50b9d5 4707 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
14f77fdd 4708 return false;
f23c20c8
ML		 4709
4710 /*
4711 * Because HDMI identifier is in Vendor Specific Block,
4712 * search it from all data blocks of CEA extension.
4713 */
9e50b9d5 4714 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
14f77fdd
VS		 4715 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
4716 return true;
f23c20c8
ML		 4717 }
4718
14f77fdd 4719 return false;
f23c20c8
ML		 4720}
4721EXPORT_SYMBOL(drm_detect_hdmi_monitor);
4722
8fe9790d
ZW		 4723/**
4724 * drm_detect_monitor_audio - check monitor audio capability
fc66811c 4725 * @edid: EDID block to scan
8fe9790d
ZW		 4726 *
4727 * Monitor should have CEA extension block.
4728 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
4729 * audio' only. If there is any audio extension block and supported
4730 * audio format, assume at least 'basic audio' support, even if 'basic
4731 * audio' is not defined in EDID.
4732 *
db6cf833 4733 * Return: True if the monitor supports audio, false otherwise.
8fe9790d
ZW		 4734 */
4735bool drm_detect_monitor_audio(struct edid *edid)
4736{
4737 u8 *edid_ext;
4738 int i, j;
4739 bool has_audio = false;
4740 int start_offset, end_offset;
4741
4742 edid_ext = drm_find_cea_extension(edid);
4743 if (!edid_ext)
4744 goto end;
4745
4746 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
4747
4748 if (has_audio) {
4749 DRM_DEBUG_KMS("Monitor has basic audio support\n");
4750 goto end;
4751 }
4752
9e50b9d5
VS		 4753 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4754 goto end;
8fe9790d 4755
9e50b9d5
VS		 4756 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4757 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
8fe9790d 4758 has_audio = true;
9e50b9d5 4759 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
8fe9790d
ZW		 4760 DRM_DEBUG_KMS("CEA audio format %d\n",
4761 (edid_ext[i + j] >> 3) & 0xf);
4762 goto end;
4763 }
4764 }
4765end:
4766 return has_audio;
4767}
4768EXPORT_SYMBOL(drm_detect_monitor_audio);
4769
b1edd6a6 4770
c8127cf0
VS		 4771/**
4772 * drm_default_rgb_quant_range - default RGB quantization range
4773 * @mode: display mode
4774 *
4775 * Determine the default RGB quantization range for the mode,
4776 * as specified in CEA-861.
4777 *
4778 * Return: The default RGB quantization range for the mode
4779 */
4780enum hdmi_quantization_range
4781drm_default_rgb_quant_range(const struct drm_display_mode *mode)
4782{
4783 /* All CEA modes other than VIC 1 use limited quantization range. */
4784 return drm_match_cea_mode(mode) > 1 ?
4785 HDMI_QUANTIZATION_RANGE_LIMITED :
4786 HDMI_QUANTIZATION_RANGE_FULL;
4787}
4788EXPORT_SYMBOL(drm_default_rgb_quant_range);
4789
1581b2df
VS		 4790static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
4791{
4792 struct drm_display_info *info = &connector->display_info;
4793
4794 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]);
4795
4796 if (db[2] & EDID_CEA_VCDB_QS)
4797 info->rgb_quant_range_selectable = true;
4798}
4799
e6a9a2c3
SS		 4800static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
4801 const u8 *db)
4802{
4803 u8 dc_mask;
4804 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4805
4806 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
9068e02f 4807 hdmi->y420_dc_modes = dc_mask;
e6a9a2c3
SS		 4808}
4809
afa1c763
SS		 4810static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector,
4811 const u8 *hf_vsdb)
4812{
62c58af3
SS		 4813 struct drm_display_info *display = &connector->display_info;
4814 struct drm_hdmi_info *hdmi = &display->hdmi;
afa1c763 4815
f1781e9b
VS		 4816 display->has_hdmi_infoframe = true;
4817
afa1c763
SS		 4818 if (hf_vsdb[6] & 0x80) {
4819 hdmi->scdc.supported = true;
4820 if (hf_vsdb[6] & 0x40)
4821 hdmi->scdc.read_request = true;
4822 }
62c58af3
SS		 4823
4824 /*
4825 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
4826 * And as per the spec, three factors confirm this:
4827 * * Availability of a HF-VSDB block in EDID (check)
4828 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
4829 * * SCDC support available (let's check)
4830 * Lets check it out.
4831 */
4832
4833 if (hf_vsdb[5]) {
4834 /* max clock is 5000 KHz times block value */
4835 u32 max_tmds_clock = hf_vsdb[5] * 5000;
4836 struct drm_scdc *scdc = &hdmi->scdc;
4837
4838 if (max_tmds_clock > 340000) {
4839 display->max_tmds_clock = max_tmds_clock;
4840 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
4841 display->max_tmds_clock);
4842 }
4843
4844 if (scdc->supported) {
4845 scdc->scrambling.supported = true;
4846
dbe2d2bf 4847 /* Few sinks support scrambling for clocks < 340M */
62c58af3
SS		 4848 if ((hf_vsdb[6] & 0x8))
4849 scdc->scrambling.low_rates = true;
4850 }
4851 }
e6a9a2c3
SS		 4852
4853 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb);
afa1c763
SS		 4854}
4855
1cea146a
VS		 4856static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
4857 const u8 *hdmi)
d0c94692 4858{
1826750f 4859 struct drm_display_info *info = &connector->display_info;
d0c94692
MK		 4860 unsigned int dc_bpc = 0;
4861
1cea146a
VS		 4862 /* HDMI supports at least 8 bpc */
4863 info->bpc = 8;
d0c94692 4864
1cea146a
VS		 4865 if (cea_db_payload_len(hdmi) < 6)
4866 return;
4867
4868 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
4869 dc_bpc = 10;
4870 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
4871 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
4872 connector->name);
4873 }
4874
4875 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
4876 dc_bpc = 12;
4877 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
4878 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
4879 connector->name);
4880 }
4881
4882 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
4883 dc_bpc = 16;
4884 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
4885 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
4886 connector->name);
4887 }
4888
4889 if (dc_bpc == 0) {
4890 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
4891 connector->name);
4892 return;
4893 }
4894
4895 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
4896 connector->name, dc_bpc);
4897 info->bpc = dc_bpc;
d0c94692
MK		 4898
4899 /*
1cea146a
VS		 4900 * Deep color support mandates RGB444 support for all video
4901 * modes and forbids YCRCB422 support for all video modes per
4902 * HDMI 1.3 spec.
d0c94692 4903 */
1cea146a 4904 info->color_formats = DRM_COLOR_FORMAT_RGB444;
d0c94692 4905
1cea146a
VS		 4906 /* YCRCB444 is optional according to spec. */
4907 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
4908 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4909 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
4910 connector->name);
4911 }
d0c94692 4912
1cea146a
VS		 4913 /*
4914 * Spec says that if any deep color mode is supported at all,
4915 * then deep color 36 bit must be supported.
4916 */
4917 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
4918 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
4919 connector->name);
4920 }
4921}
d0c94692 4922
23ebf8b9
VS		 4923static void
4924drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
4925{
4926 struct drm_display_info *info = &connector->display_info;
4927 u8 len = cea_db_payload_len(db);
4928
a92d083d
LP		 4929 info->is_hdmi = true;
4930
23ebf8b9
VS		 4931 if (len >= 6)
4932 info->dvi_dual = db[6] & 1;
4933 if (len >= 7)
4934 info->max_tmds_clock = db[7] * 5000;
4935
4936 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
4937 "max TMDS clock %d kHz\n",
4938 info->dvi_dual,
4939 info->max_tmds_clock);
4940
4941 drm_parse_hdmi_deep_color_info(connector, db);
4942}
4943
1cea146a 4944static void drm_parse_cea_ext(struct drm_connector *connector,
170178fe 4945 const struct edid *edid)
1cea146a
VS		 4946{
4947 struct drm_display_info *info = &connector->display_info;
4948 const u8 *edid_ext;
4949 int i, start, end;
d0c94692 4950
1cea146a
VS		 4951 edid_ext = drm_find_cea_extension(edid);
4952 if (!edid_ext)
4953 return;
d0c94692 4954
1cea146a 4955 info->cea_rev = edid_ext[1];
d0c94692 4956
1cea146a
VS		 4957 /* The existence of a CEA block should imply RGB support */
4958 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4959 if (edid_ext[3] & EDID_CEA_YCRCB444)
4960 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4961 if (edid_ext[3] & EDID_CEA_YCRCB422)
4962 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4963
4964 if (cea_db_offsets(edid_ext, &start, &end))
4965 return;
4966
4967 for_each_cea_db(edid_ext, i, start, end) {
4968 const u8 *db = &edid_ext[i];
4969
23ebf8b9
VS		 4970 if (cea_db_is_hdmi_vsdb(db))
4971 drm_parse_hdmi_vsdb_video(connector, db);
afa1c763
SS		 4972 if (cea_db_is_hdmi_forum_vsdb(db))
4973 drm_parse_hdmi_forum_vsdb(connector, db);
832d4f2f
SS		 4974 if (cea_db_is_y420cmdb(db))
4975 drm_parse_y420cmdb_bitmap(connector, db);
1581b2df
VS		 4976 if (cea_db_is_vcdb(db))
4977 drm_parse_vcdb(connector, db);
e85959d6
US		 4978 if (cea_db_is_hdmi_hdr_metadata_block(db))
4979 drm_parse_hdr_metadata_block(connector, db);
1cea146a 4980 }
d0c94692
MK		 4981}
4982
a1d11d1e
MN		 4983static
4984void get_monitor_range(struct detailed_timing *timing,
4985 void *info_monitor_range)
4986{
4987 struct drm_monitor_range_info *monitor_range = info_monitor_range;
4988 const struct detailed_non_pixel *data = &timing->data.other_data;
4989 const struct detailed_data_monitor_range *range = &data->data.range;
4990
4991 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE))
4992 return;
4993
4994 /*
4995 * Check for flag range limits only. If flag == 1 then
4996 * no additional timing information provided.
4997 * Default GTF, GTF Secondary curve and CVT are not
4998 * supported
4999 */
5000 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG)
5001 return;
5002
5003 monitor_range->min_vfreq = range->min_vfreq;
5004 monitor_range->max_vfreq = range->max_vfreq;
5005}
5006
5007static
5008void drm_get_monitor_range(struct drm_connector *connector,
5009 const struct edid *edid)
5010{
5011 struct drm_display_info *info = &connector->display_info;
5012
5013 if (!version_greater(edid, 1, 1))
5014 return;
5015
5016 drm_for_each_detailed_block((u8 *)edid, get_monitor_range,
5017 &info->monitor_range);
5018
5019 DRM_DEBUG_KMS("Supported Monitor Refresh rate range is %d Hz - %d Hz\n",
5020 info->monitor_range.min_vfreq,
5021 info->monitor_range.max_vfreq);
5022}
5023
170178fe
KP		 5024/* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
5025 * all of the values which would have been set from EDID
5026 */
5027void
5028drm_reset_display_info(struct drm_connector *connector)
5029{
5030 struct drm_display_info *info = &connector->display_info;
5031
5032 info->width_mm = 0;
5033 info->height_mm = 0;
5034
5035 info->bpc = 0;
5036 info->color_formats = 0;
5037 info->cea_rev = 0;
5038 info->max_tmds_clock = 0;
5039 info->dvi_dual = false;
a92d083d 5040 info->is_hdmi = false;
170178fe 5041 info->has_hdmi_infoframe = false;
1581b2df 5042 info->rgb_quant_range_selectable = false;
1f6b8eef 5043 memset(&info->hdmi, 0, sizeof(info->hdmi));
170178fe
KP		 5044
5045 info->non_desktop = 0;
a1d11d1e 5046 memset(&info->monitor_range, 0, sizeof(info->monitor_range));
170178fe 5047}
170178fe
KP		 5048
5049u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid)
3b11228b 5050{
1826750f 5051 struct drm_display_info *info = &connector->display_info;
ebec9a7b 5052
170178fe
KP		 5053 u32 quirks = edid_get_quirks(edid);
5054
1f6b8eef
VS		 5055 drm_reset_display_info(connector);
5056
3b11228b
JB		 5057 info->width_mm = edid->width_cm * 10;
5058 info->height_mm = edid->height_cm * 10;
5059
66660d4c
DA		 5060 info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP);
5061
a1d11d1e
MN		 5062 drm_get_monitor_range(connector, edid);
5063
170178fe
KP		 5064 DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop);
5065
a988bc72 5066 if (edid->revision < 3)
170178fe 5067 return quirks;
3b11228b
JB		 5068
5069 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
170178fe 5070 return quirks;
3b11228b 5071
1cea146a 5072 drm_parse_cea_ext(connector, edid);
d0c94692 5073
210a021d
MK		 5074 /*
5075 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
5076 *
5077 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
5078 * tells us to assume 8 bpc color depth if the EDID doesn't have
5079 * extensions which tell otherwise.
5080 */
3bde449f
VS		 5081 if (info->bpc == 0 && edid->revision == 3 &&
5082 edid->input & DRM_EDID_DIGITAL_DFP_1_X) {
210a021d
MK		 5083 info->bpc = 8;
5084 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
5085 connector->name, info->bpc);
5086 }
5087
a988bc72
LPC		 5088 /* Only defined for 1.4 with digital displays */
5089 if (edid->revision < 4)
170178fe 5090 return quirks;
a988bc72 5091
3b11228b
JB		 5092 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
5093 case DRM_EDID_DIGITAL_DEPTH_6:
5094 info->bpc = 6;
5095 break;
5096 case DRM_EDID_DIGITAL_DEPTH_8:
5097 info->bpc = 8;
5098 break;
5099 case DRM_EDID_DIGITAL_DEPTH_10:
5100 info->bpc = 10;
5101 break;
5102 case DRM_EDID_DIGITAL_DEPTH_12:
5103 info->bpc = 12;
5104 break;
5105 case DRM_EDID_DIGITAL_DEPTH_14:
5106 info->bpc = 14;
5107 break;
5108 case DRM_EDID_DIGITAL_DEPTH_16:
5109 info->bpc = 16;
5110 break;
5111 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
5112 default:
5113 info->bpc = 0;
5114 break;
5115 }
da05a5a7 5116
d0c94692 5117 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
25933820 5118 connector->name, info->bpc);
d0c94692 5119
a988bc72 5120 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
ee58808d
LPC		 5121 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
5122 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
5123 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
5124 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
170178fe 5125 return quirks;
3b11228b
JB		 5126}
5127
c9729177
DA		 5128static int validate_displayid(u8 *displayid, int length, int idx)
5129{
bd1f64df 5130 int i, dispid_length;
c9729177
DA		 5131 u8 csum = 0;
5132 struct displayid_hdr *base;
5133
5134 base = (struct displayid_hdr *)&displayid[idx];
5135
5136 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",
5137 base->rev, base->bytes, base->prod_id, base->ext_count);
5138
bd1f64df
VS		 5139 /* +1 for DispID checksum */
5140 dispid_length = sizeof(*base) + base->bytes + 1;
5141 if (dispid_length > length - idx)
c9729177 5142 return -EINVAL;
bd1f64df
VS		 5143
5144 for (i = 0; i < dispid_length; i++)
5145 csum += displayid[idx + i];
c9729177 5146 if (csum) {
813a7878 5147 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum);
c9729177
DA		 5148 return -EINVAL;
5149 }
bd1f64df 5150
c9729177
DA		 5151 return 0;
5152}
5153
a39ed680
DA		 5154static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
5155 struct displayid_detailed_timings_1 *timings)
5156{
5157 struct drm_display_mode *mode;
5158 unsigned pixel_clock = (timings->pixel_clock[0] |
5159 (timings->pixel_clock[1] << 8) |
6292b8ef 5160 (timings->pixel_clock[2] << 16)) + 1;
a39ed680
DA		 5161 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
5162 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
5163 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
5164 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
5165 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
5166 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
5167 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
5168 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
5169 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
5170 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
5171 mode = drm_mode_create(dev);
5172 if (!mode)
5173 return NULL;
5174
5175 mode->clock = pixel_clock * 10;
5176 mode->hdisplay = hactive;
5177 mode->hsync_start = mode->hdisplay + hsync;
5178 mode->hsync_end = mode->hsync_start + hsync_width;
5179 mode->htotal = mode->hdisplay + hblank;
5180
5181 mode->vdisplay = vactive;
5182 mode->vsync_start = mode->vdisplay + vsync;
5183 mode->vsync_end = mode->vsync_start + vsync_width;
5184 mode->vtotal = mode->vdisplay + vblank;
5185
5186 mode->flags = 0;
5187 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
5188 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
5189 mode->type = DRM_MODE_TYPE_DRIVER;
5190
5191 if (timings->flags & 0x80)
5192 mode->type |= DRM_MODE_TYPE_PREFERRED;
a39ed680
DA		 5193 drm_mode_set_name(mode);
5194
5195 return mode;
5196}
5197
5198static int add_displayid_detailed_1_modes(struct drm_connector *connector,
5199 struct displayid_block *block)
5200{
5201 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
5202 int i;
5203 int num_timings;
5204 struct drm_display_mode *newmode;
5205 int num_modes = 0;
5206 /* blocks must be multiple of 20 bytes length */
5207 if (block->num_bytes % 20)
5208 return 0;
5209
5210 num_timings = block->num_bytes / 20;
5211 for (i = 0; i < num_timings; i++) {
5212 struct displayid_detailed_timings_1 *timings = &det->timings[i];
5213
5214 newmode = drm_mode_displayid_detailed(connector->dev, timings);
5215 if (!newmode)
5216 continue;
5217
5218 drm_mode_probed_add(connector, newmode);
5219 num_modes++;
5220 }
5221 return num_modes;
5222}
5223
5224static int add_displayid_detailed_modes(struct drm_connector *connector,
5225 struct edid *edid)
5226{
5227 u8 *displayid;
23b03867 5228 int length, idx;
a39ed680
DA		 5229 struct displayid_block *block;
5230 int num_modes = 0;
5231
23b03867 5232 displayid = drm_find_displayid_extension(edid, &length, &idx);
a39ed680
DA		 5233 if (!displayid)
5234 return 0;
5235
a39ed680 5236 idx += sizeof(struct displayid_hdr);
80d42db0 5237 for_each_displayid_db(displayid, block, idx, length) {
a39ed680
DA		 5238 switch (block->tag) {
5239 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
5240 num_modes += add_displayid_detailed_1_modes(connector, block);
5241 break;
5242 }
5243 }
5244 return num_modes;
5245}
5246
f453ba04
DA		 5247/**
5248 * drm_add_edid_modes - add modes from EDID data, if available
5249 * @connector: connector we're probing
db6cf833 5250 * @edid: EDID data
f453ba04 5251 *
b3c6c8bf 5252 * Add the specified modes to the connector's mode list. Also fills out the
c945b8c1
JN		 5253 * &drm_display_info structure and ELD in @connector with any information which
5254 * can be derived from the edid.
f453ba04 5255 *
db6cf833 5256 * Return: The number of modes added or 0 if we couldn't find any.
f453ba04
DA		 5257 */
5258int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
5259{
5260 int num_modes = 0;
5261 u32 quirks;
5262
5263 if (edid == NULL) {
c945b8c1 5264 clear_eld(connector);
f453ba04
DA		 5265 return 0;
5266 }
3c537889 5267 if (!drm_edid_is_valid(edid)) {
c945b8c1 5268 clear_eld(connector);
dcdb1674 5269 dev_warn(connector->dev->dev, "%s: EDID invalid.\n",
25933820 5270 connector->name);
f453ba04
DA		 5271 return 0;
5272 }
5273
c945b8c1
JN		 5274 drm_edid_to_eld(connector, edid);
5275
0f0f8708
SS		 5276 /*
5277 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
5278 * To avoid multiple parsing of same block, lets parse that map
5279 * from sink info, before parsing CEA modes.
5280 */
170178fe 5281 quirks = drm_add_display_info(connector, edid);
0f0f8708 5282
c867df70
AJ		 5283 /*
5284 * EDID spec says modes should be preferred in this order:
5285 * - preferred detailed mode
5286 * - other detailed modes from base block
5287 * - detailed modes from extension blocks
5288 * - CVT 3-byte code modes
5289 * - standard timing codes
5290 * - established timing codes
5291 * - modes inferred from GTF or CVT range information
5292 *
13931579 5293 * We get this pretty much right.
c867df70
AJ		 5294 *
5295 * XXX order for additional mode types in extension blocks?
5296 */
13931579
AJ		 5297 num_modes += add_detailed_modes(connector, edid, quirks);
5298 num_modes += add_cvt_modes(connector, edid);
c867df70
AJ		 5299 num_modes += add_standard_modes(connector, edid);
5300 num_modes += add_established_modes(connector, edid);
54ac76f8 5301 num_modes += add_cea_modes(connector, edid);
e6e79209 5302 num_modes += add_alternate_cea_modes(connector, edid);
a39ed680 5303 num_modes += add_displayid_detailed_modes(connector, edid);
4d53dc0c
VS		 5304 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
5305 num_modes += add_inferred_modes(connector, edid);
f453ba04
DA		 5306
5307 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
5308 edid_fixup_preferred(connector, quirks);
5309
e10aec65
MK		 5310 if (quirks & EDID_QUIRK_FORCE_6BPC)
5311 connector->display_info.bpc = 6;
5312
49d45a31
RM		 5313 if (quirks & EDID_QUIRK_FORCE_8BPC)
5314 connector->display_info.bpc = 8;
5315
e345da82
MK		 5316 if (quirks & EDID_QUIRK_FORCE_10BPC)
5317 connector->display_info.bpc = 10;
5318
bc5b9641
MK		 5319 if (quirks & EDID_QUIRK_FORCE_12BPC)
5320 connector->display_info.bpc = 12;
5321
f453ba04
DA		 5322 return num_modes;
5323}
5324EXPORT_SYMBOL(drm_add_edid_modes);
f0fda0a4
ZY		 5325
5326/**
5327 * drm_add_modes_noedid - add modes for the connectors without EDID
5328 * @connector: connector we're probing
5329 * @hdisplay: the horizontal display limit
5330 * @vdisplay: the vertical display limit
5331 *
5332 * Add the specified modes to the connector's mode list. Only when the
5333 * hdisplay/vdisplay is not beyond the given limit, it will be added.
5334 *
db6cf833 5335 * Return: The number of modes added or 0 if we couldn't find any.
f0fda0a4
ZY		 5336 */
5337int drm_add_modes_noedid(struct drm_connector *connector,
5338 int hdisplay, int vdisplay)
5339{
5340 int i, count, num_modes = 0;
b1f559ec 5341 struct drm_display_mode *mode;
f0fda0a4
ZY		 5342 struct drm_device *dev = connector->dev;
5343
fbb40b28 5344 count = ARRAY_SIZE(drm_dmt_modes);
f0fda0a4
ZY		 5345 if (hdisplay < 0)
5346 hdisplay = 0;
5347 if (vdisplay < 0)
5348 vdisplay = 0;
5349
5350 for (i = 0; i < count; i++) {
b1f559ec 5351 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
f0fda0a4
ZY		 5352 if (hdisplay && vdisplay) {
5353 /*
5354 * Only when two are valid, they will be used to check
5355 * whether the mode should be added to the mode list of
5356 * the connector.
5357 */
5358 if (ptr->hdisplay > hdisplay ||
5359 ptr->vdisplay > vdisplay)
5360 continue;
5361 }
f985dedb
AJ		 5362 if (drm_mode_vrefresh(ptr) > 61)
5363 continue;
f0fda0a4
ZY		 5364 mode = drm_mode_duplicate(dev, ptr);
5365 if (mode) {
5366 drm_mode_probed_add(connector, mode);
5367 num_modes++;
5368 }
5369 }
5370 return num_modes;
5371}
5372EXPORT_SYMBOL(drm_add_modes_noedid);
10a85120 5373
db6cf833
TR		 5374/**
5375 * drm_set_preferred_mode - Sets the preferred mode of a connector
5376 * @connector: connector whose mode list should be processed
5377 * @hpref: horizontal resolution of preferred mode
5378 * @vpref: vertical resolution of preferred mode
5379 *
5380 * Marks a mode as preferred if it matches the resolution specified by @hpref
5381 * and @vpref.
5382 */
3cf70daf
GH		 5383void drm_set_preferred_mode(struct drm_connector *connector,
5384 int hpref, int vpref)
5385{
5386 struct drm_display_mode *mode;
5387
5388 list_for_each_entry(mode, &connector->probed_modes, head) {
db6cf833 5389 if (mode->hdisplay == hpref &&
9d3de138 5390 mode->vdisplay == vpref)
3cf70daf
GH		 5391 mode->type |= DRM_MODE_TYPE_PREFERRED;
5392 }
5393}
5394EXPORT_SYMBOL(drm_set_preferred_mode);
5395
192a3aa0 5396static bool is_hdmi2_sink(const struct drm_connector *connector)
13d0add3
VS		 5397{
5398 /*
5399 * FIXME: sil-sii8620 doesn't have a connector around when
5400 * we need one, so we have to be prepared for a NULL connector.
5401 */
5402 if (!connector)
5403 return true;
5404
5405 return connector->display_info.hdmi.scdc.supported ||
5406 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420;
5407}
5408
2cdbfd66
US		 5409static inline bool is_eotf_supported(u8 output_eotf, u8 sink_eotf)
5410{
5411 return sink_eotf & BIT(output_eotf);
5412}
5413
5414/**
5415 * drm_hdmi_infoframe_set_hdr_metadata() - fill an HDMI DRM infoframe with
5416 * HDR metadata from userspace
5417 * @frame: HDMI DRM infoframe
6ac98829 5418 * @conn_state: Connector state containing HDR metadata
2cdbfd66
US		 5419 *
5420 * Return: 0 on success or a negative error code on failure.
5421 */
5422int
5423drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame,
5424 const struct drm_connector_state *conn_state)
5425{
5426 struct drm_connector *connector;
5427 struct hdr_output_metadata *hdr_metadata;
5428 int err;
5429
5430 if (!frame || !conn_state)
5431 return -EINVAL;
5432
5433 connector = conn_state->connector;
5434
5435 if (!conn_state->hdr_output_metadata)
5436 return -EINVAL;
5437
5438 hdr_metadata = conn_state->hdr_output_metadata->data;
5439
5440 if (!hdr_metadata || !connector)
5441 return -EINVAL;
5442
5443 /* Sink EOTF is Bit map while infoframe is absolute values */
5444 if (!is_eotf_supported(hdr_metadata->hdmi_metadata_type1.eotf,
5445 connector->hdr_sink_metadata.hdmi_type1.eotf)) {
5446 DRM_DEBUG_KMS("EOTF Not Supported\n");
5447 return -EINVAL;
5448 }
5449
5450 err = hdmi_drm_infoframe_init(frame);
5451 if (err < 0)
5452 return err;
5453
5454 frame->eotf = hdr_metadata->hdmi_metadata_type1.eotf;
5455 frame->metadata_type = hdr_metadata->hdmi_metadata_type1.metadata_type;
5456
5457 BUILD_BUG_ON(sizeof(frame->display_primaries) !=
5458 sizeof(hdr_metadata->hdmi_metadata_type1.display_primaries));
5459 BUILD_BUG_ON(sizeof(frame->white_point) !=
5460 sizeof(hdr_metadata->hdmi_metadata_type1.white_point));
5461
5462 memcpy(&frame->display_primaries,
5463 &hdr_metadata->hdmi_metadata_type1.display_primaries,
5464 sizeof(frame->display_primaries));
5465
5466 memcpy(&frame->white_point,
5467 &hdr_metadata->hdmi_metadata_type1.white_point,
5468 sizeof(frame->white_point));
5469
5470 frame->max_display_mastering_luminance =
5471 hdr_metadata->hdmi_metadata_type1.max_display_mastering_luminance;
5472 frame->min_display_mastering_luminance =
5473 hdr_metadata->hdmi_metadata_type1.min_display_mastering_luminance;
5474 frame->max_fall = hdr_metadata->hdmi_metadata_type1.max_fall;
5475 frame->max_cll = hdr_metadata->hdmi_metadata_type1.max_cll;
5476
5477 return 0;
5478}
5479EXPORT_SYMBOL(drm_hdmi_infoframe_set_hdr_metadata);
5480
192a3aa0 5481static u8 drm_mode_hdmi_vic(const struct drm_connector *connector,
949561eb
VS		 5482 const struct drm_display_mode *mode)
5483{
5484 bool has_hdmi_infoframe = connector ?
5485 connector->display_info.has_hdmi_infoframe : false;
5486
5487 if (!has_hdmi_infoframe)
5488 return 0;
5489
5490 /* No HDMI VIC when signalling 3D video format */
5491 if (mode->flags & DRM_MODE_FLAG_3D_MASK)
5492 return 0;
5493
5494 return drm_match_hdmi_mode(mode);
5495}
5496
192a3aa0 5497static u8 drm_mode_cea_vic(const struct drm_connector *connector,
cfd6f8c3
VS		 5498 const struct drm_display_mode *mode)
5499{
cfd6f8c3
VS		 5500 u8 vic;
5501
5502 /*
5503 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
5504 * we should send its VIC in vendor infoframes, else send the
5505 * VIC in AVI infoframes. Lets check if this mode is present in
5506 * HDMI 1.4b 4K modes
5507 */
949561eb 5508 if (drm_mode_hdmi_vic(connector, mode))
cfd6f8c3
VS		 5509 return 0;
5510
5511 vic = drm_match_cea_mode(mode);
5512
5513 /*
5514 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
5515 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
5516 * have to make sure we dont break HDMI 1.4 sinks.
5517 */
5518 if (!is_hdmi2_sink(connector) && vic > 64)
5519 return 0;
5520
5521 return vic;
5522}
5523
10a85120
TR		 5524/**
5525 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
5526 * data from a DRM display mode
5527 * @frame: HDMI AVI infoframe
13d0add3 5528 * @connector: the connector
10a85120
TR		 5529 * @mode: DRM display mode
5530 *
db6cf833 5531 * Return: 0 on success or a negative error code on failure.
10a85120
TR		 5532 */
5533int
5534drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
192a3aa0 5535 const struct drm_connector *connector,
13d0add3 5536 const struct drm_display_mode *mode)
10a85120 5537{
a9c266c2 5538 enum hdmi_picture_aspect picture_aspect;
d2b43473 5539 u8 vic, hdmi_vic;
10a85120
TR		 5540
5541 if (!frame || !mode)
5542 return -EINVAL;
5543
5ee0caf1 5544 hdmi_avi_infoframe_init(frame);
10a85120 5545
bf02db99
DL		 5546 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
5547 frame->pixel_repeat = 1;
5548
d2b43473
WL		 5549 vic = drm_mode_cea_vic(connector, mode);
5550 hdmi_vic = drm_mode_hdmi_vic(connector, mode);
0c1f528c 5551
10a85120 5552 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
0967e6a5 5553
50525c33
SL		 5554 /*
5555 * As some drivers don't support atomic, we can't use connector state.
5556 * So just initialize the frame with default values, just the same way
5557 * as it's done with other properties here.
5558 */
5559 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
5560 frame->itc = 0;
5561
69ab6d35
VK		 5562 /*
5563 * Populate picture aspect ratio from either
d2b43473 5564 * user input (if specified) or from the CEA/HDMI mode lists.
69ab6d35 5565 */
a9c266c2 5566 picture_aspect = mode->picture_aspect_ratio;
d2b43473
WL		 5567 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) {
5568 if (vic)
5569 picture_aspect = drm_get_cea_aspect_ratio(vic);
5570 else if (hdmi_vic)
5571 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic);
5572 }
0967e6a5 5573
a9c266c2
VS		 5574 /*
5575 * The infoframe can't convey anything but none, 4:3
5576 * and 16:9, so if the user has asked for anything else
5577 * we can only satisfy it by specifying the right VIC.
5578 */
5579 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
d2b43473
WL		 5580 if (vic) {
5581 if (picture_aspect != drm_get_cea_aspect_ratio(vic))
5582 return -EINVAL;
5583 } else if (hdmi_vic) {
5584 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic))
5585 return -EINVAL;
5586 } else {
a9c266c2 5587 return -EINVAL;
d2b43473
WL		 5588 }
5589
a9c266c2
VS		 5590 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
5591 }
5592
d2b43473 5593 frame->video_code = vic;
a9c266c2 5594 frame->picture_aspect = picture_aspect;
10a85120 5595 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
24d01805 5596 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
10a85120
TR		 5597
5598 return 0;
5599}
5600EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
83dd0008 5601
0d68b887
US		 5602/* HDMI Colorspace Spec Definitions */
5603#define FULL_COLORIMETRY_MASK 0x1FF
5604#define NORMAL_COLORIMETRY_MASK 0x3
5605#define EXTENDED_COLORIMETRY_MASK 0x7
5606#define EXTENDED_ACE_COLORIMETRY_MASK 0xF
5607
5608#define C(x) ((x) << 0)
5609#define EC(x) ((x) << 2)
5610#define ACE(x) ((x) << 5)
5611
5612#define HDMI_COLORIMETRY_NO_DATA 0x0
5613#define HDMI_COLORIMETRY_SMPTE_170M_YCC (C(1) | EC(0) | ACE(0))
5614#define HDMI_COLORIMETRY_BT709_YCC (C(2) | EC(0) | ACE(0))
5615#define HDMI_COLORIMETRY_XVYCC_601 (C(3) | EC(0) | ACE(0))
5616#define HDMI_COLORIMETRY_XVYCC_709 (C(3) | EC(1) | ACE(0))
5617#define HDMI_COLORIMETRY_SYCC_601 (C(3) | EC(2) | ACE(0))
5618#define HDMI_COLORIMETRY_OPYCC_601 (C(3) | EC(3) | ACE(0))
5619#define HDMI_COLORIMETRY_OPRGB (C(3) | EC(4) | ACE(0))
5620#define HDMI_COLORIMETRY_BT2020_CYCC (C(3) | EC(5) | ACE(0))
5621#define HDMI_COLORIMETRY_BT2020_RGB (C(3) | EC(6) | ACE(0))
5622#define HDMI_COLORIMETRY_BT2020_YCC (C(3) | EC(6) | ACE(0))
5623#define HDMI_COLORIMETRY_DCI_P3_RGB_D65 (C(3) | EC(7) | ACE(0))
5624#define HDMI_COLORIMETRY_DCI_P3_RGB_THEATER (C(3) | EC(7) | ACE(1))
5625
5626static const u32 hdmi_colorimetry_val[] = {
5627 [DRM_MODE_COLORIMETRY_NO_DATA] = HDMI_COLORIMETRY_NO_DATA,
5628 [DRM_MODE_COLORIMETRY_SMPTE_170M_YCC] = HDMI_COLORIMETRY_SMPTE_170M_YCC,
5629 [DRM_MODE_COLORIMETRY_BT709_YCC] = HDMI_COLORIMETRY_BT709_YCC,
5630 [DRM_MODE_COLORIMETRY_XVYCC_601] = HDMI_COLORIMETRY_XVYCC_601,
5631 [DRM_MODE_COLORIMETRY_XVYCC_709] = HDMI_COLORIMETRY_XVYCC_709,
5632 [DRM_MODE_COLORIMETRY_SYCC_601] = HDMI_COLORIMETRY_SYCC_601,
5633 [DRM_MODE_COLORIMETRY_OPYCC_601] = HDMI_COLORIMETRY_OPYCC_601,
5634 [DRM_MODE_COLORIMETRY_OPRGB] = HDMI_COLORIMETRY_OPRGB,
5635 [DRM_MODE_COLORIMETRY_BT2020_CYCC] = HDMI_COLORIMETRY_BT2020_CYCC,
5636 [DRM_MODE_COLORIMETRY_BT2020_RGB] = HDMI_COLORIMETRY_BT2020_RGB,
5637 [DRM_MODE_COLORIMETRY_BT2020_YCC] = HDMI_COLORIMETRY_BT2020_YCC,
5638};
5639
5640#undef C
5641#undef EC
5642#undef ACE
5643
5644/**
5645 * drm_hdmi_avi_infoframe_colorspace() - fill the HDMI AVI infoframe
5646 * colorspace information
5647 * @frame: HDMI AVI infoframe
5648 * @conn_state: connector state
5649 */
5650void
5651drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame,
5652 const struct drm_connector_state *conn_state)
5653{
5654 u32 colorimetry_val;
5655 u32 colorimetry_index = conn_state->colorspace & FULL_COLORIMETRY_MASK;
5656
5657 if (colorimetry_index >= ARRAY_SIZE(hdmi_colorimetry_val))
5658 colorimetry_val = HDMI_COLORIMETRY_NO_DATA;
5659 else
5660 colorimetry_val = hdmi_colorimetry_val[colorimetry_index];
5661
5662 frame->colorimetry = colorimetry_val & NORMAL_COLORIMETRY_MASK;
5663 /*
5664 * ToDo: Extend it for ACE formats as well. Modify the infoframe
5665 * structure and extend it in drivers/video/hdmi
5666 */
5667 frame->extended_colorimetry = (colorimetry_val >> 2) &
5668 EXTENDED_COLORIMETRY_MASK;
5669}
5670EXPORT_SYMBOL(drm_hdmi_avi_infoframe_colorspace);
5671
a2ce26f8
VS		 5672/**
5673 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
5674 * quantization range information
5675 * @frame: HDMI AVI infoframe
13d0add3 5676 * @connector: the connector
779c4c28 5677 * @mode: DRM display mode
a2ce26f8 5678 * @rgb_quant_range: RGB quantization range (Q)
a2ce26f8
VS		 5679 */
5680void
5681drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
192a3aa0 5682 const struct drm_connector *connector,
779c4c28 5683 const struct drm_display_mode *mode,
1581b2df 5684 enum hdmi_quantization_range rgb_quant_range)
a2ce26f8 5685{
1581b2df
VS		 5686 const struct drm_display_info *info = &connector->display_info;
5687
a2ce26f8
VS		 5688 /*
5689 * CEA-861:
5690 * "A Source shall not send a non-zero Q value that does not correspond
5691 * to the default RGB Quantization Range for the transmitted Picture
5692 * unless the Sink indicates support for the Q bit in a Video
5693 * Capabilities Data Block."
779c4c28
VS		 5694 *
5695 * HDMI 2.0 recommends sending non-zero Q when it does match the
5696 * default RGB quantization range for the mode, even when QS=0.
a2ce26f8 5697 */
1581b2df 5698 if (info->rgb_quant_range_selectable ||
779c4c28 5699 rgb_quant_range == drm_default_rgb_quant_range(mode))
a2ce26f8
VS		 5700 frame->quantization_range = rgb_quant_range;
5701 else
5702 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
fcc8a22c
VS		 5703
5704 /*
5705 * CEA-861-F:
5706 * "When transmitting any RGB colorimetry, the Source should set the
5707 * YQ-field to match the RGB Quantization Range being transmitted
5708 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
5709 * set YQ=1) and the Sink shall ignore the YQ-field."
9271c0ca
VS		 5710 *
5711 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
5712 * by non-zero YQ when receiving RGB. There doesn't seem to be any
5713 * good way to tell which version of CEA-861 the sink supports, so
5714 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
5715 * on on CEA-861-F.
fcc8a22c 5716 */
13d0add3 5717 if (!is_hdmi2_sink(connector) ||
9271c0ca 5718 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
fcc8a22c
VS		 5719 frame->ycc_quantization_range =
5720 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
5721 else
5722 frame->ycc_quantization_range =
5723 HDMI_YCC_QUANTIZATION_RANGE_FULL;
a2ce26f8
VS		 5724}
5725EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
5726
076d9a5d
VS		 5727/**
5728 * drm_hdmi_avi_infoframe_bars() - fill the HDMI AVI infoframe
5729 * bar information
5730 * @frame: HDMI AVI infoframe
5731 * @conn_state: connector state
5732 */
5733void
5734drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe *frame,
5735 const struct drm_connector_state *conn_state)
5736{
5737 frame->right_bar = conn_state->tv.margins.right;
5738 frame->left_bar = conn_state->tv.margins.left;
5739 frame->top_bar = conn_state->tv.margins.top;
5740 frame->bottom_bar = conn_state->tv.margins.bottom;
5741}
5742EXPORT_SYMBOL(drm_hdmi_avi_infoframe_bars);
5743
4eed4a0a
DL		 5744static enum hdmi_3d_structure
5745s3d_structure_from_display_mode(const struct drm_display_mode *mode)
5746{
5747 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
5748
5749 switch (layout) {
5750 case DRM_MODE_FLAG_3D_FRAME_PACKING:
5751 return HDMI_3D_STRUCTURE_FRAME_PACKING;
5752 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
5753 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
5754 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
5755 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
5756 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
5757 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
5758 case DRM_MODE_FLAG_3D_L_DEPTH:
5759 return HDMI_3D_STRUCTURE_L_DEPTH;
5760 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
5761 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
5762 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
5763 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
5764 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
5765 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
5766 default:
5767 return HDMI_3D_STRUCTURE_INVALID;
5768 }
5769}
5770
83dd0008
LD		 5771/**
5772 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
5773 * data from a DRM display mode
5774 * @frame: HDMI vendor infoframe
f1781e9b 5775 * @connector: the connector
83dd0008
LD		 5776 * @mode: DRM display mode
5777 *
5778 * Note that there's is a need to send HDMI vendor infoframes only when using a
5779 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
5780 * function will return -EINVAL, error that can be safely ignored.
5781 *
db6cf833 5782 * Return: 0 on success or a negative error code on failure.
83dd0008
LD		 5783 */
5784int
5785drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
192a3aa0 5786 const struct drm_connector *connector,
83dd0008
LD		 5787 const struct drm_display_mode *mode)
5788{
f1781e9b
VS		 5789 /*
5790 * FIXME: sil-sii8620 doesn't have a connector around when
5791 * we need one, so we have to be prepared for a NULL connector.
5792 */
5793 bool has_hdmi_infoframe = connector ?
5794 connector->display_info.has_hdmi_infoframe : false;
83dd0008 5795 int err;
83dd0008
LD		 5796
5797 if (!frame || !mode)
5798 return -EINVAL;
5799
f1781e9b
VS		 5800 if (!has_hdmi_infoframe)
5801 return -EINVAL;
5802
949561eb
VS		 5803 err = hdmi_vendor_infoframe_init(frame);
5804 if (err < 0)
5805 return err;
4eed4a0a 5806
f1781e9b
VS		 5807 /*
5808 * Even if it's not absolutely necessary to send the infoframe
5809 * (ie.vic==0 and s3d_struct==0) we will still send it if we
5810 * know that the sink can handle it. This is based on a
5811 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
5812 * have trouble realizing that they shuld switch from 3D to 2D
5813 * mode if the source simply stops sending the infoframe when
5814 * it wants to switch from 3D to 2D.
5815 */
949561eb 5816 frame->vic = drm_mode_hdmi_vic(connector, mode);
f1781e9b 5817 frame->s3d_struct = s3d_structure_from_display_mode(mode);
83dd0008
LD		 5818
5819 return 0;
5820}
5821EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
40d9b043 5822
5e546cd5 5823static int drm_parse_tiled_block(struct drm_connector *connector,
092c367a 5824 const struct displayid_block *block)
5e546cd5 5825{
092c367a 5826 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
5e546cd5
DA		 5827 u16 w, h;
5828 u8 tile_v_loc, tile_h_loc;
5829 u8 num_v_tile, num_h_tile;
5830 struct drm_tile_group *tg;
5831
5832 w = tile->tile_size[0] | tile->tile_size[1] << 8;
5833 h = tile->tile_size[2] | tile->tile_size[3] << 8;
5834
5835 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
5836 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
5837 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
5838 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
5839
5840 connector->has_tile = true;
5841 if (tile->tile_cap & 0x80)
5842 connector->tile_is_single_monitor = true;
5843
5844 connector->num_h_tile = num_h_tile + 1;
5845 connector->num_v_tile = num_v_tile + 1;
5846 connector->tile_h_loc = tile_h_loc;
5847 connector->tile_v_loc = tile_v_loc;
5848 connector->tile_h_size = w + 1;
5849 connector->tile_v_size = h + 1;
5850
5851 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
5852 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
5853 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
5854 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
5855 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
5856
5857 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
5858 if (!tg) {
5859 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
5860 }
5861 if (!tg)
5862 return -ENOMEM;
5863
5864 if (connector->tile_group != tg) {
5865 /* if we haven't got a pointer,
5866 take the reference, drop ref to old tile group */
5867 if (connector->tile_group) {
5868 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5869 }
5870 connector->tile_group = tg;
5871 } else
5872 /* if same tile group, then release the ref we just took. */
5873 drm_mode_put_tile_group(connector->dev, tg);
5874 return 0;
5875}
5876
092c367a
VS		 5877static int drm_displayid_parse_tiled(struct drm_connector *connector,
5878 const u8 *displayid, int length, int idx)
40d9b043 5879{
092c367a 5880 const struct displayid_block *block;
5e546cd5 5881 int ret;
40d9b043 5882
3a4a2ea3 5883 idx += sizeof(struct displayid_hdr);
80d42db0 5884 for_each_displayid_db(displayid, block, idx, length) {
3a4a2ea3
TB		 5885 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n",
5886 block->tag, block->rev, block->num_bytes);
5887
5888 switch (block->tag) {
5889 case DATA_BLOCK_TILED_DISPLAY:
5890 ret = drm_parse_tiled_block(connector, block);
5891 if (ret)
5892 return ret;
5893 break;
5894 default:
5895 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag);
5896 break;
5897 }
40d9b043
DA		 5898 }
5899 return 0;
5900}
5901
092c367a
VS		 5902void drm_update_tile_info(struct drm_connector *connector,
5903 const struct edid *edid)
40d9b043 5904{
092c367a 5905 const void *displayid = NULL;
23b03867 5906 int length, idx;
40d9b043 5907 int ret;
36881184 5908
40d9b043 5909 connector->has_tile = false;
23b03867 5910 displayid = drm_find_displayid_extension(edid, &length, &idx);
40d9b043
DA		 5911 if (!displayid) {
5912 /* drop reference to any tile group we had */
5913 goto out_drop_ref;
5914 }
5915
092c367a 5916 ret = drm_displayid_parse_tiled(connector, displayid, length, idx);
40d9b043
DA		 5917 if (ret < 0)
5918 goto out_drop_ref;
5919 if (!connector->has_tile)
5920 goto out_drop_ref;
5921 return;
5922out_drop_ref:
5923 if (connector->tile_group) {
5924 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5925 connector->tile_group = NULL;
5926 }
5927 return;
5928}
Linux 6.x block layer and io_uring tree(s)