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drm/panfrost: Add support for multiple power domains
[linux-2.6-block.git] / drivers / gpu / drm / drm_edid.c
CommitLineData
f453ba04
DA		 1/*
2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
61e57a8d 5 * Copyright 2010 Red Hat, Inc.
f453ba04
DA		 6 *
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
8 * FB layer.
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 */
9c79edec 30
10a85120 31#include <linux/hdmi.h>
f453ba04 32#include <linux/i2c.h>
9c79edec 33#include <linux/kernel.h>
47819ba2 34#include <linux/module.h>
9c79edec 35#include <linux/slab.h>
5cb8eaa2 36#include <linux/vga_switcheroo.h>
9c79edec
JN		 37
38#include <drm/drm_displayid.h>
39#include <drm/drm_drv.h>
760285e7 40#include <drm/drm_edid.h>
9338203c 41#include <drm/drm_encoder.h>
9c79edec 42#include <drm/drm_print.h>
62c58af3 43#include <drm/drm_scdc_helper.h>
f453ba04 44
969218fe
TI		 45#include "drm_crtc_internal.h"
46
13931579
AJ		 47#define version_greater(edid, maj, min) \
48 (((edid)->version > (maj)) || \
49 ((edid)->version == (maj) && (edid)->revision > (min)))
f453ba04 50
d1ff6409
AJ		 51#define EDID_EST_TIMINGS 16
52#define EDID_STD_TIMINGS 8
53#define EDID_DETAILED_TIMINGS 4
f453ba04
DA		 54
55/*
56 * EDID blocks out in the wild have a variety of bugs, try to collect
57 * them here (note that userspace may work around broken monitors first,
58 * but fixes should make their way here so that the kernel "just works"
59 * on as many displays as possible).
60 */
61
62/* First detailed mode wrong, use largest 60Hz mode */
63#define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
64/* Reported 135MHz pixel clock is too high, needs adjustment */
65#define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
66/* Prefer the largest mode at 75 Hz */
67#define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
68/* Detail timing is in cm not mm */
69#define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
70/* Detailed timing descriptors have bogus size values, so just take the
71 * maximum size and use that.
72 */
73#define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
f453ba04
DA		 74/* use +hsync +vsync for detailed mode */
75#define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
bc42aabc
AJ		 76/* Force reduced-blanking timings for detailed modes */
77#define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
49d45a31
RM		 78/* Force 8bpc */
79#define EDID_QUIRK_FORCE_8BPC (1 << 8)
bc5b9641
MK		 80/* Force 12bpc */
81#define EDID_QUIRK_FORCE_12BPC (1 << 9)
e10aec65
MK		 82/* Force 6bpc */
83#define EDID_QUIRK_FORCE_6BPC (1 << 10)
e345da82
MK		 84/* Force 10bpc */
85#define EDID_QUIRK_FORCE_10BPC (1 << 11)
66660d4c
DA		 86/* Non desktop display (i.e. HMD) */
87#define EDID_QUIRK_NON_DESKTOP (1 << 12)
3c537889 88
13931579
AJ		 89struct detailed_mode_closure {
90 struct drm_connector *connector;
91 struct edid *edid;
92 bool preferred;
93 u32 quirks;
94 int modes;
95};
f453ba04 96
5c61259e
ZY		 97#define LEVEL_DMT 0
98#define LEVEL_GTF 1
7a374350
AJ		 99#define LEVEL_GTF2 2
100#define LEVEL_CVT 3
5c61259e 101
23c4cfbd 102static const struct edid_quirk {
c51a3fd6 103 char vendor[4];
f453ba04
DA		 104 int product_id;
105 u32 quirks;
106} edid_quirk_list[] = {
107 /* Acer AL1706 */
108 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
109 /* Acer F51 */
110 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
f453ba04 111
e10aec65
MK		 112 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
113 { "AEO", 0, EDID_QUIRK_FORCE_6BPC },
114
0711a43b
KHF		 115 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
116 { "BOE", 0x78b, EDID_QUIRK_FORCE_6BPC },
117
06998a75
KHF		 118 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
119 { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC },
120
25da7504
KHF		 121 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
122 { "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC },
123
922dceff
LS		 124 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
125 { "BOE", 0x0771, EDID_QUIRK_FORCE_6BPC },
126
f453ba04
DA		 127 /* Belinea 10 15 55 */
128 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
129 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
130
131 /* Envision Peripherals, Inc. EN-7100e */
132 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
ba1163de
AJ		 133 /* Envision EN2028 */
134 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
f453ba04
DA		 135
136 /* Funai Electronics PM36B */
137 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
138 EDID_QUIRK_DETAILED_IN_CM },
139
e345da82
MK		 140 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
141 { "LGD", 764, EDID_QUIRK_FORCE_10BPC },
142
f453ba04
DA		 143 /* LG Philips LCD LP154W01-A5 */
144 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
145 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
146
f453ba04
DA		 147 /* Samsung SyncMaster 205BW. Note: irony */
148 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
149 /* Samsung SyncMaster 22[5-6]BW */
150 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
151 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
bc42aabc 152
bc5b9641
MK		 153 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
154 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
155
bc42aabc
AJ		 156 /* ViewSonic VA2026w */
157 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
118bdbd8
AD		 158
159 /* Medion MD 30217 PG */
160 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
49d45a31 161
11bcf5f7
KHF		 162 /* Lenovo G50 */
163 { "SDC", 18514, EDID_QUIRK_FORCE_6BPC },
164
49d45a31
RM		 165 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
166 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
36fc5797
TV		 167
168 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
169 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC },
acb1d8ee 170
30d62d44
AR		 171 /* Valve Index Headset */
172 { "VLV", 0x91a8, EDID_QUIRK_NON_DESKTOP },
173 { "VLV", 0x91b0, EDID_QUIRK_NON_DESKTOP },
174 { "VLV", 0x91b1, EDID_QUIRK_NON_DESKTOP },
175 { "VLV", 0x91b2, EDID_QUIRK_NON_DESKTOP },
176 { "VLV", 0x91b3, EDID_QUIRK_NON_DESKTOP },
177 { "VLV", 0x91b4, EDID_QUIRK_NON_DESKTOP },
178 { "VLV", 0x91b5, EDID_QUIRK_NON_DESKTOP },
179 { "VLV", 0x91b6, EDID_QUIRK_NON_DESKTOP },
180 { "VLV", 0x91b7, EDID_QUIRK_NON_DESKTOP },
181 { "VLV", 0x91b8, EDID_QUIRK_NON_DESKTOP },
182 { "VLV", 0x91b9, EDID_QUIRK_NON_DESKTOP },
183 { "VLV", 0x91ba, EDID_QUIRK_NON_DESKTOP },
184 { "VLV", 0x91bb, EDID_QUIRK_NON_DESKTOP },
185 { "VLV", 0x91bc, EDID_QUIRK_NON_DESKTOP },
186 { "VLV", 0x91bd, EDID_QUIRK_NON_DESKTOP },
187 { "VLV", 0x91be, EDID_QUIRK_NON_DESKTOP },
188 { "VLV", 0x91bf, EDID_QUIRK_NON_DESKTOP },
189
6931317c 190 /* HTC Vive and Vive Pro VR Headsets */
acb1d8ee 191 { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP },
6931317c 192 { "HVR", 0xaa02, EDID_QUIRK_NON_DESKTOP },
b3b12ea3
PZ		 193
194 /* Oculus Rift DK1, DK2, and CV1 VR Headsets */
195 { "OVR", 0x0001, EDID_QUIRK_NON_DESKTOP },
196 { "OVR", 0x0003, EDID_QUIRK_NON_DESKTOP },
197 { "OVR", 0x0004, EDID_QUIRK_NON_DESKTOP },
90eda8fc
PZ		 198
199 /* Windows Mixed Reality Headsets */
200 { "ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP },
201 { "HPN", 0x3515, EDID_QUIRK_NON_DESKTOP },
202 { "LEN", 0x0408, EDID_QUIRK_NON_DESKTOP },
203 { "LEN", 0xb800, EDID_QUIRK_NON_DESKTOP },
204 { "FUJ", 0x1970, EDID_QUIRK_NON_DESKTOP },
205 { "DEL", 0x7fce, EDID_QUIRK_NON_DESKTOP },
206 { "SEC", 0x144a, EDID_QUIRK_NON_DESKTOP },
207 { "AUS", 0xc102, EDID_QUIRK_NON_DESKTOP },
ccffc9eb
PZ		 208
209 /* Sony PlayStation VR Headset */
210 { "SNY", 0x0704, EDID_QUIRK_NON_DESKTOP },
29054230
RP		 211
212 /* Sensics VR Headsets */
213 { "SEN", 0x1019, EDID_QUIRK_NON_DESKTOP },
214
215 /* OSVR HDK and HDK2 VR Headsets */
216 { "SVR", 0x1019, EDID_QUIRK_NON_DESKTOP },
f453ba04
DA		 217};
218
a6b21831
TR		 219/*
220 * Autogenerated from the DMT spec.
221 * This table is copied from xfree86/modes/xf86EdidModes.c.
222 */
223static const struct drm_display_mode drm_dmt_modes[] = {
24b856b1 224 /* 0x01 - 640x350@85Hz */
a6b21831
TR		 225 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
226 736, 832, 0, 350, 382, 385, 445, 0,
227 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 228 /* 0x02 - 640x400@85Hz */
a6b21831
TR		 229 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
230 736, 832, 0, 400, 401, 404, 445, 0,
231 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 232 /* 0x03 - 720x400@85Hz */
a6b21831
TR		 233 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
234 828, 936, 0, 400, 401, 404, 446, 0,
235 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 236 /* 0x04 - 640x480@60Hz */
a6b21831 237 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
fcf22d05 238 752, 800, 0, 480, 490, 492, 525, 0,
a6b21831 239 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 240 /* 0x05 - 640x480@72Hz */
a6b21831
TR		 241 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
242 704, 832, 0, 480, 489, 492, 520, 0,
243 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 244 /* 0x06 - 640x480@75Hz */
a6b21831
TR		 245 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
246 720, 840, 0, 480, 481, 484, 500, 0,
247 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 248 /* 0x07 - 640x480@85Hz */
a6b21831
TR		 249 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
250 752, 832, 0, 480, 481, 484, 509, 0,
251 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 252 /* 0x08 - 800x600@56Hz */
a6b21831
TR		 253 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
254 896, 1024, 0, 600, 601, 603, 625, 0,
255 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 256 /* 0x09 - 800x600@60Hz */
a6b21831
TR		 257 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
258 968, 1056, 0, 600, 601, 605, 628, 0,
259 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 260 /* 0x0a - 800x600@72Hz */
a6b21831
TR		 261 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
262 976, 1040, 0, 600, 637, 643, 666, 0,
263 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 264 /* 0x0b - 800x600@75Hz */
a6b21831
TR		 265 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
266 896, 1056, 0, 600, 601, 604, 625, 0,
267 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 268 /* 0x0c - 800x600@85Hz */
a6b21831
TR		 269 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
270 896, 1048, 0, 600, 601, 604, 631, 0,
271 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 272 /* 0x0d - 800x600@120Hz RB */
a6b21831
TR		 273 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
274 880, 960, 0, 600, 603, 607, 636, 0,
275 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 276 /* 0x0e - 848x480@60Hz */
a6b21831
TR		 277 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
278 976, 1088, 0, 480, 486, 494, 517, 0,
279 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 280 /* 0x0f - 1024x768@43Hz, interlace */
a6b21831 281 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
735b100f 282 1208, 1264, 0, 768, 768, 776, 817, 0,
a6b21831 283 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
fcf22d05 284 DRM_MODE_FLAG_INTERLACE) },
24b856b1 285 /* 0x10 - 1024x768@60Hz */
a6b21831
TR		 286 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
287 1184, 1344, 0, 768, 771, 777, 806, 0,
288 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 289 /* 0x11 - 1024x768@70Hz */
a6b21831
TR		 290 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
291 1184, 1328, 0, 768, 771, 777, 806, 0,
292 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 293 /* 0x12 - 1024x768@75Hz */
a6b21831
TR		 294 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
295 1136, 1312, 0, 768, 769, 772, 800, 0,
296 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 297 /* 0x13 - 1024x768@85Hz */
a6b21831
TR		 298 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
299 1168, 1376, 0, 768, 769, 772, 808, 0,
300 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 301 /* 0x14 - 1024x768@120Hz RB */
a6b21831
TR		 302 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
303 1104, 1184, 0, 768, 771, 775, 813, 0,
304 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 305 /* 0x15 - 1152x864@75Hz */
a6b21831
TR		 306 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
307 1344, 1600, 0, 864, 865, 868, 900, 0,
308 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
bfcd74d2
VS		 309 /* 0x55 - 1280x720@60Hz */
310 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
311 1430, 1650, 0, 720, 725, 730, 750, 0,
312 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 313 /* 0x16 - 1280x768@60Hz RB */
a6b21831
TR		 314 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
315 1360, 1440, 0, 768, 771, 778, 790, 0,
316 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 317 /* 0x17 - 1280x768@60Hz */
a6b21831
TR		 318 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
319 1472, 1664, 0, 768, 771, 778, 798, 0,
320 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 321 /* 0x18 - 1280x768@75Hz */
a6b21831
TR		 322 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
323 1488, 1696, 0, 768, 771, 778, 805, 0,
fcf22d05 324 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 325 /* 0x19 - 1280x768@85Hz */
a6b21831
TR		 326 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
327 1496, 1712, 0, 768, 771, 778, 809, 0,
328 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 329 /* 0x1a - 1280x768@120Hz RB */
a6b21831
TR		 330 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
331 1360, 1440, 0, 768, 771, 778, 813, 0,
332 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 333 /* 0x1b - 1280x800@60Hz RB */
a6b21831
TR		 334 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
335 1360, 1440, 0, 800, 803, 809, 823, 0,
336 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 337 /* 0x1c - 1280x800@60Hz */
a6b21831
TR		 338 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
339 1480, 1680, 0, 800, 803, 809, 831, 0,
fcf22d05 340 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 341 /* 0x1d - 1280x800@75Hz */
a6b21831
TR		 342 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
343 1488, 1696, 0, 800, 803, 809, 838, 0,
344 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 345 /* 0x1e - 1280x800@85Hz */
a6b21831
TR		 346 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
347 1496, 1712, 0, 800, 803, 809, 843, 0,
348 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 349 /* 0x1f - 1280x800@120Hz RB */
a6b21831
TR		 350 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
351 1360, 1440, 0, 800, 803, 809, 847, 0,
352 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 353 /* 0x20 - 1280x960@60Hz */
a6b21831
TR		 354 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
355 1488, 1800, 0, 960, 961, 964, 1000, 0,
356 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 357 /* 0x21 - 1280x960@85Hz */
a6b21831
TR		 358 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
359 1504, 1728, 0, 960, 961, 964, 1011, 0,
360 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 361 /* 0x22 - 1280x960@120Hz RB */
a6b21831
TR		 362 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
363 1360, 1440, 0, 960, 963, 967, 1017, 0,
364 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 365 /* 0x23 - 1280x1024@60Hz */
a6b21831
TR		 366 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
367 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 369 /* 0x24 - 1280x1024@75Hz */
a6b21831
TR		 370 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
371 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
372 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 373 /* 0x25 - 1280x1024@85Hz */
a6b21831
TR		 374 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
375 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
376 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 377 /* 0x26 - 1280x1024@120Hz RB */
a6b21831
TR		 378 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
379 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
380 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 381 /* 0x27 - 1360x768@60Hz */
a6b21831
TR		 382 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
383 1536, 1792, 0, 768, 771, 777, 795, 0,
384 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 385 /* 0x28 - 1360x768@120Hz RB */
a6b21831
TR		 386 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
387 1440, 1520, 0, 768, 771, 776, 813, 0,
388 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 389 /* 0x51 - 1366x768@60Hz */
390 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
391 1579, 1792, 0, 768, 771, 774, 798, 0,
392 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
393 /* 0x56 - 1366x768@60Hz */
394 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
395 1436, 1500, 0, 768, 769, 772, 800, 0,
396 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 397 /* 0x29 - 1400x1050@60Hz RB */
a6b21831
TR		 398 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
399 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
400 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 401 /* 0x2a - 1400x1050@60Hz */
a6b21831
TR		 402 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
403 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
404 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 405 /* 0x2b - 1400x1050@75Hz */
a6b21831
TR		 406 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
407 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
408 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 409 /* 0x2c - 1400x1050@85Hz */
a6b21831
TR		 410 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
411 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
412 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 413 /* 0x2d - 1400x1050@120Hz RB */
a6b21831
TR		 414 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
415 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
416 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 417 /* 0x2e - 1440x900@60Hz RB */
a6b21831
TR		 418 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
419 1520, 1600, 0, 900, 903, 909, 926, 0,
420 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 421 /* 0x2f - 1440x900@60Hz */
a6b21831
TR		 422 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
423 1672, 1904, 0, 900, 903, 909, 934, 0,
424 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 425 /* 0x30 - 1440x900@75Hz */
a6b21831
TR		 426 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
427 1688, 1936, 0, 900, 903, 909, 942, 0,
428 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 429 /* 0x31 - 1440x900@85Hz */
a6b21831
TR		 430 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
431 1696, 1952, 0, 900, 903, 909, 948, 0,
432 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 433 /* 0x32 - 1440x900@120Hz RB */
a6b21831
TR		 434 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
435 1520, 1600, 0, 900, 903, 909, 953, 0,
436 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 437 /* 0x53 - 1600x900@60Hz */
438 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
439 1704, 1800, 0, 900, 901, 904, 1000, 0,
440 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 441 /* 0x33 - 1600x1200@60Hz */
a6b21831
TR		 442 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
443 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
444 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 445 /* 0x34 - 1600x1200@65Hz */
a6b21831
TR		 446 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
447 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
448 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 449 /* 0x35 - 1600x1200@70Hz */
a6b21831
TR		 450 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
451 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
452 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 453 /* 0x36 - 1600x1200@75Hz */
a6b21831
TR		 454 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
455 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
456 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 457 /* 0x37 - 1600x1200@85Hz */
a6b21831
TR		 458 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
459 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
460 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 461 /* 0x38 - 1600x1200@120Hz RB */
a6b21831
TR		 462 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
463 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
464 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 465 /* 0x39 - 1680x1050@60Hz RB */
a6b21831
TR		 466 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
467 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
468 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 469 /* 0x3a - 1680x1050@60Hz */
a6b21831
TR		 470 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
471 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
472 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 473 /* 0x3b - 1680x1050@75Hz */
a6b21831
TR		 474 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
475 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
476 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 477 /* 0x3c - 1680x1050@85Hz */
a6b21831
TR		 478 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
479 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
480 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 481 /* 0x3d - 1680x1050@120Hz RB */
a6b21831
TR		 482 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
483 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
484 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 485 /* 0x3e - 1792x1344@60Hz */
a6b21831
TR		 486 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
487 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
488 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 489 /* 0x3f - 1792x1344@75Hz */
a6b21831
TR		 490 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
491 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
492 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 493 /* 0x40 - 1792x1344@120Hz RB */
a6b21831
TR		 494 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
495 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
496 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 497 /* 0x41 - 1856x1392@60Hz */
a6b21831
TR		 498 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
499 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
500 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 501 /* 0x42 - 1856x1392@75Hz */
a6b21831 502 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
fcf22d05 503 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
a6b21831 504 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 505 /* 0x43 - 1856x1392@120Hz RB */
a6b21831
TR		 506 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
507 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
508 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 509 /* 0x52 - 1920x1080@60Hz */
510 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
511 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
512 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 513 /* 0x44 - 1920x1200@60Hz RB */
a6b21831
TR		 514 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
515 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
516 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 517 /* 0x45 - 1920x1200@60Hz */
a6b21831
TR		 518 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
519 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
520 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 521 /* 0x46 - 1920x1200@75Hz */
a6b21831
TR		 522 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
523 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
524 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 525 /* 0x47 - 1920x1200@85Hz */
a6b21831
TR		 526 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
527 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
528 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 529 /* 0x48 - 1920x1200@120Hz RB */
a6b21831
TR		 530 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
531 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
532 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 533 /* 0x49 - 1920x1440@60Hz */
a6b21831
TR		 534 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
535 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
536 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 537 /* 0x4a - 1920x1440@75Hz */
a6b21831
TR		 538 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
539 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
540 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 541 /* 0x4b - 1920x1440@120Hz RB */
a6b21831
TR		 542 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
543 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
544 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 545 /* 0x54 - 2048x1152@60Hz */
546 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
547 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
548 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 549 /* 0x4c - 2560x1600@60Hz RB */
a6b21831
TR		 550 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
551 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
552 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 553 /* 0x4d - 2560x1600@60Hz */
a6b21831
TR		 554 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
555 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
556 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 557 /* 0x4e - 2560x1600@75Hz */
a6b21831
TR		 558 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
559 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
560 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 561 /* 0x4f - 2560x1600@85Hz */
a6b21831
TR		 562 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
563 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
564 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 565 /* 0x50 - 2560x1600@120Hz RB */
a6b21831
TR		 566 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
567 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
568 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 569 /* 0x57 - 4096x2160@60Hz RB */
570 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
571 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
572 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
573 /* 0x58 - 4096x2160@59.94Hz RB */
574 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
575 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
576 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
a6b21831
TR		 577};
578
e7bfa5c4
VS		 579/*
580 * These more or less come from the DMT spec. The 720x400 modes are
581 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
582 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
583 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
584 * mode.
585 *
586 * The DMT modes have been fact-checked; the rest are mild guesses.
587 */
a6b21831
TR		 588static const struct drm_display_mode edid_est_modes[] = {
589 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
590 968, 1056, 0, 600, 601, 605, 628, 0,
591 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
592 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
593 896, 1024, 0, 600, 601, 603, 625, 0,
594 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
595 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
596 720, 840, 0, 480, 481, 484, 500, 0,
597 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
598 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
87707cfd 599 704, 832, 0, 480, 489, 492, 520, 0,
a6b21831
TR		 600 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
601 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
602 768, 864, 0, 480, 483, 486, 525, 0,
603 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
87707cfd 604 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
a6b21831
TR		 605 752, 800, 0, 480, 490, 492, 525, 0,
606 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
607 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
608 846, 900, 0, 400, 421, 423, 449, 0,
609 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
610 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
611 846, 900, 0, 400, 412, 414, 449, 0,
612 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
613 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
614 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
615 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
87707cfd 616 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
a6b21831
TR		 617 1136, 1312, 0, 768, 769, 772, 800, 0,
618 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
619 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
620 1184, 1328, 0, 768, 771, 777, 806, 0,
621 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
622 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
623 1184, 1344, 0, 768, 771, 777, 806, 0,
624 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
625 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
626 1208, 1264, 0, 768, 768, 776, 817, 0,
627 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
628 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
629 928, 1152, 0, 624, 625, 628, 667, 0,
630 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
631 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
632 896, 1056, 0, 600, 601, 604, 625, 0,
633 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
634 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
635 976, 1040, 0, 600, 637, 643, 666, 0,
636 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
637 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
638 1344, 1600, 0, 864, 865, 868, 900, 0,
639 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
640};
641
642struct minimode {
643 short w;
644 short h;
645 short r;
646 short rb;
647};
648
649static const struct minimode est3_modes[] = {
650 /* byte 6 */
651 { 640, 350, 85, 0 },
652 { 640, 400, 85, 0 },
653 { 720, 400, 85, 0 },
654 { 640, 480, 85, 0 },
655 { 848, 480, 60, 0 },
656 { 800, 600, 85, 0 },
657 { 1024, 768, 85, 0 },
658 { 1152, 864, 75, 0 },
659 /* byte 7 */
660 { 1280, 768, 60, 1 },
661 { 1280, 768, 60, 0 },
662 { 1280, 768, 75, 0 },
663 { 1280, 768, 85, 0 },
664 { 1280, 960, 60, 0 },
665 { 1280, 960, 85, 0 },
666 { 1280, 1024, 60, 0 },
667 { 1280, 1024, 85, 0 },
668 /* byte 8 */
669 { 1360, 768, 60, 0 },
670 { 1440, 900, 60, 1 },
671 { 1440, 900, 60, 0 },
672 { 1440, 900, 75, 0 },
673 { 1440, 900, 85, 0 },
674 { 1400, 1050, 60, 1 },
675 { 1400, 1050, 60, 0 },
676 { 1400, 1050, 75, 0 },
677 /* byte 9 */
678 { 1400, 1050, 85, 0 },
679 { 1680, 1050, 60, 1 },
680 { 1680, 1050, 60, 0 },
681 { 1680, 1050, 75, 0 },
682 { 1680, 1050, 85, 0 },
683 { 1600, 1200, 60, 0 },
684 { 1600, 1200, 65, 0 },
685 { 1600, 1200, 70, 0 },
686 /* byte 10 */
687 { 1600, 1200, 75, 0 },
688 { 1600, 1200, 85, 0 },
689 { 1792, 1344, 60, 0 },
c068b32a 690 { 1792, 1344, 75, 0 },
a6b21831
TR		 691 { 1856, 1392, 60, 0 },
692 { 1856, 1392, 75, 0 },
693 { 1920, 1200, 60, 1 },
694 { 1920, 1200, 60, 0 },
695 /* byte 11 */
696 { 1920, 1200, 75, 0 },
697 { 1920, 1200, 85, 0 },
698 { 1920, 1440, 60, 0 },
699 { 1920, 1440, 75, 0 },
700};
701
702static const struct minimode extra_modes[] = {
703 { 1024, 576, 60, 0 },
704 { 1366, 768, 60, 0 },
705 { 1600, 900, 60, 0 },
706 { 1680, 945, 60, 0 },
707 { 1920, 1080, 60, 0 },
708 { 2048, 1152, 60, 0 },
709 { 2048, 1536, 60, 0 },
710};
711
712/*
7befe621 713 * From CEA/CTA-861 spec.
d9278b4c 714 *
7befe621 715 * Do not access directly, instead always use cea_mode_for_vic().
a6b21831 716 */
8c1b2bd9 717static const struct drm_display_mode edid_cea_modes_1[] = {
78691960 718 /* 1 - 640x480@60Hz 4:3 */
a6b21831
TR		 719 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
720 752, 800, 0, 480, 490, 492, 525, 0,
ee7925bb 721 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 722 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 723 /* 2 - 720x480@60Hz 4:3 */
a6b21831
TR		 724 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
725 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 726 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 727 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 728 /* 3 - 720x480@60Hz 16:9 */
a6b21831
TR		 729 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
730 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 731 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 732 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 733 /* 4 - 1280x720@60Hz 16:9 */
a6b21831
TR		 734 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
735 1430, 1650, 0, 720, 725, 730, 750, 0,
ee7925bb 736 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 737 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 738 /* 5 - 1920x1080i@60Hz 16:9 */
a6b21831
TR		 739 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
740 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
741 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 742 DRM_MODE_FLAG_INTERLACE),
985e5dc2 743 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 744 /* 6 - 720(1440)x480i@60Hz 4:3 */
fb01d280
CT		 745 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
746 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 747 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 748 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 749 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 750 /* 7 - 720(1440)x480i@60Hz 16:9 */
fb01d280
CT		 751 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
752 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 753 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 754 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 755 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 756 /* 8 - 720(1440)x240@60Hz 4:3 */
fb01d280
CT		 757 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
758 801, 858, 0, 240, 244, 247, 262, 0,
a6b21831 759 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 760 DRM_MODE_FLAG_DBLCLK),
985e5dc2 761 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 762 /* 9 - 720(1440)x240@60Hz 16:9 */
fb01d280
CT		 763 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
764 801, 858, 0, 240, 244, 247, 262, 0,
a6b21831 765 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 766 DRM_MODE_FLAG_DBLCLK),
985e5dc2 767 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 768 /* 10 - 2880x480i@60Hz 4:3 */
a6b21831
TR		 769 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
770 3204, 3432, 0, 480, 488, 494, 525, 0,
771 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 772 DRM_MODE_FLAG_INTERLACE),
985e5dc2 773 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 774 /* 11 - 2880x480i@60Hz 16:9 */
a6b21831
TR		 775 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
776 3204, 3432, 0, 480, 488, 494, 525, 0,
777 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 778 DRM_MODE_FLAG_INTERLACE),
985e5dc2 779 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 780 /* 12 - 2880x240@60Hz 4:3 */
a6b21831
TR		 781 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
782 3204, 3432, 0, 240, 244, 247, 262, 0,
ee7925bb 783 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 784 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 785 /* 13 - 2880x240@60Hz 16:9 */
a6b21831
TR		 786 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
787 3204, 3432, 0, 240, 244, 247, 262, 0,
ee7925bb 788 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 789 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 790 /* 14 - 1440x480@60Hz 4:3 */
a6b21831
TR		 791 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
792 1596, 1716, 0, 480, 489, 495, 525, 0,
ee7925bb 793 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 794 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 795 /* 15 - 1440x480@60Hz 16:9 */
a6b21831
TR		 796 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
797 1596, 1716, 0, 480, 489, 495, 525, 0,
ee7925bb 798 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 799 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 800 /* 16 - 1920x1080@60Hz 16:9 */
a6b21831
TR		 801 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
802 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 803 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 804 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 805 /* 17 - 720x576@50Hz 4:3 */
a6b21831
TR		 806 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
807 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 808 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 809 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 810 /* 18 - 720x576@50Hz 16:9 */
a6b21831
TR		 811 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
812 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 813 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 814 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 815 /* 19 - 1280x720@50Hz 16:9 */
a6b21831
TR		 816 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
817 1760, 1980, 0, 720, 725, 730, 750, 0,
ee7925bb 818 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 819 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 820 /* 20 - 1920x1080i@50Hz 16:9 */
a6b21831
TR		 821 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
822 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
823 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 824 DRM_MODE_FLAG_INTERLACE),
985e5dc2 825 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 826 /* 21 - 720(1440)x576i@50Hz 4:3 */
fb01d280
CT		 827 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
828 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 829 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 830 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 831 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 832 /* 22 - 720(1440)x576i@50Hz 16:9 */
fb01d280
CT		 833 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
834 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 835 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 836 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 837 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 838 /* 23 - 720(1440)x288@50Hz 4:3 */
fb01d280
CT		 839 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
840 795, 864, 0, 288, 290, 293, 312, 0,
a6b21831 841 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 842 DRM_MODE_FLAG_DBLCLK),
985e5dc2 843 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 844 /* 24 - 720(1440)x288@50Hz 16:9 */
fb01d280
CT		 845 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
846 795, 864, 0, 288, 290, 293, 312, 0,
a6b21831 847 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 848 DRM_MODE_FLAG_DBLCLK),
985e5dc2 849 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 850 /* 25 - 2880x576i@50Hz 4:3 */
a6b21831
TR		 851 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
852 3180, 3456, 0, 576, 580, 586, 625, 0,
853 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 854 DRM_MODE_FLAG_INTERLACE),
985e5dc2 855 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 856 /* 26 - 2880x576i@50Hz 16:9 */
a6b21831
TR		 857 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
858 3180, 3456, 0, 576, 580, 586, 625, 0,
859 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 860 DRM_MODE_FLAG_INTERLACE),
985e5dc2 861 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 862 /* 27 - 2880x288@50Hz 4:3 */
a6b21831
TR		 863 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
864 3180, 3456, 0, 288, 290, 293, 312, 0,
ee7925bb 865 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 866 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 867 /* 28 - 2880x288@50Hz 16:9 */
a6b21831
TR		 868 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
869 3180, 3456, 0, 288, 290, 293, 312, 0,
ee7925bb 870 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 871 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 872 /* 29 - 1440x576@50Hz 4:3 */
a6b21831
TR		 873 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
874 1592, 1728, 0, 576, 581, 586, 625, 0,
ee7925bb 875 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 876 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 877 /* 30 - 1440x576@50Hz 16:9 */
a6b21831
TR		 878 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
879 1592, 1728, 0, 576, 581, 586, 625, 0,
ee7925bb 880 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 881 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 882 /* 31 - 1920x1080@50Hz 16:9 */
a6b21831
TR		 883 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
884 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 885 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 886 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 887 /* 32 - 1920x1080@24Hz 16:9 */
a6b21831
TR		 888 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
889 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 890 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 891 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 892 /* 33 - 1920x1080@25Hz 16:9 */
a6b21831
TR		 893 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
894 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 895 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 896 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 897 /* 34 - 1920x1080@30Hz 16:9 */
a6b21831
TR		 898 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
899 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 900 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 901 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 902 /* 35 - 2880x480@60Hz 4:3 */
a6b21831
TR		 903 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
904 3192, 3432, 0, 480, 489, 495, 525, 0,
ee7925bb 905 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 906 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 907 /* 36 - 2880x480@60Hz 16:9 */
a6b21831
TR		 908 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
909 3192, 3432, 0, 480, 489, 495, 525, 0,
ee7925bb 910 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 911 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 912 /* 37 - 2880x576@50Hz 4:3 */
a6b21831
TR		 913 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
914 3184, 3456, 0, 576, 581, 586, 625, 0,
ee7925bb 915 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 916 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 917 /* 38 - 2880x576@50Hz 16:9 */
a6b21831
TR		 918 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
919 3184, 3456, 0, 576, 581, 586, 625, 0,
ee7925bb 920 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 921 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 922 /* 39 - 1920x1080i@50Hz 16:9 */
a6b21831
TR		 923 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
924 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
925 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 926 DRM_MODE_FLAG_INTERLACE),
985e5dc2 927 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 928 /* 40 - 1920x1080i@100Hz 16:9 */
a6b21831
TR		 929 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
930 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
931 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 932 DRM_MODE_FLAG_INTERLACE),
985e5dc2 933 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 934 /* 41 - 1280x720@100Hz 16:9 */
a6b21831
TR		 935 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
936 1760, 1980, 0, 720, 725, 730, 750, 0,
ee7925bb 937 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 938 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 939 /* 42 - 720x576@100Hz 4:3 */
a6b21831
TR		 940 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
941 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 942 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 943 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 944 /* 43 - 720x576@100Hz 16:9 */
a6b21831
TR		 945 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
946 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 947 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 948 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 949 /* 44 - 720(1440)x576i@100Hz 4:3 */
fb01d280
CT		 950 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
951 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 952 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 953 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 954 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 955 /* 45 - 720(1440)x576i@100Hz 16:9 */
fb01d280
CT		 956 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
957 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 958 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 959 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 960 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 961 /* 46 - 1920x1080i@120Hz 16:9 */
a6b21831
TR		 962 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
963 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
964 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 965 DRM_MODE_FLAG_INTERLACE),
985e5dc2 966 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 967 /* 47 - 1280x720@120Hz 16:9 */
a6b21831
TR		 968 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
969 1430, 1650, 0, 720, 725, 730, 750, 0,
ee7925bb 970 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 971 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 972 /* 48 - 720x480@120Hz 4:3 */
a6b21831
TR		 973 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
974 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 975 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 976 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 977 /* 49 - 720x480@120Hz 16:9 */
a6b21831
TR		 978 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
979 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 980 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 981 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 982 /* 50 - 720(1440)x480i@120Hz 4:3 */
fb01d280
CT		 983 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
984 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 985 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 986 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 987 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 988 /* 51 - 720(1440)x480i@120Hz 16:9 */
fb01d280
CT		 989 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
990 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 991 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 992 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 993 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 994 /* 52 - 720x576@200Hz 4:3 */
a6b21831
TR		 995 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
996 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 997 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 998 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 999 /* 53 - 720x576@200Hz 16:9 */
a6b21831
TR		 1000 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1001 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 1002 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 1003 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1004 /* 54 - 720(1440)x576i@200Hz 4:3 */
fb01d280
CT		 1005 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1006 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 1007 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1008 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 1009 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1010 /* 55 - 720(1440)x576i@200Hz 16:9 */
fb01d280
CT		 1011 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1012 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 1013 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1014 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 1015 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1016 /* 56 - 720x480@240Hz 4:3 */
a6b21831
TR		 1017 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1018 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 1019 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 1020 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1021 /* 57 - 720x480@240Hz 16:9 */
a6b21831
TR		 1022 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1023 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 1024 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 1025 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1026 /* 58 - 720(1440)x480i@240Hz 4:3 */
fb01d280
CT		 1027 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1028 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 1029 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1030 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 1031 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1032 /* 59 - 720(1440)x480i@240Hz 16:9 */
fb01d280
CT		 1033 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1034 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 1035 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1036 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 1037 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1038 /* 60 - 1280x720@24Hz 16:9 */
a6b21831
TR		 1039 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1040 3080, 3300, 0, 720, 725, 730, 750, 0,
ee7925bb 1041 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 1042 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1043 /* 61 - 1280x720@25Hz 16:9 */
a6b21831
TR		 1044 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1045 3740, 3960, 0, 720, 725, 730, 750, 0,
ee7925bb 1046 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 1047 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1048 /* 62 - 1280x720@30Hz 16:9 */
a6b21831
TR		 1049 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1050 3080, 3300, 0, 720, 725, 730, 750, 0,
ee7925bb 1051 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 1052 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1053 /* 63 - 1920x1080@120Hz 16:9 */
a6b21831
TR		 1054 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1055 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 1056 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
78691960
VS		 1057 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1058 /* 64 - 1920x1080@100Hz 16:9 */
a6b21831 1059 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
8f0e4907 1060 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 1061 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
78691960
VS		 1062 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1063 /* 65 - 1280x720@24Hz 64:27 */
8ec6e075
SS		 1064 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1065 3080, 3300, 0, 720, 725, 730, 750, 0,
1066 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1067 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1068 /* 66 - 1280x720@25Hz 64:27 */
8ec6e075
SS		 1069 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1070 3740, 3960, 0, 720, 725, 730, 750, 0,
1071 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1072 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1073 /* 67 - 1280x720@30Hz 64:27 */
8ec6e075
SS		 1074 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1075 3080, 3300, 0, 720, 725, 730, 750, 0,
1076 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1077 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1078 /* 68 - 1280x720@50Hz 64:27 */
8ec6e075
SS		 1079 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1080 1760, 1980, 0, 720, 725, 730, 750, 0,
1081 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1082 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1083 /* 69 - 1280x720@60Hz 64:27 */
8ec6e075
SS		 1084 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1085 1430, 1650, 0, 720, 725, 730, 750, 0,
1086 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1087 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1088 /* 70 - 1280x720@100Hz 64:27 */
8ec6e075
SS		 1089 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1090 1760, 1980, 0, 720, 725, 730, 750, 0,
1091 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1092 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1093 /* 71 - 1280x720@120Hz 64:27 */
8ec6e075
SS		 1094 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1095 1430, 1650, 0, 720, 725, 730, 750, 0,
1096 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1097 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1098 /* 72 - 1920x1080@24Hz 64:27 */
8ec6e075
SS		 1099 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1100 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1101 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1102 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1103 /* 73 - 1920x1080@25Hz 64:27 */
8ec6e075
SS		 1104 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1105 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1106 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1107 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1108 /* 74 - 1920x1080@30Hz 64:27 */
8ec6e075
SS		 1109 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1110 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1111 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1112 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1113 /* 75 - 1920x1080@50Hz 64:27 */
8ec6e075
SS		 1114 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1115 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1116 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1117 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1118 /* 76 - 1920x1080@60Hz 64:27 */
8ec6e075
SS		 1119 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1120 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1121 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1122 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1123 /* 77 - 1920x1080@100Hz 64:27 */
8ec6e075
SS		 1124 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1125 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1126 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1127 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1128 /* 78 - 1920x1080@120Hz 64:27 */
8ec6e075
SS		 1129 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1130 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1131 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1132 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1133 /* 79 - 1680x720@24Hz 64:27 */
8ec6e075
SS		 1134 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1135 3080, 3300, 0, 720, 725, 730, 750, 0,
1136 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1137 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1138 /* 80 - 1680x720@25Hz 64:27 */
8ec6e075
SS		 1139 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1140 2948, 3168, 0, 720, 725, 730, 750, 0,
1141 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1142 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1143 /* 81 - 1680x720@30Hz 64:27 */
8ec6e075
SS		 1144 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1145 2420, 2640, 0, 720, 725, 730, 750, 0,
1146 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1147 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1148 /* 82 - 1680x720@50Hz 64:27 */
8ec6e075
SS		 1149 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1150 1980, 2200, 0, 720, 725, 730, 750, 0,
1151 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1152 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1153 /* 83 - 1680x720@60Hz 64:27 */
8ec6e075
SS		 1154 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1155 1980, 2200, 0, 720, 725, 730, 750, 0,
1156 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1157 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1158 /* 84 - 1680x720@100Hz 64:27 */
8ec6e075
SS		 1159 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1160 1780, 2000, 0, 720, 725, 730, 825, 0,
1161 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1162 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1163 /* 85 - 1680x720@120Hz 64:27 */
8ec6e075
SS		 1164 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1165 1780, 2000, 0, 720, 725, 730, 825, 0,
1166 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1167 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1168 /* 86 - 2560x1080@24Hz 64:27 */
8ec6e075
SS		 1169 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1170 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1171 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1172 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1173 /* 87 - 2560x1080@25Hz 64:27 */
8ec6e075
SS		 1174 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1175 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1176 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1177 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1178 /* 88 - 2560x1080@30Hz 64:27 */
8ec6e075
SS		 1179 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1180 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1181 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1182 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1183 /* 89 - 2560x1080@50Hz 64:27 */
8ec6e075
SS		 1184 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1185 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1186 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1187 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1188 /* 90 - 2560x1080@60Hz 64:27 */
8ec6e075
SS		 1189 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1190 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1191 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1192 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1193 /* 91 - 2560x1080@100Hz 64:27 */
8ec6e075
SS		 1194 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1195 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1196 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1197 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1198 /* 92 - 2560x1080@120Hz 64:27 */
8ec6e075
SS		 1199 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1200 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1201 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1202 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1203 /* 93 - 3840x2160@24Hz 16:9 */
8ec6e075
SS		 1204 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1205 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1206 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1207 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1208 /* 94 - 3840x2160@25Hz 16:9 */
8ec6e075
SS		 1209 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1210 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1211 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1212 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1213 /* 95 - 3840x2160@30Hz 16:9 */
8ec6e075
SS		 1214 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1215 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1216 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1217 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1218 /* 96 - 3840x2160@50Hz 16:9 */
8ec6e075
SS		 1219 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1220 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1221 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1222 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1223 /* 97 - 3840x2160@60Hz 16:9 */
8ec6e075
SS		 1224 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1225 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1226 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1227 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1228 /* 98 - 4096x2160@24Hz 256:135 */
8ec6e075
SS		 1229 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1230 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1231 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1232 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1233 /* 99 - 4096x2160@25Hz 256:135 */
8ec6e075
SS		 1234 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1235 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1236 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1237 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1238 /* 100 - 4096x2160@30Hz 256:135 */
8ec6e075
SS		 1239 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1240 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1241 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1242 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1243 /* 101 - 4096x2160@50Hz 256:135 */
8ec6e075
SS		 1244 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1245 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1246 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1247 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1248 /* 102 - 4096x2160@60Hz 256:135 */
8ec6e075
SS		 1249 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1250 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1251 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1252 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1253 /* 103 - 3840x2160@24Hz 64:27 */
8ec6e075
SS		 1254 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1255 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1256 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1257 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1258 /* 104 - 3840x2160@25Hz 64:27 */
8ec6e075
SS		 1259 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1260 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1261 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1262 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1263 /* 105 - 3840x2160@30Hz 64:27 */
8ec6e075
SS		 1264 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1265 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1266 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1267 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1268 /* 106 - 3840x2160@50Hz 64:27 */
8ec6e075
SS		 1269 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1270 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1271 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1272 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1273 /* 107 - 3840x2160@60Hz 64:27 */
8ec6e075
SS		 1274 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1275 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1277 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1278 /* 108 - 1280x720@48Hz 16:9 */
1279 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1280 2280, 2500, 0, 720, 725, 730, 750, 0,
1281 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1282 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1283 /* 109 - 1280x720@48Hz 64:27 */
1284 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1285 2280, 2500, 0, 720, 725, 730, 750, 0,
1286 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1287 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1288 /* 110 - 1680x720@48Hz 64:27 */
1289 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490,
1290 2530, 2750, 0, 720, 725, 730, 750, 0,
1291 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1292 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1293 /* 111 - 1920x1080@48Hz 16:9 */
1294 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1295 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1296 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1297 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1298 /* 112 - 1920x1080@48Hz 64:27 */
1299 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1300 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1301 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1302 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1303 /* 113 - 2560x1080@48Hz 64:27 */
1304 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558,
1305 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1306 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1307 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1308 /* 114 - 3840x2160@48Hz 16:9 */
1309 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1310 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1311 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1312 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1313 /* 115 - 4096x2160@48Hz 256:135 */
1314 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116,
1315 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1316 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1317 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1318 /* 116 - 3840x2160@48Hz 64:27 */
1319 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1320 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1321 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1322 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1323 /* 117 - 3840x2160@100Hz 16:9 */
1324 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1325 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1326 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1327 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1328 /* 118 - 3840x2160@120Hz 16:9 */
1329 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1330 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1331 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1332 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1333 /* 119 - 3840x2160@100Hz 64:27 */
1334 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1335 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1336 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1337 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1338 /* 120 - 3840x2160@120Hz 64:27 */
1339 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1340 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1341 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1342 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1343 /* 121 - 5120x2160@24Hz 64:27 */
1344 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116,
1345 7204, 7500, 0, 2160, 2168, 2178, 2200, 0,
1346 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1347 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1348 /* 122 - 5120x2160@25Hz 64:27 */
1349 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816,
1350 6904, 7200, 0, 2160, 2168, 2178, 2200, 0,
1351 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1352 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1353 /* 123 - 5120x2160@30Hz 64:27 */
1354 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784,
1355 5872, 6000, 0, 2160, 2168, 2178, 2200, 0,
1356 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1357 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1358 /* 124 - 5120x2160@48Hz 64:27 */
1359 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866,
1360 5954, 6250, 0, 2160, 2168, 2178, 2475, 0,
1361 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1362 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1363 /* 125 - 5120x2160@50Hz 64:27 */
1364 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216,
1365 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1366 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1367 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1368 /* 126 - 5120x2160@60Hz 64:27 */
1369 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284,
1370 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1371 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1372 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1373 /* 127 - 5120x2160@100Hz 64:27 */
1374 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216,
1375 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1376 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1377 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
a6b21831
TR		 1378};
1379
f7655d42
VS		 1380/*
1381 * From CEA/CTA-861 spec.
1382 *
1383 * Do not access directly, instead always use cea_mode_for_vic().
1384 */
1385static const struct drm_display_mode edid_cea_modes_193[] = {
1386 /* 193 - 5120x2160@120Hz 64:27 */
1387 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284,
1388 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1390 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1391 /* 194 - 7680x4320@24Hz 16:9 */
1392 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1393 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1394 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1395 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1396 /* 195 - 7680x4320@25Hz 16:9 */
1397 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1398 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1399 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1400 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1401 /* 196 - 7680x4320@30Hz 16:9 */
1402 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1403 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1404 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1405 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1406 /* 197 - 7680x4320@48Hz 16:9 */
1407 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1408 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1409 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1410 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1411 /* 198 - 7680x4320@50Hz 16:9 */
1412 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1413 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1414 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1415 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1416 /* 199 - 7680x4320@60Hz 16:9 */
1417 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1418 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1419 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1420 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1421 /* 200 - 7680x4320@100Hz 16:9 */
1422 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1423 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1424 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1425 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1426 /* 201 - 7680x4320@120Hz 16:9 */
1427 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1428 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1429 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1430 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1431 /* 202 - 7680x4320@24Hz 64:27 */
1432 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1433 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1434 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1435 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1436 /* 203 - 7680x4320@25Hz 64:27 */
1437 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1438 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1439 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1440 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1441 /* 204 - 7680x4320@30Hz 64:27 */
1442 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1443 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1444 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1445 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1446 /* 205 - 7680x4320@48Hz 64:27 */
1447 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1448 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1449 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1450 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1451 /* 206 - 7680x4320@50Hz 64:27 */
1452 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1453 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1454 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1455 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1456 /* 207 - 7680x4320@60Hz 64:27 */
1457 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1458 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1459 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1460 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1461 /* 208 - 7680x4320@100Hz 64:27 */
1462 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1463 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1464 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1465 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1466 /* 209 - 7680x4320@120Hz 64:27 */
1467 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1468 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1470 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1471 /* 210 - 10240x4320@24Hz 64:27 */
1472 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732,
1473 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1474 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1475 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1476 /* 211 - 10240x4320@25Hz 64:27 */
1477 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732,
1478 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1479 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1480 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1481 /* 212 - 10240x4320@30Hz 64:27 */
1482 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528,
1483 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1484 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1485 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1486 /* 213 - 10240x4320@48Hz 64:27 */
1487 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732,
1488 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1489 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1490 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1491 /* 214 - 10240x4320@50Hz 64:27 */
1492 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732,
1493 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1494 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1495 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1496 /* 215 - 10240x4320@60Hz 64:27 */
1497 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528,
1498 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1499 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1500 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1501 /* 216 - 10240x4320@100Hz 64:27 */
1502 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432,
1503 12608, 13200, 0, 4320, 4336, 4356, 4500, 0,
1504 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1505 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1506 /* 217 - 10240x4320@120Hz 64:27 */
1507 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528,
1508 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1509 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1510 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1511 /* 218 - 4096x2160@100Hz 256:135 */
1512 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896,
1513 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1514 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1515 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1516 /* 219 - 4096x2160@120Hz 256:135 */
1517 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184,
1518 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1519 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1520 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1521};
1522
7ebe1963 1523/*
d9278b4c 1524 * HDMI 1.4 4k modes. Index using the VIC.
7ebe1963
LD		 1525 */
1526static const struct drm_display_mode edid_4k_modes[] = {
d9278b4c
JN		 1527 /* 0 - dummy, VICs start at 1 */
1528 { },
7ebe1963
LD		 1529 /* 1 - 3840x2160@30Hz */
1530 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1531 3840, 4016, 4104, 4400, 0,
1532 2160, 2168, 2178, 2250, 0,
1533 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
d2b43473 1534 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
7ebe1963
LD		 1535 /* 2 - 3840x2160@25Hz */
1536 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1537 3840, 4896, 4984, 5280, 0,
1538 2160, 2168, 2178, 2250, 0,
1539 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
d2b43473 1540 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
7ebe1963
LD		 1541 /* 3 - 3840x2160@24Hz */
1542 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1543 3840, 5116, 5204, 5500, 0,
1544 2160, 2168, 2178, 2250, 0,
1545 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
d2b43473 1546 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
7ebe1963
LD		 1547 /* 4 - 4096x2160@24Hz (SMPTE) */
1548 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1549 4096, 5116, 5204, 5500, 0,
1550 2160, 2168, 2178, 2250, 0,
1551 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
d2b43473 1552 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
7ebe1963
LD		 1553};
1554
61e57a8d 1555/*** DDC fetch and block validation ***/
f453ba04 1556
083ae056
AJ		 1557static const u8 edid_header[] = {
1558 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1559};
f453ba04 1560
db6cf833
TR		 1561/**
1562 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1563 * @raw_edid: pointer to raw base EDID block
1564 *
1565 * Sanity check the header of the base EDID block.
1566 *
1567 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
051963d4
TR		 1568 */
1569int drm_edid_header_is_valid(const u8 *raw_edid)
1570{
1571 int i, score = 0;
1572
1573 for (i = 0; i < sizeof(edid_header); i++)
1574 if (raw_edid[i] == edid_header[i])
1575 score++;
1576
1577 return score;
1578}
1579EXPORT_SYMBOL(drm_edid_header_is_valid);
1580
47819ba2
AJ		 1581static int edid_fixup __read_mostly = 6;
1582module_param_named(edid_fixup, edid_fixup, int, 0400);
1583MODULE_PARM_DESC(edid_fixup,
1584 "Minimum number of valid EDID header bytes (0-8, default 6)");
051963d4 1585
40d9b043
DA		 1586static void drm_get_displayid(struct drm_connector *connector,
1587 struct edid *edid);
e28ad544 1588static int validate_displayid(u8 *displayid, int length, int idx);
da9df2f4 1589
c465bbc8
SB		 1590static int drm_edid_block_checksum(const u8 *raw_edid)
1591{
1592 int i;
e11f5bd8
JFZ		 1593 u8 csum = 0, crc = 0;
1594
1595 for (i = 0; i < EDID_LENGTH - 1; i++)
c465bbc8
SB		 1596 csum += raw_edid[i];
1597
e11f5bd8
JFZ		 1598 crc = 0x100 - csum;
1599
1600 return crc;
1601}
1602
1603static bool drm_edid_block_checksum_diff(const u8 *raw_edid, u8 real_checksum)
1604{
1605 if (raw_edid[EDID_LENGTH - 1] != real_checksum)
1606 return true;
1607 else
1608 return false;
c465bbc8
SB		 1609}
1610
d6885d65
SB		 1611static bool drm_edid_is_zero(const u8 *in_edid, int length)
1612{
1613 if (memchr_inv(in_edid, 0, length))
1614 return false;
1615
1616 return true;
1617}
1618
db6cf833
TR		 1619/**
1620 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1621 * @raw_edid: pointer to raw EDID block
1622 * @block: type of block to validate (0 for base, extension otherwise)
1623 * @print_bad_edid: if true, dump bad EDID blocks to the console
6ba2bd3d 1624 * @edid_corrupt: if true, the header or checksum is invalid
db6cf833
TR		 1625 *
1626 * Validate a base or extension EDID block and optionally dump bad blocks to
1627 * the console.
1628 *
1629 * Return: True if the block is valid, false otherwise.
f453ba04 1630 */
6ba2bd3d
TP		 1631bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
1632 bool *edid_corrupt)
f453ba04 1633{
c465bbc8 1634 u8 csum;
61e57a8d 1635 struct edid *edid = (struct edid *)raw_edid;
f453ba04 1636
fe2ef780
SWK		 1637 if (WARN_ON(!raw_edid))
1638 return false;
1639
47819ba2
AJ		 1640 if (edid_fixup > 8 || edid_fixup < 0)
1641 edid_fixup = 6;
1642
f89ec8a4 1643 if (block == 0) {
051963d4 1644 int score = drm_edid_header_is_valid(raw_edid);
6ba2bd3d
TP		 1645 if (score == 8) {
1646 if (edid_corrupt)
ac6f2e29 1647 *edid_corrupt = false;
6ba2bd3d
TP		 1648 } else if (score >= edid_fixup) {
1649 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
1650 * The corrupt flag needs to be set here otherwise, the
1651 * fix-up code here will correct the problem, the
1652 * checksum is correct and the test fails
1653 */
1654 if (edid_corrupt)
ac6f2e29 1655 *edid_corrupt = true;
61e57a8d
AJ		 1656 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1657 memcpy(raw_edid, edid_header, sizeof(edid_header));
1658 } else {
6ba2bd3d 1659 if (edid_corrupt)
ac6f2e29 1660 *edid_corrupt = true;
61e57a8d
AJ		 1661 goto bad;
1662 }
1663 }
f453ba04 1664
c465bbc8 1665 csum = drm_edid_block_checksum(raw_edid);
e11f5bd8 1666 if (drm_edid_block_checksum_diff(raw_edid, csum)) {
6ba2bd3d 1667 if (edid_corrupt)
ac6f2e29 1668 *edid_corrupt = true;
6ba2bd3d 1669
4a638b4e 1670 /* allow CEA to slide through, switches mangle this */
82d75356
TV		 1671 if (raw_edid[0] == CEA_EXT) {
1672 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum);
1673 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n");
1674 } else {
1675 if (print_bad_edid)
813a7878 1676 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum);
82d75356 1677
4a638b4e 1678 goto bad;
82d75356 1679 }
f453ba04
DA		 1680 }
1681
61e57a8d
AJ		 1682 /* per-block-type checks */
1683 switch (raw_edid[0]) {
1684 case 0: /* base */
1685 if (edid->version != 1) {
813a7878 1686 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version);
61e57a8d
AJ		 1687 goto bad;
1688 }
862b89c0 1689
61e57a8d
AJ		 1690 if (edid->revision > 4)
1691 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1692 break;
862b89c0 1693
61e57a8d
AJ		 1694 default:
1695 break;
1696 }
47ee4ccf 1697
fe2ef780 1698 return true;
f453ba04
DA		 1699
1700bad:
fe2ef780 1701 if (print_bad_edid) {
da4c07b7 1702 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
499447db 1703 pr_notice("EDID block is all zeroes\n");
da4c07b7 1704 } else {
499447db 1705 pr_notice("Raw EDID:\n");
813a7878
CW		 1706 print_hex_dump(KERN_NOTICE,
1707 " \t", DUMP_PREFIX_NONE, 16, 1,
1708 raw_edid, EDID_LENGTH, false);
da4c07b7 1709 }
f453ba04 1710 }
fe2ef780 1711 return false;
f453ba04 1712}
da0df92b 1713EXPORT_SYMBOL(drm_edid_block_valid);
61e57a8d
AJ		 1714
1715/**
1716 * drm_edid_is_valid - sanity check EDID data
1717 * @edid: EDID data
1718 *
1719 * Sanity-check an entire EDID record (including extensions)
db6cf833
TR		 1720 *
1721 * Return: True if the EDID data is valid, false otherwise.
61e57a8d
AJ		 1722 */
1723bool drm_edid_is_valid(struct edid *edid)
1724{
1725 int i;
1726 u8 *raw = (u8 *)edid;
1727
1728 if (!edid)
1729 return false;
1730
1731 for (i = 0; i <= edid->extensions; i++)
6ba2bd3d 1732 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
61e57a8d
AJ		 1733 return false;
1734
1735 return true;
1736}
3c537889 1737EXPORT_SYMBOL(drm_edid_is_valid);
f453ba04 1738
61e57a8d
AJ		 1739#define DDC_SEGMENT_ADDR 0x30
1740/**
db6cf833 1741 * drm_do_probe_ddc_edid() - get EDID information via I2C
7c58e87e 1742 * @data: I2C device adapter
fc66811c
DV		 1743 * @buf: EDID data buffer to be filled
1744 * @block: 128 byte EDID block to start fetching from
1745 * @len: EDID data buffer length to fetch
1746 *
db6cf833 1747 * Try to fetch EDID information by calling I2C driver functions.
61e57a8d 1748 *
db6cf833 1749 * Return: 0 on success or -1 on failure.
61e57a8d
AJ		 1750 */
1751static int
18df89fe 1752drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
61e57a8d 1753{
18df89fe 1754 struct i2c_adapter *adapter = data;
61e57a8d 1755 unsigned char start = block * EDID_LENGTH;
cd004b3f
S		 1756 unsigned char segment = block >> 1;
1757 unsigned char xfers = segment ? 3 : 2;
4819d2e4
CW		 1758 int ret, retries = 5;
1759
db6cf833
TR		 1760 /*
1761 * The core I2C driver will automatically retry the transfer if the
4819d2e4
CW		 1762 * adapter reports EAGAIN. However, we find that bit-banging transfers
1763 * are susceptible to errors under a heavily loaded machine and
1764 * generate spurious NAKs and timeouts. Retrying the transfer
1765 * of the individual block a few times seems to overcome this.
1766 */
1767 do {
1768 struct i2c_msg msgs[] = {
1769 {
cd004b3f
S		 1770 .addr = DDC_SEGMENT_ADDR,
1771 .flags = 0,
1772 .len = 1,
1773 .buf = &segment,
1774 }, {
4819d2e4
CW		 1775 .addr = DDC_ADDR,
1776 .flags = 0,
1777 .len = 1,
1778 .buf = &start,
1779 }, {
1780 .addr = DDC_ADDR,
1781 .flags = I2C_M_RD,
1782 .len = len,
1783 .buf = buf,
1784 }
1785 };
cd004b3f 1786
db6cf833
TR		 1787 /*
1788 * Avoid sending the segment addr to not upset non-compliant
1789 * DDC monitors.
1790 */
cd004b3f
S		 1791 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1792
9292f37e
ED		 1793 if (ret == -ENXIO) {
1794 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1795 adapter->name);
1796 break;
1797 }
cd004b3f 1798 } while (ret != xfers && --retries);
4819d2e4 1799
cd004b3f 1800 return ret == xfers ? 0 : -1;
61e57a8d
AJ		 1801}
1802
14544d09
CW		 1803static void connector_bad_edid(struct drm_connector *connector,
1804 u8 *edid, int num_blocks)
1805{
1806 int i;
e11f5bd8
JFZ		 1807 u8 num_of_ext = edid[0x7e];
1808
1809 /* Calculate real checksum for the last edid extension block data */
1810 connector->real_edid_checksum =
1811 drm_edid_block_checksum(edid + num_of_ext * EDID_LENGTH);
14544d09 1812
f0a8f533 1813 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
14544d09
CW		 1814 return;
1815
1816 dev_warn(connector->dev->dev,
1817 "%s: EDID is invalid:\n",
1818 connector->name);
1819 for (i = 0; i < num_blocks; i++) {
1820 u8 *block = edid + i * EDID_LENGTH;
1821 char prefix[20];
1822
1823 if (drm_edid_is_zero(block, EDID_LENGTH))
1824 sprintf(prefix, "\t[%02x] ZERO ", i);
1825 else if (!drm_edid_block_valid(block, i, false, NULL))
1826 sprintf(prefix, "\t[%02x] BAD ", i);
1827 else
1828 sprintf(prefix, "\t[%02x] GOOD ", i);
1829
1830 print_hex_dump(KERN_WARNING,
1831 prefix, DUMP_PREFIX_NONE, 16, 1,
1832 block, EDID_LENGTH, false);
1833 }
1834}
1835
56a2b7f2
JN		 1836/* Get override or firmware EDID */
1837static struct edid *drm_get_override_edid(struct drm_connector *connector)
1838{
1839 struct edid *override = NULL;
1840
1841 if (connector->override_edid)
1842 override = drm_edid_duplicate(connector->edid_blob_ptr->data);
1843
1844 if (!override)
1845 override = drm_load_edid_firmware(connector);
1846
1847 return IS_ERR(override) ? NULL : override;
1848}
1849
48eaeb76
JN		 1850/**
1851 * drm_add_override_edid_modes - add modes from override/firmware EDID
1852 * @connector: connector we're probing
1853 *
1854 * Add modes from the override/firmware EDID, if available. Only to be used from
1855 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
1856 * failed during drm_get_edid() and caused the override/firmware EDID to be
1857 * skipped.
1858 *
1859 * Return: The number of modes added or 0 if we couldn't find any.
1860 */
1861int drm_add_override_edid_modes(struct drm_connector *connector)
1862{
1863 struct edid *override;
1864 int num_modes = 0;
1865
1866 override = drm_get_override_edid(connector);
1867 if (override) {
1868 drm_connector_update_edid_property(connector, override);
1869 num_modes = drm_add_edid_modes(connector, override);
1870 kfree(override);
1871
1872 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
1873 connector->base.id, connector->name, num_modes);
1874 }
1875
1876 return num_modes;
1877}
1878EXPORT_SYMBOL(drm_add_override_edid_modes);
1879
18df89fe
LPC		 1880/**
1881 * drm_do_get_edid - get EDID data using a custom EDID block read function
1882 * @connector: connector we're probing
1883 * @get_edid_block: EDID block read function
1884 * @data: private data passed to the block read function
1885 *
1886 * When the I2C adapter connected to the DDC bus is hidden behind a device that
1887 * exposes a different interface to read EDID blocks this function can be used
1888 * to get EDID data using a custom block read function.
1889 *
1890 * As in the general case the DDC bus is accessible by the kernel at the I2C
1891 * level, drivers must make all reasonable efforts to expose it as an I2C
1892 * adapter and use drm_get_edid() instead of abusing this function.
1893 *
53fd40a9
JN		 1894 * The EDID may be overridden using debugfs override_edid or firmare EDID
1895 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
1896 * order. Having either of them bypasses actual EDID reads.
1897 *
18df89fe
LPC		 1898 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1899 */
1900struct edid *drm_do_get_edid(struct drm_connector *connector,
1901 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
1902 size_t len),
1903 void *data)
61e57a8d 1904{
0ea75e23 1905 int i, j = 0, valid_extensions = 0;
f14f3686 1906 u8 *edid, *new;
56a2b7f2 1907 struct edid *override;
53fd40a9 1908
56a2b7f2
JN		 1909 override = drm_get_override_edid(connector);
1910 if (override)
53fd40a9 1911 return override;
61e57a8d 1912
f14f3686 1913 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
61e57a8d
AJ		 1914 return NULL;
1915
1916 /* base block fetch */
1917 for (i = 0; i < 4; i++) {
f14f3686 1918 if (get_edid_block(data, edid, 0, EDID_LENGTH))
61e57a8d 1919 goto out;
14544d09 1920 if (drm_edid_block_valid(edid, 0, false,
6ba2bd3d 1921 &connector->edid_corrupt))
61e57a8d 1922 break;
f14f3686 1923 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) {
4a9a8b71
DA		 1924 connector->null_edid_counter++;
1925 goto carp;
1926 }
61e57a8d
AJ		 1927 }
1928 if (i == 4)
1929 goto carp;
1930
1931 /* if there's no extensions, we're done */
14544d09
CW		 1932 valid_extensions = edid[0x7e];
1933 if (valid_extensions == 0)
f14f3686 1934 return (struct edid *)edid;
61e57a8d 1935
14544d09 1936 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
61e57a8d
AJ		 1937 if (!new)
1938 goto out;
f14f3686 1939 edid = new;
61e57a8d 1940
f14f3686 1941 for (j = 1; j <= edid[0x7e]; j++) {
14544d09 1942 u8 *block = edid + j * EDID_LENGTH;
a28187cc 1943
61e57a8d 1944 for (i = 0; i < 4; i++) {
a28187cc 1945 if (get_edid_block(data, block, j, EDID_LENGTH))
61e57a8d 1946 goto out;
14544d09 1947 if (drm_edid_block_valid(block, j, false, NULL))
61e57a8d
AJ		 1948 break;
1949 }
f934ec8c 1950
14544d09
CW		 1951 if (i == 4)
1952 valid_extensions--;
0ea75e23
ST		 1953 }
1954
f14f3686 1955 if (valid_extensions != edid[0x7e]) {
14544d09
CW		 1956 u8 *base;
1957
1958 connector_bad_edid(connector, edid, edid[0x7e] + 1);
1959
f14f3686
CW		 1960 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions;
1961 edid[0x7e] = valid_extensions;
14544d09 1962
6da2ec56
KC		 1963 new = kmalloc_array(valid_extensions + 1, EDID_LENGTH,
1964 GFP_KERNEL);
0ea75e23
ST		 1965 if (!new)
1966 goto out;
14544d09
CW		 1967
1968 base = new;
1969 for (i = 0; i <= edid[0x7e]; i++) {
1970 u8 *block = edid + i * EDID_LENGTH;
1971
1972 if (!drm_edid_block_valid(block, i, false, NULL))
1973 continue;
1974
1975 memcpy(base, block, EDID_LENGTH);
1976 base += EDID_LENGTH;
1977 }
1978
1979 kfree(edid);
f14f3686 1980 edid = new;
61e57a8d
AJ		 1981 }
1982
f14f3686 1983 return (struct edid *)edid;
61e57a8d
AJ		 1984
1985carp:
14544d09 1986 connector_bad_edid(connector, edid, 1);
61e57a8d 1987out:
f14f3686 1988 kfree(edid);
61e57a8d
AJ		 1989 return NULL;
1990}
18df89fe 1991EXPORT_SYMBOL_GPL(drm_do_get_edid);
61e57a8d
AJ		 1992
1993/**
db6cf833
TR		 1994 * drm_probe_ddc() - probe DDC presence
1995 * @adapter: I2C adapter to probe
fc66811c 1996 *
db6cf833 1997 * Return: True on success, false on failure.
61e57a8d 1998 */
fbff4690 1999bool
61e57a8d
AJ		 2000drm_probe_ddc(struct i2c_adapter *adapter)
2001{
2002 unsigned char out;
2003
2004 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
2005}
fbff4690 2006EXPORT_SYMBOL(drm_probe_ddc);
61e57a8d
AJ		 2007
2008/**
2009 * drm_get_edid - get EDID data, if available
2010 * @connector: connector we're probing
db6cf833 2011 * @adapter: I2C adapter to use for DDC
61e57a8d 2012 *
db6cf833 2013 * Poke the given I2C channel to grab EDID data if possible. If found,
61e57a8d
AJ		 2014 * attach it to the connector.
2015 *
db6cf833 2016 * Return: Pointer to valid EDID or NULL if we couldn't find any.
61e57a8d
AJ		 2017 */
2018struct edid *drm_get_edid(struct drm_connector *connector,
2019 struct i2c_adapter *adapter)
2020{
40d9b043
DA		 2021 struct edid *edid;
2022
15f080f0
JN		 2023 if (connector->force == DRM_FORCE_OFF)
2024 return NULL;
2025
2026 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
18df89fe 2027 return NULL;
61e57a8d 2028
40d9b043
DA		 2029 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
2030 if (edid)
2031 drm_get_displayid(connector, edid);
2032 return edid;
61e57a8d
AJ		 2033}
2034EXPORT_SYMBOL(drm_get_edid);
2035
5cb8eaa2
LW		 2036/**
2037 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
2038 * @connector: connector we're probing
2039 * @adapter: I2C adapter to use for DDC
2040 *
2041 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
2042 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
2043 * switch DDC to the GPU which is retrieving EDID.
2044 *
2045 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2046 */
2047struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
2048 struct i2c_adapter *adapter)
2049{
2050 struct pci_dev *pdev = connector->dev->pdev;
2051 struct edid *edid;
2052
2053 vga_switcheroo_lock_ddc(pdev);
2054 edid = drm_get_edid(connector, adapter);
2055 vga_switcheroo_unlock_ddc(pdev);
2056
2057 return edid;
2058}
2059EXPORT_SYMBOL(drm_get_edid_switcheroo);
2060
51f8da59
JN		 2061/**
2062 * drm_edid_duplicate - duplicate an EDID and the extensions
2063 * @edid: EDID to duplicate
2064 *
db6cf833 2065 * Return: Pointer to duplicated EDID or NULL on allocation failure.
51f8da59
JN		 2066 */
2067struct edid *drm_edid_duplicate(const struct edid *edid)
2068{
2069 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
2070}
2071EXPORT_SYMBOL(drm_edid_duplicate);
2072
61e57a8d
AJ		 2073/*** EDID parsing ***/
2074
f453ba04
DA		 2075/**
2076 * edid_vendor - match a string against EDID's obfuscated vendor field
2077 * @edid: EDID to match
2078 * @vendor: vendor string
2079 *
2080 * Returns true if @vendor is in @edid, false otherwise
2081 */
170178fe 2082static bool edid_vendor(const struct edid *edid, const char *vendor)
f453ba04
DA		 2083{
2084 char edid_vendor[3];
2085
2086 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
2087 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
2088 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
16456c87 2089 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
f453ba04
DA		 2090
2091 return !strncmp(edid_vendor, vendor, 3);
2092}
2093
2094/**
2095 * edid_get_quirks - return quirk flags for a given EDID
2096 * @edid: EDID to process
2097 *
2098 * This tells subsequent routines what fixes they need to apply.
2099 */
170178fe 2100static u32 edid_get_quirks(const struct edid *edid)
f453ba04 2101{
23c4cfbd 2102 const struct edid_quirk *quirk;
f453ba04
DA		 2103 int i;
2104
2105 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
2106 quirk = &edid_quirk_list[i];
2107
2108 if (edid_vendor(edid, quirk->vendor) &&
2109 (EDID_PRODUCT_ID(edid) == quirk->product_id))
2110 return quirk->quirks;
2111 }
2112
2113 return 0;
2114}
2115
2116#define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
339d202c 2117#define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
f453ba04 2118
f453ba04
DA		 2119/**
2120 * edid_fixup_preferred - set preferred modes based on quirk list
2121 * @connector: has mode list to fix up
2122 * @quirks: quirks list
2123 *
2124 * Walk the mode list for @connector, clearing the preferred status
2125 * on existing modes and setting it anew for the right mode ala @quirks.
2126 */
2127static void edid_fixup_preferred(struct drm_connector *connector,
2128 u32 quirks)
2129{
2130 struct drm_display_mode *t, *cur_mode, *preferred_mode;
f890607b 2131 int target_refresh = 0;
339d202c 2132 int cur_vrefresh, preferred_vrefresh;
f453ba04
DA		 2133
2134 if (list_empty(&connector->probed_modes))
2135 return;
2136
2137 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
2138 target_refresh = 60;
2139 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
2140 target_refresh = 75;
2141
2142 preferred_mode = list_first_entry(&connector->probed_modes,
2143 struct drm_display_mode, head);
2144
2145 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
2146 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
2147
2148 if (cur_mode == preferred_mode)
2149 continue;
2150
2151 /* Largest mode is preferred */
2152 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
2153 preferred_mode = cur_mode;
2154
339d202c
AD		 2155 cur_vrefresh = cur_mode->vrefresh ?
2156 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode);
2157 preferred_vrefresh = preferred_mode->vrefresh ?
2158 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode);
f453ba04
DA		 2159 /* At a given size, try to get closest to target refresh */
2160 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
339d202c
AD		 2161 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
2162 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
f453ba04
DA		 2163 preferred_mode = cur_mode;
2164 }
2165 }
2166
2167 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
2168}
2169
f6e252ba
AJ		 2170static bool
2171mode_is_rb(const struct drm_display_mode *mode)
2172{
2173 return (mode->htotal - mode->hdisplay == 160) &&
2174 (mode->hsync_end - mode->hdisplay == 80) &&
2175 (mode->hsync_end - mode->hsync_start == 32) &&
2176 (mode->vsync_start - mode->vdisplay == 3);
2177}
2178
33c7531d
AJ		 2179/*
2180 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
2181 * @dev: Device to duplicate against
2182 * @hsize: Mode width
2183 * @vsize: Mode height
2184 * @fresh: Mode refresh rate
f6e252ba 2185 * @rb: Mode reduced-blanking-ness
33c7531d
AJ		 2186 *
2187 * Walk the DMT mode list looking for a match for the given parameters.
db6cf833
TR		 2188 *
2189 * Return: A newly allocated copy of the mode, or NULL if not found.
33c7531d 2190 */
1d42bbc8 2191struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
f6e252ba
AJ		 2192 int hsize, int vsize, int fresh,
2193 bool rb)
559ee21d 2194{
07a5e632 2195 int i;
559ee21d 2196
a6b21831 2197 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
b1f559ec 2198 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
f8b46a05
AJ		 2199 if (hsize != ptr->hdisplay)
2200 continue;
2201 if (vsize != ptr->vdisplay)
2202 continue;
2203 if (fresh != drm_mode_vrefresh(ptr))
2204 continue;
f6e252ba
AJ		 2205 if (rb != mode_is_rb(ptr))
2206 continue;
f8b46a05
AJ		 2207
2208 return drm_mode_duplicate(dev, ptr);
559ee21d 2209 }
f8b46a05
AJ		 2210
2211 return NULL;
559ee21d 2212}
1d42bbc8 2213EXPORT_SYMBOL(drm_mode_find_dmt);
23425cae 2214
a7a131ac
VS		 2215static bool is_display_descriptor(const u8 d[18], u8 tag)
2216{
2217 return d[0] == 0x00 && d[1] == 0x00 &&
2218 d[2] == 0x00 && d[3] == tag;
2219}
2220
f447dd1f
VS		 2221static bool is_detailed_timing_descriptor(const u8 d[18])
2222{
2223 return d[0] != 0x00 || d[1] != 0x00;
2224}
2225
d1ff6409
AJ		 2226typedef void detailed_cb(struct detailed_timing *timing, void *closure);
2227
4d76a221
AJ		 2228static void
2229cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
2230{
7304b981 2231 int i, n;
4966b2a9 2232 u8 d = ext[0x02];
4d76a221
AJ		 2233 u8 *det_base = ext + d;
2234
7304b981
VS		 2235 if (d < 4 || d > 127)
2236 return;
2237
4966b2a9 2238 n = (127 - d) / 18;
4d76a221
AJ		 2239 for (i = 0; i < n; i++)
2240 cb((struct detailed_timing *)(det_base + 18 * i), closure);
2241}
2242
cbba98f8
AJ		 2243static void
2244vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
2245{
2246 unsigned int i, n = min((int)ext[0x02], 6);
2247 u8 *det_base = ext + 5;
2248
2249 if (ext[0x01] != 1)
2250 return; /* unknown version */
2251
2252 for (i = 0; i < n; i++)
2253 cb((struct detailed_timing *)(det_base + 18 * i), closure);
2254}
2255
d1ff6409
AJ		 2256static void
2257drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
2258{
2259 int i;
2260 struct edid *edid = (struct edid *)raw_edid;
2261
2262 if (edid == NULL)
2263 return;
2264
2265 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
2266 cb(&(edid->detailed_timings[i]), closure);
2267
4d76a221
AJ		 2268 for (i = 1; i <= raw_edid[0x7e]; i++) {
2269 u8 *ext = raw_edid + (i * EDID_LENGTH);
2270 switch (*ext) {
2271 case CEA_EXT:
2272 cea_for_each_detailed_block(ext, cb, closure);
2273 break;
cbba98f8
AJ		 2274 case VTB_EXT:
2275 vtb_for_each_detailed_block(ext, cb, closure);
2276 break;
4d76a221
AJ		 2277 default:
2278 break;
2279 }
2280 }
d1ff6409
AJ		 2281}
2282
2283static void
2284is_rb(struct detailed_timing *t, void *data)
2285{
2286 u8 *r = (u8 *)t;
a7a131ac
VS		 2287
2288 if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE))
2289 return;
2290
2291 if (r[15] & 0x10)
2292 *(bool *)data = true;
d1ff6409
AJ		 2293}
2294
2295/* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
2296static bool
2297drm_monitor_supports_rb(struct edid *edid)
2298{
2299 if (edid->revision >= 4) {
b196a498 2300 bool ret = false;
d1ff6409
AJ		 2301 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
2302 return ret;
2303 }
2304
2305 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
2306}
2307
7a374350
AJ		 2308static void
2309find_gtf2(struct detailed_timing *t, void *data)
2310{
2311 u8 *r = (u8 *)t;
a7a131ac
VS		 2312
2313 if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE))
2314 return;
2315
2316 if (r[10] == 0x02)
7a374350
AJ		 2317 *(u8 **)data = r;
2318}
2319
2320/* Secondary GTF curve kicks in above some break frequency */
2321static int
2322drm_gtf2_hbreak(struct edid *edid)
2323{
2324 u8 *r = NULL;
2325 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2326 return r ? (r[12] * 2) : 0;
2327}
2328
2329static int
2330drm_gtf2_2c(struct edid *edid)
2331{
2332 u8 *r = NULL;
2333 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2334 return r ? r[13] : 0;
2335}
2336
2337static int
2338drm_gtf2_m(struct edid *edid)
2339{
2340 u8 *r = NULL;
2341 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2342 return r ? (r[15] << 8) + r[14] : 0;
2343}
2344
2345static int
2346drm_gtf2_k(struct edid *edid)
2347{
2348 u8 *r = NULL;
2349 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2350 return r ? r[16] : 0;
2351}
2352
2353static int
2354drm_gtf2_2j(struct edid *edid)
2355{
2356 u8 *r = NULL;
2357 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2358 return r ? r[17] : 0;
2359}
2360
2361/**
2362 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
2363 * @edid: EDID block to scan
2364 */
2365static int standard_timing_level(struct edid *edid)
2366{
2367 if (edid->revision >= 2) {
2368 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
2369 return LEVEL_CVT;
2370 if (drm_gtf2_hbreak(edid))
2371 return LEVEL_GTF2;
bfef04ad
LS		 2372 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
2373 return LEVEL_GTF;
7a374350
AJ		 2374 }
2375 return LEVEL_DMT;
2376}
2377
23425cae
AJ		 2378/*
2379 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
2380 * monitors fill with ascii space (0x20) instead.
2381 */
2382static int
2383bad_std_timing(u8 a, u8 b)
2384{
2385 return (a == 0x00 && b == 0x00) ||
2386 (a == 0x01 && b == 0x01) ||
2387 (a == 0x20 && b == 0x20);
2388}
2389
f453ba04
DA		 2390/**
2391 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
fc66811c
DV		 2392 * @connector: connector of for the EDID block
2393 * @edid: EDID block to scan
f453ba04
DA		 2394 * @t: standard timing params
2395 *
2396 * Take the standard timing params (in this case width, aspect, and refresh)
5c61259e 2397 * and convert them into a real mode using CVT/GTF/DMT.
f453ba04 2398 */
7ca6adb3 2399static struct drm_display_mode *
7a374350 2400drm_mode_std(struct drm_connector *connector, struct edid *edid,
464fdeca 2401 struct std_timing *t)
f453ba04 2402{
7ca6adb3
AJ		 2403 struct drm_device *dev = connector->dev;
2404 struct drm_display_mode *m, *mode = NULL;
5c61259e
ZY		 2405 int hsize, vsize;
2406 int vrefresh_rate;
0454beab
MD		 2407 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
2408 >> EDID_TIMING_ASPECT_SHIFT;
5c61259e
ZY		 2409 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
2410 >> EDID_TIMING_VFREQ_SHIFT;
7a374350 2411 int timing_level = standard_timing_level(edid);
5c61259e 2412
23425cae
AJ		 2413 if (bad_std_timing(t->hsize, t->vfreq_aspect))
2414 return NULL;
2415
5c61259e
ZY		 2416 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
2417 hsize = t->hsize * 8 + 248;
2418 /* vrefresh_rate = vfreq + 60 */
2419 vrefresh_rate = vfreq + 60;
2420 /* the vdisplay is calculated based on the aspect ratio */
f066a17d 2421 if (aspect_ratio == 0) {
464fdeca 2422 if (edid->revision < 3)
f066a17d
AJ		 2423 vsize = hsize;
2424 else
2425 vsize = (hsize * 10) / 16;
2426 } else if (aspect_ratio == 1)
f453ba04 2427 vsize = (hsize * 3) / 4;
0454beab 2428 else if (aspect_ratio == 2)
f453ba04
DA		 2429 vsize = (hsize * 4) / 5;
2430 else
2431 vsize = (hsize * 9) / 16;
a0910c8e
AJ		 2432
2433 /* HDTV hack, part 1 */
2434 if (vrefresh_rate == 60 &&
2435 ((hsize == 1360 && vsize == 765) ||
2436 (hsize == 1368 && vsize == 769))) {
2437 hsize = 1366;
2438 vsize = 768;
2439 }
2440
7ca6adb3
AJ		 2441 /*
2442 * If this connector already has a mode for this size and refresh
2443 * rate (because it came from detailed or CVT info), use that
2444 * instead. This way we don't have to guess at interlace or
2445 * reduced blanking.
2446 */
522032da 2447 list_for_each_entry(m, &connector->probed_modes, head)
7ca6adb3
AJ		 2448 if (m->hdisplay == hsize && m->vdisplay == vsize &&
2449 drm_mode_vrefresh(m) == vrefresh_rate)
2450 return NULL;
2451
a0910c8e
AJ		 2452 /* HDTV hack, part 2 */
2453 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
2454 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
d50ba256 2455 false);
a5ef6567
JM		 2456 if (!mode)
2457 return NULL;
559ee21d 2458 mode->hdisplay = 1366;
a4967de6
AJ		 2459 mode->hsync_start = mode->hsync_start - 1;
2460 mode->hsync_end = mode->hsync_end - 1;
559ee21d
ZY		 2461 return mode;
2462 }
a0910c8e 2463
559ee21d 2464 /* check whether it can be found in default mode table */
f6e252ba
AJ		 2465 if (drm_monitor_supports_rb(edid)) {
2466 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
2467 true);
2468 if (mode)
2469 return mode;
2470 }
2471 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
559ee21d
ZY		 2472 if (mode)
2473 return mode;
2474
f6e252ba 2475 /* okay, generate it */
5c61259e
ZY		 2476 switch (timing_level) {
2477 case LEVEL_DMT:
5c61259e
ZY		 2478 break;
2479 case LEVEL_GTF:
2480 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2481 break;
7a374350
AJ		 2482 case LEVEL_GTF2:
2483 /*
2484 * This is potentially wrong if there's ever a monitor with
2485 * more than one ranges section, each claiming a different
2486 * secondary GTF curve. Please don't do that.
2487 */
2488 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
fc48f169
TI		 2489 if (!mode)
2490 return NULL;
7a374350 2491 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
aefd330e 2492 drm_mode_destroy(dev, mode);
7a374350
AJ		 2493 mode = drm_gtf_mode_complex(dev, hsize, vsize,
2494 vrefresh_rate, 0, 0,
2495 drm_gtf2_m(edid),
2496 drm_gtf2_2c(edid),
2497 drm_gtf2_k(edid),
2498 drm_gtf2_2j(edid));
2499 }
2500 break;
5c61259e 2501 case LEVEL_CVT:
d50ba256
DA		 2502 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
2503 false);
5c61259e
ZY		 2504 break;
2505 }
f453ba04
DA		 2506 return mode;
2507}
2508
b58db2c6
AJ		 2509/*
2510 * EDID is delightfully ambiguous about how interlaced modes are to be
2511 * encoded. Our internal representation is of frame height, but some
2512 * HDTV detailed timings are encoded as field height.
2513 *
2514 * The format list here is from CEA, in frame size. Technically we
2515 * should be checking refresh rate too. Whatever.
2516 */
2517static void
2518drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
2519 struct detailed_pixel_timing *pt)
2520{
2521 int i;
2522 static const struct {
2523 int w, h;
2524 } cea_interlaced[] = {
2525 { 1920, 1080 },
2526 { 720, 480 },
2527 { 1440, 480 },
2528 { 2880, 480 },
2529 { 720, 576 },
2530 { 1440, 576 },
2531 { 2880, 576 },
2532 };
b58db2c6
AJ		 2533
2534 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
2535 return;
2536
3c581411 2537 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
b58db2c6
AJ		 2538 if ((mode->hdisplay == cea_interlaced[i].w) &&
2539 (mode->vdisplay == cea_interlaced[i].h / 2)) {
2540 mode->vdisplay *= 2;
2541 mode->vsync_start *= 2;
2542 mode->vsync_end *= 2;
2543 mode->vtotal *= 2;
2544 mode->vtotal |= 1;
2545 }
2546 }
2547
2548 mode->flags |= DRM_MODE_FLAG_INTERLACE;
2549}
2550
f453ba04
DA		 2551/**
2552 * drm_mode_detailed - create a new mode from an EDID detailed timing section
2553 * @dev: DRM device (needed to create new mode)
2554 * @edid: EDID block
2555 * @timing: EDID detailed timing info
2556 * @quirks: quirks to apply
2557 *
2558 * An EDID detailed timing block contains enough info for us to create and
2559 * return a new struct drm_display_mode.
2560 */
2561static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
2562 struct edid *edid,
2563 struct detailed_timing *timing,
2564 u32 quirks)
2565{
2566 struct drm_display_mode *mode;
2567 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
0454beab
MD		 2568 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
2569 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
2570 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
2571 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
e14cbee4
MD		 2572 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
2573 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
16dad1d7 2574 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
e14cbee4 2575 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
f453ba04 2576
fc438966 2577 /* ignore tiny modes */
0454beab 2578 if (hactive < 64 || vactive < 64)
fc438966
AJ		 2579 return NULL;
2580
0454beab 2581 if (pt->misc & DRM_EDID_PT_STEREO) {
c7d015f3 2582 DRM_DEBUG_KMS("stereo mode not supported\n");
f453ba04
DA		 2583 return NULL;
2584 }
0454beab 2585 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
c7d015f3 2586 DRM_DEBUG_KMS("composite sync not supported\n");
f453ba04
DA		 2587 }
2588
fcb45611
ZY		 2589 /* it is incorrect if hsync/vsync width is zero */
2590 if (!hsync_pulse_width || !vsync_pulse_width) {
2591 DRM_DEBUG_KMS("Incorrect Detailed timing. "
2592 "Wrong Hsync/Vsync pulse width\n");
2593 return NULL;
2594 }
bc42aabc
AJ		 2595
2596 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
2597 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
2598 if (!mode)
2599 return NULL;
2600
2601 goto set_size;
2602 }
2603
f453ba04
DA		 2604 mode = drm_mode_create(dev);
2605 if (!mode)
2606 return NULL;
2607
f453ba04 2608 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
0454beab
MD		 2609 timing->pixel_clock = cpu_to_le16(1088);
2610
2611 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
2612
2613 mode->hdisplay = hactive;
2614 mode->hsync_start = mode->hdisplay + hsync_offset;
2615 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
2616 mode->htotal = mode->hdisplay + hblank;
2617
2618 mode->vdisplay = vactive;
2619 mode->vsync_start = mode->vdisplay + vsync_offset;
2620 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
2621 mode->vtotal = mode->vdisplay + vblank;
f453ba04 2622
7064fef5
JB		 2623 /* Some EDIDs have bogus h/vtotal values */
2624 if (mode->hsync_end > mode->htotal)
2625 mode->htotal = mode->hsync_end + 1;
2626 if (mode->vsync_end > mode->vtotal)
2627 mode->vtotal = mode->vsync_end + 1;
2628
b58db2c6 2629 drm_mode_do_interlace_quirk(mode, pt);
f453ba04
DA		 2630
2631 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
0454beab 2632 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
f453ba04
DA		 2633 }
2634
0454beab
MD		 2635 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
2636 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
2637 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
2638 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
f453ba04 2639
bc42aabc 2640set_size:
e14cbee4
MD		 2641 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
2642 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
f453ba04
DA		 2643
2644 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
2645 mode->width_mm *= 10;
2646 mode->height_mm *= 10;
2647 }
2648
2649 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
2650 mode->width_mm = edid->width_cm * 10;
2651 mode->height_mm = edid->height_cm * 10;
2652 }
2653
bc42aabc 2654 mode->type = DRM_MODE_TYPE_DRIVER;
c19b3b0f 2655 mode->vrefresh = drm_mode_vrefresh(mode);
bc42aabc
AJ		 2656 drm_mode_set_name(mode);
2657
f453ba04
DA		 2658 return mode;
2659}
2660
b17e52ef 2661static bool
b1f559ec
CW		 2662mode_in_hsync_range(const struct drm_display_mode *mode,
2663 struct edid *edid, u8 *t)
b17e52ef
AJ		 2664{
2665 int hsync, hmin, hmax;
2666
2667 hmin = t[7];
2668 if (edid->revision >= 4)
2669 hmin += ((t[4] & 0x04) ? 255 : 0);
2670 hmax = t[8];
2671 if (edid->revision >= 4)
2672 hmax += ((t[4] & 0x08) ? 255 : 0);
07a5e632 2673 hsync = drm_mode_hsync(mode);
07a5e632 2674
b17e52ef
AJ		 2675 return (hsync <= hmax && hsync >= hmin);
2676}
2677
2678static bool
b1f559ec
CW		 2679mode_in_vsync_range(const struct drm_display_mode *mode,
2680 struct edid *edid, u8 *t)
b17e52ef
AJ		 2681{
2682 int vsync, vmin, vmax;
2683
2684 vmin = t[5];
2685 if (edid->revision >= 4)
2686 vmin += ((t[4] & 0x01) ? 255 : 0);
2687 vmax = t[6];
2688 if (edid->revision >= 4)
2689 vmax += ((t[4] & 0x02) ? 255 : 0);
2690 vsync = drm_mode_vrefresh(mode);
2691
2692 return (vsync <= vmax && vsync >= vmin);
2693}
2694
2695static u32
2696range_pixel_clock(struct edid *edid, u8 *t)
2697{
2698 /* unspecified */
2699 if (t[9] == 0 || t[9] == 255)
2700 return 0;
2701
2702 /* 1.4 with CVT support gives us real precision, yay */
2703 if (edid->revision >= 4 && t[10] == 0x04)
2704 return (t[9] * 10000) - ((t[12] >> 2) * 250);
2705
2706 /* 1.3 is pathetic, so fuzz up a bit */
2707 return t[9] * 10000 + 5001;
2708}
2709
b17e52ef 2710static bool
b1f559ec 2711mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
b17e52ef
AJ		 2712 struct detailed_timing *timing)
2713{
2714 u32 max_clock;
2715 u8 *t = (u8 *)timing;
2716
2717 if (!mode_in_hsync_range(mode, edid, t))
07a5e632
AJ		 2718 return false;
2719
b17e52ef 2720 if (!mode_in_vsync_range(mode, edid, t))
07a5e632
AJ		 2721 return false;
2722
b17e52ef 2723 if ((max_clock = range_pixel_clock(edid, t)))
07a5e632
AJ		 2724 if (mode->clock > max_clock)
2725 return false;
b17e52ef
AJ		 2726
2727 /* 1.4 max horizontal check */
2728 if (edid->revision >= 4 && t[10] == 0x04)
2729 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
2730 return false;
2731
2732 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
2733 return false;
07a5e632
AJ		 2734
2735 return true;
2736}
2737
7b668ebe
TI		 2738static bool valid_inferred_mode(const struct drm_connector *connector,
2739 const struct drm_display_mode *mode)
2740{
85f8fcd6 2741 const struct drm_display_mode *m;
7b668ebe
TI		 2742 bool ok = false;
2743
2744 list_for_each_entry(m, &connector->probed_modes, head) {
2745 if (mode->hdisplay == m->hdisplay &&
2746 mode->vdisplay == m->vdisplay &&
2747 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
2748 return false; /* duplicated */
2749 if (mode->hdisplay <= m->hdisplay &&
2750 mode->vdisplay <= m->vdisplay)
2751 ok = true;
2752 }
2753 return ok;
2754}
2755
b17e52ef 2756static int
cd4cd3de 2757drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
b17e52ef 2758 struct detailed_timing *timing)
07a5e632
AJ		 2759{
2760 int i, modes = 0;
2761 struct drm_display_mode *newmode;
2762 struct drm_device *dev = connector->dev;
2763
a6b21831 2764 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
7b668ebe
TI		 2765 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
2766 valid_inferred_mode(connector, drm_dmt_modes + i)) {
07a5e632
AJ		 2767 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
2768 if (newmode) {
2769 drm_mode_probed_add(connector, newmode);
2770 modes++;
2771 }
2772 }
2773 }
2774
2775 return modes;
2776}
2777
c09dedb7
TI		 2778/* fix up 1366x768 mode from 1368x768;
2779 * GFT/CVT can't express 1366 width which isn't dividable by 8
2780 */
969218fe 2781void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
c09dedb7
TI		 2782{
2783 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
2784 mode->hdisplay = 1366;
2785 mode->hsync_start--;
2786 mode->hsync_end--;
2787 drm_mode_set_name(mode);
2788 }
2789}
2790
b309bd37
AJ		 2791static int
2792drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
2793 struct detailed_timing *timing)
2794{
2795 int i, modes = 0;
2796 struct drm_display_mode *newmode;
2797 struct drm_device *dev = connector->dev;
2798
a6b21831 2799 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
b309bd37
AJ		 2800 const struct minimode *m = &extra_modes[i];
2801 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
fc48f169
TI		 2802 if (!newmode)
2803 return modes;
b309bd37 2804
969218fe 2805 drm_mode_fixup_1366x768(newmode);
7b668ebe
TI		 2806 if (!mode_in_range(newmode, edid, timing) ||
2807 !valid_inferred_mode(connector, newmode)) {
b309bd37
AJ		 2808 drm_mode_destroy(dev, newmode);
2809 continue;
2810 }
2811
2812 drm_mode_probed_add(connector, newmode);
2813 modes++;
2814 }
2815
2816 return modes;
2817}
2818
2819static int
2820drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2821 struct detailed_timing *timing)
2822{
2823 int i, modes = 0;
2824 struct drm_display_mode *newmode;
2825 struct drm_device *dev = connector->dev;
2826 bool rb = drm_monitor_supports_rb(edid);
2827
a6b21831 2828 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
b309bd37
AJ		 2829 const struct minimode *m = &extra_modes[i];
2830 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
fc48f169
TI		 2831 if (!newmode)
2832 return modes;
b309bd37 2833
969218fe 2834 drm_mode_fixup_1366x768(newmode);
7b668ebe
TI		 2835 if (!mode_in_range(newmode, edid, timing) ||
2836 !valid_inferred_mode(connector, newmode)) {
b309bd37
AJ		 2837 drm_mode_destroy(dev, newmode);
2838 continue;
2839 }
2840
2841 drm_mode_probed_add(connector, newmode);
2842 modes++;
2843 }
2844
2845 return modes;
2846}
2847
13931579
AJ		 2848static void
2849do_inferred_modes(struct detailed_timing *timing, void *c)
9340d8cf 2850{
13931579
AJ		 2851 struct detailed_mode_closure *closure = c;
2852 struct detailed_non_pixel *data = &timing->data.other_data;
b309bd37 2853 struct detailed_data_monitor_range *range = &data->data.range;
9340d8cf 2854
a7a131ac 2855 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE))
cb21aafe
AJ		 2856 return;
2857
2858 closure->modes += drm_dmt_modes_for_range(closure->connector,
2859 closure->edid,
2860 timing);
4d23f484 2861
b309bd37
AJ		 2862 if (!version_greater(closure->edid, 1, 1))
2863 return; /* GTF not defined yet */
2864
2865 switch (range->flags) {
2866 case 0x02: /* secondary gtf, XXX could do more */
2867 case 0x00: /* default gtf */
2868 closure->modes += drm_gtf_modes_for_range(closure->connector,
2869 closure->edid,
2870 timing);
2871 break;
2872 case 0x04: /* cvt, only in 1.4+ */
2873 if (!version_greater(closure->edid, 1, 3))
2874 break;
2875
2876 closure->modes += drm_cvt_modes_for_range(closure->connector,
2877 closure->edid,
2878 timing);
2879 break;
2880 case 0x01: /* just the ranges, no formula */
2881 default:
2882 break;
2883 }
13931579 2884}
69da3015 2885
13931579
AJ		 2886static int
2887add_inferred_modes(struct drm_connector *connector, struct edid *edid)
2888{
2889 struct detailed_mode_closure closure = {
d456ea2e
JL		 2890 .connector = connector,
2891 .edid = edid,
13931579 2892 };
9340d8cf 2893
13931579
AJ		 2894 if (version_greater(edid, 1, 0))
2895 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
2896 &closure);
9340d8cf 2897
13931579 2898 return closure.modes;
9340d8cf
AJ		 2899}
2900
2255be14
AJ		 2901static int
2902drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
2903{
2904 int i, j, m, modes = 0;
2905 struct drm_display_mode *mode;
f3a32d74 2906 u8 *est = ((u8 *)timing) + 6;
2255be14
AJ		 2907
2908 for (i = 0; i < 6; i++) {
891a7469 2909 for (j = 7; j >= 0; j--) {
2255be14 2910 m = (i * 8) + (7 - j);
3c581411 2911 if (m >= ARRAY_SIZE(est3_modes))
2255be14
AJ		 2912 break;
2913 if (est[i] & (1 << j)) {
1d42bbc8
DA		 2914 mode = drm_mode_find_dmt(connector->dev,
2915 est3_modes[m].w,
2916 est3_modes[m].h,
f6e252ba
AJ		 2917 est3_modes[m].r,
2918 est3_modes[m].rb);
2255be14
AJ		 2919 if (mode) {
2920 drm_mode_probed_add(connector, mode);
2921 modes++;
2922 }
2923 }
2924 }
2925 }
2926
2927 return modes;
2928}
2929
13931579
AJ		 2930static void
2931do_established_modes(struct detailed_timing *timing, void *c)
9cf00977 2932{
13931579 2933 struct detailed_mode_closure *closure = c;
9cf00977 2934
a7a131ac
VS		 2935 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_EST_TIMINGS))
2936 return;
2937
2938 closure->modes += drm_est3_modes(closure->connector, timing);
13931579 2939}
9cf00977 2940
13931579
AJ		 2941/**
2942 * add_established_modes - get est. modes from EDID and add them
db6cf833 2943 * @connector: connector to add mode(s) to
13931579
AJ		 2944 * @edid: EDID block to scan
2945 *
2946 * Each EDID block contains a bitmap of the supported "established modes" list
2947 * (defined above). Tease them out and add them to the global modes list.
2948 */
2949static int
2950add_established_modes(struct drm_connector *connector, struct edid *edid)
2951{
2952 struct drm_device *dev = connector->dev;
2953 unsigned long est_bits = edid->established_timings.t1 |
2954 (edid->established_timings.t2 << 8) |
2955 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
2956 int i, modes = 0;
2957 struct detailed_mode_closure closure = {
d456ea2e
JL		 2958 .connector = connector,
2959 .edid = edid,
13931579 2960 };
9cf00977 2961
13931579
AJ		 2962 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
2963 if (est_bits & (1<<i)) {
2964 struct drm_display_mode *newmode;
2965 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
2966 if (newmode) {
2967 drm_mode_probed_add(connector, newmode);
2968 modes++;
2969 }
2970 }
9cf00977
AJ		 2971 }
2972
13931579
AJ		 2973 if (version_greater(edid, 1, 0))
2974 drm_for_each_detailed_block((u8 *)edid,
2975 do_established_modes, &closure);
2976
2977 return modes + closure.modes;
2978}
2979
2980static void
2981do_standard_modes(struct detailed_timing *timing, void *c)
2982{
2983 struct detailed_mode_closure *closure = c;
2984 struct detailed_non_pixel *data = &timing->data.other_data;
2985 struct drm_connector *connector = closure->connector;
2986 struct edid *edid = closure->edid;
a7a131ac 2987 int i;
13931579 2988
a7a131ac
VS		 2989 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_STD_MODES))
2990 return;
9cf00977 2991
a7a131ac
VS		 2992 for (i = 0; i < 6; i++) {
2993 struct std_timing *std = &data->data.timings[i];
2994 struct drm_display_mode *newmode;
2995
2996 newmode = drm_mode_std(connector, edid, std);
2997 if (newmode) {
2998 drm_mode_probed_add(connector, newmode);
2999 closure->modes++;
9cf00977 3000 }
9cf00977 3001 }
9cf00977
AJ		 3002}
3003
f453ba04 3004/**
13931579 3005 * add_standard_modes - get std. modes from EDID and add them
db6cf833 3006 * @connector: connector to add mode(s) to
f453ba04 3007 * @edid: EDID block to scan
f453ba04 3008 *
13931579
AJ		 3009 * Standard modes can be calculated using the appropriate standard (DMT,
3010 * GTF or CVT. Grab them from @edid and add them to the list.
f453ba04 3011 */
13931579
AJ		 3012static int
3013add_standard_modes(struct drm_connector *connector, struct edid *edid)
f453ba04 3014{
9cf00977 3015 int i, modes = 0;
13931579 3016 struct detailed_mode_closure closure = {
d456ea2e
JL		 3017 .connector = connector,
3018 .edid = edid,
13931579
AJ		 3019 };
3020
3021 for (i = 0; i < EDID_STD_TIMINGS; i++) {
3022 struct drm_display_mode *newmode;
3023
3024 newmode = drm_mode_std(connector, edid,
464fdeca 3025 &edid->standard_timings[i]);
13931579
AJ		 3026 if (newmode) {
3027 drm_mode_probed_add(connector, newmode);
3028 modes++;
3029 }
3030 }
3031
3032 if (version_greater(edid, 1, 0))
3033 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
3034 &closure);
3035
3036 /* XXX should also look for standard codes in VTB blocks */
3037
3038 return modes + closure.modes;
3039}
f453ba04 3040
13931579
AJ		 3041static int drm_cvt_modes(struct drm_connector *connector,
3042 struct detailed_timing *timing)
3043{
3044 int i, j, modes = 0;
3045 struct drm_display_mode *newmode;
3046 struct drm_device *dev = connector->dev;
3047 struct cvt_timing *cvt;
3048 const int rates[] = { 60, 85, 75, 60, 50 };
3049 const u8 empty[3] = { 0, 0, 0 };
a327f6b8 3050
13931579
AJ		 3051 for (i = 0; i < 4; i++) {
3052 int uninitialized_var(width), height;
3053 cvt = &(timing->data.other_data.data.cvt[i]);
f453ba04 3054
13931579 3055 if (!memcmp(cvt->code, empty, 3))
9cf00977 3056 continue;
f453ba04 3057
13931579
AJ		 3058 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
3059 switch (cvt->code[1] & 0x0c) {
3060 case 0x00:
3061 width = height * 4 / 3;
3062 break;
3063 case 0x04:
3064 width = height * 16 / 9;
3065 break;
3066 case 0x08:
3067 width = height * 16 / 10;
3068 break;
3069 case 0x0c:
3070 width = height * 15 / 9;
3071 break;
3072 }
3073
3074 for (j = 1; j < 5; j++) {
3075 if (cvt->code[2] & (1 << j)) {
3076 newmode = drm_cvt_mode(dev, width, height,
3077 rates[j], j == 0,
3078 false, false);
3079 if (newmode) {
3080 drm_mode_probed_add(connector, newmode);
3081 modes++;
3082 }
3083 }
3084 }
f453ba04
DA		 3085 }
3086
3087 return modes;
3088}
9cf00977 3089
13931579
AJ		 3090static void
3091do_cvt_mode(struct detailed_timing *timing, void *c)
882f0219 3092{
13931579 3093 struct detailed_mode_closure *closure = c;
882f0219 3094
a7a131ac
VS		 3095 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_CVT_3BYTE))
3096 return;
3097
3098 closure->modes += drm_cvt_modes(closure->connector, timing);
13931579 3099}
882f0219 3100
13931579
AJ		 3101static int
3102add_cvt_modes(struct drm_connector *connector, struct edid *edid)
4d23f484 3103{
13931579 3104 struct detailed_mode_closure closure = {
d456ea2e
JL		 3105 .connector = connector,
3106 .edid = edid,
13931579 3107 };
882f0219 3108
13931579
AJ		 3109 if (version_greater(edid, 1, 2))
3110 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
882f0219 3111
13931579 3112 /* XXX should also look for CVT codes in VTB blocks */
882f0219 3113
13931579
AJ		 3114 return closure.modes;
3115}
3116
fa3a7340
VS		 3117static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
3118
13931579
AJ		 3119static void
3120do_detailed_mode(struct detailed_timing *timing, void *c)
3121{
3122 struct detailed_mode_closure *closure = c;
3123 struct drm_display_mode *newmode;
3124
f447dd1f
VS		 3125 if (!is_detailed_timing_descriptor((const u8 *)timing))
3126 return;
3127
3128 newmode = drm_mode_detailed(closure->connector->dev,
3129 closure->edid, timing,
3130 closure->quirks);
3131 if (!newmode)
3132 return;
13931579 3133
f447dd1f
VS		 3134 if (closure->preferred)
3135 newmode->type |= DRM_MODE_TYPE_PREFERRED;
13931579 3136
f447dd1f
VS		 3137 /*
3138 * Detailed modes are limited to 10kHz pixel clock resolution,
3139 * so fix up anything that looks like CEA/HDMI mode, but the clock
3140 * is just slightly off.
3141 */
3142 fixup_detailed_cea_mode_clock(newmode);
fa3a7340 3143
f447dd1f
VS		 3144 drm_mode_probed_add(closure->connector, newmode);
3145 closure->modes++;
3146 closure->preferred = false;
13931579 3147}
882f0219 3148
13931579
AJ		 3149/*
3150 * add_detailed_modes - Add modes from detailed timings
3151 * @connector: attached connector
3152 * @edid: EDID block to scan
3153 * @quirks: quirks to apply
3154 */
3155static int
3156add_detailed_modes(struct drm_connector *connector, struct edid *edid,
3157 u32 quirks)
3158{
3159 struct detailed_mode_closure closure = {
d456ea2e
JL		 3160 .connector = connector,
3161 .edid = edid,
c2925bde 3162 .preferred = true,
d456ea2e 3163 .quirks = quirks,
13931579
AJ		 3164 };
3165
3166 if (closure.preferred && !version_greater(edid, 1, 3))
3167 closure.preferred =
3168 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
3169
3170 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
3171
3172 return closure.modes;
882f0219 3173}
f453ba04 3174
8fe9790d 3175#define AUDIO_BLOCK 0x01
54ac76f8 3176#define VIDEO_BLOCK 0x02
f23c20c8 3177#define VENDOR_BLOCK 0x03
76adaa34 3178#define SPEAKER_BLOCK 0x04
e85959d6 3179#define HDR_STATIC_METADATA_BLOCK 0x6
87563fc0
SS		 3180#define USE_EXTENDED_TAG 0x07
3181#define EXT_VIDEO_CAPABILITY_BLOCK 0x00
832d4f2f
SS		 3182#define EXT_VIDEO_DATA_BLOCK_420 0x0E
3183#define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F
8fe9790d 3184#define EDID_BASIC_AUDIO (1 << 6)
a988bc72
LPC		 3185#define EDID_CEA_YCRCB444 (1 << 5)
3186#define EDID_CEA_YCRCB422 (1 << 4)
b1edd6a6 3187#define EDID_CEA_VCDB_QS (1 << 6)
8fe9790d 3188
d4e4a31d 3189/*
8fe9790d 3190 * Search EDID for CEA extension block.
f23c20c8 3191 */
170178fe 3192static u8 *drm_find_edid_extension(const struct edid *edid, int ext_id)
f23c20c8 3193{
8fe9790d
ZW		 3194 u8 *edid_ext = NULL;
3195 int i;
f23c20c8
ML		 3196
3197 /* No EDID or EDID extensions */
3198 if (edid == NULL || edid->extensions == 0)
8fe9790d 3199 return NULL;
f23c20c8 3200
f23c20c8 3201 /* Find CEA extension */
7466f4cc 3202 for (i = 0; i < edid->extensions; i++) {
8fe9790d 3203 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
40d9b043 3204 if (edid_ext[0] == ext_id)
f23c20c8
ML		 3205 break;
3206 }
3207
7466f4cc 3208 if (i == edid->extensions)
8fe9790d
ZW		 3209 return NULL;
3210
3211 return edid_ext;
3212}
3213
40d9b043 3214
170178fe 3215static u8 *drm_find_displayid_extension(const struct edid *edid)
40d9b043
DA		 3216{
3217 return drm_find_edid_extension(edid, DISPLAYID_EXT);
3218}
3219
e28ad544
AR		 3220static u8 *drm_find_cea_extension(const struct edid *edid)
3221{
3222 int ret;
3223 int idx = 1;
3224 int length = EDID_LENGTH;
3225 struct displayid_block *block;
3226 u8 *cea;
3227 u8 *displayid;
3228
3229 /* Look for a top level CEA extension block */
3230 cea = drm_find_edid_extension(edid, CEA_EXT);
3231 if (cea)
3232 return cea;
3233
3234 /* CEA blocks can also be found embedded in a DisplayID block */
3235 displayid = drm_find_displayid_extension(edid);
3236 if (!displayid)
3237 return NULL;
3238
3239 ret = validate_displayid(displayid, length, idx);
3240 if (ret)
3241 return NULL;
3242
3243 idx += sizeof(struct displayid_hdr);
3244 for_each_displayid_db(displayid, block, idx, length) {
3245 if (block->tag == DATA_BLOCK_CTA) {
3246 cea = (u8 *)block;
3247 break;
3248 }
3249 }
3250
3251 return cea;
3252}
3253
e1cf35b9 3254static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic)
7befe621 3255{
9212f8ee
VS		 3256 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127);
3257 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219);
3258
8c1b2bd9
VS		 3259 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1))
3260 return &edid_cea_modes_1[vic - 1];
f7655d42
VS		 3261 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193))
3262 return &edid_cea_modes_193[vic - 193];
7befe621
VS		 3263 return NULL;
3264}
3265
3266static u8 cea_num_vics(void)
3267{
f7655d42 3268 return 193 + ARRAY_SIZE(edid_cea_modes_193);
7befe621
VS		 3269}
3270
3271static u8 cea_next_vic(u8 vic)
3272{
8c1b2bd9 3273 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1))
f7655d42
VS		 3274 vic = 193;
3275 return vic;
7befe621
VS		 3276}
3277
e6e79209
VS		 3278/*
3279 * Calculate the alternate clock for the CEA mode
3280 * (60Hz vs. 59.94Hz etc.)
3281 */
3282static unsigned int
3283cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
3284{
3285 unsigned int clock = cea_mode->clock;
3286
3287 if (cea_mode->vrefresh % 6 != 0)
3288 return clock;
3289
3290 /*
3291 * edid_cea_modes contains the 59.94Hz
3292 * variant for 240 and 480 line modes,
3293 * and the 60Hz variant otherwise.
3294 */
3295 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
9afd808c 3296 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
e6e79209 3297 else
9afd808c 3298 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
e6e79209
VS		 3299
3300 return clock;
3301}
3302
c45a4e46
VS		 3303static bool
3304cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
3305{
3306 /*
3307 * For certain VICs the spec allows the vertical
3308 * front porch to vary by one or two lines.
3309 *
3310 * cea_modes[] stores the variant with the shortest
3311 * vertical front porch. We can adjust the mode to
3312 * get the other variants by simply increasing the
3313 * vertical front porch length.
3314 */
7befe621
VS		 3315 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 ||
3316 cea_mode_for_vic(9)->vtotal != 262 ||
3317 cea_mode_for_vic(12)->vtotal != 262 ||
3318 cea_mode_for_vic(13)->vtotal != 262 ||
3319 cea_mode_for_vic(23)->vtotal != 312 ||
3320 cea_mode_for_vic(24)->vtotal != 312 ||
3321 cea_mode_for_vic(27)->vtotal != 312 ||
3322 cea_mode_for_vic(28)->vtotal != 312);
c45a4e46
VS		 3323
3324 if (((vic == 8 || vic == 9 ||
3325 vic == 12 || vic == 13) && mode->vtotal < 263) ||
3326 ((vic == 23 || vic == 24 ||
3327 vic == 27 || vic == 28) && mode->vtotal < 314)) {
3328 mode->vsync_start++;
3329 mode->vsync_end++;
3330 mode->vtotal++;
3331
3332 return true;
3333 }
3334
3335 return false;
3336}
3337
4c6bcf44
VS		 3338static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
3339 unsigned int clock_tolerance)
3340{
357768cc 3341 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 3342 u8 vic;
4c6bcf44
VS		 3343
3344 if (!to_match->clock)
3345 return 0;
3346
357768cc
VS		 3347 if (to_match->picture_aspect_ratio)
3348 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3349
7befe621
VS		 3350 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
3351 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic);
4c6bcf44
VS		 3352 unsigned int clock1, clock2;
3353
3354 /* Check both 60Hz and 59.94Hz */
c45a4e46
VS		 3355 clock1 = cea_mode.clock;
3356 clock2 = cea_mode_alternate_clock(&cea_mode);
4c6bcf44
VS		 3357
3358 if (abs(to_match->clock - clock1) > clock_tolerance &&
3359 abs(to_match->clock - clock2) > clock_tolerance)
3360 continue;
3361
c45a4e46 3362 do {
357768cc 3363 if (drm_mode_match(to_match, &cea_mode, match_flags))
c45a4e46
VS		 3364 return vic;
3365 } while (cea_mode_alternate_timings(vic, &cea_mode));
4c6bcf44
VS		 3366 }
3367
3368 return 0;
3369}
3370
18316c8c
TR		 3371/**
3372 * drm_match_cea_mode - look for a CEA mode matching given mode
3373 * @to_match: display mode
3374 *
db6cf833 3375 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
18316c8c 3376 * mode.
a4799037 3377 */
18316c8c 3378u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
a4799037 3379{
357768cc 3380 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 3381 u8 vic;
a4799037 3382
a90b590e
VS		 3383 if (!to_match->clock)
3384 return 0;
3385
357768cc
VS		 3386 if (to_match->picture_aspect_ratio)
3387 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3388
7befe621
VS		 3389 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
3390 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic);
a90b590e
VS		 3391 unsigned int clock1, clock2;
3392
a90b590e 3393 /* Check both 60Hz and 59.94Hz */
c45a4e46
VS		 3394 clock1 = cea_mode.clock;
3395 clock2 = cea_mode_alternate_clock(&cea_mode);
a4799037 3396
c45a4e46
VS		 3397 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
3398 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
3399 continue;
3400
3401 do {
357768cc 3402 if (drm_mode_match(to_match, &cea_mode, match_flags))
c45a4e46
VS		 3403 return vic;
3404 } while (cea_mode_alternate_timings(vic, &cea_mode));
a4799037 3405 }
c45a4e46 3406
a4799037
SM		 3407 return 0;
3408}
3409EXPORT_SYMBOL(drm_match_cea_mode);
3410
d9278b4c
JN		 3411static bool drm_valid_cea_vic(u8 vic)
3412{
7befe621 3413 return cea_mode_for_vic(vic) != NULL;
d9278b4c
JN		 3414}
3415
28c03a44 3416static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
0967e6a5 3417{
7befe621
VS		 3418 const struct drm_display_mode *mode = cea_mode_for_vic(video_code);
3419
3420 if (mode)
3421 return mode->picture_aspect_ratio;
3422
3423 return HDMI_PICTURE_ASPECT_NONE;
0967e6a5 3424}
0967e6a5 3425
d2b43473
WL		 3426static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code)
3427{
3428 return edid_4k_modes[video_code].picture_aspect_ratio;
3429}
3430
3f2f6533
LD		 3431/*
3432 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
3433 * specific block).
3f2f6533
LD		 3434 */
3435static unsigned int
3436hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
3437{
3f2f6533
LD		 3438 return cea_mode_alternate_clock(hdmi_mode);
3439}
3440
4c6bcf44
VS		 3441static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
3442 unsigned int clock_tolerance)
3443{
357768cc 3444 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 3445 u8 vic;
4c6bcf44
VS		 3446
3447 if (!to_match->clock)
3448 return 0;
3449
d2b43473
WL		 3450 if (to_match->picture_aspect_ratio)
3451 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3452
d9278b4c
JN		 3453 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3454 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4c6bcf44
VS		 3455 unsigned int clock1, clock2;
3456
3457 /* Make sure to also match alternate clocks */
3458 clock1 = hdmi_mode->clock;
3459 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3460
3461 if (abs(to_match->clock - clock1) > clock_tolerance &&
3462 abs(to_match->clock - clock2) > clock_tolerance)
3463 continue;
3464
357768cc 3465 if (drm_mode_match(to_match, hdmi_mode, match_flags))
d9278b4c 3466 return vic;
4c6bcf44
VS		 3467 }
3468
3469 return 0;
3470}
3471
3f2f6533
LD		 3472/*
3473 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
3474 * @to_match: display mode
3475 *
3476 * An HDMI mode is one defined in the HDMI vendor specific block.
3477 *
3478 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
3479 */
3480static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
3481{
357768cc 3482 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 3483 u8 vic;
3f2f6533
LD		 3484
3485 if (!to_match->clock)
3486 return 0;
3487
d2b43473
WL		 3488 if (to_match->picture_aspect_ratio)
3489 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3490
d9278b4c
JN		 3491 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3492 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3f2f6533
LD		 3493 unsigned int clock1, clock2;
3494
3495 /* Make sure to also match alternate clocks */
3496 clock1 = hdmi_mode->clock;
3497 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3498
3499 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
3500 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
357768cc 3501 drm_mode_match(to_match, hdmi_mode, match_flags))
d9278b4c 3502 return vic;
3f2f6533
LD		 3503 }
3504 return 0;
3505}
3506
d9278b4c
JN		 3507static bool drm_valid_hdmi_vic(u8 vic)
3508{
3509 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
3510}
3511
e6e79209
VS		 3512static int
3513add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
3514{
3515 struct drm_device *dev = connector->dev;
3516 struct drm_display_mode *mode, *tmp;
3517 LIST_HEAD(list);
3518 int modes = 0;
3519
3520 /* Don't add CEA modes if the CEA extension block is missing */
3521 if (!drm_find_cea_extension(edid))
3522 return 0;
3523
3524 /*
3525 * Go through all probed modes and create a new mode
3526 * with the alternate clock for certain CEA modes.
3527 */
3528 list_for_each_entry(mode, &connector->probed_modes, head) {
3f2f6533 3529 const struct drm_display_mode *cea_mode = NULL;
e6e79209 3530 struct drm_display_mode *newmode;
d9278b4c 3531 u8 vic = drm_match_cea_mode(mode);
e6e79209
VS		 3532 unsigned int clock1, clock2;
3533
d9278b4c 3534 if (drm_valid_cea_vic(vic)) {
7befe621 3535 cea_mode = cea_mode_for_vic(vic);
3f2f6533
LD		 3536 clock2 = cea_mode_alternate_clock(cea_mode);
3537 } else {
d9278b4c
JN		 3538 vic = drm_match_hdmi_mode(mode);
3539 if (drm_valid_hdmi_vic(vic)) {
3540 cea_mode = &edid_4k_modes[vic];
3f2f6533
LD		 3541 clock2 = hdmi_mode_alternate_clock(cea_mode);
3542 }
3543 }
e6e79209 3544
3f2f6533
LD		 3545 if (!cea_mode)
3546 continue;
e6e79209
VS		 3547
3548 clock1 = cea_mode->clock;
e6e79209
VS		 3549
3550 if (clock1 == clock2)
3551 continue;
3552
3553 if (mode->clock != clock1 && mode->clock != clock2)
3554 continue;
3555
3556 newmode = drm_mode_duplicate(dev, cea_mode);
3557 if (!newmode)
3558 continue;
3559
27130212
DL		 3560 /* Carry over the stereo flags */
3561 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
3562
e6e79209
VS		 3563 /*
3564 * The current mode could be either variant. Make
3565 * sure to pick the "other" clock for the new mode.
3566 */
3567 if (mode->clock != clock1)
3568 newmode->clock = clock1;
3569 else
3570 newmode->clock = clock2;
3571
3572 list_add_tail(&newmode->head, &list);
3573 }
3574
3575 list_for_each_entry_safe(mode, tmp, &list, head) {
3576 list_del(&mode->head);
3577 drm_mode_probed_add(connector, mode);
3578 modes++;
3579 }
3580
3581 return modes;
3582}
a4799037 3583
8ec6e075
SS		 3584static u8 svd_to_vic(u8 svd)
3585{
3586 /* 0-6 bit vic, 7th bit native mode indicator */
3587 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
3588 return svd & 127;
3589
3590 return svd;
3591}
3592
aff04ace
TW		 3593static struct drm_display_mode *
3594drm_display_mode_from_vic_index(struct drm_connector *connector,
3595 const u8 *video_db, u8 video_len,
3596 u8 video_index)
54ac76f8
CS		 3597{
3598 struct drm_device *dev = connector->dev;
aff04ace 3599 struct drm_display_mode *newmode;
d9278b4c 3600 u8 vic;
54ac76f8 3601
aff04ace
TW		 3602 if (video_db == NULL || video_index >= video_len)
3603 return NULL;
3604
3605 /* CEA modes are numbered 1..127 */
8ec6e075 3606 vic = svd_to_vic(video_db[video_index]);
d9278b4c 3607 if (!drm_valid_cea_vic(vic))
aff04ace
TW		 3608 return NULL;
3609
7befe621 3610 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
409bbf1e
DL		 3611 if (!newmode)
3612 return NULL;
3613
aff04ace
TW		 3614 newmode->vrefresh = 0;
3615
3616 return newmode;
3617}
3618
832d4f2f
SS		 3619/*
3620 * do_y420vdb_modes - Parse YCBCR 420 only modes
3621 * @connector: connector corresponding to the HDMI sink
3622 * @svds: start of the data block of CEA YCBCR 420 VDB
3623 * @len: length of the CEA YCBCR 420 VDB
3624 *
3625 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
3626 * which contains modes which can be supported in YCBCR 420
3627 * output format only.
3628 */
3629static int do_y420vdb_modes(struct drm_connector *connector,
3630 const u8 *svds, u8 svds_len)
3631{
3632 int modes = 0, i;
3633 struct drm_device *dev = connector->dev;
3634 struct drm_display_info *info = &connector->display_info;
3635 struct drm_hdmi_info *hdmi = &info->hdmi;
3636
3637 for (i = 0; i < svds_len; i++) {
3638 u8 vic = svd_to_vic(svds[i]);
3639 struct drm_display_mode *newmode;
3640
3641 if (!drm_valid_cea_vic(vic))
3642 continue;
3643
7befe621 3644 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
832d4f2f
SS		 3645 if (!newmode)
3646 break;
3647 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
3648 drm_mode_probed_add(connector, newmode);
3649 modes++;
3650 }
3651
3652 if (modes > 0)
3653 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3654 return modes;
3655}
3656
3657/*
3658 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap
3659 * @connector: connector corresponding to the HDMI sink
3660 * @vic: CEA vic for the video mode to be added in the map
3661 *
3662 * Makes an entry for a videomode in the YCBCR 420 bitmap
3663 */
3664static void
3665drm_add_cmdb_modes(struct drm_connector *connector, u8 svd)
3666{
3667 u8 vic = svd_to_vic(svd);
3668 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3669
3670 if (!drm_valid_cea_vic(vic))
3671 return;
3672
3673 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
3674}
3675
aff04ace
TW		 3676static int
3677do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
3678{
3679 int i, modes = 0;
832d4f2f 3680 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
aff04ace
TW		 3681
3682 for (i = 0; i < len; i++) {
3683 struct drm_display_mode *mode;
3684 mode = drm_display_mode_from_vic_index(connector, db, len, i);
3685 if (mode) {
832d4f2f
SS		 3686 /*
3687 * YCBCR420 capability block contains a bitmap which
3688 * gives the index of CEA modes from CEA VDB, which
3689 * can support YCBCR 420 sampling output also (apart
3690 * from RGB/YCBCR444 etc).
3691 * For example, if the bit 0 in bitmap is set,
3692 * first mode in VDB can support YCBCR420 output too.
3693 * Add YCBCR420 modes only if sink is HDMI 2.0 capable.
3694 */
3695 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i))
3696 drm_add_cmdb_modes(connector, db[i]);
3697
aff04ace
TW		 3698 drm_mode_probed_add(connector, mode);
3699 modes++;
54ac76f8
CS		 3700 }
3701 }
3702
3703 return modes;
3704}
3705
c858cfca
DL		 3706struct stereo_mandatory_mode {
3707 int width, height, vrefresh;
3708 unsigned int flags;
3709};
3710
3711static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
f7e121b7
DL		 3712 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3713 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
c858cfca
DL		 3714 { 1920, 1080, 50,
3715 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3716 { 1920, 1080, 60,
3717 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
f7e121b7
DL		 3718 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3719 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
3720 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3721 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
c858cfca
DL		 3722};
3723
3724static bool
3725stereo_match_mandatory(const struct drm_display_mode *mode,
3726 const struct stereo_mandatory_mode *stereo_mode)
3727{
3728 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
3729
3730 return mode->hdisplay == stereo_mode->width &&
3731 mode->vdisplay == stereo_mode->height &&
3732 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
3733 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
3734}
3735
c858cfca
DL		 3736static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
3737{
3738 struct drm_device *dev = connector->dev;
3739 const struct drm_display_mode *mode;
3740 struct list_head stereo_modes;
f7e121b7 3741 int modes = 0, i;
c858cfca
DL		 3742
3743 INIT_LIST_HEAD(&stereo_modes);
3744
3745 list_for_each_entry(mode, &connector->probed_modes, head) {
f7e121b7
DL		 3746 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
3747 const struct stereo_mandatory_mode *mandatory;
c858cfca
DL		 3748 struct drm_display_mode *new_mode;
3749
f7e121b7
DL		 3750 if (!stereo_match_mandatory(mode,
3751 &stereo_mandatory_modes[i]))
3752 continue;
c858cfca 3753
f7e121b7 3754 mandatory = &stereo_mandatory_modes[i];
c858cfca
DL		 3755 new_mode = drm_mode_duplicate(dev, mode);
3756 if (!new_mode)
3757 continue;
3758
f7e121b7 3759 new_mode->flags |= mandatory->flags;
c858cfca
DL		 3760 list_add_tail(&new_mode->head, &stereo_modes);
3761 modes++;
f7e121b7 3762 }
c858cfca
DL		 3763 }
3764
3765 list_splice_tail(&stereo_modes, &connector->probed_modes);
3766
3767 return modes;
3768}
3769
1deee8d7
DL		 3770static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
3771{
3772 struct drm_device *dev = connector->dev;
3773 struct drm_display_mode *newmode;
3774
d9278b4c 3775 if (!drm_valid_hdmi_vic(vic)) {
1deee8d7
DL		 3776 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
3777 return 0;
3778 }
3779
3780 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
3781 if (!newmode)
3782 return 0;
3783
3784 drm_mode_probed_add(connector, newmode);
3785
3786 return 1;
3787}
3788
fbf46025
TW		 3789static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
3790 const u8 *video_db, u8 video_len, u8 video_index)
3791{
fbf46025
TW		 3792 struct drm_display_mode *newmode;
3793 int modes = 0;
fbf46025
TW		 3794
3795 if (structure & (1 << 0)) {
aff04ace
TW		 3796 newmode = drm_display_mode_from_vic_index(connector, video_db,
3797 video_len,
3798 video_index);
fbf46025
TW		 3799 if (newmode) {
3800 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
3801 drm_mode_probed_add(connector, newmode);
3802 modes++;
3803 }
3804 }
3805 if (structure & (1 << 6)) {
aff04ace
TW		 3806 newmode = drm_display_mode_from_vic_index(connector, video_db,
3807 video_len,
3808 video_index);
fbf46025
TW		 3809 if (newmode) {
3810 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3811 drm_mode_probed_add(connector, newmode);
3812 modes++;
3813 }
3814 }
3815 if (structure & (1 << 8)) {
aff04ace
TW		 3816 newmode = drm_display_mode_from_vic_index(connector, video_db,
3817 video_len,
3818 video_index);
fbf46025 3819 if (newmode) {
89570eeb 3820 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
fbf46025
TW		 3821 drm_mode_probed_add(connector, newmode);
3822 modes++;
3823 }
3824 }
3825
3826 return modes;
3827}
3828
7ebe1963
LD		 3829/*
3830 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
3831 * @connector: connector corresponding to the HDMI sink
3832 * @db: start of the CEA vendor specific block
3833 * @len: length of the CEA block payload, ie. one can access up to db[len]
3834 *
c858cfca
DL		 3835 * Parses the HDMI VSDB looking for modes to add to @connector. This function
3836 * also adds the stereo 3d modes when applicable.
7ebe1963
LD		 3837 */
3838static int
fbf46025
TW		 3839do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
3840 const u8 *video_db, u8 video_len)
7ebe1963 3841{
f1781e9b 3842 struct drm_display_info *info = &connector->display_info;
0e5083aa 3843 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
fbf46025
TW		 3844 u8 vic_len, hdmi_3d_len = 0;
3845 u16 mask;
3846 u16 structure_all;
7ebe1963
LD		 3847
3848 if (len < 8)
3849 goto out;
3850
3851 /* no HDMI_Video_Present */
3852 if (!(db[8] & (1 << 5)))
3853 goto out;
3854
3855 /* Latency_Fields_Present */
3856 if (db[8] & (1 << 7))
3857 offset += 2;
3858
3859 /* I_Latency_Fields_Present */
3860 if (db[8] & (1 << 6))
3861 offset += 2;
3862
3863 /* the declared length is not long enough for the 2 first bytes
3864 * of additional video format capabilities */
c858cfca 3865 if (len < (8 + offset + 2))
7ebe1963
LD		 3866 goto out;
3867
c858cfca
DL		 3868 /* 3D_Present */
3869 offset++;
fbf46025 3870 if (db[8 + offset] & (1 << 7)) {
c858cfca
DL		 3871 modes += add_hdmi_mandatory_stereo_modes(connector);
3872
fbf46025
TW		 3873 /* 3D_Multi_present */
3874 multi_present = (db[8 + offset] & 0x60) >> 5;
3875 }
3876
c858cfca 3877 offset++;
7ebe1963 3878 vic_len = db[8 + offset] >> 5;
fbf46025 3879 hdmi_3d_len = db[8 + offset] & 0x1f;
7ebe1963
LD		 3880
3881 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
7ebe1963
LD		 3882 u8 vic;
3883
3884 vic = db[9 + offset + i];
1deee8d7 3885 modes += add_hdmi_mode(connector, vic);
7ebe1963 3886 }
fbf46025
TW		 3887 offset += 1 + vic_len;
3888
0e5083aa
TW		 3889 if (multi_present == 1)
3890 multi_len = 2;
3891 else if (multi_present == 2)
3892 multi_len = 4;
3893 else
3894 multi_len = 0;
fbf46025 3895
0e5083aa 3896 if (len < (8 + offset + hdmi_3d_len - 1))
fbf46025
TW		 3897 goto out;
3898
0e5083aa 3899 if (hdmi_3d_len < multi_len)
fbf46025
TW		 3900 goto out;
3901
0e5083aa
TW		 3902 if (multi_present == 1 || multi_present == 2) {
3903 /* 3D_Structure_ALL */
3904 structure_all = (db[8 + offset] << 8) | db[9 + offset];
fbf46025 3905
0e5083aa
TW		 3906 /* check if 3D_MASK is present */
3907 if (multi_present == 2)
3908 mask = (db[10 + offset] << 8) | db[11 + offset];
3909 else
3910 mask = 0xffff;
3911
3912 for (i = 0; i < 16; i++) {
3913 if (mask & (1 << i))
3914 modes += add_3d_struct_modes(connector,
3915 structure_all,
3916 video_db,
3917 video_len, i);
3918 }
3919 }
3920
3921 offset += multi_len;
3922
3923 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
3924 int vic_index;
3925 struct drm_display_mode *newmode = NULL;
3926 unsigned int newflag = 0;
3927 bool detail_present;
3928
3929 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
3930
3931 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
3932 break;
3933
3934 /* 2D_VIC_order_X */
3935 vic_index = db[8 + offset + i] >> 4;
3936
3937 /* 3D_Structure_X */
3938 switch (db[8 + offset + i] & 0x0f) {
3939 case 0:
3940 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
3941 break;
3942 case 6:
3943 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3944 break;
3945 case 8:
3946 /* 3D_Detail_X */
3947 if ((db[9 + offset + i] >> 4) == 1)
3948 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3949 break;
3950 }
3951
3952 if (newflag != 0) {
3953 newmode = drm_display_mode_from_vic_index(connector,
3954 video_db,
3955 video_len,
3956 vic_index);
3957
3958 if (newmode) {
3959 newmode->flags |= newflag;
3960 drm_mode_probed_add(connector, newmode);
3961 modes++;
3962 }
3963 }
3964
3965 if (detail_present)
3966 i++;
fbf46025 3967 }
7ebe1963
LD		 3968
3969out:
f1781e9b
VS		 3970 if (modes > 0)
3971 info->has_hdmi_infoframe = true;
7ebe1963
LD		 3972 return modes;
3973}
3974
9e50b9d5
VS		 3975static int
3976cea_db_payload_len(const u8 *db)
3977{
3978 return db[0] & 0x1f;
3979}
3980
87563fc0
SS		 3981static int
3982cea_db_extended_tag(const u8 *db)
3983{
3984 return db[1];
3985}
3986
9e50b9d5
VS		 3987static int
3988cea_db_tag(const u8 *db)
3989{
3990 return db[0] >> 5;
3991}
3992
3993static int
3994cea_revision(const u8 *cea)
3995{
5036c0d0
VS		 3996 /*
3997 * FIXME is this correct for the DispID variant?
3998 * The DispID spec doesn't really specify whether
3999 * this is the revision of the CEA extension or
4000 * the DispID CEA data block. And the only value
4001 * given as an example is 0.
4002 */
9e50b9d5
VS		 4003 return cea[1];
4004}
4005
4006static int
4007cea_db_offsets(const u8 *cea, int *start, int *end)
4008{
e28ad544
AR		 4009 /* DisplayID CTA extension blocks and top-level CEA EDID
4010 * block header definitions differ in the following bytes:
4011 * 1) Byte 2 of the header specifies length differently,
4012 * 2) Byte 3 is only present in the CEA top level block.
4013 *
4014 * The different definitions for byte 2 follow.
4015 *
4016 * DisplayID CTA extension block defines byte 2 as:
4017 * Number of payload bytes
4018 *
4019 * CEA EDID block defines byte 2 as:
4020 * Byte number (decimal) within this block where the 18-byte
4021 * DTDs begin. If no non-DTD data is present in this extension
4022 * block, the value should be set to 04h (the byte after next).
4023 * If set to 00h, there are no DTDs present in this block and
4024 * no non-DTD data.
4025 */
4026 if (cea[0] == DATA_BLOCK_CTA) {
6e8a942b
VS		 4027 /*
4028 * for_each_displayid_db() has already verified
4029 * that these stay within expected bounds.
4030 */
e28ad544
AR		 4031 *start = 3;
4032 *end = *start + cea[2];
4033 } else if (cea[0] == CEA_EXT) {
4034 /* Data block offset in CEA extension block */
4035 *start = 4;
4036 *end = cea[2];
4037 if (*end == 0)
4038 *end = 127;
4039 if (*end < 4 || *end > 127)
4040 return -ERANGE;
4041 } else {
c7581a41 4042 return -EOPNOTSUPP;
e28ad544
AR		 4043 }
4044
9e50b9d5
VS		 4045 return 0;
4046}
4047
7ebe1963
LD		 4048static bool cea_db_is_hdmi_vsdb(const u8 *db)
4049{
4050 int hdmi_id;
4051
4052 if (cea_db_tag(db) != VENDOR_BLOCK)
4053 return false;
4054
4055 if (cea_db_payload_len(db) < 5)
4056 return false;
4057
4058 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
4059
6cb3b7f1 4060 return hdmi_id == HDMI_IEEE_OUI;
7ebe1963
LD		 4061}
4062
50dd1bd1
TR		 4063static bool cea_db_is_hdmi_forum_vsdb(const u8 *db)
4064{
4065 unsigned int oui;
4066
4067 if (cea_db_tag(db) != VENDOR_BLOCK)
4068 return false;
4069
4070 if (cea_db_payload_len(db) < 7)
4071 return false;
4072
4073 oui = db[3] << 16 | db[2] << 8 | db[1];
4074
4075 return oui == HDMI_FORUM_IEEE_OUI;
4076}
4077
1581b2df
VS		 4078static bool cea_db_is_vcdb(const u8 *db)
4079{
4080 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4081 return false;
4082
4083 if (cea_db_payload_len(db) != 2)
4084 return false;
4085
4086 if (cea_db_extended_tag(db) != EXT_VIDEO_CAPABILITY_BLOCK)
4087 return false;
4088
4089 return true;
4090}
4091
832d4f2f
SS		 4092static bool cea_db_is_y420cmdb(const u8 *db)
4093{
4094 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4095 return false;
4096
4097 if (!cea_db_payload_len(db))
4098 return false;
4099
4100 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB)
4101 return false;
4102
4103 return true;
4104}
4105
4106static bool cea_db_is_y420vdb(const u8 *db)
4107{
4108 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4109 return false;
4110
4111 if (!cea_db_payload_len(db))
4112 return false;
4113
4114 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420)
4115 return false;
4116
4117 return true;
4118}
4119
9e50b9d5
VS		 4120#define for_each_cea_db(cea, i, start, end) \
4121 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
4122
832d4f2f
SS		 4123static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector,
4124 const u8 *db)
4125{
4126 struct drm_display_info *info = &connector->display_info;
4127 struct drm_hdmi_info *hdmi = &info->hdmi;
4128 u8 map_len = cea_db_payload_len(db) - 1;
4129 u8 count;
4130 u64 map = 0;
4131
4132 if (map_len == 0) {
4133 /* All CEA modes support ycbcr420 sampling also.*/
4134 hdmi->y420_cmdb_map = U64_MAX;
4135 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
4136 return;
4137 }
4138
4139 /*
4140 * This map indicates which of the existing CEA block modes
4141 * from VDB can support YCBCR420 output too. So if bit=0 is
4142 * set, first mode from VDB can support YCBCR420 output too.
4143 * We will parse and keep this map, before parsing VDB itself
4144 * to avoid going through the same block again and again.
4145 *
4146 * Spec is not clear about max possible size of this block.
4147 * Clamping max bitmap block size at 8 bytes. Every byte can
4148 * address 8 CEA modes, in this way this map can address
4149 * 8*8 = first 64 SVDs.
4150 */
4151 if (WARN_ON_ONCE(map_len > 8))
4152 map_len = 8;
4153
4154 for (count = 0; count < map_len; count++)
4155 map |= (u64)db[2 + count] << (8 * count);
4156
4157 if (map)
4158 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
4159
4160 hdmi->y420_cmdb_map = map;
4161}
4162
54ac76f8
CS		 4163static int
4164add_cea_modes(struct drm_connector *connector, struct edid *edid)
4165{
13ac3f55 4166 const u8 *cea = drm_find_cea_extension(edid);
fbf46025
TW		 4167 const u8 *db, *hdmi = NULL, *video = NULL;
4168 u8 dbl, hdmi_len, video_len = 0;
54ac76f8
CS		 4169 int modes = 0;
4170
9e50b9d5
VS		 4171 if (cea && cea_revision(cea) >= 3) {
4172 int i, start, end;
4173
4174 if (cea_db_offsets(cea, &start, &end))
4175 return 0;
4176
4177 for_each_cea_db(cea, i, start, end) {
4178 db = &cea[i];
4179 dbl = cea_db_payload_len(db);
4180
fbf46025
TW		 4181 if (cea_db_tag(db) == VIDEO_BLOCK) {
4182 video = db + 1;
4183 video_len = dbl;
4184 modes += do_cea_modes(connector, video, dbl);
832d4f2f 4185 } else if (cea_db_is_hdmi_vsdb(db)) {
c858cfca
DL		 4186 hdmi = db;
4187 hdmi_len = dbl;
832d4f2f
SS		 4188 } else if (cea_db_is_y420vdb(db)) {
4189 const u8 *vdb420 = &db[2];
4190
4191 /* Add 4:2:0(only) modes present in EDID */
4192 modes += do_y420vdb_modes(connector,
4193 vdb420,
4194 dbl - 1);
c858cfca 4195 }
54ac76f8
CS		 4196 }
4197 }
4198
c858cfca
DL		 4199 /*
4200 * We parse the HDMI VSDB after having added the cea modes as we will
4201 * be patching their flags when the sink supports stereo 3D.
4202 */
4203 if (hdmi)
fbf46025
TW		 4204 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
4205 video_len);
c858cfca 4206
54ac76f8
CS		 4207 return modes;
4208}
4209
fa3a7340
VS		 4210static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
4211{
4212 const struct drm_display_mode *cea_mode;
4213 int clock1, clock2, clock;
d9278b4c 4214 u8 vic;
fa3a7340
VS		 4215 const char *type;
4216
4c6bcf44
VS		 4217 /*
4218 * allow 5kHz clock difference either way to account for
4219 * the 10kHz clock resolution limit of detailed timings.
4220 */
d9278b4c
JN		 4221 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
4222 if (drm_valid_cea_vic(vic)) {
fa3a7340 4223 type = "CEA";
7befe621 4224 cea_mode = cea_mode_for_vic(vic);
fa3a7340
VS		 4225 clock1 = cea_mode->clock;
4226 clock2 = cea_mode_alternate_clock(cea_mode);
4227 } else {
d9278b4c
JN		 4228 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
4229 if (drm_valid_hdmi_vic(vic)) {
fa3a7340 4230 type = "HDMI";
d9278b4c 4231 cea_mode = &edid_4k_modes[vic];
fa3a7340
VS		 4232 clock1 = cea_mode->clock;
4233 clock2 = hdmi_mode_alternate_clock(cea_mode);
4234 } else {
4235 return;
4236 }
4237 }
4238
4239 /* pick whichever is closest */
4240 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
4241 clock = clock1;
4242 else
4243 clock = clock2;
4244
4245 if (mode->clock == clock)
4246 return;
4247
4248 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
d9278b4c 4249 type, vic, mode->clock, clock);
fa3a7340
VS		 4250 mode->clock = clock;
4251}
4252
e85959d6
US		 4253static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db)
4254{
4255 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4256 return false;
4257
4258 if (db[1] != HDR_STATIC_METADATA_BLOCK)
4259 return false;
4260
4261 if (cea_db_payload_len(db) < 3)
4262 return false;
4263
4264 return true;
4265}
4266
4267static uint8_t eotf_supported(const u8 *edid_ext)
4268{
4269 return edid_ext[2] &
4270 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
4271 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
b5e3eed1
VS		 4272 BIT(HDMI_EOTF_SMPTE_ST2084) |
4273 BIT(HDMI_EOTF_BT_2100_HLG));
e85959d6
US		 4274}
4275
4276static uint8_t hdr_metadata_type(const u8 *edid_ext)
4277{
4278 return edid_ext[3] &
4279 BIT(HDMI_STATIC_METADATA_TYPE1);
4280}
4281
4282static void
4283drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
4284{
4285 u16 len;
4286
4287 len = cea_db_payload_len(db);
4288
4289 connector->hdr_sink_metadata.hdmi_type1.eotf =
4290 eotf_supported(db);
4291 connector->hdr_sink_metadata.hdmi_type1.metadata_type =
4292 hdr_metadata_type(db);
4293
4294 if (len >= 4)
4295 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4];
4296 if (len >= 5)
4297 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5];
4298 if (len >= 6)
4299 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6];
4300}
4301
76adaa34 4302static void
23ebf8b9 4303drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
76adaa34 4304{
8504072a 4305 u8 len = cea_db_payload_len(db);
76adaa34 4306
f7da7785
JN		 4307 if (len >= 6 && (db[6] & (1 << 7)))
4308 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
8504072a
VS		 4309 if (len >= 8) {
4310 connector->latency_present[0] = db[8] >> 7;
4311 connector->latency_present[1] = (db[8] >> 6) & 1;
4312 }
4313 if (len >= 9)
4314 connector->video_latency[0] = db[9];
4315 if (len >= 10)
4316 connector->audio_latency[0] = db[10];
4317 if (len >= 11)
4318 connector->video_latency[1] = db[11];
4319 if (len >= 12)
4320 connector->audio_latency[1] = db[12];
76adaa34 4321
23ebf8b9
VS		 4322 DRM_DEBUG_KMS("HDMI: latency present %d %d, "
4323 "video latency %d %d, "
4324 "audio latency %d %d\n",
4325 connector->latency_present[0],
4326 connector->latency_present[1],
4327 connector->video_latency[0],
4328 connector->video_latency[1],
4329 connector->audio_latency[0],
4330 connector->audio_latency[1]);
76adaa34
WF		 4331}
4332
4333static void
4334monitor_name(struct detailed_timing *t, void *data)
4335{
a7a131ac
VS		 4336 if (!is_display_descriptor((const u8 *)t, EDID_DETAIL_MONITOR_NAME))
4337 return;
4338
4339 *(u8 **)data = t->data.other_data.data.str.str;
14f77fdd
VS		 4340}
4341
59f7c0fa
JB		 4342static int get_monitor_name(struct edid *edid, char name[13])
4343{
4344 char *edid_name = NULL;
4345 int mnl;
4346
4347 if (!edid || !name)
4348 return 0;
4349
4350 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name);
4351 for (mnl = 0; edid_name && mnl < 13; mnl++) {
4352 if (edid_name[mnl] == 0x0a)
4353 break;
4354
4355 name[mnl] = edid_name[mnl];
4356 }
4357
4358 return mnl;
4359}
4360
4361/**
4362 * drm_edid_get_monitor_name - fetch the monitor name from the edid
4363 * @edid: monitor EDID information
4364 * @name: pointer to a character array to hold the name of the monitor
4365 * @bufsize: The size of the name buffer (should be at least 14 chars.)
4366 *
4367 */
4368void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize)
4369{
4370 int name_length;
4371 char buf[13];
4d23f484 4372
59f7c0fa
JB		 4373 if (bufsize <= 0)
4374 return;
4375
4376 name_length = min(get_monitor_name(edid, buf), bufsize - 1);
4377 memcpy(name, buf, name_length);
4378 name[name_length] = '\0';
4379}
4380EXPORT_SYMBOL(drm_edid_get_monitor_name);
4381
42750d39
JN		 4382static void clear_eld(struct drm_connector *connector)
4383{
4384 memset(connector->eld, 0, sizeof(connector->eld));
4385
4386 connector->latency_present[0] = false;
4387 connector->latency_present[1] = false;
4388 connector->video_latency[0] = 0;
4389 connector->audio_latency[0] = 0;
4390 connector->video_latency[1] = 0;
4391 connector->audio_latency[1] = 0;
4392}
4393
79436a1c 4394/*
76adaa34
WF		 4395 * drm_edid_to_eld - build ELD from EDID
4396 * @connector: connector corresponding to the HDMI/DP sink
4397 * @edid: EDID to parse
4398 *
db6cf833 4399 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
1d1c3665 4400 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
76adaa34 4401 */
79436a1c 4402static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
76adaa34
WF		 4403{
4404 uint8_t *eld = connector->eld;
4405 u8 *cea;
76adaa34 4406 u8 *db;
7c018782 4407 int total_sad_count = 0;
76adaa34
WF		 4408 int mnl;
4409 int dbl;
4410
42750d39 4411 clear_eld(connector);
85c91580 4412
e9bd0b84
JN		 4413 if (!edid)
4414 return;
4415
76adaa34
WF		 4416 cea = drm_find_cea_extension(edid);
4417 if (!cea) {
4418 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
4419 return;
4420 }
4421
f7da7785
JN		 4422 mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
4423 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]);
59f7c0fa 4424
f7da7785
JN		 4425 eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT;
4426 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
76adaa34 4427
f7da7785 4428 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
76adaa34 4429
f7da7785
JN		 4430 eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0];
4431 eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1];
4432 eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0];
4433 eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1];
76adaa34 4434
9e50b9d5
VS		 4435 if (cea_revision(cea) >= 3) {
4436 int i, start, end;
4437
4438 if (cea_db_offsets(cea, &start, &end)) {
4439 start = 0;
4440 end = 0;
4441 }
4442
4443 for_each_cea_db(cea, i, start, end) {
4444 db = &cea[i];
4445 dbl = cea_db_payload_len(db);
4446
4447 switch (cea_db_tag(db)) {
7c018782
VS		 4448 int sad_count;
4449
a0ab734d
CS		 4450 case AUDIO_BLOCK:
4451 /* Audio Data Block, contains SADs */
7c018782
VS		 4452 sad_count = min(dbl / 3, 15 - total_sad_count);
4453 if (sad_count >= 1)
f7da7785 4454 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
7c018782
VS		 4455 &db[1], sad_count * 3);
4456 total_sad_count += sad_count;
a0ab734d
CS		 4457 break;
4458 case SPEAKER_BLOCK:
9e50b9d5
VS		 4459 /* Speaker Allocation Data Block */
4460 if (dbl >= 1)
f7da7785 4461 eld[DRM_ELD_SPEAKER] = db[1];
a0ab734d
CS		 4462 break;
4463 case VENDOR_BLOCK:
4464 /* HDMI Vendor-Specific Data Block */
14f77fdd 4465 if (cea_db_is_hdmi_vsdb(db))
23ebf8b9 4466 drm_parse_hdmi_vsdb_audio(connector, db);
a0ab734d
CS		 4467 break;
4468 default:
4469 break;
4470 }
76adaa34 4471 }
9e50b9d5 4472 }
f7da7785 4473 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
76adaa34 4474
1d1c3665
JN		 4475 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
4476 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4477 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
4478 else
4479 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
76adaa34 4480
938fd8aa
JN		 4481 eld[DRM_ELD_BASELINE_ELD_LEN] =
4482 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
4483
4484 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
7c018782 4485 drm_eld_size(eld), total_sad_count);
76adaa34 4486}
76adaa34 4487
fe214163
RM		 4488/**
4489 * drm_edid_to_sad - extracts SADs from EDID
4490 * @edid: EDID to parse
4491 * @sads: pointer that will be set to the extracted SADs
4492 *
4493 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
fe214163 4494 *
db6cf833
TR		 4495 * Note: The returned pointer needs to be freed using kfree().
4496 *
4497 * Return: The number of found SADs or negative number on error.
fe214163
RM		 4498 */
4499int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
4500{
4501 int count = 0;
4502 int i, start, end, dbl;
4503 u8 *cea;
4504
4505 cea = drm_find_cea_extension(edid);
4506 if (!cea) {
4507 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
42908007 4508 return 0;
fe214163
RM		 4509 }
4510
4511 if (cea_revision(cea) < 3) {
4512 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
42908007 4513 return 0;
fe214163
RM		 4514 }
4515
4516 if (cea_db_offsets(cea, &start, &end)) {
4517 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4518 return -EPROTO;
4519 }
4520
4521 for_each_cea_db(cea, i, start, end) {
4522 u8 *db = &cea[i];
4523
4524 if (cea_db_tag(db) == AUDIO_BLOCK) {
4525 int j;
4526 dbl = cea_db_payload_len(db);
4527
4528 count = dbl / 3; /* SAD is 3B */
4529 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
4530 if (!*sads)
4531 return -ENOMEM;
4532 for (j = 0; j < count; j++) {
4533 u8 *sad = &db[1 + j * 3];
4534
4535 (*sads)[j].format = (sad[0] & 0x78) >> 3;
4536 (*sads)[j].channels = sad[0] & 0x7;
4537 (*sads)[j].freq = sad[1] & 0x7F;
4538 (*sads)[j].byte2 = sad[2];
4539 }
4540 break;
4541 }
4542 }
4543
4544 return count;
4545}
4546EXPORT_SYMBOL(drm_edid_to_sad);
4547
d105f476
AD		 4548/**
4549 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
4550 * @edid: EDID to parse
4551 * @sadb: pointer to the speaker block
4552 *
4553 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
d105f476 4554 *
db6cf833
TR		 4555 * Note: The returned pointer needs to be freed using kfree().
4556 *
4557 * Return: The number of found Speaker Allocation Blocks or negative number on
4558 * error.
d105f476
AD		 4559 */
4560int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
4561{
4562 int count = 0;
4563 int i, start, end, dbl;
4564 const u8 *cea;
4565
4566 cea = drm_find_cea_extension(edid);
4567 if (!cea) {
4568 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
42908007 4569 return 0;
d105f476
AD		 4570 }
4571
4572 if (cea_revision(cea) < 3) {
4573 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
42908007 4574 return 0;
d105f476
AD		 4575 }
4576
4577 if (cea_db_offsets(cea, &start, &end)) {
4578 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4579 return -EPROTO;
4580 }
4581
4582 for_each_cea_db(cea, i, start, end) {
4583 const u8 *db = &cea[i];
4584
4585 if (cea_db_tag(db) == SPEAKER_BLOCK) {
4586 dbl = cea_db_payload_len(db);
4587
4588 /* Speaker Allocation Data Block */
4589 if (dbl == 3) {
89086bca 4590 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
618e3776
AD		 4591 if (!*sadb)
4592 return -ENOMEM;
d105f476
AD		 4593 count = dbl;
4594 break;
4595 }
4596 }
4597 }
4598
4599 return count;
4600}
4601EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
4602
76adaa34 4603/**
db6cf833 4604 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
76adaa34
WF		 4605 * @connector: connector associated with the HDMI/DP sink
4606 * @mode: the display mode
db6cf833
TR		 4607 *
4608 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
4609 * the sink doesn't support audio or video.
76adaa34
WF		 4610 */
4611int drm_av_sync_delay(struct drm_connector *connector,
3a818d35 4612 const struct drm_display_mode *mode)
76adaa34
WF		 4613{
4614 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
4615 int a, v;
4616
4617 if (!connector->latency_present[0])
4618 return 0;
4619 if (!connector->latency_present[1])
4620 i = 0;
4621
4622 a = connector->audio_latency[i];
4623 v = connector->video_latency[i];
4624
4625 /*
4626 * HDMI/DP sink doesn't support audio or video?
4627 */
4628 if (a == 255 || v == 255)
4629 return 0;
4630
4631 /*
4632 * Convert raw EDID values to millisecond.
4633 * Treat unknown latency as 0ms.
4634 */
4635 if (a)
4636 a = min(2 * (a - 1), 500);
4637 if (v)
4638 v = min(2 * (v - 1), 500);
4639
4640 return max(v - a, 0);
4641}
4642EXPORT_SYMBOL(drm_av_sync_delay);
4643
8fe9790d 4644/**
db6cf833 4645 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
8fe9790d
ZW		 4646 * @edid: monitor EDID information
4647 *
4648 * Parse the CEA extension according to CEA-861-B.
db6cf833
TR		 4649 *
4650 * Return: True if the monitor is HDMI, false if not or unknown.
8fe9790d
ZW		 4651 */
4652bool drm_detect_hdmi_monitor(struct edid *edid)
4653{
4654 u8 *edid_ext;
14f77fdd 4655 int i;
8fe9790d 4656 int start_offset, end_offset;
8fe9790d
ZW		 4657
4658 edid_ext = drm_find_cea_extension(edid);
4659 if (!edid_ext)
14f77fdd 4660 return false;
f23c20c8 4661
9e50b9d5 4662 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
14f77fdd 4663 return false;
f23c20c8
ML		 4664
4665 /*
4666 * Because HDMI identifier is in Vendor Specific Block,
4667 * search it from all data blocks of CEA extension.
4668 */
9e50b9d5 4669 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
14f77fdd
VS		 4670 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
4671 return true;
f23c20c8
ML		 4672 }
4673
14f77fdd 4674 return false;
f23c20c8
ML		 4675}
4676EXPORT_SYMBOL(drm_detect_hdmi_monitor);
4677
8fe9790d
ZW		 4678/**
4679 * drm_detect_monitor_audio - check monitor audio capability
fc66811c 4680 * @edid: EDID block to scan
8fe9790d
ZW		 4681 *
4682 * Monitor should have CEA extension block.
4683 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
4684 * audio' only. If there is any audio extension block and supported
4685 * audio format, assume at least 'basic audio' support, even if 'basic
4686 * audio' is not defined in EDID.
4687 *
db6cf833 4688 * Return: True if the monitor supports audio, false otherwise.
8fe9790d
ZW		 4689 */
4690bool drm_detect_monitor_audio(struct edid *edid)
4691{
4692 u8 *edid_ext;
4693 int i, j;
4694 bool has_audio = false;
4695 int start_offset, end_offset;
4696
4697 edid_ext = drm_find_cea_extension(edid);
4698 if (!edid_ext)
4699 goto end;
4700
4701 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
4702
4703 if (has_audio) {
4704 DRM_DEBUG_KMS("Monitor has basic audio support\n");
4705 goto end;
4706 }
4707
9e50b9d5
VS		 4708 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4709 goto end;
8fe9790d 4710
9e50b9d5
VS		 4711 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4712 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
8fe9790d 4713 has_audio = true;
9e50b9d5 4714 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
8fe9790d
ZW		 4715 DRM_DEBUG_KMS("CEA audio format %d\n",
4716 (edid_ext[i + j] >> 3) & 0xf);
4717 goto end;
4718 }
4719 }
4720end:
4721 return has_audio;
4722}
4723EXPORT_SYMBOL(drm_detect_monitor_audio);
4724
b1edd6a6 4725
c8127cf0
VS		 4726/**
4727 * drm_default_rgb_quant_range - default RGB quantization range
4728 * @mode: display mode
4729 *
4730 * Determine the default RGB quantization range for the mode,
4731 * as specified in CEA-861.
4732 *
4733 * Return: The default RGB quantization range for the mode
4734 */
4735enum hdmi_quantization_range
4736drm_default_rgb_quant_range(const struct drm_display_mode *mode)
4737{
4738 /* All CEA modes other than VIC 1 use limited quantization range. */
4739 return drm_match_cea_mode(mode) > 1 ?
4740 HDMI_QUANTIZATION_RANGE_LIMITED :
4741 HDMI_QUANTIZATION_RANGE_FULL;
4742}
4743EXPORT_SYMBOL(drm_default_rgb_quant_range);
4744
1581b2df
VS		 4745static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
4746{
4747 struct drm_display_info *info = &connector->display_info;
4748
4749 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]);
4750
4751 if (db[2] & EDID_CEA_VCDB_QS)
4752 info->rgb_quant_range_selectable = true;
4753}
4754
e6a9a2c3
SS		 4755static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
4756 const u8 *db)
4757{
4758 u8 dc_mask;
4759 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4760
4761 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
9068e02f 4762 hdmi->y420_dc_modes = dc_mask;
e6a9a2c3
SS		 4763}
4764
afa1c763
SS		 4765static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector,
4766 const u8 *hf_vsdb)
4767{
62c58af3
SS		 4768 struct drm_display_info *display = &connector->display_info;
4769 struct drm_hdmi_info *hdmi = &display->hdmi;
afa1c763 4770
f1781e9b
VS		 4771 display->has_hdmi_infoframe = true;
4772
afa1c763
SS		 4773 if (hf_vsdb[6] & 0x80) {
4774 hdmi->scdc.supported = true;
4775 if (hf_vsdb[6] & 0x40)
4776 hdmi->scdc.read_request = true;
4777 }
62c58af3
SS		 4778
4779 /*
4780 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
4781 * And as per the spec, three factors confirm this:
4782 * * Availability of a HF-VSDB block in EDID (check)
4783 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
4784 * * SCDC support available (let's check)
4785 * Lets check it out.
4786 */
4787
4788 if (hf_vsdb[5]) {
4789 /* max clock is 5000 KHz times block value */
4790 u32 max_tmds_clock = hf_vsdb[5] * 5000;
4791 struct drm_scdc *scdc = &hdmi->scdc;
4792
4793 if (max_tmds_clock > 340000) {
4794 display->max_tmds_clock = max_tmds_clock;
4795 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
4796 display->max_tmds_clock);
4797 }
4798
4799 if (scdc->supported) {
4800 scdc->scrambling.supported = true;
4801
dbe2d2bf 4802 /* Few sinks support scrambling for clocks < 340M */
62c58af3
SS		 4803 if ((hf_vsdb[6] & 0x8))
4804 scdc->scrambling.low_rates = true;
4805 }
4806 }
e6a9a2c3
SS		 4807
4808 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb);
afa1c763
SS		 4809}
4810
1cea146a
VS		 4811static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
4812 const u8 *hdmi)
d0c94692 4813{
1826750f 4814 struct drm_display_info *info = &connector->display_info;
d0c94692
MK		 4815 unsigned int dc_bpc = 0;
4816
1cea146a
VS		 4817 /* HDMI supports at least 8 bpc */
4818 info->bpc = 8;
d0c94692 4819
1cea146a
VS		 4820 if (cea_db_payload_len(hdmi) < 6)
4821 return;
4822
4823 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
4824 dc_bpc = 10;
4825 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
4826 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
4827 connector->name);
4828 }
4829
4830 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
4831 dc_bpc = 12;
4832 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
4833 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
4834 connector->name);
4835 }
4836
4837 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
4838 dc_bpc = 16;
4839 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
4840 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
4841 connector->name);
4842 }
4843
4844 if (dc_bpc == 0) {
4845 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
4846 connector->name);
4847 return;
4848 }
4849
4850 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
4851 connector->name, dc_bpc);
4852 info->bpc = dc_bpc;
d0c94692
MK		 4853
4854 /*
1cea146a
VS		 4855 * Deep color support mandates RGB444 support for all video
4856 * modes and forbids YCRCB422 support for all video modes per
4857 * HDMI 1.3 spec.
d0c94692 4858 */
1cea146a 4859 info->color_formats = DRM_COLOR_FORMAT_RGB444;
d0c94692 4860
1cea146a
VS		 4861 /* YCRCB444 is optional according to spec. */
4862 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
4863 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4864 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
4865 connector->name);
4866 }
d0c94692 4867
1cea146a
VS		 4868 /*
4869 * Spec says that if any deep color mode is supported at all,
4870 * then deep color 36 bit must be supported.
4871 */
4872 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
4873 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
4874 connector->name);
4875 }
4876}
d0c94692 4877
23ebf8b9
VS		 4878static void
4879drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
4880{
4881 struct drm_display_info *info = &connector->display_info;
4882 u8 len = cea_db_payload_len(db);
4883
4884 if (len >= 6)
4885 info->dvi_dual = db[6] & 1;
4886 if (len >= 7)
4887 info->max_tmds_clock = db[7] * 5000;
4888
4889 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
4890 "max TMDS clock %d kHz\n",
4891 info->dvi_dual,
4892 info->max_tmds_clock);
4893
4894 drm_parse_hdmi_deep_color_info(connector, db);
4895}
4896
1cea146a 4897static void drm_parse_cea_ext(struct drm_connector *connector,
170178fe 4898 const struct edid *edid)
1cea146a
VS		 4899{
4900 struct drm_display_info *info = &connector->display_info;
4901 const u8 *edid_ext;
4902 int i, start, end;
d0c94692 4903
1cea146a
VS		 4904 edid_ext = drm_find_cea_extension(edid);
4905 if (!edid_ext)
4906 return;
d0c94692 4907
1cea146a 4908 info->cea_rev = edid_ext[1];
d0c94692 4909
1cea146a
VS		 4910 /* The existence of a CEA block should imply RGB support */
4911 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4912 if (edid_ext[3] & EDID_CEA_YCRCB444)
4913 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4914 if (edid_ext[3] & EDID_CEA_YCRCB422)
4915 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4916
4917 if (cea_db_offsets(edid_ext, &start, &end))
4918 return;
4919
4920 for_each_cea_db(edid_ext, i, start, end) {
4921 const u8 *db = &edid_ext[i];
4922
23ebf8b9
VS		 4923 if (cea_db_is_hdmi_vsdb(db))
4924 drm_parse_hdmi_vsdb_video(connector, db);
afa1c763
SS		 4925 if (cea_db_is_hdmi_forum_vsdb(db))
4926 drm_parse_hdmi_forum_vsdb(connector, db);
832d4f2f
SS		 4927 if (cea_db_is_y420cmdb(db))
4928 drm_parse_y420cmdb_bitmap(connector, db);
1581b2df
VS		 4929 if (cea_db_is_vcdb(db))
4930 drm_parse_vcdb(connector, db);
e85959d6
US		 4931 if (cea_db_is_hdmi_hdr_metadata_block(db))
4932 drm_parse_hdr_metadata_block(connector, db);
1cea146a 4933 }
d0c94692
MK		 4934}
4935
170178fe
KP		 4936/* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
4937 * all of the values which would have been set from EDID
4938 */
4939void
4940drm_reset_display_info(struct drm_connector *connector)
4941{
4942 struct drm_display_info *info = &connector->display_info;
4943
4944 info->width_mm = 0;
4945 info->height_mm = 0;
4946
4947 info->bpc = 0;
4948 info->color_formats = 0;
4949 info->cea_rev = 0;
4950 info->max_tmds_clock = 0;
4951 info->dvi_dual = false;
4952 info->has_hdmi_infoframe = false;
1581b2df 4953 info->rgb_quant_range_selectable = false;
1f6b8eef 4954 memset(&info->hdmi, 0, sizeof(info->hdmi));
170178fe
KP		 4955
4956 info->non_desktop = 0;
4957}
170178fe
KP		 4958
4959u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid)
3b11228b 4960{
1826750f 4961 struct drm_display_info *info = &connector->display_info;
ebec9a7b 4962
170178fe
KP		 4963 u32 quirks = edid_get_quirks(edid);
4964
1f6b8eef
VS		 4965 drm_reset_display_info(connector);
4966
3b11228b
JB		 4967 info->width_mm = edid->width_cm * 10;
4968 info->height_mm = edid->height_cm * 10;
4969
66660d4c
DA		 4970 info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP);
4971
170178fe
KP		 4972 DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop);
4973
a988bc72 4974 if (edid->revision < 3)
170178fe 4975 return quirks;
3b11228b
JB		 4976
4977 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
170178fe 4978 return quirks;
3b11228b 4979
1cea146a 4980 drm_parse_cea_ext(connector, edid);
d0c94692 4981
210a021d
MK		 4982 /*
4983 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
4984 *
4985 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
4986 * tells us to assume 8 bpc color depth if the EDID doesn't have
4987 * extensions which tell otherwise.
4988 */
3bde449f
VS		 4989 if (info->bpc == 0 && edid->revision == 3 &&
4990 edid->input & DRM_EDID_DIGITAL_DFP_1_X) {
210a021d
MK		 4991 info->bpc = 8;
4992 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
4993 connector->name, info->bpc);
4994 }
4995
a988bc72
LPC		 4996 /* Only defined for 1.4 with digital displays */
4997 if (edid->revision < 4)
170178fe 4998 return quirks;
a988bc72 4999
3b11228b
JB		 5000 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
5001 case DRM_EDID_DIGITAL_DEPTH_6:
5002 info->bpc = 6;
5003 break;
5004 case DRM_EDID_DIGITAL_DEPTH_8:
5005 info->bpc = 8;
5006 break;
5007 case DRM_EDID_DIGITAL_DEPTH_10:
5008 info->bpc = 10;
5009 break;
5010 case DRM_EDID_DIGITAL_DEPTH_12:
5011 info->bpc = 12;
5012 break;
5013 case DRM_EDID_DIGITAL_DEPTH_14:
5014 info->bpc = 14;
5015 break;
5016 case DRM_EDID_DIGITAL_DEPTH_16:
5017 info->bpc = 16;
5018 break;
5019 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
5020 default:
5021 info->bpc = 0;
5022 break;
5023 }
da05a5a7 5024
d0c94692 5025 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
25933820 5026 connector->name, info->bpc);
d0c94692 5027
a988bc72 5028 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
ee58808d
LPC		 5029 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
5030 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
5031 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
5032 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
170178fe 5033 return quirks;
3b11228b
JB		 5034}
5035
c9729177
DA		 5036static int validate_displayid(u8 *displayid, int length, int idx)
5037{
5038 int i;
5039 u8 csum = 0;
5040 struct displayid_hdr *base;
5041
5042 base = (struct displayid_hdr *)&displayid[idx];
5043
5044 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",
5045 base->rev, base->bytes, base->prod_id, base->ext_count);
5046
5047 if (base->bytes + 5 > length - idx)
5048 return -EINVAL;
5049 for (i = idx; i <= base->bytes + 5; i++) {
5050 csum += displayid[i];
5051 }
5052 if (csum) {
813a7878 5053 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum);
c9729177
DA		 5054 return -EINVAL;
5055 }
5056 return 0;
5057}
5058
a39ed680
DA		 5059static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
5060 struct displayid_detailed_timings_1 *timings)
5061{
5062 struct drm_display_mode *mode;
5063 unsigned pixel_clock = (timings->pixel_clock[0] |
5064 (timings->pixel_clock[1] << 8) |
5065 (timings->pixel_clock[2] << 16));
5066 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
5067 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
5068 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
5069 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
5070 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
5071 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
5072 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
5073 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
5074 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
5075 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
5076 mode = drm_mode_create(dev);
5077 if (!mode)
5078 return NULL;
5079
5080 mode->clock = pixel_clock * 10;
5081 mode->hdisplay = hactive;
5082 mode->hsync_start = mode->hdisplay + hsync;
5083 mode->hsync_end = mode->hsync_start + hsync_width;
5084 mode->htotal = mode->hdisplay + hblank;
5085
5086 mode->vdisplay = vactive;
5087 mode->vsync_start = mode->vdisplay + vsync;
5088 mode->vsync_end = mode->vsync_start + vsync_width;
5089 mode->vtotal = mode->vdisplay + vblank;
5090
5091 mode->flags = 0;
5092 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
5093 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
5094 mode->type = DRM_MODE_TYPE_DRIVER;
5095
5096 if (timings->flags & 0x80)
5097 mode->type |= DRM_MODE_TYPE_PREFERRED;
5098 mode->vrefresh = drm_mode_vrefresh(mode);
5099 drm_mode_set_name(mode);
5100
5101 return mode;
5102}
5103
5104static int add_displayid_detailed_1_modes(struct drm_connector *connector,
5105 struct displayid_block *block)
5106{
5107 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
5108 int i;
5109 int num_timings;
5110 struct drm_display_mode *newmode;
5111 int num_modes = 0;
5112 /* blocks must be multiple of 20 bytes length */
5113 if (block->num_bytes % 20)
5114 return 0;
5115
5116 num_timings = block->num_bytes / 20;
5117 for (i = 0; i < num_timings; i++) {
5118 struct displayid_detailed_timings_1 *timings = &det->timings[i];
5119
5120 newmode = drm_mode_displayid_detailed(connector->dev, timings);
5121 if (!newmode)
5122 continue;
5123
5124 drm_mode_probed_add(connector, newmode);
5125 num_modes++;
5126 }
5127 return num_modes;
5128}
5129
5130static int add_displayid_detailed_modes(struct drm_connector *connector,
5131 struct edid *edid)
5132{
5133 u8 *displayid;
5134 int ret;
5135 int idx = 1;
5136 int length = EDID_LENGTH;
5137 struct displayid_block *block;
5138 int num_modes = 0;
5139
5140 displayid = drm_find_displayid_extension(edid);
5141 if (!displayid)
5142 return 0;
5143
5144 ret = validate_displayid(displayid, length, idx);
5145 if (ret)
5146 return 0;
5147
5148 idx += sizeof(struct displayid_hdr);
80d42db0 5149 for_each_displayid_db(displayid, block, idx, length) {
a39ed680
DA		 5150 switch (block->tag) {
5151 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
5152 num_modes += add_displayid_detailed_1_modes(connector, block);
5153 break;
5154 }
5155 }
5156 return num_modes;
5157}
5158
f453ba04
DA		 5159/**
5160 * drm_add_edid_modes - add modes from EDID data, if available
5161 * @connector: connector we're probing
db6cf833 5162 * @edid: EDID data
f453ba04 5163 *
b3c6c8bf 5164 * Add the specified modes to the connector's mode list. Also fills out the
c945b8c1
JN		 5165 * &drm_display_info structure and ELD in @connector with any information which
5166 * can be derived from the edid.
f453ba04 5167 *
db6cf833 5168 * Return: The number of modes added or 0 if we couldn't find any.
f453ba04
DA		 5169 */
5170int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
5171{
5172 int num_modes = 0;
5173 u32 quirks;
5174
5175 if (edid == NULL) {
c945b8c1 5176 clear_eld(connector);
f453ba04
DA		 5177 return 0;
5178 }
3c537889 5179 if (!drm_edid_is_valid(edid)) {
c945b8c1 5180 clear_eld(connector);
dcdb1674 5181 dev_warn(connector->dev->dev, "%s: EDID invalid.\n",
25933820 5182 connector->name);
f453ba04
DA		 5183 return 0;
5184 }
5185
c945b8c1
JN		 5186 drm_edid_to_eld(connector, edid);
5187
0f0f8708
SS		 5188 /*
5189 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
5190 * To avoid multiple parsing of same block, lets parse that map
5191 * from sink info, before parsing CEA modes.
5192 */
170178fe 5193 quirks = drm_add_display_info(connector, edid);
0f0f8708 5194
c867df70
AJ		 5195 /*
5196 * EDID spec says modes should be preferred in this order:
5197 * - preferred detailed mode
5198 * - other detailed modes from base block
5199 * - detailed modes from extension blocks
5200 * - CVT 3-byte code modes
5201 * - standard timing codes
5202 * - established timing codes
5203 * - modes inferred from GTF or CVT range information
5204 *
13931579 5205 * We get this pretty much right.
c867df70
AJ		 5206 *
5207 * XXX order for additional mode types in extension blocks?
5208 */
13931579
AJ		 5209 num_modes += add_detailed_modes(connector, edid, quirks);
5210 num_modes += add_cvt_modes(connector, edid);
c867df70
AJ		 5211 num_modes += add_standard_modes(connector, edid);
5212 num_modes += add_established_modes(connector, edid);
54ac76f8 5213 num_modes += add_cea_modes(connector, edid);
e6e79209 5214 num_modes += add_alternate_cea_modes(connector, edid);
a39ed680 5215 num_modes += add_displayid_detailed_modes(connector, edid);
4d53dc0c
VS		 5216 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
5217 num_modes += add_inferred_modes(connector, edid);
f453ba04
DA		 5218
5219 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
5220 edid_fixup_preferred(connector, quirks);
5221
e10aec65
MK		 5222 if (quirks & EDID_QUIRK_FORCE_6BPC)
5223 connector->display_info.bpc = 6;
5224
49d45a31
RM		 5225 if (quirks & EDID_QUIRK_FORCE_8BPC)
5226 connector->display_info.bpc = 8;
5227
e345da82
MK		 5228 if (quirks & EDID_QUIRK_FORCE_10BPC)
5229 connector->display_info.bpc = 10;
5230
bc5b9641
MK		 5231 if (quirks & EDID_QUIRK_FORCE_12BPC)
5232 connector->display_info.bpc = 12;
5233
f453ba04
DA		 5234 return num_modes;
5235}
5236EXPORT_SYMBOL(drm_add_edid_modes);
f0fda0a4
ZY		 5237
5238/**
5239 * drm_add_modes_noedid - add modes for the connectors without EDID
5240 * @connector: connector we're probing
5241 * @hdisplay: the horizontal display limit
5242 * @vdisplay: the vertical display limit
5243 *
5244 * Add the specified modes to the connector's mode list. Only when the
5245 * hdisplay/vdisplay is not beyond the given limit, it will be added.
5246 *
db6cf833 5247 * Return: The number of modes added or 0 if we couldn't find any.
f0fda0a4
ZY		 5248 */
5249int drm_add_modes_noedid(struct drm_connector *connector,
5250 int hdisplay, int vdisplay)
5251{
5252 int i, count, num_modes = 0;
b1f559ec 5253 struct drm_display_mode *mode;
f0fda0a4
ZY		 5254 struct drm_device *dev = connector->dev;
5255
fbb40b28 5256 count = ARRAY_SIZE(drm_dmt_modes);
f0fda0a4
ZY		 5257 if (hdisplay < 0)
5258 hdisplay = 0;
5259 if (vdisplay < 0)
5260 vdisplay = 0;
5261
5262 for (i = 0; i < count; i++) {
b1f559ec 5263 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
f0fda0a4
ZY		 5264 if (hdisplay && vdisplay) {
5265 /*
5266 * Only when two are valid, they will be used to check
5267 * whether the mode should be added to the mode list of
5268 * the connector.
5269 */
5270 if (ptr->hdisplay > hdisplay ||
5271 ptr->vdisplay > vdisplay)
5272 continue;
5273 }
f985dedb
AJ		 5274 if (drm_mode_vrefresh(ptr) > 61)
5275 continue;
f0fda0a4
ZY		 5276 mode = drm_mode_duplicate(dev, ptr);
5277 if (mode) {
5278 drm_mode_probed_add(connector, mode);
5279 num_modes++;
5280 }
5281 }
5282 return num_modes;
5283}
5284EXPORT_SYMBOL(drm_add_modes_noedid);
10a85120 5285
db6cf833
TR		 5286/**
5287 * drm_set_preferred_mode - Sets the preferred mode of a connector
5288 * @connector: connector whose mode list should be processed
5289 * @hpref: horizontal resolution of preferred mode
5290 * @vpref: vertical resolution of preferred mode
5291 *
5292 * Marks a mode as preferred if it matches the resolution specified by @hpref
5293 * and @vpref.
5294 */
3cf70daf
GH		 5295void drm_set_preferred_mode(struct drm_connector *connector,
5296 int hpref, int vpref)
5297{
5298 struct drm_display_mode *mode;
5299
5300 list_for_each_entry(mode, &connector->probed_modes, head) {
db6cf833 5301 if (mode->hdisplay == hpref &&
9d3de138 5302 mode->vdisplay == vpref)
3cf70daf
GH		 5303 mode->type |= DRM_MODE_TYPE_PREFERRED;
5304 }
5305}
5306EXPORT_SYMBOL(drm_set_preferred_mode);
5307
13d0add3
VS		 5308static bool is_hdmi2_sink(struct drm_connector *connector)
5309{
5310 /*
5311 * FIXME: sil-sii8620 doesn't have a connector around when
5312 * we need one, so we have to be prepared for a NULL connector.
5313 */
5314 if (!connector)
5315 return true;
5316
5317 return connector->display_info.hdmi.scdc.supported ||
5318 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420;
5319}
5320
2cdbfd66
US		 5321static inline bool is_eotf_supported(u8 output_eotf, u8 sink_eotf)
5322{
5323 return sink_eotf & BIT(output_eotf);
5324}
5325
5326/**
5327 * drm_hdmi_infoframe_set_hdr_metadata() - fill an HDMI DRM infoframe with
5328 * HDR metadata from userspace
5329 * @frame: HDMI DRM infoframe
6ac98829 5330 * @conn_state: Connector state containing HDR metadata
2cdbfd66
US		 5331 *
5332 * Return: 0 on success or a negative error code on failure.
5333 */
5334int
5335drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame,
5336 const struct drm_connector_state *conn_state)
5337{
5338 struct drm_connector *connector;
5339 struct hdr_output_metadata *hdr_metadata;
5340 int err;
5341
5342 if (!frame || !conn_state)
5343 return -EINVAL;
5344
5345 connector = conn_state->connector;
5346
5347 if (!conn_state->hdr_output_metadata)
5348 return -EINVAL;
5349
5350 hdr_metadata = conn_state->hdr_output_metadata->data;
5351
5352 if (!hdr_metadata || !connector)
5353 return -EINVAL;
5354
5355 /* Sink EOTF is Bit map while infoframe is absolute values */
5356 if (!is_eotf_supported(hdr_metadata->hdmi_metadata_type1.eotf,
5357 connector->hdr_sink_metadata.hdmi_type1.eotf)) {
5358 DRM_DEBUG_KMS("EOTF Not Supported\n");
5359 return -EINVAL;
5360 }
5361
5362 err = hdmi_drm_infoframe_init(frame);
5363 if (err < 0)
5364 return err;
5365
5366 frame->eotf = hdr_metadata->hdmi_metadata_type1.eotf;
5367 frame->metadata_type = hdr_metadata->hdmi_metadata_type1.metadata_type;
5368
5369 BUILD_BUG_ON(sizeof(frame->display_primaries) !=
5370 sizeof(hdr_metadata->hdmi_metadata_type1.display_primaries));
5371 BUILD_BUG_ON(sizeof(frame->white_point) !=
5372 sizeof(hdr_metadata->hdmi_metadata_type1.white_point));
5373
5374 memcpy(&frame->display_primaries,
5375 &hdr_metadata->hdmi_metadata_type1.display_primaries,
5376 sizeof(frame->display_primaries));
5377
5378 memcpy(&frame->white_point,
5379 &hdr_metadata->hdmi_metadata_type1.white_point,
5380 sizeof(frame->white_point));
5381
5382 frame->max_display_mastering_luminance =
5383 hdr_metadata->hdmi_metadata_type1.max_display_mastering_luminance;
5384 frame->min_display_mastering_luminance =
5385 hdr_metadata->hdmi_metadata_type1.min_display_mastering_luminance;
5386 frame->max_fall = hdr_metadata->hdmi_metadata_type1.max_fall;
5387 frame->max_cll = hdr_metadata->hdmi_metadata_type1.max_cll;
5388
5389 return 0;
5390}
5391EXPORT_SYMBOL(drm_hdmi_infoframe_set_hdr_metadata);
5392
949561eb
VS		 5393static u8 drm_mode_hdmi_vic(struct drm_connector *connector,
5394 const struct drm_display_mode *mode)
5395{
5396 bool has_hdmi_infoframe = connector ?
5397 connector->display_info.has_hdmi_infoframe : false;
5398
5399 if (!has_hdmi_infoframe)
5400 return 0;
5401
5402 /* No HDMI VIC when signalling 3D video format */
5403 if (mode->flags & DRM_MODE_FLAG_3D_MASK)
5404 return 0;
5405
5406 return drm_match_hdmi_mode(mode);
5407}
5408
cfd6f8c3
VS		 5409static u8 drm_mode_cea_vic(struct drm_connector *connector,
5410 const struct drm_display_mode *mode)
5411{
cfd6f8c3
VS		 5412 u8 vic;
5413
5414 /*
5415 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
5416 * we should send its VIC in vendor infoframes, else send the
5417 * VIC in AVI infoframes. Lets check if this mode is present in
5418 * HDMI 1.4b 4K modes
5419 */
949561eb 5420 if (drm_mode_hdmi_vic(connector, mode))
cfd6f8c3
VS		 5421 return 0;
5422
5423 vic = drm_match_cea_mode(mode);
5424
5425 /*
5426 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
5427 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
5428 * have to make sure we dont break HDMI 1.4 sinks.
5429 */
5430 if (!is_hdmi2_sink(connector) && vic > 64)
5431 return 0;
5432
5433 return vic;
5434}
5435
10a85120
TR		 5436/**
5437 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
5438 * data from a DRM display mode
5439 * @frame: HDMI AVI infoframe
13d0add3 5440 * @connector: the connector
10a85120
TR		 5441 * @mode: DRM display mode
5442 *
db6cf833 5443 * Return: 0 on success or a negative error code on failure.
10a85120
TR		 5444 */
5445int
5446drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
13d0add3
VS		 5447 struct drm_connector *connector,
5448 const struct drm_display_mode *mode)
10a85120 5449{
a9c266c2 5450 enum hdmi_picture_aspect picture_aspect;
d2b43473 5451 u8 vic, hdmi_vic;
10a85120
TR		 5452 int err;
5453
5454 if (!frame || !mode)
5455 return -EINVAL;
5456
5457 err = hdmi_avi_infoframe_init(frame);
5458 if (err < 0)
5459 return err;
5460
bf02db99
DL		 5461 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
5462 frame->pixel_repeat = 1;
5463
d2b43473
WL		 5464 vic = drm_mode_cea_vic(connector, mode);
5465 hdmi_vic = drm_mode_hdmi_vic(connector, mode);
0c1f528c 5466
10a85120 5467 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
0967e6a5 5468
50525c33
SL		 5469 /*
5470 * As some drivers don't support atomic, we can't use connector state.
5471 * So just initialize the frame with default values, just the same way
5472 * as it's done with other properties here.
5473 */
5474 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
5475 frame->itc = 0;
5476
69ab6d35
VK		 5477 /*
5478 * Populate picture aspect ratio from either
d2b43473 5479 * user input (if specified) or from the CEA/HDMI mode lists.
69ab6d35 5480 */
a9c266c2 5481 picture_aspect = mode->picture_aspect_ratio;
d2b43473
WL		 5482 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) {
5483 if (vic)
5484 picture_aspect = drm_get_cea_aspect_ratio(vic);
5485 else if (hdmi_vic)
5486 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic);
5487 }
0967e6a5 5488
a9c266c2
VS		 5489 /*
5490 * The infoframe can't convey anything but none, 4:3
5491 * and 16:9, so if the user has asked for anything else
5492 * we can only satisfy it by specifying the right VIC.
5493 */
5494 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
d2b43473
WL		 5495 if (vic) {
5496 if (picture_aspect != drm_get_cea_aspect_ratio(vic))
5497 return -EINVAL;
5498 } else if (hdmi_vic) {
5499 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic))
5500 return -EINVAL;
5501 } else {
a9c266c2 5502 return -EINVAL;
d2b43473
WL		 5503 }
5504
a9c266c2
VS		 5505 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
5506 }
5507
d2b43473 5508 frame->video_code = vic;
a9c266c2 5509 frame->picture_aspect = picture_aspect;
10a85120 5510 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
24d01805 5511 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
10a85120
TR		 5512
5513 return 0;
5514}
5515EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
83dd0008 5516
0d68b887
US		 5517/* HDMI Colorspace Spec Definitions */
5518#define FULL_COLORIMETRY_MASK 0x1FF
5519#define NORMAL_COLORIMETRY_MASK 0x3
5520#define EXTENDED_COLORIMETRY_MASK 0x7
5521#define EXTENDED_ACE_COLORIMETRY_MASK 0xF
5522
5523#define C(x) ((x) << 0)
5524#define EC(x) ((x) << 2)
5525#define ACE(x) ((x) << 5)
5526
5527#define HDMI_COLORIMETRY_NO_DATA 0x0
5528#define HDMI_COLORIMETRY_SMPTE_170M_YCC (C(1) | EC(0) | ACE(0))
5529#define HDMI_COLORIMETRY_BT709_YCC (C(2) | EC(0) | ACE(0))
5530#define HDMI_COLORIMETRY_XVYCC_601 (C(3) | EC(0) | ACE(0))
5531#define HDMI_COLORIMETRY_XVYCC_709 (C(3) | EC(1) | ACE(0))
5532#define HDMI_COLORIMETRY_SYCC_601 (C(3) | EC(2) | ACE(0))
5533#define HDMI_COLORIMETRY_OPYCC_601 (C(3) | EC(3) | ACE(0))
5534#define HDMI_COLORIMETRY_OPRGB (C(3) | EC(4) | ACE(0))
5535#define HDMI_COLORIMETRY_BT2020_CYCC (C(3) | EC(5) | ACE(0))
5536#define HDMI_COLORIMETRY_BT2020_RGB (C(3) | EC(6) | ACE(0))
5537#define HDMI_COLORIMETRY_BT2020_YCC (C(3) | EC(6) | ACE(0))
5538#define HDMI_COLORIMETRY_DCI_P3_RGB_D65 (C(3) | EC(7) | ACE(0))
5539#define HDMI_COLORIMETRY_DCI_P3_RGB_THEATER (C(3) | EC(7) | ACE(1))
5540
5541static const u32 hdmi_colorimetry_val[] = {
5542 [DRM_MODE_COLORIMETRY_NO_DATA] = HDMI_COLORIMETRY_NO_DATA,
5543 [DRM_MODE_COLORIMETRY_SMPTE_170M_YCC] = HDMI_COLORIMETRY_SMPTE_170M_YCC,
5544 [DRM_MODE_COLORIMETRY_BT709_YCC] = HDMI_COLORIMETRY_BT709_YCC,
5545 [DRM_MODE_COLORIMETRY_XVYCC_601] = HDMI_COLORIMETRY_XVYCC_601,
5546 [DRM_MODE_COLORIMETRY_XVYCC_709] = HDMI_COLORIMETRY_XVYCC_709,
5547 [DRM_MODE_COLORIMETRY_SYCC_601] = HDMI_COLORIMETRY_SYCC_601,
5548 [DRM_MODE_COLORIMETRY_OPYCC_601] = HDMI_COLORIMETRY_OPYCC_601,
5549 [DRM_MODE_COLORIMETRY_OPRGB] = HDMI_COLORIMETRY_OPRGB,
5550 [DRM_MODE_COLORIMETRY_BT2020_CYCC] = HDMI_COLORIMETRY_BT2020_CYCC,
5551 [DRM_MODE_COLORIMETRY_BT2020_RGB] = HDMI_COLORIMETRY_BT2020_RGB,
5552 [DRM_MODE_COLORIMETRY_BT2020_YCC] = HDMI_COLORIMETRY_BT2020_YCC,
5553};
5554
5555#undef C
5556#undef EC
5557#undef ACE
5558
5559/**
5560 * drm_hdmi_avi_infoframe_colorspace() - fill the HDMI AVI infoframe
5561 * colorspace information
5562 * @frame: HDMI AVI infoframe
5563 * @conn_state: connector state
5564 */
5565void
5566drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame,
5567 const struct drm_connector_state *conn_state)
5568{
5569 u32 colorimetry_val;
5570 u32 colorimetry_index = conn_state->colorspace & FULL_COLORIMETRY_MASK;
5571
5572 if (colorimetry_index >= ARRAY_SIZE(hdmi_colorimetry_val))
5573 colorimetry_val = HDMI_COLORIMETRY_NO_DATA;
5574 else
5575 colorimetry_val = hdmi_colorimetry_val[colorimetry_index];
5576
5577 frame->colorimetry = colorimetry_val & NORMAL_COLORIMETRY_MASK;
5578 /*
5579 * ToDo: Extend it for ACE formats as well. Modify the infoframe
5580 * structure and extend it in drivers/video/hdmi
5581 */
5582 frame->extended_colorimetry = (colorimetry_val >> 2) &
5583 EXTENDED_COLORIMETRY_MASK;
5584}
5585EXPORT_SYMBOL(drm_hdmi_avi_infoframe_colorspace);
5586
a2ce26f8
VS		 5587/**
5588 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
5589 * quantization range information
5590 * @frame: HDMI AVI infoframe
13d0add3 5591 * @connector: the connector
779c4c28 5592 * @mode: DRM display mode
a2ce26f8 5593 * @rgb_quant_range: RGB quantization range (Q)
a2ce26f8
VS		 5594 */
5595void
5596drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
13d0add3 5597 struct drm_connector *connector,
779c4c28 5598 const struct drm_display_mode *mode,
1581b2df 5599 enum hdmi_quantization_range rgb_quant_range)
a2ce26f8 5600{
1581b2df
VS		 5601 const struct drm_display_info *info = &connector->display_info;
5602
a2ce26f8
VS		 5603 /*
5604 * CEA-861:
5605 * "A Source shall not send a non-zero Q value that does not correspond
5606 * to the default RGB Quantization Range for the transmitted Picture
5607 * unless the Sink indicates support for the Q bit in a Video
5608 * Capabilities Data Block."
779c4c28
VS		 5609 *
5610 * HDMI 2.0 recommends sending non-zero Q when it does match the
5611 * default RGB quantization range for the mode, even when QS=0.
a2ce26f8 5612 */
1581b2df 5613 if (info->rgb_quant_range_selectable ||
779c4c28 5614 rgb_quant_range == drm_default_rgb_quant_range(mode))
a2ce26f8
VS		 5615 frame->quantization_range = rgb_quant_range;
5616 else
5617 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
fcc8a22c
VS		 5618
5619 /*
5620 * CEA-861-F:
5621 * "When transmitting any RGB colorimetry, the Source should set the
5622 * YQ-field to match the RGB Quantization Range being transmitted
5623 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
5624 * set YQ=1) and the Sink shall ignore the YQ-field."
9271c0ca
VS		 5625 *
5626 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
5627 * by non-zero YQ when receiving RGB. There doesn't seem to be any
5628 * good way to tell which version of CEA-861 the sink supports, so
5629 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
5630 * on on CEA-861-F.
fcc8a22c 5631 */
13d0add3 5632 if (!is_hdmi2_sink(connector) ||
9271c0ca 5633 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
fcc8a22c
VS		 5634 frame->ycc_quantization_range =
5635 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
5636 else
5637 frame->ycc_quantization_range =
5638 HDMI_YCC_QUANTIZATION_RANGE_FULL;
a2ce26f8
VS		 5639}
5640EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
5641
076d9a5d
VS		 5642/**
5643 * drm_hdmi_avi_infoframe_bars() - fill the HDMI AVI infoframe
5644 * bar information
5645 * @frame: HDMI AVI infoframe
5646 * @conn_state: connector state
5647 */
5648void
5649drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe *frame,
5650 const struct drm_connector_state *conn_state)
5651{
5652 frame->right_bar = conn_state->tv.margins.right;
5653 frame->left_bar = conn_state->tv.margins.left;
5654 frame->top_bar = conn_state->tv.margins.top;
5655 frame->bottom_bar = conn_state->tv.margins.bottom;
5656}
5657EXPORT_SYMBOL(drm_hdmi_avi_infoframe_bars);
5658
4eed4a0a
DL		 5659static enum hdmi_3d_structure
5660s3d_structure_from_display_mode(const struct drm_display_mode *mode)
5661{
5662 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
5663
5664 switch (layout) {
5665 case DRM_MODE_FLAG_3D_FRAME_PACKING:
5666 return HDMI_3D_STRUCTURE_FRAME_PACKING;
5667 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
5668 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
5669 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
5670 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
5671 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
5672 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
5673 case DRM_MODE_FLAG_3D_L_DEPTH:
5674 return HDMI_3D_STRUCTURE_L_DEPTH;
5675 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
5676 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
5677 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
5678 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
5679 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
5680 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
5681 default:
5682 return HDMI_3D_STRUCTURE_INVALID;
5683 }
5684}
5685
83dd0008
LD		 5686/**
5687 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
5688 * data from a DRM display mode
5689 * @frame: HDMI vendor infoframe
f1781e9b 5690 * @connector: the connector
83dd0008
LD		 5691 * @mode: DRM display mode
5692 *
5693 * Note that there's is a need to send HDMI vendor infoframes only when using a
5694 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
5695 * function will return -EINVAL, error that can be safely ignored.
5696 *
db6cf833 5697 * Return: 0 on success or a negative error code on failure.
83dd0008
LD		 5698 */
5699int
5700drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
f1781e9b 5701 struct drm_connector *connector,
83dd0008
LD		 5702 const struct drm_display_mode *mode)
5703{
f1781e9b
VS		 5704 /*
5705 * FIXME: sil-sii8620 doesn't have a connector around when
5706 * we need one, so we have to be prepared for a NULL connector.
5707 */
5708 bool has_hdmi_infoframe = connector ?
5709 connector->display_info.has_hdmi_infoframe : false;
83dd0008 5710 int err;
83dd0008
LD		 5711
5712 if (!frame || !mode)
5713 return -EINVAL;
5714
f1781e9b
VS		 5715 if (!has_hdmi_infoframe)
5716 return -EINVAL;
5717
949561eb
VS		 5718 err = hdmi_vendor_infoframe_init(frame);
5719 if (err < 0)
5720 return err;
4eed4a0a 5721
f1781e9b
VS		 5722 /*
5723 * Even if it's not absolutely necessary to send the infoframe
5724 * (ie.vic==0 and s3d_struct==0) we will still send it if we
5725 * know that the sink can handle it. This is based on a
5726 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
5727 * have trouble realizing that they shuld switch from 3D to 2D
5728 * mode if the source simply stops sending the infoframe when
5729 * it wants to switch from 3D to 2D.
5730 */
949561eb 5731 frame->vic = drm_mode_hdmi_vic(connector, mode);
f1781e9b 5732 frame->s3d_struct = s3d_structure_from_display_mode(mode);
83dd0008
LD		 5733
5734 return 0;
5735}
5736EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
40d9b043 5737
5e546cd5
DA		 5738static int drm_parse_tiled_block(struct drm_connector *connector,
5739 struct displayid_block *block)
5740{
5741 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
5742 u16 w, h;
5743 u8 tile_v_loc, tile_h_loc;
5744 u8 num_v_tile, num_h_tile;
5745 struct drm_tile_group *tg;
5746
5747 w = tile->tile_size[0] | tile->tile_size[1] << 8;
5748 h = tile->tile_size[2] | tile->tile_size[3] << 8;
5749
5750 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
5751 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
5752 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
5753 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
5754
5755 connector->has_tile = true;
5756 if (tile->tile_cap & 0x80)
5757 connector->tile_is_single_monitor = true;
5758
5759 connector->num_h_tile = num_h_tile + 1;
5760 connector->num_v_tile = num_v_tile + 1;
5761 connector->tile_h_loc = tile_h_loc;
5762 connector->tile_v_loc = tile_v_loc;
5763 connector->tile_h_size = w + 1;
5764 connector->tile_v_size = h + 1;
5765
5766 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
5767 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
5768 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
5769 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
5770 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
5771
5772 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
5773 if (!tg) {
5774 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
5775 }
5776 if (!tg)
5777 return -ENOMEM;
5778
5779 if (connector->tile_group != tg) {
5780 /* if we haven't got a pointer,
5781 take the reference, drop ref to old tile group */
5782 if (connector->tile_group) {
5783 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5784 }
5785 connector->tile_group = tg;
5786 } else
5787 /* if same tile group, then release the ref we just took. */
5788 drm_mode_put_tile_group(connector->dev, tg);
5789 return 0;
5790}
5791
40d9b043
DA		 5792static int drm_parse_display_id(struct drm_connector *connector,
5793 u8 *displayid, int length,
5794 bool is_edid_extension)
5795{
5796 /* if this is an EDID extension the first byte will be 0x70 */
5797 int idx = 0;
40d9b043 5798 struct displayid_block *block;
5e546cd5 5799 int ret;
40d9b043
DA		 5800
5801 if (is_edid_extension)
5802 idx = 1;
5803
c9729177
DA		 5804 ret = validate_displayid(displayid, length, idx);
5805 if (ret)
5806 return ret;
40d9b043 5807
3a4a2ea3 5808 idx += sizeof(struct displayid_hdr);
80d42db0 5809 for_each_displayid_db(displayid, block, idx, length) {
3a4a2ea3
TB		 5810 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n",
5811 block->tag, block->rev, block->num_bytes);
5812
5813 switch (block->tag) {
5814 case DATA_BLOCK_TILED_DISPLAY:
5815 ret = drm_parse_tiled_block(connector, block);
5816 if (ret)
5817 return ret;
5818 break;
a39ed680
DA		 5819 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
5820 /* handled in mode gathering code. */
5821 break;
e28ad544
AR		 5822 case DATA_BLOCK_CTA:
5823 /* handled in the cea parser code. */
5824 break;
3a4a2ea3
TB		 5825 default:
5826 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag);
5827 break;
5828 }
40d9b043
DA		 5829 }
5830 return 0;
5831}
5832
5833static void drm_get_displayid(struct drm_connector *connector,
5834 struct edid *edid)
5835{
5836 void *displayid = NULL;
5837 int ret;
5838 connector->has_tile = false;
5839 displayid = drm_find_displayid_extension(edid);
5840 if (!displayid) {
5841 /* drop reference to any tile group we had */
5842 goto out_drop_ref;
5843 }
5844
5845 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true);
5846 if (ret < 0)
5847 goto out_drop_ref;
5848 if (!connector->has_tile)
5849 goto out_drop_ref;
5850 return;
5851out_drop_ref:
5852 if (connector->tile_group) {
5853 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5854 connector->tile_group = NULL;
5855 }
5856 return;
5857}
Linux 6.x block layer and io_uring tree(s)