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drm/display: Move HDMI helpers into display-helper module
[linux-2.6-block.git] / drivers / gpu / drm / drm_edid.c
CommitLineData
f453ba04
DA		 1/*
2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
61e57a8d 5 * Copyright 2010 Red Hat, Inc.
f453ba04
DA		 6 *
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
8 * FB layer.
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 */
9c79edec 30
18a9cbbe 31#include <linux/bitfield.h>
10a85120 32#include <linux/hdmi.h>
f453ba04 33#include <linux/i2c.h>
9c79edec 34#include <linux/kernel.h>
47819ba2 35#include <linux/module.h>
36b73b05 36#include <linux/pci.h>
9c79edec 37#include <linux/slab.h>
5cb8eaa2 38#include <linux/vga_switcheroo.h>
9c79edec
JN		 39
40#include <drm/drm_displayid.h>
41#include <drm/drm_drv.h>
760285e7 42#include <drm/drm_edid.h>
9338203c 43#include <drm/drm_encoder.h>
9c79edec 44#include <drm/drm_print.h>
62c58af3 45#include <drm/drm_scdc_helper.h>
f453ba04 46
969218fe
TI		 47#include "drm_crtc_internal.h"
48
13931579
AJ		 49#define version_greater(edid, maj, min) \
50 (((edid)->version > (maj)) || \
51 ((edid)->version == (maj) && (edid)->revision > (min)))
f453ba04 52
37eab1fe
JN		 53static int oui(u8 first, u8 second, u8 third)
54{
55 return (first << 16) | (second << 8) | third;
56}
57
d1ff6409
AJ		 58#define EDID_EST_TIMINGS 16
59#define EDID_STD_TIMINGS 8
60#define EDID_DETAILED_TIMINGS 4
f453ba04
DA		 61
62/*
63 * EDID blocks out in the wild have a variety of bugs, try to collect
64 * them here (note that userspace may work around broken monitors first,
65 * but fixes should make their way here so that the kernel "just works"
66 * on as many displays as possible).
67 */
68
69/* First detailed mode wrong, use largest 60Hz mode */
70#define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
71/* Reported 135MHz pixel clock is too high, needs adjustment */
72#define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
73/* Prefer the largest mode at 75 Hz */
74#define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
75/* Detail timing is in cm not mm */
76#define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
77/* Detailed timing descriptors have bogus size values, so just take the
78 * maximum size and use that.
79 */
80#define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
f453ba04
DA		 81/* use +hsync +vsync for detailed mode */
82#define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
bc42aabc
AJ		 83/* Force reduced-blanking timings for detailed modes */
84#define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
49d45a31
RM		 85/* Force 8bpc */
86#define EDID_QUIRK_FORCE_8BPC (1 << 8)
bc5b9641
MK		 87/* Force 12bpc */
88#define EDID_QUIRK_FORCE_12BPC (1 << 9)
e10aec65
MK		 89/* Force 6bpc */
90#define EDID_QUIRK_FORCE_6BPC (1 << 10)
e345da82
MK		 91/* Force 10bpc */
92#define EDID_QUIRK_FORCE_10BPC (1 << 11)
66660d4c
DA		 93/* Non desktop display (i.e. HMD) */
94#define EDID_QUIRK_NON_DESKTOP (1 << 12)
3c537889 95
2869f599
PZ		 96#define MICROSOFT_IEEE_OUI 0xca125c
97
13931579
AJ		 98struct detailed_mode_closure {
99 struct drm_connector *connector;
c14e7241 100 const struct edid *edid;
13931579
AJ		 101 bool preferred;
102 u32 quirks;
103 int modes;
104};
f453ba04 105
5c61259e
ZY		 106#define LEVEL_DMT 0
107#define LEVEL_GTF 1
7a374350
AJ		 108#define LEVEL_GTF2 2
109#define LEVEL_CVT 3
5c61259e 110
7d1be0a0 111#define EDID_QUIRK(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _quirks) \
e8de4d55 112{ \
7d1be0a0
DA		 113 .panel_id = drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, \
114 product_id), \
e8de4d55
DA		 115 .quirks = _quirks \
116}
117
23c4cfbd 118static const struct edid_quirk {
e8de4d55 119 u32 panel_id;
f453ba04
DA		 120 u32 quirks;
121} edid_quirk_list[] = {
122 /* Acer AL1706 */
7d1be0a0 123 EDID_QUIRK('A', 'C', 'R', 44358, EDID_QUIRK_PREFER_LARGE_60),
f453ba04 124 /* Acer F51 */
7d1be0a0 125 EDID_QUIRK('A', 'P', 'I', 0x7602, EDID_QUIRK_PREFER_LARGE_60),
f453ba04 126
e10aec65 127 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
7d1be0a0 128 EDID_QUIRK('A', 'E', 'O', 0, EDID_QUIRK_FORCE_6BPC),
e10aec65 129
0711a43b 130 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
7d1be0a0 131 EDID_QUIRK('B', 'O', 'E', 0x78b, EDID_QUIRK_FORCE_6BPC),
0711a43b 132
06998a75 133 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
7d1be0a0 134 EDID_QUIRK('C', 'P', 'T', 0x17df, EDID_QUIRK_FORCE_6BPC),
06998a75 135
25da7504 136 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
7d1be0a0 137 EDID_QUIRK('S', 'D', 'C', 0x3652, EDID_QUIRK_FORCE_6BPC),
25da7504 138
922dceff 139 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
7d1be0a0 140 EDID_QUIRK('B', 'O', 'E', 0x0771, EDID_QUIRK_FORCE_6BPC),
922dceff 141
f453ba04 142 /* Belinea 10 15 55 */
7d1be0a0
DA		 143 EDID_QUIRK('M', 'A', 'X', 1516, EDID_QUIRK_PREFER_LARGE_60),
144 EDID_QUIRK('M', 'A', 'X', 0x77e, EDID_QUIRK_PREFER_LARGE_60),
f453ba04
DA		 145
146 /* Envision Peripherals, Inc. EN-7100e */
7d1be0a0 147 EDID_QUIRK('E', 'P', 'I', 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH),
ba1163de 148 /* Envision EN2028 */
7d1be0a0 149 EDID_QUIRK('E', 'P', 'I', 8232, EDID_QUIRK_PREFER_LARGE_60),
f453ba04
DA		 150
151 /* Funai Electronics PM36B */
7d1be0a0 152 EDID_QUIRK('F', 'C', 'M', 13600, EDID_QUIRK_PREFER_LARGE_75 |
e8de4d55 153 EDID_QUIRK_DETAILED_IN_CM),
f453ba04 154
e345da82 155 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
7d1be0a0 156 EDID_QUIRK('L', 'G', 'D', 764, EDID_QUIRK_FORCE_10BPC),
e345da82 157
f453ba04 158 /* LG Philips LCD LP154W01-A5 */
7d1be0a0
DA		 159 EDID_QUIRK('L', 'P', 'L', 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
160 EDID_QUIRK('L', 'P', 'L', 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
f453ba04 161
f453ba04 162 /* Samsung SyncMaster 205BW. Note: irony */
7d1be0a0 163 EDID_QUIRK('S', 'A', 'M', 541, EDID_QUIRK_DETAILED_SYNC_PP),
f453ba04 164 /* Samsung SyncMaster 22[5-6]BW */
7d1be0a0
DA		 165 EDID_QUIRK('S', 'A', 'M', 596, EDID_QUIRK_PREFER_LARGE_60),
166 EDID_QUIRK('S', 'A', 'M', 638, EDID_QUIRK_PREFER_LARGE_60),
bc42aabc 167
bc5b9641 168 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
7d1be0a0 169 EDID_QUIRK('S', 'N', 'Y', 0x2541, EDID_QUIRK_FORCE_12BPC),
bc5b9641 170
bc42aabc 171 /* ViewSonic VA2026w */
7d1be0a0 172 EDID_QUIRK('V', 'S', 'C', 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING),
118bdbd8
AD		 173
174 /* Medion MD 30217 PG */
7d1be0a0 175 EDID_QUIRK('M', 'E', 'D', 0x7b8, EDID_QUIRK_PREFER_LARGE_75),
49d45a31 176
11bcf5f7 177 /* Lenovo G50 */
7d1be0a0 178 EDID_QUIRK('S', 'D', 'C', 18514, EDID_QUIRK_FORCE_6BPC),
11bcf5f7 179
49d45a31 180 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
7d1be0a0 181 EDID_QUIRK('S', 'E', 'C', 0xd033, EDID_QUIRK_FORCE_8BPC),
36fc5797
TV		 182
183 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
7d1be0a0 184 EDID_QUIRK('E', 'T', 'R', 13896, EDID_QUIRK_FORCE_8BPC),
acb1d8ee 185
30d62d44 186 /* Valve Index Headset */
7d1be0a0
DA		 187 EDID_QUIRK('V', 'L', 'V', 0x91a8, EDID_QUIRK_NON_DESKTOP),
188 EDID_QUIRK('V', 'L', 'V', 0x91b0, EDID_QUIRK_NON_DESKTOP),
189 EDID_QUIRK('V', 'L', 'V', 0x91b1, EDID_QUIRK_NON_DESKTOP),
190 EDID_QUIRK('V', 'L', 'V', 0x91b2, EDID_QUIRK_NON_DESKTOP),
191 EDID_QUIRK('V', 'L', 'V', 0x91b3, EDID_QUIRK_NON_DESKTOP),
192 EDID_QUIRK('V', 'L', 'V', 0x91b4, EDID_QUIRK_NON_DESKTOP),
193 EDID_QUIRK('V', 'L', 'V', 0x91b5, EDID_QUIRK_NON_DESKTOP),
194 EDID_QUIRK('V', 'L', 'V', 0x91b6, EDID_QUIRK_NON_DESKTOP),
195 EDID_QUIRK('V', 'L', 'V', 0x91b7, EDID_QUIRK_NON_DESKTOP),
196 EDID_QUIRK('V', 'L', 'V', 0x91b8, EDID_QUIRK_NON_DESKTOP),
197 EDID_QUIRK('V', 'L', 'V', 0x91b9, EDID_QUIRK_NON_DESKTOP),
198 EDID_QUIRK('V', 'L', 'V', 0x91ba, EDID_QUIRK_NON_DESKTOP),
199 EDID_QUIRK('V', 'L', 'V', 0x91bb, EDID_QUIRK_NON_DESKTOP),
200 EDID_QUIRK('V', 'L', 'V', 0x91bc, EDID_QUIRK_NON_DESKTOP),
201 EDID_QUIRK('V', 'L', 'V', 0x91bd, EDID_QUIRK_NON_DESKTOP),
202 EDID_QUIRK('V', 'L', 'V', 0x91be, EDID_QUIRK_NON_DESKTOP),
203 EDID_QUIRK('V', 'L', 'V', 0x91bf, EDID_QUIRK_NON_DESKTOP),
30d62d44 204
6931317c 205 /* HTC Vive and Vive Pro VR Headsets */
7d1be0a0
DA		 206 EDID_QUIRK('H', 'V', 'R', 0xaa01, EDID_QUIRK_NON_DESKTOP),
207 EDID_QUIRK('H', 'V', 'R', 0xaa02, EDID_QUIRK_NON_DESKTOP),
b3b12ea3 208
5a3f6108 209 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */
7d1be0a0
DA		 210 EDID_QUIRK('O', 'V', 'R', 0x0001, EDID_QUIRK_NON_DESKTOP),
211 EDID_QUIRK('O', 'V', 'R', 0x0003, EDID_QUIRK_NON_DESKTOP),
212 EDID_QUIRK('O', 'V', 'R', 0x0004, EDID_QUIRK_NON_DESKTOP),
213 EDID_QUIRK('O', 'V', 'R', 0x0012, EDID_QUIRK_NON_DESKTOP),
90eda8fc
PZ		 214
215 /* Windows Mixed Reality Headsets */
7d1be0a0 216 EDID_QUIRK('A', 'C', 'R', 0x7fce, EDID_QUIRK_NON_DESKTOP),
7d1be0a0 217 EDID_QUIRK('L', 'E', 'N', 0x0408, EDID_QUIRK_NON_DESKTOP),
7d1be0a0
DA		 218 EDID_QUIRK('F', 'U', 'J', 0x1970, EDID_QUIRK_NON_DESKTOP),
219 EDID_QUIRK('D', 'E', 'L', 0x7fce, EDID_QUIRK_NON_DESKTOP),
220 EDID_QUIRK('S', 'E', 'C', 0x144a, EDID_QUIRK_NON_DESKTOP),
221 EDID_QUIRK('A', 'U', 'S', 0xc102, EDID_QUIRK_NON_DESKTOP),
ccffc9eb
PZ		 222
223 /* Sony PlayStation VR Headset */
7d1be0a0 224 EDID_QUIRK('S', 'N', 'Y', 0x0704, EDID_QUIRK_NON_DESKTOP),
29054230
RP		 225
226 /* Sensics VR Headsets */
7d1be0a0 227 EDID_QUIRK('S', 'E', 'N', 0x1019, EDID_QUIRK_NON_DESKTOP),
29054230
RP		 228
229 /* OSVR HDK and HDK2 VR Headsets */
7d1be0a0 230 EDID_QUIRK('S', 'V', 'R', 0x1019, EDID_QUIRK_NON_DESKTOP),
f453ba04
DA		 231};
232
a6b21831
TR		 233/*
234 * Autogenerated from the DMT spec.
235 * This table is copied from xfree86/modes/xf86EdidModes.c.
236 */
237static const struct drm_display_mode drm_dmt_modes[] = {
24b856b1 238 /* 0x01 - 640x350@85Hz */
a6b21831
TR		 239 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
240 736, 832, 0, 350, 382, 385, 445, 0,
241 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 242 /* 0x02 - 640x400@85Hz */
a6b21831
TR		 243 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
244 736, 832, 0, 400, 401, 404, 445, 0,
245 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 246 /* 0x03 - 720x400@85Hz */
a6b21831
TR		 247 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
248 828, 936, 0, 400, 401, 404, 446, 0,
249 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 250 /* 0x04 - 640x480@60Hz */
a6b21831 251 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
fcf22d05 252 752, 800, 0, 480, 490, 492, 525, 0,
a6b21831 253 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 254 /* 0x05 - 640x480@72Hz */
a6b21831
TR		 255 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
256 704, 832, 0, 480, 489, 492, 520, 0,
257 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 258 /* 0x06 - 640x480@75Hz */
a6b21831
TR		 259 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
260 720, 840, 0, 480, 481, 484, 500, 0,
261 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 262 /* 0x07 - 640x480@85Hz */
a6b21831
TR		 263 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
264 752, 832, 0, 480, 481, 484, 509, 0,
265 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 266 /* 0x08 - 800x600@56Hz */
a6b21831
TR		 267 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
268 896, 1024, 0, 600, 601, 603, 625, 0,
269 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 270 /* 0x09 - 800x600@60Hz */
a6b21831
TR		 271 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
272 968, 1056, 0, 600, 601, 605, 628, 0,
273 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 274 /* 0x0a - 800x600@72Hz */
a6b21831
TR		 275 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
276 976, 1040, 0, 600, 637, 643, 666, 0,
277 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 278 /* 0x0b - 800x600@75Hz */
a6b21831
TR		 279 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
280 896, 1056, 0, 600, 601, 604, 625, 0,
281 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 282 /* 0x0c - 800x600@85Hz */
a6b21831
TR		 283 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
284 896, 1048, 0, 600, 601, 604, 631, 0,
285 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 286 /* 0x0d - 800x600@120Hz RB */
a6b21831
TR		 287 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
288 880, 960, 0, 600, 603, 607, 636, 0,
289 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 290 /* 0x0e - 848x480@60Hz */
a6b21831
TR		 291 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
292 976, 1088, 0, 480, 486, 494, 517, 0,
293 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 294 /* 0x0f - 1024x768@43Hz, interlace */
a6b21831 295 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
735b100f 296 1208, 1264, 0, 768, 768, 776, 817, 0,
a6b21831 297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
fcf22d05 298 DRM_MODE_FLAG_INTERLACE) },
24b856b1 299 /* 0x10 - 1024x768@60Hz */
a6b21831
TR		 300 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
301 1184, 1344, 0, 768, 771, 777, 806, 0,
302 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 303 /* 0x11 - 1024x768@70Hz */
a6b21831
TR		 304 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
305 1184, 1328, 0, 768, 771, 777, 806, 0,
306 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 307 /* 0x12 - 1024x768@75Hz */
a6b21831
TR		 308 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
309 1136, 1312, 0, 768, 769, 772, 800, 0,
310 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 311 /* 0x13 - 1024x768@85Hz */
a6b21831
TR		 312 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
313 1168, 1376, 0, 768, 769, 772, 808, 0,
314 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 315 /* 0x14 - 1024x768@120Hz RB */
a6b21831
TR		 316 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
317 1104, 1184, 0, 768, 771, 775, 813, 0,
318 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 319 /* 0x15 - 1152x864@75Hz */
a6b21831
TR		 320 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
321 1344, 1600, 0, 864, 865, 868, 900, 0,
322 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
bfcd74d2
VS		 323 /* 0x55 - 1280x720@60Hz */
324 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
325 1430, 1650, 0, 720, 725, 730, 750, 0,
326 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 327 /* 0x16 - 1280x768@60Hz RB */
a6b21831
TR		 328 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
329 1360, 1440, 0, 768, 771, 778, 790, 0,
330 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 331 /* 0x17 - 1280x768@60Hz */
a6b21831
TR		 332 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
333 1472, 1664, 0, 768, 771, 778, 798, 0,
334 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 335 /* 0x18 - 1280x768@75Hz */
a6b21831
TR		 336 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
337 1488, 1696, 0, 768, 771, 778, 805, 0,
fcf22d05 338 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 339 /* 0x19 - 1280x768@85Hz */
a6b21831
TR		 340 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
341 1496, 1712, 0, 768, 771, 778, 809, 0,
342 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 343 /* 0x1a - 1280x768@120Hz RB */
a6b21831
TR		 344 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
345 1360, 1440, 0, 768, 771, 778, 813, 0,
346 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 347 /* 0x1b - 1280x800@60Hz RB */
a6b21831
TR		 348 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
349 1360, 1440, 0, 800, 803, 809, 823, 0,
350 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 351 /* 0x1c - 1280x800@60Hz */
a6b21831
TR		 352 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
353 1480, 1680, 0, 800, 803, 809, 831, 0,
fcf22d05 354 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 355 /* 0x1d - 1280x800@75Hz */
a6b21831
TR		 356 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
357 1488, 1696, 0, 800, 803, 809, 838, 0,
358 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 359 /* 0x1e - 1280x800@85Hz */
a6b21831
TR		 360 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
361 1496, 1712, 0, 800, 803, 809, 843, 0,
362 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 363 /* 0x1f - 1280x800@120Hz RB */
a6b21831
TR		 364 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
365 1360, 1440, 0, 800, 803, 809, 847, 0,
366 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 367 /* 0x20 - 1280x960@60Hz */
a6b21831
TR		 368 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
369 1488, 1800, 0, 960, 961, 964, 1000, 0,
370 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 371 /* 0x21 - 1280x960@85Hz */
a6b21831
TR		 372 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
373 1504, 1728, 0, 960, 961, 964, 1011, 0,
374 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 375 /* 0x22 - 1280x960@120Hz RB */
a6b21831
TR		 376 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
377 1360, 1440, 0, 960, 963, 967, 1017, 0,
378 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 379 /* 0x23 - 1280x1024@60Hz */
a6b21831
TR		 380 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
381 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
382 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 383 /* 0x24 - 1280x1024@75Hz */
a6b21831
TR		 384 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
385 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
386 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 387 /* 0x25 - 1280x1024@85Hz */
a6b21831
TR		 388 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
389 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
390 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 391 /* 0x26 - 1280x1024@120Hz RB */
a6b21831
TR		 392 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
393 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
394 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 395 /* 0x27 - 1360x768@60Hz */
a6b21831
TR		 396 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
397 1536, 1792, 0, 768, 771, 777, 795, 0,
398 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 399 /* 0x28 - 1360x768@120Hz RB */
a6b21831
TR		 400 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
401 1440, 1520, 0, 768, 771, 776, 813, 0,
402 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 403 /* 0x51 - 1366x768@60Hz */
404 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
405 1579, 1792, 0, 768, 771, 774, 798, 0,
406 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
407 /* 0x56 - 1366x768@60Hz */
408 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
409 1436, 1500, 0, 768, 769, 772, 800, 0,
410 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 411 /* 0x29 - 1400x1050@60Hz RB */
a6b21831
TR		 412 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
413 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
414 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 415 /* 0x2a - 1400x1050@60Hz */
a6b21831
TR		 416 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
417 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
418 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 419 /* 0x2b - 1400x1050@75Hz */
a6b21831
TR		 420 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
421 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
422 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 423 /* 0x2c - 1400x1050@85Hz */
a6b21831
TR		 424 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
425 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
426 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 427 /* 0x2d - 1400x1050@120Hz RB */
a6b21831
TR		 428 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
429 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
430 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 431 /* 0x2e - 1440x900@60Hz RB */
a6b21831
TR		 432 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
433 1520, 1600, 0, 900, 903, 909, 926, 0,
434 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 435 /* 0x2f - 1440x900@60Hz */
a6b21831
TR		 436 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
437 1672, 1904, 0, 900, 903, 909, 934, 0,
438 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 439 /* 0x30 - 1440x900@75Hz */
a6b21831
TR		 440 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
441 1688, 1936, 0, 900, 903, 909, 942, 0,
442 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 443 /* 0x31 - 1440x900@85Hz */
a6b21831
TR		 444 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
445 1696, 1952, 0, 900, 903, 909, 948, 0,
446 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 447 /* 0x32 - 1440x900@120Hz RB */
a6b21831
TR		 448 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
449 1520, 1600, 0, 900, 903, 909, 953, 0,
450 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 451 /* 0x53 - 1600x900@60Hz */
452 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
453 1704, 1800, 0, 900, 901, 904, 1000, 0,
454 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 455 /* 0x33 - 1600x1200@60Hz */
a6b21831
TR		 456 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
457 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
458 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 459 /* 0x34 - 1600x1200@65Hz */
a6b21831
TR		 460 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
461 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
462 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 463 /* 0x35 - 1600x1200@70Hz */
a6b21831
TR		 464 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
465 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
466 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 467 /* 0x36 - 1600x1200@75Hz */
a6b21831
TR		 468 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
469 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
470 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 471 /* 0x37 - 1600x1200@85Hz */
a6b21831
TR		 472 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
473 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
474 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 475 /* 0x38 - 1600x1200@120Hz RB */
a6b21831
TR		 476 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
477 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
478 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 479 /* 0x39 - 1680x1050@60Hz RB */
a6b21831
TR		 480 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
481 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
482 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 483 /* 0x3a - 1680x1050@60Hz */
a6b21831
TR		 484 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
485 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
486 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 487 /* 0x3b - 1680x1050@75Hz */
a6b21831
TR		 488 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
489 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
490 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 491 /* 0x3c - 1680x1050@85Hz */
a6b21831
TR		 492 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
493 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
494 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 495 /* 0x3d - 1680x1050@120Hz RB */
a6b21831
TR		 496 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
497 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
498 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 499 /* 0x3e - 1792x1344@60Hz */
a6b21831
TR		 500 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
501 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
502 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 503 /* 0x3f - 1792x1344@75Hz */
a6b21831
TR		 504 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
505 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
506 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 507 /* 0x40 - 1792x1344@120Hz RB */
a6b21831
TR		 508 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
509 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
510 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 511 /* 0x41 - 1856x1392@60Hz */
a6b21831
TR		 512 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
513 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
514 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 515 /* 0x42 - 1856x1392@75Hz */
a6b21831 516 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
fcf22d05 517 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
a6b21831 518 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 519 /* 0x43 - 1856x1392@120Hz RB */
a6b21831
TR		 520 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
521 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
522 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 523 /* 0x52 - 1920x1080@60Hz */
524 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
525 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
526 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 527 /* 0x44 - 1920x1200@60Hz RB */
a6b21831
TR		 528 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
529 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
530 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 531 /* 0x45 - 1920x1200@60Hz */
a6b21831
TR		 532 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
533 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
534 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 535 /* 0x46 - 1920x1200@75Hz */
a6b21831
TR		 536 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
537 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
538 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 539 /* 0x47 - 1920x1200@85Hz */
a6b21831
TR		 540 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
541 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
542 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 543 /* 0x48 - 1920x1200@120Hz RB */
a6b21831
TR		 544 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
545 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
546 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 547 /* 0x49 - 1920x1440@60Hz */
a6b21831
TR		 548 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
549 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
550 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 551 /* 0x4a - 1920x1440@75Hz */
a6b21831
TR		 552 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
553 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
554 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 555 /* 0x4b - 1920x1440@120Hz RB */
a6b21831
TR		 556 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
557 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
558 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 559 /* 0x54 - 2048x1152@60Hz */
560 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
561 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
562 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 563 /* 0x4c - 2560x1600@60Hz RB */
a6b21831
TR		 564 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
565 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
566 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 567 /* 0x4d - 2560x1600@60Hz */
a6b21831
TR		 568 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
569 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
570 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 571 /* 0x4e - 2560x1600@75Hz */
a6b21831
TR		 572 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
573 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
574 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 575 /* 0x4f - 2560x1600@85Hz */
a6b21831
TR		 576 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
577 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
578 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 579 /* 0x50 - 2560x1600@120Hz RB */
a6b21831
TR		 580 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
581 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
582 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 583 /* 0x57 - 4096x2160@60Hz RB */
584 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
585 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
586 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
587 /* 0x58 - 4096x2160@59.94Hz RB */
588 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
589 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
590 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
a6b21831
TR		 591};
592
e7bfa5c4
VS		 593/*
594 * These more or less come from the DMT spec. The 720x400 modes are
595 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
596 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
597 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
598 * mode.
599 *
600 * The DMT modes have been fact-checked; the rest are mild guesses.
601 */
a6b21831
TR		 602static const struct drm_display_mode edid_est_modes[] = {
603 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
604 968, 1056, 0, 600, 601, 605, 628, 0,
605 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
606 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
607 896, 1024, 0, 600, 601, 603, 625, 0,
608 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
609 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
610 720, 840, 0, 480, 481, 484, 500, 0,
611 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
612 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
87707cfd 613 704, 832, 0, 480, 489, 492, 520, 0,
a6b21831
TR		 614 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
615 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
616 768, 864, 0, 480, 483, 486, 525, 0,
617 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
87707cfd 618 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
a6b21831
TR		 619 752, 800, 0, 480, 490, 492, 525, 0,
620 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
621 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
622 846, 900, 0, 400, 421, 423, 449, 0,
623 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
624 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
625 846, 900, 0, 400, 412, 414, 449, 0,
626 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
627 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
628 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
629 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
87707cfd 630 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
a6b21831
TR		 631 1136, 1312, 0, 768, 769, 772, 800, 0,
632 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
633 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
634 1184, 1328, 0, 768, 771, 777, 806, 0,
635 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
636 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
637 1184, 1344, 0, 768, 771, 777, 806, 0,
638 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
639 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
640 1208, 1264, 0, 768, 768, 776, 817, 0,
641 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
642 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
643 928, 1152, 0, 624, 625, 628, 667, 0,
644 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
645 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
646 896, 1056, 0, 600, 601, 604, 625, 0,
647 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
648 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
649 976, 1040, 0, 600, 637, 643, 666, 0,
650 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
651 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
652 1344, 1600, 0, 864, 865, 868, 900, 0,
653 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
654};
655
656struct minimode {
657 short w;
658 short h;
659 short r;
660 short rb;
661};
662
663static const struct minimode est3_modes[] = {
664 /* byte 6 */
665 { 640, 350, 85, 0 },
666 { 640, 400, 85, 0 },
667 { 720, 400, 85, 0 },
668 { 640, 480, 85, 0 },
669 { 848, 480, 60, 0 },
670 { 800, 600, 85, 0 },
671 { 1024, 768, 85, 0 },
672 { 1152, 864, 75, 0 },
673 /* byte 7 */
674 { 1280, 768, 60, 1 },
675 { 1280, 768, 60, 0 },
676 { 1280, 768, 75, 0 },
677 { 1280, 768, 85, 0 },
678 { 1280, 960, 60, 0 },
679 { 1280, 960, 85, 0 },
680 { 1280, 1024, 60, 0 },
681 { 1280, 1024, 85, 0 },
682 /* byte 8 */
683 { 1360, 768, 60, 0 },
684 { 1440, 900, 60, 1 },
685 { 1440, 900, 60, 0 },
686 { 1440, 900, 75, 0 },
687 { 1440, 900, 85, 0 },
688 { 1400, 1050, 60, 1 },
689 { 1400, 1050, 60, 0 },
690 { 1400, 1050, 75, 0 },
691 /* byte 9 */
692 { 1400, 1050, 85, 0 },
693 { 1680, 1050, 60, 1 },
694 { 1680, 1050, 60, 0 },
695 { 1680, 1050, 75, 0 },
696 { 1680, 1050, 85, 0 },
697 { 1600, 1200, 60, 0 },
698 { 1600, 1200, 65, 0 },
699 { 1600, 1200, 70, 0 },
700 /* byte 10 */
701 { 1600, 1200, 75, 0 },
702 { 1600, 1200, 85, 0 },
703 { 1792, 1344, 60, 0 },
c068b32a 704 { 1792, 1344, 75, 0 },
a6b21831
TR		 705 { 1856, 1392, 60, 0 },
706 { 1856, 1392, 75, 0 },
707 { 1920, 1200, 60, 1 },
708 { 1920, 1200, 60, 0 },
709 /* byte 11 */
710 { 1920, 1200, 75, 0 },
711 { 1920, 1200, 85, 0 },
712 { 1920, 1440, 60, 0 },
713 { 1920, 1440, 75, 0 },
714};
715
716static const struct minimode extra_modes[] = {
717 { 1024, 576, 60, 0 },
718 { 1366, 768, 60, 0 },
719 { 1600, 900, 60, 0 },
720 { 1680, 945, 60, 0 },
721 { 1920, 1080, 60, 0 },
722 { 2048, 1152, 60, 0 },
723 { 2048, 1536, 60, 0 },
724};
725
726/*
7befe621 727 * From CEA/CTA-861 spec.
d9278b4c 728 *
7befe621 729 * Do not access directly, instead always use cea_mode_for_vic().
a6b21831 730 */
8c1b2bd9 731static const struct drm_display_mode edid_cea_modes_1[] = {
78691960 732 /* 1 - 640x480@60Hz 4:3 */
a6b21831
TR		 733 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
734 752, 800, 0, 480, 490, 492, 525, 0,
ee7925bb 735 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 736 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 737 /* 2 - 720x480@60Hz 4:3 */
a6b21831
TR		 738 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
739 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 740 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 741 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 742 /* 3 - 720x480@60Hz 16:9 */
a6b21831
TR		 743 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
744 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 745 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 746 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 747 /* 4 - 1280x720@60Hz 16:9 */
a6b21831
TR		 748 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
749 1430, 1650, 0, 720, 725, 730, 750, 0,
ee7925bb 750 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 751 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 752 /* 5 - 1920x1080i@60Hz 16:9 */
a6b21831
TR		 753 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
754 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
755 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 756 DRM_MODE_FLAG_INTERLACE),
0425662f 757 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 758 /* 6 - 720(1440)x480i@60Hz 4:3 */
fb01d280
CT		 759 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
760 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 761 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 762 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 763 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 764 /* 7 - 720(1440)x480i@60Hz 16:9 */
fb01d280
CT		 765 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
766 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 767 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 768 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 769 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 770 /* 8 - 720(1440)x240@60Hz 4:3 */
fb01d280
CT		 771 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
772 801, 858, 0, 240, 244, 247, 262, 0,
a6b21831 773 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 774 DRM_MODE_FLAG_DBLCLK),
0425662f 775 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 776 /* 9 - 720(1440)x240@60Hz 16:9 */
fb01d280
CT		 777 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
778 801, 858, 0, 240, 244, 247, 262, 0,
a6b21831 779 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 780 DRM_MODE_FLAG_DBLCLK),
0425662f 781 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 782 /* 10 - 2880x480i@60Hz 4:3 */
a6b21831
TR		 783 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
784 3204, 3432, 0, 480, 488, 494, 525, 0,
785 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 786 DRM_MODE_FLAG_INTERLACE),
0425662f 787 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 788 /* 11 - 2880x480i@60Hz 16:9 */
a6b21831
TR		 789 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
790 3204, 3432, 0, 480, 488, 494, 525, 0,
791 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 792 DRM_MODE_FLAG_INTERLACE),
0425662f 793 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 794 /* 12 - 2880x240@60Hz 4:3 */
a6b21831
TR		 795 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
796 3204, 3432, 0, 240, 244, 247, 262, 0,
ee7925bb 797 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 798 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 799 /* 13 - 2880x240@60Hz 16:9 */
a6b21831
TR		 800 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
801 3204, 3432, 0, 240, 244, 247, 262, 0,
ee7925bb 802 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 803 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 804 /* 14 - 1440x480@60Hz 4:3 */
a6b21831
TR		 805 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
806 1596, 1716, 0, 480, 489, 495, 525, 0,
ee7925bb 807 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 808 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 809 /* 15 - 1440x480@60Hz 16:9 */
a6b21831
TR		 810 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
811 1596, 1716, 0, 480, 489, 495, 525, 0,
ee7925bb 812 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 813 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 814 /* 16 - 1920x1080@60Hz 16:9 */
a6b21831
TR		 815 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
816 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 817 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 818 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 819 /* 17 - 720x576@50Hz 4:3 */
a6b21831
TR		 820 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
821 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 822 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 823 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 824 /* 18 - 720x576@50Hz 16:9 */
a6b21831
TR		 825 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
826 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 827 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 828 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 829 /* 19 - 1280x720@50Hz 16:9 */
a6b21831
TR		 830 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
831 1760, 1980, 0, 720, 725, 730, 750, 0,
ee7925bb 832 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 833 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 834 /* 20 - 1920x1080i@50Hz 16:9 */
a6b21831
TR		 835 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
836 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
837 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 838 DRM_MODE_FLAG_INTERLACE),
0425662f 839 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 840 /* 21 - 720(1440)x576i@50Hz 4:3 */
fb01d280
CT		 841 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
842 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 843 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 844 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 845 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 846 /* 22 - 720(1440)x576i@50Hz 16:9 */
fb01d280
CT		 847 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
848 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 849 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 850 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 851 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 852 /* 23 - 720(1440)x288@50Hz 4:3 */
fb01d280
CT		 853 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
854 795, 864, 0, 288, 290, 293, 312, 0,
a6b21831 855 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 856 DRM_MODE_FLAG_DBLCLK),
0425662f 857 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 858 /* 24 - 720(1440)x288@50Hz 16:9 */
fb01d280
CT		 859 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
860 795, 864, 0, 288, 290, 293, 312, 0,
a6b21831 861 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 862 DRM_MODE_FLAG_DBLCLK),
0425662f 863 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 864 /* 25 - 2880x576i@50Hz 4:3 */
a6b21831
TR		 865 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
866 3180, 3456, 0, 576, 580, 586, 625, 0,
867 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 868 DRM_MODE_FLAG_INTERLACE),
0425662f 869 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 870 /* 26 - 2880x576i@50Hz 16:9 */
a6b21831
TR		 871 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
872 3180, 3456, 0, 576, 580, 586, 625, 0,
873 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 874 DRM_MODE_FLAG_INTERLACE),
0425662f 875 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 876 /* 27 - 2880x288@50Hz 4:3 */
a6b21831
TR		 877 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
878 3180, 3456, 0, 288, 290, 293, 312, 0,
ee7925bb 879 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 880 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 881 /* 28 - 2880x288@50Hz 16:9 */
a6b21831
TR		 882 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
883 3180, 3456, 0, 288, 290, 293, 312, 0,
ee7925bb 884 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 885 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 886 /* 29 - 1440x576@50Hz 4:3 */
a6b21831
TR		 887 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
888 1592, 1728, 0, 576, 581, 586, 625, 0,
ee7925bb 889 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 890 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 891 /* 30 - 1440x576@50Hz 16:9 */
a6b21831
TR		 892 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
893 1592, 1728, 0, 576, 581, 586, 625, 0,
ee7925bb 894 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 895 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 896 /* 31 - 1920x1080@50Hz 16:9 */
a6b21831
TR		 897 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
898 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 899 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 900 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 901 /* 32 - 1920x1080@24Hz 16:9 */
a6b21831
TR		 902 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
903 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 904 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 905 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 906 /* 33 - 1920x1080@25Hz 16:9 */
a6b21831
TR		 907 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
908 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 909 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 910 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 911 /* 34 - 1920x1080@30Hz 16:9 */
a6b21831
TR		 912 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
913 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 914 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 915 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 916 /* 35 - 2880x480@60Hz 4:3 */
a6b21831
TR		 917 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
918 3192, 3432, 0, 480, 489, 495, 525, 0,
ee7925bb 919 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 920 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 921 /* 36 - 2880x480@60Hz 16:9 */
a6b21831
TR		 922 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
923 3192, 3432, 0, 480, 489, 495, 525, 0,
ee7925bb 924 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 925 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 926 /* 37 - 2880x576@50Hz 4:3 */
a6b21831
TR		 927 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
928 3184, 3456, 0, 576, 581, 586, 625, 0,
ee7925bb 929 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 930 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 931 /* 38 - 2880x576@50Hz 16:9 */
a6b21831
TR		 932 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
933 3184, 3456, 0, 576, 581, 586, 625, 0,
ee7925bb 934 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 935 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 936 /* 39 - 1920x1080i@50Hz 16:9 */
a6b21831
TR		 937 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
938 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
939 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 940 DRM_MODE_FLAG_INTERLACE),
0425662f 941 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 942 /* 40 - 1920x1080i@100Hz 16:9 */
a6b21831
TR		 943 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
944 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
945 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 946 DRM_MODE_FLAG_INTERLACE),
0425662f 947 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 948 /* 41 - 1280x720@100Hz 16:9 */
a6b21831
TR		 949 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
950 1760, 1980, 0, 720, 725, 730, 750, 0,
ee7925bb 951 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 952 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 953 /* 42 - 720x576@100Hz 4:3 */
a6b21831
TR		 954 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
955 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 956 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 957 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 958 /* 43 - 720x576@100Hz 16:9 */
a6b21831
TR		 959 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
960 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 961 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 962 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 963 /* 44 - 720(1440)x576i@100Hz 4:3 */
fb01d280
CT		 964 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
965 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 966 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 967 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 968 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 969 /* 45 - 720(1440)x576i@100Hz 16:9 */
fb01d280
CT		 970 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
971 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 972 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 973 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 974 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 975 /* 46 - 1920x1080i@120Hz 16:9 */
a6b21831
TR		 976 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
977 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
978 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 979 DRM_MODE_FLAG_INTERLACE),
0425662f 980 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 981 /* 47 - 1280x720@120Hz 16:9 */
a6b21831
TR		 982 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
983 1430, 1650, 0, 720, 725, 730, 750, 0,
ee7925bb 984 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 985 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 986 /* 48 - 720x480@120Hz 4:3 */
a6b21831
TR		 987 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
988 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 989 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 990 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 991 /* 49 - 720x480@120Hz 16:9 */
a6b21831
TR		 992 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
993 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 994 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 995 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 996 /* 50 - 720(1440)x480i@120Hz 4:3 */
fb01d280
CT		 997 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
998 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 999 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1000 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1001 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1002 /* 51 - 720(1440)x480i@120Hz 16:9 */
fb01d280
CT		 1003 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
1004 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 1005 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1006 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1007 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1008 /* 52 - 720x576@200Hz 4:3 */
a6b21831
TR		 1009 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1010 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 1011 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 1012 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1013 /* 53 - 720x576@200Hz 16:9 */
a6b21831
TR		 1014 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1015 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 1016 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 1017 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1018 /* 54 - 720(1440)x576i@200Hz 4:3 */
fb01d280
CT		 1019 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1020 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 1021 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1022 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1023 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1024 /* 55 - 720(1440)x576i@200Hz 16:9 */
fb01d280
CT		 1025 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1026 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 1027 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1028 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1029 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1030 /* 56 - 720x480@240Hz 4:3 */
a6b21831
TR		 1031 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1032 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 1033 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 1034 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1035 /* 57 - 720x480@240Hz 16:9 */
a6b21831
TR		 1036 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1037 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 1038 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 1039 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1040 /* 58 - 720(1440)x480i@240Hz 4:3 */
fb01d280
CT		 1041 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1042 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 1043 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1044 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1045 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1046 /* 59 - 720(1440)x480i@240Hz 16:9 */
fb01d280
CT		 1047 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1048 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 1049 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1050 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1051 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1052 /* 60 - 1280x720@24Hz 16:9 */
a6b21831
TR		 1053 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1054 3080, 3300, 0, 720, 725, 730, 750, 0,
ee7925bb 1055 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1056 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1057 /* 61 - 1280x720@25Hz 16:9 */
a6b21831
TR		 1058 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1059 3740, 3960, 0, 720, 725, 730, 750, 0,
ee7925bb 1060 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1061 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1062 /* 62 - 1280x720@30Hz 16:9 */
a6b21831
TR		 1063 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1064 3080, 3300, 0, 720, 725, 730, 750, 0,
ee7925bb 1065 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1066 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1067 /* 63 - 1920x1080@120Hz 16:9 */
a6b21831
TR		 1068 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1069 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 1070 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1071 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1072 /* 64 - 1920x1080@100Hz 16:9 */
a6b21831 1073 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
8f0e4907 1074 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 1075 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1076 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1077 /* 65 - 1280x720@24Hz 64:27 */
8ec6e075
SS		 1078 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1079 3080, 3300, 0, 720, 725, 730, 750, 0,
1080 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1081 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1082 /* 66 - 1280x720@25Hz 64:27 */
8ec6e075
SS		 1083 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1084 3740, 3960, 0, 720, 725, 730, 750, 0,
1085 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1086 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1087 /* 67 - 1280x720@30Hz 64:27 */
8ec6e075
SS		 1088 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1089 3080, 3300, 0, 720, 725, 730, 750, 0,
1090 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1091 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1092 /* 68 - 1280x720@50Hz 64:27 */
8ec6e075
SS		 1093 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1094 1760, 1980, 0, 720, 725, 730, 750, 0,
1095 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1096 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1097 /* 69 - 1280x720@60Hz 64:27 */
8ec6e075
SS		 1098 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1099 1430, 1650, 0, 720, 725, 730, 750, 0,
1100 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1101 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1102 /* 70 - 1280x720@100Hz 64:27 */
8ec6e075
SS		 1103 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1104 1760, 1980, 0, 720, 725, 730, 750, 0,
1105 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1106 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1107 /* 71 - 1280x720@120Hz 64:27 */
8ec6e075
SS		 1108 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1109 1430, 1650, 0, 720, 725, 730, 750, 0,
1110 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1111 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1112 /* 72 - 1920x1080@24Hz 64:27 */
8ec6e075
SS		 1113 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1114 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1115 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1116 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1117 /* 73 - 1920x1080@25Hz 64:27 */
8ec6e075
SS		 1118 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1119 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1120 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1121 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1122 /* 74 - 1920x1080@30Hz 64:27 */
8ec6e075
SS		 1123 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1124 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1125 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1126 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1127 /* 75 - 1920x1080@50Hz 64:27 */
8ec6e075
SS		 1128 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1129 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1130 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1131 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1132 /* 76 - 1920x1080@60Hz 64:27 */
8ec6e075
SS		 1133 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1134 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1135 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1136 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1137 /* 77 - 1920x1080@100Hz 64:27 */
8ec6e075
SS		 1138 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1139 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1140 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1141 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1142 /* 78 - 1920x1080@120Hz 64:27 */
8ec6e075
SS		 1143 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1144 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1145 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1146 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1147 /* 79 - 1680x720@24Hz 64:27 */
8ec6e075
SS		 1148 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1149 3080, 3300, 0, 720, 725, 730, 750, 0,
1150 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1151 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1152 /* 80 - 1680x720@25Hz 64:27 */
8ec6e075
SS		 1153 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1154 2948, 3168, 0, 720, 725, 730, 750, 0,
1155 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1156 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1157 /* 81 - 1680x720@30Hz 64:27 */
8ec6e075
SS		 1158 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1159 2420, 2640, 0, 720, 725, 730, 750, 0,
1160 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1161 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1162 /* 82 - 1680x720@50Hz 64:27 */
8ec6e075
SS		 1163 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1164 1980, 2200, 0, 720, 725, 730, 750, 0,
1165 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1166 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1167 /* 83 - 1680x720@60Hz 64:27 */
8ec6e075
SS		 1168 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1169 1980, 2200, 0, 720, 725, 730, 750, 0,
1170 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1171 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1172 /* 84 - 1680x720@100Hz 64:27 */
8ec6e075
SS		 1173 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1174 1780, 2000, 0, 720, 725, 730, 825, 0,
1175 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1176 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1177 /* 85 - 1680x720@120Hz 64:27 */
8ec6e075
SS		 1178 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1179 1780, 2000, 0, 720, 725, 730, 825, 0,
1180 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1181 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1182 /* 86 - 2560x1080@24Hz 64:27 */
8ec6e075
SS		 1183 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1184 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1185 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1186 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1187 /* 87 - 2560x1080@25Hz 64:27 */
8ec6e075
SS		 1188 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1189 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1190 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1191 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1192 /* 88 - 2560x1080@30Hz 64:27 */
8ec6e075
SS		 1193 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1194 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1195 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1196 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1197 /* 89 - 2560x1080@50Hz 64:27 */
8ec6e075
SS		 1198 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1199 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1200 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1201 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1202 /* 90 - 2560x1080@60Hz 64:27 */
8ec6e075
SS		 1203 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1204 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1205 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1206 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1207 /* 91 - 2560x1080@100Hz 64:27 */
8ec6e075
SS		 1208 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1209 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1210 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1211 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1212 /* 92 - 2560x1080@120Hz 64:27 */
8ec6e075
SS		 1213 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1214 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1215 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1216 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1217 /* 93 - 3840x2160@24Hz 16:9 */
8ec6e075
SS		 1218 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1219 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1220 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1221 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1222 /* 94 - 3840x2160@25Hz 16:9 */
8ec6e075
SS		 1223 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1224 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1225 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1226 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1227 /* 95 - 3840x2160@30Hz 16:9 */
8ec6e075
SS		 1228 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1229 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1230 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1231 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1232 /* 96 - 3840x2160@50Hz 16:9 */
8ec6e075
SS		 1233 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1234 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1235 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1236 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1237 /* 97 - 3840x2160@60Hz 16:9 */
8ec6e075
SS		 1238 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1239 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1240 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1241 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1242 /* 98 - 4096x2160@24Hz 256:135 */
8ec6e075
SS		 1243 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1244 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1245 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1246 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1247 /* 99 - 4096x2160@25Hz 256:135 */
8ec6e075
SS		 1248 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1249 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1250 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1251 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1252 /* 100 - 4096x2160@30Hz 256:135 */
8ec6e075
SS		 1253 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1254 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1255 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1256 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1257 /* 101 - 4096x2160@50Hz 256:135 */
8ec6e075
SS		 1258 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1259 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1260 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1261 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1262 /* 102 - 4096x2160@60Hz 256:135 */
8ec6e075
SS		 1263 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1264 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1265 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1266 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1267 /* 103 - 3840x2160@24Hz 64:27 */
8ec6e075
SS		 1268 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1269 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1270 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1271 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1272 /* 104 - 3840x2160@25Hz 64:27 */
8ec6e075
SS		 1273 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1274 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1275 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1276 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1277 /* 105 - 3840x2160@30Hz 64:27 */
8ec6e075
SS		 1278 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1279 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1281 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1282 /* 106 - 3840x2160@50Hz 64:27 */
8ec6e075
SS		 1283 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1284 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1285 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1286 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1287 /* 107 - 3840x2160@60Hz 64:27 */
8ec6e075
SS		 1288 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1289 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1290 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1291 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1292 /* 108 - 1280x720@48Hz 16:9 */
1293 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1294 2280, 2500, 0, 720, 725, 730, 750, 0,
1295 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1296 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1297 /* 109 - 1280x720@48Hz 64:27 */
1298 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1299 2280, 2500, 0, 720, 725, 730, 750, 0,
1300 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1301 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1302 /* 110 - 1680x720@48Hz 64:27 */
1303 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490,
1304 2530, 2750, 0, 720, 725, 730, 750, 0,
1305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1306 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1307 /* 111 - 1920x1080@48Hz 16:9 */
1308 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1309 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1310 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1311 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1312 /* 112 - 1920x1080@48Hz 64:27 */
1313 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1314 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1315 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1316 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1317 /* 113 - 2560x1080@48Hz 64:27 */
1318 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558,
1319 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1320 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1321 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1322 /* 114 - 3840x2160@48Hz 16:9 */
1323 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1324 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1325 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1326 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1327 /* 115 - 4096x2160@48Hz 256:135 */
1328 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116,
1329 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1330 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1331 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
978f6b06
VS		 1332 /* 116 - 3840x2160@48Hz 64:27 */
1333 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1334 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1335 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1336 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1337 /* 117 - 3840x2160@100Hz 16:9 */
1338 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1339 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1340 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1341 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1342 /* 118 - 3840x2160@120Hz 16:9 */
1343 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1344 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1345 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1346 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1347 /* 119 - 3840x2160@100Hz 64:27 */
1348 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1349 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1350 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1351 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1352 /* 120 - 3840x2160@120Hz 64:27 */
1353 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1354 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1355 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1356 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1357 /* 121 - 5120x2160@24Hz 64:27 */
1358 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116,
1359 7204, 7500, 0, 2160, 2168, 2178, 2200, 0,
1360 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1361 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1362 /* 122 - 5120x2160@25Hz 64:27 */
1363 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816,
1364 6904, 7200, 0, 2160, 2168, 2178, 2200, 0,
1365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1366 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1367 /* 123 - 5120x2160@30Hz 64:27 */
1368 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784,
1369 5872, 6000, 0, 2160, 2168, 2178, 2200, 0,
1370 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1371 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1372 /* 124 - 5120x2160@48Hz 64:27 */
1373 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866,
1374 5954, 6250, 0, 2160, 2168, 2178, 2475, 0,
1375 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1376 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1377 /* 125 - 5120x2160@50Hz 64:27 */
1378 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216,
1379 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1380 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1381 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1382 /* 126 - 5120x2160@60Hz 64:27 */
1383 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284,
1384 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1386 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1387 /* 127 - 5120x2160@100Hz 64:27 */
1388 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216,
1389 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1390 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1391 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
a6b21831
TR		 1392};
1393
f7655d42
VS		 1394/*
1395 * From CEA/CTA-861 spec.
1396 *
1397 * Do not access directly, instead always use cea_mode_for_vic().
1398 */
1399static const struct drm_display_mode edid_cea_modes_193[] = {
1400 /* 193 - 5120x2160@120Hz 64:27 */
1401 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284,
1402 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1403 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1404 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1405 /* 194 - 7680x4320@24Hz 16:9 */
1406 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1407 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1408 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1409 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1410 /* 195 - 7680x4320@25Hz 16:9 */
1411 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1412 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1413 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1414 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1415 /* 196 - 7680x4320@30Hz 16:9 */
1416 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1417 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1418 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1419 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1420 /* 197 - 7680x4320@48Hz 16:9 */
1421 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1422 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1423 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1424 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1425 /* 198 - 7680x4320@50Hz 16:9 */
1426 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1427 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1428 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1429 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1430 /* 199 - 7680x4320@60Hz 16:9 */
1431 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1432 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1433 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1434 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1435 /* 200 - 7680x4320@100Hz 16:9 */
1436 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1437 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1438 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1439 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1440 /* 201 - 7680x4320@120Hz 16:9 */
1441 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1442 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1443 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1444 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1445 /* 202 - 7680x4320@24Hz 64:27 */
1446 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1447 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1448 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1449 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1450 /* 203 - 7680x4320@25Hz 64:27 */
1451 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1452 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1454 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1455 /* 204 - 7680x4320@30Hz 64:27 */
1456 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1457 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1458 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1459 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1460 /* 205 - 7680x4320@48Hz 64:27 */
1461 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1462 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1463 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1464 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1465 /* 206 - 7680x4320@50Hz 64:27 */
1466 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1467 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1468 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1469 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1470 /* 207 - 7680x4320@60Hz 64:27 */
1471 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1472 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1473 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1474 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1475 /* 208 - 7680x4320@100Hz 64:27 */
1476 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1477 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1478 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1479 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1480 /* 209 - 7680x4320@120Hz 64:27 */
1481 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1482 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1483 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1484 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1485 /* 210 - 10240x4320@24Hz 64:27 */
1486 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732,
1487 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1488 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1489 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1490 /* 211 - 10240x4320@25Hz 64:27 */
1491 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732,
1492 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1493 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1494 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1495 /* 212 - 10240x4320@30Hz 64:27 */
1496 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528,
1497 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1498 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1499 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1500 /* 213 - 10240x4320@48Hz 64:27 */
1501 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732,
1502 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1503 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1504 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1505 /* 214 - 10240x4320@50Hz 64:27 */
1506 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732,
1507 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1508 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1509 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1510 /* 215 - 10240x4320@60Hz 64:27 */
1511 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528,
1512 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1513 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1514 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1515 /* 216 - 10240x4320@100Hz 64:27 */
1516 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432,
1517 12608, 13200, 0, 4320, 4336, 4356, 4500, 0,
1518 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1519 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1520 /* 217 - 10240x4320@120Hz 64:27 */
1521 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528,
1522 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1523 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1524 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1525 /* 218 - 4096x2160@100Hz 256:135 */
1526 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896,
1527 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1528 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1529 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
f7655d42
VS		 1530 /* 219 - 4096x2160@120Hz 256:135 */
1531 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184,
1532 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1533 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1534 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
f7655d42
VS		 1535};
1536
7ebe1963 1537/*
d9278b4c 1538 * HDMI 1.4 4k modes. Index using the VIC.
7ebe1963
LD		 1539 */
1540static const struct drm_display_mode edid_4k_modes[] = {
d9278b4c
JN		 1541 /* 0 - dummy, VICs start at 1 */
1542 { },
7ebe1963
LD		 1543 /* 1 - 3840x2160@30Hz */
1544 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1545 3840, 4016, 4104, 4400, 0,
1546 2160, 2168, 2178, 2250, 0,
1547 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1548 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
7ebe1963
LD		 1549 /* 2 - 3840x2160@25Hz */
1550 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1551 3840, 4896, 4984, 5280, 0,
1552 2160, 2168, 2178, 2250, 0,
1553 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1554 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
7ebe1963
LD		 1555 /* 3 - 3840x2160@24Hz */
1556 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1557 3840, 5116, 5204, 5500, 0,
1558 2160, 2168, 2178, 2250, 0,
1559 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1560 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
7ebe1963
LD		 1561 /* 4 - 4096x2160@24Hz (SMPTE) */
1562 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1563 4096, 5116, 5204, 5500, 0,
1564 2160, 2168, 2178, 2250, 0,
1565 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1566 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
7ebe1963
LD		 1567};
1568
61e57a8d 1569/*** DDC fetch and block validation ***/
f453ba04 1570
f1e4c916
JN		 1571static int edid_extension_block_count(const struct edid *edid)
1572{
1573 return edid->extensions;
1574}
1575
1576static int edid_block_count(const struct edid *edid)
1577{
1578 return edid_extension_block_count(edid) + 1;
1579}
1580
1581static int edid_size_by_blocks(int num_blocks)
1582{
1583 return num_blocks * EDID_LENGTH;
1584}
1585
1586static int edid_size(const struct edid *edid)
1587{
1588 return edid_size_by_blocks(edid_block_count(edid));
1589}
1590
1591static const void *edid_block_data(const struct edid *edid, int index)
1592{
1593 BUILD_BUG_ON(sizeof(*edid) != EDID_LENGTH);
1594
1595 return edid + index;
1596}
1597
1598static const void *edid_extension_block_data(const struct edid *edid, int index)
1599{
1600 return edid_block_data(edid, index + 1);
1601}
1602
083ae056
AJ		 1603static const u8 edid_header[] = {
1604 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1605};
f453ba04 1606
0a612bbd
JN		 1607static void edid_header_fix(void *edid)
1608{
1609 memcpy(edid, edid_header, sizeof(edid_header));
1610}
1611
db6cf833
TR		 1612/**
1613 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1614 * @raw_edid: pointer to raw base EDID block
1615 *
1616 * Sanity check the header of the base EDID block.
1617 *
1618 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
051963d4 1619 */
6d987ddd 1620int drm_edid_header_is_valid(const void *_edid)
051963d4 1621{
6d987ddd 1622 const struct edid *edid = _edid;
051963d4
TR		 1623 int i, score = 0;
1624
6d987ddd
JN		 1625 for (i = 0; i < sizeof(edid_header); i++) {
1626 if (edid->header[i] == edid_header[i])
051963d4 1627 score++;
6d987ddd 1628 }
051963d4
TR		 1629
1630 return score;
1631}
1632EXPORT_SYMBOL(drm_edid_header_is_valid);
1633
47819ba2
AJ		 1634static int edid_fixup __read_mostly = 6;
1635module_param_named(edid_fixup, edid_fixup, int, 0400);
1636MODULE_PARM_DESC(edid_fixup,
1637 "Minimum number of valid EDID header bytes (0-8, default 6)");
051963d4 1638
70e49ebe 1639static int edid_block_compute_checksum(const void *_block)
c465bbc8 1640{
70e49ebe 1641 const u8 *block = _block;
c465bbc8 1642 int i;
e11f5bd8
JFZ		 1643 u8 csum = 0, crc = 0;
1644
1645 for (i = 0; i < EDID_LENGTH - 1; i++)
70e49ebe 1646 csum += block[i];
c465bbc8 1647
e11f5bd8
JFZ		 1648 crc = 0x100 - csum;
1649
1650 return crc;
1651}
1652
70e49ebe 1653static int edid_block_get_checksum(const void *_block)
e11f5bd8 1654{
70e49ebe
JN		 1655 const struct edid *block = _block;
1656
1657 return block->checksum;
c465bbc8
SB		 1658}
1659
4ba0f53c
JN		 1660static int edid_block_tag(const void *_block)
1661{
1662 const u8 *block = _block;
1663
1664 return block[0];
1665}
1666
8baccb27 1667static bool edid_block_is_zero(const void *edid)
d6885d65 1668{
8baccb27 1669 return !memchr_inv(edid, 0, EDID_LENGTH);
d6885d65
SB		 1670}
1671
536faa45
SL		 1672/**
1673 * drm_edid_are_equal - compare two edid blobs.
1674 * @edid1: pointer to first blob
1675 * @edid2: pointer to second blob
1676 * This helper can be used during probing to determine if
1677 * edid had changed.
1678 */
1679bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2)
1680{
1681 int edid1_len, edid2_len;
1682 bool edid1_present = edid1 != NULL;
1683 bool edid2_present = edid2 != NULL;
1684
1685 if (edid1_present != edid2_present)
1686 return false;
1687
1688 if (edid1) {
f1e4c916
JN		 1689 edid1_len = edid_size(edid1);
1690 edid2_len = edid_size(edid2);
536faa45
SL		 1691
1692 if (edid1_len != edid2_len)
1693 return false;
1694
1695 if (memcmp(edid1, edid2, edid1_len))
1696 return false;
1697 }
1698
1699 return true;
1700}
1701EXPORT_SYMBOL(drm_edid_are_equal);
1702
1f221284
JN		 1703enum edid_block_status {
1704 EDID_BLOCK_OK = 0,
2deaf1c2 1705 EDID_BLOCK_READ_FAIL,
1f221284 1706 EDID_BLOCK_NULL,
49dc0558 1707 EDID_BLOCK_ZERO,
1f221284
JN		 1708 EDID_BLOCK_HEADER_CORRUPT,
1709 EDID_BLOCK_HEADER_REPAIR,
1710 EDID_BLOCK_HEADER_FIXED,
1711 EDID_BLOCK_CHECKSUM,
1712 EDID_BLOCK_VERSION,
1713};
1714
1715static enum edid_block_status edid_block_check(const void *_block,
1716 bool is_base_block)
1717{
1718 const struct edid *block = _block;
1719
1720 if (!block)
1721 return EDID_BLOCK_NULL;
1722
1723 if (is_base_block) {
1724 int score = drm_edid_header_is_valid(block);
1725
49dc0558
JN		 1726 if (score < clamp(edid_fixup, 0, 8)) {
1727 if (edid_block_is_zero(block))
1728 return EDID_BLOCK_ZERO;
1729 else
1730 return EDID_BLOCK_HEADER_CORRUPT;
1731 }
1f221284
JN		 1732
1733 if (score < 8)
1734 return EDID_BLOCK_HEADER_REPAIR;
1735 }
1736
49dc0558
JN		 1737 if (edid_block_compute_checksum(block) != edid_block_get_checksum(block)) {
1738 if (edid_block_is_zero(block))
1739 return EDID_BLOCK_ZERO;
1740 else
1741 return EDID_BLOCK_CHECKSUM;
1742 }
1f221284
JN		 1743
1744 if (is_base_block) {
1745 if (block->version != 1)
1746 return EDID_BLOCK_VERSION;
1747 }
1748
1749 return EDID_BLOCK_OK;
1750}
1751
1752static bool edid_block_status_valid(enum edid_block_status status, int tag)
1753{
1754 return status == EDID_BLOCK_OK ||
1755 status == EDID_BLOCK_HEADER_FIXED ||
1756 (status == EDID_BLOCK_CHECKSUM && tag == CEA_EXT);
1757}
1758
23e38d7b
JN		 1759static bool edid_block_valid(const void *block, bool base)
1760{
1761 return edid_block_status_valid(edid_block_check(block, base),
1762 edid_block_tag(block));
1763}
1764
cee2ce1a
JN		 1765static void edid_block_status_print(enum edid_block_status status,
1766 const struct edid *block,
1767 int block_num)
1768{
1769 switch (status) {
1770 case EDID_BLOCK_OK:
1771 break;
2deaf1c2
JN		 1772 case EDID_BLOCK_READ_FAIL:
1773 pr_debug("EDID block %d read failed\n", block_num);
1774 break;
cee2ce1a
JN		 1775 case EDID_BLOCK_NULL:
1776 pr_debug("EDID block %d pointer is NULL\n", block_num);
1777 break;
1778 case EDID_BLOCK_ZERO:
1779 pr_notice("EDID block %d is all zeroes\n", block_num);
1780 break;
1781 case EDID_BLOCK_HEADER_CORRUPT:
1782 pr_notice("EDID has corrupt header\n");
1783 break;
1784 case EDID_BLOCK_HEADER_REPAIR:
1785 pr_debug("EDID corrupt header needs repair\n");
1786 break;
1787 case EDID_BLOCK_HEADER_FIXED:
1788 pr_debug("EDID corrupt header fixed\n");
1789 break;
1790 case EDID_BLOCK_CHECKSUM:
1791 if (edid_block_status_valid(status, edid_block_tag(block))) {
1792 pr_debug("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d, ignoring\n",
1793 block_num, edid_block_tag(block),
1794 edid_block_compute_checksum(block));
1795 } else {
1796 pr_notice("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d\n",
1797 block_num, edid_block_tag(block),
1798 edid_block_compute_checksum(block));
1799 }
1800 break;
1801 case EDID_BLOCK_VERSION:
1802 pr_notice("EDID has major version %d, instead of 1\n",
1803 block->version);
1804 break;
1805 default:
1806 WARN(1, "EDID block %d unknown edid block status code %d\n",
1807 block_num, status);
1808 break;
1809 }
1810}
1811
9c7345de
JN		 1812static void edid_block_dump(const char *level, const void *block, int block_num)
1813{
1814 enum edid_block_status status;
1815 char prefix[20];
1816
1817 status = edid_block_check(block, block_num == 0);
1818 if (status == EDID_BLOCK_ZERO)
1819 sprintf(prefix, "\t[%02x] ZERO ", block_num);
1820 else if (!edid_block_status_valid(status, edid_block_tag(block)))
1821 sprintf(prefix, "\t[%02x] BAD ", block_num);
1822 else
1823 sprintf(prefix, "\t[%02x] GOOD ", block_num);
1824
1825 print_hex_dump(level, prefix, DUMP_PREFIX_NONE, 16, 1,
1826 block, EDID_LENGTH, false);
1827}
1828
db6cf833
TR		 1829/**
1830 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1831 * @raw_edid: pointer to raw EDID block
1f221284 1832 * @block_num: type of block to validate (0 for base, extension otherwise)
db6cf833 1833 * @print_bad_edid: if true, dump bad EDID blocks to the console
6ba2bd3d 1834 * @edid_corrupt: if true, the header or checksum is invalid
db6cf833
TR		 1835 *
1836 * Validate a base or extension EDID block and optionally dump bad blocks to
1837 * the console.
1838 *
1839 * Return: True if the block is valid, false otherwise.
f453ba04 1840 */
1f221284 1841bool drm_edid_block_valid(u8 *_block, int block_num, bool print_bad_edid,
6ba2bd3d 1842 bool *edid_corrupt)
f453ba04 1843{
1f221284
JN		 1844 struct edid *block = (struct edid *)_block;
1845 enum edid_block_status status;
1846 bool is_base_block = block_num == 0;
1847 bool valid;
f453ba04 1848
1f221284 1849 if (WARN_ON(!block))
fe2ef780
SWK		 1850 return false;
1851
1f221284
JN		 1852 status = edid_block_check(block, is_base_block);
1853 if (status == EDID_BLOCK_HEADER_REPAIR) {
1854 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1855 edid_header_fix(block);
1856
1857 /* Retry with fixed header, update status if that worked. */
1858 status = edid_block_check(block, is_base_block);
1859 if (status == EDID_BLOCK_OK)
1860 status = EDID_BLOCK_HEADER_FIXED;
61e57a8d 1861 }
f453ba04 1862
1f221284
JN		 1863 if (edid_corrupt) {
1864 /*
1865 * Unknown major version isn't corrupt but we can't use it. Only
1866 * the base block can reset edid_corrupt to false.
1867 */
1868 if (is_base_block &&
1869 (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION))
1870 *edid_corrupt = false;
1871 else if (status != EDID_BLOCK_OK)
ac6f2e29 1872 *edid_corrupt = true;
f453ba04
DA		 1873 }
1874
cee2ce1a
JN		 1875 edid_block_status_print(status, block, block_num);
1876
1f221284
JN		 1877 /* Determine whether we can use this block with this status. */
1878 valid = edid_block_status_valid(status, edid_block_tag(block));
1879
cee2ce1a
JN		 1880 if (!valid && print_bad_edid && status != EDID_BLOCK_ZERO) {
1881 pr_notice("Raw EDID:\n");
9c7345de 1882 edid_block_dump(KERN_NOTICE, block, block_num);
f453ba04 1883 }
1f221284
JN		 1884
1885 return valid;
f453ba04 1886}
da0df92b 1887EXPORT_SYMBOL(drm_edid_block_valid);
61e57a8d
AJ		 1888
1889/**
1890 * drm_edid_is_valid - sanity check EDID data
1891 * @edid: EDID data
1892 *
1893 * Sanity-check an entire EDID record (including extensions)
db6cf833
TR		 1894 *
1895 * Return: True if the EDID data is valid, false otherwise.
61e57a8d
AJ		 1896 */
1897bool drm_edid_is_valid(struct edid *edid)
1898{
1899 int i;
61e57a8d
AJ		 1900
1901 if (!edid)
1902 return false;
1903
f1e4c916
JN		 1904 for (i = 0; i < edid_block_count(edid); i++) {
1905 void *block = (void *)edid_block_data(edid, i);
1906
1907 if (!drm_edid_block_valid(block, i, true, NULL))
61e57a8d 1908 return false;
f1e4c916 1909 }
61e57a8d
AJ		 1910
1911 return true;
1912}
3c537889 1913EXPORT_SYMBOL(drm_edid_is_valid);
f453ba04 1914
4ec53461 1915static struct edid *edid_filter_invalid_blocks(const struct edid *edid,
ccc97def 1916 int invalid_blocks)
4ec53461
JN		 1917{
1918 struct edid *new, *dest_block;
ccc97def 1919 int valid_extensions = edid->extensions - invalid_blocks;
4ec53461
JN		 1920 int i;
1921
f1e4c916 1922 new = kmalloc(edid_size_by_blocks(valid_extensions + 1), GFP_KERNEL);
4ec53461
JN		 1923 if (!new)
1924 goto out;
1925
1926 dest_block = new;
f1e4c916
JN		 1927 for (i = 0; i < edid_block_count(edid); i++) {
1928 const void *block = edid_block_data(edid, i);
4ec53461
JN		 1929
1930 if (edid_block_valid(block, i == 0))
1931 memcpy(dest_block++, block, EDID_LENGTH);
1932 }
1933
4ec53461 1934 new->extensions = valid_extensions;
ab0609a5 1935 new->checksum = edid_block_compute_checksum(new);
4ec53461
JN		 1936
1937out:
1938 kfree(edid);
1939
1940 return new;
1941}
1942
61e57a8d
AJ		 1943#define DDC_SEGMENT_ADDR 0x30
1944/**
db6cf833 1945 * drm_do_probe_ddc_edid() - get EDID information via I2C
7c58e87e 1946 * @data: I2C device adapter
fc66811c
DV		 1947 * @buf: EDID data buffer to be filled
1948 * @block: 128 byte EDID block to start fetching from
1949 * @len: EDID data buffer length to fetch
1950 *
db6cf833 1951 * Try to fetch EDID information by calling I2C driver functions.
61e57a8d 1952 *
db6cf833 1953 * Return: 0 on success or -1 on failure.
61e57a8d
AJ		 1954 */
1955static int
18df89fe 1956drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
61e57a8d 1957{
18df89fe 1958 struct i2c_adapter *adapter = data;
61e57a8d 1959 unsigned char start = block * EDID_LENGTH;
cd004b3f
S		 1960 unsigned char segment = block >> 1;
1961 unsigned char xfers = segment ? 3 : 2;
4819d2e4
CW		 1962 int ret, retries = 5;
1963
db6cf833
TR		 1964 /*
1965 * The core I2C driver will automatically retry the transfer if the
4819d2e4
CW		 1966 * adapter reports EAGAIN. However, we find that bit-banging transfers
1967 * are susceptible to errors under a heavily loaded machine and
1968 * generate spurious NAKs and timeouts. Retrying the transfer
1969 * of the individual block a few times seems to overcome this.
1970 */
1971 do {
1972 struct i2c_msg msgs[] = {
1973 {
cd004b3f
S		 1974 .addr = DDC_SEGMENT_ADDR,
1975 .flags = 0,
1976 .len = 1,
1977 .buf = &segment,
1978 }, {
4819d2e4
CW		 1979 .addr = DDC_ADDR,
1980 .flags = 0,
1981 .len = 1,
1982 .buf = &start,
1983 }, {
1984 .addr = DDC_ADDR,
1985 .flags = I2C_M_RD,
1986 .len = len,
1987 .buf = buf,
1988 }
1989 };
cd004b3f 1990
db6cf833
TR		 1991 /*
1992 * Avoid sending the segment addr to not upset non-compliant
1993 * DDC monitors.
1994 */
cd004b3f
S		 1995 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1996
9292f37e
ED		 1997 if (ret == -ENXIO) {
1998 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1999 adapter->name);
2000 break;
2001 }
cd004b3f 2002 } while (ret != xfers && --retries);
4819d2e4 2003
cd004b3f 2004 return ret == xfers ? 0 : -1;
61e57a8d
AJ		 2005}
2006
14544d09 2007static void connector_bad_edid(struct drm_connector *connector,
63cae081 2008 const struct edid *edid, int num_blocks)
14544d09
CW		 2009{
2010 int i;
97794170
DA		 2011 u8 last_block;
2012
2013 /*
2014 * 0x7e in the EDID is the number of extension blocks. The EDID
2015 * is 1 (base block) + num_ext_blocks big. That means we can think
2016 * of 0x7e in the EDID of the _index_ of the last block in the
2017 * combined chunk of memory.
2018 */
63cae081 2019 last_block = edid->extensions;
e11f5bd8
JFZ		 2020
2021 /* Calculate real checksum for the last edid extension block data */
97794170
DA		 2022 if (last_block < num_blocks)
2023 connector->real_edid_checksum =
63cae081 2024 edid_block_compute_checksum(edid + last_block);
14544d09 2025
f0a8f533 2026 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
14544d09
CW		 2027 return;
2028
fa3bfa35 2029 drm_dbg_kms(connector->dev, "%s: EDID is invalid:\n", connector->name);
63cae081
JN		 2030 for (i = 0; i < num_blocks; i++)
2031 edid_block_dump(KERN_DEBUG, edid + i, i);
14544d09
CW		 2032}
2033
56a2b7f2
JN		 2034/* Get override or firmware EDID */
2035static struct edid *drm_get_override_edid(struct drm_connector *connector)
2036{
2037 struct edid *override = NULL;
2038
2039 if (connector->override_edid)
2040 override = drm_edid_duplicate(connector->edid_blob_ptr->data);
2041
2042 if (!override)
2043 override = drm_load_edid_firmware(connector);
2044
2045 return IS_ERR(override) ? NULL : override;
2046}
2047
48eaeb76
JN		 2048/**
2049 * drm_add_override_edid_modes - add modes from override/firmware EDID
2050 * @connector: connector we're probing
2051 *
2052 * Add modes from the override/firmware EDID, if available. Only to be used from
2053 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
2054 * failed during drm_get_edid() and caused the override/firmware EDID to be
2055 * skipped.
2056 *
2057 * Return: The number of modes added or 0 if we couldn't find any.
2058 */
2059int drm_add_override_edid_modes(struct drm_connector *connector)
2060{
2061 struct edid *override;
2062 int num_modes = 0;
2063
2064 override = drm_get_override_edid(connector);
2065 if (override) {
2066 drm_connector_update_edid_property(connector, override);
2067 num_modes = drm_add_edid_modes(connector, override);
2068 kfree(override);
2069
2070 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
2071 connector->base.id, connector->name, num_modes);
2072 }
2073
2074 return num_modes;
2075}
2076EXPORT_SYMBOL(drm_add_override_edid_modes);
2077
89fb7536
JN		 2078typedef int read_block_fn(void *context, u8 *buf, unsigned int block, size_t len);
2079
2deaf1c2
JN		 2080static enum edid_block_status edid_block_read(void *block, unsigned int block_num,
2081 read_block_fn read_block,
2082 void *context)
2083{
2084 enum edid_block_status status;
2085 bool is_base_block = block_num == 0;
2086 int try;
2087
2088 for (try = 0; try < 4; try++) {
2089 if (read_block(context, block, block_num, EDID_LENGTH))
2090 return EDID_BLOCK_READ_FAIL;
2091
2092 status = edid_block_check(block, is_base_block);
2093 if (status == EDID_BLOCK_HEADER_REPAIR) {
2094 edid_header_fix(block);
2095
2096 /* Retry with fixed header, update status if that worked. */
2097 status = edid_block_check(block, is_base_block);
2098 if (status == EDID_BLOCK_OK)
2099 status = EDID_BLOCK_HEADER_FIXED;
2100 }
2101
2102 if (edid_block_status_valid(status, edid_block_tag(block)))
2103 break;
2104
2105 /* Fail early for unrepairable base block all zeros. */
2106 if (try == 0 && is_base_block && status == EDID_BLOCK_ZERO)
2107 break;
2108 }
2109
2110 return status;
2111}
2112
18df89fe
LPC		 2113/**
2114 * drm_do_get_edid - get EDID data using a custom EDID block read function
2115 * @connector: connector we're probing
2116 * @get_edid_block: EDID block read function
2117 * @data: private data passed to the block read function
2118 *
2119 * When the I2C adapter connected to the DDC bus is hidden behind a device that
2120 * exposes a different interface to read EDID blocks this function can be used
2121 * to get EDID data using a custom block read function.
2122 *
2123 * As in the general case the DDC bus is accessible by the kernel at the I2C
2124 * level, drivers must make all reasonable efforts to expose it as an I2C
2125 * adapter and use drm_get_edid() instead of abusing this function.
2126 *
0ae865ef 2127 * The EDID may be overridden using debugfs override_edid or firmware EDID
53fd40a9
JN		 2128 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
2129 * order. Having either of them bypasses actual EDID reads.
2130 *
18df89fe
LPC		 2131 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2132 */
2133struct edid *drm_do_get_edid(struct drm_connector *connector,
89fb7536
JN		 2134 read_block_fn read_block,
2135 void *context)
61e57a8d 2136{
c12561ce 2137 enum edid_block_status status;
f1e4c916 2138 int i, invalid_blocks = 0;
b3eb97b6 2139 struct edid *edid, *new;
53fd40a9 2140
b3eb97b6
JN		 2141 edid = drm_get_override_edid(connector);
2142 if (edid)
1c788f69 2143 goto ok;
61e57a8d 2144
c12561ce 2145 edid = kmalloc(EDID_LENGTH, GFP_KERNEL);
e7bd95a7 2146 if (!edid)
61e57a8d 2147 return NULL;
61e57a8d 2148
c12561ce
JN		 2149 status = edid_block_read(edid, 0, read_block, context);
2150
2151 edid_block_status_print(status, edid, 0);
2152
2153 if (status == EDID_BLOCK_READ_FAIL)
1c788f69 2154 goto fail;
c12561ce
JN		 2155
2156 /* FIXME: Clarify what a corrupt EDID actually means. */
2157 if (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION)
2158 connector->edid_corrupt = false;
2159 else
2160 connector->edid_corrupt = true;
2161
2162 if (!edid_block_status_valid(status, edid_block_tag(edid))) {
2163 if (status == EDID_BLOCK_ZERO)
2164 connector->null_edid_counter++;
2165
2166 connector_bad_edid(connector, edid, 1);
1c788f69 2167 goto fail;
c12561ce
JN		 2168 }
2169
f1e4c916 2170 if (!edid_extension_block_count(edid))
1c788f69 2171 goto ok;
61e57a8d 2172
f1e4c916 2173 new = krealloc(edid, edid_size(edid), GFP_KERNEL);
61e57a8d 2174 if (!new)
1c788f69 2175 goto fail;
f14f3686 2176 edid = new;
61e57a8d 2177
f1e4c916
JN		 2178 for (i = 1; i < edid_block_count(edid); i++) {
2179 void *block = (void *)edid_block_data(edid, i);
a28187cc 2180
f1e4c916 2181 status = edid_block_read(block, i, read_block, context);
d3da3f40 2182
f1e4c916 2183 edid_block_status_print(status, block, i);
f934ec8c 2184
d3da3f40
JN		 2185 if (!edid_block_status_valid(status, edid_block_tag(block))) {
2186 if (status == EDID_BLOCK_READ_FAIL)
1c788f69 2187 goto fail;
ccc97def 2188 invalid_blocks++;
d3da3f40 2189 }
0ea75e23
ST		 2190 }
2191
ccc97def 2192 if (invalid_blocks) {
f1e4c916 2193 connector_bad_edid(connector, edid, edid_block_count(edid));
14544d09 2194
ccc97def 2195 edid = edid_filter_invalid_blocks(edid, invalid_blocks);
61e57a8d
AJ		 2196 }
2197
1c788f69 2198ok:
e9a9e076 2199 return edid;
61e57a8d 2200
1c788f69 2201fail:
f14f3686 2202 kfree(edid);
61e57a8d
AJ		 2203 return NULL;
2204}
18df89fe 2205EXPORT_SYMBOL_GPL(drm_do_get_edid);
61e57a8d
AJ		 2206
2207/**
db6cf833
TR		 2208 * drm_probe_ddc() - probe DDC presence
2209 * @adapter: I2C adapter to probe
fc66811c 2210 *
db6cf833 2211 * Return: True on success, false on failure.
61e57a8d 2212 */
fbff4690 2213bool
61e57a8d
AJ		 2214drm_probe_ddc(struct i2c_adapter *adapter)
2215{
2216 unsigned char out;
2217
2218 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
2219}
fbff4690 2220EXPORT_SYMBOL(drm_probe_ddc);
61e57a8d
AJ		 2221
2222/**
2223 * drm_get_edid - get EDID data, if available
2224 * @connector: connector we're probing
db6cf833 2225 * @adapter: I2C adapter to use for DDC
61e57a8d 2226 *
db6cf833 2227 * Poke the given I2C channel to grab EDID data if possible. If found,
61e57a8d
AJ		 2228 * attach it to the connector.
2229 *
db6cf833 2230 * Return: Pointer to valid EDID or NULL if we couldn't find any.
61e57a8d
AJ		 2231 */
2232struct edid *drm_get_edid(struct drm_connector *connector,
2233 struct i2c_adapter *adapter)
2234{
5186421c
SL		 2235 struct edid *edid;
2236
15f080f0
JN		 2237 if (connector->force == DRM_FORCE_OFF)
2238 return NULL;
2239
2240 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
18df89fe 2241 return NULL;
61e57a8d 2242
5186421c
SL		 2243 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
2244 drm_connector_update_edid_property(connector, edid);
2245 return edid;
61e57a8d
AJ		 2246}
2247EXPORT_SYMBOL(drm_get_edid);
2248
d9f91a10
DA		 2249static u32 edid_extract_panel_id(const struct edid *edid)
2250{
2251 /*
e8de4d55
DA		 2252 * We represent the ID as a 32-bit number so it can easily be compared
2253 * with "==".
d9f91a10
DA		 2254 *
2255 * NOTE that we deal with endianness differently for the top half
2256 * of this ID than for the bottom half. The bottom half (the product
2257 * id) gets decoded as little endian by the EDID_PRODUCT_ID because
2258 * that's how everyone seems to interpret it. The top half (the mfg_id)
2259 * gets stored as big endian because that makes
2260 * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier
2261 * to write (it's easier to extract the ASCII). It doesn't really
2262 * matter, though, as long as the number here is unique.
2263 */
2264 return (u32)edid->mfg_id[0] << 24 |
2265 (u32)edid->mfg_id[1] << 16 |
2266 (u32)EDID_PRODUCT_ID(edid);
2267}
2268
2269/**
2270 * drm_edid_get_panel_id - Get a panel's ID through DDC
2271 * @adapter: I2C adapter to use for DDC
2272 *
2273 * This function reads the first block of the EDID of a panel and (assuming
2274 * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value
2275 * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's
2276 * supposed to be different for each different modem of panel.
2277 *
2278 * This function is intended to be used during early probing on devices where
2279 * more than one panel might be present. Because of its intended use it must
2280 * assume that the EDID of the panel is correct, at least as far as the ID
2281 * is concerned (in other words, we don't process any overrides here).
2282 *
2283 * NOTE: it's expected that this function and drm_do_get_edid() will both
2284 * be read the EDID, but there is no caching between them. Since we're only
2285 * reading the first block, hopefully this extra overhead won't be too big.
2286 *
2287 * Return: A 32-bit ID that should be different for each make/model of panel.
2288 * See the functions drm_edid_encode_panel_id() and
2289 * drm_edid_decode_panel_id() for some details on the structure of this
2290 * ID.
2291 */
2292
2293u32 drm_edid_get_panel_id(struct i2c_adapter *adapter)
2294{
2deaf1c2
JN		 2295 enum edid_block_status status;
2296 void *base_block;
2297 u32 panel_id = 0;
d9f91a10
DA		 2298
2299 /*
2300 * There are no manufacturer IDs of 0, so if there is a problem reading
2301 * the EDID then we'll just return 0.
2302 */
2deaf1c2
JN		 2303
2304 base_block = kmalloc(EDID_LENGTH, GFP_KERNEL);
2305 if (!base_block)
d9f91a10
DA		 2306 return 0;
2307
2deaf1c2
JN		 2308 status = edid_block_read(base_block, 0, drm_do_probe_ddc_edid, adapter);
2309
2310 edid_block_status_print(status, base_block, 0);
2311
2312 if (edid_block_status_valid(status, edid_block_tag(base_block)))
2313 panel_id = edid_extract_panel_id(base_block);
2314
2315 kfree(base_block);
d9f91a10
DA		 2316
2317 return panel_id;
2318}
2319EXPORT_SYMBOL(drm_edid_get_panel_id);
2320
5cb8eaa2
LW		 2321/**
2322 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
2323 * @connector: connector we're probing
2324 * @adapter: I2C adapter to use for DDC
2325 *
2326 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
2327 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
2328 * switch DDC to the GPU which is retrieving EDID.
2329 *
2330 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2331 */
2332struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
2333 struct i2c_adapter *adapter)
2334{
36b73b05
TZ		 2335 struct drm_device *dev = connector->dev;
2336 struct pci_dev *pdev = to_pci_dev(dev->dev);
5cb8eaa2
LW		 2337 struct edid *edid;
2338
36b73b05
TZ		 2339 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev)))
2340 return NULL;
2341
5cb8eaa2
LW		 2342 vga_switcheroo_lock_ddc(pdev);
2343 edid = drm_get_edid(connector, adapter);
2344 vga_switcheroo_unlock_ddc(pdev);
2345
2346 return edid;
2347}
2348EXPORT_SYMBOL(drm_get_edid_switcheroo);
2349
51f8da59
JN		 2350/**
2351 * drm_edid_duplicate - duplicate an EDID and the extensions
2352 * @edid: EDID to duplicate
2353 *
db6cf833 2354 * Return: Pointer to duplicated EDID or NULL on allocation failure.
51f8da59
JN		 2355 */
2356struct edid *drm_edid_duplicate(const struct edid *edid)
2357{
f1e4c916 2358 return kmemdup(edid, edid_size(edid), GFP_KERNEL);
51f8da59
JN		 2359}
2360EXPORT_SYMBOL(drm_edid_duplicate);
2361
61e57a8d
AJ		 2362/*** EDID parsing ***/
2363
f453ba04
DA		 2364/**
2365 * edid_get_quirks - return quirk flags for a given EDID
2366 * @edid: EDID to process
2367 *
2368 * This tells subsequent routines what fixes they need to apply.
2369 */
170178fe 2370static u32 edid_get_quirks(const struct edid *edid)
f453ba04 2371{
e8de4d55 2372 u32 panel_id = edid_extract_panel_id(edid);
23c4cfbd 2373 const struct edid_quirk *quirk;
f453ba04
DA		 2374 int i;
2375
2376 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
2377 quirk = &edid_quirk_list[i];
e8de4d55 2378 if (quirk->panel_id == panel_id)
f453ba04
DA		 2379 return quirk->quirks;
2380 }
2381
2382 return 0;
2383}
2384
2385#define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
339d202c 2386#define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
f453ba04 2387
f453ba04
DA		 2388/**
2389 * edid_fixup_preferred - set preferred modes based on quirk list
2390 * @connector: has mode list to fix up
2391 * @quirks: quirks list
2392 *
2393 * Walk the mode list for @connector, clearing the preferred status
2394 * on existing modes and setting it anew for the right mode ala @quirks.
2395 */
2396static void edid_fixup_preferred(struct drm_connector *connector,
2397 u32 quirks)
2398{
2399 struct drm_display_mode *t, *cur_mode, *preferred_mode;
f890607b 2400 int target_refresh = 0;
339d202c 2401 int cur_vrefresh, preferred_vrefresh;
f453ba04
DA		 2402
2403 if (list_empty(&connector->probed_modes))
2404 return;
2405
2406 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
2407 target_refresh = 60;
2408 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
2409 target_refresh = 75;
2410
2411 preferred_mode = list_first_entry(&connector->probed_modes,
2412 struct drm_display_mode, head);
2413
2414 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
2415 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
2416
2417 if (cur_mode == preferred_mode)
2418 continue;
2419
2420 /* Largest mode is preferred */
2421 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
2422 preferred_mode = cur_mode;
2423
0425662f
VS		 2424 cur_vrefresh = drm_mode_vrefresh(cur_mode);
2425 preferred_vrefresh = drm_mode_vrefresh(preferred_mode);
f453ba04
DA		 2426 /* At a given size, try to get closest to target refresh */
2427 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
339d202c
AD		 2428 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
2429 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
f453ba04
DA		 2430 preferred_mode = cur_mode;
2431 }
2432 }
2433
2434 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
2435}
2436
f6e252ba
AJ		 2437static bool
2438mode_is_rb(const struct drm_display_mode *mode)
2439{
2440 return (mode->htotal - mode->hdisplay == 160) &&
2441 (mode->hsync_end - mode->hdisplay == 80) &&
2442 (mode->hsync_end - mode->hsync_start == 32) &&
2443 (mode->vsync_start - mode->vdisplay == 3);
2444}
2445
33c7531d
AJ		 2446/*
2447 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
2448 * @dev: Device to duplicate against
2449 * @hsize: Mode width
2450 * @vsize: Mode height
2451 * @fresh: Mode refresh rate
f6e252ba 2452 * @rb: Mode reduced-blanking-ness
33c7531d
AJ		 2453 *
2454 * Walk the DMT mode list looking for a match for the given parameters.
db6cf833
TR		 2455 *
2456 * Return: A newly allocated copy of the mode, or NULL if not found.
33c7531d 2457 */
1d42bbc8 2458struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
f6e252ba
AJ		 2459 int hsize, int vsize, int fresh,
2460 bool rb)
559ee21d 2461{
07a5e632 2462 int i;
559ee21d 2463
a6b21831 2464 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
b1f559ec 2465 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
948de842 2466
f8b46a05
AJ		 2467 if (hsize != ptr->hdisplay)
2468 continue;
2469 if (vsize != ptr->vdisplay)
2470 continue;
2471 if (fresh != drm_mode_vrefresh(ptr))
2472 continue;
f6e252ba
AJ		 2473 if (rb != mode_is_rb(ptr))
2474 continue;
f8b46a05
AJ		 2475
2476 return drm_mode_duplicate(dev, ptr);
559ee21d 2477 }
f8b46a05
AJ		 2478
2479 return NULL;
559ee21d 2480}
1d42bbc8 2481EXPORT_SYMBOL(drm_mode_find_dmt);
23425cae 2482
e379814b 2483static bool is_display_descriptor(const struct detailed_timing *descriptor, u8 type)
a7a131ac 2484{
e379814b
JN		 2485 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
2486 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.pad1) != 2);
2487 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.type) != 3);
2488
2489 return descriptor->pixel_clock == 0 &&
2490 descriptor->data.other_data.pad1 == 0 &&
2491 descriptor->data.other_data.type == type;
a7a131ac
VS		 2492}
2493
a9b1f15f 2494static bool is_detailed_timing_descriptor(const struct detailed_timing *descriptor)
f447dd1f 2495{
a9b1f15f
JN		 2496 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
2497
2498 return descriptor->pixel_clock != 0;
f447dd1f
VS		 2499}
2500
4194442d 2501typedef void detailed_cb(const struct detailed_timing *timing, void *closure);
d1ff6409 2502
4d76a221 2503static void
eed628f1 2504cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
4d76a221 2505{
7304b981 2506 int i, n;
4966b2a9 2507 u8 d = ext[0x02];
eed628f1 2508 const u8 *det_base = ext + d;
4d76a221 2509
7304b981
VS		 2510 if (d < 4 || d > 127)
2511 return;
2512
4966b2a9 2513 n = (127 - d) / 18;
4d76a221 2514 for (i = 0; i < n; i++)
eed628f1 2515 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
4d76a221
AJ		 2516}
2517
cbba98f8 2518static void
eed628f1 2519vtb_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
cbba98f8
AJ		 2520{
2521 unsigned int i, n = min((int)ext[0x02], 6);
eed628f1 2522 const u8 *det_base = ext + 5;
cbba98f8
AJ		 2523
2524 if (ext[0x01] != 1)
2525 return; /* unknown version */
2526
2527 for (i = 0; i < n; i++)
eed628f1 2528 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
cbba98f8
AJ		 2529}
2530
d1ff6409 2531static void
eed628f1 2532drm_for_each_detailed_block(const struct edid *edid, detailed_cb *cb, void *closure)
d1ff6409
AJ		 2533{
2534 int i;
d1ff6409
AJ		 2535
2536 if (edid == NULL)
2537 return;
2538
2539 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
2540 cb(&(edid->detailed_timings[i]), closure);
2541
f1e4c916
JN		 2542 for (i = 0; i < edid_extension_block_count(edid); i++) {
2543 const u8 *ext = edid_extension_block_data(edid, i);
948de842 2544
4d76a221
AJ		 2545 switch (*ext) {
2546 case CEA_EXT:
2547 cea_for_each_detailed_block(ext, cb, closure);
2548 break;
cbba98f8
AJ		 2549 case VTB_EXT:
2550 vtb_for_each_detailed_block(ext, cb, closure);
2551 break;
4d76a221
AJ		 2552 default:
2553 break;
2554 }
2555 }
d1ff6409
AJ		 2556}
2557
2558static void
4194442d 2559is_rb(const struct detailed_timing *descriptor, void *data)
d1ff6409 2560{
90fd588f 2561 bool *res = data;
a7a131ac 2562
90fd588f 2563 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
a7a131ac
VS		 2564 return;
2565
90fd588f
JN		 2566 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
2567 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.cvt.flags) != 15);
2568
2569 if (descriptor->data.other_data.data.range.flags == DRM_EDID_CVT_SUPPORT_FLAG &&
2570 descriptor->data.other_data.data.range.formula.cvt.flags & 0x10)
2571 *res = true;
d1ff6409
AJ		 2572}
2573
2574/* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
2575static bool
c14e7241 2576drm_monitor_supports_rb(const struct edid *edid)
d1ff6409
AJ		 2577{
2578 if (edid->revision >= 4) {
b196a498 2579 bool ret = false;
948de842 2580
eed628f1 2581 drm_for_each_detailed_block(edid, is_rb, &ret);
d1ff6409
AJ		 2582 return ret;
2583 }
2584
2585 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
2586}
2587
7a374350 2588static void
4194442d 2589find_gtf2(const struct detailed_timing *descriptor, void *data)
7a374350 2590{
4194442d 2591 const struct detailed_timing **res = data;
a7a131ac 2592
c8a4beba 2593 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
a7a131ac
VS		 2594 return;
2595
c8a4beba
JN		 2596 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
2597
2598 if (descriptor->data.other_data.data.range.flags == 0x02)
2599 *res = descriptor;
7a374350
AJ		 2600}
2601
2602/* Secondary GTF curve kicks in above some break frequency */
2603static int
c14e7241 2604drm_gtf2_hbreak(const struct edid *edid)
7a374350 2605{
4194442d 2606 const struct detailed_timing *descriptor = NULL;
c8a4beba 2607
eed628f1 2608 drm_for_each_detailed_block(edid, find_gtf2, &descriptor);
948de842 2609
c8a4beba
JN		 2610 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12);
2611
2612 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.hfreq_start_khz * 2 : 0;
7a374350
AJ		 2613}
2614
2615static int
c14e7241 2616drm_gtf2_2c(const struct edid *edid)
7a374350 2617{
4194442d 2618 const struct detailed_timing *descriptor = NULL;
c8a4beba 2619
eed628f1 2620 drm_for_each_detailed_block(edid, find_gtf2, &descriptor);
c8a4beba
JN		 2621
2622 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.c) != 13);
948de842 2623
c8a4beba 2624 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.c : 0;
7a374350
AJ		 2625}
2626
2627static int
c14e7241 2628drm_gtf2_m(const struct edid *edid)
7a374350 2629{
4194442d 2630 const struct detailed_timing *descriptor = NULL;
948de842 2631
eed628f1 2632 drm_for_each_detailed_block(edid, find_gtf2, &descriptor);
c8a4beba
JN		 2633
2634 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.m) != 14);
2635
2636 return descriptor ? le16_to_cpu(descriptor->data.other_data.data.range.formula.gtf2.m) : 0;
7a374350
AJ		 2637}
2638
2639static int
c14e7241 2640drm_gtf2_k(const struct edid *edid)
7a374350 2641{
4194442d 2642 const struct detailed_timing *descriptor = NULL;
c8a4beba 2643
eed628f1 2644 drm_for_each_detailed_block(edid, find_gtf2, &descriptor);
948de842 2645
c8a4beba
JN		 2646 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.k) != 16);
2647
2648 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.k : 0;
7a374350
AJ		 2649}
2650
2651static int
c14e7241 2652drm_gtf2_2j(const struct edid *edid)
7a374350 2653{
4194442d 2654 const struct detailed_timing *descriptor = NULL;
c8a4beba 2655
eed628f1 2656 drm_for_each_detailed_block(edid, find_gtf2, &descriptor);
c8a4beba
JN		 2657
2658 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.j) != 17);
948de842 2659
c8a4beba 2660 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.j : 0;
7a374350
AJ		 2661}
2662
2663/**
2664 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
2665 * @edid: EDID block to scan
2666 */
c14e7241 2667static int standard_timing_level(const struct edid *edid)
7a374350
AJ		 2668{
2669 if (edid->revision >= 2) {
2670 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
2671 return LEVEL_CVT;
2672 if (drm_gtf2_hbreak(edid))
2673 return LEVEL_GTF2;
bfef04ad
LS		 2674 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
2675 return LEVEL_GTF;
7a374350
AJ		 2676 }
2677 return LEVEL_DMT;
2678}
2679
23425cae
AJ		 2680/*
2681 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
2682 * monitors fill with ascii space (0x20) instead.
2683 */
2684static int
2685bad_std_timing(u8 a, u8 b)
2686{
2687 return (a == 0x00 && b == 0x00) ||
2688 (a == 0x01 && b == 0x01) ||
2689 (a == 0x20 && b == 0x20);
2690}
2691
58911c24
VS		 2692static int drm_mode_hsync(const struct drm_display_mode *mode)
2693{
2694 if (mode->htotal <= 0)
2695 return 0;
2696
2697 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal);
2698}
2699
f453ba04
DA		 2700/**
2701 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
fc66811c
DV		 2702 * @connector: connector of for the EDID block
2703 * @edid: EDID block to scan
f453ba04
DA		 2704 * @t: standard timing params
2705 *
2706 * Take the standard timing params (in this case width, aspect, and refresh)
5c61259e 2707 * and convert them into a real mode using CVT/GTF/DMT.
f453ba04 2708 */
7ca6adb3 2709static struct drm_display_mode *
c14e7241 2710drm_mode_std(struct drm_connector *connector, const struct edid *edid,
fcfb2ea1 2711 const struct std_timing *t)
f453ba04 2712{
7ca6adb3
AJ		 2713 struct drm_device *dev = connector->dev;
2714 struct drm_display_mode *m, *mode = NULL;
5c61259e
ZY		 2715 int hsize, vsize;
2716 int vrefresh_rate;
0454beab
MD		 2717 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
2718 >> EDID_TIMING_ASPECT_SHIFT;
5c61259e
ZY		 2719 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
2720 >> EDID_TIMING_VFREQ_SHIFT;
7a374350 2721 int timing_level = standard_timing_level(edid);
5c61259e 2722
23425cae
AJ		 2723 if (bad_std_timing(t->hsize, t->vfreq_aspect))
2724 return NULL;
2725
5c61259e
ZY		 2726 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
2727 hsize = t->hsize * 8 + 248;
2728 /* vrefresh_rate = vfreq + 60 */
2729 vrefresh_rate = vfreq + 60;
2730 /* the vdisplay is calculated based on the aspect ratio */
f066a17d 2731 if (aspect_ratio == 0) {
464fdeca 2732 if (edid->revision < 3)
f066a17d
AJ		 2733 vsize = hsize;
2734 else
2735 vsize = (hsize * 10) / 16;
2736 } else if (aspect_ratio == 1)
f453ba04 2737 vsize = (hsize * 3) / 4;
0454beab 2738 else if (aspect_ratio == 2)
f453ba04
DA		 2739 vsize = (hsize * 4) / 5;
2740 else
2741 vsize = (hsize * 9) / 16;
a0910c8e
AJ		 2742
2743 /* HDTV hack, part 1 */
2744 if (vrefresh_rate == 60 &&
2745 ((hsize == 1360 && vsize == 765) ||
2746 (hsize == 1368 && vsize == 769))) {
2747 hsize = 1366;
2748 vsize = 768;
2749 }
2750
7ca6adb3
AJ		 2751 /*
2752 * If this connector already has a mode for this size and refresh
2753 * rate (because it came from detailed or CVT info), use that
2754 * instead. This way we don't have to guess at interlace or
2755 * reduced blanking.
2756 */
522032da 2757 list_for_each_entry(m, &connector->probed_modes, head)
7ca6adb3
AJ		 2758 if (m->hdisplay == hsize && m->vdisplay == vsize &&
2759 drm_mode_vrefresh(m) == vrefresh_rate)
2760 return NULL;
2761
a0910c8e
AJ		 2762 /* HDTV hack, part 2 */
2763 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
2764 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
d50ba256 2765 false);
a5ef6567
JM		 2766 if (!mode)
2767 return NULL;
559ee21d 2768 mode->hdisplay = 1366;
a4967de6
AJ		 2769 mode->hsync_start = mode->hsync_start - 1;
2770 mode->hsync_end = mode->hsync_end - 1;
559ee21d
ZY		 2771 return mode;
2772 }
a0910c8e 2773
559ee21d 2774 /* check whether it can be found in default mode table */
f6e252ba
AJ		 2775 if (drm_monitor_supports_rb(edid)) {
2776 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
2777 true);
2778 if (mode)
2779 return mode;
2780 }
2781 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
559ee21d
ZY		 2782 if (mode)
2783 return mode;
2784
f6e252ba 2785 /* okay, generate it */
5c61259e
ZY		 2786 switch (timing_level) {
2787 case LEVEL_DMT:
5c61259e
ZY		 2788 break;
2789 case LEVEL_GTF:
2790 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2791 break;
7a374350
AJ		 2792 case LEVEL_GTF2:
2793 /*
2794 * This is potentially wrong if there's ever a monitor with
2795 * more than one ranges section, each claiming a different
2796 * secondary GTF curve. Please don't do that.
2797 */
2798 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
fc48f169
TI		 2799 if (!mode)
2800 return NULL;
7a374350 2801 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
aefd330e 2802 drm_mode_destroy(dev, mode);
7a374350
AJ		 2803 mode = drm_gtf_mode_complex(dev, hsize, vsize,
2804 vrefresh_rate, 0, 0,
2805 drm_gtf2_m(edid),
2806 drm_gtf2_2c(edid),
2807 drm_gtf2_k(edid),
2808 drm_gtf2_2j(edid));
2809 }
2810 break;
5c61259e 2811 case LEVEL_CVT:
d50ba256
DA		 2812 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
2813 false);
5c61259e
ZY		 2814 break;
2815 }
f453ba04
DA		 2816 return mode;
2817}
2818
b58db2c6
AJ		 2819/*
2820 * EDID is delightfully ambiguous about how interlaced modes are to be
2821 * encoded. Our internal representation is of frame height, but some
2822 * HDTV detailed timings are encoded as field height.
2823 *
2824 * The format list here is from CEA, in frame size. Technically we
2825 * should be checking refresh rate too. Whatever.
2826 */
2827static void
2828drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
fcfb2ea1 2829 const struct detailed_pixel_timing *pt)
b58db2c6
AJ		 2830{
2831 int i;
2832 static const struct {
2833 int w, h;
2834 } cea_interlaced[] = {
2835 { 1920, 1080 },
2836 { 720, 480 },
2837 { 1440, 480 },
2838 { 2880, 480 },
2839 { 720, 576 },
2840 { 1440, 576 },
2841 { 2880, 576 },
2842 };
b58db2c6
AJ		 2843
2844 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
2845 return;
2846
3c581411 2847 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
b58db2c6
AJ		 2848 if ((mode->hdisplay == cea_interlaced[i].w) &&
2849 (mode->vdisplay == cea_interlaced[i].h / 2)) {
2850 mode->vdisplay *= 2;
2851 mode->vsync_start *= 2;
2852 mode->vsync_end *= 2;
2853 mode->vtotal *= 2;
2854 mode->vtotal |= 1;
2855 }
2856 }
2857
2858 mode->flags |= DRM_MODE_FLAG_INTERLACE;
2859}
2860
f453ba04
DA		 2861/**
2862 * drm_mode_detailed - create a new mode from an EDID detailed timing section
2863 * @dev: DRM device (needed to create new mode)
2864 * @edid: EDID block
2865 * @timing: EDID detailed timing info
2866 * @quirks: quirks to apply
2867 *
2868 * An EDID detailed timing block contains enough info for us to create and
2869 * return a new struct drm_display_mode.
2870 */
2871static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
c14e7241 2872 const struct edid *edid,
fcfb2ea1 2873 const struct detailed_timing *timing,
f453ba04
DA		 2874 u32 quirks)
2875{
2876 struct drm_display_mode *mode;
fcfb2ea1 2877 const struct detailed_pixel_timing *pt = &timing->data.pixel_data;
0454beab
MD		 2878 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
2879 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
2880 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
2881 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
e14cbee4
MD		 2882 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
2883 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
16dad1d7 2884 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
e14cbee4 2885 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
f453ba04 2886
fc438966 2887 /* ignore tiny modes */
0454beab 2888 if (hactive < 64 || vactive < 64)
fc438966
AJ		 2889 return NULL;
2890
0454beab 2891 if (pt->misc & DRM_EDID_PT_STEREO) {
c7d015f3 2892 DRM_DEBUG_KMS("stereo mode not supported\n");
f453ba04
DA		 2893 return NULL;
2894 }
0454beab 2895 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
c7d015f3 2896 DRM_DEBUG_KMS("composite sync not supported\n");
f453ba04
DA		 2897 }
2898
fcb45611
ZY		 2899 /* it is incorrect if hsync/vsync width is zero */
2900 if (!hsync_pulse_width || !vsync_pulse_width) {
2901 DRM_DEBUG_KMS("Incorrect Detailed timing. "
2902 "Wrong Hsync/Vsync pulse width\n");
2903 return NULL;
2904 }
bc42aabc
AJ		 2905
2906 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
2907 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
2908 if (!mode)
2909 return NULL;
2910
2911 goto set_size;
2912 }
2913
f453ba04
DA		 2914 mode = drm_mode_create(dev);
2915 if (!mode)
2916 return NULL;
2917
f453ba04 2918 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
faacff8e
JN		 2919 mode->clock = 1088 * 10;
2920 else
2921 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
0454beab
MD		 2922
2923 mode->hdisplay = hactive;
2924 mode->hsync_start = mode->hdisplay + hsync_offset;
2925 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
2926 mode->htotal = mode->hdisplay + hblank;
2927
2928 mode->vdisplay = vactive;
2929 mode->vsync_start = mode->vdisplay + vsync_offset;
2930 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
2931 mode->vtotal = mode->vdisplay + vblank;
f453ba04 2932
7064fef5
JB		 2933 /* Some EDIDs have bogus h/vtotal values */
2934 if (mode->hsync_end > mode->htotal)
2935 mode->htotal = mode->hsync_end + 1;
2936 if (mode->vsync_end > mode->vtotal)
2937 mode->vtotal = mode->vsync_end + 1;
2938
b58db2c6 2939 drm_mode_do_interlace_quirk(mode, pt);
f453ba04
DA		 2940
2941 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
faacff8e
JN		 2942 mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC;
2943 } else {
2944 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
2945 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
2946 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
2947 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
f453ba04
DA		 2948 }
2949
bc42aabc 2950set_size:
e14cbee4
MD		 2951 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
2952 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
f453ba04
DA		 2953
2954 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
2955 mode->width_mm *= 10;
2956 mode->height_mm *= 10;
2957 }
2958
2959 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
2960 mode->width_mm = edid->width_cm * 10;
2961 mode->height_mm = edid->height_cm * 10;
2962 }
2963
bc42aabc
AJ		 2964 mode->type = DRM_MODE_TYPE_DRIVER;
2965 drm_mode_set_name(mode);
2966
f453ba04
DA		 2967 return mode;
2968}
2969
b17e52ef 2970static bool
b1f559ec 2971mode_in_hsync_range(const struct drm_display_mode *mode,
c14e7241 2972 const struct edid *edid, const u8 *t)
b17e52ef
AJ		 2973{
2974 int hsync, hmin, hmax;
2975
2976 hmin = t[7];
2977 if (edid->revision >= 4)
2978 hmin += ((t[4] & 0x04) ? 255 : 0);
2979 hmax = t[8];
2980 if (edid->revision >= 4)
2981 hmax += ((t[4] & 0x08) ? 255 : 0);
07a5e632 2982 hsync = drm_mode_hsync(mode);
07a5e632 2983
b17e52ef
AJ		 2984 return (hsync <= hmax && hsync >= hmin);
2985}
2986
2987static bool
b1f559ec 2988mode_in_vsync_range(const struct drm_display_mode *mode,
c14e7241 2989 const struct edid *edid, const u8 *t)
b17e52ef
AJ		 2990{
2991 int vsync, vmin, vmax;
2992
2993 vmin = t[5];
2994 if (edid->revision >= 4)
2995 vmin += ((t[4] & 0x01) ? 255 : 0);
2996 vmax = t[6];
2997 if (edid->revision >= 4)
2998 vmax += ((t[4] & 0x02) ? 255 : 0);
2999 vsync = drm_mode_vrefresh(mode);
3000
3001 return (vsync <= vmax && vsync >= vmin);
3002}
3003
3004static u32
c14e7241 3005range_pixel_clock(const struct edid *edid, const u8 *t)
b17e52ef
AJ		 3006{
3007 /* unspecified */
3008 if (t[9] == 0 || t[9] == 255)
3009 return 0;
3010
3011 /* 1.4 with CVT support gives us real precision, yay */
3012 if (edid->revision >= 4 && t[10] == 0x04)
3013 return (t[9] * 10000) - ((t[12] >> 2) * 250);
3014
3015 /* 1.3 is pathetic, so fuzz up a bit */
3016 return t[9] * 10000 + 5001;
3017}
3018
b17e52ef 3019static bool
c14e7241 3020mode_in_range(const struct drm_display_mode *mode, const struct edid *edid,
fcfb2ea1 3021 const struct detailed_timing *timing)
b17e52ef
AJ		 3022{
3023 u32 max_clock;
fcfb2ea1 3024 const u8 *t = (const u8 *)timing;
b17e52ef
AJ		 3025
3026 if (!mode_in_hsync_range(mode, edid, t))
07a5e632
AJ		 3027 return false;
3028
b17e52ef 3029 if (!mode_in_vsync_range(mode, edid, t))
07a5e632
AJ		 3030 return false;
3031
b17e52ef 3032 if ((max_clock = range_pixel_clock(edid, t)))
07a5e632
AJ		 3033 if (mode->clock > max_clock)
3034 return false;
b17e52ef
AJ		 3035
3036 /* 1.4 max horizontal check */
3037 if (edid->revision >= 4 && t[10] == 0x04)
3038 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
3039 return false;
3040
3041 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
3042 return false;
07a5e632
AJ		 3043
3044 return true;
3045}
3046
7b668ebe
TI		 3047static bool valid_inferred_mode(const struct drm_connector *connector,
3048 const struct drm_display_mode *mode)
3049{
85f8fcd6 3050 const struct drm_display_mode *m;
7b668ebe
TI		 3051 bool ok = false;
3052
3053 list_for_each_entry(m, &connector->probed_modes, head) {
3054 if (mode->hdisplay == m->hdisplay &&
3055 mode->vdisplay == m->vdisplay &&
3056 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
3057 return false; /* duplicated */
3058 if (mode->hdisplay <= m->hdisplay &&
3059 mode->vdisplay <= m->vdisplay)
3060 ok = true;
3061 }
3062 return ok;
3063}
3064
b17e52ef 3065static int
c14e7241 3066drm_dmt_modes_for_range(struct drm_connector *connector, const struct edid *edid,
fcfb2ea1 3067 const struct detailed_timing *timing)
07a5e632
AJ		 3068{
3069 int i, modes = 0;
3070 struct drm_display_mode *newmode;
3071 struct drm_device *dev = connector->dev;
3072
a6b21831 3073 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
7b668ebe
TI		 3074 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
3075 valid_inferred_mode(connector, drm_dmt_modes + i)) {
07a5e632
AJ		 3076 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
3077 if (newmode) {
3078 drm_mode_probed_add(connector, newmode);
3079 modes++;
3080 }
3081 }
3082 }
3083
3084 return modes;
3085}
3086
c09dedb7
TI		 3087/* fix up 1366x768 mode from 1368x768;
3088 * GFT/CVT can't express 1366 width which isn't dividable by 8
3089 */
969218fe 3090void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
c09dedb7
TI		 3091{
3092 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
3093 mode->hdisplay = 1366;
3094 mode->hsync_start--;
3095 mode->hsync_end--;
3096 drm_mode_set_name(mode);
3097 }
3098}
3099
b309bd37 3100static int
c14e7241 3101drm_gtf_modes_for_range(struct drm_connector *connector, const struct edid *edid,
fcfb2ea1 3102 const struct detailed_timing *timing)
b309bd37
AJ		 3103{
3104 int i, modes = 0;
3105 struct drm_display_mode *newmode;
3106 struct drm_device *dev = connector->dev;
3107
a6b21831 3108 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
b309bd37 3109 const struct minimode *m = &extra_modes[i];
948de842 3110
b309bd37 3111 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
fc48f169
TI		 3112 if (!newmode)
3113 return modes;
b309bd37 3114
969218fe 3115 drm_mode_fixup_1366x768(newmode);
7b668ebe
TI		 3116 if (!mode_in_range(newmode, edid, timing) ||
3117 !valid_inferred_mode(connector, newmode)) {
b309bd37
AJ		 3118 drm_mode_destroy(dev, newmode);
3119 continue;
3120 }
3121
3122 drm_mode_probed_add(connector, newmode);
3123 modes++;
3124 }
3125
3126 return modes;
3127}
3128
3129static int
c14e7241 3130drm_cvt_modes_for_range(struct drm_connector *connector, const struct edid *edid,
fcfb2ea1 3131 const struct detailed_timing *timing)
b309bd37
AJ		 3132{
3133 int i, modes = 0;
3134 struct drm_display_mode *newmode;
3135 struct drm_device *dev = connector->dev;
3136 bool rb = drm_monitor_supports_rb(edid);
3137
a6b21831 3138 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
b309bd37 3139 const struct minimode *m = &extra_modes[i];
948de842 3140
b309bd37 3141 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
fc48f169
TI		 3142 if (!newmode)
3143 return modes;
b309bd37 3144
969218fe 3145 drm_mode_fixup_1366x768(newmode);
7b668ebe
TI		 3146 if (!mode_in_range(newmode, edid, timing) ||
3147 !valid_inferred_mode(connector, newmode)) {
b309bd37
AJ		 3148 drm_mode_destroy(dev, newmode);
3149 continue;
3150 }
3151
3152 drm_mode_probed_add(connector, newmode);
3153 modes++;
3154 }
3155
3156 return modes;
3157}
3158
13931579 3159static void
4194442d 3160do_inferred_modes(const struct detailed_timing *timing, void *c)
9340d8cf 3161{
13931579 3162 struct detailed_mode_closure *closure = c;
fcfb2ea1
JN		 3163 const struct detailed_non_pixel *data = &timing->data.other_data;
3164 const struct detailed_data_monitor_range *range = &data->data.range;
9340d8cf 3165
e379814b 3166 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
cb21aafe
AJ		 3167 return;
3168
3169 closure->modes += drm_dmt_modes_for_range(closure->connector,
3170 closure->edid,
3171 timing);
4d23f484 3172
b309bd37
AJ		 3173 if (!version_greater(closure->edid, 1, 1))
3174 return; /* GTF not defined yet */
3175
3176 switch (range->flags) {
3177 case 0x02: /* secondary gtf, XXX could do more */
3178 case 0x00: /* default gtf */
3179 closure->modes += drm_gtf_modes_for_range(closure->connector,
3180 closure->edid,
3181 timing);
3182 break;
3183 case 0x04: /* cvt, only in 1.4+ */
3184 if (!version_greater(closure->edid, 1, 3))
3185 break;
3186
3187 closure->modes += drm_cvt_modes_for_range(closure->connector,
3188 closure->edid,
3189 timing);
3190 break;
3191 case 0x01: /* just the ranges, no formula */
3192 default:
3193 break;
3194 }
13931579 3195}
69da3015 3196
13931579 3197static int
c14e7241 3198add_inferred_modes(struct drm_connector *connector, const struct edid *edid)
13931579
AJ		 3199{
3200 struct detailed_mode_closure closure = {
d456ea2e
JL		 3201 .connector = connector,
3202 .edid = edid,
13931579 3203 };
9340d8cf 3204
13931579 3205 if (version_greater(edid, 1, 0))
eed628f1 3206 drm_for_each_detailed_block(edid, do_inferred_modes, &closure);
9340d8cf 3207
13931579 3208 return closure.modes;
9340d8cf
AJ		 3209}
3210
2255be14 3211static int
fcfb2ea1 3212drm_est3_modes(struct drm_connector *connector, const struct detailed_timing *timing)
2255be14
AJ		 3213{
3214 int i, j, m, modes = 0;
3215 struct drm_display_mode *mode;
fcfb2ea1 3216 const u8 *est = ((const u8 *)timing) + 6;
2255be14
AJ		 3217
3218 for (i = 0; i < 6; i++) {
891a7469 3219 for (j = 7; j >= 0; j--) {
2255be14 3220 m = (i * 8) + (7 - j);
3c581411 3221 if (m >= ARRAY_SIZE(est3_modes))
2255be14
AJ		 3222 break;
3223 if (est[i] & (1 << j)) {
1d42bbc8
DA		 3224 mode = drm_mode_find_dmt(connector->dev,
3225 est3_modes[m].w,
3226 est3_modes[m].h,
f6e252ba
AJ		 3227 est3_modes[m].r,
3228 est3_modes[m].rb);
2255be14
AJ		 3229 if (mode) {
3230 drm_mode_probed_add(connector, mode);
3231 modes++;
3232 }
3233 }
3234 }
3235 }
3236
3237 return modes;
3238}
3239
13931579 3240static void
4194442d 3241do_established_modes(const struct detailed_timing *timing, void *c)
9cf00977 3242{
13931579 3243 struct detailed_mode_closure *closure = c;
9cf00977 3244
e379814b 3245 if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS))
a7a131ac
VS		 3246 return;
3247
3248 closure->modes += drm_est3_modes(closure->connector, timing);
13931579 3249}
9cf00977 3250
13931579
AJ		 3251/**
3252 * add_established_modes - get est. modes from EDID and add them
db6cf833 3253 * @connector: connector to add mode(s) to
13931579
AJ		 3254 * @edid: EDID block to scan
3255 *
3256 * Each EDID block contains a bitmap of the supported "established modes" list
3257 * (defined above). Tease them out and add them to the global modes list.
3258 */
3259static int
c14e7241 3260add_established_modes(struct drm_connector *connector, const struct edid *edid)
13931579
AJ		 3261{
3262 struct drm_device *dev = connector->dev;
3263 unsigned long est_bits = edid->established_timings.t1 |
3264 (edid->established_timings.t2 << 8) |
3265 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
3266 int i, modes = 0;
3267 struct detailed_mode_closure closure = {
d456ea2e
JL		 3268 .connector = connector,
3269 .edid = edid,
13931579 3270 };
9cf00977 3271
13931579
AJ		 3272 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
3273 if (est_bits & (1<<i)) {
3274 struct drm_display_mode *newmode;
948de842 3275
13931579
AJ		 3276 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
3277 if (newmode) {
3278 drm_mode_probed_add(connector, newmode);
3279 modes++;
3280 }
3281 }
9cf00977
AJ		 3282 }
3283
13931579 3284 if (version_greater(edid, 1, 0))
eed628f1
JN		 3285 drm_for_each_detailed_block(edid, do_established_modes,
3286 &closure);
13931579
AJ		 3287
3288 return modes + closure.modes;
3289}
3290
3291static void
4194442d 3292do_standard_modes(const struct detailed_timing *timing, void *c)
13931579
AJ		 3293{
3294 struct detailed_mode_closure *closure = c;
fcfb2ea1 3295 const struct detailed_non_pixel *data = &timing->data.other_data;
13931579 3296 struct drm_connector *connector = closure->connector;
c14e7241 3297 const struct edid *edid = closure->edid;
a7a131ac 3298 int i;
13931579 3299
e379814b 3300 if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES))
a7a131ac 3301 return;
9cf00977 3302
a7a131ac 3303 for (i = 0; i < 6; i++) {
fcfb2ea1 3304 const struct std_timing *std = &data->data.timings[i];
a7a131ac
VS		 3305 struct drm_display_mode *newmode;
3306
3307 newmode = drm_mode_std(connector, edid, std);
3308 if (newmode) {
3309 drm_mode_probed_add(connector, newmode);
3310 closure->modes++;
9cf00977 3311 }
9cf00977 3312 }
9cf00977
AJ		 3313}
3314
f453ba04 3315/**
13931579 3316 * add_standard_modes - get std. modes from EDID and add them
db6cf833 3317 * @connector: connector to add mode(s) to
f453ba04 3318 * @edid: EDID block to scan
f453ba04 3319 *
13931579
AJ		 3320 * Standard modes can be calculated using the appropriate standard (DMT,
3321 * GTF or CVT. Grab them from @edid and add them to the list.
f453ba04 3322 */
13931579 3323static int
c14e7241 3324add_standard_modes(struct drm_connector *connector, const struct edid *edid)
f453ba04 3325{
9cf00977 3326 int i, modes = 0;
13931579 3327 struct detailed_mode_closure closure = {
d456ea2e
JL		 3328 .connector = connector,
3329 .edid = edid,
13931579
AJ		 3330 };
3331
3332 for (i = 0; i < EDID_STD_TIMINGS; i++) {
3333 struct drm_display_mode *newmode;
3334
3335 newmode = drm_mode_std(connector, edid,
464fdeca 3336 &edid->standard_timings[i]);
13931579
AJ		 3337 if (newmode) {
3338 drm_mode_probed_add(connector, newmode);
3339 modes++;
3340 }
3341 }
3342
3343 if (version_greater(edid, 1, 0))
eed628f1 3344 drm_for_each_detailed_block(edid, do_standard_modes,
13931579
AJ		 3345 &closure);
3346
3347 /* XXX should also look for standard codes in VTB blocks */
3348
3349 return modes + closure.modes;
3350}
f453ba04 3351
13931579 3352static int drm_cvt_modes(struct drm_connector *connector,
fcfb2ea1 3353 const struct detailed_timing *timing)
13931579
AJ		 3354{
3355 int i, j, modes = 0;
3356 struct drm_display_mode *newmode;
3357 struct drm_device *dev = connector->dev;
fcfb2ea1 3358 const struct cvt_timing *cvt;
13931579
AJ		 3359 const int rates[] = { 60, 85, 75, 60, 50 };
3360 const u8 empty[3] = { 0, 0, 0 };
a327f6b8 3361
13931579 3362 for (i = 0; i < 4; i++) {
3f649ab7 3363 int width, height;
948de842 3364
13931579 3365 cvt = &(timing->data.other_data.data.cvt[i]);
f453ba04 3366
13931579 3367 if (!memcmp(cvt->code, empty, 3))
9cf00977 3368 continue;
f453ba04 3369
13931579
AJ		 3370 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
3371 switch (cvt->code[1] & 0x0c) {
d652d5f1
LT		 3372 /* default - because compiler doesn't see that we've enumerated all cases */
3373 default:
13931579
AJ		 3374 case 0x00:
3375 width = height * 4 / 3;
3376 break;
3377 case 0x04:
3378 width = height * 16 / 9;
3379 break;
3380 case 0x08:
3381 width = height * 16 / 10;
3382 break;
3383 case 0x0c:
3384 width = height * 15 / 9;
3385 break;
3386 }
3387
3388 for (j = 1; j < 5; j++) {
3389 if (cvt->code[2] & (1 << j)) {
3390 newmode = drm_cvt_mode(dev, width, height,
3391 rates[j], j == 0,
3392 false, false);
3393 if (newmode) {
3394 drm_mode_probed_add(connector, newmode);
3395 modes++;
3396 }
3397 }
3398 }
f453ba04
DA		 3399 }
3400
3401 return modes;
3402}
9cf00977 3403
13931579 3404static void
4194442d 3405do_cvt_mode(const struct detailed_timing *timing, void *c)
882f0219 3406{
13931579 3407 struct detailed_mode_closure *closure = c;
882f0219 3408
e379814b 3409 if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE))
a7a131ac
VS		 3410 return;
3411
3412 closure->modes += drm_cvt_modes(closure->connector, timing);
13931579 3413}
882f0219 3414
13931579 3415static int
c14e7241 3416add_cvt_modes(struct drm_connector *connector, const struct edid *edid)
4d23f484 3417{
13931579 3418 struct detailed_mode_closure closure = {
d456ea2e
JL		 3419 .connector = connector,
3420 .edid = edid,
13931579 3421 };
882f0219 3422
13931579 3423 if (version_greater(edid, 1, 2))
eed628f1 3424 drm_for_each_detailed_block(edid, do_cvt_mode, &closure);
882f0219 3425
13931579 3426 /* XXX should also look for CVT codes in VTB blocks */
882f0219 3427
13931579
AJ		 3428 return closure.modes;
3429}
3430
fa3a7340
VS		 3431static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
3432
13931579 3433static void
4194442d 3434do_detailed_mode(const struct detailed_timing *timing, void *c)
13931579
AJ		 3435{
3436 struct detailed_mode_closure *closure = c;
3437 struct drm_display_mode *newmode;
3438
a9b1f15f 3439 if (!is_detailed_timing_descriptor(timing))
f447dd1f
VS		 3440 return;
3441
3442 newmode = drm_mode_detailed(closure->connector->dev,
3443 closure->edid, timing,
3444 closure->quirks);
3445 if (!newmode)
3446 return;
13931579 3447
f447dd1f
VS		 3448 if (closure->preferred)
3449 newmode->type |= DRM_MODE_TYPE_PREFERRED;
13931579 3450
f447dd1f
VS		 3451 /*
3452 * Detailed modes are limited to 10kHz pixel clock resolution,
3453 * so fix up anything that looks like CEA/HDMI mode, but the clock
3454 * is just slightly off.
3455 */
3456 fixup_detailed_cea_mode_clock(newmode);
fa3a7340 3457
f447dd1f
VS		 3458 drm_mode_probed_add(closure->connector, newmode);
3459 closure->modes++;
3460 closure->preferred = false;
13931579 3461}
882f0219 3462
13931579
AJ		 3463/*
3464 * add_detailed_modes - Add modes from detailed timings
3465 * @connector: attached connector
3466 * @edid: EDID block to scan
3467 * @quirks: quirks to apply
3468 */
3469static int
c14e7241 3470add_detailed_modes(struct drm_connector *connector, const struct edid *edid,
13931579
AJ		 3471 u32 quirks)
3472{
3473 struct detailed_mode_closure closure = {
d456ea2e
JL		 3474 .connector = connector,
3475 .edid = edid,
c2925bde 3476 .preferred = true,
d456ea2e 3477 .quirks = quirks,
13931579
AJ		 3478 };
3479
3480 if (closure.preferred && !version_greater(edid, 1, 3))
3481 closure.preferred =
3482 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
3483
eed628f1 3484 drm_for_each_detailed_block(edid, do_detailed_mode, &closure);
13931579
AJ		 3485
3486 return closure.modes;
882f0219 3487}
f453ba04 3488
8fe9790d 3489#define AUDIO_BLOCK 0x01
54ac76f8 3490#define VIDEO_BLOCK 0x02
f23c20c8 3491#define VENDOR_BLOCK 0x03
76adaa34 3492#define SPEAKER_BLOCK 0x04
e85959d6 3493#define HDR_STATIC_METADATA_BLOCK 0x6
87563fc0
SS		 3494#define USE_EXTENDED_TAG 0x07
3495#define EXT_VIDEO_CAPABILITY_BLOCK 0x00
832d4f2f
SS		 3496#define EXT_VIDEO_DATA_BLOCK_420 0x0E
3497#define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F
8fe9790d 3498#define EDID_BASIC_AUDIO (1 << 6)
a988bc72
LPC		 3499#define EDID_CEA_YCRCB444 (1 << 5)
3500#define EDID_CEA_YCRCB422 (1 << 4)
b1edd6a6 3501#define EDID_CEA_VCDB_QS (1 << 6)
8fe9790d 3502
d4e4a31d 3503/*
8fe9790d 3504 * Search EDID for CEA extension block.
f23c20c8 3505 */
4cc4f09e
JN		 3506const u8 *drm_find_edid_extension(const struct edid *edid,
3507 int ext_id, int *ext_index)
f23c20c8 3508{
43d16d84 3509 const u8 *edid_ext = NULL;
8fe9790d 3510 int i;
f23c20c8
ML		 3511
3512 /* No EDID or EDID extensions */
f1e4c916 3513 if (!edid || !edid_extension_block_count(edid))
8fe9790d 3514 return NULL;
f23c20c8 3515
f23c20c8 3516 /* Find CEA extension */
f1e4c916
JN		 3517 for (i = *ext_index; i < edid_extension_block_count(edid); i++) {
3518 edid_ext = edid_extension_block_data(edid, i);
4ba0f53c 3519 if (edid_block_tag(edid_ext) == ext_id)
f23c20c8
ML		 3520 break;
3521 }
3522
f1e4c916 3523 if (i >= edid_extension_block_count(edid))
8fe9790d
ZW		 3524 return NULL;
3525
8873cfa3
VS		 3526 *ext_index = i + 1;
3527
8fe9790d
ZW		 3528 return edid_ext;
3529}
3530
43d16d84 3531static const u8 *drm_find_cea_extension(const struct edid *edid)
e28ad544 3532{
43d16d84 3533 const struct displayid_block *block;
1ba63caf 3534 struct displayid_iter iter;
43d16d84 3535 const u8 *cea;
1ba63caf 3536 int ext_index = 0;
e28ad544
AR		 3537
3538 /* Look for a top level CEA extension block */
7f261afd 3539 /* FIXME: make callers iterate through multiple CEA ext blocks? */
8873cfa3 3540 cea = drm_find_edid_extension(edid, CEA_EXT, &ext_index);
e28ad544
AR		 3541 if (cea)
3542 return cea;
3543
3544 /* CEA blocks can also be found embedded in a DisplayID block */
1ba63caf
JN		 3545 displayid_iter_edid_begin(edid, &iter);
3546 displayid_iter_for_each(block, &iter) {
3547 if (block->tag == DATA_BLOCK_CTA) {
3548 cea = (const u8 *)block;
3549 break;
e28ad544
AR		 3550 }
3551 }
1ba63caf 3552 displayid_iter_end(&iter);
e28ad544 3553
1ba63caf 3554 return cea;
e28ad544
AR		 3555}
3556
e1cf35b9 3557static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic)
7befe621 3558{
9212f8ee
VS		 3559 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127);
3560 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219);
3561
8c1b2bd9
VS		 3562 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1))
3563 return &edid_cea_modes_1[vic - 1];
f7655d42
VS		 3564 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193))
3565 return &edid_cea_modes_193[vic - 193];
7befe621
VS		 3566 return NULL;
3567}
3568
3569static u8 cea_num_vics(void)
3570{
f7655d42 3571 return 193 + ARRAY_SIZE(edid_cea_modes_193);
7befe621
VS		 3572}
3573
3574static u8 cea_next_vic(u8 vic)
3575{
8c1b2bd9 3576 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1))
f7655d42
VS		 3577 vic = 193;
3578 return vic;
7befe621
VS		 3579}
3580
e6e79209
VS		 3581/*
3582 * Calculate the alternate clock for the CEA mode
3583 * (60Hz vs. 59.94Hz etc.)
3584 */
3585static unsigned int
3586cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
3587{
3588 unsigned int clock = cea_mode->clock;
3589
0425662f 3590 if (drm_mode_vrefresh(cea_mode) % 6 != 0)
e6e79209
VS		 3591 return clock;
3592
3593 /*
3594 * edid_cea_modes contains the 59.94Hz
3595 * variant for 240 and 480 line modes,
3596 * and the 60Hz variant otherwise.
3597 */
3598 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
9afd808c 3599 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
e6e79209 3600 else
9afd808c 3601 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
e6e79209
VS		 3602
3603 return clock;
3604}
3605
c45a4e46
VS		 3606static bool
3607cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
3608{
3609 /*
3610 * For certain VICs the spec allows the vertical
3611 * front porch to vary by one or two lines.
3612 *
3613 * cea_modes[] stores the variant with the shortest
3614 * vertical front porch. We can adjust the mode to
3615 * get the other variants by simply increasing the
3616 * vertical front porch length.
3617 */
7befe621
VS		 3618 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 ||
3619 cea_mode_for_vic(9)->vtotal != 262 ||
3620 cea_mode_for_vic(12)->vtotal != 262 ||
3621 cea_mode_for_vic(13)->vtotal != 262 ||
3622 cea_mode_for_vic(23)->vtotal != 312 ||
3623 cea_mode_for_vic(24)->vtotal != 312 ||
3624 cea_mode_for_vic(27)->vtotal != 312 ||
3625 cea_mode_for_vic(28)->vtotal != 312);
c45a4e46
VS		 3626
3627 if (((vic == 8 || vic == 9 ||
3628 vic == 12 || vic == 13) && mode->vtotal < 263) ||
3629 ((vic == 23 || vic == 24 ||
3630 vic == 27 || vic == 28) && mode->vtotal < 314)) {
3631 mode->vsync_start++;
3632 mode->vsync_end++;
3633 mode->vtotal++;
3634
3635 return true;
3636 }
3637
3638 return false;
3639}
3640
4c6bcf44
VS		 3641static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
3642 unsigned int clock_tolerance)
3643{
357768cc 3644 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 3645 u8 vic;
4c6bcf44
VS		 3646
3647 if (!to_match->clock)
3648 return 0;
3649
357768cc
VS		 3650 if (to_match->picture_aspect_ratio)
3651 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3652
7befe621 3653 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
563c4a75 3654 struct drm_display_mode cea_mode;
4c6bcf44
VS		 3655 unsigned int clock1, clock2;
3656
563c4a75
VS		 3657 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
3658
4c6bcf44 3659 /* Check both 60Hz and 59.94Hz */
c45a4e46
VS		 3660 clock1 = cea_mode.clock;
3661 clock2 = cea_mode_alternate_clock(&cea_mode);
4c6bcf44
VS		 3662
3663 if (abs(to_match->clock - clock1) > clock_tolerance &&
3664 abs(to_match->clock - clock2) > clock_tolerance)
3665 continue;
3666
c45a4e46 3667 do {
357768cc 3668 if (drm_mode_match(to_match, &cea_mode, match_flags))
c45a4e46
VS		 3669 return vic;
3670 } while (cea_mode_alternate_timings(vic, &cea_mode));
4c6bcf44
VS		 3671 }
3672
3673 return 0;
3674}
3675
18316c8c
TR		 3676/**
3677 * drm_match_cea_mode - look for a CEA mode matching given mode
3678 * @to_match: display mode
3679 *
db6cf833 3680 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
18316c8c 3681 * mode.
a4799037 3682 */
18316c8c 3683u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
a4799037 3684{
357768cc 3685 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 3686 u8 vic;
a4799037 3687
a90b590e
VS		 3688 if (!to_match->clock)
3689 return 0;
3690
357768cc
VS		 3691 if (to_match->picture_aspect_ratio)
3692 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3693
7befe621 3694 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
563c4a75 3695 struct drm_display_mode cea_mode;
a90b590e
VS		 3696 unsigned int clock1, clock2;
3697
563c4a75
VS		 3698 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
3699
a90b590e 3700 /* Check both 60Hz and 59.94Hz */
c45a4e46
VS		 3701 clock1 = cea_mode.clock;
3702 clock2 = cea_mode_alternate_clock(&cea_mode);
a4799037 3703
c45a4e46
VS		 3704 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
3705 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
3706 continue;
3707
3708 do {
357768cc 3709 if (drm_mode_match(to_match, &cea_mode, match_flags))
c45a4e46
VS		 3710 return vic;
3711 } while (cea_mode_alternate_timings(vic, &cea_mode));
a4799037 3712 }
c45a4e46 3713
a4799037
SM		 3714 return 0;
3715}
3716EXPORT_SYMBOL(drm_match_cea_mode);
3717
d9278b4c
JN		 3718static bool drm_valid_cea_vic(u8 vic)
3719{
7befe621 3720 return cea_mode_for_vic(vic) != NULL;
d9278b4c
JN		 3721}
3722
28c03a44 3723static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
0967e6a5 3724{
7befe621
VS		 3725 const struct drm_display_mode *mode = cea_mode_for_vic(video_code);
3726
3727 if (mode)
3728 return mode->picture_aspect_ratio;
3729
3730 return HDMI_PICTURE_ASPECT_NONE;
0967e6a5 3731}
0967e6a5 3732
d2b43473
WL		 3733static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code)
3734{
3735 return edid_4k_modes[video_code].picture_aspect_ratio;
3736}
3737
3f2f6533
LD		 3738/*
3739 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
3740 * specific block).
3f2f6533
LD		 3741 */
3742static unsigned int
3743hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
3744{
3f2f6533
LD		 3745 return cea_mode_alternate_clock(hdmi_mode);
3746}
3747
4c6bcf44
VS		 3748static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
3749 unsigned int clock_tolerance)
3750{
357768cc 3751 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 3752 u8 vic;
4c6bcf44
VS		 3753
3754 if (!to_match->clock)
3755 return 0;
3756
d2b43473
WL		 3757 if (to_match->picture_aspect_ratio)
3758 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3759
d9278b4c
JN		 3760 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3761 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4c6bcf44
VS		 3762 unsigned int clock1, clock2;
3763
3764 /* Make sure to also match alternate clocks */
3765 clock1 = hdmi_mode->clock;
3766 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3767
3768 if (abs(to_match->clock - clock1) > clock_tolerance &&
3769 abs(to_match->clock - clock2) > clock_tolerance)
3770 continue;
3771
357768cc 3772 if (drm_mode_match(to_match, hdmi_mode, match_flags))
d9278b4c 3773 return vic;
4c6bcf44
VS		 3774 }
3775
3776 return 0;
3777}
3778
3f2f6533
LD		 3779/*
3780 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
3781 * @to_match: display mode
3782 *
3783 * An HDMI mode is one defined in the HDMI vendor specific block.
3784 *
3785 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
3786 */
3787static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
3788{
357768cc 3789 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 3790 u8 vic;
3f2f6533
LD		 3791
3792 if (!to_match->clock)
3793 return 0;
3794
d2b43473
WL		 3795 if (to_match->picture_aspect_ratio)
3796 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3797
d9278b4c
JN		 3798 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3799 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3f2f6533
LD		 3800 unsigned int clock1, clock2;
3801
3802 /* Make sure to also match alternate clocks */
3803 clock1 = hdmi_mode->clock;
3804 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3805
3806 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
3807 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
357768cc 3808 drm_mode_match(to_match, hdmi_mode, match_flags))
d9278b4c 3809 return vic;
3f2f6533
LD		 3810 }
3811 return 0;
3812}
3813
d9278b4c
JN		 3814static bool drm_valid_hdmi_vic(u8 vic)
3815{
3816 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
3817}
3818
e6e79209 3819static int
f4e558ec 3820add_alternate_cea_modes(struct drm_connector *connector, const struct edid *edid)
e6e79209
VS		 3821{
3822 struct drm_device *dev = connector->dev;
3823 struct drm_display_mode *mode, *tmp;
3824 LIST_HEAD(list);
3825 int modes = 0;
3826
3827 /* Don't add CEA modes if the CEA extension block is missing */
3828 if (!drm_find_cea_extension(edid))
3829 return 0;
3830
3831 /*
3832 * Go through all probed modes and create a new mode
3833 * with the alternate clock for certain CEA modes.
3834 */
3835 list_for_each_entry(mode, &connector->probed_modes, head) {
3f2f6533 3836 const struct drm_display_mode *cea_mode = NULL;
e6e79209 3837 struct drm_display_mode *newmode;
d9278b4c 3838 u8 vic = drm_match_cea_mode(mode);
e6e79209
VS		 3839 unsigned int clock1, clock2;
3840
d9278b4c 3841 if (drm_valid_cea_vic(vic)) {
7befe621 3842 cea_mode = cea_mode_for_vic(vic);
3f2f6533
LD		 3843 clock2 = cea_mode_alternate_clock(cea_mode);
3844 } else {
d9278b4c
JN		 3845 vic = drm_match_hdmi_mode(mode);
3846 if (drm_valid_hdmi_vic(vic)) {
3847 cea_mode = &edid_4k_modes[vic];
3f2f6533
LD		 3848 clock2 = hdmi_mode_alternate_clock(cea_mode);
3849 }
3850 }
e6e79209 3851
3f2f6533
LD		 3852 if (!cea_mode)
3853 continue;
e6e79209
VS		 3854
3855 clock1 = cea_mode->clock;
e6e79209
VS		 3856
3857 if (clock1 == clock2)
3858 continue;
3859
3860 if (mode->clock != clock1 && mode->clock != clock2)
3861 continue;
3862
3863 newmode = drm_mode_duplicate(dev, cea_mode);
3864 if (!newmode)
3865 continue;
3866
27130212
DL		 3867 /* Carry over the stereo flags */
3868 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
3869
e6e79209
VS		 3870 /*
3871 * The current mode could be either variant. Make
3872 * sure to pick the "other" clock for the new mode.
3873 */
3874 if (mode->clock != clock1)
3875 newmode->clock = clock1;
3876 else
3877 newmode->clock = clock2;
3878
3879 list_add_tail(&newmode->head, &list);
3880 }
3881
3882 list_for_each_entry_safe(mode, tmp, &list, head) {
3883 list_del(&mode->head);
3884 drm_mode_probed_add(connector, mode);
3885 modes++;
3886 }
3887
3888 return modes;
3889}
a4799037 3890
8ec6e075
SS		 3891static u8 svd_to_vic(u8 svd)
3892{
3893 /* 0-6 bit vic, 7th bit native mode indicator */
3894 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
3895 return svd & 127;
3896
3897 return svd;
3898}
3899
aff04ace
TW		 3900static struct drm_display_mode *
3901drm_display_mode_from_vic_index(struct drm_connector *connector,
3902 const u8 *video_db, u8 video_len,
3903 u8 video_index)
54ac76f8
CS		 3904{
3905 struct drm_device *dev = connector->dev;
aff04ace 3906 struct drm_display_mode *newmode;
d9278b4c 3907 u8 vic;
54ac76f8 3908
aff04ace
TW		 3909 if (video_db == NULL || video_index >= video_len)
3910 return NULL;
3911
3912 /* CEA modes are numbered 1..127 */
8ec6e075 3913 vic = svd_to_vic(video_db[video_index]);
d9278b4c 3914 if (!drm_valid_cea_vic(vic))
aff04ace
TW		 3915 return NULL;
3916
7befe621 3917 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
409bbf1e
DL		 3918 if (!newmode)
3919 return NULL;
3920
aff04ace
TW		 3921 return newmode;
3922}
3923
832d4f2f
SS		 3924/*
3925 * do_y420vdb_modes - Parse YCBCR 420 only modes
3926 * @connector: connector corresponding to the HDMI sink
3927 * @svds: start of the data block of CEA YCBCR 420 VDB
3928 * @len: length of the CEA YCBCR 420 VDB
3929 *
3930 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
3931 * which contains modes which can be supported in YCBCR 420
3932 * output format only.
3933 */
3934static int do_y420vdb_modes(struct drm_connector *connector,
3935 const u8 *svds, u8 svds_len)
3936{
3937 int modes = 0, i;
3938 struct drm_device *dev = connector->dev;
3939 struct drm_display_info *info = &connector->display_info;
3940 struct drm_hdmi_info *hdmi = &info->hdmi;
3941
3942 for (i = 0; i < svds_len; i++) {
3943 u8 vic = svd_to_vic(svds[i]);
3944 struct drm_display_mode *newmode;
3945
3946 if (!drm_valid_cea_vic(vic))
3947 continue;
3948
7befe621 3949 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
832d4f2f
SS		 3950 if (!newmode)
3951 break;
3952 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
3953 drm_mode_probed_add(connector, newmode);
3954 modes++;
3955 }
3956
3957 if (modes > 0)
c03d0b52 3958 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
832d4f2f
SS		 3959 return modes;
3960}
3961
3962/*
3963 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap
3964 * @connector: connector corresponding to the HDMI sink
3965 * @vic: CEA vic for the video mode to be added in the map
3966 *
3967 * Makes an entry for a videomode in the YCBCR 420 bitmap
3968 */
3969static void
3970drm_add_cmdb_modes(struct drm_connector *connector, u8 svd)
3971{
3972 u8 vic = svd_to_vic(svd);
3973 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3974
3975 if (!drm_valid_cea_vic(vic))
3976 return;
3977
3978 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
3979}
3980
7af655bc
VS		 3981/**
3982 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC
3983 * @dev: DRM device
8d7d8c0a 3984 * @video_code: CEA VIC of the mode
7af655bc
VS		 3985 *
3986 * Creates a new mode matching the specified CEA VIC.
3987 *
3988 * Returns: A new drm_display_mode on success or NULL on failure
3989 */
3990struct drm_display_mode *
3991drm_display_mode_from_cea_vic(struct drm_device *dev,
3992 u8 video_code)
3993{
3994 const struct drm_display_mode *cea_mode;
3995 struct drm_display_mode *newmode;
3996
3997 cea_mode = cea_mode_for_vic(video_code);
3998 if (!cea_mode)
3999 return NULL;
4000
4001 newmode = drm_mode_duplicate(dev, cea_mode);
4002 if (!newmode)
4003 return NULL;
4004
4005 return newmode;
4006}
4007EXPORT_SYMBOL(drm_display_mode_from_cea_vic);
4008
aff04ace
TW		 4009static int
4010do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
4011{
4012 int i, modes = 0;
832d4f2f 4013 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
aff04ace
TW		 4014
4015 for (i = 0; i < len; i++) {
4016 struct drm_display_mode *mode;
948de842 4017
aff04ace
TW		 4018 mode = drm_display_mode_from_vic_index(connector, db, len, i);
4019 if (mode) {
832d4f2f
SS		 4020 /*
4021 * YCBCR420 capability block contains a bitmap which
4022 * gives the index of CEA modes from CEA VDB, which
4023 * can support YCBCR 420 sampling output also (apart
4024 * from RGB/YCBCR444 etc).
4025 * For example, if the bit 0 in bitmap is set,
4026 * first mode in VDB can support YCBCR420 output too.
4027 * Add YCBCR420 modes only if sink is HDMI 2.0 capable.
4028 */
4029 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i))
4030 drm_add_cmdb_modes(connector, db[i]);
4031
aff04ace
TW		 4032 drm_mode_probed_add(connector, mode);
4033 modes++;
54ac76f8
CS		 4034 }
4035 }
4036
4037 return modes;
4038}
4039
c858cfca
DL		 4040struct stereo_mandatory_mode {
4041 int width, height, vrefresh;
4042 unsigned int flags;
4043};
4044
4045static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
f7e121b7
DL		 4046 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4047 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
c858cfca
DL		 4048 { 1920, 1080, 50,
4049 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
4050 { 1920, 1080, 60,
4051 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
f7e121b7
DL		 4052 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4053 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
4054 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4055 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
c858cfca
DL		 4056};
4057
4058static bool
4059stereo_match_mandatory(const struct drm_display_mode *mode,
4060 const struct stereo_mandatory_mode *stereo_mode)
4061{
4062 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
4063
4064 return mode->hdisplay == stereo_mode->width &&
4065 mode->vdisplay == stereo_mode->height &&
4066 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
4067 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
4068}
4069
c858cfca
DL		 4070static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
4071{
4072 struct drm_device *dev = connector->dev;
4073 const struct drm_display_mode *mode;
4074 struct list_head stereo_modes;
f7e121b7 4075 int modes = 0, i;
c858cfca
DL		 4076
4077 INIT_LIST_HEAD(&stereo_modes);
4078
4079 list_for_each_entry(mode, &connector->probed_modes, head) {
f7e121b7
DL		 4080 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
4081 const struct stereo_mandatory_mode *mandatory;
c858cfca
DL		 4082 struct drm_display_mode *new_mode;
4083
f7e121b7
DL		 4084 if (!stereo_match_mandatory(mode,
4085 &stereo_mandatory_modes[i]))
4086 continue;
c858cfca 4087
f7e121b7 4088 mandatory = &stereo_mandatory_modes[i];
c858cfca
DL		 4089 new_mode = drm_mode_duplicate(dev, mode);
4090 if (!new_mode)
4091 continue;
4092
f7e121b7 4093 new_mode->flags |= mandatory->flags;
c858cfca
DL		 4094 list_add_tail(&new_mode->head, &stereo_modes);
4095 modes++;
f7e121b7 4096 }
c858cfca
DL		 4097 }
4098
4099 list_splice_tail(&stereo_modes, &connector->probed_modes);
4100
4101 return modes;
4102}
4103
1deee8d7
DL		 4104static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
4105{
4106 struct drm_device *dev = connector->dev;
4107 struct drm_display_mode *newmode;
4108
d9278b4c 4109 if (!drm_valid_hdmi_vic(vic)) {
1deee8d7
DL		 4110 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
4111 return 0;
4112 }
4113
4114 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
4115 if (!newmode)
4116 return 0;
4117
4118 drm_mode_probed_add(connector, newmode);
4119
4120 return 1;
4121}
4122
fbf46025
TW		 4123static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
4124 const u8 *video_db, u8 video_len, u8 video_index)
4125{
fbf46025
TW		 4126 struct drm_display_mode *newmode;
4127 int modes = 0;
fbf46025
TW		 4128
4129 if (structure & (1 << 0)) {
aff04ace
TW		 4130 newmode = drm_display_mode_from_vic_index(connector, video_db,
4131 video_len,
4132 video_index);
fbf46025
TW		 4133 if (newmode) {
4134 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
4135 drm_mode_probed_add(connector, newmode);
4136 modes++;
4137 }
4138 }
4139 if (structure & (1 << 6)) {
aff04ace
TW		 4140 newmode = drm_display_mode_from_vic_index(connector, video_db,
4141 video_len,
4142 video_index);
fbf46025
TW		 4143 if (newmode) {
4144 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4145 drm_mode_probed_add(connector, newmode);
4146 modes++;
4147 }
4148 }
4149 if (structure & (1 << 8)) {
aff04ace
TW		 4150 newmode = drm_display_mode_from_vic_index(connector, video_db,
4151 video_len,
4152 video_index);
fbf46025 4153 if (newmode) {
89570eeb 4154 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
fbf46025
TW		 4155 drm_mode_probed_add(connector, newmode);
4156 modes++;
4157 }
4158 }
4159
4160 return modes;
4161}
4162
7ebe1963
LD		 4163/*
4164 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
4165 * @connector: connector corresponding to the HDMI sink
4166 * @db: start of the CEA vendor specific block
4167 * @len: length of the CEA block payload, ie. one can access up to db[len]
4168 *
c858cfca
DL		 4169 * Parses the HDMI VSDB looking for modes to add to @connector. This function
4170 * also adds the stereo 3d modes when applicable.
7ebe1963
LD		 4171 */
4172static int
fbf46025
TW		 4173do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
4174 const u8 *video_db, u8 video_len)
7ebe1963 4175{
f1781e9b 4176 struct drm_display_info *info = &connector->display_info;
0e5083aa 4177 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
fbf46025
TW		 4178 u8 vic_len, hdmi_3d_len = 0;
4179 u16 mask;
4180 u16 structure_all;
7ebe1963
LD		 4181
4182 if (len < 8)
4183 goto out;
4184
4185 /* no HDMI_Video_Present */
4186 if (!(db[8] & (1 << 5)))
4187 goto out;
4188
4189 /* Latency_Fields_Present */
4190 if (db[8] & (1 << 7))
4191 offset += 2;
4192
4193 /* I_Latency_Fields_Present */
4194 if (db[8] & (1 << 6))
4195 offset += 2;
4196
4197 /* the declared length is not long enough for the 2 first bytes
4198 * of additional video format capabilities */
c858cfca 4199 if (len < (8 + offset + 2))
7ebe1963
LD		 4200 goto out;
4201
c858cfca
DL		 4202 /* 3D_Present */
4203 offset++;
fbf46025 4204 if (db[8 + offset] & (1 << 7)) {
c858cfca
DL		 4205 modes += add_hdmi_mandatory_stereo_modes(connector);
4206
fbf46025
TW		 4207 /* 3D_Multi_present */
4208 multi_present = (db[8 + offset] & 0x60) >> 5;
4209 }
4210
c858cfca 4211 offset++;
7ebe1963 4212 vic_len = db[8 + offset] >> 5;
fbf46025 4213 hdmi_3d_len = db[8 + offset] & 0x1f;
7ebe1963
LD		 4214
4215 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
7ebe1963
LD		 4216 u8 vic;
4217
4218 vic = db[9 + offset + i];
1deee8d7 4219 modes += add_hdmi_mode(connector, vic);
7ebe1963 4220 }
fbf46025
TW		 4221 offset += 1 + vic_len;
4222
0e5083aa
TW		 4223 if (multi_present == 1)
4224 multi_len = 2;
4225 else if (multi_present == 2)
4226 multi_len = 4;
4227 else
4228 multi_len = 0;
fbf46025 4229
0e5083aa 4230 if (len < (8 + offset + hdmi_3d_len - 1))
fbf46025
TW		 4231 goto out;
4232
0e5083aa 4233 if (hdmi_3d_len < multi_len)
fbf46025
TW		 4234 goto out;
4235
0e5083aa
TW		 4236 if (multi_present == 1 || multi_present == 2) {
4237 /* 3D_Structure_ALL */
4238 structure_all = (db[8 + offset] << 8) | db[9 + offset];
fbf46025 4239
0e5083aa
TW		 4240 /* check if 3D_MASK is present */
4241 if (multi_present == 2)
4242 mask = (db[10 + offset] << 8) | db[11 + offset];
4243 else
4244 mask = 0xffff;
4245
4246 for (i = 0; i < 16; i++) {
4247 if (mask & (1 << i))
4248 modes += add_3d_struct_modes(connector,
4249 structure_all,
4250 video_db,
4251 video_len, i);
4252 }
4253 }
4254
4255 offset += multi_len;
4256
4257 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
4258 int vic_index;
4259 struct drm_display_mode *newmode = NULL;
4260 unsigned int newflag = 0;
4261 bool detail_present;
4262
4263 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
4264
4265 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
4266 break;
4267
4268 /* 2D_VIC_order_X */
4269 vic_index = db[8 + offset + i] >> 4;
4270
4271 /* 3D_Structure_X */
4272 switch (db[8 + offset + i] & 0x0f) {
4273 case 0:
4274 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
4275 break;
4276 case 6:
4277 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4278 break;
4279 case 8:
4280 /* 3D_Detail_X */
4281 if ((db[9 + offset + i] >> 4) == 1)
4282 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4283 break;
4284 }
4285
4286 if (newflag != 0) {
4287 newmode = drm_display_mode_from_vic_index(connector,
4288 video_db,
4289 video_len,
4290 vic_index);
4291
4292 if (newmode) {
4293 newmode->flags |= newflag;
4294 drm_mode_probed_add(connector, newmode);
4295 modes++;
4296 }
4297 }
4298
4299 if (detail_present)
4300 i++;
fbf46025 4301 }
7ebe1963
LD		 4302
4303out:
f1781e9b
VS		 4304 if (modes > 0)
4305 info->has_hdmi_infoframe = true;
7ebe1963
LD		 4306 return modes;
4307}
4308
9e50b9d5
VS		 4309static int
4310cea_db_payload_len(const u8 *db)
4311{
4312 return db[0] & 0x1f;
4313}
4314
87563fc0
SS		 4315static int
4316cea_db_extended_tag(const u8 *db)
4317{
4318 return db[1];
4319}
4320
9e50b9d5
VS		 4321static int
4322cea_db_tag(const u8 *db)
4323{
4324 return db[0] >> 5;
4325}
4326
4327static int
4328cea_revision(const u8 *cea)
4329{
5036c0d0
VS		 4330 /*
4331 * FIXME is this correct for the DispID variant?
4332 * The DispID spec doesn't really specify whether
4333 * this is the revision of the CEA extension or
4334 * the DispID CEA data block. And the only value
4335 * given as an example is 0.
4336 */
9e50b9d5
VS		 4337 return cea[1];
4338}
4339
4340static int
4341cea_db_offsets(const u8 *cea, int *start, int *end)
4342{
e28ad544
AR		 4343 /* DisplayID CTA extension blocks and top-level CEA EDID
4344 * block header definitions differ in the following bytes:
4345 * 1) Byte 2 of the header specifies length differently,
4346 * 2) Byte 3 is only present in the CEA top level block.
4347 *
4348 * The different definitions for byte 2 follow.
4349 *
4350 * DisplayID CTA extension block defines byte 2 as:
4351 * Number of payload bytes
4352 *
4353 * CEA EDID block defines byte 2 as:
4354 * Byte number (decimal) within this block where the 18-byte
4355 * DTDs begin. If no non-DTD data is present in this extension
4356 * block, the value should be set to 04h (the byte after next).
4357 * If set to 00h, there are no DTDs present in this block and
4358 * no non-DTD data.
4359 */
4360 if (cea[0] == DATA_BLOCK_CTA) {
6e8a942b
VS		 4361 /*
4362 * for_each_displayid_db() has already verified
4363 * that these stay within expected bounds.
4364 */
e28ad544
AR		 4365 *start = 3;
4366 *end = *start + cea[2];
4367 } else if (cea[0] == CEA_EXT) {
4368 /* Data block offset in CEA extension block */
4369 *start = 4;
4370 *end = cea[2];
4371 if (*end == 0)
4372 *end = 127;
4373 if (*end < 4 || *end > 127)
4374 return -ERANGE;
4375 } else {
c7581a41 4376 return -EOPNOTSUPP;
e28ad544
AR		 4377 }
4378
9e50b9d5
VS		 4379 return 0;
4380}
4381
7ebe1963
LD		 4382static bool cea_db_is_hdmi_vsdb(const u8 *db)
4383{
7ebe1963
LD		 4384 if (cea_db_tag(db) != VENDOR_BLOCK)
4385 return false;
4386
4387 if (cea_db_payload_len(db) < 5)
4388 return false;
4389
37eab1fe 4390 return oui(db[3], db[2], db[1]) == HDMI_IEEE_OUI;
7ebe1963
LD		 4391}
4392
50dd1bd1
TR		 4393static bool cea_db_is_hdmi_forum_vsdb(const u8 *db)
4394{
50dd1bd1
TR		 4395 if (cea_db_tag(db) != VENDOR_BLOCK)
4396 return false;
4397
4398 if (cea_db_payload_len(db) < 7)
4399 return false;
4400
37eab1fe 4401 return oui(db[3], db[2], db[1]) == HDMI_FORUM_IEEE_OUI;
50dd1bd1
TR		 4402}
4403
2869f599
PZ		 4404static bool cea_db_is_microsoft_vsdb(const u8 *db)
4405{
4406 if (cea_db_tag(db) != VENDOR_BLOCK)
4407 return false;
4408
4409 if (cea_db_payload_len(db) != 21)
4410 return false;
4411
4412 return oui(db[3], db[2], db[1]) == MICROSOFT_IEEE_OUI;
4413}
4414
1581b2df
VS		 4415static bool cea_db_is_vcdb(const u8 *db)
4416{
4417 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4418 return false;
4419
4420 if (cea_db_payload_len(db) != 2)
4421 return false;
4422
4423 if (cea_db_extended_tag(db) != EXT_VIDEO_CAPABILITY_BLOCK)
4424 return false;
4425
4426 return true;
4427}
4428
832d4f2f
SS		 4429static bool cea_db_is_y420cmdb(const u8 *db)
4430{
4431 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4432 return false;
4433
4434 if (!cea_db_payload_len(db))
4435 return false;
4436
4437 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB)
4438 return false;
4439
4440 return true;
4441}
4442
4443static bool cea_db_is_y420vdb(const u8 *db)
4444{
4445 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4446 return false;
4447
4448 if (!cea_db_payload_len(db))
4449 return false;
4450
4451 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420)
4452 return false;
4453
4454 return true;
4455}
4456
9e50b9d5
VS		 4457#define for_each_cea_db(cea, i, start, end) \
4458 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
4459
832d4f2f
SS		 4460static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector,
4461 const u8 *db)
4462{
4463 struct drm_display_info *info = &connector->display_info;
4464 struct drm_hdmi_info *hdmi = &info->hdmi;
4465 u8 map_len = cea_db_payload_len(db) - 1;
4466 u8 count;
4467 u64 map = 0;
4468
4469 if (map_len == 0) {
4470 /* All CEA modes support ycbcr420 sampling also.*/
4471 hdmi->y420_cmdb_map = U64_MAX;
c03d0b52 4472 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
832d4f2f
SS		 4473 return;
4474 }
4475
4476 /*
4477 * This map indicates which of the existing CEA block modes
4478 * from VDB can support YCBCR420 output too. So if bit=0 is
4479 * set, first mode from VDB can support YCBCR420 output too.
4480 * We will parse and keep this map, before parsing VDB itself
4481 * to avoid going through the same block again and again.
4482 *
4483 * Spec is not clear about max possible size of this block.
4484 * Clamping max bitmap block size at 8 bytes. Every byte can
4485 * address 8 CEA modes, in this way this map can address
4486 * 8*8 = first 64 SVDs.
4487 */
4488 if (WARN_ON_ONCE(map_len > 8))
4489 map_len = 8;
4490
4491 for (count = 0; count < map_len; count++)
4492 map |= (u64)db[2 + count] << (8 * count);
4493
4494 if (map)
c03d0b52 4495 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
832d4f2f
SS		 4496
4497 hdmi->y420_cmdb_map = map;
4498}
4499
54ac76f8 4500static int
f4e558ec 4501add_cea_modes(struct drm_connector *connector, const struct edid *edid)
54ac76f8 4502{
13ac3f55 4503 const u8 *cea = drm_find_cea_extension(edid);
fbf46025
TW		 4504 const u8 *db, *hdmi = NULL, *video = NULL;
4505 u8 dbl, hdmi_len, video_len = 0;
54ac76f8
CS		 4506 int modes = 0;
4507
9e50b9d5
VS		 4508 if (cea && cea_revision(cea) >= 3) {
4509 int i, start, end;
4510
4511 if (cea_db_offsets(cea, &start, &end))
4512 return 0;
4513
4514 for_each_cea_db(cea, i, start, end) {
4515 db = &cea[i];
4516 dbl = cea_db_payload_len(db);
4517
fbf46025
TW		 4518 if (cea_db_tag(db) == VIDEO_BLOCK) {
4519 video = db + 1;
4520 video_len = dbl;
4521 modes += do_cea_modes(connector, video, dbl);
832d4f2f 4522 } else if (cea_db_is_hdmi_vsdb(db)) {
c858cfca
DL		 4523 hdmi = db;
4524 hdmi_len = dbl;
832d4f2f
SS		 4525 } else if (cea_db_is_y420vdb(db)) {
4526 const u8 *vdb420 = &db[2];
4527
4528 /* Add 4:2:0(only) modes present in EDID */
4529 modes += do_y420vdb_modes(connector,
4530 vdb420,
4531 dbl - 1);
c858cfca 4532 }
54ac76f8
CS		 4533 }
4534 }
4535
c858cfca
DL		 4536 /*
4537 * We parse the HDMI VSDB after having added the cea modes as we will
4538 * be patching their flags when the sink supports stereo 3D.
4539 */
4540 if (hdmi)
fbf46025
TW		 4541 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
4542 video_len);
c858cfca 4543
54ac76f8
CS		 4544 return modes;
4545}
4546
fa3a7340
VS		 4547static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
4548{
4549 const struct drm_display_mode *cea_mode;
4550 int clock1, clock2, clock;
d9278b4c 4551 u8 vic;
fa3a7340
VS		 4552 const char *type;
4553
4c6bcf44
VS		 4554 /*
4555 * allow 5kHz clock difference either way to account for
4556 * the 10kHz clock resolution limit of detailed timings.
4557 */
d9278b4c
JN		 4558 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
4559 if (drm_valid_cea_vic(vic)) {
fa3a7340 4560 type = "CEA";
7befe621 4561 cea_mode = cea_mode_for_vic(vic);
fa3a7340
VS		 4562 clock1 = cea_mode->clock;
4563 clock2 = cea_mode_alternate_clock(cea_mode);
4564 } else {
d9278b4c
JN		 4565 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
4566 if (drm_valid_hdmi_vic(vic)) {
fa3a7340 4567 type = "HDMI";
d9278b4c 4568 cea_mode = &edid_4k_modes[vic];
fa3a7340
VS		 4569 clock1 = cea_mode->clock;
4570 clock2 = hdmi_mode_alternate_clock(cea_mode);
4571 } else {
4572 return;
4573 }
4574 }
4575
4576 /* pick whichever is closest */
4577 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
4578 clock = clock1;
4579 else
4580 clock = clock2;
4581
4582 if (mode->clock == clock)
4583 return;
4584
4585 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
d9278b4c 4586 type, vic, mode->clock, clock);
fa3a7340
VS		 4587 mode->clock = clock;
4588}
4589
e85959d6
US		 4590static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db)
4591{
4592 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4593 return false;
4594
4595 if (db[1] != HDR_STATIC_METADATA_BLOCK)
4596 return false;
4597
4598 if (cea_db_payload_len(db) < 3)
4599 return false;
4600
4601 return true;
4602}
4603
4604static uint8_t eotf_supported(const u8 *edid_ext)
4605{
4606 return edid_ext[2] &
4607 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
4608 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
b5e3eed1
VS		 4609 BIT(HDMI_EOTF_SMPTE_ST2084) |
4610 BIT(HDMI_EOTF_BT_2100_HLG));
e85959d6
US		 4611}
4612
4613static uint8_t hdr_metadata_type(const u8 *edid_ext)
4614{
4615 return edid_ext[3] &
4616 BIT(HDMI_STATIC_METADATA_TYPE1);
4617}
4618
4619static void
4620drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
4621{
4622 u16 len;
4623
4624 len = cea_db_payload_len(db);
4625
4626 connector->hdr_sink_metadata.hdmi_type1.eotf =
4627 eotf_supported(db);
4628 connector->hdr_sink_metadata.hdmi_type1.metadata_type =
4629 hdr_metadata_type(db);
4630
4631 if (len >= 4)
4632 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4];
4633 if (len >= 5)
4634 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5];
4635 if (len >= 6)
4636 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6];
4637}
4638
76adaa34 4639static void
23ebf8b9 4640drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
76adaa34 4641{
8504072a 4642 u8 len = cea_db_payload_len(db);
76adaa34 4643
f7da7785
JN		 4644 if (len >= 6 && (db[6] & (1 << 7)))
4645 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
8504072a
VS		 4646 if (len >= 8) {
4647 connector->latency_present[0] = db[8] >> 7;
4648 connector->latency_present[1] = (db[8] >> 6) & 1;
4649 }
4650 if (len >= 9)
4651 connector->video_latency[0] = db[9];
4652 if (len >= 10)
4653 connector->audio_latency[0] = db[10];
4654 if (len >= 11)
4655 connector->video_latency[1] = db[11];
4656 if (len >= 12)
4657 connector->audio_latency[1] = db[12];
76adaa34 4658
23ebf8b9
VS		 4659 DRM_DEBUG_KMS("HDMI: latency present %d %d, "
4660 "video latency %d %d, "
4661 "audio latency %d %d\n",
4662 connector->latency_present[0],
4663 connector->latency_present[1],
4664 connector->video_latency[0],
4665 connector->video_latency[1],
4666 connector->audio_latency[0],
4667 connector->audio_latency[1]);
76adaa34
WF		 4668}
4669
4670static void
4194442d 4671monitor_name(const struct detailed_timing *timing, void *data)
76adaa34 4672{
4194442d
JN		 4673 const char **res = data;
4674
4675 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME))
a7a131ac
VS		 4676 return;
4677
4194442d 4678 *res = timing->data.other_data.data.str.str;
14f77fdd
VS		 4679}
4680
c14e7241 4681static int get_monitor_name(const struct edid *edid, char name[13])
59f7c0fa 4682{
4194442d 4683 const char *edid_name = NULL;
59f7c0fa
JB		 4684 int mnl;
4685
4686 if (!edid || !name)
4687 return 0;
4688
eed628f1 4689 drm_for_each_detailed_block(edid, monitor_name, &edid_name);
59f7c0fa
JB		 4690 for (mnl = 0; edid_name && mnl < 13; mnl++) {
4691 if (edid_name[mnl] == 0x0a)
4692 break;
4693
4694 name[mnl] = edid_name[mnl];
4695 }
4696
4697 return mnl;
4698}
4699
4700/**
4701 * drm_edid_get_monitor_name - fetch the monitor name from the edid
4702 * @edid: monitor EDID information
4703 * @name: pointer to a character array to hold the name of the monitor
4704 * @bufsize: The size of the name buffer (should be at least 14 chars.)
4705 *
4706 */
f4e558ec 4707void drm_edid_get_monitor_name(const struct edid *edid, char *name, int bufsize)
59f7c0fa
JB		 4708{
4709 int name_length;
4710 char buf[13];
4d23f484 4711
59f7c0fa
JB		 4712 if (bufsize <= 0)
4713 return;
4714
4715 name_length = min(get_monitor_name(edid, buf), bufsize - 1);
4716 memcpy(name, buf, name_length);
4717 name[name_length] = '\0';
4718}
4719EXPORT_SYMBOL(drm_edid_get_monitor_name);
4720
42750d39
JN		 4721static void clear_eld(struct drm_connector *connector)
4722{
4723 memset(connector->eld, 0, sizeof(connector->eld));
4724
4725 connector->latency_present[0] = false;
4726 connector->latency_present[1] = false;
4727 connector->video_latency[0] = 0;
4728 connector->audio_latency[0] = 0;
4729 connector->video_latency[1] = 0;
4730 connector->audio_latency[1] = 0;
4731}
4732
79436a1c 4733/*
76adaa34
WF		 4734 * drm_edid_to_eld - build ELD from EDID
4735 * @connector: connector corresponding to the HDMI/DP sink
4736 * @edid: EDID to parse
4737 *
db6cf833 4738 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
1d1c3665 4739 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
76adaa34 4740 */
f4e558ec
JN		 4741static void drm_edid_to_eld(struct drm_connector *connector,
4742 const struct edid *edid)
76adaa34
WF		 4743{
4744 uint8_t *eld = connector->eld;
43d16d84
JN		 4745 const u8 *cea;
4746 const u8 *db;
7c018782 4747 int total_sad_count = 0;
76adaa34
WF		 4748 int mnl;
4749 int dbl;
4750
42750d39 4751 clear_eld(connector);
85c91580 4752
e9bd0b84
JN		 4753 if (!edid)
4754 return;
4755
76adaa34
WF		 4756 cea = drm_find_cea_extension(edid);
4757 if (!cea) {
4758 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
4759 return;
4760 }
4761
f7da7785
JN		 4762 mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
4763 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]);
59f7c0fa 4764
f7da7785
JN		 4765 eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT;
4766 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
76adaa34 4767
f7da7785 4768 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
76adaa34 4769
f7da7785
JN		 4770 eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0];
4771 eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1];
4772 eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0];
4773 eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1];
76adaa34 4774
9e50b9d5
VS		 4775 if (cea_revision(cea) >= 3) {
4776 int i, start, end;
deec222e 4777 int sad_count;
9e50b9d5
VS		 4778
4779 if (cea_db_offsets(cea, &start, &end)) {
4780 start = 0;
4781 end = 0;
4782 }
4783
4784 for_each_cea_db(cea, i, start, end) {
4785 db = &cea[i];
4786 dbl = cea_db_payload_len(db);
4787
4788 switch (cea_db_tag(db)) {
a0ab734d
CS		 4789 case AUDIO_BLOCK:
4790 /* Audio Data Block, contains SADs */
7c018782
VS		 4791 sad_count = min(dbl / 3, 15 - total_sad_count);
4792 if (sad_count >= 1)
f7da7785 4793 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
7c018782
VS		 4794 &db[1], sad_count * 3);
4795 total_sad_count += sad_count;
a0ab734d
CS		 4796 break;
4797 case SPEAKER_BLOCK:
9e50b9d5
VS		 4798 /* Speaker Allocation Data Block */
4799 if (dbl >= 1)
f7da7785 4800 eld[DRM_ELD_SPEAKER] = db[1];
a0ab734d
CS		 4801 break;
4802 case VENDOR_BLOCK:
4803 /* HDMI Vendor-Specific Data Block */
14f77fdd 4804 if (cea_db_is_hdmi_vsdb(db))
23ebf8b9 4805 drm_parse_hdmi_vsdb_audio(connector, db);
a0ab734d
CS		 4806 break;
4807 default:
4808 break;
4809 }
76adaa34 4810 }
9e50b9d5 4811 }
f7da7785 4812 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
76adaa34 4813
1d1c3665
JN		 4814 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
4815 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4816 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
4817 else
4818 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
76adaa34 4819
938fd8aa
JN		 4820 eld[DRM_ELD_BASELINE_ELD_LEN] =
4821 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
4822
4823 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
7c018782 4824 drm_eld_size(eld), total_sad_count);
76adaa34 4825}
76adaa34 4826
fe214163
RM		 4827/**
4828 * drm_edid_to_sad - extracts SADs from EDID
4829 * @edid: EDID to parse
4830 * @sads: pointer that will be set to the extracted SADs
4831 *
4832 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
fe214163 4833 *
db6cf833
TR		 4834 * Note: The returned pointer needs to be freed using kfree().
4835 *
4836 * Return: The number of found SADs or negative number on error.
fe214163 4837 */
f4e558ec 4838int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads)
fe214163
RM		 4839{
4840 int count = 0;
4841 int i, start, end, dbl;
43d16d84 4842 const u8 *cea;
fe214163
RM		 4843
4844 cea = drm_find_cea_extension(edid);
4845 if (!cea) {
4846 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
42908007 4847 return 0;
fe214163
RM		 4848 }
4849
4850 if (cea_revision(cea) < 3) {
4851 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
42908007 4852 return 0;
fe214163
RM		 4853 }
4854
4855 if (cea_db_offsets(cea, &start, &end)) {
4856 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4857 return -EPROTO;
4858 }
4859
4860 for_each_cea_db(cea, i, start, end) {
43d16d84 4861 const u8 *db = &cea[i];
fe214163
RM		 4862
4863 if (cea_db_tag(db) == AUDIO_BLOCK) {
4864 int j;
948de842 4865
fe214163
RM		 4866 dbl = cea_db_payload_len(db);
4867
4868 count = dbl / 3; /* SAD is 3B */
4869 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
4870 if (!*sads)
4871 return -ENOMEM;
4872 for (j = 0; j < count; j++) {
43d16d84 4873 const u8 *sad = &db[1 + j * 3];
fe214163
RM		 4874
4875 (*sads)[j].format = (sad[0] & 0x78) >> 3;
4876 (*sads)[j].channels = sad[0] & 0x7;
4877 (*sads)[j].freq = sad[1] & 0x7F;
4878 (*sads)[j].byte2 = sad[2];
4879 }
4880 break;
4881 }
4882 }
4883
4884 return count;
4885}
4886EXPORT_SYMBOL(drm_edid_to_sad);
4887
d105f476
AD		 4888/**
4889 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
4890 * @edid: EDID to parse
4891 * @sadb: pointer to the speaker block
4892 *
4893 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
d105f476 4894 *
db6cf833
TR		 4895 * Note: The returned pointer needs to be freed using kfree().
4896 *
4897 * Return: The number of found Speaker Allocation Blocks or negative number on
4898 * error.
d105f476 4899 */
f4e558ec 4900int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb)
d105f476
AD		 4901{
4902 int count = 0;
4903 int i, start, end, dbl;
4904 const u8 *cea;
4905
4906 cea = drm_find_cea_extension(edid);
4907 if (!cea) {
4908 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
42908007 4909 return 0;
d105f476
AD		 4910 }
4911
4912 if (cea_revision(cea) < 3) {
4913 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
42908007 4914 return 0;
d105f476
AD		 4915 }
4916
4917 if (cea_db_offsets(cea, &start, &end)) {
4918 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4919 return -EPROTO;
4920 }
4921
4922 for_each_cea_db(cea, i, start, end) {
4923 const u8 *db = &cea[i];
4924
4925 if (cea_db_tag(db) == SPEAKER_BLOCK) {
4926 dbl = cea_db_payload_len(db);
4927
4928 /* Speaker Allocation Data Block */
4929 if (dbl == 3) {
89086bca 4930 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
618e3776
AD		 4931 if (!*sadb)
4932 return -ENOMEM;
d105f476
AD		 4933 count = dbl;
4934 break;
4935 }
4936 }
4937 }
4938
4939 return count;
4940}
4941EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
4942
76adaa34 4943/**
db6cf833 4944 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
76adaa34
WF		 4945 * @connector: connector associated with the HDMI/DP sink
4946 * @mode: the display mode
db6cf833
TR		 4947 *
4948 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
4949 * the sink doesn't support audio or video.
76adaa34
WF		 4950 */
4951int drm_av_sync_delay(struct drm_connector *connector,
3a818d35 4952 const struct drm_display_mode *mode)
76adaa34
WF		 4953{
4954 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
4955 int a, v;
4956
4957 if (!connector->latency_present[0])
4958 return 0;
4959 if (!connector->latency_present[1])
4960 i = 0;
4961
4962 a = connector->audio_latency[i];
4963 v = connector->video_latency[i];
4964
4965 /*
4966 * HDMI/DP sink doesn't support audio or video?
4967 */
4968 if (a == 255 || v == 255)
4969 return 0;
4970
4971 /*
4972 * Convert raw EDID values to millisecond.
4973 * Treat unknown latency as 0ms.
4974 */
4975 if (a)
4976 a = min(2 * (a - 1), 500);
4977 if (v)
4978 v = min(2 * (v - 1), 500);
4979
4980 return max(v - a, 0);
4981}
4982EXPORT_SYMBOL(drm_av_sync_delay);
4983
8fe9790d 4984/**
db6cf833 4985 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
8fe9790d
ZW		 4986 * @edid: monitor EDID information
4987 *
4988 * Parse the CEA extension according to CEA-861-B.
db6cf833 4989 *
a92d083d
LP		 4990 * Drivers that have added the modes parsed from EDID to drm_display_info
4991 * should use &drm_display_info.is_hdmi instead of calling this function.
4992 *
db6cf833 4993 * Return: True if the monitor is HDMI, false if not or unknown.
8fe9790d 4994 */
f4e558ec 4995bool drm_detect_hdmi_monitor(const struct edid *edid)
8fe9790d 4996{
43d16d84 4997 const u8 *edid_ext;
14f77fdd 4998 int i;
8fe9790d 4999 int start_offset, end_offset;
8fe9790d
ZW		 5000
5001 edid_ext = drm_find_cea_extension(edid);
5002 if (!edid_ext)
14f77fdd 5003 return false;
f23c20c8 5004
9e50b9d5 5005 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
14f77fdd 5006 return false;
f23c20c8
ML		 5007
5008 /*
5009 * Because HDMI identifier is in Vendor Specific Block,
5010 * search it from all data blocks of CEA extension.
5011 */
9e50b9d5 5012 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
14f77fdd
VS		 5013 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
5014 return true;
f23c20c8
ML		 5015 }
5016
14f77fdd 5017 return false;
f23c20c8
ML		 5018}
5019EXPORT_SYMBOL(drm_detect_hdmi_monitor);
5020
8fe9790d
ZW		 5021/**
5022 * drm_detect_monitor_audio - check monitor audio capability
fc66811c 5023 * @edid: EDID block to scan
8fe9790d
ZW		 5024 *
5025 * Monitor should have CEA extension block.
5026 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
5027 * audio' only. If there is any audio extension block and supported
5028 * audio format, assume at least 'basic audio' support, even if 'basic
5029 * audio' is not defined in EDID.
5030 *
db6cf833 5031 * Return: True if the monitor supports audio, false otherwise.
8fe9790d 5032 */
f4e558ec 5033bool drm_detect_monitor_audio(const struct edid *edid)
8fe9790d 5034{
43d16d84 5035 const u8 *edid_ext;
8fe9790d
ZW		 5036 int i, j;
5037 bool has_audio = false;
5038 int start_offset, end_offset;
5039
5040 edid_ext = drm_find_cea_extension(edid);
5041 if (!edid_ext)
5042 goto end;
5043
5662abf6
CC		 5044 has_audio = (edid_ext[0] == CEA_EXT &&
5045 (edid_ext[3] & EDID_BASIC_AUDIO) != 0);
8fe9790d
ZW		 5046
5047 if (has_audio) {
5048 DRM_DEBUG_KMS("Monitor has basic audio support\n");
5049 goto end;
5050 }
5051
9e50b9d5
VS		 5052 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
5053 goto end;
8fe9790d 5054
9e50b9d5
VS		 5055 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
5056 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
8fe9790d 5057 has_audio = true;
9e50b9d5 5058 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
8fe9790d
ZW		 5059 DRM_DEBUG_KMS("CEA audio format %d\n",
5060 (edid_ext[i + j] >> 3) & 0xf);
5061 goto end;
5062 }
5063 }
5064end:
5065 return has_audio;
5066}
5067EXPORT_SYMBOL(drm_detect_monitor_audio);
5068
b1edd6a6 5069
c8127cf0
VS		 5070/**
5071 * drm_default_rgb_quant_range - default RGB quantization range
5072 * @mode: display mode
5073 *
5074 * Determine the default RGB quantization range for the mode,
5075 * as specified in CEA-861.
5076 *
5077 * Return: The default RGB quantization range for the mode
5078 */
5079enum hdmi_quantization_range
5080drm_default_rgb_quant_range(const struct drm_display_mode *mode)
5081{
5082 /* All CEA modes other than VIC 1 use limited quantization range. */
5083 return drm_match_cea_mode(mode) > 1 ?
5084 HDMI_QUANTIZATION_RANGE_LIMITED :
5085 HDMI_QUANTIZATION_RANGE_FULL;
5086}
5087EXPORT_SYMBOL(drm_default_rgb_quant_range);
5088
1581b2df
VS		 5089static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
5090{
5091 struct drm_display_info *info = &connector->display_info;
5092
5093 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]);
5094
5095 if (db[2] & EDID_CEA_VCDB_QS)
5096 info->rgb_quant_range_selectable = true;
5097}
5098
4499d488
SS		 5099static
5100void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane)
5101{
5102 switch (max_frl_rate) {
5103 case 1:
5104 *max_lanes = 3;
5105 *max_rate_per_lane = 3;
5106 break;
5107 case 2:
5108 *max_lanes = 3;
5109 *max_rate_per_lane = 6;
5110 break;
5111 case 3:
5112 *max_lanes = 4;
5113 *max_rate_per_lane = 6;
5114 break;
5115 case 4:
5116 *max_lanes = 4;
5117 *max_rate_per_lane = 8;
5118 break;
5119 case 5:
5120 *max_lanes = 4;
5121 *max_rate_per_lane = 10;
5122 break;
5123 case 6:
5124 *max_lanes = 4;
5125 *max_rate_per_lane = 12;
5126 break;
5127 case 0:
5128 default:
5129 *max_lanes = 0;
5130 *max_rate_per_lane = 0;
5131 }
5132}
5133
e6a9a2c3
SS		 5134static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
5135 const u8 *db)
5136{
5137 u8 dc_mask;
5138 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
5139
5140 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
9068e02f 5141 hdmi->y420_dc_modes = dc_mask;
e6a9a2c3
SS		 5142}
5143
afa1c763
SS		 5144static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector,
5145 const u8 *hf_vsdb)
5146{
62c58af3
SS		 5147 struct drm_display_info *display = &connector->display_info;
5148 struct drm_hdmi_info *hdmi = &display->hdmi;
afa1c763 5149
f1781e9b
VS		 5150 display->has_hdmi_infoframe = true;
5151
afa1c763
SS		 5152 if (hf_vsdb[6] & 0x80) {
5153 hdmi->scdc.supported = true;
5154 if (hf_vsdb[6] & 0x40)
5155 hdmi->scdc.read_request = true;
5156 }
62c58af3
SS		 5157
5158 /*
5159 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
5160 * And as per the spec, three factors confirm this:
5161 * * Availability of a HF-VSDB block in EDID (check)
5162 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
5163 * * SCDC support available (let's check)
5164 * Lets check it out.
5165 */
5166
5167 if (hf_vsdb[5]) {
5168 /* max clock is 5000 KHz times block value */
5169 u32 max_tmds_clock = hf_vsdb[5] * 5000;
5170 struct drm_scdc *scdc = &hdmi->scdc;
5171
5172 if (max_tmds_clock > 340000) {
5173 display->max_tmds_clock = max_tmds_clock;
5174 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
5175 display->max_tmds_clock);
5176 }
5177
5178 if (scdc->supported) {
5179 scdc->scrambling.supported = true;
5180
dbe2d2bf 5181 /* Few sinks support scrambling for clocks < 340M */
62c58af3
SS		 5182 if ((hf_vsdb[6] & 0x8))
5183 scdc->scrambling.low_rates = true;
5184 }
5185 }
e6a9a2c3 5186
4499d488
SS		 5187 if (hf_vsdb[7]) {
5188 u8 max_frl_rate;
76ee7b90
AN		 5189 u8 dsc_max_frl_rate;
5190 u8 dsc_max_slices;
5191 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap;
4499d488
SS		 5192
5193 DRM_DEBUG_KMS("hdmi_21 sink detected. parsing edid\n");
5194 max_frl_rate = (hf_vsdb[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4;
5195 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes,
5196 &hdmi->max_frl_rate_per_lane);
76ee7b90
AN		 5197 hdmi_dsc->v_1p2 = hf_vsdb[11] & DRM_EDID_DSC_1P2;
5198
5199 if (hdmi_dsc->v_1p2) {
5200 hdmi_dsc->native_420 = hf_vsdb[11] & DRM_EDID_DSC_NATIVE_420;
5201 hdmi_dsc->all_bpp = hf_vsdb[11] & DRM_EDID_DSC_ALL_BPP;
5202
5203 if (hf_vsdb[11] & DRM_EDID_DSC_16BPC)
5204 hdmi_dsc->bpc_supported = 16;
5205 else if (hf_vsdb[11] & DRM_EDID_DSC_12BPC)
5206 hdmi_dsc->bpc_supported = 12;
5207 else if (hf_vsdb[11] & DRM_EDID_DSC_10BPC)
5208 hdmi_dsc->bpc_supported = 10;
5209 else
5210 hdmi_dsc->bpc_supported = 0;
5211
5212 dsc_max_frl_rate = (hf_vsdb[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4;
5213 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes,
5214 &hdmi_dsc->max_frl_rate_per_lane);
5215 hdmi_dsc->total_chunk_kbytes = hf_vsdb[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES;
5216
5217 dsc_max_slices = hf_vsdb[12] & DRM_EDID_DSC_MAX_SLICES;
5218 switch (dsc_max_slices) {
5219 case 1:
5220 hdmi_dsc->max_slices = 1;
5221 hdmi_dsc->clk_per_slice = 340;
5222 break;
5223 case 2:
5224 hdmi_dsc->max_slices = 2;
5225 hdmi_dsc->clk_per_slice = 340;
5226 break;
5227 case 3:
5228 hdmi_dsc->max_slices = 4;
5229 hdmi_dsc->clk_per_slice = 340;
5230 break;
5231 case 4:
5232 hdmi_dsc->max_slices = 8;
5233 hdmi_dsc->clk_per_slice = 340;
5234 break;
5235 case 5:
5236 hdmi_dsc->max_slices = 8;
5237 hdmi_dsc->clk_per_slice = 400;
5238 break;
5239 case 6:
5240 hdmi_dsc->max_slices = 12;
5241 hdmi_dsc->clk_per_slice = 400;
5242 break;
5243 case 7:
5244 hdmi_dsc->max_slices = 16;
5245 hdmi_dsc->clk_per_slice = 400;
5246 break;
5247 case 0:
5248 default:
5249 hdmi_dsc->max_slices = 0;
5250 hdmi_dsc->clk_per_slice = 0;
5251 }
5252 }
4499d488
SS		 5253 }
5254
e6a9a2c3 5255 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb);
afa1c763
SS		 5256}
5257
1cea146a
VS		 5258static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
5259 const u8 *hdmi)
d0c94692 5260{
1826750f 5261 struct drm_display_info *info = &connector->display_info;
d0c94692
MK		 5262 unsigned int dc_bpc = 0;
5263
1cea146a
VS		 5264 /* HDMI supports at least 8 bpc */
5265 info->bpc = 8;
d0c94692 5266
1cea146a
VS		 5267 if (cea_db_payload_len(hdmi) < 6)
5268 return;
5269
5270 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
5271 dc_bpc = 10;
4adc33f3 5272 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_30;
1cea146a
VS		 5273 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
5274 connector->name);
5275 }
5276
5277 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
5278 dc_bpc = 12;
4adc33f3 5279 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_36;
1cea146a
VS		 5280 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
5281 connector->name);
5282 }
5283
5284 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
5285 dc_bpc = 16;
4adc33f3 5286 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_48;
1cea146a
VS		 5287 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
5288 connector->name);
5289 }
5290
5291 if (dc_bpc == 0) {
5292 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
5293 connector->name);
5294 return;
5295 }
5296
5297 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
5298 connector->name, dc_bpc);
5299 info->bpc = dc_bpc;
d0c94692 5300
1cea146a
VS		 5301 /* YCRCB444 is optional according to spec. */
5302 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
4adc33f3 5303 info->edid_hdmi_ycbcr444_dc_modes = info->edid_hdmi_rgb444_dc_modes;
1cea146a
VS		 5304 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
5305 connector->name);
5306 }
d0c94692 5307
1cea146a
VS		 5308 /*
5309 * Spec says that if any deep color mode is supported at all,
5310 * then deep color 36 bit must be supported.
5311 */
5312 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
5313 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
5314 connector->name);
5315 }
5316}
d0c94692 5317
23ebf8b9
VS		 5318static void
5319drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
5320{
5321 struct drm_display_info *info = &connector->display_info;
5322 u8 len = cea_db_payload_len(db);
5323
a92d083d
LP		 5324 info->is_hdmi = true;
5325
23ebf8b9
VS		 5326 if (len >= 6)
5327 info->dvi_dual = db[6] & 1;
5328 if (len >= 7)
5329 info->max_tmds_clock = db[7] * 5000;
5330
5331 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
5332 "max TMDS clock %d kHz\n",
5333 info->dvi_dual,
5334 info->max_tmds_clock);
5335
5336 drm_parse_hdmi_deep_color_info(connector, db);
5337}
5338
2869f599
PZ		 5339/*
5340 * See EDID extension for head-mounted and specialized monitors, specified at:
5341 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/specialized-monitors-edid-extension
5342 */
5343static void drm_parse_microsoft_vsdb(struct drm_connector *connector,
5344 const u8 *db)
5345{
5346 struct drm_display_info *info = &connector->display_info;
5347 u8 version = db[4];
5348 bool desktop_usage = db[5] & BIT(6);
5349
5350 /* Version 1 and 2 for HMDs, version 3 flags desktop usage explicitly */
5351 if (version == 1 || version == 2 || (version == 3 && !desktop_usage))
5352 info->non_desktop = true;
5353
5354 drm_dbg_kms(connector->dev, "HMD or specialized display VSDB version %u: 0x%02x\n",
5355 version, db[5]);
5356}
5357
1cea146a 5358static void drm_parse_cea_ext(struct drm_connector *connector,
170178fe 5359 const struct edid *edid)
1cea146a
VS		 5360{
5361 struct drm_display_info *info = &connector->display_info;
5362 const u8 *edid_ext;
5363 int i, start, end;
d0c94692 5364
1cea146a
VS		 5365 edid_ext = drm_find_cea_extension(edid);
5366 if (!edid_ext)
5367 return;
d0c94692 5368
1cea146a 5369 info->cea_rev = edid_ext[1];
d0c94692 5370
1cea146a
VS		 5371 /* The existence of a CEA block should imply RGB support */
5372 info->color_formats = DRM_COLOR_FORMAT_RGB444;
7344bad7
JN		 5373
5374 /* CTA DisplayID Data Block does not have byte #3 */
5375 if (edid_ext[0] == CEA_EXT) {
5376 if (edid_ext[3] & EDID_CEA_YCRCB444)
5377 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
5378 if (edid_ext[3] & EDID_CEA_YCRCB422)
5379 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
5380 }
1cea146a
VS		 5381
5382 if (cea_db_offsets(edid_ext, &start, &end))
5383 return;
5384
5385 for_each_cea_db(edid_ext, i, start, end) {
5386 const u8 *db = &edid_ext[i];
5387
23ebf8b9
VS		 5388 if (cea_db_is_hdmi_vsdb(db))
5389 drm_parse_hdmi_vsdb_video(connector, db);
afa1c763
SS		 5390 if (cea_db_is_hdmi_forum_vsdb(db))
5391 drm_parse_hdmi_forum_vsdb(connector, db);
2869f599
PZ		 5392 if (cea_db_is_microsoft_vsdb(db))
5393 drm_parse_microsoft_vsdb(connector, db);
832d4f2f
SS		 5394 if (cea_db_is_y420cmdb(db))
5395 drm_parse_y420cmdb_bitmap(connector, db);
1581b2df
VS		 5396 if (cea_db_is_vcdb(db))
5397 drm_parse_vcdb(connector, db);
e85959d6
US		 5398 if (cea_db_is_hdmi_hdr_metadata_block(db))
5399 drm_parse_hdr_metadata_block(connector, db);
1cea146a 5400 }
d0c94692
MK		 5401}
5402
a1d11d1e 5403static
4194442d 5404void get_monitor_range(const struct detailed_timing *timing,
a1d11d1e
MN		 5405 void *info_monitor_range)
5406{
5407 struct drm_monitor_range_info *monitor_range = info_monitor_range;
5408 const struct detailed_non_pixel *data = &timing->data.other_data;
5409 const struct detailed_data_monitor_range *range = &data->data.range;
5410
e379814b 5411 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
a1d11d1e
MN		 5412 return;
5413
5414 /*
5415 * Check for flag range limits only. If flag == 1 then
5416 * no additional timing information provided.
5417 * Default GTF, GTF Secondary curve and CVT are not
5418 * supported
5419 */
5420 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG)
5421 return;
5422
5423 monitor_range->min_vfreq = range->min_vfreq;
5424 monitor_range->max_vfreq = range->max_vfreq;
5425}
5426
5427static
5428void drm_get_monitor_range(struct drm_connector *connector,
5429 const struct edid *edid)
5430{
5431 struct drm_display_info *info = &connector->display_info;
5432
5433 if (!version_greater(edid, 1, 1))
5434 return;
5435
eed628f1 5436 drm_for_each_detailed_block(edid, get_monitor_range,
a1d11d1e
MN		 5437 &info->monitor_range);
5438
5439 DRM_DEBUG_KMS("Supported Monitor Refresh rate range is %d Hz - %d Hz\n",
5440 info->monitor_range.min_vfreq,
5441 info->monitor_range.max_vfreq);
5442}
5443
18a9cbbe
JN		 5444static void drm_parse_vesa_mso_data(struct drm_connector *connector,
5445 const struct displayid_block *block)
5446{
5447 struct displayid_vesa_vendor_specific_block *vesa =
5448 (struct displayid_vesa_vendor_specific_block *)block;
5449 struct drm_display_info *info = &connector->display_info;
5450
5451 if (block->num_bytes < 3) {
5452 drm_dbg_kms(connector->dev, "Unexpected vendor block size %u\n",
5453 block->num_bytes);
5454 return;
5455 }
5456
5457 if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI)
5458 return;
5459
5460 if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
5461 drm_dbg_kms(connector->dev, "Unexpected VESA vendor block size\n");
5462 return;
5463 }
5464
5465 switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
5466 default:
5467 drm_dbg_kms(connector->dev, "Reserved MSO mode value\n");
5468 fallthrough;
5469 case 0:
5470 info->mso_stream_count = 0;
5471 break;
5472 case 1:
5473 info->mso_stream_count = 2; /* 2 or 4 links */
5474 break;
5475 case 2:
5476 info->mso_stream_count = 4; /* 4 links */
5477 break;
5478 }
5479
5480 if (!info->mso_stream_count) {
5481 info->mso_pixel_overlap = 0;
5482 return;
5483 }
5484
5485 info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
5486 if (info->mso_pixel_overlap > 8) {
5487 drm_dbg_kms(connector->dev, "Reserved MSO pixel overlap value %u\n",
5488 info->mso_pixel_overlap);
5489 info->mso_pixel_overlap = 8;
5490 }
5491
5492 drm_dbg_kms(connector->dev, "MSO stream count %u, pixel overlap %u\n",
5493 info->mso_stream_count, info->mso_pixel_overlap);
5494}
5495
5496static void drm_update_mso(struct drm_connector *connector, const struct edid *edid)
5497{
5498 const struct displayid_block *block;
5499 struct displayid_iter iter;
5500
5501 displayid_iter_edid_begin(edid, &iter);
5502 displayid_iter_for_each(block, &iter) {
5503 if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC)
5504 drm_parse_vesa_mso_data(connector, block);
5505 }
5506 displayid_iter_end(&iter);
5507}
5508
170178fe
KP		 5509/* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
5510 * all of the values which would have been set from EDID
5511 */
5512void
5513drm_reset_display_info(struct drm_connector *connector)
5514{
5515 struct drm_display_info *info = &connector->display_info;
5516
5517 info->width_mm = 0;
5518 info->height_mm = 0;
5519
5520 info->bpc = 0;
5521 info->color_formats = 0;
5522 info->cea_rev = 0;
5523 info->max_tmds_clock = 0;
5524 info->dvi_dual = false;
a92d083d 5525 info->is_hdmi = false;
170178fe 5526 info->has_hdmi_infoframe = false;
1581b2df 5527 info->rgb_quant_range_selectable = false;
1f6b8eef 5528 memset(&info->hdmi, 0, sizeof(info->hdmi));
170178fe 5529
70c0b80d
MR		 5530 info->edid_hdmi_rgb444_dc_modes = 0;
5531 info->edid_hdmi_ycbcr444_dc_modes = 0;
5532
170178fe 5533 info->non_desktop = 0;
a1d11d1e 5534 memset(&info->monitor_range, 0, sizeof(info->monitor_range));
18a9cbbe
JN		 5535
5536 info->mso_stream_count = 0;
5537 info->mso_pixel_overlap = 0;
170178fe 5538}
170178fe
KP		 5539
5540u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid)
3b11228b 5541{
1826750f 5542 struct drm_display_info *info = &connector->display_info;
ebec9a7b 5543
170178fe
KP		 5544 u32 quirks = edid_get_quirks(edid);
5545
1f6b8eef
VS		 5546 drm_reset_display_info(connector);
5547
3b11228b
JB		 5548 info->width_mm = edid->width_cm * 10;
5549 info->height_mm = edid->height_cm * 10;
5550
a1d11d1e
MN		 5551 drm_get_monitor_range(connector, edid);
5552
a988bc72 5553 if (edid->revision < 3)
ce99534e 5554 goto out;
3b11228b
JB		 5555
5556 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
ce99534e 5557 goto out;
3b11228b 5558
ecbd4912 5559 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
1cea146a 5560 drm_parse_cea_ext(connector, edid);
d0c94692 5561
210a021d
MK		 5562 /*
5563 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
5564 *
5565 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
5566 * tells us to assume 8 bpc color depth if the EDID doesn't have
5567 * extensions which tell otherwise.
5568 */
3bde449f
VS		 5569 if (info->bpc == 0 && edid->revision == 3 &&
5570 edid->input & DRM_EDID_DIGITAL_DFP_1_X) {
210a021d
MK		 5571 info->bpc = 8;
5572 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
5573 connector->name, info->bpc);
5574 }
5575
a988bc72
LPC		 5576 /* Only defined for 1.4 with digital displays */
5577 if (edid->revision < 4)
ce99534e 5578 goto out;
a988bc72 5579
3b11228b
JB		 5580 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
5581 case DRM_EDID_DIGITAL_DEPTH_6:
5582 info->bpc = 6;
5583 break;
5584 case DRM_EDID_DIGITAL_DEPTH_8:
5585 info->bpc = 8;
5586 break;
5587 case DRM_EDID_DIGITAL_DEPTH_10:
5588 info->bpc = 10;
5589 break;
5590 case DRM_EDID_DIGITAL_DEPTH_12:
5591 info->bpc = 12;
5592 break;
5593 case DRM_EDID_DIGITAL_DEPTH_14:
5594 info->bpc = 14;
5595 break;
5596 case DRM_EDID_DIGITAL_DEPTH_16:
5597 info->bpc = 16;
5598 break;
5599 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
5600 default:
5601 info->bpc = 0;
5602 break;
5603 }
da05a5a7 5604
d0c94692 5605 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
25933820 5606 connector->name, info->bpc);
d0c94692 5607
ee58808d 5608 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
c03d0b52 5609 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
ee58808d 5610 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
c03d0b52 5611 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
18a9cbbe
JN		 5612
5613 drm_update_mso(connector, edid);
5614
ce99534e
JN		 5615out:
5616 if (quirks & EDID_QUIRK_NON_DESKTOP) {
5617 drm_dbg_kms(connector->dev, "Non-desktop display%s\n",
5618 info->non_desktop ? " (redundant quirk)" : "");
5619 info->non_desktop = true;
5620 }
5621
170178fe 5622 return quirks;
3b11228b
JB		 5623}
5624
a39ed680 5625static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
80ecb5d7
YB		 5626 struct displayid_detailed_timings_1 *timings,
5627 bool type_7)
a39ed680
DA		 5628{
5629 struct drm_display_mode *mode;
5630 unsigned pixel_clock = (timings->pixel_clock[0] |
5631 (timings->pixel_clock[1] << 8) |
6292b8ef 5632 (timings->pixel_clock[2] << 16)) + 1;
a39ed680
DA		 5633 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
5634 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
5635 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
5636 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
5637 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
5638 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
5639 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
5640 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
5641 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
5642 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
948de842 5643
a39ed680
DA		 5644 mode = drm_mode_create(dev);
5645 if (!mode)
5646 return NULL;
5647
80ecb5d7
YB		 5648 /* resolution is kHz for type VII, and 10 kHz for type I */
5649 mode->clock = type_7 ? pixel_clock : pixel_clock * 10;
a39ed680
DA		 5650 mode->hdisplay = hactive;
5651 mode->hsync_start = mode->hdisplay + hsync;
5652 mode->hsync_end = mode->hsync_start + hsync_width;
5653 mode->htotal = mode->hdisplay + hblank;
5654
5655 mode->vdisplay = vactive;
5656 mode->vsync_start = mode->vdisplay + vsync;
5657 mode->vsync_end = mode->vsync_start + vsync_width;
5658 mode->vtotal = mode->vdisplay + vblank;
5659
5660 mode->flags = 0;
5661 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
5662 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
5663 mode->type = DRM_MODE_TYPE_DRIVER;
5664
5665 if (timings->flags & 0x80)
5666 mode->type |= DRM_MODE_TYPE_PREFERRED;
a39ed680
DA		 5667 drm_mode_set_name(mode);
5668
5669 return mode;
5670}
5671
5672static int add_displayid_detailed_1_modes(struct drm_connector *connector,
43d16d84 5673 const struct displayid_block *block)
a39ed680
DA		 5674{
5675 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
5676 int i;
5677 int num_timings;
5678 struct drm_display_mode *newmode;
5679 int num_modes = 0;
80ecb5d7 5680 bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING;
a39ed680
DA		 5681 /* blocks must be multiple of 20 bytes length */
5682 if (block->num_bytes % 20)
5683 return 0;
5684
5685 num_timings = block->num_bytes / 20;
5686 for (i = 0; i < num_timings; i++) {
5687 struct displayid_detailed_timings_1 *timings = &det->timings[i];
5688
80ecb5d7 5689 newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7);
a39ed680
DA		 5690 if (!newmode)
5691 continue;
5692
5693 drm_mode_probed_add(connector, newmode);
5694 num_modes++;
5695 }
5696 return num_modes;
5697}
5698
5699static int add_displayid_detailed_modes(struct drm_connector *connector,
f4e558ec 5700 const struct edid *edid)
a39ed680 5701{
43d16d84 5702 const struct displayid_block *block;
5ef88dc5 5703 struct displayid_iter iter;
a39ed680
DA		 5704 int num_modes = 0;
5705
5ef88dc5
JN		 5706 displayid_iter_edid_begin(edid, &iter);
5707 displayid_iter_for_each(block, &iter) {
80ecb5d7
YB		 5708 if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING ||
5709 block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING)
5ef88dc5 5710 num_modes += add_displayid_detailed_1_modes(connector, block);
a39ed680 5711 }
5ef88dc5 5712 displayid_iter_end(&iter);
7f261afd 5713
a39ed680
DA		 5714 return num_modes;
5715}
5716
f40ab034
JN		 5717static int drm_edid_connector_update(struct drm_connector *connector,
5718 const struct edid *edid)
f453ba04
DA		 5719{
5720 int num_modes = 0;
5721 u32 quirks;
5722
5723 if (edid == NULL) {
c945b8c1 5724 clear_eld(connector);
f453ba04
DA		 5725 return 0;
5726 }
f453ba04 5727
c945b8c1
JN		 5728 drm_edid_to_eld(connector, edid);
5729
0f0f8708
SS		 5730 /*
5731 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
5732 * To avoid multiple parsing of same block, lets parse that map
5733 * from sink info, before parsing CEA modes.
5734 */
170178fe 5735 quirks = drm_add_display_info(connector, edid);
0f0f8708 5736
c867df70
AJ		 5737 /*
5738 * EDID spec says modes should be preferred in this order:
5739 * - preferred detailed mode
5740 * - other detailed modes from base block
5741 * - detailed modes from extension blocks
5742 * - CVT 3-byte code modes
5743 * - standard timing codes
5744 * - established timing codes
5745 * - modes inferred from GTF or CVT range information
5746 *
13931579 5747 * We get this pretty much right.
c867df70
AJ		 5748 *
5749 * XXX order for additional mode types in extension blocks?
5750 */
13931579
AJ		 5751 num_modes += add_detailed_modes(connector, edid, quirks);
5752 num_modes += add_cvt_modes(connector, edid);
c867df70
AJ		 5753 num_modes += add_standard_modes(connector, edid);
5754 num_modes += add_established_modes(connector, edid);
54ac76f8 5755 num_modes += add_cea_modes(connector, edid);
e6e79209 5756 num_modes += add_alternate_cea_modes(connector, edid);
a39ed680 5757 num_modes += add_displayid_detailed_modes(connector, edid);
4d53dc0c
VS		 5758 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
5759 num_modes += add_inferred_modes(connector, edid);
f453ba04
DA		 5760
5761 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
5762 edid_fixup_preferred(connector, quirks);
5763
e10aec65
MK		 5764 if (quirks & EDID_QUIRK_FORCE_6BPC)
5765 connector->display_info.bpc = 6;
5766
49d45a31
RM		 5767 if (quirks & EDID_QUIRK_FORCE_8BPC)
5768 connector->display_info.bpc = 8;
5769
e345da82
MK		 5770 if (quirks & EDID_QUIRK_FORCE_10BPC)
5771 connector->display_info.bpc = 10;
5772
bc5b9641
MK		 5773 if (quirks & EDID_QUIRK_FORCE_12BPC)
5774 connector->display_info.bpc = 12;
5775
f453ba04
DA		 5776 return num_modes;
5777}
f40ab034
JN		 5778
5779/**
5780 * drm_add_edid_modes - add modes from EDID data, if available
5781 * @connector: connector we're probing
5782 * @edid: EDID data
5783 *
5784 * Add the specified modes to the connector's mode list. Also fills out the
5785 * &drm_display_info structure and ELD in @connector with any information which
5786 * can be derived from the edid.
5787 *
5788 * Return: The number of modes added or 0 if we couldn't find any.
5789 */
5790int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
5791{
5792 if (edid && !drm_edid_is_valid(edid)) {
5793 drm_warn(connector->dev, "%s: EDID invalid.\n",
5794 connector->name);
5795 edid = NULL;
5796 }
5797
5798 return drm_edid_connector_update(connector, edid);
5799}
f453ba04 5800EXPORT_SYMBOL(drm_add_edid_modes);
f0fda0a4
ZY		 5801
5802/**
5803 * drm_add_modes_noedid - add modes for the connectors without EDID
5804 * @connector: connector we're probing
5805 * @hdisplay: the horizontal display limit
5806 * @vdisplay: the vertical display limit
5807 *
5808 * Add the specified modes to the connector's mode list. Only when the
5809 * hdisplay/vdisplay is not beyond the given limit, it will be added.
5810 *
db6cf833 5811 * Return: The number of modes added or 0 if we couldn't find any.
f0fda0a4
ZY		 5812 */
5813int drm_add_modes_noedid(struct drm_connector *connector,
5814 int hdisplay, int vdisplay)
5815{
5816 int i, count, num_modes = 0;
b1f559ec 5817 struct drm_display_mode *mode;
f0fda0a4
ZY		 5818 struct drm_device *dev = connector->dev;
5819
fbb40b28 5820 count = ARRAY_SIZE(drm_dmt_modes);
f0fda0a4
ZY		 5821 if (hdisplay < 0)
5822 hdisplay = 0;
5823 if (vdisplay < 0)
5824 vdisplay = 0;
5825
5826 for (i = 0; i < count; i++) {
b1f559ec 5827 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
948de842 5828
f0fda0a4
ZY		 5829 if (hdisplay && vdisplay) {
5830 /*
5831 * Only when two are valid, they will be used to check
5832 * whether the mode should be added to the mode list of
5833 * the connector.
5834 */
5835 if (ptr->hdisplay > hdisplay ||
5836 ptr->vdisplay > vdisplay)
5837 continue;
5838 }
f985dedb
AJ		 5839 if (drm_mode_vrefresh(ptr) > 61)
5840 continue;
f0fda0a4
ZY		 5841 mode = drm_mode_duplicate(dev, ptr);
5842 if (mode) {
5843 drm_mode_probed_add(connector, mode);
5844 num_modes++;
5845 }
5846 }
5847 return num_modes;
5848}
5849EXPORT_SYMBOL(drm_add_modes_noedid);
10a85120 5850
db6cf833
TR		 5851/**
5852 * drm_set_preferred_mode - Sets the preferred mode of a connector
5853 * @connector: connector whose mode list should be processed
5854 * @hpref: horizontal resolution of preferred mode
5855 * @vpref: vertical resolution of preferred mode
5856 *
5857 * Marks a mode as preferred if it matches the resolution specified by @hpref
5858 * and @vpref.
5859 */
3cf70daf
GH		 5860void drm_set_preferred_mode(struct drm_connector *connector,
5861 int hpref, int vpref)
5862{
5863 struct drm_display_mode *mode;
5864
5865 list_for_each_entry(mode, &connector->probed_modes, head) {
db6cf833 5866 if (mode->hdisplay == hpref &&
9d3de138 5867 mode->vdisplay == vpref)
3cf70daf
GH		 5868 mode->type |= DRM_MODE_TYPE_PREFERRED;
5869 }
5870}
5871EXPORT_SYMBOL(drm_set_preferred_mode);
5872
192a3aa0 5873static bool is_hdmi2_sink(const struct drm_connector *connector)
13d0add3
VS		 5874{
5875 /*
5876 * FIXME: sil-sii8620 doesn't have a connector around when
5877 * we need one, so we have to be prepared for a NULL connector.
5878 */
5879 if (!connector)
5880 return true;
5881
5882 return connector->display_info.hdmi.scdc.supported ||
c03d0b52 5883 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR420;
13d0add3
VS		 5884}
5885
192a3aa0 5886static u8 drm_mode_hdmi_vic(const struct drm_connector *connector,
949561eb
VS		 5887 const struct drm_display_mode *mode)
5888{
5889 bool has_hdmi_infoframe = connector ?
5890 connector->display_info.has_hdmi_infoframe : false;
5891
5892 if (!has_hdmi_infoframe)
5893 return 0;
5894
5895 /* No HDMI VIC when signalling 3D video format */
5896 if (mode->flags & DRM_MODE_FLAG_3D_MASK)
5897 return 0;
5898
5899 return drm_match_hdmi_mode(mode);
5900}
5901
192a3aa0 5902static u8 drm_mode_cea_vic(const struct drm_connector *connector,
cfd6f8c3
VS		 5903 const struct drm_display_mode *mode)
5904{
cfd6f8c3
VS		 5905 u8 vic;
5906
5907 /*
5908 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
5909 * we should send its VIC in vendor infoframes, else send the
5910 * VIC in AVI infoframes. Lets check if this mode is present in
5911 * HDMI 1.4b 4K modes
5912 */
949561eb 5913 if (drm_mode_hdmi_vic(connector, mode))
cfd6f8c3
VS		 5914 return 0;
5915
5916 vic = drm_match_cea_mode(mode);
5917
5918 /*
5919 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
5920 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
5921 * have to make sure we dont break HDMI 1.4 sinks.
5922 */
5923 if (!is_hdmi2_sink(connector) && vic > 64)
5924 return 0;
5925
5926 return vic;
5927}
5928
10a85120
TR		 5929/**
5930 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
5931 * data from a DRM display mode
5932 * @frame: HDMI AVI infoframe
13d0add3 5933 * @connector: the connector
10a85120
TR		 5934 * @mode: DRM display mode
5935 *
db6cf833 5936 * Return: 0 on success or a negative error code on failure.
10a85120
TR		 5937 */
5938int
5939drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
192a3aa0 5940 const struct drm_connector *connector,
13d0add3 5941 const struct drm_display_mode *mode)
10a85120 5942{
a9c266c2 5943 enum hdmi_picture_aspect picture_aspect;
d2b43473 5944 u8 vic, hdmi_vic;
10a85120
TR		 5945
5946 if (!frame || !mode)
5947 return -EINVAL;
5948
5ee0caf1 5949 hdmi_avi_infoframe_init(frame);
10a85120 5950
bf02db99
DL		 5951 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
5952 frame->pixel_repeat = 1;
5953
d2b43473
WL		 5954 vic = drm_mode_cea_vic(connector, mode);
5955 hdmi_vic = drm_mode_hdmi_vic(connector, mode);
0c1f528c 5956
10a85120 5957 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
0967e6a5 5958
50525c33
SL		 5959 /*
5960 * As some drivers don't support atomic, we can't use connector state.
5961 * So just initialize the frame with default values, just the same way
5962 * as it's done with other properties here.
5963 */
5964 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
5965 frame->itc = 0;
5966
69ab6d35
VK		 5967 /*
5968 * Populate picture aspect ratio from either
d2b43473 5969 * user input (if specified) or from the CEA/HDMI mode lists.
69ab6d35 5970 */
a9c266c2 5971 picture_aspect = mode->picture_aspect_ratio;
d2b43473
WL		 5972 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) {
5973 if (vic)
5974 picture_aspect = drm_get_cea_aspect_ratio(vic);
5975 else if (hdmi_vic)
5976 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic);
5977 }
0967e6a5 5978
a9c266c2
VS		 5979 /*
5980 * The infoframe can't convey anything but none, 4:3
5981 * and 16:9, so if the user has asked for anything else
5982 * we can only satisfy it by specifying the right VIC.
5983 */
5984 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
d2b43473
WL		 5985 if (vic) {
5986 if (picture_aspect != drm_get_cea_aspect_ratio(vic))
5987 return -EINVAL;
5988 } else if (hdmi_vic) {
5989 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic))
5990 return -EINVAL;
5991 } else {
a9c266c2 5992 return -EINVAL;
d2b43473
WL		 5993 }
5994
a9c266c2
VS		 5995 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
5996 }
5997
d2b43473 5998 frame->video_code = vic;
a9c266c2 5999 frame->picture_aspect = picture_aspect;
10a85120 6000 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
24d01805 6001 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
10a85120
TR		 6002
6003 return 0;
6004}
6005EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
83dd0008 6006
a2ce26f8
VS		 6007/**
6008 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
6009 * quantization range information
6010 * @frame: HDMI AVI infoframe
13d0add3 6011 * @connector: the connector
779c4c28 6012 * @mode: DRM display mode
a2ce26f8 6013 * @rgb_quant_range: RGB quantization range (Q)
a2ce26f8
VS		 6014 */
6015void
6016drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
192a3aa0 6017 const struct drm_connector *connector,
779c4c28 6018 const struct drm_display_mode *mode,
1581b2df 6019 enum hdmi_quantization_range rgb_quant_range)
a2ce26f8 6020{
1581b2df
VS		 6021 const struct drm_display_info *info = &connector->display_info;
6022
a2ce26f8
VS		 6023 /*
6024 * CEA-861:
6025 * "A Source shall not send a non-zero Q value that does not correspond
6026 * to the default RGB Quantization Range for the transmitted Picture
6027 * unless the Sink indicates support for the Q bit in a Video
6028 * Capabilities Data Block."
779c4c28
VS		 6029 *
6030 * HDMI 2.0 recommends sending non-zero Q when it does match the
6031 * default RGB quantization range for the mode, even when QS=0.
a2ce26f8 6032 */
1581b2df 6033 if (info->rgb_quant_range_selectable ||
779c4c28 6034 rgb_quant_range == drm_default_rgb_quant_range(mode))
a2ce26f8
VS		 6035 frame->quantization_range = rgb_quant_range;
6036 else
6037 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
fcc8a22c
VS		 6038
6039 /*
6040 * CEA-861-F:
6041 * "When transmitting any RGB colorimetry, the Source should set the
6042 * YQ-field to match the RGB Quantization Range being transmitted
6043 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
6044 * set YQ=1) and the Sink shall ignore the YQ-field."
9271c0ca
VS		 6045 *
6046 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
6047 * by non-zero YQ when receiving RGB. There doesn't seem to be any
6048 * good way to tell which version of CEA-861 the sink supports, so
6049 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
6050 * on on CEA-861-F.
fcc8a22c 6051 */
13d0add3 6052 if (!is_hdmi2_sink(connector) ||
9271c0ca 6053 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
fcc8a22c
VS		 6054 frame->ycc_quantization_range =
6055 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
6056 else
6057 frame->ycc_quantization_range =
6058 HDMI_YCC_QUANTIZATION_RANGE_FULL;
a2ce26f8
VS		 6059}
6060EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
6061
4eed4a0a
DL		 6062static enum hdmi_3d_structure
6063s3d_structure_from_display_mode(const struct drm_display_mode *mode)
6064{
6065 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
6066
6067 switch (layout) {
6068 case DRM_MODE_FLAG_3D_FRAME_PACKING:
6069 return HDMI_3D_STRUCTURE_FRAME_PACKING;
6070 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
6071 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
6072 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
6073 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
6074 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
6075 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
6076 case DRM_MODE_FLAG_3D_L_DEPTH:
6077 return HDMI_3D_STRUCTURE_L_DEPTH;
6078 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
6079 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
6080 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
6081 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
6082 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
6083 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
6084 default:
6085 return HDMI_3D_STRUCTURE_INVALID;
6086 }
6087}
6088
83dd0008
LD		 6089/**
6090 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
6091 * data from a DRM display mode
6092 * @frame: HDMI vendor infoframe
f1781e9b 6093 * @connector: the connector
83dd0008
LD		 6094 * @mode: DRM display mode
6095 *
6096 * Note that there's is a need to send HDMI vendor infoframes only when using a
6097 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
6098 * function will return -EINVAL, error that can be safely ignored.
6099 *
db6cf833 6100 * Return: 0 on success or a negative error code on failure.
83dd0008
LD		 6101 */
6102int
6103drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
192a3aa0 6104 const struct drm_connector *connector,
83dd0008
LD		 6105 const struct drm_display_mode *mode)
6106{
f1781e9b
VS		 6107 /*
6108 * FIXME: sil-sii8620 doesn't have a connector around when
6109 * we need one, so we have to be prepared for a NULL connector.
6110 */
6111 bool has_hdmi_infoframe = connector ?
6112 connector->display_info.has_hdmi_infoframe : false;
83dd0008 6113 int err;
83dd0008
LD		 6114
6115 if (!frame || !mode)
6116 return -EINVAL;
6117
f1781e9b
VS		 6118 if (!has_hdmi_infoframe)
6119 return -EINVAL;
6120
949561eb
VS		 6121 err = hdmi_vendor_infoframe_init(frame);
6122 if (err < 0)
6123 return err;
4eed4a0a 6124
f1781e9b
VS		 6125 /*
6126 * Even if it's not absolutely necessary to send the infoframe
6127 * (ie.vic==0 and s3d_struct==0) we will still send it if we
6128 * know that the sink can handle it. This is based on a
6129 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
0ae865ef 6130 * have trouble realizing that they should switch from 3D to 2D
f1781e9b
VS		 6131 * mode if the source simply stops sending the infoframe when
6132 * it wants to switch from 3D to 2D.
6133 */
949561eb 6134 frame->vic = drm_mode_hdmi_vic(connector, mode);
f1781e9b 6135 frame->s3d_struct = s3d_structure_from_display_mode(mode);
83dd0008
LD		 6136
6137 return 0;
6138}
6139EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
40d9b043 6140
7f261afd
VS		 6141static void drm_parse_tiled_block(struct drm_connector *connector,
6142 const struct displayid_block *block)
5e546cd5 6143{
092c367a 6144 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
5e546cd5
DA		 6145 u16 w, h;
6146 u8 tile_v_loc, tile_h_loc;
6147 u8 num_v_tile, num_h_tile;
6148 struct drm_tile_group *tg;
6149
6150 w = tile->tile_size[0] | tile->tile_size[1] << 8;
6151 h = tile->tile_size[2] | tile->tile_size[3] << 8;
6152
6153 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
6154 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
6155 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
6156 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
6157
6158 connector->has_tile = true;
6159 if (tile->tile_cap & 0x80)
6160 connector->tile_is_single_monitor = true;
6161
6162 connector->num_h_tile = num_h_tile + 1;
6163 connector->num_v_tile = num_v_tile + 1;
6164 connector->tile_h_loc = tile_h_loc;
6165 connector->tile_v_loc = tile_v_loc;
6166 connector->tile_h_size = w + 1;
6167 connector->tile_v_size = h + 1;
6168
6169 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
6170 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
6171 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
6172 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
6173 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
6174
6175 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
392f9fcb 6176 if (!tg)
5e546cd5 6177 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
5e546cd5 6178 if (!tg)
7f261afd 6179 return;
5e546cd5
DA		 6180
6181 if (connector->tile_group != tg) {
6182 /* if we haven't got a pointer,
6183 take the reference, drop ref to old tile group */
392f9fcb 6184 if (connector->tile_group)
5e546cd5 6185 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5e546cd5 6186 connector->tile_group = tg;
392f9fcb 6187 } else {
5e546cd5
DA		 6188 /* if same tile group, then release the ref we just took. */
6189 drm_mode_put_tile_group(connector->dev, tg);
392f9fcb 6190 }
5e546cd5
DA		 6191}
6192
092c367a
VS		 6193void drm_update_tile_info(struct drm_connector *connector,
6194 const struct edid *edid)
40d9b043 6195{
bfd4e192
JN		 6196 const struct displayid_block *block;
6197 struct displayid_iter iter;
36881184 6198
40d9b043 6199 connector->has_tile = false;
7f261afd 6200
bfd4e192
JN		 6201 displayid_iter_edid_begin(edid, &iter);
6202 displayid_iter_for_each(block, &iter) {
6203 if (block->tag == DATA_BLOCK_TILED_DISPLAY)
6204 drm_parse_tiled_block(connector, block);
40d9b043 6205 }
bfd4e192 6206 displayid_iter_end(&iter);
40d9b043 6207
7f261afd 6208 if (!connector->has_tile && connector->tile_group) {
40d9b043
DA		 6209 drm_mode_put_tile_group(connector->dev, connector->tile_group);
6210 connector->tile_group = NULL;
6211 }
40d9b043 6212}
Linux 6.x block layer and io_uring tree(s)