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Merge branch 'urgent' of git://git.kernel.org/pub/scm/linux/kernel/git/brodo/pcmcia-2.6
[linux-2.6-block.git] / drivers / gpu / drm / drm_edid.c
CommitLineData
f453ba04
DA		 1/*
2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
7 * FB layer.
8 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
9 *
10 * Permission is hereby granted, free of charge, to any person obtaining a
11 * copy of this software and associated documentation files (the "Software"),
12 * to deal in the Software without restriction, including without limitation
13 * the rights to use, copy, modify, merge, publish, distribute, sub license,
14 * and/or sell copies of the Software, and to permit persons to whom the
15 * Software is furnished to do so, subject to the following conditions:
16 *
17 * The above copyright notice and this permission notice (including the
18 * next paragraph) shall be included in all copies or substantial portions
19 * of the Software.
20 *
21 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
22 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
23 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
24 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
25 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
26 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
27 * DEALINGS IN THE SOFTWARE.
28 */
29#include <linux/kernel.h>
5a0e3ad6 30#include <linux/slab.h>
f453ba04
DA		 31#include <linux/i2c.h>
32#include <linux/i2c-algo-bit.h>
33#include "drmP.h"
34#include "drm_edid.h"
35
36/*
37 * TODO:
38 * - support EDID 1.4 (incl. CE blocks)
39 */
40
41/*
42 * EDID blocks out in the wild have a variety of bugs, try to collect
43 * them here (note that userspace may work around broken monitors first,
44 * but fixes should make their way here so that the kernel "just works"
45 * on as many displays as possible).
46 */
47
48/* First detailed mode wrong, use largest 60Hz mode */
49#define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
50/* Reported 135MHz pixel clock is too high, needs adjustment */
51#define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
52/* Prefer the largest mode at 75 Hz */
53#define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
54/* Detail timing is in cm not mm */
55#define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
56/* Detailed timing descriptors have bogus size values, so just take the
57 * maximum size and use that.
58 */
59#define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
60/* Monitor forgot to set the first detailed is preferred bit. */
61#define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5)
62/* use +hsync +vsync for detailed mode */
63#define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
3c537889 64
f453ba04 65
5c61259e
ZY		 66#define LEVEL_DMT 0
67#define LEVEL_GTF 1
68#define LEVEL_CVT 2
69
f453ba04
DA		 70static struct edid_quirk {
71 char *vendor;
72 int product_id;
73 u32 quirks;
74} edid_quirk_list[] = {
75 /* Acer AL1706 */
76 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
77 /* Acer F51 */
78 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
79 /* Unknown Acer */
80 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
81
82 /* Belinea 10 15 55 */
83 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
84 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
85
86 /* Envision Peripherals, Inc. EN-7100e */
87 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
88
89 /* Funai Electronics PM36B */
90 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
91 EDID_QUIRK_DETAILED_IN_CM },
92
93 /* LG Philips LCD LP154W01-A5 */
94 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
95 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
96
97 /* Philips 107p5 CRT */
98 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
99
100 /* Proview AY765C */
101 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
102
103 /* Samsung SyncMaster 205BW. Note: irony */
104 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
105 /* Samsung SyncMaster 22[5-6]BW */
106 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
107 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
108};
109
110
111/* Valid EDID header has these bytes */
083ae056
AJ		 112static const u8 edid_header[] = {
113 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
114};
f453ba04
DA		 115
116/**
3c537889 117 * drm_edid_is_valid - sanity check EDID data
f453ba04
DA		 118 * @edid: EDID data
119 *
120 * Sanity check the EDID block by looking at the header, the version number
121 * and the checksum. Return 0 if the EDID doesn't check out, or 1 if it's
122 * valid.
123 */
3c537889 124bool drm_edid_is_valid(struct edid *edid)
f453ba04 125{
862b89c0 126 int i, score = 0;
f453ba04
DA		 127 u8 csum = 0;
128 u8 *raw_edid = (u8 *)edid;
129
862b89c0
AJ		 130 for (i = 0; i < sizeof(edid_header); i++)
131 if (raw_edid[i] == edid_header[i])
132 score++;
133
134 if (score == 8) ;
135 else if (score >= 6) {
136 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
137 memcpy(raw_edid, edid_header, sizeof(edid_header));
138 } else
f453ba04 139 goto bad;
f453ba04
DA		 140
141 for (i = 0; i < EDID_LENGTH; i++)
142 csum += raw_edid[i];
143 if (csum) {
144 DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum);
145 goto bad;
146 }
147
862b89c0
AJ		 148 if (edid->version != 1) {
149 DRM_ERROR("EDID has major version %d, instead of 1\n", edid->version);
150 goto bad;
151 }
152
47ee4ccf
AJ		 153 if (edid->revision > 4)
154 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
155
f453ba04
DA		 156 return 1;
157
158bad:
159 if (raw_edid) {
160 DRM_ERROR("Raw EDID:\n");
161 print_hex_dump_bytes(KERN_ERR, DUMP_PREFIX_NONE, raw_edid, EDID_LENGTH);
162 printk("\n");
163 }
164 return 0;
165}
3c537889 166EXPORT_SYMBOL(drm_edid_is_valid);
f453ba04
DA		 167
168/**
169 * edid_vendor - match a string against EDID's obfuscated vendor field
170 * @edid: EDID to match
171 * @vendor: vendor string
172 *
173 * Returns true if @vendor is in @edid, false otherwise
174 */
175static bool edid_vendor(struct edid *edid, char *vendor)
176{
177 char edid_vendor[3];
178
179 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
180 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
181 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
16456c87 182 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
f453ba04
DA		 183
184 return !strncmp(edid_vendor, vendor, 3);
185}
186
187/**
188 * edid_get_quirks - return quirk flags for a given EDID
189 * @edid: EDID to process
190 *
191 * This tells subsequent routines what fixes they need to apply.
192 */
193static u32 edid_get_quirks(struct edid *edid)
194{
195 struct edid_quirk *quirk;
196 int i;
197
198 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
199 quirk = &edid_quirk_list[i];
200
201 if (edid_vendor(edid, quirk->vendor) &&
202 (EDID_PRODUCT_ID(edid) == quirk->product_id))
203 return quirk->quirks;
204 }
205
206 return 0;
207}
208
209#define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
210#define MODE_REFRESH_DIFF(m,r) (abs((m)->vrefresh - target_refresh))
211
212
213/**
214 * edid_fixup_preferred - set preferred modes based on quirk list
215 * @connector: has mode list to fix up
216 * @quirks: quirks list
217 *
218 * Walk the mode list for @connector, clearing the preferred status
219 * on existing modes and setting it anew for the right mode ala @quirks.
220 */
221static void edid_fixup_preferred(struct drm_connector *connector,
222 u32 quirks)
223{
224 struct drm_display_mode *t, *cur_mode, *preferred_mode;
f890607b 225 int target_refresh = 0;
f453ba04
DA		 226
227 if (list_empty(&connector->probed_modes))
228 return;
229
230 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
231 target_refresh = 60;
232 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
233 target_refresh = 75;
234
235 preferred_mode = list_first_entry(&connector->probed_modes,
236 struct drm_display_mode, head);
237
238 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
239 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
240
241 if (cur_mode == preferred_mode)
242 continue;
243
244 /* Largest mode is preferred */
245 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
246 preferred_mode = cur_mode;
247
248 /* At a given size, try to get closest to target refresh */
249 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
250 MODE_REFRESH_DIFF(cur_mode, target_refresh) <
251 MODE_REFRESH_DIFF(preferred_mode, target_refresh)) {
252 preferred_mode = cur_mode;
253 }
254 }
255
256 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
257}
258
aa9eaa1f
ZY		 259/*
260 * Add the Autogenerated from the DMT spec.
261 * This table is copied from xfree86/modes/xf86EdidModes.c.
262 * But the mode with Reduced blank feature is deleted.
263 */
264static struct drm_display_mode drm_dmt_modes[] = {
265 /* 640x350@85Hz */
266 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
267 736, 832, 0, 350, 382, 385, 445, 0,
268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
269 /* 640x400@85Hz */
270 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
271 736, 832, 0, 400, 401, 404, 445, 0,
272 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
273 /* 720x400@85Hz */
274 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
275 828, 936, 0, 400, 401, 404, 446, 0,
276 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
277 /* 640x480@60Hz */
278 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
279 752, 800, 0, 480, 489, 492, 525, 0,
280 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
281 /* 640x480@72Hz */
282 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
283 704, 832, 0, 480, 489, 492, 520, 0,
284 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
285 /* 640x480@75Hz */
286 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
287 720, 840, 0, 480, 481, 484, 500, 0,
288 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
289 /* 640x480@85Hz */
290 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
291 752, 832, 0, 480, 481, 484, 509, 0,
292 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
293 /* 800x600@56Hz */
294 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
295 896, 1024, 0, 600, 601, 603, 625, 0,
296 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
297 /* 800x600@60Hz */
298 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
299 968, 1056, 0, 600, 601, 605, 628, 0,
300 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
301 /* 800x600@72Hz */
302 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
303 976, 1040, 0, 600, 637, 643, 666, 0,
304 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
305 /* 800x600@75Hz */
306 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
307 896, 1056, 0, 600, 601, 604, 625, 0,
308 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
309 /* 800x600@85Hz */
310 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
311 896, 1048, 0, 600, 601, 604, 631, 0,
312 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
313 /* 848x480@60Hz */
314 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
315 976, 1088, 0, 480, 486, 494, 517, 0,
316 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
317 /* 1024x768@43Hz, interlace */
318 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
319 1208, 1264, 0, 768, 768, 772, 817, 0,
320 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
321 DRM_MODE_FLAG_INTERLACE) },
322 /* 1024x768@60Hz */
323 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
324 1184, 1344, 0, 768, 771, 777, 806, 0,
325 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
326 /* 1024x768@70Hz */
327 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
328 1184, 1328, 0, 768, 771, 777, 806, 0,
329 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
330 /* 1024x768@75Hz */
331 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
332 1136, 1312, 0, 768, 769, 772, 800, 0,
333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
334 /* 1024x768@85Hz */
335 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
336 1072, 1376, 0, 768, 769, 772, 808, 0,
337 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
338 /* 1152x864@75Hz */
339 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
340 1344, 1600, 0, 864, 865, 868, 900, 0,
341 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
342 /* 1280x768@60Hz */
343 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
344 1472, 1664, 0, 768, 771, 778, 798, 0,
345 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
346 /* 1280x768@75Hz */
347 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
348 1488, 1696, 0, 768, 771, 778, 805, 0,
349 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
350 /* 1280x768@85Hz */
351 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
352 1496, 1712, 0, 768, 771, 778, 809, 0,
353 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
354 /* 1280x800@60Hz */
355 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
356 1480, 1680, 0, 800, 803, 809, 831, 0,
357 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
358 /* 1280x800@75Hz */
359 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
360 1488, 1696, 0, 800, 803, 809, 838, 0,
361 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
362 /* 1280x800@85Hz */
363 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
364 1496, 1712, 0, 800, 803, 809, 843, 0,
365 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
366 /* 1280x960@60Hz */
367 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
368 1488, 1800, 0, 960, 961, 964, 1000, 0,
369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
370 /* 1280x960@85Hz */
371 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
372 1504, 1728, 0, 960, 961, 964, 1011, 0,
373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
374 /* 1280x1024@60Hz */
375 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
376 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
378 /* 1280x1024@75Hz */
379 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
380 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
381 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
382 /* 1280x1024@85Hz */
383 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
384 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
386 /* 1360x768@60Hz */
387 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
388 1536, 1792, 0, 768, 771, 777, 795, 0,
389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
390 /* 1440x1050@60Hz */
391 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
392 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
393 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
394 /* 1440x1050@75Hz */
395 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
396 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
397 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
398 /* 1440x1050@85Hz */
399 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
400 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
401 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
402 /* 1440x900@60Hz */
403 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
404 1672, 1904, 0, 900, 903, 909, 934, 0,
405 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
406 /* 1440x900@75Hz */
407 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
408 1688, 1936, 0, 900, 903, 909, 942, 0,
409 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
410 /* 1440x900@85Hz */
411 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
412 1696, 1952, 0, 900, 903, 909, 948, 0,
413 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
414 /* 1600x1200@60Hz */
415 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
416 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
417 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
418 /* 1600x1200@65Hz */
419 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
420 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
421 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
422 /* 1600x1200@70Hz */
423 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
424 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
425 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
426 /* 1600x1200@75Hz */
427 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 2025000, 1600, 1664,
428 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
429 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
430 /* 1600x1200@85Hz */
431 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
432 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
433 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
434 /* 1680x1050@60Hz */
435 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
436 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
437 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
438 /* 1680x1050@75Hz */
439 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
440 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
441 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
442 /* 1680x1050@85Hz */
443 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
444 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
445 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
446 /* 1792x1344@60Hz */
447 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
448 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
449 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
450 /* 1729x1344@75Hz */
451 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
452 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
453 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
454 /* 1853x1392@60Hz */
455 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
456 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
457 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
458 /* 1856x1392@75Hz */
459 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
460 2208, 2560, 0, 1392, 1395, 1399, 1500, 0,
461 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
462 /* 1920x1200@60Hz */
463 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
464 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
465 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
466 /* 1920x1200@75Hz */
467 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
468 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
469 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
470 /* 1920x1200@85Hz */
471 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
472 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
473 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
474 /* 1920x1440@60Hz */
475 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
476 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
477 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
478 /* 1920x1440@75Hz */
479 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
480 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
481 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
482 /* 2560x1600@60Hz */
483 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
484 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
485 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
486 /* 2560x1600@75HZ */
487 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
488 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
489 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
490 /* 2560x1600@85HZ */
491 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
492 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
493 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
494};
07a5e632
AJ		 495static const int drm_num_dmt_modes =
496 sizeof(drm_dmt_modes) / sizeof(struct drm_display_mode);
aa9eaa1f 497
559ee21d
ZY		 498static struct drm_display_mode *drm_find_dmt(struct drm_device *dev,
499 int hsize, int vsize, int fresh)
500{
07a5e632 501 int i;
559ee21d
ZY		 502 struct drm_display_mode *ptr, *mode;
503
559ee21d 504 mode = NULL;
07a5e632 505 for (i = 0; i < drm_num_dmt_modes; i++) {
559ee21d
ZY		 506 ptr = &drm_dmt_modes[i];
507 if (hsize == ptr->hdisplay &&
508 vsize == ptr->vdisplay &&
509 fresh == drm_mode_vrefresh(ptr)) {
510 /* get the expected default mode */
511 mode = drm_mode_duplicate(dev, ptr);
512 break;
513 }
514 }
515 return mode;
516}
23425cae
AJ		 517
518/*
519 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
520 * monitors fill with ascii space (0x20) instead.
521 */
522static int
523bad_std_timing(u8 a, u8 b)
524{
525 return (a == 0x00 && b == 0x00) ||
526 (a == 0x01 && b == 0x01) ||
527 (a == 0x20 && b == 0x20);
528}
529
f453ba04
DA		 530/**
531 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
532 * @t: standard timing params
5c61259e 533 * @timing_level: standard timing level
f453ba04
DA		 534 *
535 * Take the standard timing params (in this case width, aspect, and refresh)
5c61259e 536 * and convert them into a real mode using CVT/GTF/DMT.
f453ba04
DA		 537 *
538 * Punts for now, but should eventually use the FB layer's CVT based mode
539 * generation code.
540 */
541struct drm_display_mode *drm_mode_std(struct drm_device *dev,
5c61259e 542 struct std_timing *t,
f066a17d 543 int revision,
5c61259e 544 int timing_level)
f453ba04
DA		 545{
546 struct drm_display_mode *mode;
5c61259e
ZY		 547 int hsize, vsize;
548 int vrefresh_rate;
0454beab
MD		 549 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
550 >> EDID_TIMING_ASPECT_SHIFT;
5c61259e
ZY		 551 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
552 >> EDID_TIMING_VFREQ_SHIFT;
553
23425cae
AJ		 554 if (bad_std_timing(t->hsize, t->vfreq_aspect))
555 return NULL;
556
5c61259e
ZY		 557 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
558 hsize = t->hsize * 8 + 248;
559 /* vrefresh_rate = vfreq + 60 */
560 vrefresh_rate = vfreq + 60;
561 /* the vdisplay is calculated based on the aspect ratio */
f066a17d
AJ		 562 if (aspect_ratio == 0) {
563 if (revision < 3)
564 vsize = hsize;
565 else
566 vsize = (hsize * 10) / 16;
567 } else if (aspect_ratio == 1)
f453ba04 568 vsize = (hsize * 3) / 4;
0454beab 569 else if (aspect_ratio == 2)
f453ba04
DA		 570 vsize = (hsize * 4) / 5;
571 else
572 vsize = (hsize * 9) / 16;
559ee21d
ZY		 573 /* HDTV hack */
574 if (hsize == 1360 && vsize == 765 && vrefresh_rate == 60) {
d50ba256
DA		 575 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
576 false);
559ee21d
ZY		 577 mode->hdisplay = 1366;
578 mode->vsync_start = mode->vsync_start - 1;
579 mode->vsync_end = mode->vsync_end - 1;
580 return mode;
581 }
5c61259e 582 mode = NULL;
559ee21d
ZY		 583 /* check whether it can be found in default mode table */
584 mode = drm_find_dmt(dev, hsize, vsize, vrefresh_rate);
585 if (mode)
586 return mode;
587
5c61259e
ZY		 588 switch (timing_level) {
589 case LEVEL_DMT:
5c61259e
ZY		 590 break;
591 case LEVEL_GTF:
592 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
593 break;
594 case LEVEL_CVT:
d50ba256
DA		 595 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
596 false);
5c61259e
ZY		 597 break;
598 }
f453ba04
DA		 599 return mode;
600}
601
b58db2c6
AJ		 602/*
603 * EDID is delightfully ambiguous about how interlaced modes are to be
604 * encoded. Our internal representation is of frame height, but some
605 * HDTV detailed timings are encoded as field height.
606 *
607 * The format list here is from CEA, in frame size. Technically we
608 * should be checking refresh rate too. Whatever.
609 */
610static void
611drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
612 struct detailed_pixel_timing *pt)
613{
614 int i;
615 static const struct {
616 int w, h;
617 } cea_interlaced[] = {
618 { 1920, 1080 },
619 { 720, 480 },
620 { 1440, 480 },
621 { 2880, 480 },
622 { 720, 576 },
623 { 1440, 576 },
624 { 2880, 576 },
625 };
626 static const int n_sizes =
627 sizeof(cea_interlaced)/sizeof(cea_interlaced[0]);
628
629 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
630 return;
631
632 for (i = 0; i < n_sizes; i++) {
633 if ((mode->hdisplay == cea_interlaced[i].w) &&
634 (mode->vdisplay == cea_interlaced[i].h / 2)) {
635 mode->vdisplay *= 2;
636 mode->vsync_start *= 2;
637 mode->vsync_end *= 2;
638 mode->vtotal *= 2;
639 mode->vtotal |= 1;
640 }
641 }
642
643 mode->flags |= DRM_MODE_FLAG_INTERLACE;
644}
645
f453ba04
DA		 646/**
647 * drm_mode_detailed - create a new mode from an EDID detailed timing section
648 * @dev: DRM device (needed to create new mode)
649 * @edid: EDID block
650 * @timing: EDID detailed timing info
651 * @quirks: quirks to apply
652 *
653 * An EDID detailed timing block contains enough info for us to create and
654 * return a new struct drm_display_mode.
655 */
656static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
657 struct edid *edid,
658 struct detailed_timing *timing,
659 u32 quirks)
660{
661 struct drm_display_mode *mode;
662 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
0454beab
MD		 663 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
664 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
665 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
666 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
e14cbee4
MD		 667 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
668 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
669 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) >> 2 | pt->vsync_offset_pulse_width_lo >> 4;
670 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
f453ba04 671
fc438966 672 /* ignore tiny modes */
0454beab 673 if (hactive < 64 || vactive < 64)
fc438966
AJ		 674 return NULL;
675
0454beab 676 if (pt->misc & DRM_EDID_PT_STEREO) {
f453ba04
DA		 677 printk(KERN_WARNING "stereo mode not supported\n");
678 return NULL;
679 }
0454beab 680 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
79b7dcb2 681 printk(KERN_WARNING "composite sync not supported\n");
f453ba04
DA		 682 }
683
fcb45611
ZY		 684 /* it is incorrect if hsync/vsync width is zero */
685 if (!hsync_pulse_width || !vsync_pulse_width) {
686 DRM_DEBUG_KMS("Incorrect Detailed timing. "
687 "Wrong Hsync/Vsync pulse width\n");
688 return NULL;
689 }
f453ba04
DA		 690 mode = drm_mode_create(dev);
691 if (!mode)
692 return NULL;
693
694 mode->type = DRM_MODE_TYPE_DRIVER;
695
696 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
0454beab
MD		 697 timing->pixel_clock = cpu_to_le16(1088);
698
699 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
700
701 mode->hdisplay = hactive;
702 mode->hsync_start = mode->hdisplay + hsync_offset;
703 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
704 mode->htotal = mode->hdisplay + hblank;
705
706 mode->vdisplay = vactive;
707 mode->vsync_start = mode->vdisplay + vsync_offset;
708 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
709 mode->vtotal = mode->vdisplay + vblank;
f453ba04 710
7064fef5
JB		 711 /* Some EDIDs have bogus h/vtotal values */
712 if (mode->hsync_end > mode->htotal)
713 mode->htotal = mode->hsync_end + 1;
714 if (mode->vsync_end > mode->vtotal)
715 mode->vtotal = mode->vsync_end + 1;
716
f453ba04
DA		 717 drm_mode_set_name(mode);
718
b58db2c6 719 drm_mode_do_interlace_quirk(mode, pt);
f453ba04
DA		 720
721 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
0454beab 722 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
f453ba04
DA		 723 }
724
0454beab
MD		 725 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
726 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
727 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
728 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
f453ba04 729
e14cbee4
MD		 730 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
731 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
f453ba04
DA		 732
733 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
734 mode->width_mm *= 10;
735 mode->height_mm *= 10;
736 }
737
738 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
739 mode->width_mm = edid->width_cm * 10;
740 mode->height_mm = edid->height_cm * 10;
741 }
742
743 return mode;
744}
745
746/*
747 * Detailed mode info for the EDID "established modes" data to use.
748 */
749static struct drm_display_mode edid_est_modes[] = {
750 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
751 968, 1056, 0, 600, 601, 605, 628, 0,
752 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
753 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
754 896, 1024, 0, 600, 601, 603, 625, 0,
755 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
756 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
757 720, 840, 0, 480, 481, 484, 500, 0,
758 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
759 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
760 704, 832, 0, 480, 489, 491, 520, 0,
761 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
762 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
763 768, 864, 0, 480, 483, 486, 525, 0,
764 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
765 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25200, 640, 656,
766 752, 800, 0, 480, 490, 492, 525, 0,
767 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
768 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
769 846, 900, 0, 400, 421, 423, 449, 0,
770 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
771 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
772 846, 900, 0, 400, 412, 414, 449, 0,
773 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
774 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
775 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
776 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
777 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78800, 1024, 1040,
778 1136, 1312, 0, 768, 769, 772, 800, 0,
779 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
780 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
781 1184, 1328, 0, 768, 771, 777, 806, 0,
782 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
783 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
784 1184, 1344, 0, 768, 771, 777, 806, 0,
785 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
786 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
787 1208, 1264, 0, 768, 768, 776, 817, 0,
788 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
789 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
790 928, 1152, 0, 624, 625, 628, 667, 0,
791 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
792 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
793 896, 1056, 0, 600, 601, 604, 625, 0,
794 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
795 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
796 976, 1040, 0, 600, 637, 643, 666, 0,
797 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
798 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
799 1344, 1600, 0, 864, 865, 868, 900, 0,
800 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
801};
802
803#define EDID_EST_TIMINGS 16
804#define EDID_STD_TIMINGS 8
805#define EDID_DETAILED_TIMINGS 4
806
807/**
808 * add_established_modes - get est. modes from EDID and add them
809 * @edid: EDID block to scan
810 *
811 * Each EDID block contains a bitmap of the supported "established modes" list
812 * (defined above). Tease them out and add them to the global modes list.
813 */
814static int add_established_modes(struct drm_connector *connector, struct edid *edid)
815{
816 struct drm_device *dev = connector->dev;
817 unsigned long est_bits = edid->established_timings.t1 |
818 (edid->established_timings.t2 << 8) |
819 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
820 int i, modes = 0;
821
822 for (i = 0; i <= EDID_EST_TIMINGS; i++)
823 if (est_bits & (1<<i)) {
824 struct drm_display_mode *newmode;
825 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
826 if (newmode) {
827 drm_mode_probed_add(connector, newmode);
828 modes++;
829 }
830 }
831
832 return modes;
833}
5c61259e
ZY		 834/**
835 * stanard_timing_level - get std. timing level(CVT/GTF/DMT)
836 * @edid: EDID block to scan
837 */
838static int standard_timing_level(struct edid *edid)
839{
840 if (edid->revision >= 2) {
841 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
842 return LEVEL_CVT;
843 return LEVEL_GTF;
844 }
845 return LEVEL_DMT;
846}
f453ba04
DA		 847
848/**
849 * add_standard_modes - get std. modes from EDID and add them
850 * @edid: EDID block to scan
851 *
852 * Standard modes can be calculated using the CVT standard. Grab them from
853 * @edid, calculate them, and add them to the list.
854 */
855static int add_standard_modes(struct drm_connector *connector, struct edid *edid)
856{
857 struct drm_device *dev = connector->dev;
858 int i, modes = 0;
5c61259e
ZY		 859 int timing_level;
860
861 timing_level = standard_timing_level(edid);
f453ba04
DA		 862
863 for (i = 0; i < EDID_STD_TIMINGS; i++) {
864 struct std_timing *t = &edid->standard_timings[i];
865 struct drm_display_mode *newmode;
866
867 /* If std timings bytes are 1, 1 it's empty */
0454beab 868 if (t->hsize == 1 && t->vfreq_aspect == 1)
f453ba04
DA		 869 continue;
870
5c61259e 871 newmode = drm_mode_std(dev, &edid->standard_timings[i],
f066a17d 872 edid->revision, timing_level);
f453ba04
DA		 873 if (newmode) {
874 drm_mode_probed_add(connector, newmode);
875 modes++;
876 }
877 }
878
879 return modes;
880}
881
07a5e632
AJ		 882/*
883 * XXX fix this for:
884 * - GTF secondary curve formula
885 * - EDID 1.4 range offsets
886 * - CVT extended bits
887 */
888static bool
889mode_in_range(struct drm_display_mode *mode, struct detailed_timing *timing)
890{
891 struct detailed_data_monitor_range *range;
892 int hsync, vrefresh;
893
894 range = &timing->data.other_data.data.range;
895
896 hsync = drm_mode_hsync(mode);
897 vrefresh = drm_mode_vrefresh(mode);
898
899 if (hsync < range->min_hfreq_khz || hsync > range->max_hfreq_khz)
900 return false;
901
902 if (vrefresh < range->min_vfreq || vrefresh > range->max_vfreq)
903 return false;
904
905 if (range->pixel_clock_mhz && range->pixel_clock_mhz != 0xff) {
906 /* be forgiving since it's in units of 10MHz */
907 int max_clock = range->pixel_clock_mhz * 10 + 9;
908 max_clock *= 1000;
909 if (mode->clock > max_clock)
910 return false;
911 }
912
913 return true;
914}
915
916/*
917 * XXX If drm_dmt_modes ever regrows the CVT-R modes (and it will) this will
918 * need to account for them.
919 */
920static int drm_gtf_modes_for_range(struct drm_connector *connector,
921 struct detailed_timing *timing)
922{
923 int i, modes = 0;
924 struct drm_display_mode *newmode;
925 struct drm_device *dev = connector->dev;
926
927 for (i = 0; i < drm_num_dmt_modes; i++) {
928 if (mode_in_range(drm_dmt_modes + i, timing)) {
929 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
930 if (newmode) {
931 drm_mode_probed_add(connector, newmode);
932 modes++;
933 }
934 }
935 }
936
937 return modes;
938}
939
9340d8cf
AJ		 940static int drm_cvt_modes(struct drm_connector *connector,
941 struct detailed_timing *timing)
942{
943 int i, j, modes = 0;
944 struct drm_display_mode *newmode;
945 struct drm_device *dev = connector->dev;
946 struct cvt_timing *cvt;
947 const int rates[] = { 60, 85, 75, 60, 50 };
69da3015 948 const u8 empty[3] = { 0, 0, 0 };
9340d8cf
AJ		 949
950 for (i = 0; i < 4; i++) {
29ebdf92 951 int uninitialized_var(width), height;
9340d8cf
AJ		 952 cvt = &(timing->data.other_data.data.cvt[i]);
953
69da3015
AJ		 954 if (!memcmp(cvt->code, empty, 3))
955 continue;
956
8e10ee9a
AJ		 957 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
958 switch (cvt->code[1] & 0x0c) {
9340d8cf
AJ		 959 case 0x00:
960 width = height * 4 / 3;
961 break;
8e10ee9a 962 case 0x04:
9340d8cf
AJ		 963 width = height * 16 / 9;
964 break;
8e10ee9a 965 case 0x08:
9340d8cf
AJ		 966 width = height * 16 / 10;
967 break;
8e10ee9a 968 case 0x0c:
9340d8cf
AJ		 969 width = height * 15 / 9;
970 break;
971 }
972
973 for (j = 1; j < 5; j++) {
974 if (cvt->code[2] & (1 << j)) {
975 newmode = drm_cvt_mode(dev, width, height,
976 rates[j], j == 0,
977 false, false);
978 if (newmode) {
979 drm_mode_probed_add(connector, newmode);
980 modes++;
981 }
982 }
983 }
984 }
985
986 return modes;
987}
988
9cf00977
AJ		 989static int add_detailed_modes(struct drm_connector *connector,
990 struct detailed_timing *timing,
991 struct edid *edid, u32 quirks, int preferred)
992{
993 int i, modes = 0;
994 struct detailed_non_pixel *data = &timing->data.other_data;
995 int timing_level = standard_timing_level(edid);
07a5e632 996 int gtf = (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF);
9cf00977
AJ		 997 struct drm_display_mode *newmode;
998 struct drm_device *dev = connector->dev;
999
1000 if (timing->pixel_clock) {
1001 newmode = drm_mode_detailed(dev, edid, timing, quirks);
1002 if (!newmode)
1003 return 0;
1004
1005 if (preferred)
1006 newmode->type |= DRM_MODE_TYPE_PREFERRED;
1007
1008 drm_mode_probed_add(connector, newmode);
1009 return 1;
1010 }
1011
1012 /* other timing types */
1013 switch (data->type) {
1014 case EDID_DETAIL_MONITOR_RANGE:
07a5e632
AJ		 1015 if (gtf)
1016 modes += drm_gtf_modes_for_range(connector, timing);
9cf00977
AJ		 1017 break;
1018 case EDID_DETAIL_STD_MODES:
1019 /* Six modes per detailed section */
1020 for (i = 0; i < 6; i++) {
1021 struct std_timing *std;
1022 struct drm_display_mode *newmode;
1023
1024 std = &data->data.timings[i];
1025 newmode = drm_mode_std(dev, std, edid->revision,
1026 timing_level);
1027 if (newmode) {
1028 drm_mode_probed_add(connector, newmode);
1029 modes++;
1030 }
1031 }
1032 break;
9340d8cf
AJ		 1033 case EDID_DETAIL_CVT_3BYTE:
1034 modes += drm_cvt_modes(connector, timing);
1035 break;
9cf00977
AJ		 1036 default:
1037 break;
1038 }
1039
1040 return modes;
1041}
1042
f453ba04 1043/**
9cf00977 1044 * add_detailed_info - get detailed mode info from EDID data
f453ba04
DA		 1045 * @connector: attached connector
1046 * @edid: EDID block to scan
1047 * @quirks: quirks to apply
1048 *
1049 * Some of the detailed timing sections may contain mode information. Grab
1050 * it and add it to the list.
1051 */
1052static int add_detailed_info(struct drm_connector *connector,
1053 struct edid *edid, u32 quirks)
1054{
9cf00977 1055 int i, modes = 0;
f453ba04
DA		 1056
1057 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) {
1058 struct detailed_timing *timing = &edid->detailed_timings[i];
9cf00977 1059 int preferred = (i == 0) && (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
f453ba04 1060
9cf00977
AJ		 1061 /* In 1.0, only timings are allowed */
1062 if (!timing->pixel_clock && edid->version == 1 &&
1063 edid->revision == 0)
1064 continue;
f453ba04 1065
9cf00977
AJ		 1066 modes += add_detailed_modes(connector, timing, edid, quirks,
1067 preferred);
f453ba04
DA		 1068 }
1069
1070 return modes;
1071}
9cf00977 1072
882f0219
ZY		 1073/**
1074 * add_detailed_mode_eedid - get detailed mode info from addtional timing
1075 * EDID block
1076 * @connector: attached connector
1077 * @edid: EDID block to scan(It is only to get addtional timing EDID block)
1078 * @quirks: quirks to apply
1079 *
1080 * Some of the detailed timing sections may contain mode information. Grab
1081 * it and add it to the list.
1082 */
1083static int add_detailed_info_eedid(struct drm_connector *connector,
1084 struct edid *edid, u32 quirks)
1085{
9cf00977 1086 int i, modes = 0;
882f0219
ZY		 1087 char *edid_ext = NULL;
1088 struct detailed_timing *timing;
882f0219
ZY		 1089 int edid_ext_num;
1090 int start_offset, end_offset;
1091 int timing_level;
1092
1093 if (edid->version == 1 && edid->revision < 3) {
1094 /* If the EDID version is less than 1.3, there is no
1095 * extension EDID.
1096 */
1097 return 0;
1098 }
1099 if (!edid->extensions) {
1100 /* if there is no extension EDID, it is unnecessary to
1101 * parse the E-EDID to get detailed info
1102 */
1103 return 0;
1104 }
1105
1106 /* Chose real EDID extension number */
3c537889
AD		 1107 edid_ext_num = edid->extensions > DRM_MAX_EDID_EXT_NUM ?
1108 DRM_MAX_EDID_EXT_NUM : edid->extensions;
882f0219
ZY		 1109
1110 /* Find CEA extension */
1111 for (i = 0; i < edid_ext_num; i++) {
1112 edid_ext = (char *)edid + EDID_LENGTH * (i + 1);
1113 /* This block is CEA extension */
1114 if (edid_ext[0] == 0x02)
1115 break;
1116 }
1117
1118 if (i == edid_ext_num) {
1119 /* if there is no additional timing EDID block, return */
1120 return 0;
1121 }
1122
1123 /* Get the start offset of detailed timing block */
1124 start_offset = edid_ext[2];
1125 if (start_offset == 0) {
1126 /* If the start_offset is zero, it means that neither detailed
1127 * info nor data block exist. In such case it is also
1128 * unnecessary to parse the detailed timing info.
1129 */
1130 return 0;
1131 }
1132
1133 timing_level = standard_timing_level(edid);
1134 end_offset = EDID_LENGTH;
1135 end_offset -= sizeof(struct detailed_timing);
1136 for (i = start_offset; i < end_offset;
1137 i += sizeof(struct detailed_timing)) {
1138 timing = (struct detailed_timing *)(edid_ext + i);
9cf00977 1139 modes += add_detailed_modes(connector, timing, edid, quirks, 0);
882f0219
ZY		 1140 }
1141
1142 return modes;
1143}
f453ba04
DA		 1144
1145#define DDC_ADDR 0x50
167f3a04
ML		 1146/**
1147 * Get EDID information via I2C.
1148 *
1149 * \param adapter : i2c device adaptor
1150 * \param buf : EDID data buffer to be filled
1151 * \param len : EDID data buffer length
1152 * \return 0 on success or -1 on failure.
1153 *
1154 * Try to fetch EDID information by calling i2c driver function.
1155 */
1156int drm_do_probe_ddc_edid(struct i2c_adapter *adapter,
1157 unsigned char *buf, int len)
f453ba04
DA		 1158{
1159 unsigned char start = 0x0;
f453ba04
DA		 1160 struct i2c_msg msgs[] = {
1161 {
1162 .addr = DDC_ADDR,
1163 .flags = 0,
1164 .len = 1,
1165 .buf = &start,
1166 }, {
1167 .addr = DDC_ADDR,
1168 .flags = I2C_M_RD,
167f3a04 1169 .len = len,
f453ba04
DA		 1170 .buf = buf,
1171 }
1172 };
1173
f453ba04 1174 if (i2c_transfer(adapter, msgs, 2) == 2)
167f3a04 1175 return 0;
f453ba04 1176
167f3a04 1177 return -1;
f453ba04
DA		 1178}
1179EXPORT_SYMBOL(drm_do_probe_ddc_edid);
1180
167f3a04
ML		 1181static int drm_ddc_read_edid(struct drm_connector *connector,
1182 struct i2c_adapter *adapter,
1183 char *buf, int len)
1184{
47ee4ccf 1185 int i;
167f3a04 1186
47ee4ccf
AJ		 1187 for (i = 0; i < 4; i++) {
1188 if (drm_do_probe_ddc_edid(adapter, buf, len))
1189 return -1;
3c537889 1190 if (drm_edid_is_valid((struct edid *)buf))
47ee4ccf 1191 return 0;
167f3a04 1192 }
47ee4ccf
AJ		 1193
1194 /* repeated checksum failures; warn, but carry on */
1195 dev_warn(&connector->dev->pdev->dev, "%s: EDID invalid.\n",
1196 drm_get_connector_name(connector));
1197 return -1;
f453ba04
DA		 1198}
1199
1200/**
1201 * drm_get_edid - get EDID data, if available
1202 * @connector: connector we're probing
1203 * @adapter: i2c adapter to use for DDC
1204 *
1205 * Poke the given connector's i2c channel to grab EDID data if possible.
1206 *
1207 * Return edid data or NULL if we couldn't find any.
1208 */
1209struct edid *drm_get_edid(struct drm_connector *connector,
1210 struct i2c_adapter *adapter)
1211{
167f3a04 1212 int ret;
f453ba04
DA		 1213 struct edid *edid;
1214
3c537889 1215 edid = kmalloc(EDID_LENGTH * (DRM_MAX_EDID_EXT_NUM + 1),
167f3a04
ML		 1216 GFP_KERNEL);
1217 if (edid == NULL) {
1218 dev_warn(&connector->dev->pdev->dev,
1219 "Failed to allocate EDID\n");
1220 goto end;
f453ba04 1221 }
167f3a04
ML		 1222
1223 /* Read first EDID block */
1224 ret = drm_ddc_read_edid(connector, adapter,
1225 (unsigned char *)edid, EDID_LENGTH);
1226 if (ret != 0)
1227 goto clean_up;
1228
1229 /* There are EDID extensions to be read */
1230 if (edid->extensions != 0) {
1231 int edid_ext_num = edid->extensions;
1232
3c537889 1233 if (edid_ext_num > DRM_MAX_EDID_EXT_NUM) {
167f3a04
ML		 1234 dev_warn(&connector->dev->pdev->dev,
1235 "The number of extension(%d) is "
1236 "over max (%d), actually read number (%d)\n",
3c537889
AD		 1237 edid_ext_num, DRM_MAX_EDID_EXT_NUM,
1238 DRM_MAX_EDID_EXT_NUM);
167f3a04 1239 /* Reset EDID extension number to be read */
3c537889 1240 edid_ext_num = DRM_MAX_EDID_EXT_NUM;
167f3a04
ML		 1241 }
1242 /* Read EDID including extensions too */
1243 ret = drm_ddc_read_edid(connector, adapter, (char *)edid,
1244 EDID_LENGTH * (edid_ext_num + 1));
1245 if (ret != 0)
1246 goto clean_up;
1247
f453ba04
DA		 1248 }
1249
1250 connector->display_info.raw_edid = (char *)edid;
167f3a04 1251 goto end;
f453ba04 1252
167f3a04
ML		 1253clean_up:
1254 kfree(edid);
1255 edid = NULL;
1256end:
f453ba04 1257 return edid;
167f3a04 1258
f453ba04
DA		 1259}
1260EXPORT_SYMBOL(drm_get_edid);
1261
f23c20c8
ML		 1262#define HDMI_IDENTIFIER 0x000C03
1263#define VENDOR_BLOCK 0x03
1264/**
1265 * drm_detect_hdmi_monitor - detect whether monitor is hdmi.
1266 * @edid: monitor EDID information
1267 *
1268 * Parse the CEA extension according to CEA-861-B.
1269 * Return true if HDMI, false if not or unknown.
1270 */
1271bool drm_detect_hdmi_monitor(struct edid *edid)
1272{
1273 char *edid_ext = NULL;
1274 int i, hdmi_id, edid_ext_num;
1275 int start_offset, end_offset;
1276 bool is_hdmi = false;
1277
1278 /* No EDID or EDID extensions */
1279 if (edid == NULL || edid->extensions == 0)
1280 goto end;
1281
1282 /* Chose real EDID extension number */
3c537889
AD		 1283 edid_ext_num = edid->extensions > DRM_MAX_EDID_EXT_NUM ?
1284 DRM_MAX_EDID_EXT_NUM : edid->extensions;
f23c20c8
ML		 1285
1286 /* Find CEA extension */
1287 for (i = 0; i < edid_ext_num; i++) {
1288 edid_ext = (char *)edid + EDID_LENGTH * (i + 1);
1289 /* This block is CEA extension */
1290 if (edid_ext[0] == 0x02)
1291 break;
1292 }
1293
1294 if (i == edid_ext_num)
1295 goto end;
1296
1297 /* Data block offset in CEA extension block */
1298 start_offset = 4;
1299 end_offset = edid_ext[2];
1300
1301 /*
1302 * Because HDMI identifier is in Vendor Specific Block,
1303 * search it from all data blocks of CEA extension.
1304 */
1305 for (i = start_offset; i < end_offset;
1306 /* Increased by data block len */
1307 i += ((edid_ext[i] & 0x1f) + 1)) {
1308 /* Find vendor specific block */
1309 if ((edid_ext[i] >> 5) == VENDOR_BLOCK) {
1310 hdmi_id = edid_ext[i + 1] | (edid_ext[i + 2] << 8) |
1311 edid_ext[i + 3] << 16;
1312 /* Find HDMI identifier */
1313 if (hdmi_id == HDMI_IDENTIFIER)
1314 is_hdmi = true;
1315 break;
1316 }
1317 }
1318
1319end:
1320 return is_hdmi;
1321}
1322EXPORT_SYMBOL(drm_detect_hdmi_monitor);
1323
f453ba04
DA		 1324/**
1325 * drm_add_edid_modes - add modes from EDID data, if available
1326 * @connector: connector we're probing
1327 * @edid: edid data
1328 *
1329 * Add the specified modes to the connector's mode list.
1330 *
1331 * Return number of modes added or 0 if we couldn't find any.
1332 */
1333int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
1334{
1335 int num_modes = 0;
1336 u32 quirks;
1337
1338 if (edid == NULL) {
1339 return 0;
1340 }
3c537889 1341 if (!drm_edid_is_valid(edid)) {
f453ba04
DA		 1342 dev_warn(&connector->dev->pdev->dev, "%s: EDID invalid.\n",
1343 drm_get_connector_name(connector));
1344 return 0;
1345 }
1346
1347 quirks = edid_get_quirks(edid);
1348
1349 num_modes += add_established_modes(connector, edid);
1350 num_modes += add_standard_modes(connector, edid);
1351 num_modes += add_detailed_info(connector, edid, quirks);
882f0219 1352 num_modes += add_detailed_info_eedid(connector, edid, quirks);
f453ba04
DA		 1353
1354 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
1355 edid_fixup_preferred(connector, quirks);
1356
0454beab
MD		 1357 connector->display_info.serration_vsync = (edid->input & DRM_EDID_INPUT_SERRATION_VSYNC) ? 1 : 0;
1358 connector->display_info.sync_on_green = (edid->input & DRM_EDID_INPUT_SYNC_ON_GREEN) ? 1 : 0;
1359 connector->display_info.composite_sync = (edid->input & DRM_EDID_INPUT_COMPOSITE_SYNC) ? 1 : 0;
1360 connector->display_info.separate_syncs = (edid->input & DRM_EDID_INPUT_SEPARATE_SYNCS) ? 1 : 0;
1361 connector->display_info.blank_to_black = (edid->input & DRM_EDID_INPUT_BLANK_TO_BLACK) ? 1 : 0;
1362 connector->display_info.video_level = (edid->input & DRM_EDID_INPUT_VIDEO_LEVEL) >> 5;
1363 connector->display_info.digital = (edid->input & DRM_EDID_INPUT_DIGITAL) ? 1 : 0;
f453ba04
DA		 1364 connector->display_info.width_mm = edid->width_cm * 10;
1365 connector->display_info.height_mm = edid->height_cm * 10;
1366 connector->display_info.gamma = edid->gamma;
0454beab
MD		 1367 connector->display_info.gtf_supported = (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) ? 1 : 0;
1368 connector->display_info.standard_color = (edid->features & DRM_EDID_FEATURE_STANDARD_COLOR) ? 1 : 0;
1369 connector->display_info.display_type = (edid->features & DRM_EDID_FEATURE_DISPLAY_TYPE) >> 3;
1370 connector->display_info.active_off_supported = (edid->features & DRM_EDID_FEATURE_PM_ACTIVE_OFF) ? 1 : 0;
1371 connector->display_info.suspend_supported = (edid->features & DRM_EDID_FEATURE_PM_SUSPEND) ? 1 : 0;
1372 connector->display_info.standby_supported = (edid->features & DRM_EDID_FEATURE_PM_STANDBY) ? 1 : 0;
f453ba04
DA		 1373 connector->display_info.gamma = edid->gamma;
1374
1375 return num_modes;
1376}
1377EXPORT_SYMBOL(drm_add_edid_modes);
f0fda0a4
ZY		 1378
1379/**
1380 * drm_add_modes_noedid - add modes for the connectors without EDID
1381 * @connector: connector we're probing
1382 * @hdisplay: the horizontal display limit
1383 * @vdisplay: the vertical display limit
1384 *
1385 * Add the specified modes to the connector's mode list. Only when the
1386 * hdisplay/vdisplay is not beyond the given limit, it will be added.
1387 *
1388 * Return number of modes added or 0 if we couldn't find any.
1389 */
1390int drm_add_modes_noedid(struct drm_connector *connector,
1391 int hdisplay, int vdisplay)
1392{
1393 int i, count, num_modes = 0;
1394 struct drm_display_mode *mode, *ptr;
1395 struct drm_device *dev = connector->dev;
1396
1397 count = sizeof(drm_dmt_modes) / sizeof(struct drm_display_mode);
1398 if (hdisplay < 0)
1399 hdisplay = 0;
1400 if (vdisplay < 0)
1401 vdisplay = 0;
1402
1403 for (i = 0; i < count; i++) {
1404 ptr = &drm_dmt_modes[i];
1405 if (hdisplay && vdisplay) {
1406 /*
1407 * Only when two are valid, they will be used to check
1408 * whether the mode should be added to the mode list of
1409 * the connector.
1410 */
1411 if (ptr->hdisplay > hdisplay ||
1412 ptr->vdisplay > vdisplay)
1413 continue;
1414 }
f985dedb
AJ		 1415 if (drm_mode_vrefresh(ptr) > 61)
1416 continue;
f0fda0a4
ZY		 1417 mode = drm_mode_duplicate(dev, ptr);
1418 if (mode) {
1419 drm_mode_probed_add(connector, mode);
1420 num_modes++;
1421 }
1422 }
1423 return num_modes;
1424}
1425EXPORT_SYMBOL(drm_add_modes_noedid);
Linux 6.x block layer and io_uring tree(s)