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drm/edid: parse sink information before CEA blocks
[linux-2.6-block.git] / drivers / gpu / drm / drm_edid.c
CommitLineData
f453ba04
DA		 1/*
2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
61e57a8d 5 * Copyright 2010 Red Hat, Inc.
f453ba04
DA		 6 *
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
8 * FB layer.
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 */
30#include <linux/kernel.h>
5a0e3ad6 31#include <linux/slab.h>
10a85120 32#include <linux/hdmi.h>
f453ba04 33#include <linux/i2c.h>
47819ba2 34#include <linux/module.h>
5cb8eaa2 35#include <linux/vga_switcheroo.h>
760285e7
DH		 36#include <drm/drmP.h>
37#include <drm/drm_edid.h>
9338203c 38#include <drm/drm_encoder.h>
40d9b043 39#include <drm/drm_displayid.h>
62c58af3 40#include <drm/drm_scdc_helper.h>
f453ba04 41
969218fe
TI		 42#include "drm_crtc_internal.h"
43
13931579
AJ		 44#define version_greater(edid, maj, min) \
45 (((edid)->version > (maj)) || \
46 ((edid)->version == (maj) && (edid)->revision > (min)))
f453ba04 47
d1ff6409
AJ		 48#define EDID_EST_TIMINGS 16
49#define EDID_STD_TIMINGS 8
50#define EDID_DETAILED_TIMINGS 4
f453ba04
DA		 51
52/*
53 * EDID blocks out in the wild have a variety of bugs, try to collect
54 * them here (note that userspace may work around broken monitors first,
55 * but fixes should make their way here so that the kernel "just works"
56 * on as many displays as possible).
57 */
58
59/* First detailed mode wrong, use largest 60Hz mode */
60#define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
61/* Reported 135MHz pixel clock is too high, needs adjustment */
62#define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
63/* Prefer the largest mode at 75 Hz */
64#define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
65/* Detail timing is in cm not mm */
66#define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
67/* Detailed timing descriptors have bogus size values, so just take the
68 * maximum size and use that.
69 */
70#define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
71/* Monitor forgot to set the first detailed is preferred bit. */
72#define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5)
73/* use +hsync +vsync for detailed mode */
74#define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
bc42aabc
AJ		 75/* Force reduced-blanking timings for detailed modes */
76#define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
49d45a31
RM		 77/* Force 8bpc */
78#define EDID_QUIRK_FORCE_8BPC (1 << 8)
bc5b9641
MK		 79/* Force 12bpc */
80#define EDID_QUIRK_FORCE_12BPC (1 << 9)
e10aec65
MK		 81/* Force 6bpc */
82#define EDID_QUIRK_FORCE_6BPC (1 << 10)
e345da82
MK		 83/* Force 10bpc */
84#define EDID_QUIRK_FORCE_10BPC (1 << 11)
3c537889 85
13931579
AJ		 86struct detailed_mode_closure {
87 struct drm_connector *connector;
88 struct edid *edid;
89 bool preferred;
90 u32 quirks;
91 int modes;
92};
f453ba04 93
5c61259e
ZY		 94#define LEVEL_DMT 0
95#define LEVEL_GTF 1
7a374350
AJ		 96#define LEVEL_GTF2 2
97#define LEVEL_CVT 3
5c61259e 98
23c4cfbd 99static const struct edid_quirk {
c51a3fd6 100 char vendor[4];
f453ba04
DA		 101 int product_id;
102 u32 quirks;
103} edid_quirk_list[] = {
104 /* Acer AL1706 */
105 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
106 /* Acer F51 */
107 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
108 /* Unknown Acer */
109 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
110
e10aec65
MK		 111 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
112 { "AEO", 0, EDID_QUIRK_FORCE_6BPC },
113
f453ba04
DA		 114 /* Belinea 10 15 55 */
115 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
116 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
117
118 /* Envision Peripherals, Inc. EN-7100e */
119 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
ba1163de
AJ		 120 /* Envision EN2028 */
121 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
f453ba04
DA		 122
123 /* Funai Electronics PM36B */
124 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
125 EDID_QUIRK_DETAILED_IN_CM },
126
e345da82
MK		 127 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
128 { "LGD", 764, EDID_QUIRK_FORCE_10BPC },
129
f453ba04
DA		 130 /* LG Philips LCD LP154W01-A5 */
131 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
132 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
133
134 /* Philips 107p5 CRT */
135 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
136
137 /* Proview AY765C */
138 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
139
140 /* Samsung SyncMaster 205BW. Note: irony */
141 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
142 /* Samsung SyncMaster 22[5-6]BW */
143 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
144 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
bc42aabc 145
bc5b9641
MK		 146 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
147 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
148
bc42aabc
AJ		 149 /* ViewSonic VA2026w */
150 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
118bdbd8
AD		 151
152 /* Medion MD 30217 PG */
153 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
49d45a31
RM		 154
155 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
156 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
36fc5797
TV		 157
158 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
159 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC },
f453ba04
DA		 160};
161
a6b21831
TR		 162/*
163 * Autogenerated from the DMT spec.
164 * This table is copied from xfree86/modes/xf86EdidModes.c.
165 */
166static const struct drm_display_mode drm_dmt_modes[] = {
24b856b1 167 /* 0x01 - 640x350@85Hz */
a6b21831
TR		 168 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
169 736, 832, 0, 350, 382, 385, 445, 0,
170 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 171 /* 0x02 - 640x400@85Hz */
a6b21831
TR		 172 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
173 736, 832, 0, 400, 401, 404, 445, 0,
174 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 175 /* 0x03 - 720x400@85Hz */
a6b21831
TR		 176 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
177 828, 936, 0, 400, 401, 404, 446, 0,
178 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 179 /* 0x04 - 640x480@60Hz */
a6b21831 180 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
fcf22d05 181 752, 800, 0, 480, 490, 492, 525, 0,
a6b21831 182 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 183 /* 0x05 - 640x480@72Hz */
a6b21831
TR		 184 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
185 704, 832, 0, 480, 489, 492, 520, 0,
186 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 187 /* 0x06 - 640x480@75Hz */
a6b21831
TR		 188 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
189 720, 840, 0, 480, 481, 484, 500, 0,
190 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 191 /* 0x07 - 640x480@85Hz */
a6b21831
TR		 192 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
193 752, 832, 0, 480, 481, 484, 509, 0,
194 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 195 /* 0x08 - 800x600@56Hz */
a6b21831
TR		 196 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
197 896, 1024, 0, 600, 601, 603, 625, 0,
198 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 199 /* 0x09 - 800x600@60Hz */
a6b21831
TR		 200 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
201 968, 1056, 0, 600, 601, 605, 628, 0,
202 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 203 /* 0x0a - 800x600@72Hz */
a6b21831
TR		 204 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
205 976, 1040, 0, 600, 637, 643, 666, 0,
206 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 207 /* 0x0b - 800x600@75Hz */
a6b21831
TR		 208 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
209 896, 1056, 0, 600, 601, 604, 625, 0,
210 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 211 /* 0x0c - 800x600@85Hz */
a6b21831
TR		 212 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
213 896, 1048, 0, 600, 601, 604, 631, 0,
214 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 215 /* 0x0d - 800x600@120Hz RB */
a6b21831
TR		 216 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
217 880, 960, 0, 600, 603, 607, 636, 0,
218 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 219 /* 0x0e - 848x480@60Hz */
a6b21831
TR		 220 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
221 976, 1088, 0, 480, 486, 494, 517, 0,
222 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 223 /* 0x0f - 1024x768@43Hz, interlace */
a6b21831 224 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
735b100f 225 1208, 1264, 0, 768, 768, 776, 817, 0,
a6b21831 226 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
fcf22d05 227 DRM_MODE_FLAG_INTERLACE) },
24b856b1 228 /* 0x10 - 1024x768@60Hz */
a6b21831
TR		 229 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
230 1184, 1344, 0, 768, 771, 777, 806, 0,
231 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 232 /* 0x11 - 1024x768@70Hz */
a6b21831
TR		 233 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
234 1184, 1328, 0, 768, 771, 777, 806, 0,
235 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 236 /* 0x12 - 1024x768@75Hz */
a6b21831
TR		 237 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
238 1136, 1312, 0, 768, 769, 772, 800, 0,
239 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 240 /* 0x13 - 1024x768@85Hz */
a6b21831
TR		 241 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
242 1168, 1376, 0, 768, 769, 772, 808, 0,
243 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 244 /* 0x14 - 1024x768@120Hz RB */
a6b21831
TR		 245 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
246 1104, 1184, 0, 768, 771, 775, 813, 0,
247 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 248 /* 0x15 - 1152x864@75Hz */
a6b21831
TR		 249 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
250 1344, 1600, 0, 864, 865, 868, 900, 0,
251 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
bfcd74d2
VS		 252 /* 0x55 - 1280x720@60Hz */
253 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
254 1430, 1650, 0, 720, 725, 730, 750, 0,
255 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 256 /* 0x16 - 1280x768@60Hz RB */
a6b21831
TR		 257 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
258 1360, 1440, 0, 768, 771, 778, 790, 0,
259 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 260 /* 0x17 - 1280x768@60Hz */
a6b21831
TR		 261 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
262 1472, 1664, 0, 768, 771, 778, 798, 0,
263 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 264 /* 0x18 - 1280x768@75Hz */
a6b21831
TR		 265 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
266 1488, 1696, 0, 768, 771, 778, 805, 0,
fcf22d05 267 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 268 /* 0x19 - 1280x768@85Hz */
a6b21831
TR		 269 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
270 1496, 1712, 0, 768, 771, 778, 809, 0,
271 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 272 /* 0x1a - 1280x768@120Hz RB */
a6b21831
TR		 273 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
274 1360, 1440, 0, 768, 771, 778, 813, 0,
275 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 276 /* 0x1b - 1280x800@60Hz RB */
a6b21831
TR		 277 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
278 1360, 1440, 0, 800, 803, 809, 823, 0,
279 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 280 /* 0x1c - 1280x800@60Hz */
a6b21831
TR		 281 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
282 1480, 1680, 0, 800, 803, 809, 831, 0,
fcf22d05 283 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 284 /* 0x1d - 1280x800@75Hz */
a6b21831
TR		 285 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
286 1488, 1696, 0, 800, 803, 809, 838, 0,
287 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 288 /* 0x1e - 1280x800@85Hz */
a6b21831
TR		 289 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
290 1496, 1712, 0, 800, 803, 809, 843, 0,
291 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 292 /* 0x1f - 1280x800@120Hz RB */
a6b21831
TR		 293 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
294 1360, 1440, 0, 800, 803, 809, 847, 0,
295 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 296 /* 0x20 - 1280x960@60Hz */
a6b21831
TR		 297 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
298 1488, 1800, 0, 960, 961, 964, 1000, 0,
299 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 300 /* 0x21 - 1280x960@85Hz */
a6b21831
TR		 301 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
302 1504, 1728, 0, 960, 961, 964, 1011, 0,
303 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 304 /* 0x22 - 1280x960@120Hz RB */
a6b21831
TR		 305 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
306 1360, 1440, 0, 960, 963, 967, 1017, 0,
307 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 308 /* 0x23 - 1280x1024@60Hz */
a6b21831
TR		 309 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
310 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
311 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 312 /* 0x24 - 1280x1024@75Hz */
a6b21831
TR		 313 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
314 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
315 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 316 /* 0x25 - 1280x1024@85Hz */
a6b21831
TR		 317 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
318 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
319 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 320 /* 0x26 - 1280x1024@120Hz RB */
a6b21831
TR		 321 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
322 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
323 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 324 /* 0x27 - 1360x768@60Hz */
a6b21831
TR		 325 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
326 1536, 1792, 0, 768, 771, 777, 795, 0,
327 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 328 /* 0x28 - 1360x768@120Hz RB */
a6b21831
TR		 329 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
330 1440, 1520, 0, 768, 771, 776, 813, 0,
331 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 332 /* 0x51 - 1366x768@60Hz */
333 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
334 1579, 1792, 0, 768, 771, 774, 798, 0,
335 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
336 /* 0x56 - 1366x768@60Hz */
337 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
338 1436, 1500, 0, 768, 769, 772, 800, 0,
339 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 340 /* 0x29 - 1400x1050@60Hz RB */
a6b21831
TR		 341 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
342 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
343 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 344 /* 0x2a - 1400x1050@60Hz */
a6b21831
TR		 345 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
346 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
347 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 348 /* 0x2b - 1400x1050@75Hz */
a6b21831
TR		 349 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
350 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
351 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 352 /* 0x2c - 1400x1050@85Hz */
a6b21831
TR		 353 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
354 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
355 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 356 /* 0x2d - 1400x1050@120Hz RB */
a6b21831
TR		 357 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
358 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
359 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 360 /* 0x2e - 1440x900@60Hz RB */
a6b21831
TR		 361 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
362 1520, 1600, 0, 900, 903, 909, 926, 0,
363 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 364 /* 0x2f - 1440x900@60Hz */
a6b21831
TR		 365 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
366 1672, 1904, 0, 900, 903, 909, 934, 0,
367 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 368 /* 0x30 - 1440x900@75Hz */
a6b21831
TR		 369 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
370 1688, 1936, 0, 900, 903, 909, 942, 0,
371 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 372 /* 0x31 - 1440x900@85Hz */
a6b21831
TR		 373 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
374 1696, 1952, 0, 900, 903, 909, 948, 0,
375 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 376 /* 0x32 - 1440x900@120Hz RB */
a6b21831
TR		 377 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
378 1520, 1600, 0, 900, 903, 909, 953, 0,
379 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 380 /* 0x53 - 1600x900@60Hz */
381 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
382 1704, 1800, 0, 900, 901, 904, 1000, 0,
383 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 384 /* 0x33 - 1600x1200@60Hz */
a6b21831
TR		 385 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
386 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
387 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 388 /* 0x34 - 1600x1200@65Hz */
a6b21831
TR		 389 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
390 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
391 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 392 /* 0x35 - 1600x1200@70Hz */
a6b21831
TR		 393 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
394 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
395 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 396 /* 0x36 - 1600x1200@75Hz */
a6b21831
TR		 397 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
398 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
399 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 400 /* 0x37 - 1600x1200@85Hz */
a6b21831
TR		 401 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
402 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
403 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 404 /* 0x38 - 1600x1200@120Hz RB */
a6b21831
TR		 405 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
406 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
407 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 408 /* 0x39 - 1680x1050@60Hz RB */
a6b21831
TR		 409 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
410 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
411 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 412 /* 0x3a - 1680x1050@60Hz */
a6b21831
TR		 413 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
414 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
415 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 416 /* 0x3b - 1680x1050@75Hz */
a6b21831
TR		 417 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
418 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
419 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 420 /* 0x3c - 1680x1050@85Hz */
a6b21831
TR		 421 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
422 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
423 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 424 /* 0x3d - 1680x1050@120Hz RB */
a6b21831
TR		 425 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
426 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
427 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 428 /* 0x3e - 1792x1344@60Hz */
a6b21831
TR		 429 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
430 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
431 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 432 /* 0x3f - 1792x1344@75Hz */
a6b21831
TR		 433 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
434 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
435 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 436 /* 0x40 - 1792x1344@120Hz RB */
a6b21831
TR		 437 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
438 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
439 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 440 /* 0x41 - 1856x1392@60Hz */
a6b21831
TR		 441 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
442 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
443 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 444 /* 0x42 - 1856x1392@75Hz */
a6b21831 445 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
fcf22d05 446 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
a6b21831 447 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 448 /* 0x43 - 1856x1392@120Hz RB */
a6b21831
TR		 449 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
450 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
451 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 452 /* 0x52 - 1920x1080@60Hz */
453 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
454 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
455 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 456 /* 0x44 - 1920x1200@60Hz RB */
a6b21831
TR		 457 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
458 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
459 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 460 /* 0x45 - 1920x1200@60Hz */
a6b21831
TR		 461 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
462 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
463 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 464 /* 0x46 - 1920x1200@75Hz */
a6b21831
TR		 465 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
466 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
467 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 468 /* 0x47 - 1920x1200@85Hz */
a6b21831
TR		 469 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
470 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
471 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 472 /* 0x48 - 1920x1200@120Hz RB */
a6b21831
TR		 473 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
474 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
475 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 476 /* 0x49 - 1920x1440@60Hz */
a6b21831
TR		 477 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
478 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
479 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 480 /* 0x4a - 1920x1440@75Hz */
a6b21831
TR		 481 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
482 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
483 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 484 /* 0x4b - 1920x1440@120Hz RB */
a6b21831
TR		 485 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
486 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
487 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 488 /* 0x54 - 2048x1152@60Hz */
489 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
490 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
491 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 492 /* 0x4c - 2560x1600@60Hz RB */
a6b21831
TR		 493 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
494 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
495 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 496 /* 0x4d - 2560x1600@60Hz */
a6b21831
TR		 497 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
498 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
499 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 500 /* 0x4e - 2560x1600@75Hz */
a6b21831
TR		 501 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
502 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
503 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 504 /* 0x4f - 2560x1600@85Hz */
a6b21831
TR		 505 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
506 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
507 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 508 /* 0x50 - 2560x1600@120Hz RB */
a6b21831
TR		 509 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
510 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
511 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 512 /* 0x57 - 4096x2160@60Hz RB */
513 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
514 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
515 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
516 /* 0x58 - 4096x2160@59.94Hz RB */
517 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
518 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
519 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
a6b21831
TR		 520};
521
e7bfa5c4
VS		 522/*
523 * These more or less come from the DMT spec. The 720x400 modes are
524 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
525 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
526 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
527 * mode.
528 *
529 * The DMT modes have been fact-checked; the rest are mild guesses.
530 */
a6b21831
TR		 531static const struct drm_display_mode edid_est_modes[] = {
532 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
533 968, 1056, 0, 600, 601, 605, 628, 0,
534 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
535 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
536 896, 1024, 0, 600, 601, 603, 625, 0,
537 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
538 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
539 720, 840, 0, 480, 481, 484, 500, 0,
540 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
541 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
87707cfd 542 704, 832, 0, 480, 489, 492, 520, 0,
a6b21831
TR		 543 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
544 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
545 768, 864, 0, 480, 483, 486, 525, 0,
546 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
87707cfd 547 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
a6b21831
TR		 548 752, 800, 0, 480, 490, 492, 525, 0,
549 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
550 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
551 846, 900, 0, 400, 421, 423, 449, 0,
552 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
553 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
554 846, 900, 0, 400, 412, 414, 449, 0,
555 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
556 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
557 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
558 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
87707cfd 559 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
a6b21831
TR		 560 1136, 1312, 0, 768, 769, 772, 800, 0,
561 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
562 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
563 1184, 1328, 0, 768, 771, 777, 806, 0,
564 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
565 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
566 1184, 1344, 0, 768, 771, 777, 806, 0,
567 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
568 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
569 1208, 1264, 0, 768, 768, 776, 817, 0,
570 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
571 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
572 928, 1152, 0, 624, 625, 628, 667, 0,
573 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
574 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
575 896, 1056, 0, 600, 601, 604, 625, 0,
576 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
577 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
578 976, 1040, 0, 600, 637, 643, 666, 0,
579 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
580 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
581 1344, 1600, 0, 864, 865, 868, 900, 0,
582 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
583};
584
585struct minimode {
586 short w;
587 short h;
588 short r;
589 short rb;
590};
591
592static const struct minimode est3_modes[] = {
593 /* byte 6 */
594 { 640, 350, 85, 0 },
595 { 640, 400, 85, 0 },
596 { 720, 400, 85, 0 },
597 { 640, 480, 85, 0 },
598 { 848, 480, 60, 0 },
599 { 800, 600, 85, 0 },
600 { 1024, 768, 85, 0 },
601 { 1152, 864, 75, 0 },
602 /* byte 7 */
603 { 1280, 768, 60, 1 },
604 { 1280, 768, 60, 0 },
605 { 1280, 768, 75, 0 },
606 { 1280, 768, 85, 0 },
607 { 1280, 960, 60, 0 },
608 { 1280, 960, 85, 0 },
609 { 1280, 1024, 60, 0 },
610 { 1280, 1024, 85, 0 },
611 /* byte 8 */
612 { 1360, 768, 60, 0 },
613 { 1440, 900, 60, 1 },
614 { 1440, 900, 60, 0 },
615 { 1440, 900, 75, 0 },
616 { 1440, 900, 85, 0 },
617 { 1400, 1050, 60, 1 },
618 { 1400, 1050, 60, 0 },
619 { 1400, 1050, 75, 0 },
620 /* byte 9 */
621 { 1400, 1050, 85, 0 },
622 { 1680, 1050, 60, 1 },
623 { 1680, 1050, 60, 0 },
624 { 1680, 1050, 75, 0 },
625 { 1680, 1050, 85, 0 },
626 { 1600, 1200, 60, 0 },
627 { 1600, 1200, 65, 0 },
628 { 1600, 1200, 70, 0 },
629 /* byte 10 */
630 { 1600, 1200, 75, 0 },
631 { 1600, 1200, 85, 0 },
632 { 1792, 1344, 60, 0 },
c068b32a 633 { 1792, 1344, 75, 0 },
a6b21831
TR		 634 { 1856, 1392, 60, 0 },
635 { 1856, 1392, 75, 0 },
636 { 1920, 1200, 60, 1 },
637 { 1920, 1200, 60, 0 },
638 /* byte 11 */
639 { 1920, 1200, 75, 0 },
640 { 1920, 1200, 85, 0 },
641 { 1920, 1440, 60, 0 },
642 { 1920, 1440, 75, 0 },
643};
644
645static const struct minimode extra_modes[] = {
646 { 1024, 576, 60, 0 },
647 { 1366, 768, 60, 0 },
648 { 1600, 900, 60, 0 },
649 { 1680, 945, 60, 0 },
650 { 1920, 1080, 60, 0 },
651 { 2048, 1152, 60, 0 },
652 { 2048, 1536, 60, 0 },
653};
654
655/*
656 * Probably taken from CEA-861 spec.
657 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c.
d9278b4c
JN		 658 *
659 * Index using the VIC.
a6b21831
TR		 660 */
661static const struct drm_display_mode edid_cea_modes[] = {
d9278b4c
JN		 662 /* 0 - dummy, VICs start at 1 */
663 { },
a6b21831
TR		 664 /* 1 - 640x480@60Hz */
665 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
666 752, 800, 0, 480, 490, 492, 525, 0,
ee7925bb 667 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 668 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 669 /* 2 - 720x480@60Hz */
670 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
671 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 672 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 673 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 674 /* 3 - 720x480@60Hz */
675 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
676 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 677 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 678 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 679 /* 4 - 1280x720@60Hz */
680 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
681 1430, 1650, 0, 720, 725, 730, 750, 0,
ee7925bb 682 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 683 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 684 /* 5 - 1920x1080i@60Hz */
685 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
686 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
687 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
ee7925bb 688 DRM_MODE_FLAG_INTERLACE),
985e5dc2 689 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
fb01d280
CT		 690 /* 6 - 720(1440)x480i@60Hz */
691 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
692 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 693 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 694 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 695 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
fb01d280
CT		 696 /* 7 - 720(1440)x480i@60Hz */
697 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
698 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 699 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 700 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 701 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
fb01d280
CT		 702 /* 8 - 720(1440)x240@60Hz */
703 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
704 801, 858, 0, 240, 244, 247, 262, 0,
a6b21831 705 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 706 DRM_MODE_FLAG_DBLCLK),
985e5dc2 707 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
fb01d280
CT		 708 /* 9 - 720(1440)x240@60Hz */
709 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
710 801, 858, 0, 240, 244, 247, 262, 0,
a6b21831 711 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 712 DRM_MODE_FLAG_DBLCLK),
985e5dc2 713 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 714 /* 10 - 2880x480i@60Hz */
715 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
716 3204, 3432, 0, 480, 488, 494, 525, 0,
717 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 718 DRM_MODE_FLAG_INTERLACE),
985e5dc2 719 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 720 /* 11 - 2880x480i@60Hz */
721 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
722 3204, 3432, 0, 480, 488, 494, 525, 0,
723 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 724 DRM_MODE_FLAG_INTERLACE),
985e5dc2 725 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 726 /* 12 - 2880x240@60Hz */
727 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
728 3204, 3432, 0, 240, 244, 247, 262, 0,
ee7925bb 729 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 730 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 731 /* 13 - 2880x240@60Hz */
732 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
733 3204, 3432, 0, 240, 244, 247, 262, 0,
ee7925bb 734 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 735 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 736 /* 14 - 1440x480@60Hz */
737 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
738 1596, 1716, 0, 480, 489, 495, 525, 0,
ee7925bb 739 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 740 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 741 /* 15 - 1440x480@60Hz */
742 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
743 1596, 1716, 0, 480, 489, 495, 525, 0,
ee7925bb 744 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 745 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 746 /* 16 - 1920x1080@60Hz */
747 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
748 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 749 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 750 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 751 /* 17 - 720x576@50Hz */
752 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
753 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 754 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 755 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 756 /* 18 - 720x576@50Hz */
757 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
758 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 759 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 760 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 761 /* 19 - 1280x720@50Hz */
762 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
763 1760, 1980, 0, 720, 725, 730, 750, 0,
ee7925bb 764 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 765 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 766 /* 20 - 1920x1080i@50Hz */
767 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
768 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
769 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
ee7925bb 770 DRM_MODE_FLAG_INTERLACE),
985e5dc2 771 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
fb01d280
CT		 772 /* 21 - 720(1440)x576i@50Hz */
773 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
774 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 775 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 776 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 777 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
fb01d280
CT		 778 /* 22 - 720(1440)x576i@50Hz */
779 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
780 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 781 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 782 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 783 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
fb01d280
CT		 784 /* 23 - 720(1440)x288@50Hz */
785 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
786 795, 864, 0, 288, 290, 293, 312, 0,
a6b21831 787 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 788 DRM_MODE_FLAG_DBLCLK),
985e5dc2 789 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
fb01d280
CT		 790 /* 24 - 720(1440)x288@50Hz */
791 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
792 795, 864, 0, 288, 290, 293, 312, 0,
a6b21831 793 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 794 DRM_MODE_FLAG_DBLCLK),
985e5dc2 795 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 796 /* 25 - 2880x576i@50Hz */
797 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
798 3180, 3456, 0, 576, 580, 586, 625, 0,
799 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 800 DRM_MODE_FLAG_INTERLACE),
985e5dc2 801 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 802 /* 26 - 2880x576i@50Hz */
803 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
804 3180, 3456, 0, 576, 580, 586, 625, 0,
805 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 806 DRM_MODE_FLAG_INTERLACE),
985e5dc2 807 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 808 /* 27 - 2880x288@50Hz */
809 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
810 3180, 3456, 0, 288, 290, 293, 312, 0,
ee7925bb 811 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 812 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 813 /* 28 - 2880x288@50Hz */
814 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
815 3180, 3456, 0, 288, 290, 293, 312, 0,
ee7925bb 816 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 817 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 818 /* 29 - 1440x576@50Hz */
819 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
820 1592, 1728, 0, 576, 581, 586, 625, 0,
ee7925bb 821 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 822 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 823 /* 30 - 1440x576@50Hz */
824 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
825 1592, 1728, 0, 576, 581, 586, 625, 0,
ee7925bb 826 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 827 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 828 /* 31 - 1920x1080@50Hz */
829 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
830 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 831 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 832 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 833 /* 32 - 1920x1080@24Hz */
834 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
835 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 836 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 837 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 838 /* 33 - 1920x1080@25Hz */
839 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
840 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 841 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 842 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 843 /* 34 - 1920x1080@30Hz */
844 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
845 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 846 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 847 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 848 /* 35 - 2880x480@60Hz */
849 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
850 3192, 3432, 0, 480, 489, 495, 525, 0,
ee7925bb 851 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 852 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 853 /* 36 - 2880x480@60Hz */
854 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
855 3192, 3432, 0, 480, 489, 495, 525, 0,
ee7925bb 856 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 857 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 858 /* 37 - 2880x576@50Hz */
859 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
860 3184, 3456, 0, 576, 581, 586, 625, 0,
ee7925bb 861 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 862 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 863 /* 38 - 2880x576@50Hz */
864 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
865 3184, 3456, 0, 576, 581, 586, 625, 0,
ee7925bb 866 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 867 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 868 /* 39 - 1920x1080i@50Hz */
869 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
870 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
871 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 872 DRM_MODE_FLAG_INTERLACE),
985e5dc2 873 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 874 /* 40 - 1920x1080i@100Hz */
875 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
876 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
877 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
ee7925bb 878 DRM_MODE_FLAG_INTERLACE),
985e5dc2 879 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 880 /* 41 - 1280x720@100Hz */
881 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
882 1760, 1980, 0, 720, 725, 730, 750, 0,
ee7925bb 883 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 884 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 885 /* 42 - 720x576@100Hz */
886 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
887 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 888 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 889 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 890 /* 43 - 720x576@100Hz */
891 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
892 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 893 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 894 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
fb01d280
CT		 895 /* 44 - 720(1440)x576i@100Hz */
896 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
897 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 898 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
5a11f7f8 899 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 900 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
fb01d280
CT		 901 /* 45 - 720(1440)x576i@100Hz */
902 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
903 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 904 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
5a11f7f8 905 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 906 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 907 /* 46 - 1920x1080i@120Hz */
908 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
909 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
910 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
ee7925bb 911 DRM_MODE_FLAG_INTERLACE),
985e5dc2 912 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 913 /* 47 - 1280x720@120Hz */
914 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
915 1430, 1650, 0, 720, 725, 730, 750, 0,
ee7925bb 916 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 917 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 918 /* 48 - 720x480@120Hz */
919 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
920 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 921 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 922 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 923 /* 49 - 720x480@120Hz */
924 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
925 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 926 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 927 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
fb01d280
CT		 928 /* 50 - 720(1440)x480i@120Hz */
929 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
930 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 931 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 932 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 933 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
fb01d280
CT		 934 /* 51 - 720(1440)x480i@120Hz */
935 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
936 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 937 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 938 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 939 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 940 /* 52 - 720x576@200Hz */
941 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
942 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 943 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 944 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 945 /* 53 - 720x576@200Hz */
946 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
947 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 948 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 949 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
fb01d280
CT		 950 /* 54 - 720(1440)x576i@200Hz */
951 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
952 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 953 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 954 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 955 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
fb01d280
CT		 956 /* 55 - 720(1440)x576i@200Hz */
957 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
958 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 959 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 960 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 961 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 962 /* 56 - 720x480@240Hz */
963 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
964 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 965 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 966 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 967 /* 57 - 720x480@240Hz */
968 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
969 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 970 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 971 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
e587803c 972 /* 58 - 720(1440)x480i@240Hz */
fb01d280
CT		 973 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
974 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 975 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 976 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 977 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
e587803c 978 /* 59 - 720(1440)x480i@240Hz */
fb01d280
CT		 979 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
980 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 981 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 982 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 983 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 984 /* 60 - 1280x720@24Hz */
985 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
986 3080, 3300, 0, 720, 725, 730, 750, 0,
ee7925bb 987 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 988 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 989 /* 61 - 1280x720@25Hz */
990 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
991 3740, 3960, 0, 720, 725, 730, 750, 0,
ee7925bb 992 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 993 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 994 /* 62 - 1280x720@30Hz */
995 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
996 3080, 3300, 0, 720, 725, 730, 750, 0,
ee7925bb 997 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 998 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 999 /* 63 - 1920x1080@120Hz */
1000 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1001 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 1002 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 1003 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 1004 /* 64 - 1920x1080@100Hz */
1005 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
8f0e4907 1006 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 1007 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 1008 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
8ec6e075
SS		 1009 /* 65 - 1280x720@24Hz */
1010 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1011 3080, 3300, 0, 720, 725, 730, 750, 0,
1012 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1013 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1014 /* 66 - 1280x720@25Hz */
1015 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1016 3740, 3960, 0, 720, 725, 730, 750, 0,
1017 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1018 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1019 /* 67 - 1280x720@30Hz */
1020 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1021 3080, 3300, 0, 720, 725, 730, 750, 0,
1022 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1023 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1024 /* 68 - 1280x720@50Hz */
1025 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1026 1760, 1980, 0, 720, 725, 730, 750, 0,
1027 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1028 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1029 /* 69 - 1280x720@60Hz */
1030 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1031 1430, 1650, 0, 720, 725, 730, 750, 0,
1032 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1033 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1034 /* 70 - 1280x720@100Hz */
1035 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1036 1760, 1980, 0, 720, 725, 730, 750, 0,
1037 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1038 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1039 /* 71 - 1280x720@120Hz */
1040 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1041 1430, 1650, 0, 720, 725, 730, 750, 0,
1042 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1043 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1044 /* 72 - 1920x1080@24Hz */
1045 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1046 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1047 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1048 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1049 /* 73 - 1920x1080@25Hz */
1050 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1051 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1052 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1053 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1054 /* 74 - 1920x1080@30Hz */
1055 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1056 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1057 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1058 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1059 /* 75 - 1920x1080@50Hz */
1060 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1061 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1062 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1063 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1064 /* 76 - 1920x1080@60Hz */
1065 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1066 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1067 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1068 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1069 /* 77 - 1920x1080@100Hz */
1070 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1071 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1072 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1073 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1074 /* 78 - 1920x1080@120Hz */
1075 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1076 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1077 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1078 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1079 /* 79 - 1680x720@24Hz */
1080 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1081 3080, 3300, 0, 720, 725, 730, 750, 0,
1082 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1083 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1084 /* 80 - 1680x720@25Hz */
1085 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1086 2948, 3168, 0, 720, 725, 730, 750, 0,
1087 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1088 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1089 /* 81 - 1680x720@30Hz */
1090 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1091 2420, 2640, 0, 720, 725, 730, 750, 0,
1092 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1093 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1094 /* 82 - 1680x720@50Hz */
1095 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1096 1980, 2200, 0, 720, 725, 730, 750, 0,
1097 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1098 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1099 /* 83 - 1680x720@60Hz */
1100 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1101 1980, 2200, 0, 720, 725, 730, 750, 0,
1102 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1103 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1104 /* 84 - 1680x720@100Hz */
1105 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1106 1780, 2000, 0, 720, 725, 730, 825, 0,
1107 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1108 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1109 /* 85 - 1680x720@120Hz */
1110 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1111 1780, 2000, 0, 720, 725, 730, 825, 0,
1112 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1113 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1114 /* 86 - 2560x1080@24Hz */
1115 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1116 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1117 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1118 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1119 /* 87 - 2560x1080@25Hz */
1120 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1121 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1122 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1123 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1124 /* 88 - 2560x1080@30Hz */
1125 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1126 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1127 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1128 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1129 /* 89 - 2560x1080@50Hz */
1130 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1131 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1132 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1133 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1134 /* 90 - 2560x1080@60Hz */
1135 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1136 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1137 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1138 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1139 /* 91 - 2560x1080@100Hz */
1140 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1141 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1142 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1143 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1144 /* 92 - 2560x1080@120Hz */
1145 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1146 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1147 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1148 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1149 /* 93 - 3840x2160p@24Hz 16:9 */
1150 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1151 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1152 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1153 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1154 /* 94 - 3840x2160p@25Hz 16:9 */
1155 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1156 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1157 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1158 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1159 /* 95 - 3840x2160p@30Hz 16:9 */
1160 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1161 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1162 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1163 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1164 /* 96 - 3840x2160p@50Hz 16:9 */
1165 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1166 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1167 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1168 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1169 /* 97 - 3840x2160p@60Hz 16:9 */
1170 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1171 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1172 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1173 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1174 /* 98 - 4096x2160p@24Hz 256:135 */
1175 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1176 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1177 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1178 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1179 /* 99 - 4096x2160p@25Hz 256:135 */
1180 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1181 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1182 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1183 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1184 /* 100 - 4096x2160p@30Hz 256:135 */
1185 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1186 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1187 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1188 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1189 /* 101 - 4096x2160p@50Hz 256:135 */
1190 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1191 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1192 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1193 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1194 /* 102 - 4096x2160p@60Hz 256:135 */
1195 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1196 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1197 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1198 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1199 /* 103 - 3840x2160p@24Hz 64:27 */
1200 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1201 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1202 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1203 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1204 /* 104 - 3840x2160p@25Hz 64:27 */
1205 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1206 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1207 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1208 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1209 /* 105 - 3840x2160p@30Hz 64:27 */
1210 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1211 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1212 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1213 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1214 /* 106 - 3840x2160p@50Hz 64:27 */
1215 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1216 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1217 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1218 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1219 /* 107 - 3840x2160p@60Hz 64:27 */
1220 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1221 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1222 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1223 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
a6b21831
TR		 1224};
1225
7ebe1963 1226/*
d9278b4c 1227 * HDMI 1.4 4k modes. Index using the VIC.
7ebe1963
LD		 1228 */
1229static const struct drm_display_mode edid_4k_modes[] = {
d9278b4c
JN		 1230 /* 0 - dummy, VICs start at 1 */
1231 { },
7ebe1963
LD		 1232 /* 1 - 3840x2160@30Hz */
1233 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1234 3840, 4016, 4104, 4400, 0,
1235 2160, 2168, 2178, 2250, 0,
1236 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1237 .vrefresh = 30, },
1238 /* 2 - 3840x2160@25Hz */
1239 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1240 3840, 4896, 4984, 5280, 0,
1241 2160, 2168, 2178, 2250, 0,
1242 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1243 .vrefresh = 25, },
1244 /* 3 - 3840x2160@24Hz */
1245 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1246 3840, 5116, 5204, 5500, 0,
1247 2160, 2168, 2178, 2250, 0,
1248 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1249 .vrefresh = 24, },
1250 /* 4 - 4096x2160@24Hz (SMPTE) */
1251 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1252 4096, 5116, 5204, 5500, 0,
1253 2160, 2168, 2178, 2250, 0,
1254 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1255 .vrefresh = 24, },
1256};
1257
61e57a8d 1258/*** DDC fetch and block validation ***/
f453ba04 1259
083ae056
AJ		 1260static const u8 edid_header[] = {
1261 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1262};
f453ba04 1263
db6cf833
TR		 1264/**
1265 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1266 * @raw_edid: pointer to raw base EDID block
1267 *
1268 * Sanity check the header of the base EDID block.
1269 *
1270 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
051963d4
TR		 1271 */
1272int drm_edid_header_is_valid(const u8 *raw_edid)
1273{
1274 int i, score = 0;
1275
1276 for (i = 0; i < sizeof(edid_header); i++)
1277 if (raw_edid[i] == edid_header[i])
1278 score++;
1279
1280 return score;
1281}
1282EXPORT_SYMBOL(drm_edid_header_is_valid);
1283
47819ba2
AJ		 1284static int edid_fixup __read_mostly = 6;
1285module_param_named(edid_fixup, edid_fixup, int, 0400);
1286MODULE_PARM_DESC(edid_fixup,
1287 "Minimum number of valid EDID header bytes (0-8, default 6)");
051963d4 1288
40d9b043
DA		 1289static void drm_get_displayid(struct drm_connector *connector,
1290 struct edid *edid);
da9df2f4 1291
c465bbc8
SB		 1292static int drm_edid_block_checksum(const u8 *raw_edid)
1293{
1294 int i;
1295 u8 csum = 0;
1296 for (i = 0; i < EDID_LENGTH; i++)
1297 csum += raw_edid[i];
1298
1299 return csum;
1300}
1301
d6885d65
SB		 1302static bool drm_edid_is_zero(const u8 *in_edid, int length)
1303{
1304 if (memchr_inv(in_edid, 0, length))
1305 return false;
1306
1307 return true;
1308}
1309
db6cf833
TR		 1310/**
1311 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1312 * @raw_edid: pointer to raw EDID block
1313 * @block: type of block to validate (0 for base, extension otherwise)
1314 * @print_bad_edid: if true, dump bad EDID blocks to the console
6ba2bd3d 1315 * @edid_corrupt: if true, the header or checksum is invalid
db6cf833
TR		 1316 *
1317 * Validate a base or extension EDID block and optionally dump bad blocks to
1318 * the console.
1319 *
1320 * Return: True if the block is valid, false otherwise.
f453ba04 1321 */
6ba2bd3d
TP		 1322bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
1323 bool *edid_corrupt)
f453ba04 1324{
c465bbc8 1325 u8 csum;
61e57a8d 1326 struct edid *edid = (struct edid *)raw_edid;
f453ba04 1327
fe2ef780
SWK		 1328 if (WARN_ON(!raw_edid))
1329 return false;
1330
47819ba2
AJ		 1331 if (edid_fixup > 8 || edid_fixup < 0)
1332 edid_fixup = 6;
1333
f89ec8a4 1334 if (block == 0) {
051963d4 1335 int score = drm_edid_header_is_valid(raw_edid);
6ba2bd3d
TP		 1336 if (score == 8) {
1337 if (edid_corrupt)
ac6f2e29 1338 *edid_corrupt = false;
6ba2bd3d
TP		 1339 } else if (score >= edid_fixup) {
1340 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
1341 * The corrupt flag needs to be set here otherwise, the
1342 * fix-up code here will correct the problem, the
1343 * checksum is correct and the test fails
1344 */
1345 if (edid_corrupt)
ac6f2e29 1346 *edid_corrupt = true;
61e57a8d
AJ		 1347 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1348 memcpy(raw_edid, edid_header, sizeof(edid_header));
1349 } else {
6ba2bd3d 1350 if (edid_corrupt)
ac6f2e29 1351 *edid_corrupt = true;
61e57a8d
AJ		 1352 goto bad;
1353 }
1354 }
f453ba04 1355
c465bbc8 1356 csum = drm_edid_block_checksum(raw_edid);
f453ba04 1357 if (csum) {
6ba2bd3d 1358 if (edid_corrupt)
ac6f2e29 1359 *edid_corrupt = true;
6ba2bd3d 1360
4a638b4e 1361 /* allow CEA to slide through, switches mangle this */
82d75356
TV		 1362 if (raw_edid[0] == CEA_EXT) {
1363 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum);
1364 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n");
1365 } else {
1366 if (print_bad_edid)
813a7878 1367 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum);
82d75356 1368
4a638b4e 1369 goto bad;
82d75356 1370 }
f453ba04
DA		 1371 }
1372
61e57a8d
AJ		 1373 /* per-block-type checks */
1374 switch (raw_edid[0]) {
1375 case 0: /* base */
1376 if (edid->version != 1) {
813a7878 1377 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version);
61e57a8d
AJ		 1378 goto bad;
1379 }
862b89c0 1380
61e57a8d
AJ		 1381 if (edid->revision > 4)
1382 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1383 break;
862b89c0 1384
61e57a8d
AJ		 1385 default:
1386 break;
1387 }
47ee4ccf 1388
fe2ef780 1389 return true;
f453ba04
DA		 1390
1391bad:
fe2ef780 1392 if (print_bad_edid) {
da4c07b7 1393 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
499447db 1394 pr_notice("EDID block is all zeroes\n");
da4c07b7 1395 } else {
499447db 1396 pr_notice("Raw EDID:\n");
813a7878
CW		 1397 print_hex_dump(KERN_NOTICE,
1398 " \t", DUMP_PREFIX_NONE, 16, 1,
1399 raw_edid, EDID_LENGTH, false);
da4c07b7 1400 }
f453ba04 1401 }
fe2ef780 1402 return false;
f453ba04 1403}
da0df92b 1404EXPORT_SYMBOL(drm_edid_block_valid);
61e57a8d
AJ		 1405
1406/**
1407 * drm_edid_is_valid - sanity check EDID data
1408 * @edid: EDID data
1409 *
1410 * Sanity-check an entire EDID record (including extensions)
db6cf833
TR		 1411 *
1412 * Return: True if the EDID data is valid, false otherwise.
61e57a8d
AJ		 1413 */
1414bool drm_edid_is_valid(struct edid *edid)
1415{
1416 int i;
1417 u8 *raw = (u8 *)edid;
1418
1419 if (!edid)
1420 return false;
1421
1422 for (i = 0; i <= edid->extensions; i++)
6ba2bd3d 1423 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
61e57a8d
AJ		 1424 return false;
1425
1426 return true;
1427}
3c537889 1428EXPORT_SYMBOL(drm_edid_is_valid);
f453ba04 1429
61e57a8d
AJ		 1430#define DDC_SEGMENT_ADDR 0x30
1431/**
db6cf833 1432 * drm_do_probe_ddc_edid() - get EDID information via I2C
7c58e87e 1433 * @data: I2C device adapter
fc66811c
DV		 1434 * @buf: EDID data buffer to be filled
1435 * @block: 128 byte EDID block to start fetching from
1436 * @len: EDID data buffer length to fetch
1437 *
db6cf833 1438 * Try to fetch EDID information by calling I2C driver functions.
61e57a8d 1439 *
db6cf833 1440 * Return: 0 on success or -1 on failure.
61e57a8d
AJ		 1441 */
1442static int
18df89fe 1443drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
61e57a8d 1444{
18df89fe 1445 struct i2c_adapter *adapter = data;
61e57a8d 1446 unsigned char start = block * EDID_LENGTH;
cd004b3f
S		 1447 unsigned char segment = block >> 1;
1448 unsigned char xfers = segment ? 3 : 2;
4819d2e4
CW		 1449 int ret, retries = 5;
1450
db6cf833
TR		 1451 /*
1452 * The core I2C driver will automatically retry the transfer if the
4819d2e4
CW		 1453 * adapter reports EAGAIN. However, we find that bit-banging transfers
1454 * are susceptible to errors under a heavily loaded machine and
1455 * generate spurious NAKs and timeouts. Retrying the transfer
1456 * of the individual block a few times seems to overcome this.
1457 */
1458 do {
1459 struct i2c_msg msgs[] = {
1460 {
cd004b3f
S		 1461 .addr = DDC_SEGMENT_ADDR,
1462 .flags = 0,
1463 .len = 1,
1464 .buf = &segment,
1465 }, {
4819d2e4
CW		 1466 .addr = DDC_ADDR,
1467 .flags = 0,
1468 .len = 1,
1469 .buf = &start,
1470 }, {
1471 .addr = DDC_ADDR,
1472 .flags = I2C_M_RD,
1473 .len = len,
1474 .buf = buf,
1475 }
1476 };
cd004b3f 1477
db6cf833
TR		 1478 /*
1479 * Avoid sending the segment addr to not upset non-compliant
1480 * DDC monitors.
1481 */
cd004b3f
S		 1482 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1483
9292f37e
ED		 1484 if (ret == -ENXIO) {
1485 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1486 adapter->name);
1487 break;
1488 }
cd004b3f 1489 } while (ret != xfers && --retries);
4819d2e4 1490
cd004b3f 1491 return ret == xfers ? 0 : -1;
61e57a8d
AJ		 1492}
1493
14544d09
CW		 1494static void connector_bad_edid(struct drm_connector *connector,
1495 u8 *edid, int num_blocks)
1496{
1497 int i;
1498
1499 if (connector->bad_edid_counter++ && !(drm_debug & DRM_UT_KMS))
1500 return;
1501
1502 dev_warn(connector->dev->dev,
1503 "%s: EDID is invalid:\n",
1504 connector->name);
1505 for (i = 0; i < num_blocks; i++) {
1506 u8 *block = edid + i * EDID_LENGTH;
1507 char prefix[20];
1508
1509 if (drm_edid_is_zero(block, EDID_LENGTH))
1510 sprintf(prefix, "\t[%02x] ZERO ", i);
1511 else if (!drm_edid_block_valid(block, i, false, NULL))
1512 sprintf(prefix, "\t[%02x] BAD ", i);
1513 else
1514 sprintf(prefix, "\t[%02x] GOOD ", i);
1515
1516 print_hex_dump(KERN_WARNING,
1517 prefix, DUMP_PREFIX_NONE, 16, 1,
1518 block, EDID_LENGTH, false);
1519 }
1520}
1521
18df89fe
LPC		 1522/**
1523 * drm_do_get_edid - get EDID data using a custom EDID block read function
1524 * @connector: connector we're probing
1525 * @get_edid_block: EDID block read function
1526 * @data: private data passed to the block read function
1527 *
1528 * When the I2C adapter connected to the DDC bus is hidden behind a device that
1529 * exposes a different interface to read EDID blocks this function can be used
1530 * to get EDID data using a custom block read function.
1531 *
1532 * As in the general case the DDC bus is accessible by the kernel at the I2C
1533 * level, drivers must make all reasonable efforts to expose it as an I2C
1534 * adapter and use drm_get_edid() instead of abusing this function.
1535 *
1536 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1537 */
1538struct edid *drm_do_get_edid(struct drm_connector *connector,
1539 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
1540 size_t len),
1541 void *data)
61e57a8d 1542{
0ea75e23 1543 int i, j = 0, valid_extensions = 0;
f14f3686 1544 u8 *edid, *new;
61e57a8d 1545
f14f3686 1546 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
61e57a8d
AJ		 1547 return NULL;
1548
1549 /* base block fetch */
1550 for (i = 0; i < 4; i++) {
f14f3686 1551 if (get_edid_block(data, edid, 0, EDID_LENGTH))
61e57a8d 1552 goto out;
14544d09 1553 if (drm_edid_block_valid(edid, 0, false,
6ba2bd3d 1554 &connector->edid_corrupt))
61e57a8d 1555 break;
f14f3686 1556 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) {
4a9a8b71
DA		 1557 connector->null_edid_counter++;
1558 goto carp;
1559 }
61e57a8d
AJ		 1560 }
1561 if (i == 4)
1562 goto carp;
1563
1564 /* if there's no extensions, we're done */
14544d09
CW		 1565 valid_extensions = edid[0x7e];
1566 if (valid_extensions == 0)
f14f3686 1567 return (struct edid *)edid;
61e57a8d 1568
14544d09 1569 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
61e57a8d
AJ		 1570 if (!new)
1571 goto out;
f14f3686 1572 edid = new;
61e57a8d 1573
f14f3686 1574 for (j = 1; j <= edid[0x7e]; j++) {
14544d09 1575 u8 *block = edid + j * EDID_LENGTH;
a28187cc 1576
61e57a8d 1577 for (i = 0; i < 4; i++) {
a28187cc 1578 if (get_edid_block(data, block, j, EDID_LENGTH))
61e57a8d 1579 goto out;
14544d09 1580 if (drm_edid_block_valid(block, j, false, NULL))
61e57a8d
AJ		 1581 break;
1582 }
f934ec8c 1583
14544d09
CW		 1584 if (i == 4)
1585 valid_extensions--;
0ea75e23
ST		 1586 }
1587
f14f3686 1588 if (valid_extensions != edid[0x7e]) {
14544d09
CW		 1589 u8 *base;
1590
1591 connector_bad_edid(connector, edid, edid[0x7e] + 1);
1592
f14f3686
CW		 1593 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions;
1594 edid[0x7e] = valid_extensions;
14544d09
CW		 1595
1596 new = kmalloc((valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
0ea75e23
ST		 1597 if (!new)
1598 goto out;
14544d09
CW		 1599
1600 base = new;
1601 for (i = 0; i <= edid[0x7e]; i++) {
1602 u8 *block = edid + i * EDID_LENGTH;
1603
1604 if (!drm_edid_block_valid(block, i, false, NULL))
1605 continue;
1606
1607 memcpy(base, block, EDID_LENGTH);
1608 base += EDID_LENGTH;
1609 }
1610
1611 kfree(edid);
f14f3686 1612 edid = new;
61e57a8d
AJ		 1613 }
1614
f14f3686 1615 return (struct edid *)edid;
61e57a8d
AJ		 1616
1617carp:
14544d09 1618 connector_bad_edid(connector, edid, 1);
61e57a8d 1619out:
f14f3686 1620 kfree(edid);
61e57a8d
AJ		 1621 return NULL;
1622}
18df89fe 1623EXPORT_SYMBOL_GPL(drm_do_get_edid);
61e57a8d
AJ		 1624
1625/**
db6cf833
TR		 1626 * drm_probe_ddc() - probe DDC presence
1627 * @adapter: I2C adapter to probe
fc66811c 1628 *
db6cf833 1629 * Return: True on success, false on failure.
61e57a8d 1630 */
fbff4690 1631bool
61e57a8d
AJ		 1632drm_probe_ddc(struct i2c_adapter *adapter)
1633{
1634 unsigned char out;
1635
1636 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
1637}
fbff4690 1638EXPORT_SYMBOL(drm_probe_ddc);
61e57a8d
AJ		 1639
1640/**
1641 * drm_get_edid - get EDID data, if available
1642 * @connector: connector we're probing
db6cf833 1643 * @adapter: I2C adapter to use for DDC
61e57a8d 1644 *
db6cf833 1645 * Poke the given I2C channel to grab EDID data if possible. If found,
61e57a8d
AJ		 1646 * attach it to the connector.
1647 *
db6cf833 1648 * Return: Pointer to valid EDID or NULL if we couldn't find any.
61e57a8d
AJ		 1649 */
1650struct edid *drm_get_edid(struct drm_connector *connector,
1651 struct i2c_adapter *adapter)
1652{
40d9b043
DA		 1653 struct edid *edid;
1654
15f080f0
JN		 1655 if (connector->force == DRM_FORCE_OFF)
1656 return NULL;
1657
1658 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
18df89fe 1659 return NULL;
61e57a8d 1660
40d9b043
DA		 1661 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
1662 if (edid)
1663 drm_get_displayid(connector, edid);
1664 return edid;
61e57a8d
AJ		 1665}
1666EXPORT_SYMBOL(drm_get_edid);
1667
5cb8eaa2
LW		 1668/**
1669 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
1670 * @connector: connector we're probing
1671 * @adapter: I2C adapter to use for DDC
1672 *
1673 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
1674 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
1675 * switch DDC to the GPU which is retrieving EDID.
1676 *
1677 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
1678 */
1679struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
1680 struct i2c_adapter *adapter)
1681{
1682 struct pci_dev *pdev = connector->dev->pdev;
1683 struct edid *edid;
1684
1685 vga_switcheroo_lock_ddc(pdev);
1686 edid = drm_get_edid(connector, adapter);
1687 vga_switcheroo_unlock_ddc(pdev);
1688
1689 return edid;
1690}
1691EXPORT_SYMBOL(drm_get_edid_switcheroo);
1692
51f8da59
JN		 1693/**
1694 * drm_edid_duplicate - duplicate an EDID and the extensions
1695 * @edid: EDID to duplicate
1696 *
db6cf833 1697 * Return: Pointer to duplicated EDID or NULL on allocation failure.
51f8da59
JN		 1698 */
1699struct edid *drm_edid_duplicate(const struct edid *edid)
1700{
1701 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1702}
1703EXPORT_SYMBOL(drm_edid_duplicate);
1704
61e57a8d
AJ		 1705/*** EDID parsing ***/
1706
f453ba04
DA		 1707/**
1708 * edid_vendor - match a string against EDID's obfuscated vendor field
1709 * @edid: EDID to match
1710 * @vendor: vendor string
1711 *
1712 * Returns true if @vendor is in @edid, false otherwise
1713 */
23c4cfbd 1714static bool edid_vendor(struct edid *edid, const char *vendor)
f453ba04
DA		 1715{
1716 char edid_vendor[3];
1717
1718 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
1719 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
1720 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
16456c87 1721 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
f453ba04
DA		 1722
1723 return !strncmp(edid_vendor, vendor, 3);
1724}
1725
1726/**
1727 * edid_get_quirks - return quirk flags for a given EDID
1728 * @edid: EDID to process
1729 *
1730 * This tells subsequent routines what fixes they need to apply.
1731 */
1732static u32 edid_get_quirks(struct edid *edid)
1733{
23c4cfbd 1734 const struct edid_quirk *quirk;
f453ba04
DA		 1735 int i;
1736
1737 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
1738 quirk = &edid_quirk_list[i];
1739
1740 if (edid_vendor(edid, quirk->vendor) &&
1741 (EDID_PRODUCT_ID(edid) == quirk->product_id))
1742 return quirk->quirks;
1743 }
1744
1745 return 0;
1746}
1747
1748#define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
339d202c 1749#define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
f453ba04 1750
f453ba04
DA		 1751/**
1752 * edid_fixup_preferred - set preferred modes based on quirk list
1753 * @connector: has mode list to fix up
1754 * @quirks: quirks list
1755 *
1756 * Walk the mode list for @connector, clearing the preferred status
1757 * on existing modes and setting it anew for the right mode ala @quirks.
1758 */
1759static void edid_fixup_preferred(struct drm_connector *connector,
1760 u32 quirks)
1761{
1762 struct drm_display_mode *t, *cur_mode, *preferred_mode;
f890607b 1763 int target_refresh = 0;
339d202c 1764 int cur_vrefresh, preferred_vrefresh;
f453ba04
DA		 1765
1766 if (list_empty(&connector->probed_modes))
1767 return;
1768
1769 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
1770 target_refresh = 60;
1771 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
1772 target_refresh = 75;
1773
1774 preferred_mode = list_first_entry(&connector->probed_modes,
1775 struct drm_display_mode, head);
1776
1777 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
1778 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
1779
1780 if (cur_mode == preferred_mode)
1781 continue;
1782
1783 /* Largest mode is preferred */
1784 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
1785 preferred_mode = cur_mode;
1786
339d202c
AD		 1787 cur_vrefresh = cur_mode->vrefresh ?
1788 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode);
1789 preferred_vrefresh = preferred_mode->vrefresh ?
1790 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode);
f453ba04
DA		 1791 /* At a given size, try to get closest to target refresh */
1792 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
339d202c
AD		 1793 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
1794 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
f453ba04
DA		 1795 preferred_mode = cur_mode;
1796 }
1797 }
1798
1799 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
1800}
1801
f6e252ba
AJ		 1802static bool
1803mode_is_rb(const struct drm_display_mode *mode)
1804{
1805 return (mode->htotal - mode->hdisplay == 160) &&
1806 (mode->hsync_end - mode->hdisplay == 80) &&
1807 (mode->hsync_end - mode->hsync_start == 32) &&
1808 (mode->vsync_start - mode->vdisplay == 3);
1809}
1810
33c7531d
AJ		 1811/*
1812 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
1813 * @dev: Device to duplicate against
1814 * @hsize: Mode width
1815 * @vsize: Mode height
1816 * @fresh: Mode refresh rate
f6e252ba 1817 * @rb: Mode reduced-blanking-ness
33c7531d
AJ		 1818 *
1819 * Walk the DMT mode list looking for a match for the given parameters.
db6cf833
TR		 1820 *
1821 * Return: A newly allocated copy of the mode, or NULL if not found.
33c7531d 1822 */
1d42bbc8 1823struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
f6e252ba
AJ		 1824 int hsize, int vsize, int fresh,
1825 bool rb)
559ee21d 1826{
07a5e632 1827 int i;
559ee21d 1828
a6b21831 1829 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
b1f559ec 1830 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
f8b46a05
AJ		 1831 if (hsize != ptr->hdisplay)
1832 continue;
1833 if (vsize != ptr->vdisplay)
1834 continue;
1835 if (fresh != drm_mode_vrefresh(ptr))
1836 continue;
f6e252ba
AJ		 1837 if (rb != mode_is_rb(ptr))
1838 continue;
f8b46a05
AJ		 1839
1840 return drm_mode_duplicate(dev, ptr);
559ee21d 1841 }
f8b46a05
AJ		 1842
1843 return NULL;
559ee21d 1844}
1d42bbc8 1845EXPORT_SYMBOL(drm_mode_find_dmt);
23425cae 1846
d1ff6409
AJ		 1847typedef void detailed_cb(struct detailed_timing *timing, void *closure);
1848
4d76a221
AJ		 1849static void
1850cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1851{
1852 int i, n = 0;
4966b2a9 1853 u8 d = ext[0x02];
4d76a221
AJ		 1854 u8 *det_base = ext + d;
1855
4966b2a9 1856 n = (127 - d) / 18;
4d76a221
AJ		 1857 for (i = 0; i < n; i++)
1858 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1859}
1860
cbba98f8
AJ		 1861static void
1862vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1863{
1864 unsigned int i, n = min((int)ext[0x02], 6);
1865 u8 *det_base = ext + 5;
1866
1867 if (ext[0x01] != 1)
1868 return; /* unknown version */
1869
1870 for (i = 0; i < n; i++)
1871 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1872}
1873
d1ff6409
AJ		 1874static void
1875drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
1876{
1877 int i;
1878 struct edid *edid = (struct edid *)raw_edid;
1879
1880 if (edid == NULL)
1881 return;
1882
1883 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
1884 cb(&(edid->detailed_timings[i]), closure);
1885
4d76a221
AJ		 1886 for (i = 1; i <= raw_edid[0x7e]; i++) {
1887 u8 *ext = raw_edid + (i * EDID_LENGTH);
1888 switch (*ext) {
1889 case CEA_EXT:
1890 cea_for_each_detailed_block(ext, cb, closure);
1891 break;
cbba98f8
AJ		 1892 case VTB_EXT:
1893 vtb_for_each_detailed_block(ext, cb, closure);
1894 break;
4d76a221
AJ		 1895 default:
1896 break;
1897 }
1898 }
d1ff6409
AJ		 1899}
1900
1901static void
1902is_rb(struct detailed_timing *t, void *data)
1903{
1904 u8 *r = (u8 *)t;
1905 if (r[3] == EDID_DETAIL_MONITOR_RANGE)
1906 if (r[15] & 0x10)
1907 *(bool *)data = true;
1908}
1909
1910/* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
1911static bool
1912drm_monitor_supports_rb(struct edid *edid)
1913{
1914 if (edid->revision >= 4) {
b196a498 1915 bool ret = false;
d1ff6409
AJ		 1916 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
1917 return ret;
1918 }
1919
1920 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
1921}
1922
7a374350
AJ		 1923static void
1924find_gtf2(struct detailed_timing *t, void *data)
1925{
1926 u8 *r = (u8 *)t;
1927 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02)
1928 *(u8 **)data = r;
1929}
1930
1931/* Secondary GTF curve kicks in above some break frequency */
1932static int
1933drm_gtf2_hbreak(struct edid *edid)
1934{
1935 u8 *r = NULL;
1936 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1937 return r ? (r[12] * 2) : 0;
1938}
1939
1940static int
1941drm_gtf2_2c(struct edid *edid)
1942{
1943 u8 *r = NULL;
1944 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1945 return r ? r[13] : 0;
1946}
1947
1948static int
1949drm_gtf2_m(struct edid *edid)
1950{
1951 u8 *r = NULL;
1952 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1953 return r ? (r[15] << 8) + r[14] : 0;
1954}
1955
1956static int
1957drm_gtf2_k(struct edid *edid)
1958{
1959 u8 *r = NULL;
1960 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1961 return r ? r[16] : 0;
1962}
1963
1964static int
1965drm_gtf2_2j(struct edid *edid)
1966{
1967 u8 *r = NULL;
1968 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1969 return r ? r[17] : 0;
1970}
1971
1972/**
1973 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
1974 * @edid: EDID block to scan
1975 */
1976static int standard_timing_level(struct edid *edid)
1977{
1978 if (edid->revision >= 2) {
1979 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
1980 return LEVEL_CVT;
1981 if (drm_gtf2_hbreak(edid))
1982 return LEVEL_GTF2;
1983 return LEVEL_GTF;
1984 }
1985 return LEVEL_DMT;
1986}
1987
23425cae
AJ		 1988/*
1989 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
1990 * monitors fill with ascii space (0x20) instead.
1991 */
1992static int
1993bad_std_timing(u8 a, u8 b)
1994{
1995 return (a == 0x00 && b == 0x00) ||
1996 (a == 0x01 && b == 0x01) ||
1997 (a == 0x20 && b == 0x20);
1998}
1999
f453ba04
DA		 2000/**
2001 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
fc66811c
DV		 2002 * @connector: connector of for the EDID block
2003 * @edid: EDID block to scan
f453ba04
DA		 2004 * @t: standard timing params
2005 *
2006 * Take the standard timing params (in this case width, aspect, and refresh)
5c61259e 2007 * and convert them into a real mode using CVT/GTF/DMT.
f453ba04 2008 */
7ca6adb3 2009static struct drm_display_mode *
7a374350 2010drm_mode_std(struct drm_connector *connector, struct edid *edid,
464fdeca 2011 struct std_timing *t)
f453ba04 2012{
7ca6adb3
AJ		 2013 struct drm_device *dev = connector->dev;
2014 struct drm_display_mode *m, *mode = NULL;
5c61259e
ZY		 2015 int hsize, vsize;
2016 int vrefresh_rate;
0454beab
MD		 2017 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
2018 >> EDID_TIMING_ASPECT_SHIFT;
5c61259e
ZY		 2019 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
2020 >> EDID_TIMING_VFREQ_SHIFT;
7a374350 2021 int timing_level = standard_timing_level(edid);
5c61259e 2022
23425cae
AJ		 2023 if (bad_std_timing(t->hsize, t->vfreq_aspect))
2024 return NULL;
2025
5c61259e
ZY		 2026 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
2027 hsize = t->hsize * 8 + 248;
2028 /* vrefresh_rate = vfreq + 60 */
2029 vrefresh_rate = vfreq + 60;
2030 /* the vdisplay is calculated based on the aspect ratio */
f066a17d 2031 if (aspect_ratio == 0) {
464fdeca 2032 if (edid->revision < 3)
f066a17d
AJ		 2033 vsize = hsize;
2034 else
2035 vsize = (hsize * 10) / 16;
2036 } else if (aspect_ratio == 1)
f453ba04 2037 vsize = (hsize * 3) / 4;
0454beab 2038 else if (aspect_ratio == 2)
f453ba04
DA		 2039 vsize = (hsize * 4) / 5;
2040 else
2041 vsize = (hsize * 9) / 16;
a0910c8e
AJ		 2042
2043 /* HDTV hack, part 1 */
2044 if (vrefresh_rate == 60 &&
2045 ((hsize == 1360 && vsize == 765) ||
2046 (hsize == 1368 && vsize == 769))) {
2047 hsize = 1366;
2048 vsize = 768;
2049 }
2050
7ca6adb3
AJ		 2051 /*
2052 * If this connector already has a mode for this size and refresh
2053 * rate (because it came from detailed or CVT info), use that
2054 * instead. This way we don't have to guess at interlace or
2055 * reduced blanking.
2056 */
522032da 2057 list_for_each_entry(m, &connector->probed_modes, head)
7ca6adb3
AJ		 2058 if (m->hdisplay == hsize && m->vdisplay == vsize &&
2059 drm_mode_vrefresh(m) == vrefresh_rate)
2060 return NULL;
2061
a0910c8e
AJ		 2062 /* HDTV hack, part 2 */
2063 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
2064 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
d50ba256 2065 false);
559ee21d 2066 mode->hdisplay = 1366;
a4967de6
AJ		 2067 mode->hsync_start = mode->hsync_start - 1;
2068 mode->hsync_end = mode->hsync_end - 1;
559ee21d
ZY		 2069 return mode;
2070 }
a0910c8e 2071
559ee21d 2072 /* check whether it can be found in default mode table */
f6e252ba
AJ		 2073 if (drm_monitor_supports_rb(edid)) {
2074 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
2075 true);
2076 if (mode)
2077 return mode;
2078 }
2079 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
559ee21d
ZY		 2080 if (mode)
2081 return mode;
2082
f6e252ba 2083 /* okay, generate it */
5c61259e
ZY		 2084 switch (timing_level) {
2085 case LEVEL_DMT:
5c61259e
ZY		 2086 break;
2087 case LEVEL_GTF:
2088 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2089 break;
7a374350
AJ		 2090 case LEVEL_GTF2:
2091 /*
2092 * This is potentially wrong if there's ever a monitor with
2093 * more than one ranges section, each claiming a different
2094 * secondary GTF curve. Please don't do that.
2095 */
2096 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
fc48f169
TI		 2097 if (!mode)
2098 return NULL;
7a374350 2099 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
aefd330e 2100 drm_mode_destroy(dev, mode);
7a374350
AJ		 2101 mode = drm_gtf_mode_complex(dev, hsize, vsize,
2102 vrefresh_rate, 0, 0,
2103 drm_gtf2_m(edid),
2104 drm_gtf2_2c(edid),
2105 drm_gtf2_k(edid),
2106 drm_gtf2_2j(edid));
2107 }
2108 break;
5c61259e 2109 case LEVEL_CVT:
d50ba256
DA		 2110 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
2111 false);
5c61259e
ZY		 2112 break;
2113 }
f453ba04
DA		 2114 return mode;
2115}
2116
b58db2c6
AJ		 2117/*
2118 * EDID is delightfully ambiguous about how interlaced modes are to be
2119 * encoded. Our internal representation is of frame height, but some
2120 * HDTV detailed timings are encoded as field height.
2121 *
2122 * The format list here is from CEA, in frame size. Technically we
2123 * should be checking refresh rate too. Whatever.
2124 */
2125static void
2126drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
2127 struct detailed_pixel_timing *pt)
2128{
2129 int i;
2130 static const struct {
2131 int w, h;
2132 } cea_interlaced[] = {
2133 { 1920, 1080 },
2134 { 720, 480 },
2135 { 1440, 480 },
2136 { 2880, 480 },
2137 { 720, 576 },
2138 { 1440, 576 },
2139 { 2880, 576 },
2140 };
b58db2c6
AJ		 2141
2142 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
2143 return;
2144
3c581411 2145 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
b58db2c6
AJ		 2146 if ((mode->hdisplay == cea_interlaced[i].w) &&
2147 (mode->vdisplay == cea_interlaced[i].h / 2)) {
2148 mode->vdisplay *= 2;
2149 mode->vsync_start *= 2;
2150 mode->vsync_end *= 2;
2151 mode->vtotal *= 2;
2152 mode->vtotal |= 1;
2153 }
2154 }
2155
2156 mode->flags |= DRM_MODE_FLAG_INTERLACE;
2157}
2158
f453ba04
DA		 2159/**
2160 * drm_mode_detailed - create a new mode from an EDID detailed timing section
2161 * @dev: DRM device (needed to create new mode)
2162 * @edid: EDID block
2163 * @timing: EDID detailed timing info
2164 * @quirks: quirks to apply
2165 *
2166 * An EDID detailed timing block contains enough info for us to create and
2167 * return a new struct drm_display_mode.
2168 */
2169static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
2170 struct edid *edid,
2171 struct detailed_timing *timing,
2172 u32 quirks)
2173{
2174 struct drm_display_mode *mode;
2175 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
0454beab
MD		 2176 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
2177 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
2178 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
2179 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
e14cbee4
MD		 2180 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
2181 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
16dad1d7 2182 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
e14cbee4 2183 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
f453ba04 2184
fc438966 2185 /* ignore tiny modes */
0454beab 2186 if (hactive < 64 || vactive < 64)
fc438966
AJ		 2187 return NULL;
2188
0454beab 2189 if (pt->misc & DRM_EDID_PT_STEREO) {
c7d015f3 2190 DRM_DEBUG_KMS("stereo mode not supported\n");
f453ba04
DA		 2191 return NULL;
2192 }
0454beab 2193 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
c7d015f3 2194 DRM_DEBUG_KMS("composite sync not supported\n");
f453ba04
DA		 2195 }
2196
fcb45611
ZY		 2197 /* it is incorrect if hsync/vsync width is zero */
2198 if (!hsync_pulse_width || !vsync_pulse_width) {
2199 DRM_DEBUG_KMS("Incorrect Detailed timing. "
2200 "Wrong Hsync/Vsync pulse width\n");
2201 return NULL;
2202 }
bc42aabc
AJ		 2203
2204 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
2205 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
2206 if (!mode)
2207 return NULL;
2208
2209 goto set_size;
2210 }
2211
f453ba04
DA		 2212 mode = drm_mode_create(dev);
2213 if (!mode)
2214 return NULL;
2215
f453ba04 2216 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
0454beab
MD		 2217 timing->pixel_clock = cpu_to_le16(1088);
2218
2219 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
2220
2221 mode->hdisplay = hactive;
2222 mode->hsync_start = mode->hdisplay + hsync_offset;
2223 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
2224 mode->htotal = mode->hdisplay + hblank;
2225
2226 mode->vdisplay = vactive;
2227 mode->vsync_start = mode->vdisplay + vsync_offset;
2228 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
2229 mode->vtotal = mode->vdisplay + vblank;
f453ba04 2230
7064fef5
JB		 2231 /* Some EDIDs have bogus h/vtotal values */
2232 if (mode->hsync_end > mode->htotal)
2233 mode->htotal = mode->hsync_end + 1;
2234 if (mode->vsync_end > mode->vtotal)
2235 mode->vtotal = mode->vsync_end + 1;
2236
b58db2c6 2237 drm_mode_do_interlace_quirk(mode, pt);
f453ba04
DA		 2238
2239 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
0454beab 2240 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
f453ba04
DA		 2241 }
2242
0454beab
MD		 2243 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
2244 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
2245 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
2246 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
f453ba04 2247
bc42aabc 2248set_size:
e14cbee4
MD		 2249 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
2250 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
f453ba04
DA		 2251
2252 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
2253 mode->width_mm *= 10;
2254 mode->height_mm *= 10;
2255 }
2256
2257 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
2258 mode->width_mm = edid->width_cm * 10;
2259 mode->height_mm = edid->height_cm * 10;
2260 }
2261
bc42aabc 2262 mode->type = DRM_MODE_TYPE_DRIVER;
c19b3b0f 2263 mode->vrefresh = drm_mode_vrefresh(mode);
bc42aabc
AJ		 2264 drm_mode_set_name(mode);
2265
f453ba04
DA		 2266 return mode;
2267}
2268
b17e52ef 2269static bool
b1f559ec
CW		 2270mode_in_hsync_range(const struct drm_display_mode *mode,
2271 struct edid *edid, u8 *t)
b17e52ef
AJ		 2272{
2273 int hsync, hmin, hmax;
2274
2275 hmin = t[7];
2276 if (edid->revision >= 4)
2277 hmin += ((t[4] & 0x04) ? 255 : 0);
2278 hmax = t[8];
2279 if (edid->revision >= 4)
2280 hmax += ((t[4] & 0x08) ? 255 : 0);
07a5e632 2281 hsync = drm_mode_hsync(mode);
07a5e632 2282
b17e52ef
AJ		 2283 return (hsync <= hmax && hsync >= hmin);
2284}
2285
2286static bool
b1f559ec
CW		 2287mode_in_vsync_range(const struct drm_display_mode *mode,
2288 struct edid *edid, u8 *t)
b17e52ef
AJ		 2289{
2290 int vsync, vmin, vmax;
2291
2292 vmin = t[5];
2293 if (edid->revision >= 4)
2294 vmin += ((t[4] & 0x01) ? 255 : 0);
2295 vmax = t[6];
2296 if (edid->revision >= 4)
2297 vmax += ((t[4] & 0x02) ? 255 : 0);
2298 vsync = drm_mode_vrefresh(mode);
2299
2300 return (vsync <= vmax && vsync >= vmin);
2301}
2302
2303static u32
2304range_pixel_clock(struct edid *edid, u8 *t)
2305{
2306 /* unspecified */
2307 if (t[9] == 0 || t[9] == 255)
2308 return 0;
2309
2310 /* 1.4 with CVT support gives us real precision, yay */
2311 if (edid->revision >= 4 && t[10] == 0x04)
2312 return (t[9] * 10000) - ((t[12] >> 2) * 250);
2313
2314 /* 1.3 is pathetic, so fuzz up a bit */
2315 return t[9] * 10000 + 5001;
2316}
2317
b17e52ef 2318static bool
b1f559ec 2319mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
b17e52ef
AJ		 2320 struct detailed_timing *timing)
2321{
2322 u32 max_clock;
2323 u8 *t = (u8 *)timing;
2324
2325 if (!mode_in_hsync_range(mode, edid, t))
07a5e632
AJ		 2326 return false;
2327
b17e52ef 2328 if (!mode_in_vsync_range(mode, edid, t))
07a5e632
AJ		 2329 return false;
2330
b17e52ef 2331 if ((max_clock = range_pixel_clock(edid, t)))
07a5e632
AJ		 2332 if (mode->clock > max_clock)
2333 return false;
b17e52ef
AJ		 2334
2335 /* 1.4 max horizontal check */
2336 if (edid->revision >= 4 && t[10] == 0x04)
2337 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
2338 return false;
2339
2340 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
2341 return false;
07a5e632
AJ		 2342
2343 return true;
2344}
2345
7b668ebe
TI		 2346static bool valid_inferred_mode(const struct drm_connector *connector,
2347 const struct drm_display_mode *mode)
2348{
85f8fcd6 2349 const struct drm_display_mode *m;
7b668ebe
TI		 2350 bool ok = false;
2351
2352 list_for_each_entry(m, &connector->probed_modes, head) {
2353 if (mode->hdisplay == m->hdisplay &&
2354 mode->vdisplay == m->vdisplay &&
2355 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
2356 return false; /* duplicated */
2357 if (mode->hdisplay <= m->hdisplay &&
2358 mode->vdisplay <= m->vdisplay)
2359 ok = true;
2360 }
2361 return ok;
2362}
2363
b17e52ef 2364static int
cd4cd3de 2365drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
b17e52ef 2366 struct detailed_timing *timing)
07a5e632
AJ		 2367{
2368 int i, modes = 0;
2369 struct drm_display_mode *newmode;
2370 struct drm_device *dev = connector->dev;
2371
a6b21831 2372 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
7b668ebe
TI		 2373 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
2374 valid_inferred_mode(connector, drm_dmt_modes + i)) {
07a5e632
AJ		 2375 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
2376 if (newmode) {
2377 drm_mode_probed_add(connector, newmode);
2378 modes++;
2379 }
2380 }
2381 }
2382
2383 return modes;
2384}
2385
c09dedb7
TI		 2386/* fix up 1366x768 mode from 1368x768;
2387 * GFT/CVT can't express 1366 width which isn't dividable by 8
2388 */
969218fe 2389void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
c09dedb7
TI		 2390{
2391 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
2392 mode->hdisplay = 1366;
2393 mode->hsync_start--;
2394 mode->hsync_end--;
2395 drm_mode_set_name(mode);
2396 }
2397}
2398
b309bd37
AJ		 2399static int
2400drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
2401 struct detailed_timing *timing)
2402{
2403 int i, modes = 0;
2404 struct drm_display_mode *newmode;
2405 struct drm_device *dev = connector->dev;
2406
a6b21831 2407 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
b309bd37
AJ		 2408 const struct minimode *m = &extra_modes[i];
2409 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
fc48f169
TI		 2410 if (!newmode)
2411 return modes;
b309bd37 2412
969218fe 2413 drm_mode_fixup_1366x768(newmode);
7b668ebe
TI		 2414 if (!mode_in_range(newmode, edid, timing) ||
2415 !valid_inferred_mode(connector, newmode)) {
b309bd37
AJ		 2416 drm_mode_destroy(dev, newmode);
2417 continue;
2418 }
2419
2420 drm_mode_probed_add(connector, newmode);
2421 modes++;
2422 }
2423
2424 return modes;
2425}
2426
2427static int
2428drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2429 struct detailed_timing *timing)
2430{
2431 int i, modes = 0;
2432 struct drm_display_mode *newmode;
2433 struct drm_device *dev = connector->dev;
2434 bool rb = drm_monitor_supports_rb(edid);
2435
a6b21831 2436 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
b309bd37
AJ		 2437 const struct minimode *m = &extra_modes[i];
2438 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
fc48f169
TI		 2439 if (!newmode)
2440 return modes;
b309bd37 2441
969218fe 2442 drm_mode_fixup_1366x768(newmode);
7b668ebe
TI		 2443 if (!mode_in_range(newmode, edid, timing) ||
2444 !valid_inferred_mode(connector, newmode)) {
b309bd37
AJ		 2445 drm_mode_destroy(dev, newmode);
2446 continue;
2447 }
2448
2449 drm_mode_probed_add(connector, newmode);
2450 modes++;
2451 }
2452
2453 return modes;
2454}
2455
13931579
AJ		 2456static void
2457do_inferred_modes(struct detailed_timing *timing, void *c)
9340d8cf 2458{
13931579
AJ		 2459 struct detailed_mode_closure *closure = c;
2460 struct detailed_non_pixel *data = &timing->data.other_data;
b309bd37 2461 struct detailed_data_monitor_range *range = &data->data.range;
9340d8cf 2462
cb21aafe
AJ		 2463 if (data->type != EDID_DETAIL_MONITOR_RANGE)
2464 return;
2465
2466 closure->modes += drm_dmt_modes_for_range(closure->connector,
2467 closure->edid,
2468 timing);
b309bd37
AJ		 2469
2470 if (!version_greater(closure->edid, 1, 1))
2471 return; /* GTF not defined yet */
2472
2473 switch (range->flags) {
2474 case 0x02: /* secondary gtf, XXX could do more */
2475 case 0x00: /* default gtf */
2476 closure->modes += drm_gtf_modes_for_range(closure->connector,
2477 closure->edid,
2478 timing);
2479 break;
2480 case 0x04: /* cvt, only in 1.4+ */
2481 if (!version_greater(closure->edid, 1, 3))
2482 break;
2483
2484 closure->modes += drm_cvt_modes_for_range(closure->connector,
2485 closure->edid,
2486 timing);
2487 break;
2488 case 0x01: /* just the ranges, no formula */
2489 default:
2490 break;
2491 }
13931579 2492}
69da3015 2493
13931579
AJ		 2494static int
2495add_inferred_modes(struct drm_connector *connector, struct edid *edid)
2496{
2497 struct detailed_mode_closure closure = {
d456ea2e
JL		 2498 .connector = connector,
2499 .edid = edid,
13931579 2500 };
9340d8cf 2501
13931579
AJ		 2502 if (version_greater(edid, 1, 0))
2503 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
2504 &closure);
9340d8cf 2505
13931579 2506 return closure.modes;
9340d8cf
AJ		 2507}
2508
2255be14
AJ		 2509static int
2510drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
2511{
2512 int i, j, m, modes = 0;
2513 struct drm_display_mode *mode;
f3a32d74 2514 u8 *est = ((u8 *)timing) + 6;
2255be14
AJ		 2515
2516 for (i = 0; i < 6; i++) {
891a7469 2517 for (j = 7; j >= 0; j--) {
2255be14 2518 m = (i * 8) + (7 - j);
3c581411 2519 if (m >= ARRAY_SIZE(est3_modes))
2255be14
AJ		 2520 break;
2521 if (est[i] & (1 << j)) {
1d42bbc8
DA		 2522 mode = drm_mode_find_dmt(connector->dev,
2523 est3_modes[m].w,
2524 est3_modes[m].h,
f6e252ba
AJ		 2525 est3_modes[m].r,
2526 est3_modes[m].rb);
2255be14
AJ		 2527 if (mode) {
2528 drm_mode_probed_add(connector, mode);
2529 modes++;
2530 }
2531 }
2532 }
2533 }
2534
2535 return modes;
2536}
2537
13931579
AJ		 2538static void
2539do_established_modes(struct detailed_timing *timing, void *c)
9cf00977 2540{
13931579 2541 struct detailed_mode_closure *closure = c;
9cf00977 2542 struct detailed_non_pixel *data = &timing->data.other_data;
9cf00977 2543
13931579
AJ		 2544 if (data->type == EDID_DETAIL_EST_TIMINGS)
2545 closure->modes += drm_est3_modes(closure->connector, timing);
2546}
9cf00977 2547
13931579
AJ		 2548/**
2549 * add_established_modes - get est. modes from EDID and add them
db6cf833 2550 * @connector: connector to add mode(s) to
13931579
AJ		 2551 * @edid: EDID block to scan
2552 *
2553 * Each EDID block contains a bitmap of the supported "established modes" list
2554 * (defined above). Tease them out and add them to the global modes list.
2555 */
2556static int
2557add_established_modes(struct drm_connector *connector, struct edid *edid)
2558{
2559 struct drm_device *dev = connector->dev;
2560 unsigned long est_bits = edid->established_timings.t1 |
2561 (edid->established_timings.t2 << 8) |
2562 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
2563 int i, modes = 0;
2564 struct detailed_mode_closure closure = {
d456ea2e
JL		 2565 .connector = connector,
2566 .edid = edid,
13931579 2567 };
9cf00977 2568
13931579
AJ		 2569 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
2570 if (est_bits & (1<<i)) {
2571 struct drm_display_mode *newmode;
2572 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
2573 if (newmode) {
2574 drm_mode_probed_add(connector, newmode);
2575 modes++;
2576 }
2577 }
9cf00977
AJ		 2578 }
2579
13931579
AJ		 2580 if (version_greater(edid, 1, 0))
2581 drm_for_each_detailed_block((u8 *)edid,
2582 do_established_modes, &closure);
2583
2584 return modes + closure.modes;
2585}
2586
2587static void
2588do_standard_modes(struct detailed_timing *timing, void *c)
2589{
2590 struct detailed_mode_closure *closure = c;
2591 struct detailed_non_pixel *data = &timing->data.other_data;
2592 struct drm_connector *connector = closure->connector;
2593 struct edid *edid = closure->edid;
2594
2595 if (data->type == EDID_DETAIL_STD_MODES) {
2596 int i;
9cf00977
AJ		 2597 for (i = 0; i < 6; i++) {
2598 struct std_timing *std;
2599 struct drm_display_mode *newmode;
2600
2601 std = &data->data.timings[i];
464fdeca 2602 newmode = drm_mode_std(connector, edid, std);
9cf00977
AJ		 2603 if (newmode) {
2604 drm_mode_probed_add(connector, newmode);
13931579 2605 closure->modes++;
9cf00977
AJ		 2606 }
2607 }
9cf00977 2608 }
9cf00977
AJ		 2609}
2610
f453ba04 2611/**
13931579 2612 * add_standard_modes - get std. modes from EDID and add them
db6cf833 2613 * @connector: connector to add mode(s) to
f453ba04 2614 * @edid: EDID block to scan
f453ba04 2615 *
13931579
AJ		 2616 * Standard modes can be calculated using the appropriate standard (DMT,
2617 * GTF or CVT. Grab them from @edid and add them to the list.
f453ba04 2618 */
13931579
AJ		 2619static int
2620add_standard_modes(struct drm_connector *connector, struct edid *edid)
f453ba04 2621{
9cf00977 2622 int i, modes = 0;
13931579 2623 struct detailed_mode_closure closure = {
d456ea2e
JL		 2624 .connector = connector,
2625 .edid = edid,
13931579
AJ		 2626 };
2627
2628 for (i = 0; i < EDID_STD_TIMINGS; i++) {
2629 struct drm_display_mode *newmode;
2630
2631 newmode = drm_mode_std(connector, edid,
464fdeca 2632 &edid->standard_timings[i]);
13931579
AJ		 2633 if (newmode) {
2634 drm_mode_probed_add(connector, newmode);
2635 modes++;
2636 }
2637 }
2638
2639 if (version_greater(edid, 1, 0))
2640 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
2641 &closure);
2642
2643 /* XXX should also look for standard codes in VTB blocks */
2644
2645 return modes + closure.modes;
2646}
f453ba04 2647
13931579
AJ		 2648static int drm_cvt_modes(struct drm_connector *connector,
2649 struct detailed_timing *timing)
2650{
2651 int i, j, modes = 0;
2652 struct drm_display_mode *newmode;
2653 struct drm_device *dev = connector->dev;
2654 struct cvt_timing *cvt;
2655 const int rates[] = { 60, 85, 75, 60, 50 };
2656 const u8 empty[3] = { 0, 0, 0 };
a327f6b8 2657
13931579
AJ		 2658 for (i = 0; i < 4; i++) {
2659 int uninitialized_var(width), height;
2660 cvt = &(timing->data.other_data.data.cvt[i]);
f453ba04 2661
13931579 2662 if (!memcmp(cvt->code, empty, 3))
9cf00977 2663 continue;
f453ba04 2664
13931579
AJ		 2665 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
2666 switch (cvt->code[1] & 0x0c) {
2667 case 0x00:
2668 width = height * 4 / 3;
2669 break;
2670 case 0x04:
2671 width = height * 16 / 9;
2672 break;
2673 case 0x08:
2674 width = height * 16 / 10;
2675 break;
2676 case 0x0c:
2677 width = height * 15 / 9;
2678 break;
2679 }
2680
2681 for (j = 1; j < 5; j++) {
2682 if (cvt->code[2] & (1 << j)) {
2683 newmode = drm_cvt_mode(dev, width, height,
2684 rates[j], j == 0,
2685 false, false);
2686 if (newmode) {
2687 drm_mode_probed_add(connector, newmode);
2688 modes++;
2689 }
2690 }
2691 }
f453ba04
DA		 2692 }
2693
2694 return modes;
2695}
9cf00977 2696
13931579
AJ		 2697static void
2698do_cvt_mode(struct detailed_timing *timing, void *c)
882f0219 2699{
13931579
AJ		 2700 struct detailed_mode_closure *closure = c;
2701 struct detailed_non_pixel *data = &timing->data.other_data;
882f0219 2702
13931579
AJ		 2703 if (data->type == EDID_DETAIL_CVT_3BYTE)
2704 closure->modes += drm_cvt_modes(closure->connector, timing);
2705}
882f0219 2706
13931579
AJ		 2707static int
2708add_cvt_modes(struct drm_connector *connector, struct edid *edid)
2709{
2710 struct detailed_mode_closure closure = {
d456ea2e
JL		 2711 .connector = connector,
2712 .edid = edid,
13931579 2713 };
882f0219 2714
13931579
AJ		 2715 if (version_greater(edid, 1, 2))
2716 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
882f0219 2717
13931579 2718 /* XXX should also look for CVT codes in VTB blocks */
882f0219 2719
13931579
AJ		 2720 return closure.modes;
2721}
2722
fa3a7340
VS		 2723static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
2724
13931579
AJ		 2725static void
2726do_detailed_mode(struct detailed_timing *timing, void *c)
2727{
2728 struct detailed_mode_closure *closure = c;
2729 struct drm_display_mode *newmode;
2730
2731 if (timing->pixel_clock) {
2732 newmode = drm_mode_detailed(closure->connector->dev,
2733 closure->edid, timing,
2734 closure->quirks);
2735 if (!newmode)
2736 return;
2737
2738 if (closure->preferred)
2739 newmode->type |= DRM_MODE_TYPE_PREFERRED;
2740
fa3a7340
VS		 2741 /*
2742 * Detailed modes are limited to 10kHz pixel clock resolution,
2743 * so fix up anything that looks like CEA/HDMI mode, but the clock
2744 * is just slightly off.
2745 */
2746 fixup_detailed_cea_mode_clock(newmode);
2747
13931579
AJ		 2748 drm_mode_probed_add(closure->connector, newmode);
2749 closure->modes++;
2750 closure->preferred = 0;
882f0219 2751 }
13931579 2752}
882f0219 2753
13931579
AJ		 2754/*
2755 * add_detailed_modes - Add modes from detailed timings
2756 * @connector: attached connector
2757 * @edid: EDID block to scan
2758 * @quirks: quirks to apply
2759 */
2760static int
2761add_detailed_modes(struct drm_connector *connector, struct edid *edid,
2762 u32 quirks)
2763{
2764 struct detailed_mode_closure closure = {
d456ea2e
JL		 2765 .connector = connector,
2766 .edid = edid,
2767 .preferred = 1,
2768 .quirks = quirks,
13931579
AJ		 2769 };
2770
2771 if (closure.preferred && !version_greater(edid, 1, 3))
2772 closure.preferred =
2773 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
2774
2775 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
2776
2777 return closure.modes;
882f0219 2778}
f453ba04 2779
8fe9790d 2780#define AUDIO_BLOCK 0x01
54ac76f8 2781#define VIDEO_BLOCK 0x02
f23c20c8 2782#define VENDOR_BLOCK 0x03
76adaa34 2783#define SPEAKER_BLOCK 0x04
b1edd6a6 2784#define VIDEO_CAPABILITY_BLOCK 0x07
8fe9790d 2785#define EDID_BASIC_AUDIO (1 << 6)
a988bc72
LPC		 2786#define EDID_CEA_YCRCB444 (1 << 5)
2787#define EDID_CEA_YCRCB422 (1 << 4)
b1edd6a6 2788#define EDID_CEA_VCDB_QS (1 << 6)
8fe9790d 2789
d4e4a31d 2790/*
8fe9790d 2791 * Search EDID for CEA extension block.
f23c20c8 2792 */
40d9b043 2793static u8 *drm_find_edid_extension(struct edid *edid, int ext_id)
f23c20c8 2794{
8fe9790d
ZW		 2795 u8 *edid_ext = NULL;
2796 int i;
f23c20c8
ML		 2797
2798 /* No EDID or EDID extensions */
2799 if (edid == NULL || edid->extensions == 0)
8fe9790d 2800 return NULL;
f23c20c8 2801
f23c20c8 2802 /* Find CEA extension */
7466f4cc 2803 for (i = 0; i < edid->extensions; i++) {
8fe9790d 2804 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
40d9b043 2805 if (edid_ext[0] == ext_id)
f23c20c8
ML		 2806 break;
2807 }
2808
7466f4cc 2809 if (i == edid->extensions)
8fe9790d
ZW		 2810 return NULL;
2811
2812 return edid_ext;
2813}
2814
40d9b043
DA		 2815static u8 *drm_find_cea_extension(struct edid *edid)
2816{
2817 return drm_find_edid_extension(edid, CEA_EXT);
2818}
2819
2820static u8 *drm_find_displayid_extension(struct edid *edid)
2821{
2822 return drm_find_edid_extension(edid, DISPLAYID_EXT);
2823}
2824
e6e79209
VS		 2825/*
2826 * Calculate the alternate clock for the CEA mode
2827 * (60Hz vs. 59.94Hz etc.)
2828 */
2829static unsigned int
2830cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
2831{
2832 unsigned int clock = cea_mode->clock;
2833
2834 if (cea_mode->vrefresh % 6 != 0)
2835 return clock;
2836
2837 /*
2838 * edid_cea_modes contains the 59.94Hz
2839 * variant for 240 and 480 line modes,
2840 * and the 60Hz variant otherwise.
2841 */
2842 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
9afd808c 2843 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
e6e79209 2844 else
9afd808c 2845 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
e6e79209
VS		 2846
2847 return clock;
2848}
2849
c45a4e46
VS		 2850static bool
2851cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
2852{
2853 /*
2854 * For certain VICs the spec allows the vertical
2855 * front porch to vary by one or two lines.
2856 *
2857 * cea_modes[] stores the variant with the shortest
2858 * vertical front porch. We can adjust the mode to
2859 * get the other variants by simply increasing the
2860 * vertical front porch length.
2861 */
2862 BUILD_BUG_ON(edid_cea_modes[8].vtotal != 262 ||
2863 edid_cea_modes[9].vtotal != 262 ||
2864 edid_cea_modes[12].vtotal != 262 ||
2865 edid_cea_modes[13].vtotal != 262 ||
2866 edid_cea_modes[23].vtotal != 312 ||
2867 edid_cea_modes[24].vtotal != 312 ||
2868 edid_cea_modes[27].vtotal != 312 ||
2869 edid_cea_modes[28].vtotal != 312);
2870
2871 if (((vic == 8 || vic == 9 ||
2872 vic == 12 || vic == 13) && mode->vtotal < 263) ||
2873 ((vic == 23 || vic == 24 ||
2874 vic == 27 || vic == 28) && mode->vtotal < 314)) {
2875 mode->vsync_start++;
2876 mode->vsync_end++;
2877 mode->vtotal++;
2878
2879 return true;
2880 }
2881
2882 return false;
2883}
2884
4c6bcf44
VS		 2885static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
2886 unsigned int clock_tolerance)
2887{
d9278b4c 2888 u8 vic;
4c6bcf44
VS		 2889
2890 if (!to_match->clock)
2891 return 0;
2892
d9278b4c 2893 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
c45a4e46 2894 struct drm_display_mode cea_mode = edid_cea_modes[vic];
4c6bcf44
VS		 2895 unsigned int clock1, clock2;
2896
2897 /* Check both 60Hz and 59.94Hz */
c45a4e46
VS		 2898 clock1 = cea_mode.clock;
2899 clock2 = cea_mode_alternate_clock(&cea_mode);
4c6bcf44
VS		 2900
2901 if (abs(to_match->clock - clock1) > clock_tolerance &&
2902 abs(to_match->clock - clock2) > clock_tolerance)
2903 continue;
2904
c45a4e46
VS		 2905 do {
2906 if (drm_mode_equal_no_clocks_no_stereo(to_match, &cea_mode))
2907 return vic;
2908 } while (cea_mode_alternate_timings(vic, &cea_mode));
4c6bcf44
VS		 2909 }
2910
2911 return 0;
2912}
2913
18316c8c
TR		 2914/**
2915 * drm_match_cea_mode - look for a CEA mode matching given mode
2916 * @to_match: display mode
2917 *
db6cf833 2918 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
18316c8c 2919 * mode.
a4799037 2920 */
18316c8c 2921u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
a4799037 2922{
d9278b4c 2923 u8 vic;
a4799037 2924
a90b590e
VS		 2925 if (!to_match->clock)
2926 return 0;
2927
d9278b4c 2928 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
c45a4e46 2929 struct drm_display_mode cea_mode = edid_cea_modes[vic];
a90b590e
VS		 2930 unsigned int clock1, clock2;
2931
a90b590e 2932 /* Check both 60Hz and 59.94Hz */
c45a4e46
VS		 2933 clock1 = cea_mode.clock;
2934 clock2 = cea_mode_alternate_clock(&cea_mode);
a4799037 2935
c45a4e46
VS		 2936 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
2937 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
2938 continue;
2939
2940 do {
2941 if (drm_mode_equal_no_clocks_no_stereo(to_match, &cea_mode))
2942 return vic;
2943 } while (cea_mode_alternate_timings(vic, &cea_mode));
a4799037 2944 }
c45a4e46 2945
a4799037
SM		 2946 return 0;
2947}
2948EXPORT_SYMBOL(drm_match_cea_mode);
2949
d9278b4c
JN		 2950static bool drm_valid_cea_vic(u8 vic)
2951{
2952 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes);
2953}
2954
0967e6a5
VK		 2955/**
2956 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to
2957 * the input VIC from the CEA mode list
2958 * @video_code: ID given to each of the CEA modes
2959 *
2960 * Returns picture aspect ratio
2961 */
2962enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
2963{
d9278b4c 2964 return edid_cea_modes[video_code].picture_aspect_ratio;
0967e6a5
VK		 2965}
2966EXPORT_SYMBOL(drm_get_cea_aspect_ratio);
2967
3f2f6533
LD		 2968/*
2969 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
2970 * specific block).
2971 *
2972 * It's almost like cea_mode_alternate_clock(), we just need to add an
2973 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this
2974 * one.
2975 */
2976static unsigned int
2977hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
2978{
2979 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160)
2980 return hdmi_mode->clock;
2981
2982 return cea_mode_alternate_clock(hdmi_mode);
2983}
2984
4c6bcf44
VS		 2985static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
2986 unsigned int clock_tolerance)
2987{
d9278b4c 2988 u8 vic;
4c6bcf44
VS		 2989
2990 if (!to_match->clock)
2991 return 0;
2992
d9278b4c
JN		 2993 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
2994 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4c6bcf44
VS		 2995 unsigned int clock1, clock2;
2996
2997 /* Make sure to also match alternate clocks */
2998 clock1 = hdmi_mode->clock;
2999 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3000
3001 if (abs(to_match->clock - clock1) > clock_tolerance &&
3002 abs(to_match->clock - clock2) > clock_tolerance)
3003 continue;
3004
3005 if (drm_mode_equal_no_clocks(to_match, hdmi_mode))
d9278b4c 3006 return vic;
4c6bcf44
VS		 3007 }
3008
3009 return 0;
3010}
3011
3f2f6533
LD		 3012/*
3013 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
3014 * @to_match: display mode
3015 *
3016 * An HDMI mode is one defined in the HDMI vendor specific block.
3017 *
3018 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
3019 */
3020static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
3021{
d9278b4c 3022 u8 vic;
3f2f6533
LD		 3023
3024 if (!to_match->clock)
3025 return 0;
3026
d9278b4c
JN		 3027 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3028 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3f2f6533
LD		 3029 unsigned int clock1, clock2;
3030
3031 /* Make sure to also match alternate clocks */
3032 clock1 = hdmi_mode->clock;
3033 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3034
3035 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
3036 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
f2ecf2e3 3037 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode))
d9278b4c 3038 return vic;
3f2f6533
LD		 3039 }
3040 return 0;
3041}
3042
d9278b4c
JN		 3043static bool drm_valid_hdmi_vic(u8 vic)
3044{
3045 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
3046}
3047
e6e79209
VS		 3048static int
3049add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
3050{
3051 struct drm_device *dev = connector->dev;
3052 struct drm_display_mode *mode, *tmp;
3053 LIST_HEAD(list);
3054 int modes = 0;
3055
3056 /* Don't add CEA modes if the CEA extension block is missing */
3057 if (!drm_find_cea_extension(edid))
3058 return 0;
3059
3060 /*
3061 * Go through all probed modes and create a new mode
3062 * with the alternate clock for certain CEA modes.
3063 */
3064 list_for_each_entry(mode, &connector->probed_modes, head) {
3f2f6533 3065 const struct drm_display_mode *cea_mode = NULL;
e6e79209 3066 struct drm_display_mode *newmode;
d9278b4c 3067 u8 vic = drm_match_cea_mode(mode);
e6e79209
VS		 3068 unsigned int clock1, clock2;
3069
d9278b4c
JN		 3070 if (drm_valid_cea_vic(vic)) {
3071 cea_mode = &edid_cea_modes[vic];
3f2f6533
LD		 3072 clock2 = cea_mode_alternate_clock(cea_mode);
3073 } else {
d9278b4c
JN		 3074 vic = drm_match_hdmi_mode(mode);
3075 if (drm_valid_hdmi_vic(vic)) {
3076 cea_mode = &edid_4k_modes[vic];
3f2f6533
LD		 3077 clock2 = hdmi_mode_alternate_clock(cea_mode);
3078 }
3079 }
e6e79209 3080
3f2f6533
LD		 3081 if (!cea_mode)
3082 continue;
e6e79209
VS		 3083
3084 clock1 = cea_mode->clock;
e6e79209
VS		 3085
3086 if (clock1 == clock2)
3087 continue;
3088
3089 if (mode->clock != clock1 && mode->clock != clock2)
3090 continue;
3091
3092 newmode = drm_mode_duplicate(dev, cea_mode);
3093 if (!newmode)
3094 continue;
3095
27130212
DL		 3096 /* Carry over the stereo flags */
3097 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
3098
e6e79209
VS		 3099 /*
3100 * The current mode could be either variant. Make
3101 * sure to pick the "other" clock for the new mode.
3102 */
3103 if (mode->clock != clock1)
3104 newmode->clock = clock1;
3105 else
3106 newmode->clock = clock2;
3107
3108 list_add_tail(&newmode->head, &list);
3109 }
3110
3111 list_for_each_entry_safe(mode, tmp, &list, head) {
3112 list_del(&mode->head);
3113 drm_mode_probed_add(connector, mode);
3114 modes++;
3115 }
3116
3117 return modes;
3118}
a4799037 3119
8ec6e075
SS		 3120static u8 svd_to_vic(u8 svd)
3121{
3122 /* 0-6 bit vic, 7th bit native mode indicator */
3123 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
3124 return svd & 127;
3125
3126 return svd;
3127}
3128
aff04ace
TW		 3129static struct drm_display_mode *
3130drm_display_mode_from_vic_index(struct drm_connector *connector,
3131 const u8 *video_db, u8 video_len,
3132 u8 video_index)
54ac76f8
CS		 3133{
3134 struct drm_device *dev = connector->dev;
aff04ace 3135 struct drm_display_mode *newmode;
d9278b4c 3136 u8 vic;
54ac76f8 3137
aff04ace
TW		 3138 if (video_db == NULL || video_index >= video_len)
3139 return NULL;
3140
3141 /* CEA modes are numbered 1..127 */
8ec6e075 3142 vic = svd_to_vic(video_db[video_index]);
d9278b4c 3143 if (!drm_valid_cea_vic(vic))
aff04ace
TW		 3144 return NULL;
3145
d9278b4c 3146 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
409bbf1e
DL		 3147 if (!newmode)
3148 return NULL;
3149
aff04ace
TW		 3150 newmode->vrefresh = 0;
3151
3152 return newmode;
3153}
3154
3155static int
3156do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
3157{
3158 int i, modes = 0;
3159
3160 for (i = 0; i < len; i++) {
3161 struct drm_display_mode *mode;
3162 mode = drm_display_mode_from_vic_index(connector, db, len, i);
3163 if (mode) {
3164 drm_mode_probed_add(connector, mode);
3165 modes++;
54ac76f8
CS		 3166 }
3167 }
3168
3169 return modes;
3170}
3171
c858cfca
DL		 3172struct stereo_mandatory_mode {
3173 int width, height, vrefresh;
3174 unsigned int flags;
3175};
3176
3177static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
f7e121b7
DL		 3178 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3179 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
c858cfca
DL		 3180 { 1920, 1080, 50,
3181 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3182 { 1920, 1080, 60,
3183 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
f7e121b7
DL		 3184 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3185 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
3186 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3187 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
c858cfca
DL		 3188};
3189
3190static bool
3191stereo_match_mandatory(const struct drm_display_mode *mode,
3192 const struct stereo_mandatory_mode *stereo_mode)
3193{
3194 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
3195
3196 return mode->hdisplay == stereo_mode->width &&
3197 mode->vdisplay == stereo_mode->height &&
3198 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
3199 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
3200}
3201
c858cfca
DL		 3202static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
3203{
3204 struct drm_device *dev = connector->dev;
3205 const struct drm_display_mode *mode;
3206 struct list_head stereo_modes;
f7e121b7 3207 int modes = 0, i;
c858cfca
DL		 3208
3209 INIT_LIST_HEAD(&stereo_modes);
3210
3211 list_for_each_entry(mode, &connector->probed_modes, head) {
f7e121b7
DL		 3212 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
3213 const struct stereo_mandatory_mode *mandatory;
c858cfca
DL		 3214 struct drm_display_mode *new_mode;
3215
f7e121b7
DL		 3216 if (!stereo_match_mandatory(mode,
3217 &stereo_mandatory_modes[i]))
3218 continue;
c858cfca 3219
f7e121b7 3220 mandatory = &stereo_mandatory_modes[i];
c858cfca
DL		 3221 new_mode = drm_mode_duplicate(dev, mode);
3222 if (!new_mode)
3223 continue;
3224
f7e121b7 3225 new_mode->flags |= mandatory->flags;
c858cfca
DL		 3226 list_add_tail(&new_mode->head, &stereo_modes);
3227 modes++;
f7e121b7 3228 }
c858cfca
DL		 3229 }
3230
3231 list_splice_tail(&stereo_modes, &connector->probed_modes);
3232
3233 return modes;
3234}
3235
1deee8d7
DL		 3236static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
3237{
3238 struct drm_device *dev = connector->dev;
3239 struct drm_display_mode *newmode;
3240
d9278b4c 3241 if (!drm_valid_hdmi_vic(vic)) {
1deee8d7
DL		 3242 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
3243 return 0;
3244 }
3245
3246 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
3247 if (!newmode)
3248 return 0;
3249
3250 drm_mode_probed_add(connector, newmode);
3251
3252 return 1;
3253}
3254
fbf46025
TW		 3255static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
3256 const u8 *video_db, u8 video_len, u8 video_index)
3257{
fbf46025
TW		 3258 struct drm_display_mode *newmode;
3259 int modes = 0;
fbf46025
TW		 3260
3261 if (structure & (1 << 0)) {
aff04ace
TW		 3262 newmode = drm_display_mode_from_vic_index(connector, video_db,
3263 video_len,
3264 video_index);
fbf46025
TW		 3265 if (newmode) {
3266 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
3267 drm_mode_probed_add(connector, newmode);
3268 modes++;
3269 }
3270 }
3271 if (structure & (1 << 6)) {
aff04ace
TW		 3272 newmode = drm_display_mode_from_vic_index(connector, video_db,
3273 video_len,
3274 video_index);
fbf46025
TW		 3275 if (newmode) {
3276 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3277 drm_mode_probed_add(connector, newmode);
3278 modes++;
3279 }
3280 }
3281 if (structure & (1 << 8)) {
aff04ace
TW		 3282 newmode = drm_display_mode_from_vic_index(connector, video_db,
3283 video_len,
3284 video_index);
fbf46025 3285 if (newmode) {
89570eeb 3286 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
fbf46025
TW		 3287 drm_mode_probed_add(connector, newmode);
3288 modes++;
3289 }
3290 }
3291
3292 return modes;
3293}
3294
7ebe1963
LD		 3295/*
3296 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
3297 * @connector: connector corresponding to the HDMI sink
3298 * @db: start of the CEA vendor specific block
3299 * @len: length of the CEA block payload, ie. one can access up to db[len]
3300 *
c858cfca
DL		 3301 * Parses the HDMI VSDB looking for modes to add to @connector. This function
3302 * also adds the stereo 3d modes when applicable.
7ebe1963
LD		 3303 */
3304static int
fbf46025
TW		 3305do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
3306 const u8 *video_db, u8 video_len)
7ebe1963 3307{
0e5083aa 3308 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
fbf46025
TW		 3309 u8 vic_len, hdmi_3d_len = 0;
3310 u16 mask;
3311 u16 structure_all;
7ebe1963
LD		 3312
3313 if (len < 8)
3314 goto out;
3315
3316 /* no HDMI_Video_Present */
3317 if (!(db[8] & (1 << 5)))
3318 goto out;
3319
3320 /* Latency_Fields_Present */
3321 if (db[8] & (1 << 7))
3322 offset += 2;
3323
3324 /* I_Latency_Fields_Present */
3325 if (db[8] & (1 << 6))
3326 offset += 2;
3327
3328 /* the declared length is not long enough for the 2 first bytes
3329 * of additional video format capabilities */
c858cfca 3330 if (len < (8 + offset + 2))
7ebe1963
LD		 3331 goto out;
3332
c858cfca
DL		 3333 /* 3D_Present */
3334 offset++;
fbf46025 3335 if (db[8 + offset] & (1 << 7)) {
c858cfca
DL		 3336 modes += add_hdmi_mandatory_stereo_modes(connector);
3337
fbf46025
TW		 3338 /* 3D_Multi_present */
3339 multi_present = (db[8 + offset] & 0x60) >> 5;
3340 }
3341
c858cfca 3342 offset++;
7ebe1963 3343 vic_len = db[8 + offset] >> 5;
fbf46025 3344 hdmi_3d_len = db[8 + offset] & 0x1f;
7ebe1963
LD		 3345
3346 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
7ebe1963
LD		 3347 u8 vic;
3348
3349 vic = db[9 + offset + i];
1deee8d7 3350 modes += add_hdmi_mode(connector, vic);
7ebe1963 3351 }
fbf46025
TW		 3352 offset += 1 + vic_len;
3353
0e5083aa
TW		 3354 if (multi_present == 1)
3355 multi_len = 2;
3356 else if (multi_present == 2)
3357 multi_len = 4;
3358 else
3359 multi_len = 0;
fbf46025 3360
0e5083aa 3361 if (len < (8 + offset + hdmi_3d_len - 1))
fbf46025
TW		 3362 goto out;
3363
0e5083aa 3364 if (hdmi_3d_len < multi_len)
fbf46025
TW		 3365 goto out;
3366
0e5083aa
TW		 3367 if (multi_present == 1 || multi_present == 2) {
3368 /* 3D_Structure_ALL */
3369 structure_all = (db[8 + offset] << 8) | db[9 + offset];
fbf46025 3370
0e5083aa
TW		 3371 /* check if 3D_MASK is present */
3372 if (multi_present == 2)
3373 mask = (db[10 + offset] << 8) | db[11 + offset];
3374 else
3375 mask = 0xffff;
3376
3377 for (i = 0; i < 16; i++) {
3378 if (mask & (1 << i))
3379 modes += add_3d_struct_modes(connector,
3380 structure_all,
3381 video_db,
3382 video_len, i);
3383 }
3384 }
3385
3386 offset += multi_len;
3387
3388 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
3389 int vic_index;
3390 struct drm_display_mode *newmode = NULL;
3391 unsigned int newflag = 0;
3392 bool detail_present;
3393
3394 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
3395
3396 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
3397 break;
3398
3399 /* 2D_VIC_order_X */
3400 vic_index = db[8 + offset + i] >> 4;
3401
3402 /* 3D_Structure_X */
3403 switch (db[8 + offset + i] & 0x0f) {
3404 case 0:
3405 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
3406 break;
3407 case 6:
3408 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3409 break;
3410 case 8:
3411 /* 3D_Detail_X */
3412 if ((db[9 + offset + i] >> 4) == 1)
3413 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3414 break;
3415 }
3416
3417 if (newflag != 0) {
3418 newmode = drm_display_mode_from_vic_index(connector,
3419 video_db,
3420 video_len,
3421 vic_index);
3422
3423 if (newmode) {
3424 newmode->flags |= newflag;
3425 drm_mode_probed_add(connector, newmode);
3426 modes++;
3427 }
3428 }
3429
3430 if (detail_present)
3431 i++;
fbf46025 3432 }
7ebe1963
LD		 3433
3434out:
3435 return modes;
3436}
3437
9e50b9d5
VS		 3438static int
3439cea_db_payload_len(const u8 *db)
3440{
3441 return db[0] & 0x1f;
3442}
3443
3444static int
3445cea_db_tag(const u8 *db)
3446{
3447 return db[0] >> 5;
3448}
3449
3450static int
3451cea_revision(const u8 *cea)
3452{
3453 return cea[1];
3454}
3455
3456static int
3457cea_db_offsets(const u8 *cea, int *start, int *end)
3458{
3459 /* Data block offset in CEA extension block */
3460 *start = 4;
3461 *end = cea[2];
3462 if (*end == 0)
3463 *end = 127;
3464 if (*end < 4 || *end > 127)
3465 return -ERANGE;
3466 return 0;
3467}
3468
7ebe1963
LD		 3469static bool cea_db_is_hdmi_vsdb(const u8 *db)
3470{
3471 int hdmi_id;
3472
3473 if (cea_db_tag(db) != VENDOR_BLOCK)
3474 return false;
3475
3476 if (cea_db_payload_len(db) < 5)
3477 return false;
3478
3479 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
3480
6cb3b7f1 3481 return hdmi_id == HDMI_IEEE_OUI;
7ebe1963
LD		 3482}
3483
50dd1bd1
TR		 3484static bool cea_db_is_hdmi_forum_vsdb(const u8 *db)
3485{
3486 unsigned int oui;
3487
3488 if (cea_db_tag(db) != VENDOR_BLOCK)
3489 return false;
3490
3491 if (cea_db_payload_len(db) < 7)
3492 return false;
3493
3494 oui = db[3] << 16 | db[2] << 8 | db[1];
3495
3496 return oui == HDMI_FORUM_IEEE_OUI;
3497}
3498
9e50b9d5
VS		 3499#define for_each_cea_db(cea, i, start, end) \
3500 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
3501
54ac76f8
CS		 3502static int
3503add_cea_modes(struct drm_connector *connector, struct edid *edid)
3504{
13ac3f55 3505 const u8 *cea = drm_find_cea_extension(edid);
fbf46025
TW		 3506 const u8 *db, *hdmi = NULL, *video = NULL;
3507 u8 dbl, hdmi_len, video_len = 0;
54ac76f8
CS		 3508 int modes = 0;
3509
9e50b9d5
VS		 3510 if (cea && cea_revision(cea) >= 3) {
3511 int i, start, end;
3512
3513 if (cea_db_offsets(cea, &start, &end))
3514 return 0;
3515
3516 for_each_cea_db(cea, i, start, end) {
3517 db = &cea[i];
3518 dbl = cea_db_payload_len(db);
3519
fbf46025
TW		 3520 if (cea_db_tag(db) == VIDEO_BLOCK) {
3521 video = db + 1;
3522 video_len = dbl;
3523 modes += do_cea_modes(connector, video, dbl);
3524 }
c858cfca
DL		 3525 else if (cea_db_is_hdmi_vsdb(db)) {
3526 hdmi = db;
3527 hdmi_len = dbl;
3528 }
54ac76f8
CS		 3529 }
3530 }
3531
c858cfca
DL		 3532 /*
3533 * We parse the HDMI VSDB after having added the cea modes as we will
3534 * be patching their flags when the sink supports stereo 3D.
3535 */
3536 if (hdmi)
fbf46025
TW		 3537 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
3538 video_len);
c858cfca 3539
54ac76f8
CS		 3540 return modes;
3541}
3542
fa3a7340
VS		 3543static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
3544{
3545 const struct drm_display_mode *cea_mode;
3546 int clock1, clock2, clock;
d9278b4c 3547 u8 vic;
fa3a7340
VS		 3548 const char *type;
3549
4c6bcf44
VS		 3550 /*
3551 * allow 5kHz clock difference either way to account for
3552 * the 10kHz clock resolution limit of detailed timings.
3553 */
d9278b4c
JN		 3554 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
3555 if (drm_valid_cea_vic(vic)) {
fa3a7340 3556 type = "CEA";
d9278b4c 3557 cea_mode = &edid_cea_modes[vic];
fa3a7340
VS		 3558 clock1 = cea_mode->clock;
3559 clock2 = cea_mode_alternate_clock(cea_mode);
3560 } else {
d9278b4c
JN		 3561 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
3562 if (drm_valid_hdmi_vic(vic)) {
fa3a7340 3563 type = "HDMI";
d9278b4c 3564 cea_mode = &edid_4k_modes[vic];
fa3a7340
VS		 3565 clock1 = cea_mode->clock;
3566 clock2 = hdmi_mode_alternate_clock(cea_mode);
3567 } else {
3568 return;
3569 }
3570 }
3571
3572 /* pick whichever is closest */
3573 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
3574 clock = clock1;
3575 else
3576 clock = clock2;
3577
3578 if (mode->clock == clock)
3579 return;
3580
3581 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
d9278b4c 3582 type, vic, mode->clock, clock);
fa3a7340
VS		 3583 mode->clock = clock;
3584}
3585
76adaa34 3586static void
23ebf8b9 3587drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
76adaa34 3588{
8504072a 3589 u8 len = cea_db_payload_len(db);
76adaa34 3590
23ebf8b9 3591 if (len >= 6)
8504072a 3592 connector->eld[5] |= (db[6] >> 7) << 1; /* Supports_AI */
8504072a
VS		 3593 if (len >= 8) {
3594 connector->latency_present[0] = db[8] >> 7;
3595 connector->latency_present[1] = (db[8] >> 6) & 1;
3596 }
3597 if (len >= 9)
3598 connector->video_latency[0] = db[9];
3599 if (len >= 10)
3600 connector->audio_latency[0] = db[10];
3601 if (len >= 11)
3602 connector->video_latency[1] = db[11];
3603 if (len >= 12)
3604 connector->audio_latency[1] = db[12];
76adaa34 3605
23ebf8b9
VS		 3606 DRM_DEBUG_KMS("HDMI: latency present %d %d, "
3607 "video latency %d %d, "
3608 "audio latency %d %d\n",
3609 connector->latency_present[0],
3610 connector->latency_present[1],
3611 connector->video_latency[0],
3612 connector->video_latency[1],
3613 connector->audio_latency[0],
3614 connector->audio_latency[1]);
76adaa34
WF		 3615}
3616
3617static void
3618monitor_name(struct detailed_timing *t, void *data)
3619{
3620 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME)
3621 *(u8 **)data = t->data.other_data.data.str.str;
14f77fdd
VS		 3622}
3623
59f7c0fa
JB		 3624static int get_monitor_name(struct edid *edid, char name[13])
3625{
3626 char *edid_name = NULL;
3627 int mnl;
3628
3629 if (!edid || !name)
3630 return 0;
3631
3632 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name);
3633 for (mnl = 0; edid_name && mnl < 13; mnl++) {
3634 if (edid_name[mnl] == 0x0a)
3635 break;
3636
3637 name[mnl] = edid_name[mnl];
3638 }
3639
3640 return mnl;
3641}
3642
3643/**
3644 * drm_edid_get_monitor_name - fetch the monitor name from the edid
3645 * @edid: monitor EDID information
3646 * @name: pointer to a character array to hold the name of the monitor
3647 * @bufsize: The size of the name buffer (should be at least 14 chars.)
3648 *
3649 */
3650void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize)
3651{
3652 int name_length;
3653 char buf[13];
3654
3655 if (bufsize <= 0)
3656 return;
3657
3658 name_length = min(get_monitor_name(edid, buf), bufsize - 1);
3659 memcpy(name, buf, name_length);
3660 name[name_length] = '\0';
3661}
3662EXPORT_SYMBOL(drm_edid_get_monitor_name);
3663
76adaa34
WF		 3664/**
3665 * drm_edid_to_eld - build ELD from EDID
3666 * @connector: connector corresponding to the HDMI/DP sink
3667 * @edid: EDID to parse
3668 *
db6cf833
TR		 3669 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
3670 * Conn_Type, HDCP and Port_ID ELD fields are left for the graphics driver to
3671 * fill in.
76adaa34
WF		 3672 */
3673void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
3674{
3675 uint8_t *eld = connector->eld;
3676 u8 *cea;
76adaa34 3677 u8 *db;
7c018782 3678 int total_sad_count = 0;
76adaa34
WF		 3679 int mnl;
3680 int dbl;
3681
3682 memset(eld, 0, sizeof(connector->eld));
3683
85c91580
VS		 3684 connector->latency_present[0] = false;
3685 connector->latency_present[1] = false;
3686 connector->video_latency[0] = 0;
3687 connector->audio_latency[0] = 0;
3688 connector->video_latency[1] = 0;
3689 connector->audio_latency[1] = 0;
3690
e9bd0b84
JN		 3691 if (!edid)
3692 return;
3693
76adaa34
WF		 3694 cea = drm_find_cea_extension(edid);
3695 if (!cea) {
3696 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
3697 return;
3698 }
3699
59f7c0fa
JB		 3700 mnl = get_monitor_name(edid, eld + 20);
3701
76adaa34
WF		 3702 eld[4] = (cea[1] << 5) | mnl;
3703 DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20);
3704
3705 eld[0] = 2 << 3; /* ELD version: 2 */
3706
3707 eld[16] = edid->mfg_id[0];
3708 eld[17] = edid->mfg_id[1];
3709 eld[18] = edid->prod_code[0];
3710 eld[19] = edid->prod_code[1];
3711
9e50b9d5
VS		 3712 if (cea_revision(cea) >= 3) {
3713 int i, start, end;
3714
3715 if (cea_db_offsets(cea, &start, &end)) {
3716 start = 0;
3717 end = 0;
3718 }
3719
3720 for_each_cea_db(cea, i, start, end) {
3721 db = &cea[i];
3722 dbl = cea_db_payload_len(db);
3723
3724 switch (cea_db_tag(db)) {
7c018782
VS		 3725 int sad_count;
3726
a0ab734d
CS		 3727 case AUDIO_BLOCK:
3728 /* Audio Data Block, contains SADs */
7c018782
VS		 3729 sad_count = min(dbl / 3, 15 - total_sad_count);
3730 if (sad_count >= 1)
3731 memcpy(eld + 20 + mnl + total_sad_count * 3,
3732 &db[1], sad_count * 3);
3733 total_sad_count += sad_count;
a0ab734d
CS		 3734 break;
3735 case SPEAKER_BLOCK:
9e50b9d5
VS		 3736 /* Speaker Allocation Data Block */
3737 if (dbl >= 1)
3738 eld[7] = db[1];
a0ab734d
CS		 3739 break;
3740 case VENDOR_BLOCK:
3741 /* HDMI Vendor-Specific Data Block */
14f77fdd 3742 if (cea_db_is_hdmi_vsdb(db))
23ebf8b9 3743 drm_parse_hdmi_vsdb_audio(connector, db);
a0ab734d
CS		 3744 break;
3745 default:
3746 break;
3747 }
76adaa34 3748 }
9e50b9d5 3749 }
7c018782 3750 eld[5] |= total_sad_count << 4;
76adaa34 3751
938fd8aa
JN		 3752 eld[DRM_ELD_BASELINE_ELD_LEN] =
3753 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
3754
3755 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
7c018782 3756 drm_eld_size(eld), total_sad_count);
76adaa34
WF		 3757}
3758EXPORT_SYMBOL(drm_edid_to_eld);
3759
fe214163
RM		 3760/**
3761 * drm_edid_to_sad - extracts SADs from EDID
3762 * @edid: EDID to parse
3763 * @sads: pointer that will be set to the extracted SADs
3764 *
3765 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
fe214163 3766 *
db6cf833
TR		 3767 * Note: The returned pointer needs to be freed using kfree().
3768 *
3769 * Return: The number of found SADs or negative number on error.
fe214163
RM		 3770 */
3771int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
3772{
3773 int count = 0;
3774 int i, start, end, dbl;
3775 u8 *cea;
3776
3777 cea = drm_find_cea_extension(edid);
3778 if (!cea) {
3779 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
3780 return -ENOENT;
3781 }
3782
3783 if (cea_revision(cea) < 3) {
3784 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
3785 return -ENOTSUPP;
3786 }
3787
3788 if (cea_db_offsets(cea, &start, &end)) {
3789 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
3790 return -EPROTO;
3791 }
3792
3793 for_each_cea_db(cea, i, start, end) {
3794 u8 *db = &cea[i];
3795
3796 if (cea_db_tag(db) == AUDIO_BLOCK) {
3797 int j;
3798 dbl = cea_db_payload_len(db);
3799
3800 count = dbl / 3; /* SAD is 3B */
3801 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
3802 if (!*sads)
3803 return -ENOMEM;
3804 for (j = 0; j < count; j++) {
3805 u8 *sad = &db[1 + j * 3];
3806
3807 (*sads)[j].format = (sad[0] & 0x78) >> 3;
3808 (*sads)[j].channels = sad[0] & 0x7;
3809 (*sads)[j].freq = sad[1] & 0x7F;
3810 (*sads)[j].byte2 = sad[2];
3811 }
3812 break;
3813 }
3814 }
3815
3816 return count;
3817}
3818EXPORT_SYMBOL(drm_edid_to_sad);
3819
d105f476
AD		 3820/**
3821 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
3822 * @edid: EDID to parse
3823 * @sadb: pointer to the speaker block
3824 *
3825 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
d105f476 3826 *
db6cf833
TR		 3827 * Note: The returned pointer needs to be freed using kfree().
3828 *
3829 * Return: The number of found Speaker Allocation Blocks or negative number on
3830 * error.
d105f476
AD		 3831 */
3832int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
3833{
3834 int count = 0;
3835 int i, start, end, dbl;
3836 const u8 *cea;
3837
3838 cea = drm_find_cea_extension(edid);
3839 if (!cea) {
3840 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
3841 return -ENOENT;
3842 }
3843
3844 if (cea_revision(cea) < 3) {
3845 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
3846 return -ENOTSUPP;
3847 }
3848
3849 if (cea_db_offsets(cea, &start, &end)) {
3850 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
3851 return -EPROTO;
3852 }
3853
3854 for_each_cea_db(cea, i, start, end) {
3855 const u8 *db = &cea[i];
3856
3857 if (cea_db_tag(db) == SPEAKER_BLOCK) {
3858 dbl = cea_db_payload_len(db);
3859
3860 /* Speaker Allocation Data Block */
3861 if (dbl == 3) {
89086bca 3862 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
618e3776
AD		 3863 if (!*sadb)
3864 return -ENOMEM;
d105f476
AD		 3865 count = dbl;
3866 break;
3867 }
3868 }
3869 }
3870
3871 return count;
3872}
3873EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
3874
76adaa34 3875/**
db6cf833 3876 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
76adaa34
WF		 3877 * @connector: connector associated with the HDMI/DP sink
3878 * @mode: the display mode
db6cf833
TR		 3879 *
3880 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
3881 * the sink doesn't support audio or video.
76adaa34
WF		 3882 */
3883int drm_av_sync_delay(struct drm_connector *connector,
3a818d35 3884 const struct drm_display_mode *mode)
76adaa34
WF		 3885{
3886 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
3887 int a, v;
3888
3889 if (!connector->latency_present[0])
3890 return 0;
3891 if (!connector->latency_present[1])
3892 i = 0;
3893
3894 a = connector->audio_latency[i];
3895 v = connector->video_latency[i];
3896
3897 /*
3898 * HDMI/DP sink doesn't support audio or video?
3899 */
3900 if (a == 255 || v == 255)
3901 return 0;
3902
3903 /*
3904 * Convert raw EDID values to millisecond.
3905 * Treat unknown latency as 0ms.
3906 */
3907 if (a)
3908 a = min(2 * (a - 1), 500);
3909 if (v)
3910 v = min(2 * (v - 1), 500);
3911
3912 return max(v - a, 0);
3913}
3914EXPORT_SYMBOL(drm_av_sync_delay);
3915
8fe9790d 3916/**
db6cf833 3917 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
8fe9790d
ZW		 3918 * @edid: monitor EDID information
3919 *
3920 * Parse the CEA extension according to CEA-861-B.
db6cf833
TR		 3921 *
3922 * Return: True if the monitor is HDMI, false if not or unknown.
8fe9790d
ZW		 3923 */
3924bool drm_detect_hdmi_monitor(struct edid *edid)
3925{
3926 u8 *edid_ext;
14f77fdd 3927 int i;
8fe9790d 3928 int start_offset, end_offset;
8fe9790d
ZW		 3929
3930 edid_ext = drm_find_cea_extension(edid);
3931 if (!edid_ext)
14f77fdd 3932 return false;
f23c20c8 3933
9e50b9d5 3934 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
14f77fdd 3935 return false;
f23c20c8
ML		 3936
3937 /*
3938 * Because HDMI identifier is in Vendor Specific Block,
3939 * search it from all data blocks of CEA extension.
3940 */
9e50b9d5 3941 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
14f77fdd
VS		 3942 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
3943 return true;
f23c20c8
ML		 3944 }
3945
14f77fdd 3946 return false;
f23c20c8
ML		 3947}
3948EXPORT_SYMBOL(drm_detect_hdmi_monitor);
3949
8fe9790d
ZW		 3950/**
3951 * drm_detect_monitor_audio - check monitor audio capability
fc66811c 3952 * @edid: EDID block to scan
8fe9790d
ZW		 3953 *
3954 * Monitor should have CEA extension block.
3955 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
3956 * audio' only. If there is any audio extension block and supported
3957 * audio format, assume at least 'basic audio' support, even if 'basic
3958 * audio' is not defined in EDID.
3959 *
db6cf833 3960 * Return: True if the monitor supports audio, false otherwise.
8fe9790d
ZW		 3961 */
3962bool drm_detect_monitor_audio(struct edid *edid)
3963{
3964 u8 *edid_ext;
3965 int i, j;
3966 bool has_audio = false;
3967 int start_offset, end_offset;
3968
3969 edid_ext = drm_find_cea_extension(edid);
3970 if (!edid_ext)
3971 goto end;
3972
3973 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
3974
3975 if (has_audio) {
3976 DRM_DEBUG_KMS("Monitor has basic audio support\n");
3977 goto end;
3978 }
3979
9e50b9d5
VS		 3980 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
3981 goto end;
8fe9790d 3982
9e50b9d5
VS		 3983 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
3984 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
8fe9790d 3985 has_audio = true;
9e50b9d5 3986 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
8fe9790d
ZW		 3987 DRM_DEBUG_KMS("CEA audio format %d\n",
3988 (edid_ext[i + j] >> 3) & 0xf);
3989 goto end;
3990 }
3991 }
3992end:
3993 return has_audio;
3994}
3995EXPORT_SYMBOL(drm_detect_monitor_audio);
3996
b1edd6a6
VS		 3997/**
3998 * drm_rgb_quant_range_selectable - is RGB quantization range selectable?
fc66811c 3999 * @edid: EDID block to scan
b1edd6a6
VS		 4000 *
4001 * Check whether the monitor reports the RGB quantization range selection
4002 * as supported. The AVI infoframe can then be used to inform the monitor
4003 * which quantization range (full or limited) is used.
db6cf833
TR		 4004 *
4005 * Return: True if the RGB quantization range is selectable, false otherwise.
b1edd6a6
VS		 4006 */
4007bool drm_rgb_quant_range_selectable(struct edid *edid)
4008{
4009 u8 *edid_ext;
4010 int i, start, end;
4011
4012 edid_ext = drm_find_cea_extension(edid);
4013 if (!edid_ext)
4014 return false;
4015
4016 if (cea_db_offsets(edid_ext, &start, &end))
4017 return false;
4018
4019 for_each_cea_db(edid_ext, i, start, end) {
4020 if (cea_db_tag(&edid_ext[i]) == VIDEO_CAPABILITY_BLOCK &&
4021 cea_db_payload_len(&edid_ext[i]) == 2) {
4022 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]);
4023 return edid_ext[i + 2] & EDID_CEA_VCDB_QS;
4024 }
4025 }
4026
4027 return false;
4028}
4029EXPORT_SYMBOL(drm_rgb_quant_range_selectable);
4030
c8127cf0
VS		 4031/**
4032 * drm_default_rgb_quant_range - default RGB quantization range
4033 * @mode: display mode
4034 *
4035 * Determine the default RGB quantization range for the mode,
4036 * as specified in CEA-861.
4037 *
4038 * Return: The default RGB quantization range for the mode
4039 */
4040enum hdmi_quantization_range
4041drm_default_rgb_quant_range(const struct drm_display_mode *mode)
4042{
4043 /* All CEA modes other than VIC 1 use limited quantization range. */
4044 return drm_match_cea_mode(mode) > 1 ?
4045 HDMI_QUANTIZATION_RANGE_LIMITED :
4046 HDMI_QUANTIZATION_RANGE_FULL;
4047}
4048EXPORT_SYMBOL(drm_default_rgb_quant_range);
4049
afa1c763
SS		 4050static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector,
4051 const u8 *hf_vsdb)
4052{
62c58af3
SS		 4053 struct drm_display_info *display = &connector->display_info;
4054 struct drm_hdmi_info *hdmi = &display->hdmi;
afa1c763
SS		 4055
4056 if (hf_vsdb[6] & 0x80) {
4057 hdmi->scdc.supported = true;
4058 if (hf_vsdb[6] & 0x40)
4059 hdmi->scdc.read_request = true;
4060 }
62c58af3
SS		 4061
4062 /*
4063 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
4064 * And as per the spec, three factors confirm this:
4065 * * Availability of a HF-VSDB block in EDID (check)
4066 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
4067 * * SCDC support available (let's check)
4068 * Lets check it out.
4069 */
4070
4071 if (hf_vsdb[5]) {
4072 /* max clock is 5000 KHz times block value */
4073 u32 max_tmds_clock = hf_vsdb[5] * 5000;
4074 struct drm_scdc *scdc = &hdmi->scdc;
4075
4076 if (max_tmds_clock > 340000) {
4077 display->max_tmds_clock = max_tmds_clock;
4078 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
4079 display->max_tmds_clock);
4080 }
4081
4082 if (scdc->supported) {
4083 scdc->scrambling.supported = true;
4084
4085 /* Few sinks support scrambling for cloks < 340M */
4086 if ((hf_vsdb[6] & 0x8))
4087 scdc->scrambling.low_rates = true;
4088 }
4089 }
afa1c763
SS		 4090}
4091
1cea146a
VS		 4092static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
4093 const u8 *hdmi)
d0c94692 4094{
1826750f 4095 struct drm_display_info *info = &connector->display_info;
d0c94692
MK		 4096 unsigned int dc_bpc = 0;
4097
1cea146a
VS		 4098 /* HDMI supports at least 8 bpc */
4099 info->bpc = 8;
d0c94692 4100
1cea146a
VS		 4101 if (cea_db_payload_len(hdmi) < 6)
4102 return;
4103
4104 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
4105 dc_bpc = 10;
4106 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
4107 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
4108 connector->name);
4109 }
4110
4111 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
4112 dc_bpc = 12;
4113 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
4114 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
4115 connector->name);
4116 }
4117
4118 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
4119 dc_bpc = 16;
4120 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
4121 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
4122 connector->name);
4123 }
4124
4125 if (dc_bpc == 0) {
4126 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
4127 connector->name);
4128 return;
4129 }
4130
4131 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
4132 connector->name, dc_bpc);
4133 info->bpc = dc_bpc;
d0c94692
MK		 4134
4135 /*
1cea146a
VS		 4136 * Deep color support mandates RGB444 support for all video
4137 * modes and forbids YCRCB422 support for all video modes per
4138 * HDMI 1.3 spec.
d0c94692 4139 */
1cea146a 4140 info->color_formats = DRM_COLOR_FORMAT_RGB444;
d0c94692 4141
1cea146a
VS		 4142 /* YCRCB444 is optional according to spec. */
4143 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
4144 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4145 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
4146 connector->name);
4147 }
d0c94692 4148
1cea146a
VS		 4149 /*
4150 * Spec says that if any deep color mode is supported at all,
4151 * then deep color 36 bit must be supported.
4152 */
4153 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
4154 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
4155 connector->name);
4156 }
4157}
d0c94692 4158
23ebf8b9
VS		 4159static void
4160drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
4161{
4162 struct drm_display_info *info = &connector->display_info;
4163 u8 len = cea_db_payload_len(db);
4164
4165 if (len >= 6)
4166 info->dvi_dual = db[6] & 1;
4167 if (len >= 7)
4168 info->max_tmds_clock = db[7] * 5000;
4169
4170 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
4171 "max TMDS clock %d kHz\n",
4172 info->dvi_dual,
4173 info->max_tmds_clock);
4174
4175 drm_parse_hdmi_deep_color_info(connector, db);
4176}
4177
1cea146a
VS		 4178static void drm_parse_cea_ext(struct drm_connector *connector,
4179 struct edid *edid)
4180{
4181 struct drm_display_info *info = &connector->display_info;
4182 const u8 *edid_ext;
4183 int i, start, end;
d0c94692 4184
1cea146a
VS		 4185 edid_ext = drm_find_cea_extension(edid);
4186 if (!edid_ext)
4187 return;
d0c94692 4188
1cea146a 4189 info->cea_rev = edid_ext[1];
d0c94692 4190
1cea146a
VS		 4191 /* The existence of a CEA block should imply RGB support */
4192 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4193 if (edid_ext[3] & EDID_CEA_YCRCB444)
4194 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4195 if (edid_ext[3] & EDID_CEA_YCRCB422)
4196 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4197
4198 if (cea_db_offsets(edid_ext, &start, &end))
4199 return;
4200
4201 for_each_cea_db(edid_ext, i, start, end) {
4202 const u8 *db = &edid_ext[i];
4203
23ebf8b9
VS		 4204 if (cea_db_is_hdmi_vsdb(db))
4205 drm_parse_hdmi_vsdb_video(connector, db);
afa1c763
SS		 4206 if (cea_db_is_hdmi_forum_vsdb(db))
4207 drm_parse_hdmi_forum_vsdb(connector, db);
1cea146a 4208 }
d0c94692
MK		 4209}
4210
1cea146a
VS		 4211static void drm_add_display_info(struct drm_connector *connector,
4212 struct edid *edid)
3b11228b 4213{
1826750f 4214 struct drm_display_info *info = &connector->display_info;
ebec9a7b 4215
3b11228b
JB		 4216 info->width_mm = edid->width_cm * 10;
4217 info->height_mm = edid->height_cm * 10;
4218
4219 /* driver figures it out in this case */
4220 info->bpc = 0;
da05a5a7 4221 info->color_formats = 0;
011acce2 4222 info->cea_rev = 0;
23ebf8b9
VS		 4223 info->max_tmds_clock = 0;
4224 info->dvi_dual = false;
3b11228b 4225
a988bc72 4226 if (edid->revision < 3)
3b11228b
JB		 4227 return;
4228
4229 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
4230 return;
4231
1cea146a 4232 drm_parse_cea_ext(connector, edid);
d0c94692 4233
210a021d
MK		 4234 /*
4235 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
4236 *
4237 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
4238 * tells us to assume 8 bpc color depth if the EDID doesn't have
4239 * extensions which tell otherwise.
4240 */
4241 if ((info->bpc == 0) && (edid->revision < 4) &&
4242 (edid->input & DRM_EDID_DIGITAL_TYPE_DVI)) {
4243 info->bpc = 8;
4244 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
4245 connector->name, info->bpc);
4246 }
4247
a988bc72
LPC		 4248 /* Only defined for 1.4 with digital displays */
4249 if (edid->revision < 4)
4250 return;
4251
3b11228b
JB		 4252 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
4253 case DRM_EDID_DIGITAL_DEPTH_6:
4254 info->bpc = 6;
4255 break;
4256 case DRM_EDID_DIGITAL_DEPTH_8:
4257 info->bpc = 8;
4258 break;
4259 case DRM_EDID_DIGITAL_DEPTH_10:
4260 info->bpc = 10;
4261 break;
4262 case DRM_EDID_DIGITAL_DEPTH_12:
4263 info->bpc = 12;
4264 break;
4265 case DRM_EDID_DIGITAL_DEPTH_14:
4266 info->bpc = 14;
4267 break;
4268 case DRM_EDID_DIGITAL_DEPTH_16:
4269 info->bpc = 16;
4270 break;
4271 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
4272 default:
4273 info->bpc = 0;
4274 break;
4275 }
da05a5a7 4276
d0c94692 4277 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
25933820 4278 connector->name, info->bpc);
d0c94692 4279
a988bc72 4280 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
ee58808d
LPC		 4281 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
4282 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4283 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
4284 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
3b11228b
JB		 4285}
4286
c9729177
DA		 4287static int validate_displayid(u8 *displayid, int length, int idx)
4288{
4289 int i;
4290 u8 csum = 0;
4291 struct displayid_hdr *base;
4292
4293 base = (struct displayid_hdr *)&displayid[idx];
4294
4295 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",
4296 base->rev, base->bytes, base->prod_id, base->ext_count);
4297
4298 if (base->bytes + 5 > length - idx)
4299 return -EINVAL;
4300 for (i = idx; i <= base->bytes + 5; i++) {
4301 csum += displayid[i];
4302 }
4303 if (csum) {
813a7878 4304 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum);
c9729177
DA		 4305 return -EINVAL;
4306 }
4307 return 0;
4308}
4309
a39ed680
DA		 4310static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
4311 struct displayid_detailed_timings_1 *timings)
4312{
4313 struct drm_display_mode *mode;
4314 unsigned pixel_clock = (timings->pixel_clock[0] |
4315 (timings->pixel_clock[1] << 8) |
4316 (timings->pixel_clock[2] << 16));
4317 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
4318 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
4319 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
4320 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
4321 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
4322 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
4323 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
4324 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
4325 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
4326 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
4327 mode = drm_mode_create(dev);
4328 if (!mode)
4329 return NULL;
4330
4331 mode->clock = pixel_clock * 10;
4332 mode->hdisplay = hactive;
4333 mode->hsync_start = mode->hdisplay + hsync;
4334 mode->hsync_end = mode->hsync_start + hsync_width;
4335 mode->htotal = mode->hdisplay + hblank;
4336
4337 mode->vdisplay = vactive;
4338 mode->vsync_start = mode->vdisplay + vsync;
4339 mode->vsync_end = mode->vsync_start + vsync_width;
4340 mode->vtotal = mode->vdisplay + vblank;
4341
4342 mode->flags = 0;
4343 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
4344 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
4345 mode->type = DRM_MODE_TYPE_DRIVER;
4346
4347 if (timings->flags & 0x80)
4348 mode->type |= DRM_MODE_TYPE_PREFERRED;
4349 mode->vrefresh = drm_mode_vrefresh(mode);
4350 drm_mode_set_name(mode);
4351
4352 return mode;
4353}
4354
4355static int add_displayid_detailed_1_modes(struct drm_connector *connector,
4356 struct displayid_block *block)
4357{
4358 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
4359 int i;
4360 int num_timings;
4361 struct drm_display_mode *newmode;
4362 int num_modes = 0;
4363 /* blocks must be multiple of 20 bytes length */
4364 if (block->num_bytes % 20)
4365 return 0;
4366
4367 num_timings = block->num_bytes / 20;
4368 for (i = 0; i < num_timings; i++) {
4369 struct displayid_detailed_timings_1 *timings = &det->timings[i];
4370
4371 newmode = drm_mode_displayid_detailed(connector->dev, timings);
4372 if (!newmode)
4373 continue;
4374
4375 drm_mode_probed_add(connector, newmode);
4376 num_modes++;
4377 }
4378 return num_modes;
4379}
4380
4381static int add_displayid_detailed_modes(struct drm_connector *connector,
4382 struct edid *edid)
4383{
4384 u8 *displayid;
4385 int ret;
4386 int idx = 1;
4387 int length = EDID_LENGTH;
4388 struct displayid_block *block;
4389 int num_modes = 0;
4390
4391 displayid = drm_find_displayid_extension(edid);
4392 if (!displayid)
4393 return 0;
4394
4395 ret = validate_displayid(displayid, length, idx);
4396 if (ret)
4397 return 0;
4398
4399 idx += sizeof(struct displayid_hdr);
4400 while (block = (struct displayid_block *)&displayid[idx],
4401 idx + sizeof(struct displayid_block) <= length &&
4402 idx + sizeof(struct displayid_block) + block->num_bytes <= length &&
4403 block->num_bytes > 0) {
4404 idx += block->num_bytes + sizeof(struct displayid_block);
4405 switch (block->tag) {
4406 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
4407 num_modes += add_displayid_detailed_1_modes(connector, block);
4408 break;
4409 }
4410 }
4411 return num_modes;
4412}
4413
f453ba04
DA		 4414/**
4415 * drm_add_edid_modes - add modes from EDID data, if available
4416 * @connector: connector we're probing
db6cf833 4417 * @edid: EDID data
f453ba04 4418 *
b3c6c8bf
DV		 4419 * Add the specified modes to the connector's mode list. Also fills out the
4420 * &drm_display_info structure in @connector with any information which can be
4421 * derived from the edid.
f453ba04 4422 *
db6cf833 4423 * Return: The number of modes added or 0 if we couldn't find any.
f453ba04
DA		 4424 */
4425int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
4426{
4427 int num_modes = 0;
4428 u32 quirks;
4429
4430 if (edid == NULL) {
4431 return 0;
4432 }
3c537889 4433 if (!drm_edid_is_valid(edid)) {
dcdb1674 4434 dev_warn(connector->dev->dev, "%s: EDID invalid.\n",
25933820 4435 connector->name);
f453ba04
DA		 4436 return 0;
4437 }
4438
4439 quirks = edid_get_quirks(edid);
4440
0f0f8708
SS		 4441 /*
4442 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
4443 * To avoid multiple parsing of same block, lets parse that map
4444 * from sink info, before parsing CEA modes.
4445 */
4446 drm_add_display_info(connector, edid);
4447
c867df70
AJ		 4448 /*
4449 * EDID spec says modes should be preferred in this order:
4450 * - preferred detailed mode
4451 * - other detailed modes from base block
4452 * - detailed modes from extension blocks
4453 * - CVT 3-byte code modes
4454 * - standard timing codes
4455 * - established timing codes
4456 * - modes inferred from GTF or CVT range information
4457 *
13931579 4458 * We get this pretty much right.
c867df70
AJ		 4459 *
4460 * XXX order for additional mode types in extension blocks?
4461 */
13931579
AJ		 4462 num_modes += add_detailed_modes(connector, edid, quirks);
4463 num_modes += add_cvt_modes(connector, edid);
c867df70
AJ		 4464 num_modes += add_standard_modes(connector, edid);
4465 num_modes += add_established_modes(connector, edid);
54ac76f8 4466 num_modes += add_cea_modes(connector, edid);
e6e79209 4467 num_modes += add_alternate_cea_modes(connector, edid);
a39ed680 4468 num_modes += add_displayid_detailed_modes(connector, edid);
4d53dc0c
VS		 4469 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
4470 num_modes += add_inferred_modes(connector, edid);
f453ba04
DA		 4471
4472 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
4473 edid_fixup_preferred(connector, quirks);
4474
e10aec65
MK		 4475 if (quirks & EDID_QUIRK_FORCE_6BPC)
4476 connector->display_info.bpc = 6;
4477
49d45a31
RM		 4478 if (quirks & EDID_QUIRK_FORCE_8BPC)
4479 connector->display_info.bpc = 8;
4480
e345da82
MK		 4481 if (quirks & EDID_QUIRK_FORCE_10BPC)
4482 connector->display_info.bpc = 10;
4483
bc5b9641
MK		 4484 if (quirks & EDID_QUIRK_FORCE_12BPC)
4485 connector->display_info.bpc = 12;
4486
f453ba04
DA		 4487 return num_modes;
4488}
4489EXPORT_SYMBOL(drm_add_edid_modes);
f0fda0a4
ZY		 4490
4491/**
4492 * drm_add_modes_noedid - add modes for the connectors without EDID
4493 * @connector: connector we're probing
4494 * @hdisplay: the horizontal display limit
4495 * @vdisplay: the vertical display limit
4496 *
4497 * Add the specified modes to the connector's mode list. Only when the
4498 * hdisplay/vdisplay is not beyond the given limit, it will be added.
4499 *
db6cf833 4500 * Return: The number of modes added or 0 if we couldn't find any.
f0fda0a4
ZY		 4501 */
4502int drm_add_modes_noedid(struct drm_connector *connector,
4503 int hdisplay, int vdisplay)
4504{
4505 int i, count, num_modes = 0;
b1f559ec 4506 struct drm_display_mode *mode;
f0fda0a4
ZY		 4507 struct drm_device *dev = connector->dev;
4508
fbb40b28 4509 count = ARRAY_SIZE(drm_dmt_modes);
f0fda0a4
ZY		 4510 if (hdisplay < 0)
4511 hdisplay = 0;
4512 if (vdisplay < 0)
4513 vdisplay = 0;
4514
4515 for (i = 0; i < count; i++) {
b1f559ec 4516 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
f0fda0a4
ZY		 4517 if (hdisplay && vdisplay) {
4518 /*
4519 * Only when two are valid, they will be used to check
4520 * whether the mode should be added to the mode list of
4521 * the connector.
4522 */
4523 if (ptr->hdisplay > hdisplay ||
4524 ptr->vdisplay > vdisplay)
4525 continue;
4526 }
f985dedb
AJ		 4527 if (drm_mode_vrefresh(ptr) > 61)
4528 continue;
f0fda0a4
ZY		 4529 mode = drm_mode_duplicate(dev, ptr);
4530 if (mode) {
4531 drm_mode_probed_add(connector, mode);
4532 num_modes++;
4533 }
4534 }
4535 return num_modes;
4536}
4537EXPORT_SYMBOL(drm_add_modes_noedid);
10a85120 4538
db6cf833
TR		 4539/**
4540 * drm_set_preferred_mode - Sets the preferred mode of a connector
4541 * @connector: connector whose mode list should be processed
4542 * @hpref: horizontal resolution of preferred mode
4543 * @vpref: vertical resolution of preferred mode
4544 *
4545 * Marks a mode as preferred if it matches the resolution specified by @hpref
4546 * and @vpref.
4547 */
3cf70daf
GH		 4548void drm_set_preferred_mode(struct drm_connector *connector,
4549 int hpref, int vpref)
4550{
4551 struct drm_display_mode *mode;
4552
4553 list_for_each_entry(mode, &connector->probed_modes, head) {
db6cf833 4554 if (mode->hdisplay == hpref &&
9d3de138 4555 mode->vdisplay == vpref)
3cf70daf
GH		 4556 mode->type |= DRM_MODE_TYPE_PREFERRED;
4557 }
4558}
4559EXPORT_SYMBOL(drm_set_preferred_mode);
4560
10a85120
TR		 4561/**
4562 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
4563 * data from a DRM display mode
4564 * @frame: HDMI AVI infoframe
4565 * @mode: DRM display mode
0c1f528c 4566 * @is_hdmi2_sink: Sink is HDMI 2.0 compliant
10a85120 4567 *
db6cf833 4568 * Return: 0 on success or a negative error code on failure.
10a85120
TR		 4569 */
4570int
4571drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
0c1f528c
SS		 4572 const struct drm_display_mode *mode,
4573 bool is_hdmi2_sink)
10a85120
TR		 4574{
4575 int err;
4576
4577 if (!frame || !mode)
4578 return -EINVAL;
4579
4580 err = hdmi_avi_infoframe_init(frame);
4581 if (err < 0)
4582 return err;
4583
bf02db99
DL		 4584 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
4585 frame->pixel_repeat = 1;
4586
10a85120 4587 frame->video_code = drm_match_cea_mode(mode);
10a85120 4588
0c1f528c
SS		 4589 /*
4590 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
4591 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
4592 * have to make sure we dont break HDMI 1.4 sinks.
4593 */
4594 if (!is_hdmi2_sink && frame->video_code > 64)
4595 frame->video_code = 0;
4596
4597 /*
4598 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
4599 * we should send its VIC in vendor infoframes, else send the
4600 * VIC in AVI infoframes. Lets check if this mode is present in
4601 * HDMI 1.4b 4K modes
4602 */
4603 if (frame->video_code) {
4604 u8 vendor_if_vic = drm_match_hdmi_mode(mode);
4605 bool is_s3d = mode->flags & DRM_MODE_FLAG_3D_MASK;
4606
4607 if (drm_valid_hdmi_vic(vendor_if_vic) && !is_s3d)
4608 frame->video_code = 0;
4609 }
4610
10a85120 4611 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
0967e6a5 4612
69ab6d35
VK		 4613 /*
4614 * Populate picture aspect ratio from either
4615 * user input (if specified) or from the CEA mode list.
4616 */
4617 if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 ||
4618 mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9)
4619 frame->picture_aspect = mode->picture_aspect_ratio;
4620 else if (frame->video_code > 0)
0967e6a5
VK		 4621 frame->picture_aspect = drm_get_cea_aspect_ratio(
4622 frame->video_code);
4623
10a85120 4624 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
24d01805 4625 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
10a85120
TR		 4626
4627 return 0;
4628}
4629EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
83dd0008 4630
a2ce26f8
VS		 4631/**
4632 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
4633 * quantization range information
4634 * @frame: HDMI AVI infoframe
779c4c28 4635 * @mode: DRM display mode
a2ce26f8
VS		 4636 * @rgb_quant_range: RGB quantization range (Q)
4637 * @rgb_quant_range_selectable: Sink support selectable RGB quantization range (QS)
4638 */
4639void
4640drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
779c4c28 4641 const struct drm_display_mode *mode,
a2ce26f8
VS		 4642 enum hdmi_quantization_range rgb_quant_range,
4643 bool rgb_quant_range_selectable)
4644{
4645 /*
4646 * CEA-861:
4647 * "A Source shall not send a non-zero Q value that does not correspond
4648 * to the default RGB Quantization Range for the transmitted Picture
4649 * unless the Sink indicates support for the Q bit in a Video
4650 * Capabilities Data Block."
779c4c28
VS		 4651 *
4652 * HDMI 2.0 recommends sending non-zero Q when it does match the
4653 * default RGB quantization range for the mode, even when QS=0.
a2ce26f8 4654 */
779c4c28
VS		 4655 if (rgb_quant_range_selectable ||
4656 rgb_quant_range == drm_default_rgb_quant_range(mode))
a2ce26f8
VS		 4657 frame->quantization_range = rgb_quant_range;
4658 else
4659 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
fcc8a22c
VS		 4660
4661 /*
4662 * CEA-861-F:
4663 * "When transmitting any RGB colorimetry, the Source should set the
4664 * YQ-field to match the RGB Quantization Range being transmitted
4665 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
4666 * set YQ=1) and the Sink shall ignore the YQ-field."
4667 */
4668 if (rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
4669 frame->ycc_quantization_range =
4670 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
4671 else
4672 frame->ycc_quantization_range =
4673 HDMI_YCC_QUANTIZATION_RANGE_FULL;
a2ce26f8
VS		 4674}
4675EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
4676
4eed4a0a
DL		 4677static enum hdmi_3d_structure
4678s3d_structure_from_display_mode(const struct drm_display_mode *mode)
4679{
4680 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
4681
4682 switch (layout) {
4683 case DRM_MODE_FLAG_3D_FRAME_PACKING:
4684 return HDMI_3D_STRUCTURE_FRAME_PACKING;
4685 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
4686 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
4687 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
4688 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
4689 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
4690 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
4691 case DRM_MODE_FLAG_3D_L_DEPTH:
4692 return HDMI_3D_STRUCTURE_L_DEPTH;
4693 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
4694 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
4695 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
4696 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
4697 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
4698 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
4699 default:
4700 return HDMI_3D_STRUCTURE_INVALID;
4701 }
4702}
4703
83dd0008
LD		 4704/**
4705 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
4706 * data from a DRM display mode
4707 * @frame: HDMI vendor infoframe
4708 * @mode: DRM display mode
4709 *
4710 * Note that there's is a need to send HDMI vendor infoframes only when using a
4711 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
4712 * function will return -EINVAL, error that can be safely ignored.
4713 *
db6cf833 4714 * Return: 0 on success or a negative error code on failure.
83dd0008
LD		 4715 */
4716int
4717drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
4718 const struct drm_display_mode *mode)
4719{
4720 int err;
4eed4a0a 4721 u32 s3d_flags;
83dd0008
LD		 4722 u8 vic;
4723
4724 if (!frame || !mode)
4725 return -EINVAL;
4726
4727 vic = drm_match_hdmi_mode(mode);
4eed4a0a
DL		 4728 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK;
4729
4730 if (!vic && !s3d_flags)
4731 return -EINVAL;
4732
4733 if (vic && s3d_flags)
83dd0008
LD		 4734 return -EINVAL;
4735
4736 err = hdmi_vendor_infoframe_init(frame);
4737 if (err < 0)
4738 return err;
4739
4eed4a0a
DL		 4740 if (vic)
4741 frame->vic = vic;
4742 else
4743 frame->s3d_struct = s3d_structure_from_display_mode(mode);
83dd0008
LD		 4744
4745 return 0;
4746}
4747EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
40d9b043 4748
5e546cd5
DA		 4749static int drm_parse_tiled_block(struct drm_connector *connector,
4750 struct displayid_block *block)
4751{
4752 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
4753 u16 w, h;
4754 u8 tile_v_loc, tile_h_loc;
4755 u8 num_v_tile, num_h_tile;
4756 struct drm_tile_group *tg;
4757
4758 w = tile->tile_size[0] | tile->tile_size[1] << 8;
4759 h = tile->tile_size[2] | tile->tile_size[3] << 8;
4760
4761 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
4762 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
4763 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
4764 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
4765
4766 connector->has_tile = true;
4767 if (tile->tile_cap & 0x80)
4768 connector->tile_is_single_monitor = true;
4769
4770 connector->num_h_tile = num_h_tile + 1;
4771 connector->num_v_tile = num_v_tile + 1;
4772 connector->tile_h_loc = tile_h_loc;
4773 connector->tile_v_loc = tile_v_loc;
4774 connector->tile_h_size = w + 1;
4775 connector->tile_v_size = h + 1;
4776
4777 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
4778 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
4779 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
4780 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
4781 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
4782
4783 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
4784 if (!tg) {
4785 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
4786 }
4787 if (!tg)
4788 return -ENOMEM;
4789
4790 if (connector->tile_group != tg) {
4791 /* if we haven't got a pointer,
4792 take the reference, drop ref to old tile group */
4793 if (connector->tile_group) {
4794 drm_mode_put_tile_group(connector->dev, connector->tile_group);
4795 }
4796 connector->tile_group = tg;
4797 } else
4798 /* if same tile group, then release the ref we just took. */
4799 drm_mode_put_tile_group(connector->dev, tg);
4800 return 0;
4801}
4802
40d9b043
DA		 4803static int drm_parse_display_id(struct drm_connector *connector,
4804 u8 *displayid, int length,
4805 bool is_edid_extension)
4806{
4807 /* if this is an EDID extension the first byte will be 0x70 */
4808 int idx = 0;
40d9b043 4809 struct displayid_block *block;
5e546cd5 4810 int ret;
40d9b043
DA		 4811
4812 if (is_edid_extension)
4813 idx = 1;
4814
c9729177
DA		 4815 ret = validate_displayid(displayid, length, idx);
4816 if (ret)
4817 return ret;
40d9b043 4818
3a4a2ea3
TB		 4819 idx += sizeof(struct displayid_hdr);
4820 while (block = (struct displayid_block *)&displayid[idx],
4821 idx + sizeof(struct displayid_block) <= length &&
4822 idx + sizeof(struct displayid_block) + block->num_bytes <= length &&
4823 block->num_bytes > 0) {
4824 idx += block->num_bytes + sizeof(struct displayid_block);
4825 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n",
4826 block->tag, block->rev, block->num_bytes);
4827
4828 switch (block->tag) {
4829 case DATA_BLOCK_TILED_DISPLAY:
4830 ret = drm_parse_tiled_block(connector, block);
4831 if (ret)
4832 return ret;
4833 break;
a39ed680
DA		 4834 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
4835 /* handled in mode gathering code. */
4836 break;
3a4a2ea3
TB		 4837 default:
4838 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag);
4839 break;
4840 }
40d9b043
DA		 4841 }
4842 return 0;
4843}
4844
4845static void drm_get_displayid(struct drm_connector *connector,
4846 struct edid *edid)
4847{
4848 void *displayid = NULL;
4849 int ret;
4850 connector->has_tile = false;
4851 displayid = drm_find_displayid_extension(edid);
4852 if (!displayid) {
4853 /* drop reference to any tile group we had */
4854 goto out_drop_ref;
4855 }
4856
4857 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true);
4858 if (ret < 0)
4859 goto out_drop_ref;
4860 if (!connector->has_tile)
4861 goto out_drop_ref;
4862 return;
4863out_drop_ref:
4864 if (connector->tile_group) {
4865 drm_mode_put_tile_group(connector->dev, connector->tile_group);
4866 connector->tile_group = NULL;
4867 }
4868 return;
4869}
Linux 6.x block layer and io_uring tree(s)