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vc4: fix build failure in vc4_dsi_dev_probe()
[linux-2.6-block.git] / drivers / gpu / drm / drm_edid.c
CommitLineData
f453ba04
DA		 1/*
2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
61e57a8d 5 * Copyright 2010 Red Hat, Inc.
f453ba04
DA		 6 *
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
8 * FB layer.
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 */
9c79edec 30
18a9cbbe 31#include <linux/bitfield.h>
10a85120 32#include <linux/hdmi.h>
f453ba04 33#include <linux/i2c.h>
9c79edec 34#include <linux/kernel.h>
47819ba2 35#include <linux/module.h>
36b73b05 36#include <linux/pci.h>
9c79edec 37#include <linux/slab.h>
5cb8eaa2 38#include <linux/vga_switcheroo.h>
9c79edec
JN		 39
40#include <drm/drm_displayid.h>
41#include <drm/drm_drv.h>
760285e7 42#include <drm/drm_edid.h>
9338203c 43#include <drm/drm_encoder.h>
9c79edec 44#include <drm/drm_print.h>
f453ba04 45
969218fe
TI		 46#include "drm_crtc_internal.h"
47
37eab1fe
JN		 48static int oui(u8 first, u8 second, u8 third)
49{
50 return (first << 16) | (second << 8) | third;
51}
52
d1ff6409
AJ		 53#define EDID_EST_TIMINGS 16
54#define EDID_STD_TIMINGS 8
55#define EDID_DETAILED_TIMINGS 4
f453ba04
DA		 56
57/*
58 * EDID blocks out in the wild have a variety of bugs, try to collect
59 * them here (note that userspace may work around broken monitors first,
60 * but fixes should make their way here so that the kernel "just works"
61 * on as many displays as possible).
62 */
63
64/* First detailed mode wrong, use largest 60Hz mode */
65#define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
66/* Reported 135MHz pixel clock is too high, needs adjustment */
67#define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
68/* Prefer the largest mode at 75 Hz */
69#define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
70/* Detail timing is in cm not mm */
71#define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
72/* Detailed timing descriptors have bogus size values, so just take the
73 * maximum size and use that.
74 */
75#define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
f453ba04
DA		 76/* use +hsync +vsync for detailed mode */
77#define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
bc42aabc
AJ		 78/* Force reduced-blanking timings for detailed modes */
79#define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
49d45a31
RM		 80/* Force 8bpc */
81#define EDID_QUIRK_FORCE_8BPC (1 << 8)
bc5b9641
MK		 82/* Force 12bpc */
83#define EDID_QUIRK_FORCE_12BPC (1 << 9)
e10aec65
MK		 84/* Force 6bpc */
85#define EDID_QUIRK_FORCE_6BPC (1 << 10)
e345da82
MK		 86/* Force 10bpc */
87#define EDID_QUIRK_FORCE_10BPC (1 << 11)
66660d4c
DA		 88/* Non desktop display (i.e. HMD) */
89#define EDID_QUIRK_NON_DESKTOP (1 << 12)
aa193f7e
HM		 90/* Cap the DSC target bitrate to 15bpp */
91#define EDID_QUIRK_CAP_DSC_15BPP (1 << 13)
3c537889 92
2869f599
PZ		 93#define MICROSOFT_IEEE_OUI 0xca125c
94
13931579
AJ		 95struct detailed_mode_closure {
96 struct drm_connector *connector;
dd0f4470 97 const struct drm_edid *drm_edid;
13931579
AJ		 98 bool preferred;
99 u32 quirks;
100 int modes;
101};
f453ba04 102
5c61259e
ZY		 103#define LEVEL_DMT 0
104#define LEVEL_GTF 1
7a374350
AJ		 105#define LEVEL_GTF2 2
106#define LEVEL_CVT 3
5c61259e 107
7d1be0a0 108#define EDID_QUIRK(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _quirks) \
e8de4d55 109{ \
7d1be0a0
DA		 110 .panel_id = drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, \
111 product_id), \
e8de4d55
DA		 112 .quirks = _quirks \
113}
114
23c4cfbd 115static const struct edid_quirk {
e8de4d55 116 u32 panel_id;
f453ba04
DA		 117 u32 quirks;
118} edid_quirk_list[] = {
119 /* Acer AL1706 */
7d1be0a0 120 EDID_QUIRK('A', 'C', 'R', 44358, EDID_QUIRK_PREFER_LARGE_60),
f453ba04 121 /* Acer F51 */
7d1be0a0 122 EDID_QUIRK('A', 'P', 'I', 0x7602, EDID_QUIRK_PREFER_LARGE_60),
f453ba04 123
e10aec65 124 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
7d1be0a0 125 EDID_QUIRK('A', 'E', 'O', 0, EDID_QUIRK_FORCE_6BPC),
e10aec65 126
0711a43b 127 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
7d1be0a0 128 EDID_QUIRK('B', 'O', 'E', 0x78b, EDID_QUIRK_FORCE_6BPC),
0711a43b 129
06998a75 130 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
7d1be0a0 131 EDID_QUIRK('C', 'P', 'T', 0x17df, EDID_QUIRK_FORCE_6BPC),
06998a75 132
25da7504 133 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
7d1be0a0 134 EDID_QUIRK('S', 'D', 'C', 0x3652, EDID_QUIRK_FORCE_6BPC),
25da7504 135
922dceff 136 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
7d1be0a0 137 EDID_QUIRK('B', 'O', 'E', 0x0771, EDID_QUIRK_FORCE_6BPC),
922dceff 138
f453ba04 139 /* Belinea 10 15 55 */
7d1be0a0
DA		 140 EDID_QUIRK('M', 'A', 'X', 1516, EDID_QUIRK_PREFER_LARGE_60),
141 EDID_QUIRK('M', 'A', 'X', 0x77e, EDID_QUIRK_PREFER_LARGE_60),
f453ba04
DA		 142
143 /* Envision Peripherals, Inc. EN-7100e */
7d1be0a0 144 EDID_QUIRK('E', 'P', 'I', 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH),
ba1163de 145 /* Envision EN2028 */
7d1be0a0 146 EDID_QUIRK('E', 'P', 'I', 8232, EDID_QUIRK_PREFER_LARGE_60),
f453ba04
DA		 147
148 /* Funai Electronics PM36B */
7d1be0a0 149 EDID_QUIRK('F', 'C', 'M', 13600, EDID_QUIRK_PREFER_LARGE_75 |
e8de4d55 150 EDID_QUIRK_DETAILED_IN_CM),
f453ba04 151
aa193f7e
HM		 152 /* LG 27GP950 */
153 EDID_QUIRK('G', 'S', 'M', 0x5bbf, EDID_QUIRK_CAP_DSC_15BPP),
154
155 /* LG 27GN950 */
156 EDID_QUIRK('G', 'S', 'M', 0x5b9a, EDID_QUIRK_CAP_DSC_15BPP),
157
e345da82 158 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
7d1be0a0 159 EDID_QUIRK('L', 'G', 'D', 764, EDID_QUIRK_FORCE_10BPC),
e345da82 160
f453ba04 161 /* LG Philips LCD LP154W01-A5 */
7d1be0a0
DA		 162 EDID_QUIRK('L', 'P', 'L', 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
163 EDID_QUIRK('L', 'P', 'L', 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
f453ba04 164
f453ba04 165 /* Samsung SyncMaster 205BW. Note: irony */
7d1be0a0 166 EDID_QUIRK('S', 'A', 'M', 541, EDID_QUIRK_DETAILED_SYNC_PP),
f453ba04 167 /* Samsung SyncMaster 22[5-6]BW */
7d1be0a0
DA		 168 EDID_QUIRK('S', 'A', 'M', 596, EDID_QUIRK_PREFER_LARGE_60),
169 EDID_QUIRK('S', 'A', 'M', 638, EDID_QUIRK_PREFER_LARGE_60),
bc42aabc 170
bc5b9641 171 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
7d1be0a0 172 EDID_QUIRK('S', 'N', 'Y', 0x2541, EDID_QUIRK_FORCE_12BPC),
bc5b9641 173
bc42aabc 174 /* ViewSonic VA2026w */
7d1be0a0 175 EDID_QUIRK('V', 'S', 'C', 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING),
118bdbd8
AD		 176
177 /* Medion MD 30217 PG */
7d1be0a0 178 EDID_QUIRK('M', 'E', 'D', 0x7b8, EDID_QUIRK_PREFER_LARGE_75),
49d45a31 179
11bcf5f7 180 /* Lenovo G50 */
7d1be0a0 181 EDID_QUIRK('S', 'D', 'C', 18514, EDID_QUIRK_FORCE_6BPC),
11bcf5f7 182
49d45a31 183 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
7d1be0a0 184 EDID_QUIRK('S', 'E', 'C', 0xd033, EDID_QUIRK_FORCE_8BPC),
36fc5797
TV		 185
186 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
7d1be0a0 187 EDID_QUIRK('E', 'T', 'R', 13896, EDID_QUIRK_FORCE_8BPC),
acb1d8ee 188
30d62d44 189 /* Valve Index Headset */
7d1be0a0
DA		 190 EDID_QUIRK('V', 'L', 'V', 0x91a8, EDID_QUIRK_NON_DESKTOP),
191 EDID_QUIRK('V', 'L', 'V', 0x91b0, EDID_QUIRK_NON_DESKTOP),
192 EDID_QUIRK('V', 'L', 'V', 0x91b1, EDID_QUIRK_NON_DESKTOP),
193 EDID_QUIRK('V', 'L', 'V', 0x91b2, EDID_QUIRK_NON_DESKTOP),
194 EDID_QUIRK('V', 'L', 'V', 0x91b3, EDID_QUIRK_NON_DESKTOP),
195 EDID_QUIRK('V', 'L', 'V', 0x91b4, EDID_QUIRK_NON_DESKTOP),
196 EDID_QUIRK('V', 'L', 'V', 0x91b5, EDID_QUIRK_NON_DESKTOP),
197 EDID_QUIRK('V', 'L', 'V', 0x91b6, EDID_QUIRK_NON_DESKTOP),
198 EDID_QUIRK('V', 'L', 'V', 0x91b7, EDID_QUIRK_NON_DESKTOP),
199 EDID_QUIRK('V', 'L', 'V', 0x91b8, EDID_QUIRK_NON_DESKTOP),
200 EDID_QUIRK('V', 'L', 'V', 0x91b9, EDID_QUIRK_NON_DESKTOP),
201 EDID_QUIRK('V', 'L', 'V', 0x91ba, EDID_QUIRK_NON_DESKTOP),
202 EDID_QUIRK('V', 'L', 'V', 0x91bb, EDID_QUIRK_NON_DESKTOP),
203 EDID_QUIRK('V', 'L', 'V', 0x91bc, EDID_QUIRK_NON_DESKTOP),
204 EDID_QUIRK('V', 'L', 'V', 0x91bd, EDID_QUIRK_NON_DESKTOP),
205 EDID_QUIRK('V', 'L', 'V', 0x91be, EDID_QUIRK_NON_DESKTOP),
206 EDID_QUIRK('V', 'L', 'V', 0x91bf, EDID_QUIRK_NON_DESKTOP),
30d62d44 207
6931317c 208 /* HTC Vive and Vive Pro VR Headsets */
7d1be0a0
DA		 209 EDID_QUIRK('H', 'V', 'R', 0xaa01, EDID_QUIRK_NON_DESKTOP),
210 EDID_QUIRK('H', 'V', 'R', 0xaa02, EDID_QUIRK_NON_DESKTOP),
b3b12ea3 211
5a3f6108 212 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */
7d1be0a0
DA		 213 EDID_QUIRK('O', 'V', 'R', 0x0001, EDID_QUIRK_NON_DESKTOP),
214 EDID_QUIRK('O', 'V', 'R', 0x0003, EDID_QUIRK_NON_DESKTOP),
215 EDID_QUIRK('O', 'V', 'R', 0x0004, EDID_QUIRK_NON_DESKTOP),
216 EDID_QUIRK('O', 'V', 'R', 0x0012, EDID_QUIRK_NON_DESKTOP),
90eda8fc
PZ		 217
218 /* Windows Mixed Reality Headsets */
7d1be0a0 219 EDID_QUIRK('A', 'C', 'R', 0x7fce, EDID_QUIRK_NON_DESKTOP),
7d1be0a0 220 EDID_QUIRK('L', 'E', 'N', 0x0408, EDID_QUIRK_NON_DESKTOP),
7d1be0a0
DA		 221 EDID_QUIRK('F', 'U', 'J', 0x1970, EDID_QUIRK_NON_DESKTOP),
222 EDID_QUIRK('D', 'E', 'L', 0x7fce, EDID_QUIRK_NON_DESKTOP),
223 EDID_QUIRK('S', 'E', 'C', 0x144a, EDID_QUIRK_NON_DESKTOP),
224 EDID_QUIRK('A', 'U', 'S', 0xc102, EDID_QUIRK_NON_DESKTOP),
ccffc9eb
PZ		 225
226 /* Sony PlayStation VR Headset */
7d1be0a0 227 EDID_QUIRK('S', 'N', 'Y', 0x0704, EDID_QUIRK_NON_DESKTOP),
29054230
RP		 228
229 /* Sensics VR Headsets */
7d1be0a0 230 EDID_QUIRK('S', 'E', 'N', 0x1019, EDID_QUIRK_NON_DESKTOP),
29054230
RP		 231
232 /* OSVR HDK and HDK2 VR Headsets */
7d1be0a0 233 EDID_QUIRK('S', 'V', 'R', 0x1019, EDID_QUIRK_NON_DESKTOP),
f453ba04
DA		 234};
235
a6b21831
TR		 236/*
237 * Autogenerated from the DMT spec.
238 * This table is copied from xfree86/modes/xf86EdidModes.c.
239 */
240static const struct drm_display_mode drm_dmt_modes[] = {
24b856b1 241 /* 0x01 - 640x350@85Hz */
a6b21831
TR		 242 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
243 736, 832, 0, 350, 382, 385, 445, 0,
244 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 245 /* 0x02 - 640x400@85Hz */
a6b21831
TR		 246 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
247 736, 832, 0, 400, 401, 404, 445, 0,
248 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 249 /* 0x03 - 720x400@85Hz */
a6b21831
TR		 250 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
251 828, 936, 0, 400, 401, 404, 446, 0,
252 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 253 /* 0x04 - 640x480@60Hz */
a6b21831 254 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
fcf22d05 255 752, 800, 0, 480, 490, 492, 525, 0,
a6b21831 256 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 257 /* 0x05 - 640x480@72Hz */
a6b21831
TR		 258 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
259 704, 832, 0, 480, 489, 492, 520, 0,
260 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 261 /* 0x06 - 640x480@75Hz */
a6b21831
TR		 262 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
263 720, 840, 0, 480, 481, 484, 500, 0,
264 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 265 /* 0x07 - 640x480@85Hz */
a6b21831
TR		 266 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
267 752, 832, 0, 480, 481, 484, 509, 0,
268 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 269 /* 0x08 - 800x600@56Hz */
a6b21831
TR		 270 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
271 896, 1024, 0, 600, 601, 603, 625, 0,
272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 273 /* 0x09 - 800x600@60Hz */
a6b21831
TR		 274 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
275 968, 1056, 0, 600, 601, 605, 628, 0,
276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 277 /* 0x0a - 800x600@72Hz */
a6b21831
TR		 278 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
279 976, 1040, 0, 600, 637, 643, 666, 0,
280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 281 /* 0x0b - 800x600@75Hz */
a6b21831
TR		 282 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
283 896, 1056, 0, 600, 601, 604, 625, 0,
284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 285 /* 0x0c - 800x600@85Hz */
a6b21831
TR		 286 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
287 896, 1048, 0, 600, 601, 604, 631, 0,
288 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 289 /* 0x0d - 800x600@120Hz RB */
a6b21831
TR		 290 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
291 880, 960, 0, 600, 603, 607, 636, 0,
292 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 293 /* 0x0e - 848x480@60Hz */
a6b21831
TR		 294 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
295 976, 1088, 0, 480, 486, 494, 517, 0,
296 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 297 /* 0x0f - 1024x768@43Hz, interlace */
a6b21831 298 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
735b100f 299 1208, 1264, 0, 768, 768, 776, 817, 0,
a6b21831 300 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
fcf22d05 301 DRM_MODE_FLAG_INTERLACE) },
24b856b1 302 /* 0x10 - 1024x768@60Hz */
a6b21831
TR		 303 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
304 1184, 1344, 0, 768, 771, 777, 806, 0,
305 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 306 /* 0x11 - 1024x768@70Hz */
a6b21831
TR		 307 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
308 1184, 1328, 0, 768, 771, 777, 806, 0,
309 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 310 /* 0x12 - 1024x768@75Hz */
a6b21831
TR		 311 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
312 1136, 1312, 0, 768, 769, 772, 800, 0,
313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 314 /* 0x13 - 1024x768@85Hz */
a6b21831
TR		 315 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
316 1168, 1376, 0, 768, 769, 772, 808, 0,
317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 318 /* 0x14 - 1024x768@120Hz RB */
a6b21831
TR		 319 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
320 1104, 1184, 0, 768, 771, 775, 813, 0,
321 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 322 /* 0x15 - 1152x864@75Hz */
a6b21831
TR		 323 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
324 1344, 1600, 0, 864, 865, 868, 900, 0,
325 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
bfcd74d2
VS		 326 /* 0x55 - 1280x720@60Hz */
327 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
328 1430, 1650, 0, 720, 725, 730, 750, 0,
329 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 330 /* 0x16 - 1280x768@60Hz RB */
a6b21831
TR		 331 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
332 1360, 1440, 0, 768, 771, 778, 790, 0,
333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 334 /* 0x17 - 1280x768@60Hz */
a6b21831
TR		 335 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
336 1472, 1664, 0, 768, 771, 778, 798, 0,
337 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 338 /* 0x18 - 1280x768@75Hz */
a6b21831
TR		 339 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
340 1488, 1696, 0, 768, 771, 778, 805, 0,
fcf22d05 341 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 342 /* 0x19 - 1280x768@85Hz */
a6b21831
TR		 343 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
344 1496, 1712, 0, 768, 771, 778, 809, 0,
345 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 346 /* 0x1a - 1280x768@120Hz RB */
a6b21831
TR		 347 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
348 1360, 1440, 0, 768, 771, 778, 813, 0,
349 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 350 /* 0x1b - 1280x800@60Hz RB */
a6b21831
TR		 351 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
352 1360, 1440, 0, 800, 803, 809, 823, 0,
353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 354 /* 0x1c - 1280x800@60Hz */
a6b21831
TR		 355 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
356 1480, 1680, 0, 800, 803, 809, 831, 0,
fcf22d05 357 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 358 /* 0x1d - 1280x800@75Hz */
a6b21831
TR		 359 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
360 1488, 1696, 0, 800, 803, 809, 838, 0,
361 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 362 /* 0x1e - 1280x800@85Hz */
a6b21831
TR		 363 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
364 1496, 1712, 0, 800, 803, 809, 843, 0,
365 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 366 /* 0x1f - 1280x800@120Hz RB */
a6b21831
TR		 367 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
368 1360, 1440, 0, 800, 803, 809, 847, 0,
369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 370 /* 0x20 - 1280x960@60Hz */
a6b21831
TR		 371 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
372 1488, 1800, 0, 960, 961, 964, 1000, 0,
373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 374 /* 0x21 - 1280x960@85Hz */
a6b21831
TR		 375 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
376 1504, 1728, 0, 960, 961, 964, 1011, 0,
377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 378 /* 0x22 - 1280x960@120Hz RB */
a6b21831
TR		 379 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
380 1360, 1440, 0, 960, 963, 967, 1017, 0,
381 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 382 /* 0x23 - 1280x1024@60Hz */
a6b21831
TR		 383 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
384 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 386 /* 0x24 - 1280x1024@75Hz */
a6b21831
TR		 387 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
388 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 390 /* 0x25 - 1280x1024@85Hz */
a6b21831
TR		 391 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
392 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 394 /* 0x26 - 1280x1024@120Hz RB */
a6b21831
TR		 395 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
396 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
397 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 398 /* 0x27 - 1360x768@60Hz */
a6b21831
TR		 399 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
400 1536, 1792, 0, 768, 771, 777, 795, 0,
401 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 402 /* 0x28 - 1360x768@120Hz RB */
a6b21831
TR		 403 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
404 1440, 1520, 0, 768, 771, 776, 813, 0,
405 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 406 /* 0x51 - 1366x768@60Hz */
407 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
408 1579, 1792, 0, 768, 771, 774, 798, 0,
409 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
410 /* 0x56 - 1366x768@60Hz */
411 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
412 1436, 1500, 0, 768, 769, 772, 800, 0,
413 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 414 /* 0x29 - 1400x1050@60Hz RB */
a6b21831
TR		 415 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
416 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
417 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 418 /* 0x2a - 1400x1050@60Hz */
a6b21831
TR		 419 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
420 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
421 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 422 /* 0x2b - 1400x1050@75Hz */
a6b21831
TR		 423 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
424 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
425 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 426 /* 0x2c - 1400x1050@85Hz */
a6b21831
TR		 427 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
428 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
429 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 430 /* 0x2d - 1400x1050@120Hz RB */
a6b21831
TR		 431 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
432 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
433 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 434 /* 0x2e - 1440x900@60Hz RB */
a6b21831
TR		 435 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
436 1520, 1600, 0, 900, 903, 909, 926, 0,
437 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 438 /* 0x2f - 1440x900@60Hz */
a6b21831
TR		 439 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
440 1672, 1904, 0, 900, 903, 909, 934, 0,
441 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 442 /* 0x30 - 1440x900@75Hz */
a6b21831
TR		 443 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
444 1688, 1936, 0, 900, 903, 909, 942, 0,
445 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 446 /* 0x31 - 1440x900@85Hz */
a6b21831
TR		 447 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
448 1696, 1952, 0, 900, 903, 909, 948, 0,
449 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 450 /* 0x32 - 1440x900@120Hz RB */
a6b21831
TR		 451 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
452 1520, 1600, 0, 900, 903, 909, 953, 0,
453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 454 /* 0x53 - 1600x900@60Hz */
455 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
456 1704, 1800, 0, 900, 901, 904, 1000, 0,
457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 458 /* 0x33 - 1600x1200@60Hz */
a6b21831
TR		 459 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
460 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 462 /* 0x34 - 1600x1200@65Hz */
a6b21831
TR		 463 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
464 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 466 /* 0x35 - 1600x1200@70Hz */
a6b21831
TR		 467 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
468 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 470 /* 0x36 - 1600x1200@75Hz */
a6b21831
TR		 471 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
472 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
473 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 474 /* 0x37 - 1600x1200@85Hz */
a6b21831
TR		 475 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
476 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
477 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 478 /* 0x38 - 1600x1200@120Hz RB */
a6b21831
TR		 479 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
480 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 482 /* 0x39 - 1680x1050@60Hz RB */
a6b21831
TR		 483 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
484 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
485 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 486 /* 0x3a - 1680x1050@60Hz */
a6b21831
TR		 487 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
488 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
489 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 490 /* 0x3b - 1680x1050@75Hz */
a6b21831
TR		 491 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
492 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
493 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 494 /* 0x3c - 1680x1050@85Hz */
a6b21831
TR		 495 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
496 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
497 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 498 /* 0x3d - 1680x1050@120Hz RB */
a6b21831
TR		 499 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
500 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
501 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 502 /* 0x3e - 1792x1344@60Hz */
a6b21831
TR		 503 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
504 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
505 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 506 /* 0x3f - 1792x1344@75Hz */
a6b21831
TR		 507 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
508 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
509 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 510 /* 0x40 - 1792x1344@120Hz RB */
a6b21831
TR		 511 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
512 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
513 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 514 /* 0x41 - 1856x1392@60Hz */
a6b21831
TR		 515 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
516 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
517 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 518 /* 0x42 - 1856x1392@75Hz */
a6b21831 519 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
fcf22d05 520 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
a6b21831 521 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 522 /* 0x43 - 1856x1392@120Hz RB */
a6b21831
TR		 523 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
524 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
525 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 526 /* 0x52 - 1920x1080@60Hz */
527 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
528 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
529 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 530 /* 0x44 - 1920x1200@60Hz RB */
a6b21831
TR		 531 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
532 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
533 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 534 /* 0x45 - 1920x1200@60Hz */
a6b21831
TR		 535 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
536 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
537 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 538 /* 0x46 - 1920x1200@75Hz */
a6b21831
TR		 539 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
540 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
541 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 542 /* 0x47 - 1920x1200@85Hz */
a6b21831
TR		 543 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
544 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
545 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 546 /* 0x48 - 1920x1200@120Hz RB */
a6b21831
TR		 547 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
548 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
549 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 550 /* 0x49 - 1920x1440@60Hz */
a6b21831
TR		 551 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
552 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
553 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 554 /* 0x4a - 1920x1440@75Hz */
a6b21831
TR		 555 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
556 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
557 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 558 /* 0x4b - 1920x1440@120Hz RB */
a6b21831
TR		 559 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
560 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
561 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 562 /* 0x54 - 2048x1152@60Hz */
563 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
564 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
565 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 566 /* 0x4c - 2560x1600@60Hz RB */
a6b21831
TR		 567 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
568 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
569 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 570 /* 0x4d - 2560x1600@60Hz */
a6b21831
TR		 571 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
572 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
573 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 574 /* 0x4e - 2560x1600@75Hz */
a6b21831
TR		 575 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
576 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
577 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 578 /* 0x4f - 2560x1600@85Hz */
a6b21831
TR		 579 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
580 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
581 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 582 /* 0x50 - 2560x1600@120Hz RB */
a6b21831
TR		 583 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
584 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
585 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 586 /* 0x57 - 4096x2160@60Hz RB */
587 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
588 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
589 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
590 /* 0x58 - 4096x2160@59.94Hz RB */
591 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
592 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
593 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
a6b21831
TR		 594};
595
e7bfa5c4
VS		 596/*
597 * These more or less come from the DMT spec. The 720x400 modes are
598 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
599 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
600 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
601 * mode.
602 *
603 * The DMT modes have been fact-checked; the rest are mild guesses.
604 */
a6b21831
TR		 605static const struct drm_display_mode edid_est_modes[] = {
606 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
607 968, 1056, 0, 600, 601, 605, 628, 0,
608 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
609 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
610 896, 1024, 0, 600, 601, 603, 625, 0,
611 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
612 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
613 720, 840, 0, 480, 481, 484, 500, 0,
614 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
615 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
87707cfd 616 704, 832, 0, 480, 489, 492, 520, 0,
a6b21831
TR		 617 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
618 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
619 768, 864, 0, 480, 483, 486, 525, 0,
620 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
87707cfd 621 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
a6b21831
TR		 622 752, 800, 0, 480, 490, 492, 525, 0,
623 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
624 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
625 846, 900, 0, 400, 421, 423, 449, 0,
626 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
627 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
628 846, 900, 0, 400, 412, 414, 449, 0,
629 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
630 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
631 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
632 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
87707cfd 633 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
a6b21831
TR		 634 1136, 1312, 0, 768, 769, 772, 800, 0,
635 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
636 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
637 1184, 1328, 0, 768, 771, 777, 806, 0,
638 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
639 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
640 1184, 1344, 0, 768, 771, 777, 806, 0,
641 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
642 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
643 1208, 1264, 0, 768, 768, 776, 817, 0,
644 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
645 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
646 928, 1152, 0, 624, 625, 628, 667, 0,
647 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
648 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
649 896, 1056, 0, 600, 601, 604, 625, 0,
650 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
651 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
652 976, 1040, 0, 600, 637, 643, 666, 0,
653 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
654 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
655 1344, 1600, 0, 864, 865, 868, 900, 0,
656 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
657};
658
659struct minimode {
660 short w;
661 short h;
662 short r;
663 short rb;
664};
665
666static const struct minimode est3_modes[] = {
667 /* byte 6 */
668 { 640, 350, 85, 0 },
669 { 640, 400, 85, 0 },
670 { 720, 400, 85, 0 },
671 { 640, 480, 85, 0 },
672 { 848, 480, 60, 0 },
673 { 800, 600, 85, 0 },
674 { 1024, 768, 85, 0 },
675 { 1152, 864, 75, 0 },
676 /* byte 7 */
677 { 1280, 768, 60, 1 },
678 { 1280, 768, 60, 0 },
679 { 1280, 768, 75, 0 },
680 { 1280, 768, 85, 0 },
681 { 1280, 960, 60, 0 },
682 { 1280, 960, 85, 0 },
683 { 1280, 1024, 60, 0 },
684 { 1280, 1024, 85, 0 },
685 /* byte 8 */
686 { 1360, 768, 60, 0 },
687 { 1440, 900, 60, 1 },
688 { 1440, 900, 60, 0 },
689 { 1440, 900, 75, 0 },
690 { 1440, 900, 85, 0 },
691 { 1400, 1050, 60, 1 },
692 { 1400, 1050, 60, 0 },
693 { 1400, 1050, 75, 0 },
694 /* byte 9 */
695 { 1400, 1050, 85, 0 },
696 { 1680, 1050, 60, 1 },
697 { 1680, 1050, 60, 0 },
698 { 1680, 1050, 75, 0 },
699 { 1680, 1050, 85, 0 },
700 { 1600, 1200, 60, 0 },
701 { 1600, 1200, 65, 0 },
702 { 1600, 1200, 70, 0 },
703 /* byte 10 */
704 { 1600, 1200, 75, 0 },
705 { 1600, 1200, 85, 0 },
706 { 1792, 1344, 60, 0 },
c068b32a 707 { 1792, 1344, 75, 0 },
a6b21831
TR		 708 { 1856, 1392, 60, 0 },
709 { 1856, 1392, 75, 0 },
710 { 1920, 1200, 60, 1 },
711 { 1920, 1200, 60, 0 },
712 /* byte 11 */
713 { 1920, 1200, 75, 0 },
714 { 1920, 1200, 85, 0 },
715 { 1920, 1440, 60, 0 },
716 { 1920, 1440, 75, 0 },
717};
718
719static const struct minimode extra_modes[] = {
720 { 1024, 576, 60, 0 },
721 { 1366, 768, 60, 0 },
722 { 1600, 900, 60, 0 },
723 { 1680, 945, 60, 0 },
724 { 1920, 1080, 60, 0 },
725 { 2048, 1152, 60, 0 },
726 { 2048, 1536, 60, 0 },
727};
728
729/*
7befe621 730 * From CEA/CTA-861 spec.
d9278b4c 731 *
7befe621 732 * Do not access directly, instead always use cea_mode_for_vic().
a6b21831 733 */
8c1b2bd9 734static const struct drm_display_mode edid_cea_modes_1[] = {
78691960 735 /* 1 - 640x480@60Hz 4:3 */
a6b21831
TR		 736 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
737 752, 800, 0, 480, 490, 492, 525, 0,
ee7925bb 738 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 739 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 740 /* 2 - 720x480@60Hz 4:3 */
a6b21831
TR		 741 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
742 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 743 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 744 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 745 /* 3 - 720x480@60Hz 16:9 */
a6b21831
TR		 746 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
747 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 748 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 749 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 750 /* 4 - 1280x720@60Hz 16:9 */
a6b21831
TR		 751 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
752 1430, 1650, 0, 720, 725, 730, 750, 0,
ee7925bb 753 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 754 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 755 /* 5 - 1920x1080i@60Hz 16:9 */
a6b21831
TR		 756 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
757 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
758 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 759 DRM_MODE_FLAG_INTERLACE),
0425662f 760 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 761 /* 6 - 720(1440)x480i@60Hz 4:3 */
fb01d280
CT		 762 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
763 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 764 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 765 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 766 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 767 /* 7 - 720(1440)x480i@60Hz 16:9 */
fb01d280
CT		 768 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
769 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 770 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 771 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 772 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 773 /* 8 - 720(1440)x240@60Hz 4:3 */
fb01d280
CT		 774 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
775 801, 858, 0, 240, 244, 247, 262, 0,
a6b21831 776 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 777 DRM_MODE_FLAG_DBLCLK),
0425662f 778 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 779 /* 9 - 720(1440)x240@60Hz 16:9 */
fb01d280
CT		 780 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
781 801, 858, 0, 240, 244, 247, 262, 0,
a6b21831 782 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 783 DRM_MODE_FLAG_DBLCLK),
0425662f 784 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 785 /* 10 - 2880x480i@60Hz 4:3 */
a6b21831
TR		 786 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
787 3204, 3432, 0, 480, 488, 494, 525, 0,
788 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 789 DRM_MODE_FLAG_INTERLACE),
0425662f 790 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 791 /* 11 - 2880x480i@60Hz 16:9 */
a6b21831
TR		 792 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
793 3204, 3432, 0, 480, 488, 494, 525, 0,
794 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 795 DRM_MODE_FLAG_INTERLACE),
0425662f 796 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 797 /* 12 - 2880x240@60Hz 4:3 */
a6b21831
TR		 798 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
799 3204, 3432, 0, 240, 244, 247, 262, 0,
ee7925bb 800 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 801 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 802 /* 13 - 2880x240@60Hz 16:9 */
a6b21831
TR		 803 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
804 3204, 3432, 0, 240, 244, 247, 262, 0,
ee7925bb 805 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 806 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 807 /* 14 - 1440x480@60Hz 4:3 */
a6b21831
TR		 808 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
809 1596, 1716, 0, 480, 489, 495, 525, 0,
ee7925bb 810 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 811 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 812 /* 15 - 1440x480@60Hz 16:9 */
a6b21831
TR		 813 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
814 1596, 1716, 0, 480, 489, 495, 525, 0,
ee7925bb 815 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 816 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 817 /* 16 - 1920x1080@60Hz 16:9 */
a6b21831
TR		 818 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
819 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 820 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 821 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 822 /* 17 - 720x576@50Hz 4:3 */
a6b21831
TR		 823 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
824 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 825 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 826 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 827 /* 18 - 720x576@50Hz 16:9 */
a6b21831
TR		 828 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
829 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 830 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 831 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 832 /* 19 - 1280x720@50Hz 16:9 */
a6b21831
TR		 833 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
834 1760, 1980, 0, 720, 725, 730, 750, 0,
ee7925bb 835 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 836 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 837 /* 20 - 1920x1080i@50Hz 16:9 */
a6b21831
TR		 838 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
839 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
840 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 841 DRM_MODE_FLAG_INTERLACE),
0425662f 842 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 843 /* 21 - 720(1440)x576i@50Hz 4:3 */
fb01d280
CT		 844 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
845 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 846 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 847 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 848 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 849 /* 22 - 720(1440)x576i@50Hz 16:9 */
fb01d280
CT		 850 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
851 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 852 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 853 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 854 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 855 /* 23 - 720(1440)x288@50Hz 4:3 */
fb01d280
CT		 856 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
857 795, 864, 0, 288, 290, 293, 312, 0,
a6b21831 858 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 859 DRM_MODE_FLAG_DBLCLK),
0425662f 860 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 861 /* 24 - 720(1440)x288@50Hz 16:9 */
fb01d280
CT		 862 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
863 795, 864, 0, 288, 290, 293, 312, 0,
a6b21831 864 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 865 DRM_MODE_FLAG_DBLCLK),
0425662f 866 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 867 /* 25 - 2880x576i@50Hz 4:3 */
a6b21831
TR		 868 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
869 3180, 3456, 0, 576, 580, 586, 625, 0,
870 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 871 DRM_MODE_FLAG_INTERLACE),
0425662f 872 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 873 /* 26 - 2880x576i@50Hz 16:9 */
a6b21831
TR		 874 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
875 3180, 3456, 0, 576, 580, 586, 625, 0,
876 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 877 DRM_MODE_FLAG_INTERLACE),
0425662f 878 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 879 /* 27 - 2880x288@50Hz 4:3 */
a6b21831
TR		 880 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
881 3180, 3456, 0, 288, 290, 293, 312, 0,
ee7925bb 882 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 883 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 884 /* 28 - 2880x288@50Hz 16:9 */
a6b21831
TR		 885 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
886 3180, 3456, 0, 288, 290, 293, 312, 0,
ee7925bb 887 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 888 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 889 /* 29 - 1440x576@50Hz 4:3 */
a6b21831
TR		 890 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
891 1592, 1728, 0, 576, 581, 586, 625, 0,
ee7925bb 892 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 893 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 894 /* 30 - 1440x576@50Hz 16:9 */
a6b21831
TR		 895 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
896 1592, 1728, 0, 576, 581, 586, 625, 0,
ee7925bb 897 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 898 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 899 /* 31 - 1920x1080@50Hz 16:9 */
a6b21831
TR		 900 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
901 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 902 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 903 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 904 /* 32 - 1920x1080@24Hz 16:9 */
a6b21831
TR		 905 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
906 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 907 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 908 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 909 /* 33 - 1920x1080@25Hz 16:9 */
a6b21831
TR		 910 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
911 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 912 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 913 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 914 /* 34 - 1920x1080@30Hz 16:9 */
a6b21831
TR		 915 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
916 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 917 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 918 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 919 /* 35 - 2880x480@60Hz 4:3 */
a6b21831
TR		 920 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
921 3192, 3432, 0, 480, 489, 495, 525, 0,
ee7925bb 922 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 923 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 924 /* 36 - 2880x480@60Hz 16:9 */
a6b21831
TR		 925 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
926 3192, 3432, 0, 480, 489, 495, 525, 0,
ee7925bb 927 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 928 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 929 /* 37 - 2880x576@50Hz 4:3 */
a6b21831
TR		 930 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
931 3184, 3456, 0, 576, 581, 586, 625, 0,
ee7925bb 932 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 933 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 934 /* 38 - 2880x576@50Hz 16:9 */
a6b21831
TR		 935 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
936 3184, 3456, 0, 576, 581, 586, 625, 0,
ee7925bb 937 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 938 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 939 /* 39 - 1920x1080i@50Hz 16:9 */
a6b21831
TR		 940 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
941 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
942 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 943 DRM_MODE_FLAG_INTERLACE),
0425662f 944 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 945 /* 40 - 1920x1080i@100Hz 16:9 */
a6b21831
TR		 946 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
947 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
948 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 949 DRM_MODE_FLAG_INTERLACE),
0425662f 950 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 951 /* 41 - 1280x720@100Hz 16:9 */
a6b21831
TR		 952 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
953 1760, 1980, 0, 720, 725, 730, 750, 0,
ee7925bb 954 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 955 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 956 /* 42 - 720x576@100Hz 4:3 */
a6b21831
TR		 957 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
958 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 959 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 960 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 961 /* 43 - 720x576@100Hz 16:9 */
a6b21831
TR		 962 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
963 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 964 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 965 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 966 /* 44 - 720(1440)x576i@100Hz 4:3 */
fb01d280
CT		 967 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
968 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 969 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 970 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 971 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 972 /* 45 - 720(1440)x576i@100Hz 16:9 */
fb01d280
CT		 973 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
974 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 975 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 976 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 977 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 978 /* 46 - 1920x1080i@120Hz 16:9 */
a6b21831
TR		 979 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
980 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
981 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
78691960 982 DRM_MODE_FLAG_INTERLACE),
0425662f 983 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 984 /* 47 - 1280x720@120Hz 16:9 */
a6b21831
TR		 985 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
986 1430, 1650, 0, 720, 725, 730, 750, 0,
ee7925bb 987 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 988 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 989 /* 48 - 720x480@120Hz 4:3 */
a6b21831
TR		 990 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
991 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 992 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 993 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 994 /* 49 - 720x480@120Hz 16:9 */
a6b21831
TR		 995 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
996 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 997 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 998 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 999 /* 50 - 720(1440)x480i@120Hz 4:3 */
fb01d280
CT		 1000 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
1001 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 1002 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1003 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1004 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1005 /* 51 - 720(1440)x480i@120Hz 16:9 */
fb01d280
CT		 1006 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
1007 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 1008 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1009 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1010 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1011 /* 52 - 720x576@200Hz 4:3 */
a6b21831
TR		 1012 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1013 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 1014 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 1015 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1016 /* 53 - 720x576@200Hz 16:9 */
a6b21831
TR		 1017 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1018 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 1019 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 1020 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1021 /* 54 - 720(1440)x576i@200Hz 4:3 */
fb01d280
CT		 1022 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1023 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 1024 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1025 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1026 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1027 /* 55 - 720(1440)x576i@200Hz 16:9 */
fb01d280
CT		 1028 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1029 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 1030 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1031 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1032 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1033 /* 56 - 720x480@240Hz 4:3 */
a6b21831
TR		 1034 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1035 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 1036 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 1037 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1038 /* 57 - 720x480@240Hz 16:9 */
a6b21831
TR		 1039 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1040 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 1041 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
0425662f 1042 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1043 /* 58 - 720(1440)x480i@240Hz 4:3 */
fb01d280
CT		 1044 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1045 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 1046 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1047 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1048 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
78691960 1049 /* 59 - 720(1440)x480i@240Hz 16:9 */
fb01d280
CT		 1050 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1051 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 1052 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78691960 1053 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
0425662f 1054 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1055 /* 60 - 1280x720@24Hz 16:9 */
a6b21831
TR		 1056 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1057 3080, 3300, 0, 720, 725, 730, 750, 0,
ee7925bb 1058 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1059 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1060 /* 61 - 1280x720@25Hz 16:9 */
a6b21831
TR		 1061 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1062 3740, 3960, 0, 720, 725, 730, 750, 0,
ee7925bb 1063 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1064 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1065 /* 62 - 1280x720@30Hz 16:9 */
a6b21831
TR		 1066 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1067 3080, 3300, 0, 720, 725, 730, 750, 0,
ee7925bb 1068 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1069 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1070 /* 63 - 1920x1080@120Hz 16:9 */
a6b21831
TR		 1071 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1072 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 1073 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1074 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1075 /* 64 - 1920x1080@100Hz 16:9 */
a6b21831 1076 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
8f0e4907 1077 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 1078 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1079 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1080 /* 65 - 1280x720@24Hz 64:27 */
8ec6e075
SS		 1081 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1082 3080, 3300, 0, 720, 725, 730, 750, 0,
1083 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1084 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1085 /* 66 - 1280x720@25Hz 64:27 */
8ec6e075
SS		 1086 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1087 3740, 3960, 0, 720, 725, 730, 750, 0,
1088 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1089 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1090 /* 67 - 1280x720@30Hz 64:27 */
8ec6e075
SS		 1091 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1092 3080, 3300, 0, 720, 725, 730, 750, 0,
1093 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1094 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1095 /* 68 - 1280x720@50Hz 64:27 */
8ec6e075
SS		 1096 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1097 1760, 1980, 0, 720, 725, 730, 750, 0,
1098 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1099 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1100 /* 69 - 1280x720@60Hz 64:27 */
8ec6e075
SS		 1101 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1102 1430, 1650, 0, 720, 725, 730, 750, 0,
1103 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1104 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1105 /* 70 - 1280x720@100Hz 64:27 */
8ec6e075
SS		 1106 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1107 1760, 1980, 0, 720, 725, 730, 750, 0,
1108 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1109 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1110 /* 71 - 1280x720@120Hz 64:27 */
8ec6e075
SS		 1111 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1112 1430, 1650, 0, 720, 725, 730, 750, 0,
1113 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1114 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1115 /* 72 - 1920x1080@24Hz 64:27 */
8ec6e075
SS		 1116 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1117 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1118 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1119 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1120 /* 73 - 1920x1080@25Hz 64:27 */
8ec6e075
SS		 1121 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1122 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1123 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1124 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1125 /* 74 - 1920x1080@30Hz 64:27 */
8ec6e075
SS		 1126 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1127 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1128 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1129 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1130 /* 75 - 1920x1080@50Hz 64:27 */
8ec6e075
SS		 1131 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1132 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1133 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1134 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1135 /* 76 - 1920x1080@60Hz 64:27 */
8ec6e075
SS		 1136 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1137 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1138 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1139 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1140 /* 77 - 1920x1080@100Hz 64:27 */
8ec6e075
SS		 1141 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1142 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1143 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1144 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1145 /* 78 - 1920x1080@120Hz 64:27 */
8ec6e075
SS		 1146 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1147 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1148 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1149 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1150 /* 79 - 1680x720@24Hz 64:27 */
8ec6e075
SS		 1151 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1152 3080, 3300, 0, 720, 725, 730, 750, 0,
1153 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1154 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1155 /* 80 - 1680x720@25Hz 64:27 */
8ec6e075
SS		 1156 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1157 2948, 3168, 0, 720, 725, 730, 750, 0,
1158 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1159 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1160 /* 81 - 1680x720@30Hz 64:27 */
8ec6e075
SS		 1161 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1162 2420, 2640, 0, 720, 725, 730, 750, 0,
1163 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1164 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1165 /* 82 - 1680x720@50Hz 64:27 */
8ec6e075
SS		 1166 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1167 1980, 2200, 0, 720, 725, 730, 750, 0,
1168 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1169 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1170 /* 83 - 1680x720@60Hz 64:27 */
8ec6e075
SS		 1171 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1172 1980, 2200, 0, 720, 725, 730, 750, 0,
1173 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1174 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1175 /* 84 - 1680x720@100Hz 64:27 */
8ec6e075
SS		 1176 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1177 1780, 2000, 0, 720, 725, 730, 825, 0,
1178 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1179 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1180 /* 85 - 1680x720@120Hz 64:27 */
8ec6e075
SS		 1181 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1182 1780, 2000, 0, 720, 725, 730, 825, 0,
1183 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1184 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1185 /* 86 - 2560x1080@24Hz 64:27 */
8ec6e075
SS		 1186 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1187 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1188 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1189 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1190 /* 87 - 2560x1080@25Hz 64:27 */
8ec6e075
SS		 1191 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1192 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1193 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1194 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1195 /* 88 - 2560x1080@30Hz 64:27 */
8ec6e075
SS		 1196 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1197 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1198 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1199 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1200 /* 89 - 2560x1080@50Hz 64:27 */
8ec6e075
SS		 1201 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1202 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1203 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1204 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1205 /* 90 - 2560x1080@60Hz 64:27 */
8ec6e075
SS		 1206 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1207 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1208 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1209 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1210 /* 91 - 2560x1080@100Hz 64:27 */
8ec6e075
SS		 1211 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1212 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1213 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1214 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1215 /* 92 - 2560x1080@120Hz 64:27 */
8ec6e075
SS		 1216 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1217 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1218 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1219 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1220 /* 93 - 3840x2160@24Hz 16:9 */
8ec6e075
SS		 1221 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1222 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1223 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1224 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1225 /* 94 - 3840x2160@25Hz 16:9 */
8ec6e075
SS		 1226 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1227 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1228 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1229 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1230 /* 95 - 3840x2160@30Hz 16:9 */
8ec6e075
SS		 1231 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1232 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1233 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1234 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1235 /* 96 - 3840x2160@50Hz 16:9 */
8ec6e075
SS		 1236 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1237 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1238 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1239 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1240 /* 97 - 3840x2160@60Hz 16:9 */
8ec6e075
SS		 1241 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1242 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1243 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1244 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
78691960 1245 /* 98 - 4096x2160@24Hz 256:135 */
8ec6e075
SS		 1246 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1247 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1248 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1249 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1250 /* 99 - 4096x2160@25Hz 256:135 */
8ec6e075
SS		 1251 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1252 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1253 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1254 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1255 /* 100 - 4096x2160@30Hz 256:135 */
8ec6e075
SS		 1256 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1257 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1258 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1259 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1260 /* 101 - 4096x2160@50Hz 256:135 */
8ec6e075
SS		 1261 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1262 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1263 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1264 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1265 /* 102 - 4096x2160@60Hz 256:135 */
8ec6e075
SS		 1266 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1267 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1269 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
78691960 1270 /* 103 - 3840x2160@24Hz 64:27 */
8ec6e075
SS		 1271 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1272 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1273 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1274 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1275 /* 104 - 3840x2160@25Hz 64:27 */
8ec6e075
SS		 1276 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1277 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1278 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1279 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1280 /* 105 - 3840x2160@30Hz 64:27 */
8ec6e075
SS		 1281 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1282 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1283 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1284 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1285 /* 106 - 3840x2160@50Hz 64:27 */
8ec6e075
SS		 1286 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1287 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1288 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1289 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
78691960 1290 /* 107 - 3840x2160@60Hz 64:27 */
8ec6e075
SS		 1291 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1292 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1293 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1294 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1295 /* 108 - 1280x720@48Hz 16:9 */
1296 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1297 2280, 2500, 0, 720, 725, 730, 750, 0,
1298 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1299 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1300 /* 109 - 1280x720@48Hz 64:27 */
1301 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1302 2280, 2500, 0, 720, 725, 730, 750, 0,
1303 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1304 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1305 /* 110 - 1680x720@48Hz 64:27 */
1306 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490,
1307 2530, 2750, 0, 720, 725, 730, 750, 0,
1308 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1309 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1310 /* 111 - 1920x1080@48Hz 16:9 */
1311 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1312 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1314 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1315 /* 112 - 1920x1080@48Hz 64:27 */
1316 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1317 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1318 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1319 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1320 /* 113 - 2560x1080@48Hz 64:27 */
1321 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558,
1322 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1323 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1324 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1325 /* 114 - 3840x2160@48Hz 16:9 */
1326 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1327 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1328 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1329 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1330 /* 115 - 4096x2160@48Hz 256:135 */
1331 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116,
1332 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1334 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
978f6b06
VS		 1335 /* 116 - 3840x2160@48Hz 64:27 */
1336 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1337 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1338 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1339 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1340 /* 117 - 3840x2160@100Hz 16:9 */
1341 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1342 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1343 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1344 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1345 /* 118 - 3840x2160@120Hz 16:9 */
1346 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1347 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1348 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1349 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978f6b06
VS		 1350 /* 119 - 3840x2160@100Hz 64:27 */
1351 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1352 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1354 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1355 /* 120 - 3840x2160@120Hz 64:27 */
1356 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1357 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1358 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1359 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1360 /* 121 - 5120x2160@24Hz 64:27 */
1361 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116,
1362 7204, 7500, 0, 2160, 2168, 2178, 2200, 0,
1363 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1364 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1365 /* 122 - 5120x2160@25Hz 64:27 */
1366 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816,
1367 6904, 7200, 0, 2160, 2168, 2178, 2200, 0,
1368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1369 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1370 /* 123 - 5120x2160@30Hz 64:27 */
1371 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784,
1372 5872, 6000, 0, 2160, 2168, 2178, 2200, 0,
1373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1374 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1375 /* 124 - 5120x2160@48Hz 64:27 */
1376 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866,
1377 5954, 6250, 0, 2160, 2168, 2178, 2475, 0,
1378 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1379 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1380 /* 125 - 5120x2160@50Hz 64:27 */
1381 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216,
1382 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1383 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1384 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1385 /* 126 - 5120x2160@60Hz 64:27 */
1386 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284,
1387 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1388 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1389 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
978f6b06
VS		 1390 /* 127 - 5120x2160@100Hz 64:27 */
1391 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216,
1392 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1394 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
a6b21831
TR		 1395};
1396
f7655d42
VS		 1397/*
1398 * From CEA/CTA-861 spec.
1399 *
1400 * Do not access directly, instead always use cea_mode_for_vic().
1401 */
1402static const struct drm_display_mode edid_cea_modes_193[] = {
1403 /* 193 - 5120x2160@120Hz 64:27 */
1404 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284,
1405 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1406 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1407 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1408 /* 194 - 7680x4320@24Hz 16:9 */
1409 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1410 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1411 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1412 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1413 /* 195 - 7680x4320@25Hz 16:9 */
1414 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1415 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1416 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1417 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1418 /* 196 - 7680x4320@30Hz 16:9 */
1419 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1420 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1421 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1422 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1423 /* 197 - 7680x4320@48Hz 16:9 */
1424 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1425 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1426 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1427 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1428 /* 198 - 7680x4320@50Hz 16:9 */
1429 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1430 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1431 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1432 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1433 /* 199 - 7680x4320@60Hz 16:9 */
1434 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1435 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1436 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1437 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1438 /* 200 - 7680x4320@100Hz 16:9 */
1439 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1440 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1441 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1442 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1443 /* 201 - 7680x4320@120Hz 16:9 */
1444 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1445 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1446 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1447 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
f7655d42
VS		 1448 /* 202 - 7680x4320@24Hz 64:27 */
1449 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1450 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1451 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1452 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1453 /* 203 - 7680x4320@25Hz 64:27 */
1454 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1455 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1456 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1457 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1458 /* 204 - 7680x4320@30Hz 64:27 */
1459 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1460 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1462 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1463 /* 205 - 7680x4320@48Hz 64:27 */
1464 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1465 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1466 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1467 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1468 /* 206 - 7680x4320@50Hz 64:27 */
1469 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1470 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1471 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1472 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1473 /* 207 - 7680x4320@60Hz 64:27 */
1474 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1475 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1476 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1477 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1478 /* 208 - 7680x4320@100Hz 64:27 */
1479 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1480 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1482 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1483 /* 209 - 7680x4320@120Hz 64:27 */
1484 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1485 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1486 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1487 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1488 /* 210 - 10240x4320@24Hz 64:27 */
1489 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732,
1490 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1491 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1492 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1493 /* 211 - 10240x4320@25Hz 64:27 */
1494 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732,
1495 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1496 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1497 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1498 /* 212 - 10240x4320@30Hz 64:27 */
1499 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528,
1500 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1501 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1502 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1503 /* 213 - 10240x4320@48Hz 64:27 */
1504 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732,
1505 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1506 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1507 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1508 /* 214 - 10240x4320@50Hz 64:27 */
1509 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732,
1510 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1511 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1512 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1513 /* 215 - 10240x4320@60Hz 64:27 */
1514 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528,
1515 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1516 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1517 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1518 /* 216 - 10240x4320@100Hz 64:27 */
1519 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432,
1520 12608, 13200, 0, 4320, 4336, 4356, 4500, 0,
1521 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1522 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1523 /* 217 - 10240x4320@120Hz 64:27 */
1524 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528,
1525 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1526 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1527 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
f7655d42
VS		 1528 /* 218 - 4096x2160@100Hz 256:135 */
1529 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896,
1530 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1531 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1532 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
f7655d42
VS		 1533 /* 219 - 4096x2160@120Hz 256:135 */
1534 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184,
1535 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1536 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1537 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
f7655d42
VS		 1538};
1539
7ebe1963 1540/*
d9278b4c 1541 * HDMI 1.4 4k modes. Index using the VIC.
7ebe1963
LD		 1542 */
1543static const struct drm_display_mode edid_4k_modes[] = {
d9278b4c
JN		 1544 /* 0 - dummy, VICs start at 1 */
1545 { },
7ebe1963
LD		 1546 /* 1 - 3840x2160@30Hz */
1547 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1548 3840, 4016, 4104, 4400, 0,
1549 2160, 2168, 2178, 2250, 0,
1550 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1551 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
7ebe1963
LD		 1552 /* 2 - 3840x2160@25Hz */
1553 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1554 3840, 4896, 4984, 5280, 0,
1555 2160, 2168, 2178, 2250, 0,
1556 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1557 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
7ebe1963
LD		 1558 /* 3 - 3840x2160@24Hz */
1559 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1560 3840, 5116, 5204, 5500, 0,
1561 2160, 2168, 2178, 2250, 0,
1562 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1563 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
7ebe1963
LD		 1564 /* 4 - 4096x2160@24Hz (SMPTE) */
1565 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1566 4096, 5116, 5204, 5500, 0,
1567 2160, 2168, 2178, 2250, 0,
1568 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
0425662f 1569 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
7ebe1963
LD		 1570};
1571
61e57a8d 1572/*** DDC fetch and block validation ***/
f453ba04 1573
e4ccf9a7
JN		 1574/*
1575 * The opaque EDID type, internal to drm_edid.c.
1576 */
1577struct drm_edid {
1578 /* Size allocated for edid */
1579 size_t size;
1580 const struct edid *edid;
1581};
1582
18e3c1d5
JN		 1583static int edid_hfeeodb_extension_block_count(const struct edid *edid);
1584
1585static int edid_hfeeodb_block_count(const struct edid *edid)
1586{
1587 int eeodb = edid_hfeeodb_extension_block_count(edid);
1588
1589 return eeodb ? eeodb + 1 : 0;
1590}
1591
f1e4c916
JN		 1592static int edid_extension_block_count(const struct edid *edid)
1593{
1594 return edid->extensions;
1595}
1596
1597static int edid_block_count(const struct edid *edid)
1598{
1599 return edid_extension_block_count(edid) + 1;
1600}
1601
1602static int edid_size_by_blocks(int num_blocks)
1603{
1604 return num_blocks * EDID_LENGTH;
1605}
1606
1607static int edid_size(const struct edid *edid)
1608{
1609 return edid_size_by_blocks(edid_block_count(edid));
1610}
1611
1612static const void *edid_block_data(const struct edid *edid, int index)
1613{
1614 BUILD_BUG_ON(sizeof(*edid) != EDID_LENGTH);
1615
1616 return edid + index;
1617}
1618
1619static const void *edid_extension_block_data(const struct edid *edid, int index)
1620{
1621 return edid_block_data(edid, index + 1);
1622}
1623
b16c9e6c
JN		 1624/* EDID block count indicated in EDID, may exceed allocated size */
1625static int __drm_edid_block_count(const struct drm_edid *drm_edid)
d9307f27
JN		 1626{
1627 int num_blocks;
1628
1629 /* Starting point */
1630 num_blocks = edid_block_count(drm_edid->edid);
1631
b1dee952
JN		 1632 /* HF-EEODB override */
1633 if (drm_edid->size >= edid_size_by_blocks(2)) {
1634 int eeodb;
1635
1636 /*
1637 * Note: HF-EEODB may specify a smaller extension count than the
1638 * regular one. Unlike in buffer allocation, here we can use it.
1639 */
1640 eeodb = edid_hfeeodb_block_count(drm_edid->edid);
1641 if (eeodb)
1642 num_blocks = eeodb;
1643 }
1644
d9307f27
JN		 1645 return num_blocks;
1646}
1647
b16c9e6c
JN		 1648/* EDID block count, limited by allocated size */
1649static int drm_edid_block_count(const struct drm_edid *drm_edid)
1650{
1651 /* Limit by allocated size */
1652 return min(__drm_edid_block_count(drm_edid),
1653 (int)drm_edid->size / EDID_LENGTH);
1654}
1655
1656/* EDID extension block count, limited by allocated size */
d9307f27
JN		 1657static int drm_edid_extension_block_count(const struct drm_edid *drm_edid)
1658{
1659 return drm_edid_block_count(drm_edid) - 1;
1660}
1661
1662static const void *drm_edid_block_data(const struct drm_edid *drm_edid, int index)
1663{
1664 return edid_block_data(drm_edid->edid, index);
1665}
1666
1667static const void *drm_edid_extension_block_data(const struct drm_edid *drm_edid,
1668 int index)
1669{
1670 return edid_extension_block_data(drm_edid->edid, index);
1671}
1672
22a27e05
JN		 1673/*
1674 * Initializer helper for legacy interfaces, where we have no choice but to
1675 * trust edid size. Not for general purpose use.
1676 */
1677static const struct drm_edid *drm_edid_legacy_init(struct drm_edid *drm_edid,
1678 const struct edid *edid)
1679{
1680 if (!edid)
1681 return NULL;
1682
1683 memset(drm_edid, 0, sizeof(*drm_edid));
1684
1685 drm_edid->edid = edid;
1686 drm_edid->size = edid_size(edid);
1687
1688 return drm_edid;
1689}
1690
94afc538
JN		 1691/*
1692 * EDID base and extension block iterator.
1693 *
1694 * struct drm_edid_iter iter;
1695 * const u8 *block;
1696 *
bbded689 1697 * drm_edid_iter_begin(drm_edid, &iter);
94afc538
JN		 1698 * drm_edid_iter_for_each(block, &iter) {
1699 * // do stuff with block
1700 * }
1701 * drm_edid_iter_end(&iter);
1702 */
1703struct drm_edid_iter {
bbded689 1704 const struct drm_edid *drm_edid;
94afc538
JN		 1705
1706 /* Current block index. */
1707 int index;
1708};
1709
bbded689 1710static void drm_edid_iter_begin(const struct drm_edid *drm_edid,
94afc538
JN		 1711 struct drm_edid_iter *iter)
1712{
1713 memset(iter, 0, sizeof(*iter));
1714
bbded689 1715 iter->drm_edid = drm_edid;
94afc538
JN		 1716}
1717
1718static const void *__drm_edid_iter_next(struct drm_edid_iter *iter)
1719{
1720 const void *block = NULL;
1721
bbded689 1722 if (!iter->drm_edid)
94afc538
JN		 1723 return NULL;
1724
d9307f27
JN		 1725 if (iter->index < drm_edid_block_count(iter->drm_edid))
1726 block = drm_edid_block_data(iter->drm_edid, iter->index++);
94afc538
JN		 1727
1728 return block;
1729}
1730
1731#define drm_edid_iter_for_each(__block, __iter) \
1732 while (((__block) = __drm_edid_iter_next(__iter)))
1733
1734static void drm_edid_iter_end(struct drm_edid_iter *iter)
1735{
1736 memset(iter, 0, sizeof(*iter));
1737}
1738
083ae056
AJ		 1739static const u8 edid_header[] = {
1740 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1741};
f453ba04 1742
0a612bbd
JN		 1743static void edid_header_fix(void *edid)
1744{
1745 memcpy(edid, edid_header, sizeof(edid_header));
1746}
1747
db6cf833
TR		 1748/**
1749 * drm_edid_header_is_valid - sanity check the header of the base EDID block
5d96fc9c 1750 * @_edid: pointer to raw base EDID block
db6cf833
TR		 1751 *
1752 * Sanity check the header of the base EDID block.
1753 *
1754 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
051963d4 1755 */
6d987ddd 1756int drm_edid_header_is_valid(const void *_edid)
051963d4 1757{
6d987ddd 1758 const struct edid *edid = _edid;
051963d4
TR		 1759 int i, score = 0;
1760
6d987ddd
JN		 1761 for (i = 0; i < sizeof(edid_header); i++) {
1762 if (edid->header[i] == edid_header[i])
051963d4 1763 score++;
6d987ddd 1764 }
051963d4
TR		 1765
1766 return score;
1767}
1768EXPORT_SYMBOL(drm_edid_header_is_valid);
1769
47819ba2
AJ		 1770static int edid_fixup __read_mostly = 6;
1771module_param_named(edid_fixup, edid_fixup, int, 0400);
1772MODULE_PARM_DESC(edid_fixup,
1773 "Minimum number of valid EDID header bytes (0-8, default 6)");
051963d4 1774
70e49ebe 1775static int edid_block_compute_checksum(const void *_block)
c465bbc8 1776{
70e49ebe 1777 const u8 *block = _block;
c465bbc8 1778 int i;
e11f5bd8
JFZ		 1779 u8 csum = 0, crc = 0;
1780
1781 for (i = 0; i < EDID_LENGTH - 1; i++)
70e49ebe 1782 csum += block[i];
c465bbc8 1783
e11f5bd8
JFZ		 1784 crc = 0x100 - csum;
1785
1786 return crc;
1787}
1788
70e49ebe 1789static int edid_block_get_checksum(const void *_block)
e11f5bd8 1790{
70e49ebe
JN		 1791 const struct edid *block = _block;
1792
1793 return block->checksum;
c465bbc8
SB		 1794}
1795
4ba0f53c
JN		 1796static int edid_block_tag(const void *_block)
1797{
1798 const u8 *block = _block;
1799
1800 return block[0];
1801}
1802
8baccb27 1803static bool edid_block_is_zero(const void *edid)
d6885d65 1804{
8baccb27 1805 return !memchr_inv(edid, 0, EDID_LENGTH);
d6885d65
SB		 1806}
1807
536faa45
SL		 1808/**
1809 * drm_edid_are_equal - compare two edid blobs.
1810 * @edid1: pointer to first blob
1811 * @edid2: pointer to second blob
1812 * This helper can be used during probing to determine if
1813 * edid had changed.
1814 */
1815bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2)
1816{
1817 int edid1_len, edid2_len;
1818 bool edid1_present = edid1 != NULL;
1819 bool edid2_present = edid2 != NULL;
1820
1821 if (edid1_present != edid2_present)
1822 return false;
1823
1824 if (edid1) {
f1e4c916
JN		 1825 edid1_len = edid_size(edid1);
1826 edid2_len = edid_size(edid2);
536faa45
SL		 1827
1828 if (edid1_len != edid2_len)
1829 return false;
1830
1831 if (memcmp(edid1, edid2, edid1_len))
1832 return false;
1833 }
1834
1835 return true;
1836}
1837EXPORT_SYMBOL(drm_edid_are_equal);
1838
1f221284
JN		 1839enum edid_block_status {
1840 EDID_BLOCK_OK = 0,
2deaf1c2 1841 EDID_BLOCK_READ_FAIL,
1f221284 1842 EDID_BLOCK_NULL,
49dc0558 1843 EDID_BLOCK_ZERO,
1f221284
JN		 1844 EDID_BLOCK_HEADER_CORRUPT,
1845 EDID_BLOCK_HEADER_REPAIR,
1846 EDID_BLOCK_HEADER_FIXED,
1847 EDID_BLOCK_CHECKSUM,
1848 EDID_BLOCK_VERSION,
1849};
1850
1851static enum edid_block_status edid_block_check(const void *_block,
1852 bool is_base_block)
1853{
1854 const struct edid *block = _block;
1855
1856 if (!block)
1857 return EDID_BLOCK_NULL;
1858
1859 if (is_base_block) {
1860 int score = drm_edid_header_is_valid(block);
1861
49dc0558
JN		 1862 if (score < clamp(edid_fixup, 0, 8)) {
1863 if (edid_block_is_zero(block))
1864 return EDID_BLOCK_ZERO;
1865 else
1866 return EDID_BLOCK_HEADER_CORRUPT;
1867 }
1f221284
JN		 1868
1869 if (score < 8)
1870 return EDID_BLOCK_HEADER_REPAIR;
1871 }
1872
49dc0558
JN		 1873 if (edid_block_compute_checksum(block) != edid_block_get_checksum(block)) {
1874 if (edid_block_is_zero(block))
1875 return EDID_BLOCK_ZERO;
1876 else
1877 return EDID_BLOCK_CHECKSUM;
1878 }
1f221284
JN		 1879
1880 if (is_base_block) {
1881 if (block->version != 1)
1882 return EDID_BLOCK_VERSION;
1883 }
1884
1885 return EDID_BLOCK_OK;
1886}
1887
1888static bool edid_block_status_valid(enum edid_block_status status, int tag)
1889{
1890 return status == EDID_BLOCK_OK ||
1891 status == EDID_BLOCK_HEADER_FIXED ||
1892 (status == EDID_BLOCK_CHECKSUM && tag == CEA_EXT);
1893}
1894
23e38d7b
JN		 1895static bool edid_block_valid(const void *block, bool base)
1896{
1897 return edid_block_status_valid(edid_block_check(block, base),
1898 edid_block_tag(block));
1899}
1900
cee2ce1a
JN		 1901static void edid_block_status_print(enum edid_block_status status,
1902 const struct edid *block,
1903 int block_num)
1904{
1905 switch (status) {
1906 case EDID_BLOCK_OK:
1907 break;
2deaf1c2
JN		 1908 case EDID_BLOCK_READ_FAIL:
1909 pr_debug("EDID block %d read failed\n", block_num);
1910 break;
cee2ce1a
JN		 1911 case EDID_BLOCK_NULL:
1912 pr_debug("EDID block %d pointer is NULL\n", block_num);
1913 break;
1914 case EDID_BLOCK_ZERO:
1915 pr_notice("EDID block %d is all zeroes\n", block_num);
1916 break;
1917 case EDID_BLOCK_HEADER_CORRUPT:
1918 pr_notice("EDID has corrupt header\n");
1919 break;
1920 case EDID_BLOCK_HEADER_REPAIR:
1921 pr_debug("EDID corrupt header needs repair\n");
1922 break;
1923 case EDID_BLOCK_HEADER_FIXED:
1924 pr_debug("EDID corrupt header fixed\n");
1925 break;
1926 case EDID_BLOCK_CHECKSUM:
1927 if (edid_block_status_valid(status, edid_block_tag(block))) {
1928 pr_debug("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d, ignoring\n",
1929 block_num, edid_block_tag(block),
1930 edid_block_compute_checksum(block));
1931 } else {
1932 pr_notice("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d\n",
1933 block_num, edid_block_tag(block),
1934 edid_block_compute_checksum(block));
1935 }
1936 break;
1937 case EDID_BLOCK_VERSION:
1938 pr_notice("EDID has major version %d, instead of 1\n",
1939 block->version);
1940 break;
1941 default:
1942 WARN(1, "EDID block %d unknown edid block status code %d\n",
1943 block_num, status);
1944 break;
1945 }
1946}
1947
9c7345de
JN		 1948static void edid_block_dump(const char *level, const void *block, int block_num)
1949{
1950 enum edid_block_status status;
1951 char prefix[20];
1952
1953 status = edid_block_check(block, block_num == 0);
1954 if (status == EDID_BLOCK_ZERO)
1955 sprintf(prefix, "\t[%02x] ZERO ", block_num);
1956 else if (!edid_block_status_valid(status, edid_block_tag(block)))
1957 sprintf(prefix, "\t[%02x] BAD ", block_num);
1958 else
1959 sprintf(prefix, "\t[%02x] GOOD ", block_num);
1960
1961 print_hex_dump(level, prefix, DUMP_PREFIX_NONE, 16, 1,
1962 block, EDID_LENGTH, false);
1963}
1964
db6cf833
TR		 1965/**
1966 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
5d96fc9c 1967 * @_block: pointer to raw EDID block
1f221284 1968 * @block_num: type of block to validate (0 for base, extension otherwise)
db6cf833 1969 * @print_bad_edid: if true, dump bad EDID blocks to the console
6ba2bd3d 1970 * @edid_corrupt: if true, the header or checksum is invalid
db6cf833
TR		 1971 *
1972 * Validate a base or extension EDID block and optionally dump bad blocks to
1973 * the console.
1974 *
1975 * Return: True if the block is valid, false otherwise.
f453ba04 1976 */
1f221284 1977bool drm_edid_block_valid(u8 *_block, int block_num, bool print_bad_edid,
6ba2bd3d 1978 bool *edid_corrupt)
f453ba04 1979{
1f221284
JN		 1980 struct edid *block = (struct edid *)_block;
1981 enum edid_block_status status;
1982 bool is_base_block = block_num == 0;
1983 bool valid;
f453ba04 1984
1f221284 1985 if (WARN_ON(!block))
fe2ef780
SWK		 1986 return false;
1987
1f221284
JN		 1988 status = edid_block_check(block, is_base_block);
1989 if (status == EDID_BLOCK_HEADER_REPAIR) {
e1e7bc48 1990 DRM_DEBUG_KMS("Fixing EDID header, your hardware may be failing\n");
1f221284
JN		 1991 edid_header_fix(block);
1992
1993 /* Retry with fixed header, update status if that worked. */
1994 status = edid_block_check(block, is_base_block);
1995 if (status == EDID_BLOCK_OK)
1996 status = EDID_BLOCK_HEADER_FIXED;
61e57a8d 1997 }
f453ba04 1998
1f221284
JN		 1999 if (edid_corrupt) {
2000 /*
2001 * Unknown major version isn't corrupt but we can't use it. Only
2002 * the base block can reset edid_corrupt to false.
2003 */
2004 if (is_base_block &&
2005 (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION))
2006 *edid_corrupt = false;
2007 else if (status != EDID_BLOCK_OK)
ac6f2e29 2008 *edid_corrupt = true;
f453ba04
DA		 2009 }
2010
cee2ce1a
JN		 2011 edid_block_status_print(status, block, block_num);
2012
1f221284
JN		 2013 /* Determine whether we can use this block with this status. */
2014 valid = edid_block_status_valid(status, edid_block_tag(block));
2015
cee2ce1a
JN		 2016 if (!valid && print_bad_edid && status != EDID_BLOCK_ZERO) {
2017 pr_notice("Raw EDID:\n");
9c7345de 2018 edid_block_dump(KERN_NOTICE, block, block_num);
f453ba04 2019 }
1f221284
JN		 2020
2021 return valid;
f453ba04 2022}
da0df92b 2023EXPORT_SYMBOL(drm_edid_block_valid);
61e57a8d
AJ		 2024
2025/**
2026 * drm_edid_is_valid - sanity check EDID data
2027 * @edid: EDID data
2028 *
2029 * Sanity-check an entire EDID record (including extensions)
db6cf833
TR		 2030 *
2031 * Return: True if the EDID data is valid, false otherwise.
61e57a8d
AJ		 2032 */
2033bool drm_edid_is_valid(struct edid *edid)
2034{
2035 int i;
61e57a8d
AJ		 2036
2037 if (!edid)
2038 return false;
2039
f1e4c916
JN		 2040 for (i = 0; i < edid_block_count(edid); i++) {
2041 void *block = (void *)edid_block_data(edid, i);
2042
2043 if (!drm_edid_block_valid(block, i, true, NULL))
61e57a8d 2044 return false;
f1e4c916 2045 }
61e57a8d
AJ		 2046
2047 return true;
2048}
3c537889 2049EXPORT_SYMBOL(drm_edid_is_valid);
f453ba04 2050
6c9b3db7
JN		 2051/**
2052 * drm_edid_valid - sanity check EDID data
2053 * @drm_edid: EDID data
2054 *
2055 * Sanity check an EDID. Cross check block count against allocated size and
2056 * checksum the blocks.
2057 *
2058 * Return: True if the EDID data is valid, false otherwise.
2059 */
2060bool drm_edid_valid(const struct drm_edid *drm_edid)
2061{
2062 int i;
2063
2064 if (!drm_edid)
2065 return false;
2066
2067 if (edid_size_by_blocks(__drm_edid_block_count(drm_edid)) != drm_edid->size)
2068 return false;
2069
2070 for (i = 0; i < drm_edid_block_count(drm_edid); i++) {
2071 const void *block = drm_edid_block_data(drm_edid, i);
2072
2073 if (!edid_block_valid(block, i == 0))
2074 return false;
2075 }
2076
2077 return true;
2078}
2079EXPORT_SYMBOL(drm_edid_valid);
2080
89f4b4c5 2081static struct edid *edid_filter_invalid_blocks(struct edid *edid,
407d63b3 2082 size_t *alloc_size)
4ec53461 2083{
89f4b4c5
JN		 2084 struct edid *new;
2085 int i, valid_blocks = 0;
4ec53461 2086
18e3c1d5
JN		 2087 /*
2088 * Note: If the EDID uses HF-EEODB, but has invalid blocks, we'll revert
2089 * back to regular extension count here. We don't want to start
2090 * modifying the HF-EEODB extension too.
2091 */
89f4b4c5
JN		 2092 for (i = 0; i < edid_block_count(edid); i++) {
2093 const void *src_block = edid_block_data(edid, i);
407d63b3 2094
89f4b4c5
JN		 2095 if (edid_block_valid(src_block, i == 0)) {
2096 void *dst_block = (void *)edid_block_data(edid, valid_blocks);
4ec53461 2097
89f4b4c5
JN		 2098 memmove(dst_block, src_block, EDID_LENGTH);
2099 valid_blocks++;
2100 }
2101 }
4ec53461 2102
89f4b4c5
JN		 2103 /* We already trusted the base block to be valid here... */
2104 if (WARN_ON(!valid_blocks)) {
2105 kfree(edid);
2106 return NULL;
4ec53461
JN		 2107 }
2108
89f4b4c5
JN		 2109 edid->extensions = valid_blocks - 1;
2110 edid->checksum = edid_block_compute_checksum(edid);
4ec53461 2111
89f4b4c5
JN		 2112 *alloc_size = edid_size_by_blocks(valid_blocks);
2113
2114 new = krealloc(edid, *alloc_size, GFP_KERNEL);
2115 if (!new)
2116 kfree(edid);
4ec53461
JN		 2117
2118 return new;
2119}
2120
61e57a8d
AJ		 2121#define DDC_SEGMENT_ADDR 0x30
2122/**
db6cf833 2123 * drm_do_probe_ddc_edid() - get EDID information via I2C
7c58e87e 2124 * @data: I2C device adapter
fc66811c
DV		 2125 * @buf: EDID data buffer to be filled
2126 * @block: 128 byte EDID block to start fetching from
2127 * @len: EDID data buffer length to fetch
2128 *
db6cf833 2129 * Try to fetch EDID information by calling I2C driver functions.
61e57a8d 2130 *
db6cf833 2131 * Return: 0 on success or -1 on failure.
61e57a8d
AJ		 2132 */
2133static int
18df89fe 2134drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
61e57a8d 2135{
18df89fe 2136 struct i2c_adapter *adapter = data;
61e57a8d 2137 unsigned char start = block * EDID_LENGTH;
cd004b3f
S		 2138 unsigned char segment = block >> 1;
2139 unsigned char xfers = segment ? 3 : 2;
4819d2e4
CW		 2140 int ret, retries = 5;
2141
db6cf833
TR		 2142 /*
2143 * The core I2C driver will automatically retry the transfer if the
4819d2e4
CW		 2144 * adapter reports EAGAIN. However, we find that bit-banging transfers
2145 * are susceptible to errors under a heavily loaded machine and
2146 * generate spurious NAKs and timeouts. Retrying the transfer
2147 * of the individual block a few times seems to overcome this.
2148 */
2149 do {
2150 struct i2c_msg msgs[] = {
2151 {
cd004b3f
S		 2152 .addr = DDC_SEGMENT_ADDR,
2153 .flags = 0,
2154 .len = 1,
2155 .buf = &segment,
2156 }, {
4819d2e4
CW		 2157 .addr = DDC_ADDR,
2158 .flags = 0,
2159 .len = 1,
2160 .buf = &start,
2161 }, {
2162 .addr = DDC_ADDR,
2163 .flags = I2C_M_RD,
2164 .len = len,
2165 .buf = buf,
2166 }
2167 };
cd004b3f 2168
db6cf833
TR		 2169 /*
2170 * Avoid sending the segment addr to not upset non-compliant
2171 * DDC monitors.
2172 */
cd004b3f
S		 2173 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
2174
9292f37e
ED		 2175 if (ret == -ENXIO) {
2176 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
2177 adapter->name);
2178 break;
2179 }
cd004b3f 2180 } while (ret != xfers && --retries);
4819d2e4 2181
cd004b3f 2182 return ret == xfers ? 0 : -1;
61e57a8d
AJ		 2183}
2184
14544d09 2185static void connector_bad_edid(struct drm_connector *connector,
63cae081 2186 const struct edid *edid, int num_blocks)
14544d09
CW		 2187{
2188 int i;
97794170
DA		 2189 u8 last_block;
2190
2191 /*
2192 * 0x7e in the EDID is the number of extension blocks. The EDID
2193 * is 1 (base block) + num_ext_blocks big. That means we can think
2194 * of 0x7e in the EDID of the _index_ of the last block in the
2195 * combined chunk of memory.
2196 */
63cae081 2197 last_block = edid->extensions;
e11f5bd8
JFZ		 2198
2199 /* Calculate real checksum for the last edid extension block data */
97794170
DA		 2200 if (last_block < num_blocks)
2201 connector->real_edid_checksum =
63cae081 2202 edid_block_compute_checksum(edid + last_block);
14544d09 2203
f0a8f533 2204 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
14544d09
CW		 2205 return;
2206
66d17ecd
JN		 2207 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID is invalid:\n",
2208 connector->base.id, connector->name);
63cae081
JN		 2209 for (i = 0; i < num_blocks; i++)
2210 edid_block_dump(KERN_DEBUG, edid + i, i);
14544d09
CW		 2211}
2212
56a2b7f2 2213/* Get override or firmware EDID */
794aca0e 2214static const struct drm_edid *drm_edid_override_get(struct drm_connector *connector)
56a2b7f2 2215{
794aca0e 2216 const struct drm_edid *override = NULL;
56a2b7f2 2217
90b575f5
JN		 2218 mutex_lock(&connector->edid_override_mutex);
2219
2220 if (connector->edid_override)
794aca0e 2221 override = drm_edid_dup(connector->edid_override);
90b575f5
JN		 2222
2223 mutex_unlock(&connector->edid_override_mutex);
56a2b7f2
JN		 2224
2225 if (!override)
a05992d5 2226 override = drm_edid_load_firmware(connector);
56a2b7f2
JN		 2227
2228 return IS_ERR(override) ? NULL : override;
2229}
2230
91ec9ab4
JN		 2231/* For debugfs edid_override implementation */
2232int drm_edid_override_show(struct drm_connector *connector, struct seq_file *m)
2233{
90b575f5 2234 const struct drm_edid *drm_edid;
91ec9ab4 2235
90b575f5
JN		 2236 mutex_lock(&connector->edid_override_mutex);
2237
2238 drm_edid = connector->edid_override;
2239 if (drm_edid)
2240 seq_write(m, drm_edid->edid, drm_edid->size);
2241
2242 mutex_unlock(&connector->edid_override_mutex);
91ec9ab4
JN		 2243
2244 return 0;
2245}
2246
6aa145bc
JN		 2247/* For debugfs edid_override implementation */
2248int drm_edid_override_set(struct drm_connector *connector, const void *edid,
2249 size_t size)
2250{
90b575f5 2251 const struct drm_edid *drm_edid;
6aa145bc 2252
90b575f5
JN		 2253 drm_edid = drm_edid_alloc(edid, size);
2254 if (!drm_edid_valid(drm_edid)) {
2255 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override invalid\n",
2256 connector->base.id, connector->name);
2257 drm_edid_free(drm_edid);
6aa145bc 2258 return -EINVAL;
90b575f5 2259 }
6aa145bc 2260
2c9332de
JN		 2261 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override set\n",
2262 connector->base.id, connector->name);
2263
90b575f5 2264 mutex_lock(&connector->edid_override_mutex);
6aa145bc 2265
90b575f5
JN		 2266 drm_edid_free(connector->edid_override);
2267 connector->edid_override = drm_edid;
2268
2269 mutex_unlock(&connector->edid_override_mutex);
2270
2271 return 0;
6aa145bc
JN		 2272}
2273
2274/* For debugfs edid_override implementation */
2275int drm_edid_override_reset(struct drm_connector *connector)
2276{
2c9332de
JN		 2277 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override reset\n",
2278 connector->base.id, connector->name);
2279
90b575f5
JN		 2280 mutex_lock(&connector->edid_override_mutex);
2281
2282 drm_edid_free(connector->edid_override);
2283 connector->edid_override = NULL;
2284
2285 mutex_unlock(&connector->edid_override_mutex);
2286
2287 return 0;
6aa145bc
JN		 2288}
2289
48eaeb76 2290/**
019b9387 2291 * drm_edid_override_connector_update - add modes from override/firmware EDID
48eaeb76
JN		 2292 * @connector: connector we're probing
2293 *
2294 * Add modes from the override/firmware EDID, if available. Only to be used from
2295 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
2296 * failed during drm_get_edid() and caused the override/firmware EDID to be
2297 * skipped.
2298 *
2299 * Return: The number of modes added or 0 if we couldn't find any.
2300 */
019b9387 2301int drm_edid_override_connector_update(struct drm_connector *connector)
48eaeb76 2302{
794aca0e 2303 const struct drm_edid *override;
48eaeb76
JN		 2304 int num_modes = 0;
2305
794aca0e 2306 override = drm_edid_override_get(connector);
48eaeb76 2307 if (override) {
794aca0e
JN		 2308 num_modes = drm_edid_connector_update(connector, override);
2309
2310 drm_edid_free(override);
48eaeb76 2311
e1e7bc48
JN		 2312 drm_dbg_kms(connector->dev,
2313 "[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
2314 connector->base.id, connector->name, num_modes);
48eaeb76
JN		 2315 }
2316
2317 return num_modes;
2318}
019b9387 2319EXPORT_SYMBOL(drm_edid_override_connector_update);
48eaeb76 2320
89fb7536
JN		 2321typedef int read_block_fn(void *context, u8 *buf, unsigned int block, size_t len);
2322
2deaf1c2
JN		 2323static enum edid_block_status edid_block_read(void *block, unsigned int block_num,
2324 read_block_fn read_block,
2325 void *context)
2326{
2327 enum edid_block_status status;
2328 bool is_base_block = block_num == 0;
2329 int try;
2330
2331 for (try = 0; try < 4; try++) {
2332 if (read_block(context, block, block_num, EDID_LENGTH))
2333 return EDID_BLOCK_READ_FAIL;
2334
2335 status = edid_block_check(block, is_base_block);
2336 if (status == EDID_BLOCK_HEADER_REPAIR) {
2337 edid_header_fix(block);
2338
2339 /* Retry with fixed header, update status if that worked. */
2340 status = edid_block_check(block, is_base_block);
2341 if (status == EDID_BLOCK_OK)
2342 status = EDID_BLOCK_HEADER_FIXED;
2343 }
2344
2345 if (edid_block_status_valid(status, edid_block_tag(block)))
2346 break;
2347
2348 /* Fail early for unrepairable base block all zeros. */
2349 if (try == 0 && is_base_block && status == EDID_BLOCK_ZERO)
2350 break;
2351 }
2352
2353 return status;
2354}
2355
6537f79a
JN		 2356static struct edid *_drm_do_get_edid(struct drm_connector *connector,
2357 read_block_fn read_block, void *context,
2358 size_t *size)
61e57a8d 2359{
c12561ce 2360 enum edid_block_status status;
18e3c1d5 2361 int i, num_blocks, invalid_blocks = 0;
794aca0e 2362 const struct drm_edid *override;
b3eb97b6 2363 struct edid *edid, *new;
407d63b3 2364 size_t alloc_size = EDID_LENGTH;
53fd40a9 2365
794aca0e
JN		 2366 override = drm_edid_override_get(connector);
2367 if (override) {
2368 alloc_size = override->size;
2369 edid = kmemdup(override->edid, alloc_size, GFP_KERNEL);
2370 drm_edid_free(override);
2371 if (!edid)
2372 return NULL;
1c788f69 2373 goto ok;
794aca0e 2374 }
61e57a8d 2375
407d63b3 2376 edid = kmalloc(alloc_size, GFP_KERNEL);
e7bd95a7 2377 if (!edid)
61e57a8d 2378 return NULL;
61e57a8d 2379
c12561ce
JN		 2380 status = edid_block_read(edid, 0, read_block, context);
2381
2382 edid_block_status_print(status, edid, 0);
2383
2384 if (status == EDID_BLOCK_READ_FAIL)
1c788f69 2385 goto fail;
c12561ce
JN		 2386
2387 /* FIXME: Clarify what a corrupt EDID actually means. */
2388 if (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION)
2389 connector->edid_corrupt = false;
2390 else
2391 connector->edid_corrupt = true;
2392
2393 if (!edid_block_status_valid(status, edid_block_tag(edid))) {
2394 if (status == EDID_BLOCK_ZERO)
2395 connector->null_edid_counter++;
2396
2397 connector_bad_edid(connector, edid, 1);
1c788f69 2398 goto fail;
c12561ce
JN		 2399 }
2400
f1e4c916 2401 if (!edid_extension_block_count(edid))
1c788f69 2402 goto ok;
61e57a8d 2403
407d63b3
JN		 2404 alloc_size = edid_size(edid);
2405 new = krealloc(edid, alloc_size, GFP_KERNEL);
61e57a8d 2406 if (!new)
1c788f69 2407 goto fail;
f14f3686 2408 edid = new;
61e57a8d 2409
18e3c1d5
JN		 2410 num_blocks = edid_block_count(edid);
2411 for (i = 1; i < num_blocks; i++) {
f1e4c916 2412 void *block = (void *)edid_block_data(edid, i);
a28187cc 2413
f1e4c916 2414 status = edid_block_read(block, i, read_block, context);
d3da3f40 2415
f1e4c916 2416 edid_block_status_print(status, block, i);
f934ec8c 2417
d3da3f40
JN		 2418 if (!edid_block_status_valid(status, edid_block_tag(block))) {
2419 if (status == EDID_BLOCK_READ_FAIL)
1c788f69 2420 goto fail;
ccc97def 2421 invalid_blocks++;
18e3c1d5
JN		 2422 } else if (i == 1) {
2423 /*
2424 * If the first EDID extension is a CTA extension, and
2425 * the first Data Block is HF-EEODB, override the
2426 * extension block count.
2427 *
2428 * Note: HF-EEODB could specify a smaller extension
2429 * count too, but we can't risk allocating a smaller
2430 * amount.
2431 */
2432 int eeodb = edid_hfeeodb_block_count(edid);
2433
2434 if (eeodb > num_blocks) {
2435 num_blocks = eeodb;
2436 alloc_size = edid_size_by_blocks(num_blocks);
2437 new = krealloc(edid, alloc_size, GFP_KERNEL);
2438 if (!new)
2439 goto fail;
2440 edid = new;
2441 }
d3da3f40 2442 }
0ea75e23
ST		 2443 }
2444
ccc97def 2445 if (invalid_blocks) {
18e3c1d5 2446 connector_bad_edid(connector, edid, num_blocks);
14544d09 2447
89f4b4c5 2448 edid = edid_filter_invalid_blocks(edid, &alloc_size);
61e57a8d
AJ		 2449 }
2450
1c788f69 2451ok:
6537f79a
JN		 2452 if (size)
2453 *size = alloc_size;
2454
e9a9e076 2455 return edid;
61e57a8d 2456
1c788f69 2457fail:
f14f3686 2458 kfree(edid);
61e57a8d
AJ		 2459 return NULL;
2460}
6537f79a
JN		 2461
2462/**
2463 * drm_do_get_edid - get EDID data using a custom EDID block read function
2464 * @connector: connector we're probing
2465 * @read_block: EDID block read function
2466 * @context: private data passed to the block read function
2467 *
2468 * When the I2C adapter connected to the DDC bus is hidden behind a device that
2469 * exposes a different interface to read EDID blocks this function can be used
2470 * to get EDID data using a custom block read function.
2471 *
2472 * As in the general case the DDC bus is accessible by the kernel at the I2C
2473 * level, drivers must make all reasonable efforts to expose it as an I2C
2474 * adapter and use drm_get_edid() instead of abusing this function.
2475 *
2476 * The EDID may be overridden using debugfs override_edid or firmware EDID
a05992d5 2477 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
6537f79a
JN		 2478 * order. Having either of them bypasses actual EDID reads.
2479 *
2480 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2481 */
2482struct edid *drm_do_get_edid(struct drm_connector *connector,
2483 read_block_fn read_block,
2484 void *context)
2485{
2486 return _drm_do_get_edid(connector, read_block, context, NULL);
2487}
18df89fe 2488EXPORT_SYMBOL_GPL(drm_do_get_edid);
61e57a8d 2489
3d1ab66e
JN		 2490/**
2491 * drm_edid_raw - Get a pointer to the raw EDID data.
2492 * @drm_edid: drm_edid container
2493 *
2494 * Get a pointer to the raw EDID data.
2495 *
2496 * This is for transition only. Avoid using this like the plague.
2497 *
2498 * Return: Pointer to raw EDID data.
2499 */
2500const struct edid *drm_edid_raw(const struct drm_edid *drm_edid)
2501{
2502 if (!drm_edid || !drm_edid->size)
2503 return NULL;
2504
2505 /*
2506 * Do not return pointers where relying on EDID extension count would
2507 * lead to buffer overflow.
2508 */
2509 if (WARN_ON(edid_size(drm_edid->edid) > drm_edid->size))
2510 return NULL;
2511
2512 return drm_edid->edid;
2513}
2514EXPORT_SYMBOL(drm_edid_raw);
2515
6537f79a
JN		 2516/* Allocate struct drm_edid container *without* duplicating the edid data */
2517static const struct drm_edid *_drm_edid_alloc(const void *edid, size_t size)
2518{
2519 struct drm_edid *drm_edid;
2520
2521 if (!edid || !size || size < EDID_LENGTH)
2522 return NULL;
2523
2524 drm_edid = kzalloc(sizeof(*drm_edid), GFP_KERNEL);
2525 if (drm_edid) {
2526 drm_edid->edid = edid;
2527 drm_edid->size = size;
2528 }
2529
2530 return drm_edid;
2531}
2532
2533/**
2534 * drm_edid_alloc - Allocate a new drm_edid container
2535 * @edid: Pointer to raw EDID data
2536 * @size: Size of memory allocated for EDID
2537 *
2538 * Allocate a new drm_edid container. Do not calculate edid size from edid, pass
2539 * the actual size that has been allocated for the data. There is no validation
2540 * of the raw EDID data against the size, but at least the EDID base block must
2541 * fit in the buffer.
2542 *
2543 * The returned pointer must be freed using drm_edid_free().
2544 *
2545 * Return: drm_edid container, or NULL on errors
2546 */
2547const struct drm_edid *drm_edid_alloc(const void *edid, size_t size)
2548{
2549 const struct drm_edid *drm_edid;
2550
2551 if (!edid || !size || size < EDID_LENGTH)
2552 return NULL;
2553
2554 edid = kmemdup(edid, size, GFP_KERNEL);
2555 if (!edid)
2556 return NULL;
2557
2558 drm_edid = _drm_edid_alloc(edid, size);
2559 if (!drm_edid)
2560 kfree(edid);
2561
2562 return drm_edid;
2563}
2564EXPORT_SYMBOL(drm_edid_alloc);
2565
2566/**
2567 * drm_edid_dup - Duplicate a drm_edid container
2568 * @drm_edid: EDID to duplicate
2569 *
2570 * The returned pointer must be freed using drm_edid_free().
2571 *
2572 * Returns: drm_edid container copy, or NULL on errors
2573 */
2574const struct drm_edid *drm_edid_dup(const struct drm_edid *drm_edid)
2575{
2576 if (!drm_edid)
2577 return NULL;
2578
2579 return drm_edid_alloc(drm_edid->edid, drm_edid->size);
2580}
2581EXPORT_SYMBOL(drm_edid_dup);
2582
2583/**
2584 * drm_edid_free - Free the drm_edid container
2585 * @drm_edid: EDID to free
2586 */
2587void drm_edid_free(const struct drm_edid *drm_edid)
2588{
2589 if (!drm_edid)
2590 return;
2591
2592 kfree(drm_edid->edid);
2593 kfree(drm_edid);
2594}
2595EXPORT_SYMBOL(drm_edid_free);
2596
61e57a8d 2597/**
db6cf833
TR		 2598 * drm_probe_ddc() - probe DDC presence
2599 * @adapter: I2C adapter to probe
fc66811c 2600 *
db6cf833 2601 * Return: True on success, false on failure.
61e57a8d 2602 */
fbff4690 2603bool
61e57a8d
AJ		 2604drm_probe_ddc(struct i2c_adapter *adapter)
2605{
2606 unsigned char out;
2607
2608 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
2609}
fbff4690 2610EXPORT_SYMBOL(drm_probe_ddc);
61e57a8d
AJ		 2611
2612/**
2613 * drm_get_edid - get EDID data, if available
2614 * @connector: connector we're probing
db6cf833 2615 * @adapter: I2C adapter to use for DDC
61e57a8d 2616 *
db6cf833 2617 * Poke the given I2C channel to grab EDID data if possible. If found,
61e57a8d
AJ		 2618 * attach it to the connector.
2619 *
db6cf833 2620 * Return: Pointer to valid EDID or NULL if we couldn't find any.
61e57a8d
AJ		 2621 */
2622struct edid *drm_get_edid(struct drm_connector *connector,
2623 struct i2c_adapter *adapter)
2624{
5186421c
SL		 2625 struct edid *edid;
2626
15f080f0
JN		 2627 if (connector->force == DRM_FORCE_OFF)
2628 return NULL;
2629
2630 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
18df89fe 2631 return NULL;
61e57a8d 2632
6537f79a 2633 edid = _drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter, NULL);
5186421c
SL		 2634 drm_connector_update_edid_property(connector, edid);
2635 return edid;
61e57a8d
AJ		 2636}
2637EXPORT_SYMBOL(drm_get_edid);
2638
6537f79a
JN		 2639/**
2640 * drm_edid_read_custom - Read EDID data using given EDID block read function
2641 * @connector: Connector to use
2642 * @read_block: EDID block read function
2643 * @context: Private data passed to the block read function
2644 *
2645 * When the I2C adapter connected to the DDC bus is hidden behind a device that
2646 * exposes a different interface to read EDID blocks this function can be used
2647 * to get EDID data using a custom block read function.
2648 *
2649 * As in the general case the DDC bus is accessible by the kernel at the I2C
2650 * level, drivers must make all reasonable efforts to expose it as an I2C
2651 * adapter and use drm_edid_read() or drm_edid_read_ddc() instead of abusing
2652 * this function.
2653 *
2654 * The EDID may be overridden using debugfs override_edid or firmware EDID
a05992d5 2655 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
6537f79a
JN		 2656 * order. Having either of them bypasses actual EDID reads.
2657 *
2658 * The returned pointer must be freed using drm_edid_free().
2659 *
2660 * Return: Pointer to EDID, or NULL if probe/read failed.
2661 */
2662const struct drm_edid *drm_edid_read_custom(struct drm_connector *connector,
2663 read_block_fn read_block,
2664 void *context)
2665{
2666 const struct drm_edid *drm_edid;
2667 struct edid *edid;
2668 size_t size = 0;
2669
2670 edid = _drm_do_get_edid(connector, read_block, context, &size);
2671 if (!edid)
2672 return NULL;
2673
2674 /* Sanity check for now */
2675 drm_WARN_ON(connector->dev, !size);
2676
2677 drm_edid = _drm_edid_alloc(edid, size);
2678 if (!drm_edid)
2679 kfree(edid);
2680
2681 return drm_edid;
2682}
2683EXPORT_SYMBOL(drm_edid_read_custom);
2684
2685/**
2686 * drm_edid_read_ddc - Read EDID data using given I2C adapter
2687 * @connector: Connector to use
2688 * @adapter: I2C adapter to use for DDC
2689 *
2690 * Read EDID using the given I2C adapter.
2691 *
2692 * The EDID may be overridden using debugfs override_edid or firmware EDID
a05992d5 2693 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
6537f79a
JN		 2694 * order. Having either of them bypasses actual EDID reads.
2695 *
2696 * Prefer initializing connector->ddc with drm_connector_init_with_ddc() and
2697 * using drm_edid_read() instead of this function.
2698 *
2699 * The returned pointer must be freed using drm_edid_free().
2700 *
2701 * Return: Pointer to EDID, or NULL if probe/read failed.
2702 */
2703const struct drm_edid *drm_edid_read_ddc(struct drm_connector *connector,
2704 struct i2c_adapter *adapter)
2705{
2706 const struct drm_edid *drm_edid;
2707
2708 if (connector->force == DRM_FORCE_OFF)
2709 return NULL;
2710
2711 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2712 return NULL;
2713
2714 drm_edid = drm_edid_read_custom(connector, drm_do_probe_ddc_edid, adapter);
2715
2716 /* Note: Do *not* call connector updates here. */
2717
2718 return drm_edid;
2719}
2720EXPORT_SYMBOL(drm_edid_read_ddc);
2721
2722/**
2723 * drm_edid_read - Read EDID data using connector's I2C adapter
2724 * @connector: Connector to use
2725 *
2726 * Read EDID using the connector's I2C adapter.
2727 *
2728 * The EDID may be overridden using debugfs override_edid or firmware EDID
a05992d5 2729 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
6537f79a
JN		 2730 * order. Having either of them bypasses actual EDID reads.
2731 *
2732 * The returned pointer must be freed using drm_edid_free().
2733 *
2734 * Return: Pointer to EDID, or NULL if probe/read failed.
2735 */
2736const struct drm_edid *drm_edid_read(struct drm_connector *connector)
2737{
2738 if (drm_WARN_ON(connector->dev, !connector->ddc))
2739 return NULL;
2740
2741 return drm_edid_read_ddc(connector, connector->ddc);
2742}
2743EXPORT_SYMBOL(drm_edid_read);
2744
d9f91a10
DA		 2745static u32 edid_extract_panel_id(const struct edid *edid)
2746{
2747 /*
e8de4d55
DA		 2748 * We represent the ID as a 32-bit number so it can easily be compared
2749 * with "==".
d9f91a10
DA		 2750 *
2751 * NOTE that we deal with endianness differently for the top half
2752 * of this ID than for the bottom half. The bottom half (the product
2753 * id) gets decoded as little endian by the EDID_PRODUCT_ID because
2754 * that's how everyone seems to interpret it. The top half (the mfg_id)
2755 * gets stored as big endian because that makes
2756 * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier
2757 * to write (it's easier to extract the ASCII). It doesn't really
2758 * matter, though, as long as the number here is unique.
2759 */
2760 return (u32)edid->mfg_id[0] << 24 |
2761 (u32)edid->mfg_id[1] << 16 |
2762 (u32)EDID_PRODUCT_ID(edid);
2763}
2764
2765/**
2766 * drm_edid_get_panel_id - Get a panel's ID through DDC
2767 * @adapter: I2C adapter to use for DDC
2768 *
2769 * This function reads the first block of the EDID of a panel and (assuming
2770 * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value
2771 * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's
2772 * supposed to be different for each different modem of panel.
2773 *
2774 * This function is intended to be used during early probing on devices where
2775 * more than one panel might be present. Because of its intended use it must
2776 * assume that the EDID of the panel is correct, at least as far as the ID
2777 * is concerned (in other words, we don't process any overrides here).
2778 *
2779 * NOTE: it's expected that this function and drm_do_get_edid() will both
2780 * be read the EDID, but there is no caching between them. Since we're only
2781 * reading the first block, hopefully this extra overhead won't be too big.
2782 *
2783 * Return: A 32-bit ID that should be different for each make/model of panel.
2784 * See the functions drm_edid_encode_panel_id() and
2785 * drm_edid_decode_panel_id() for some details on the structure of this
2786 * ID.
2787 */
2788
2789u32 drm_edid_get_panel_id(struct i2c_adapter *adapter)
2790{
2deaf1c2
JN		 2791 enum edid_block_status status;
2792 void *base_block;
2793 u32 panel_id = 0;
d9f91a10
DA		 2794
2795 /*
2796 * There are no manufacturer IDs of 0, so if there is a problem reading
2797 * the EDID then we'll just return 0.
2798 */
2deaf1c2
JN		 2799
2800 base_block = kmalloc(EDID_LENGTH, GFP_KERNEL);
2801 if (!base_block)
d9f91a10
DA		 2802 return 0;
2803
2deaf1c2
JN		 2804 status = edid_block_read(base_block, 0, drm_do_probe_ddc_edid, adapter);
2805
2806 edid_block_status_print(status, base_block, 0);
2807
2808 if (edid_block_status_valid(status, edid_block_tag(base_block)))
2809 panel_id = edid_extract_panel_id(base_block);
69c7717c
DA		 2810 else
2811 edid_block_dump(KERN_NOTICE, base_block, 0);
2deaf1c2
JN		 2812
2813 kfree(base_block);
d9f91a10
DA		 2814
2815 return panel_id;
2816}
2817EXPORT_SYMBOL(drm_edid_get_panel_id);
2818
5cb8eaa2
LW		 2819/**
2820 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
2821 * @connector: connector we're probing
2822 * @adapter: I2C adapter to use for DDC
2823 *
2824 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
2825 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
2826 * switch DDC to the GPU which is retrieving EDID.
2827 *
2828 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2829 */
2830struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
2831 struct i2c_adapter *adapter)
2832{
36b73b05
TZ		 2833 struct drm_device *dev = connector->dev;
2834 struct pci_dev *pdev = to_pci_dev(dev->dev);
5cb8eaa2
LW		 2835 struct edid *edid;
2836
36b73b05
TZ		 2837 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev)))
2838 return NULL;
2839
5cb8eaa2
LW		 2840 vga_switcheroo_lock_ddc(pdev);
2841 edid = drm_get_edid(connector, adapter);
2842 vga_switcheroo_unlock_ddc(pdev);
2843
2844 return edid;
2845}
2846EXPORT_SYMBOL(drm_get_edid_switcheroo);
2847
51f8da59
JN		 2848/**
2849 * drm_edid_duplicate - duplicate an EDID and the extensions
2850 * @edid: EDID to duplicate
2851 *
db6cf833 2852 * Return: Pointer to duplicated EDID or NULL on allocation failure.
51f8da59
JN		 2853 */
2854struct edid *drm_edid_duplicate(const struct edid *edid)
2855{
f1e4c916 2856 return kmemdup(edid, edid_size(edid), GFP_KERNEL);
51f8da59
JN		 2857}
2858EXPORT_SYMBOL(drm_edid_duplicate);
2859
61e57a8d
AJ		 2860/*** EDID parsing ***/
2861
f453ba04
DA		 2862/**
2863 * edid_get_quirks - return quirk flags for a given EDID
e42192b4 2864 * @drm_edid: EDID to process
f453ba04
DA		 2865 *
2866 * This tells subsequent routines what fixes they need to apply.
2867 */
e42192b4 2868static u32 edid_get_quirks(const struct drm_edid *drm_edid)
f453ba04 2869{
e42192b4 2870 u32 panel_id = edid_extract_panel_id(drm_edid->edid);
23c4cfbd 2871 const struct edid_quirk *quirk;
f453ba04
DA		 2872 int i;
2873
2874 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
2875 quirk = &edid_quirk_list[i];
e8de4d55 2876 if (quirk->panel_id == panel_id)
f453ba04
DA		 2877 return quirk->quirks;
2878 }
2879
2880 return 0;
2881}
2882
2883#define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
339d202c 2884#define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
f453ba04 2885
17edb8e1
JN		 2886/*
2887 * Walk the mode list for connector, clearing the preferred status on existing
2888 * modes and setting it anew for the right mode ala quirks.
f453ba04
DA		 2889 */
2890static void edid_fixup_preferred(struct drm_connector *connector,
2891 u32 quirks)
2892{
2893 struct drm_display_mode *t, *cur_mode, *preferred_mode;
f890607b 2894 int target_refresh = 0;
339d202c 2895 int cur_vrefresh, preferred_vrefresh;
f453ba04
DA		 2896
2897 if (list_empty(&connector->probed_modes))
2898 return;
2899
2900 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
2901 target_refresh = 60;
2902 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
2903 target_refresh = 75;
2904
2905 preferred_mode = list_first_entry(&connector->probed_modes,
2906 struct drm_display_mode, head);
2907
2908 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
2909 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
2910
2911 if (cur_mode == preferred_mode)
2912 continue;
2913
2914 /* Largest mode is preferred */
2915 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
2916 preferred_mode = cur_mode;
2917
0425662f
VS		 2918 cur_vrefresh = drm_mode_vrefresh(cur_mode);
2919 preferred_vrefresh = drm_mode_vrefresh(preferred_mode);
f453ba04
DA		 2920 /* At a given size, try to get closest to target refresh */
2921 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
339d202c
AD		 2922 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
2923 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
f453ba04
DA		 2924 preferred_mode = cur_mode;
2925 }
2926 }
2927
2928 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
2929}
2930
f6e252ba
AJ		 2931static bool
2932mode_is_rb(const struct drm_display_mode *mode)
2933{
2934 return (mode->htotal - mode->hdisplay == 160) &&
2935 (mode->hsync_end - mode->hdisplay == 80) &&
2936 (mode->hsync_end - mode->hsync_start == 32) &&
2937 (mode->vsync_start - mode->vdisplay == 3);
2938}
2939
33c7531d
AJ		 2940/*
2941 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
2942 * @dev: Device to duplicate against
2943 * @hsize: Mode width
2944 * @vsize: Mode height
2945 * @fresh: Mode refresh rate
f6e252ba 2946 * @rb: Mode reduced-blanking-ness
33c7531d
AJ		 2947 *
2948 * Walk the DMT mode list looking for a match for the given parameters.
db6cf833
TR		 2949 *
2950 * Return: A newly allocated copy of the mode, or NULL if not found.
33c7531d 2951 */
1d42bbc8 2952struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
f6e252ba
AJ		 2953 int hsize, int vsize, int fresh,
2954 bool rb)
559ee21d 2955{
07a5e632 2956 int i;
559ee21d 2957
a6b21831 2958 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
b1f559ec 2959 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
948de842 2960
f8b46a05
AJ		 2961 if (hsize != ptr->hdisplay)
2962 continue;
2963 if (vsize != ptr->vdisplay)
2964 continue;
2965 if (fresh != drm_mode_vrefresh(ptr))
2966 continue;
f6e252ba
AJ		 2967 if (rb != mode_is_rb(ptr))
2968 continue;
f8b46a05
AJ		 2969
2970 return drm_mode_duplicate(dev, ptr);
559ee21d 2971 }
f8b46a05
AJ		 2972
2973 return NULL;
559ee21d 2974}
1d42bbc8 2975EXPORT_SYMBOL(drm_mode_find_dmt);
23425cae 2976
e379814b 2977static bool is_display_descriptor(const struct detailed_timing *descriptor, u8 type)
a7a131ac 2978{
e379814b
JN		 2979 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
2980 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.pad1) != 2);
2981 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.type) != 3);
2982
2983 return descriptor->pixel_clock == 0 &&
2984 descriptor->data.other_data.pad1 == 0 &&
2985 descriptor->data.other_data.type == type;
a7a131ac
VS		 2986}
2987
a9b1f15f 2988static bool is_detailed_timing_descriptor(const struct detailed_timing *descriptor)
f447dd1f 2989{
a9b1f15f
JN		 2990 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
2991
2992 return descriptor->pixel_clock != 0;
f447dd1f
VS		 2993}
2994
4194442d 2995typedef void detailed_cb(const struct detailed_timing *timing, void *closure);
d1ff6409 2996
4d76a221 2997static void
eed628f1 2998cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
4d76a221 2999{
7304b981 3000 int i, n;
4966b2a9 3001 u8 d = ext[0x02];
eed628f1 3002 const u8 *det_base = ext + d;
4d76a221 3003
7304b981
VS		 3004 if (d < 4 || d > 127)
3005 return;
3006
4966b2a9 3007 n = (127 - d) / 18;
4d76a221 3008 for (i = 0; i < n; i++)
eed628f1 3009 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
4d76a221
AJ		 3010}
3011
cbba98f8 3012static void
eed628f1 3013vtb_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
cbba98f8
AJ		 3014{
3015 unsigned int i, n = min((int)ext[0x02], 6);
eed628f1 3016 const u8 *det_base = ext + 5;
cbba98f8
AJ		 3017
3018 if (ext[0x01] != 1)
3019 return; /* unknown version */
3020
3021 for (i = 0; i < n; i++)
eed628f1 3022 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
cbba98f8
AJ		 3023}
3024
45aa2336
JN		 3025static void drm_for_each_detailed_block(const struct drm_edid *drm_edid,
3026 detailed_cb *cb, void *closure)
d1ff6409 3027{
ab1747cc
JN		 3028 struct drm_edid_iter edid_iter;
3029 const u8 *ext;
d1ff6409 3030 int i;
d1ff6409 3031
45aa2336 3032 if (!drm_edid)
d1ff6409
AJ		 3033 return;
3034
3035 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
45aa2336 3036 cb(&drm_edid->edid->detailed_timings[i], closure);
d1ff6409 3037
bbded689 3038 drm_edid_iter_begin(drm_edid, &edid_iter);
ab1747cc 3039 drm_edid_iter_for_each(ext, &edid_iter) {
4d76a221
AJ		 3040 switch (*ext) {
3041 case CEA_EXT:
3042 cea_for_each_detailed_block(ext, cb, closure);
3043 break;
cbba98f8
AJ		 3044 case VTB_EXT:
3045 vtb_for_each_detailed_block(ext, cb, closure);
3046 break;
4d76a221
AJ		 3047 default:
3048 break;
3049 }
3050 }
ab1747cc 3051 drm_edid_iter_end(&edid_iter);
d1ff6409
AJ		 3052}
3053
3054static void
4194442d 3055is_rb(const struct detailed_timing *descriptor, void *data)
d1ff6409 3056{
90fd588f 3057 bool *res = data;
a7a131ac 3058
90fd588f 3059 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
a7a131ac
VS		 3060 return;
3061
90fd588f
JN		 3062 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3063 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.cvt.flags) != 15);
3064
3065 if (descriptor->data.other_data.data.range.flags == DRM_EDID_CVT_SUPPORT_FLAG &&
afd4429e 3066 descriptor->data.other_data.data.range.formula.cvt.flags & DRM_EDID_CVT_FLAGS_REDUCED_BLANKING)
90fd588f 3067 *res = true;
d1ff6409
AJ		 3068}
3069
3070/* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
3071static bool
874d98ee 3072drm_monitor_supports_rb(const struct drm_edid *drm_edid)
d1ff6409 3073{
874d98ee 3074 if (drm_edid->edid->revision >= 4) {
b196a498 3075 bool ret = false;
948de842 3076
45aa2336 3077 drm_for_each_detailed_block(drm_edid, is_rb, &ret);
d1ff6409
AJ		 3078 return ret;
3079 }
3080
874d98ee 3081 return ((drm_edid->edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
d1ff6409
AJ		 3082}
3083
7a374350 3084static void
4194442d 3085find_gtf2(const struct detailed_timing *descriptor, void *data)
7a374350 3086{
4194442d 3087 const struct detailed_timing **res = data;
a7a131ac 3088
c8a4beba 3089 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
a7a131ac
VS		 3090 return;
3091
c8a4beba
JN		 3092 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3093
afd4429e 3094 if (descriptor->data.other_data.data.range.flags == DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG)
c8a4beba 3095 *res = descriptor;
7a374350
AJ		 3096}
3097
3098/* Secondary GTF curve kicks in above some break frequency */
3099static int
67d87fac 3100drm_gtf2_hbreak(const struct drm_edid *drm_edid)
7a374350 3101{
4194442d 3102 const struct detailed_timing *descriptor = NULL;
c8a4beba 3103
45aa2336 3104 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
948de842 3105
c8a4beba
JN		 3106 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12);
3107
3108 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.hfreq_start_khz * 2 : 0;
7a374350
AJ		 3109}
3110
3111static int
67d87fac 3112drm_gtf2_2c(const struct drm_edid *drm_edid)
7a374350 3113{
4194442d 3114 const struct detailed_timing *descriptor = NULL;
c8a4beba 3115
45aa2336 3116 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
c8a4beba
JN		 3117
3118 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.c) != 13);
948de842 3119
c8a4beba 3120 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.c : 0;
7a374350
AJ		 3121}
3122
3123static int
67d87fac 3124drm_gtf2_m(const struct drm_edid *drm_edid)
7a374350 3125{
4194442d 3126 const struct detailed_timing *descriptor = NULL;
948de842 3127
45aa2336 3128 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
c8a4beba
JN		 3129
3130 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.m) != 14);
3131
3132 return descriptor ? le16_to_cpu(descriptor->data.other_data.data.range.formula.gtf2.m) : 0;
7a374350
AJ		 3133}
3134
3135static int
67d87fac 3136drm_gtf2_k(const struct drm_edid *drm_edid)
7a374350 3137{
4194442d 3138 const struct detailed_timing *descriptor = NULL;
c8a4beba 3139
45aa2336 3140 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
948de842 3141
c8a4beba
JN		 3142 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.k) != 16);
3143
3144 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.k : 0;
7a374350
AJ		 3145}
3146
3147static int
67d87fac 3148drm_gtf2_2j(const struct drm_edid *drm_edid)
7a374350 3149{
4194442d 3150 const struct detailed_timing *descriptor = NULL;
c8a4beba 3151
45aa2336 3152 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
c8a4beba
JN		 3153
3154 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.j) != 17);
948de842 3155
c8a4beba 3156 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.j : 0;
7a374350
AJ		 3157}
3158
bf72b5ef
VS		 3159static void
3160get_timing_level(const struct detailed_timing *descriptor, void *data)
3161{
3162 int *res = data;
3163
3164 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3165 return;
3166
3167 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3168
3169 switch (descriptor->data.other_data.data.range.flags) {
3170 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG:
3171 *res = LEVEL_GTF;
3172 break;
3173 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG:
3174 *res = LEVEL_GTF2;
3175 break;
3176 case DRM_EDID_CVT_SUPPORT_FLAG:
3177 *res = LEVEL_CVT;
3178 break;
3179 default:
3180 break;
3181 }
3182}
3183
17edb8e1 3184/* Get standard timing level (CVT/GTF/DMT). */
67d87fac 3185static int standard_timing_level(const struct drm_edid *drm_edid)
7a374350 3186{
67d87fac
JN		 3187 const struct edid *edid = drm_edid->edid;
3188
bf72b5ef
VS		 3189 if (edid->revision >= 4) {
3190 /*
3191 * If the range descriptor doesn't
3192 * indicate otherwise default to CVT
3193 */
3194 int ret = LEVEL_CVT;
3195
3196 drm_for_each_detailed_block(drm_edid, get_timing_level, &ret);
3197
3198 return ret;
3199 } else if (edid->revision >= 3 && drm_gtf2_hbreak(drm_edid)) {
3200 return LEVEL_GTF2;
3201 } else if (edid->revision >= 2) {
3202 return LEVEL_GTF;
3203 } else {
3204 return LEVEL_DMT;
7a374350 3205 }
7a374350
AJ		 3206}
3207
23425cae
AJ		 3208/*
3209 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
3210 * monitors fill with ascii space (0x20) instead.
3211 */
3212static int
3213bad_std_timing(u8 a, u8 b)
3214{
3215 return (a == 0x00 && b == 0x00) ||
3216 (a == 0x01 && b == 0x01) ||
3217 (a == 0x20 && b == 0x20);
3218}
3219
58911c24
VS		 3220static int drm_mode_hsync(const struct drm_display_mode *mode)
3221{
3222 if (mode->htotal <= 0)
3223 return 0;
3224
3225 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal);
3226}
3227
86101bb7
VS		 3228static struct drm_display_mode *
3229drm_gtf2_mode(struct drm_device *dev,
3230 const struct drm_edid *drm_edid,
3231 int hsize, int vsize, int vrefresh_rate)
3232{
3233 struct drm_display_mode *mode;
3234
3235 /*
3236 * This is potentially wrong if there's ever a monitor with
3237 * more than one ranges section, each claiming a different
3238 * secondary GTF curve. Please don't do that.
3239 */
3240 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
3241 if (!mode)
3242 return NULL;
3243
3244 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(drm_edid)) {
3245 drm_mode_destroy(dev, mode);
3246 mode = drm_gtf_mode_complex(dev, hsize, vsize,
3247 vrefresh_rate, 0, 0,
3248 drm_gtf2_m(drm_edid),
3249 drm_gtf2_2c(drm_edid),
3250 drm_gtf2_k(drm_edid),
3251 drm_gtf2_2j(drm_edid));
3252 }
3253
3254 return mode;
3255}
3256
17edb8e1 3257/*
f453ba04 3258 * Take the standard timing params (in this case width, aspect, and refresh)
5c61259e 3259 * and convert them into a real mode using CVT/GTF/DMT.
f453ba04 3260 */
67d87fac
JN		 3261static struct drm_display_mode *drm_mode_std(struct drm_connector *connector,
3262 const struct drm_edid *drm_edid,
3263 const struct std_timing *t)
f453ba04 3264{
7ca6adb3
AJ		 3265 struct drm_device *dev = connector->dev;
3266 struct drm_display_mode *m, *mode = NULL;
5c61259e
ZY		 3267 int hsize, vsize;
3268 int vrefresh_rate;
0454beab
MD		 3269 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
3270 >> EDID_TIMING_ASPECT_SHIFT;
5c61259e
ZY		 3271 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
3272 >> EDID_TIMING_VFREQ_SHIFT;
67d87fac 3273 int timing_level = standard_timing_level(drm_edid);
5c61259e 3274
23425cae
AJ		 3275 if (bad_std_timing(t->hsize, t->vfreq_aspect))
3276 return NULL;
3277
5c61259e
ZY		 3278 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
3279 hsize = t->hsize * 8 + 248;
3280 /* vrefresh_rate = vfreq + 60 */
3281 vrefresh_rate = vfreq + 60;
3282 /* the vdisplay is calculated based on the aspect ratio */
f066a17d 3283 if (aspect_ratio == 0) {
67d87fac 3284 if (drm_edid->edid->revision < 3)
f066a17d
AJ		 3285 vsize = hsize;
3286 else
3287 vsize = (hsize * 10) / 16;
3288 } else if (aspect_ratio == 1)
f453ba04 3289 vsize = (hsize * 3) / 4;
0454beab 3290 else if (aspect_ratio == 2)
f453ba04
DA		 3291 vsize = (hsize * 4) / 5;
3292 else
3293 vsize = (hsize * 9) / 16;
a0910c8e
AJ		 3294
3295 /* HDTV hack, part 1 */
3296 if (vrefresh_rate == 60 &&
3297 ((hsize == 1360 && vsize == 765) ||
3298 (hsize == 1368 && vsize == 769))) {
3299 hsize = 1366;
3300 vsize = 768;
3301 }
3302
7ca6adb3
AJ		 3303 /*
3304 * If this connector already has a mode for this size and refresh
3305 * rate (because it came from detailed or CVT info), use that
3306 * instead. This way we don't have to guess at interlace or
3307 * reduced blanking.
3308 */
522032da 3309 list_for_each_entry(m, &connector->probed_modes, head)
7ca6adb3
AJ		 3310 if (m->hdisplay == hsize && m->vdisplay == vsize &&
3311 drm_mode_vrefresh(m) == vrefresh_rate)
3312 return NULL;
3313
a0910c8e
AJ		 3314 /* HDTV hack, part 2 */
3315 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
3316 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
d50ba256 3317 false);
a5ef6567
JM		 3318 if (!mode)
3319 return NULL;
559ee21d 3320 mode->hdisplay = 1366;
a4967de6
AJ		 3321 mode->hsync_start = mode->hsync_start - 1;
3322 mode->hsync_end = mode->hsync_end - 1;
559ee21d
ZY		 3323 return mode;
3324 }
a0910c8e 3325
559ee21d 3326 /* check whether it can be found in default mode table */
874d98ee 3327 if (drm_monitor_supports_rb(drm_edid)) {
f6e252ba
AJ		 3328 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
3329 true);
3330 if (mode)
3331 return mode;
3332 }
3333 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
559ee21d
ZY		 3334 if (mode)
3335 return mode;
3336
f6e252ba 3337 /* okay, generate it */
5c61259e
ZY		 3338 switch (timing_level) {
3339 case LEVEL_DMT:
5c61259e
ZY		 3340 break;
3341 case LEVEL_GTF:
3342 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
3343 break;
7a374350 3344 case LEVEL_GTF2:
86101bb7 3345 mode = drm_gtf2_mode(dev, drm_edid, hsize, vsize, vrefresh_rate);
7a374350 3346 break;
5c61259e 3347 case LEVEL_CVT:
d50ba256
DA		 3348 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
3349 false);
5c61259e
ZY		 3350 break;
3351 }
f453ba04
DA		 3352 return mode;
3353}
3354
b58db2c6
AJ		 3355/*
3356 * EDID is delightfully ambiguous about how interlaced modes are to be
3357 * encoded. Our internal representation is of frame height, but some
3358 * HDTV detailed timings are encoded as field height.
3359 *
3360 * The format list here is from CEA, in frame size. Technically we
3361 * should be checking refresh rate too. Whatever.
3362 */
3363static void
3364drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
fcfb2ea1 3365 const struct detailed_pixel_timing *pt)
b58db2c6
AJ		 3366{
3367 int i;
3368 static const struct {
3369 int w, h;
3370 } cea_interlaced[] = {
3371 { 1920, 1080 },
3372 { 720, 480 },
3373 { 1440, 480 },
3374 { 2880, 480 },
3375 { 720, 576 },
3376 { 1440, 576 },
3377 { 2880, 576 },
3378 };
b58db2c6
AJ		 3379
3380 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
3381 return;
3382
3c581411 3383 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
b58db2c6
AJ		 3384 if ((mode->hdisplay == cea_interlaced[i].w) &&
3385 (mode->vdisplay == cea_interlaced[i].h / 2)) {
3386 mode->vdisplay *= 2;
3387 mode->vsync_start *= 2;
3388 mode->vsync_end *= 2;
3389 mode->vtotal *= 2;
3390 mode->vtotal |= 1;
3391 }
3392 }
3393
3394 mode->flags |= DRM_MODE_FLAG_INTERLACE;
3395}
3396
17edb8e1
JN		 3397/*
3398 * Create a new mode from an EDID detailed timing section. An EDID detailed
3399 * timing block contains enough info for us to create and return a new struct
3400 * drm_display_mode.
f453ba04 3401 */
e1e7bc48 3402static struct drm_display_mode *drm_mode_detailed(struct drm_connector *connector,
f0d080ff 3403 const struct drm_edid *drm_edid,
fcfb2ea1 3404 const struct detailed_timing *timing,
f453ba04
DA		 3405 u32 quirks)
3406{
e1e7bc48 3407 struct drm_device *dev = connector->dev;
f453ba04 3408 struct drm_display_mode *mode;
fcfb2ea1 3409 const struct detailed_pixel_timing *pt = &timing->data.pixel_data;
0454beab
MD		 3410 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
3411 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
3412 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
3413 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
e14cbee4
MD		 3414 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
3415 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
16dad1d7 3416 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
e14cbee4 3417 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
f453ba04 3418
fc438966 3419 /* ignore tiny modes */
0454beab 3420 if (hactive < 64 || vactive < 64)
fc438966
AJ		 3421 return NULL;
3422
0454beab 3423 if (pt->misc & DRM_EDID_PT_STEREO) {
e1e7bc48
JN		 3424 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Stereo mode not supported\n",
3425 connector->base.id, connector->name);
f453ba04
DA		 3426 return NULL;
3427 }
0454beab 3428 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
e1e7bc48
JN		 3429 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Composite sync not supported\n",
3430 connector->base.id, connector->name);
f453ba04
DA		 3431 }
3432
fcb45611
ZY		 3433 /* it is incorrect if hsync/vsync width is zero */
3434 if (!hsync_pulse_width || !vsync_pulse_width) {
e1e7bc48
JN		 3435 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Incorrect Detailed timing. Wrong Hsync/Vsync pulse width\n",
3436 connector->base.id, connector->name);
fcb45611
ZY		 3437 return NULL;
3438 }
bc42aabc
AJ		 3439
3440 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
3441 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
3442 if (!mode)
3443 return NULL;
3444
3445 goto set_size;
3446 }
3447
f453ba04
DA		 3448 mode = drm_mode_create(dev);
3449 if (!mode)
3450 return NULL;
3451
f453ba04 3452 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
faacff8e
JN		 3453 mode->clock = 1088 * 10;
3454 else
3455 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
0454beab
MD		 3456
3457 mode->hdisplay = hactive;
3458 mode->hsync_start = mode->hdisplay + hsync_offset;
3459 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
3460 mode->htotal = mode->hdisplay + hblank;
3461
3462 mode->vdisplay = vactive;
3463 mode->vsync_start = mode->vdisplay + vsync_offset;
3464 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
3465 mode->vtotal = mode->vdisplay + vblank;
f453ba04 3466
7064fef5
JB		 3467 /* Some EDIDs have bogus h/vtotal values */
3468 if (mode->hsync_end > mode->htotal)
3469 mode->htotal = mode->hsync_end + 1;
3470 if (mode->vsync_end > mode->vtotal)
3471 mode->vtotal = mode->vsync_end + 1;
3472
b58db2c6 3473 drm_mode_do_interlace_quirk(mode, pt);
f453ba04
DA		 3474
3475 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
faacff8e
JN		 3476 mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC;
3477 } else {
3478 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
3479 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
3480 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
3481 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
f453ba04
DA		 3482 }
3483
bc42aabc 3484set_size:
e14cbee4
MD		 3485 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
3486 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
f453ba04
DA		 3487
3488 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
3489 mode->width_mm *= 10;
3490 mode->height_mm *= 10;
3491 }
3492
3493 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
f0d080ff
JN		 3494 mode->width_mm = drm_edid->edid->width_cm * 10;
3495 mode->height_mm = drm_edid->edid->height_cm * 10;
f453ba04
DA		 3496 }
3497
bc42aabc
AJ		 3498 mode->type = DRM_MODE_TYPE_DRIVER;
3499 drm_mode_set_name(mode);
3500
f453ba04
DA		 3501 return mode;
3502}
3503
b17e52ef 3504static bool
b1f559ec 3505mode_in_hsync_range(const struct drm_display_mode *mode,
c14e7241 3506 const struct edid *edid, const u8 *t)
b17e52ef
AJ		 3507{
3508 int hsync, hmin, hmax;
3509
3510 hmin = t[7];
3511 if (edid->revision >= 4)
3512 hmin += ((t[4] & 0x04) ? 255 : 0);
3513 hmax = t[8];
3514 if (edid->revision >= 4)
3515 hmax += ((t[4] & 0x08) ? 255 : 0);
07a5e632 3516 hsync = drm_mode_hsync(mode);
07a5e632 3517
b17e52ef
AJ		 3518 return (hsync <= hmax && hsync >= hmin);
3519}
3520
3521static bool
b1f559ec 3522mode_in_vsync_range(const struct drm_display_mode *mode,
c14e7241 3523 const struct edid *edid, const u8 *t)
b17e52ef
AJ		 3524{
3525 int vsync, vmin, vmax;
3526
3527 vmin = t[5];
3528 if (edid->revision >= 4)
3529 vmin += ((t[4] & 0x01) ? 255 : 0);
3530 vmax = t[6];
3531 if (edid->revision >= 4)
3532 vmax += ((t[4] & 0x02) ? 255 : 0);
3533 vsync = drm_mode_vrefresh(mode);
3534
3535 return (vsync <= vmax && vsync >= vmin);
3536}
3537
3538static u32
c14e7241 3539range_pixel_clock(const struct edid *edid, const u8 *t)
b17e52ef
AJ		 3540{
3541 /* unspecified */
3542 if (t[9] == 0 || t[9] == 255)
3543 return 0;
3544
3545 /* 1.4 with CVT support gives us real precision, yay */
afd4429e 3546 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG)
b17e52ef
AJ		 3547 return (t[9] * 10000) - ((t[12] >> 2) * 250);
3548
3549 /* 1.3 is pathetic, so fuzz up a bit */
3550 return t[9] * 10000 + 5001;
3551}
3552
874d98ee
JN		 3553static bool mode_in_range(const struct drm_display_mode *mode,
3554 const struct drm_edid *drm_edid,
3555 const struct detailed_timing *timing)
b17e52ef 3556{
874d98ee 3557 const struct edid *edid = drm_edid->edid;
b17e52ef 3558 u32 max_clock;
fcfb2ea1 3559 const u8 *t = (const u8 *)timing;
b17e52ef
AJ		 3560
3561 if (!mode_in_hsync_range(mode, edid, t))
07a5e632
AJ		 3562 return false;
3563
b17e52ef 3564 if (!mode_in_vsync_range(mode, edid, t))
07a5e632
AJ		 3565 return false;
3566
b17e52ef 3567 if ((max_clock = range_pixel_clock(edid, t)))
07a5e632
AJ		 3568 if (mode->clock > max_clock)
3569 return false;
b17e52ef
AJ		 3570
3571 /* 1.4 max horizontal check */
afd4429e 3572 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG)
b17e52ef
AJ		 3573 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
3574 return false;
3575
874d98ee 3576 if (mode_is_rb(mode) && !drm_monitor_supports_rb(drm_edid))
b17e52ef 3577 return false;
07a5e632
AJ		 3578
3579 return true;
3580}
3581
7b668ebe
TI		 3582static bool valid_inferred_mode(const struct drm_connector *connector,
3583 const struct drm_display_mode *mode)
3584{
85f8fcd6 3585 const struct drm_display_mode *m;
7b668ebe
TI		 3586 bool ok = false;
3587
3588 list_for_each_entry(m, &connector->probed_modes, head) {
3589 if (mode->hdisplay == m->hdisplay &&
3590 mode->vdisplay == m->vdisplay &&
3591 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
3592 return false; /* duplicated */
3593 if (mode->hdisplay <= m->hdisplay &&
3594 mode->vdisplay <= m->vdisplay)
3595 ok = true;
3596 }
3597 return ok;
3598}
3599
084c7a7c
JN		 3600static int drm_dmt_modes_for_range(struct drm_connector *connector,
3601 const struct drm_edid *drm_edid,
3602 const struct detailed_timing *timing)
07a5e632
AJ		 3603{
3604 int i, modes = 0;
3605 struct drm_display_mode *newmode;
3606 struct drm_device *dev = connector->dev;
3607
a6b21831 3608 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
874d98ee 3609 if (mode_in_range(drm_dmt_modes + i, drm_edid, timing) &&
7b668ebe 3610 valid_inferred_mode(connector, drm_dmt_modes + i)) {
07a5e632
AJ		 3611 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
3612 if (newmode) {
3613 drm_mode_probed_add(connector, newmode);
3614 modes++;
3615 }
3616 }
3617 }
3618
3619 return modes;
3620}
3621
c09dedb7
TI		 3622/* fix up 1366x768 mode from 1368x768;
3623 * GFT/CVT can't express 1366 width which isn't dividable by 8
3624 */
969218fe 3625void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
c09dedb7
TI		 3626{
3627 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
3628 mode->hdisplay = 1366;
3629 mode->hsync_start--;
3630 mode->hsync_end--;
3631 drm_mode_set_name(mode);
3632 }
3633}
3634
a77f7c89
JN		 3635static int drm_gtf_modes_for_range(struct drm_connector *connector,
3636 const struct drm_edid *drm_edid,
3637 const struct detailed_timing *timing)
b309bd37
AJ		 3638{
3639 int i, modes = 0;
3640 struct drm_display_mode *newmode;
3641 struct drm_device *dev = connector->dev;
3642
a6b21831 3643 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
b309bd37 3644 const struct minimode *m = &extra_modes[i];
948de842 3645
b309bd37 3646 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
fc48f169
TI		 3647 if (!newmode)
3648 return modes;
b309bd37 3649
969218fe 3650 drm_mode_fixup_1366x768(newmode);
874d98ee 3651 if (!mode_in_range(newmode, drm_edid, timing) ||
7b668ebe 3652 !valid_inferred_mode(connector, newmode)) {
b309bd37
AJ		 3653 drm_mode_destroy(dev, newmode);
3654 continue;
3655 }
3656
3657 drm_mode_probed_add(connector, newmode);
3658 modes++;
3659 }
3660
3661 return modes;
3662}
3663
9ed15f91
VS		 3664static int drm_gtf2_modes_for_range(struct drm_connector *connector,
3665 const struct drm_edid *drm_edid,
3666 const struct detailed_timing *timing)
3667{
3668 int i, modes = 0;
3669 struct drm_display_mode *newmode;
3670 struct drm_device *dev = connector->dev;
3671
3672 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3673 const struct minimode *m = &extra_modes[i];
3674
3675 newmode = drm_gtf2_mode(dev, drm_edid, m->w, m->h, m->r);
3676 if (!newmode)
3677 return modes;
3678
3679 drm_mode_fixup_1366x768(newmode);
3680 if (!mode_in_range(newmode, drm_edid, timing) ||
3681 !valid_inferred_mode(connector, newmode)) {
3682 drm_mode_destroy(dev, newmode);
3683 continue;
3684 }
3685
3686 drm_mode_probed_add(connector, newmode);
3687 modes++;
3688 }
3689
3690 return modes;
3691}
3692
7428bfbd
JN		 3693static int drm_cvt_modes_for_range(struct drm_connector *connector,
3694 const struct drm_edid *drm_edid,
3695 const struct detailed_timing *timing)
b309bd37
AJ		 3696{
3697 int i, modes = 0;
3698 struct drm_display_mode *newmode;
3699 struct drm_device *dev = connector->dev;
874d98ee 3700 bool rb = drm_monitor_supports_rb(drm_edid);
b309bd37 3701
a6b21831 3702 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
b309bd37 3703 const struct minimode *m = &extra_modes[i];
948de842 3704
b309bd37 3705 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
fc48f169
TI		 3706 if (!newmode)
3707 return modes;
b309bd37 3708
969218fe 3709 drm_mode_fixup_1366x768(newmode);
874d98ee 3710 if (!mode_in_range(newmode, drm_edid, timing) ||
7b668ebe 3711 !valid_inferred_mode(connector, newmode)) {
b309bd37
AJ		 3712 drm_mode_destroy(dev, newmode);
3713 continue;
3714 }
3715
3716 drm_mode_probed_add(connector, newmode);
3717 modes++;
3718 }
3719
3720 return modes;
3721}
3722
13931579 3723static void
4194442d 3724do_inferred_modes(const struct detailed_timing *timing, void *c)
9340d8cf 3725{
13931579 3726 struct detailed_mode_closure *closure = c;
fcfb2ea1
JN		 3727 const struct detailed_non_pixel *data = &timing->data.other_data;
3728 const struct detailed_data_monitor_range *range = &data->data.range;
9340d8cf 3729
e379814b 3730 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
cb21aafe
AJ		 3731 return;
3732
3733 closure->modes += drm_dmt_modes_for_range(closure->connector,
084c7a7c 3734 closure->drm_edid,
cb21aafe 3735 timing);
4d23f484 3736
dd3abfe4 3737 if (closure->drm_edid->edid->revision < 2)
b309bd37
AJ		 3738 return; /* GTF not defined yet */
3739
3740 switch (range->flags) {
9ed15f91
VS		 3741 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG:
3742 closure->modes += drm_gtf2_modes_for_range(closure->connector,
3743 closure->drm_edid,
3744 timing);
3745 break;
afd4429e 3746 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG:
b309bd37 3747 closure->modes += drm_gtf_modes_for_range(closure->connector,
a77f7c89 3748 closure->drm_edid,
b309bd37
AJ		 3749 timing);
3750 break;
afd4429e 3751 case DRM_EDID_CVT_SUPPORT_FLAG:
dd3abfe4 3752 if (closure->drm_edid->edid->revision < 4)
b309bd37
AJ		 3753 break;
3754
3755 closure->modes += drm_cvt_modes_for_range(closure->connector,
7428bfbd 3756 closure->drm_edid,
b309bd37
AJ		 3757 timing);
3758 break;
afd4429e 3759 case DRM_EDID_RANGE_LIMITS_ONLY_FLAG:
b309bd37
AJ		 3760 default:
3761 break;
3762 }
13931579 3763}
69da3015 3764
40f71f5b
JN		 3765static int add_inferred_modes(struct drm_connector *connector,
3766 const struct drm_edid *drm_edid)
13931579
AJ		 3767{
3768 struct detailed_mode_closure closure = {
d456ea2e 3769 .connector = connector,
dd0f4470 3770 .drm_edid = drm_edid,
13931579 3771 };
9340d8cf 3772
dd3abfe4 3773 if (drm_edid->edid->revision >= 1)
45aa2336 3774 drm_for_each_detailed_block(drm_edid, do_inferred_modes, &closure);
9340d8cf 3775
13931579 3776 return closure.modes;
9340d8cf
AJ		 3777}
3778
2255be14 3779static int
fcfb2ea1 3780drm_est3_modes(struct drm_connector *connector, const struct detailed_timing *timing)
2255be14
AJ		 3781{
3782 int i, j, m, modes = 0;
3783 struct drm_display_mode *mode;
fcfb2ea1 3784 const u8 *est = ((const u8 *)timing) + 6;
2255be14
AJ		 3785
3786 for (i = 0; i < 6; i++) {
891a7469 3787 for (j = 7; j >= 0; j--) {
2255be14 3788 m = (i * 8) + (7 - j);
3c581411 3789 if (m >= ARRAY_SIZE(est3_modes))
2255be14
AJ		 3790 break;
3791 if (est[i] & (1 << j)) {
1d42bbc8
DA		 3792 mode = drm_mode_find_dmt(connector->dev,
3793 est3_modes[m].w,
3794 est3_modes[m].h,
f6e252ba
AJ		 3795 est3_modes[m].r,
3796 est3_modes[m].rb);
2255be14
AJ		 3797 if (mode) {
3798 drm_mode_probed_add(connector, mode);
3799 modes++;
3800 }
3801 }
3802 }
3803 }
3804
3805 return modes;
3806}
3807
13931579 3808static void
4194442d 3809do_established_modes(const struct detailed_timing *timing, void *c)
9cf00977 3810{
13931579 3811 struct detailed_mode_closure *closure = c;
9cf00977 3812
e379814b 3813 if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS))
a7a131ac
VS		 3814 return;
3815
3816 closure->modes += drm_est3_modes(closure->connector, timing);
13931579 3817}
9cf00977 3818
17edb8e1
JN		 3819/*
3820 * Get established modes from EDID and add them. Each EDID block contains a
3821 * bitmap of the supported "established modes" list (defined above). Tease them
3822 * out and add them to the global modes list.
13931579 3823 */
40f71f5b
JN		 3824static int add_established_modes(struct drm_connector *connector,
3825 const struct drm_edid *drm_edid)
13931579
AJ		 3826{
3827 struct drm_device *dev = connector->dev;
40f71f5b 3828 const struct edid *edid = drm_edid->edid;
13931579
AJ		 3829 unsigned long est_bits = edid->established_timings.t1 |
3830 (edid->established_timings.t2 << 8) |
3831 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
3832 int i, modes = 0;
3833 struct detailed_mode_closure closure = {
d456ea2e 3834 .connector = connector,
dd0f4470 3835 .drm_edid = drm_edid,
13931579 3836 };
9cf00977 3837
13931579
AJ		 3838 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
3839 if (est_bits & (1<<i)) {
3840 struct drm_display_mode *newmode;
948de842 3841
13931579
AJ		 3842 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
3843 if (newmode) {
3844 drm_mode_probed_add(connector, newmode);
3845 modes++;
3846 }
3847 }
9cf00977
AJ		 3848 }
3849
dd3abfe4 3850 if (edid->revision >= 1)
45aa2336 3851 drm_for_each_detailed_block(drm_edid, do_established_modes,
eed628f1 3852 &closure);
13931579
AJ		 3853
3854 return modes + closure.modes;
3855}
3856
3857static void
4194442d 3858do_standard_modes(const struct detailed_timing *timing, void *c)
13931579
AJ		 3859{
3860 struct detailed_mode_closure *closure = c;
fcfb2ea1 3861 const struct detailed_non_pixel *data = &timing->data.other_data;
13931579 3862 struct drm_connector *connector = closure->connector;
a7a131ac 3863 int i;
13931579 3864
e379814b 3865 if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES))
a7a131ac 3866 return;
9cf00977 3867
a7a131ac 3868 for (i = 0; i < 6; i++) {
fcfb2ea1 3869 const struct std_timing *std = &data->data.timings[i];
a7a131ac
VS		 3870 struct drm_display_mode *newmode;
3871
67d87fac 3872 newmode = drm_mode_std(connector, closure->drm_edid, std);
a7a131ac
VS		 3873 if (newmode) {
3874 drm_mode_probed_add(connector, newmode);
3875 closure->modes++;
9cf00977 3876 }
9cf00977 3877 }
9cf00977
AJ		 3878}
3879
17edb8e1
JN		 3880/*
3881 * Get standard modes from EDID and add them. Standard modes can be calculated
3882 * using the appropriate standard (DMT, GTF, or CVT). Grab them from EDID and
3883 * add them to the list.
f453ba04 3884 */
40f71f5b
JN		 3885static int add_standard_modes(struct drm_connector *connector,
3886 const struct drm_edid *drm_edid)
f453ba04 3887{
9cf00977 3888 int i, modes = 0;
13931579 3889 struct detailed_mode_closure closure = {
d456ea2e 3890 .connector = connector,
dd0f4470 3891 .drm_edid = drm_edid,
13931579
AJ		 3892 };
3893
3894 for (i = 0; i < EDID_STD_TIMINGS; i++) {
3895 struct drm_display_mode *newmode;
3896
67d87fac 3897 newmode = drm_mode_std(connector, drm_edid,
40f71f5b 3898 &drm_edid->edid->standard_timings[i]);
13931579
AJ		 3899 if (newmode) {
3900 drm_mode_probed_add(connector, newmode);
3901 modes++;
3902 }
3903 }
3904
dd3abfe4 3905 if (drm_edid->edid->revision >= 1)
45aa2336 3906 drm_for_each_detailed_block(drm_edid, do_standard_modes,
13931579
AJ		 3907 &closure);
3908
3909 /* XXX should also look for standard codes in VTB blocks */
3910
3911 return modes + closure.modes;
3912}
f453ba04 3913
13931579 3914static int drm_cvt_modes(struct drm_connector *connector,
fcfb2ea1 3915 const struct detailed_timing *timing)
13931579
AJ		 3916{
3917 int i, j, modes = 0;
3918 struct drm_display_mode *newmode;
3919 struct drm_device *dev = connector->dev;
fcfb2ea1 3920 const struct cvt_timing *cvt;
13931579
AJ		 3921 const int rates[] = { 60, 85, 75, 60, 50 };
3922 const u8 empty[3] = { 0, 0, 0 };
a327f6b8 3923
13931579 3924 for (i = 0; i < 4; i++) {
3f649ab7 3925 int width, height;
948de842 3926
13931579 3927 cvt = &(timing->data.other_data.data.cvt[i]);
f453ba04 3928
13931579 3929 if (!memcmp(cvt->code, empty, 3))
9cf00977 3930 continue;
f453ba04 3931
13931579
AJ		 3932 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
3933 switch (cvt->code[1] & 0x0c) {
d652d5f1
LT		 3934 /* default - because compiler doesn't see that we've enumerated all cases */
3935 default:
13931579
AJ		 3936 case 0x00:
3937 width = height * 4 / 3;
3938 break;
3939 case 0x04:
3940 width = height * 16 / 9;
3941 break;
3942 case 0x08:
3943 width = height * 16 / 10;
3944 break;
3945 case 0x0c:
3946 width = height * 15 / 9;
3947 break;
3948 }
3949
3950 for (j = 1; j < 5; j++) {
3951 if (cvt->code[2] & (1 << j)) {
3952 newmode = drm_cvt_mode(dev, width, height,
3953 rates[j], j == 0,
3954 false, false);
3955 if (newmode) {
3956 drm_mode_probed_add(connector, newmode);
3957 modes++;
3958 }
3959 }
3960 }
f453ba04
DA		 3961 }
3962
3963 return modes;
3964}
9cf00977 3965
13931579 3966static void
4194442d 3967do_cvt_mode(const struct detailed_timing *timing, void *c)
882f0219 3968{
13931579 3969 struct detailed_mode_closure *closure = c;
882f0219 3970
e379814b 3971 if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE))
a7a131ac
VS		 3972 return;
3973
3974 closure->modes += drm_cvt_modes(closure->connector, timing);
13931579 3975}
882f0219 3976
13931579 3977static int
40f71f5b 3978add_cvt_modes(struct drm_connector *connector, const struct drm_edid *drm_edid)
4d23f484 3979{
13931579 3980 struct detailed_mode_closure closure = {
d456ea2e 3981 .connector = connector,
dd0f4470 3982 .drm_edid = drm_edid,
13931579 3983 };
882f0219 3984
dd3abfe4 3985 if (drm_edid->edid->revision >= 3)
45aa2336 3986 drm_for_each_detailed_block(drm_edid, do_cvt_mode, &closure);
882f0219 3987
13931579 3988 /* XXX should also look for CVT codes in VTB blocks */
882f0219 3989
13931579
AJ		 3990 return closure.modes;
3991}
3992
e1e7bc48
JN		 3993static void fixup_detailed_cea_mode_clock(struct drm_connector *connector,
3994 struct drm_display_mode *mode);
fa3a7340 3995
13931579 3996static void
4194442d 3997do_detailed_mode(const struct detailed_timing *timing, void *c)
13931579
AJ		 3998{
3999 struct detailed_mode_closure *closure = c;
4000 struct drm_display_mode *newmode;
4001
a9b1f15f 4002 if (!is_detailed_timing_descriptor(timing))
f447dd1f
VS		 4003 return;
4004
e1e7bc48 4005 newmode = drm_mode_detailed(closure->connector,
f0d080ff 4006 closure->drm_edid, timing,
f447dd1f
VS		 4007 closure->quirks);
4008 if (!newmode)
4009 return;
13931579 4010
f447dd1f
VS		 4011 if (closure->preferred)
4012 newmode->type |= DRM_MODE_TYPE_PREFERRED;
13931579 4013
f447dd1f
VS		 4014 /*
4015 * Detailed modes are limited to 10kHz pixel clock resolution,
4016 * so fix up anything that looks like CEA/HDMI mode, but the clock
4017 * is just slightly off.
4018 */
e1e7bc48 4019 fixup_detailed_cea_mode_clock(closure->connector, newmode);
fa3a7340 4020
f447dd1f
VS		 4021 drm_mode_probed_add(closure->connector, newmode);
4022 closure->modes++;
4023 closure->preferred = false;
13931579 4024}
882f0219 4025
13931579
AJ		 4026/*
4027 * add_detailed_modes - Add modes from detailed timings
4028 * @connector: attached connector
40f71f5b 4029 * @drm_edid: EDID block to scan
13931579
AJ		 4030 * @quirks: quirks to apply
4031 */
40f71f5b
JN		 4032static int add_detailed_modes(struct drm_connector *connector,
4033 const struct drm_edid *drm_edid, u32 quirks)
13931579
AJ		 4034{
4035 struct detailed_mode_closure closure = {
d456ea2e 4036 .connector = connector,
dd0f4470 4037 .drm_edid = drm_edid,
d456ea2e 4038 .quirks = quirks,
13931579
AJ		 4039 };
4040
dd3abfe4 4041 if (drm_edid->edid->revision >= 4)
f72f9529
VS		 4042 closure.preferred = true; /* first detailed timing is always preferred */
4043 else
13931579 4044 closure.preferred =
f72f9529 4045 drm_edid->edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING;
13931579 4046
45aa2336 4047 drm_for_each_detailed_block(drm_edid, do_detailed_mode, &closure);
13931579
AJ		 4048
4049 return closure.modes;
882f0219 4050}
f453ba04 4051
9d72b7e2
JN		 4052/* CTA-861-H Table 60 - CTA Tag Codes */
4053#define CTA_DB_AUDIO 1
4054#define CTA_DB_VIDEO 2
4055#define CTA_DB_VENDOR 3
4056#define CTA_DB_SPEAKER 4
4057#define CTA_DB_EXTENDED_TAG 7
4058
4059/* CTA-861-H Table 62 - CTA Extended Tag Codes */
4060#define CTA_EXT_DB_VIDEO_CAP 0
4061#define CTA_EXT_DB_VENDOR 1
4062#define CTA_EXT_DB_HDR_STATIC_METADATA 6
4063#define CTA_EXT_DB_420_VIDEO_DATA 14
4064#define CTA_EXT_DB_420_VIDEO_CAP_MAP 15
18e3c1d5 4065#define CTA_EXT_DB_HF_EEODB 0x78
9d72b7e2
JN		 4066#define CTA_EXT_DB_HF_SCDB 0x79
4067
8fe9790d 4068#define EDID_BASIC_AUDIO (1 << 6)
a988bc72
LPC		 4069#define EDID_CEA_YCRCB444 (1 << 5)
4070#define EDID_CEA_YCRCB422 (1 << 4)
b1edd6a6 4071#define EDID_CEA_VCDB_QS (1 << 6)
8fe9790d 4072
d4e4a31d 4073/*
8fe9790d 4074 * Search EDID for CEA extension block.
d9ba1b4c
JN		 4075 *
4076 * FIXME: Prefer not returning pointers to raw EDID data.
f23c20c8 4077 */
d9ba1b4c 4078const u8 *drm_find_edid_extension(const struct drm_edid *drm_edid,
4cc4f09e 4079 int ext_id, int *ext_index)
f23c20c8 4080{
43d16d84 4081 const u8 *edid_ext = NULL;
8fe9790d 4082 int i;
f23c20c8
ML		 4083
4084 /* No EDID or EDID extensions */
d9307f27 4085 if (!drm_edid || !drm_edid_extension_block_count(drm_edid))
8fe9790d 4086 return NULL;
f23c20c8 4087
f23c20c8 4088 /* Find CEA extension */
d9307f27
JN		 4089 for (i = *ext_index; i < drm_edid_extension_block_count(drm_edid); i++) {
4090 edid_ext = drm_edid_extension_block_data(drm_edid, i);
4ba0f53c 4091 if (edid_block_tag(edid_ext) == ext_id)
f23c20c8
ML		 4092 break;
4093 }
4094
d9307f27 4095 if (i >= drm_edid_extension_block_count(drm_edid))
8fe9790d
ZW		 4096 return NULL;
4097
8873cfa3
VS		 4098 *ext_index = i + 1;
4099
8fe9790d
ZW		 4100 return edid_ext;
4101}
4102
6ff1c19f 4103/* Return true if the EDID has a CTA extension or a DisplayID CTA data block */
40f71f5b 4104static bool drm_edid_has_cta_extension(const struct drm_edid *drm_edid)
e28ad544 4105{
43d16d84 4106 const struct displayid_block *block;
1ba63caf 4107 struct displayid_iter iter;
1ba63caf 4108 int ext_index = 0;
6ff1c19f 4109 bool found = false;
e28ad544
AR		 4110
4111 /* Look for a top level CEA extension block */
d9ba1b4c 4112 if (drm_find_edid_extension(drm_edid, CEA_EXT, &ext_index))
6ff1c19f 4113 return true;
e28ad544
AR		 4114
4115 /* CEA blocks can also be found embedded in a DisplayID block */
d9ba1b4c 4116 displayid_iter_edid_begin(drm_edid, &iter);
1ba63caf
JN		 4117 displayid_iter_for_each(block, &iter) {
4118 if (block->tag == DATA_BLOCK_CTA) {
6ff1c19f 4119 found = true;
1ba63caf 4120 break;
e28ad544
AR		 4121 }
4122 }
1ba63caf 4123 displayid_iter_end(&iter);
e28ad544 4124
6ff1c19f 4125 return found;
e28ad544
AR		 4126}
4127
e1cf35b9 4128static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic)
7befe621 4129{
9212f8ee
VS		 4130 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127);
4131 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219);
4132
8c1b2bd9
VS		 4133 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1))
4134 return &edid_cea_modes_1[vic - 1];
f7655d42
VS		 4135 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193))
4136 return &edid_cea_modes_193[vic - 193];
7befe621
VS		 4137 return NULL;
4138}
4139
4140static u8 cea_num_vics(void)
4141{
f7655d42 4142 return 193 + ARRAY_SIZE(edid_cea_modes_193);
7befe621
VS		 4143}
4144
4145static u8 cea_next_vic(u8 vic)
4146{
8c1b2bd9 4147 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1))
f7655d42
VS		 4148 vic = 193;
4149 return vic;
7befe621
VS		 4150}
4151
e6e79209
VS		 4152/*
4153 * Calculate the alternate clock for the CEA mode
4154 * (60Hz vs. 59.94Hz etc.)
4155 */
4156static unsigned int
4157cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
4158{
4159 unsigned int clock = cea_mode->clock;
4160
0425662f 4161 if (drm_mode_vrefresh(cea_mode) % 6 != 0)
e6e79209
VS		 4162 return clock;
4163
4164 /*
4165 * edid_cea_modes contains the 59.94Hz
4166 * variant for 240 and 480 line modes,
4167 * and the 60Hz variant otherwise.
4168 */
4169 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
9afd808c 4170 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
e6e79209 4171 else
9afd808c 4172 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
e6e79209
VS		 4173
4174 return clock;
4175}
4176
c45a4e46
VS		 4177static bool
4178cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
4179{
4180 /*
4181 * For certain VICs the spec allows the vertical
4182 * front porch to vary by one or two lines.
4183 *
4184 * cea_modes[] stores the variant with the shortest
4185 * vertical front porch. We can adjust the mode to
4186 * get the other variants by simply increasing the
4187 * vertical front porch length.
4188 */
7befe621
VS		 4189 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 ||
4190 cea_mode_for_vic(9)->vtotal != 262 ||
4191 cea_mode_for_vic(12)->vtotal != 262 ||
4192 cea_mode_for_vic(13)->vtotal != 262 ||
4193 cea_mode_for_vic(23)->vtotal != 312 ||
4194 cea_mode_for_vic(24)->vtotal != 312 ||
4195 cea_mode_for_vic(27)->vtotal != 312 ||
4196 cea_mode_for_vic(28)->vtotal != 312);
c45a4e46
VS		 4197
4198 if (((vic == 8 || vic == 9 ||
4199 vic == 12 || vic == 13) && mode->vtotal < 263) ||
4200 ((vic == 23 || vic == 24 ||
4201 vic == 27 || vic == 28) && mode->vtotal < 314)) {
4202 mode->vsync_start++;
4203 mode->vsync_end++;
4204 mode->vtotal++;
4205
4206 return true;
4207 }
4208
4209 return false;
4210}
4211
4c6bcf44
VS		 4212static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
4213 unsigned int clock_tolerance)
4214{
357768cc 4215 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 4216 u8 vic;
4c6bcf44
VS		 4217
4218 if (!to_match->clock)
4219 return 0;
4220
357768cc
VS		 4221 if (to_match->picture_aspect_ratio)
4222 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4223
7befe621 4224 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
563c4a75 4225 struct drm_display_mode cea_mode;
4c6bcf44
VS		 4226 unsigned int clock1, clock2;
4227
563c4a75
VS		 4228 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
4229
4c6bcf44 4230 /* Check both 60Hz and 59.94Hz */
c45a4e46
VS		 4231 clock1 = cea_mode.clock;
4232 clock2 = cea_mode_alternate_clock(&cea_mode);
4c6bcf44
VS		 4233
4234 if (abs(to_match->clock - clock1) > clock_tolerance &&
4235 abs(to_match->clock - clock2) > clock_tolerance)
4236 continue;
4237
c45a4e46 4238 do {
357768cc 4239 if (drm_mode_match(to_match, &cea_mode, match_flags))
c45a4e46
VS		 4240 return vic;
4241 } while (cea_mode_alternate_timings(vic, &cea_mode));
4c6bcf44
VS		 4242 }
4243
4244 return 0;
4245}
4246
18316c8c
TR		 4247/**
4248 * drm_match_cea_mode - look for a CEA mode matching given mode
4249 * @to_match: display mode
4250 *
db6cf833 4251 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
18316c8c 4252 * mode.
a4799037 4253 */
18316c8c 4254u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
a4799037 4255{
357768cc 4256 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 4257 u8 vic;
a4799037 4258
a90b590e
VS		 4259 if (!to_match->clock)
4260 return 0;
4261
357768cc
VS		 4262 if (to_match->picture_aspect_ratio)
4263 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4264
7befe621 4265 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
563c4a75 4266 struct drm_display_mode cea_mode;
a90b590e
VS		 4267 unsigned int clock1, clock2;
4268
563c4a75
VS		 4269 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
4270
a90b590e 4271 /* Check both 60Hz and 59.94Hz */
c45a4e46
VS		 4272 clock1 = cea_mode.clock;
4273 clock2 = cea_mode_alternate_clock(&cea_mode);
a4799037 4274
c45a4e46
VS		 4275 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
4276 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
4277 continue;
4278
4279 do {
357768cc 4280 if (drm_mode_match(to_match, &cea_mode, match_flags))
c45a4e46
VS		 4281 return vic;
4282 } while (cea_mode_alternate_timings(vic, &cea_mode));
a4799037 4283 }
c45a4e46 4284
a4799037
SM		 4285 return 0;
4286}
4287EXPORT_SYMBOL(drm_match_cea_mode);
4288
d9278b4c
JN		 4289static bool drm_valid_cea_vic(u8 vic)
4290{
7befe621 4291 return cea_mode_for_vic(vic) != NULL;
d9278b4c
JN		 4292}
4293
28c03a44 4294static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
0967e6a5 4295{
7befe621
VS		 4296 const struct drm_display_mode *mode = cea_mode_for_vic(video_code);
4297
4298 if (mode)
4299 return mode->picture_aspect_ratio;
4300
4301 return HDMI_PICTURE_ASPECT_NONE;
0967e6a5 4302}
0967e6a5 4303
d2b43473
WL		 4304static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code)
4305{
4306 return edid_4k_modes[video_code].picture_aspect_ratio;
4307}
4308
3f2f6533
LD		 4309/*
4310 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
4311 * specific block).
3f2f6533
LD		 4312 */
4313static unsigned int
4314hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
4315{
3f2f6533
LD		 4316 return cea_mode_alternate_clock(hdmi_mode);
4317}
4318
4c6bcf44
VS		 4319static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
4320 unsigned int clock_tolerance)
4321{
357768cc 4322 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 4323 u8 vic;
4c6bcf44
VS		 4324
4325 if (!to_match->clock)
4326 return 0;
4327
d2b43473
WL		 4328 if (to_match->picture_aspect_ratio)
4329 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4330
d9278b4c
JN		 4331 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
4332 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4c6bcf44
VS		 4333 unsigned int clock1, clock2;
4334
4335 /* Make sure to also match alternate clocks */
4336 clock1 = hdmi_mode->clock;
4337 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
4338
4339 if (abs(to_match->clock - clock1) > clock_tolerance &&
4340 abs(to_match->clock - clock2) > clock_tolerance)
4341 continue;
4342
357768cc 4343 if (drm_mode_match(to_match, hdmi_mode, match_flags))
d9278b4c 4344 return vic;
4c6bcf44
VS		 4345 }
4346
4347 return 0;
4348}
4349
3f2f6533
LD		 4350/*
4351 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
4352 * @to_match: display mode
4353 *
4354 * An HDMI mode is one defined in the HDMI vendor specific block.
4355 *
4356 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
4357 */
4358static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
4359{
357768cc 4360 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
d9278b4c 4361 u8 vic;
3f2f6533
LD		 4362
4363 if (!to_match->clock)
4364 return 0;
4365
d2b43473
WL		 4366 if (to_match->picture_aspect_ratio)
4367 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4368
d9278b4c
JN		 4369 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
4370 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3f2f6533
LD		 4371 unsigned int clock1, clock2;
4372
4373 /* Make sure to also match alternate clocks */
4374 clock1 = hdmi_mode->clock;
4375 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
4376
4377 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
4378 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
357768cc 4379 drm_mode_match(to_match, hdmi_mode, match_flags))
d9278b4c 4380 return vic;
3f2f6533
LD		 4381 }
4382 return 0;
4383}
4384
d9278b4c
JN		 4385static bool drm_valid_hdmi_vic(u8 vic)
4386{
4387 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
4388}
4389
40f71f5b
JN		 4390static int add_alternate_cea_modes(struct drm_connector *connector,
4391 const struct drm_edid *drm_edid)
e6e79209
VS		 4392{
4393 struct drm_device *dev = connector->dev;
4394 struct drm_display_mode *mode, *tmp;
4395 LIST_HEAD(list);
4396 int modes = 0;
4397
6ff1c19f 4398 /* Don't add CTA modes if the CTA extension block is missing */
40f71f5b 4399 if (!drm_edid_has_cta_extension(drm_edid))
e6e79209
VS		 4400 return 0;
4401
4402 /*
4403 * Go through all probed modes and create a new mode
4404 * with the alternate clock for certain CEA modes.
4405 */
4406 list_for_each_entry(mode, &connector->probed_modes, head) {
3f2f6533 4407 const struct drm_display_mode *cea_mode = NULL;
e6e79209 4408 struct drm_display_mode *newmode;
d9278b4c 4409 u8 vic = drm_match_cea_mode(mode);
e6e79209
VS		 4410 unsigned int clock1, clock2;
4411
d9278b4c 4412 if (drm_valid_cea_vic(vic)) {
7befe621 4413 cea_mode = cea_mode_for_vic(vic);
3f2f6533
LD		 4414 clock2 = cea_mode_alternate_clock(cea_mode);
4415 } else {
d9278b4c
JN		 4416 vic = drm_match_hdmi_mode(mode);
4417 if (drm_valid_hdmi_vic(vic)) {
4418 cea_mode = &edid_4k_modes[vic];
3f2f6533
LD		 4419 clock2 = hdmi_mode_alternate_clock(cea_mode);
4420 }
4421 }
e6e79209 4422
3f2f6533
LD		 4423 if (!cea_mode)
4424 continue;
e6e79209
VS		 4425
4426 clock1 = cea_mode->clock;
e6e79209
VS		 4427
4428 if (clock1 == clock2)
4429 continue;
4430
4431 if (mode->clock != clock1 && mode->clock != clock2)
4432 continue;
4433
4434 newmode = drm_mode_duplicate(dev, cea_mode);
4435 if (!newmode)
4436 continue;
4437
27130212
DL		 4438 /* Carry over the stereo flags */
4439 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
4440
e6e79209
VS		 4441 /*
4442 * The current mode could be either variant. Make
4443 * sure to pick the "other" clock for the new mode.
4444 */
4445 if (mode->clock != clock1)
4446 newmode->clock = clock1;
4447 else
4448 newmode->clock = clock2;
4449
4450 list_add_tail(&newmode->head, &list);
4451 }
4452
4453 list_for_each_entry_safe(mode, tmp, &list, head) {
4454 list_del(&mode->head);
4455 drm_mode_probed_add(connector, mode);
4456 modes++;
4457 }
4458
4459 return modes;
4460}
a4799037 4461
8ec6e075
SS		 4462static u8 svd_to_vic(u8 svd)
4463{
4464 /* 0-6 bit vic, 7th bit native mode indicator */
4465 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
4466 return svd & 127;
4467
4468 return svd;
4469}
4470
aff04ace
TW		 4471static struct drm_display_mode *
4472drm_display_mode_from_vic_index(struct drm_connector *connector,
4473 const u8 *video_db, u8 video_len,
4474 u8 video_index)
54ac76f8
CS		 4475{
4476 struct drm_device *dev = connector->dev;
aff04ace 4477 struct drm_display_mode *newmode;
d9278b4c 4478 u8 vic;
54ac76f8 4479
aff04ace
TW		 4480 if (video_db == NULL || video_index >= video_len)
4481 return NULL;
4482
4483 /* CEA modes are numbered 1..127 */
8ec6e075 4484 vic = svd_to_vic(video_db[video_index]);
d9278b4c 4485 if (!drm_valid_cea_vic(vic))
aff04ace
TW		 4486 return NULL;
4487
7befe621 4488 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
409bbf1e
DL		 4489 if (!newmode)
4490 return NULL;
4491
aff04ace
TW		 4492 return newmode;
4493}
4494
832d4f2f
SS		 4495/*
4496 * do_y420vdb_modes - Parse YCBCR 420 only modes
4497 * @connector: connector corresponding to the HDMI sink
4498 * @svds: start of the data block of CEA YCBCR 420 VDB
4499 * @len: length of the CEA YCBCR 420 VDB
4500 *
4501 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
4502 * which contains modes which can be supported in YCBCR 420
4503 * output format only.
4504 */
4505static int do_y420vdb_modes(struct drm_connector *connector,
4506 const u8 *svds, u8 svds_len)
4507{
4508 int modes = 0, i;
4509 struct drm_device *dev = connector->dev;
4510 struct drm_display_info *info = &connector->display_info;
4511 struct drm_hdmi_info *hdmi = &info->hdmi;
4512
4513 for (i = 0; i < svds_len; i++) {
4514 u8 vic = svd_to_vic(svds[i]);
4515 struct drm_display_mode *newmode;
4516
4517 if (!drm_valid_cea_vic(vic))
4518 continue;
4519
7befe621 4520 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
832d4f2f
SS		 4521 if (!newmode)
4522 break;
4523 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
4524 drm_mode_probed_add(connector, newmode);
4525 modes++;
4526 }
4527
4528 if (modes > 0)
c03d0b52 4529 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
832d4f2f
SS		 4530 return modes;
4531}
4532
4533/*
4534 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap
4535 * @connector: connector corresponding to the HDMI sink
4536 * @vic: CEA vic for the video mode to be added in the map
4537 *
4538 * Makes an entry for a videomode in the YCBCR 420 bitmap
4539 */
4540static void
4541drm_add_cmdb_modes(struct drm_connector *connector, u8 svd)
4542{
4543 u8 vic = svd_to_vic(svd);
4544 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4545
4546 if (!drm_valid_cea_vic(vic))
4547 return;
4548
4549 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
4550}
4551
7af655bc
VS		 4552/**
4553 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC
4554 * @dev: DRM device
8d7d8c0a 4555 * @video_code: CEA VIC of the mode
7af655bc
VS		 4556 *
4557 * Creates a new mode matching the specified CEA VIC.
4558 *
4559 * Returns: A new drm_display_mode on success or NULL on failure
4560 */
4561struct drm_display_mode *
4562drm_display_mode_from_cea_vic(struct drm_device *dev,
4563 u8 video_code)
4564{
4565 const struct drm_display_mode *cea_mode;
4566 struct drm_display_mode *newmode;
4567
4568 cea_mode = cea_mode_for_vic(video_code);
4569 if (!cea_mode)
4570 return NULL;
4571
4572 newmode = drm_mode_duplicate(dev, cea_mode);
4573 if (!newmode)
4574 return NULL;
4575
4576 return newmode;
4577}
4578EXPORT_SYMBOL(drm_display_mode_from_cea_vic);
4579
aff04ace
TW		 4580static int
4581do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
4582{
4583 int i, modes = 0;
832d4f2f 4584 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
aff04ace
TW		 4585
4586 for (i = 0; i < len; i++) {
4587 struct drm_display_mode *mode;
948de842 4588
aff04ace
TW		 4589 mode = drm_display_mode_from_vic_index(connector, db, len, i);
4590 if (mode) {
832d4f2f
SS		 4591 /*
4592 * YCBCR420 capability block contains a bitmap which
4593 * gives the index of CEA modes from CEA VDB, which
4594 * can support YCBCR 420 sampling output also (apart
4595 * from RGB/YCBCR444 etc).
4596 * For example, if the bit 0 in bitmap is set,
4597 * first mode in VDB can support YCBCR420 output too.
4598 * Add YCBCR420 modes only if sink is HDMI 2.0 capable.
4599 */
4600 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i))
4601 drm_add_cmdb_modes(connector, db[i]);
4602
aff04ace
TW		 4603 drm_mode_probed_add(connector, mode);
4604 modes++;
54ac76f8
CS		 4605 }
4606 }
4607
4608 return modes;
4609}
4610
c858cfca
DL		 4611struct stereo_mandatory_mode {
4612 int width, height, vrefresh;
4613 unsigned int flags;
4614};
4615
4616static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
f7e121b7
DL		 4617 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4618 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
c858cfca
DL		 4619 { 1920, 1080, 50,
4620 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
4621 { 1920, 1080, 60,
4622 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
f7e121b7
DL		 4623 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4624 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
4625 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4626 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
c858cfca
DL		 4627};
4628
4629static bool
4630stereo_match_mandatory(const struct drm_display_mode *mode,
4631 const struct stereo_mandatory_mode *stereo_mode)
4632{
4633 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
4634
4635 return mode->hdisplay == stereo_mode->width &&
4636 mode->vdisplay == stereo_mode->height &&
4637 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
4638 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
4639}
4640
c858cfca
DL		 4641static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
4642{
4643 struct drm_device *dev = connector->dev;
4644 const struct drm_display_mode *mode;
4645 struct list_head stereo_modes;
f7e121b7 4646 int modes = 0, i;
c858cfca
DL		 4647
4648 INIT_LIST_HEAD(&stereo_modes);
4649
4650 list_for_each_entry(mode, &connector->probed_modes, head) {
f7e121b7
DL		 4651 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
4652 const struct stereo_mandatory_mode *mandatory;
c858cfca
DL		 4653 struct drm_display_mode *new_mode;
4654
f7e121b7
DL		 4655 if (!stereo_match_mandatory(mode,
4656 &stereo_mandatory_modes[i]))
4657 continue;
c858cfca 4658
f7e121b7 4659 mandatory = &stereo_mandatory_modes[i];
c858cfca
DL		 4660 new_mode = drm_mode_duplicate(dev, mode);
4661 if (!new_mode)
4662 continue;
4663
f7e121b7 4664 new_mode->flags |= mandatory->flags;
c858cfca
DL		 4665 list_add_tail(&new_mode->head, &stereo_modes);
4666 modes++;
f7e121b7 4667 }
c858cfca
DL		 4668 }
4669
4670 list_splice_tail(&stereo_modes, &connector->probed_modes);
4671
4672 return modes;
4673}
4674
1deee8d7
DL		 4675static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
4676{
4677 struct drm_device *dev = connector->dev;
4678 struct drm_display_mode *newmode;
4679
d9278b4c 4680 if (!drm_valid_hdmi_vic(vic)) {
e1e7bc48
JN		 4681 drm_err(connector->dev, "[CONNECTOR:%d:%s] Unknown HDMI VIC: %d\n",
4682 connector->base.id, connector->name, vic);
1deee8d7
DL		 4683 return 0;
4684 }
4685
4686 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
4687 if (!newmode)
4688 return 0;
4689
4690 drm_mode_probed_add(connector, newmode);
4691
4692 return 1;
4693}
4694
fbf46025
TW		 4695static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
4696 const u8 *video_db, u8 video_len, u8 video_index)
4697{
fbf46025
TW		 4698 struct drm_display_mode *newmode;
4699 int modes = 0;
fbf46025
TW		 4700
4701 if (structure & (1 << 0)) {
aff04ace
TW		 4702 newmode = drm_display_mode_from_vic_index(connector, video_db,
4703 video_len,
4704 video_index);
fbf46025
TW		 4705 if (newmode) {
4706 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
4707 drm_mode_probed_add(connector, newmode);
4708 modes++;
4709 }
4710 }
4711 if (structure & (1 << 6)) {
aff04ace
TW		 4712 newmode = drm_display_mode_from_vic_index(connector, video_db,
4713 video_len,
4714 video_index);
fbf46025
TW		 4715 if (newmode) {
4716 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4717 drm_mode_probed_add(connector, newmode);
4718 modes++;
4719 }
4720 }
4721 if (structure & (1 << 8)) {
aff04ace
TW		 4722 newmode = drm_display_mode_from_vic_index(connector, video_db,
4723 video_len,
4724 video_index);
fbf46025 4725 if (newmode) {
89570eeb 4726 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
fbf46025
TW		 4727 drm_mode_probed_add(connector, newmode);
4728 modes++;
4729 }
4730 }
4731
4732 return modes;
4733}
4734
7ebe1963
LD		 4735/*
4736 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
4737 * @connector: connector corresponding to the HDMI sink
4738 * @db: start of the CEA vendor specific block
4739 * @len: length of the CEA block payload, ie. one can access up to db[len]
4740 *
c858cfca
DL		 4741 * Parses the HDMI VSDB looking for modes to add to @connector. This function
4742 * also adds the stereo 3d modes when applicable.
7ebe1963
LD		 4743 */
4744static int
fbf46025
TW		 4745do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
4746 const u8 *video_db, u8 video_len)
7ebe1963 4747{
f1781e9b 4748 struct drm_display_info *info = &connector->display_info;
0e5083aa 4749 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
fbf46025
TW		 4750 u8 vic_len, hdmi_3d_len = 0;
4751 u16 mask;
4752 u16 structure_all;
7ebe1963
LD		 4753
4754 if (len < 8)
4755 goto out;
4756
4757 /* no HDMI_Video_Present */
4758 if (!(db[8] & (1 << 5)))
4759 goto out;
4760
4761 /* Latency_Fields_Present */
4762 if (db[8] & (1 << 7))
4763 offset += 2;
4764
4765 /* I_Latency_Fields_Present */
4766 if (db[8] & (1 << 6))
4767 offset += 2;
4768
4769 /* the declared length is not long enough for the 2 first bytes
4770 * of additional video format capabilities */
c858cfca 4771 if (len < (8 + offset + 2))
7ebe1963
LD		 4772 goto out;
4773
c858cfca
DL		 4774 /* 3D_Present */
4775 offset++;
fbf46025 4776 if (db[8 + offset] & (1 << 7)) {
c858cfca
DL		 4777 modes += add_hdmi_mandatory_stereo_modes(connector);
4778
fbf46025
TW		 4779 /* 3D_Multi_present */
4780 multi_present = (db[8 + offset] & 0x60) >> 5;
4781 }
4782
c858cfca 4783 offset++;
7ebe1963 4784 vic_len = db[8 + offset] >> 5;
fbf46025 4785 hdmi_3d_len = db[8 + offset] & 0x1f;
7ebe1963
LD		 4786
4787 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
7ebe1963
LD		 4788 u8 vic;
4789
4790 vic = db[9 + offset + i];
1deee8d7 4791 modes += add_hdmi_mode(connector, vic);
7ebe1963 4792 }
fbf46025
TW		 4793 offset += 1 + vic_len;
4794
0e5083aa
TW		 4795 if (multi_present == 1)
4796 multi_len = 2;
4797 else if (multi_present == 2)
4798 multi_len = 4;
4799 else
4800 multi_len = 0;
fbf46025 4801
0e5083aa 4802 if (len < (8 + offset + hdmi_3d_len - 1))
fbf46025
TW		 4803 goto out;
4804
0e5083aa 4805 if (hdmi_3d_len < multi_len)
fbf46025
TW		 4806 goto out;
4807
0e5083aa
TW		 4808 if (multi_present == 1 || multi_present == 2) {
4809 /* 3D_Structure_ALL */
4810 structure_all = (db[8 + offset] << 8) | db[9 + offset];
fbf46025 4811
0e5083aa
TW		 4812 /* check if 3D_MASK is present */
4813 if (multi_present == 2)
4814 mask = (db[10 + offset] << 8) | db[11 + offset];
4815 else
4816 mask = 0xffff;
4817
4818 for (i = 0; i < 16; i++) {
4819 if (mask & (1 << i))
4820 modes += add_3d_struct_modes(connector,
4821 structure_all,
4822 video_db,
4823 video_len, i);
4824 }
4825 }
4826
4827 offset += multi_len;
4828
4829 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
4830 int vic_index;
4831 struct drm_display_mode *newmode = NULL;
4832 unsigned int newflag = 0;
4833 bool detail_present;
4834
4835 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
4836
4837 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
4838 break;
4839
4840 /* 2D_VIC_order_X */
4841 vic_index = db[8 + offset + i] >> 4;
4842
4843 /* 3D_Structure_X */
4844 switch (db[8 + offset + i] & 0x0f) {
4845 case 0:
4846 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
4847 break;
4848 case 6:
4849 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4850 break;
4851 case 8:
4852 /* 3D_Detail_X */
4853 if ((db[9 + offset + i] >> 4) == 1)
4854 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4855 break;
4856 }
4857
4858 if (newflag != 0) {
4859 newmode = drm_display_mode_from_vic_index(connector,
4860 video_db,
4861 video_len,
4862 vic_index);
4863
4864 if (newmode) {
4865 newmode->flags |= newflag;
4866 drm_mode_probed_add(connector, newmode);
4867 modes++;
4868 }
4869 }
4870
4871 if (detail_present)
4872 i++;
fbf46025 4873 }
7ebe1963
LD		 4874
4875out:
f1781e9b
VS		 4876 if (modes > 0)
4877 info->has_hdmi_infoframe = true;
7ebe1963
LD		 4878 return modes;
4879}
4880
9e50b9d5
VS		 4881static int
4882cea_revision(const u8 *cea)
4883{
5036c0d0
VS		 4884 /*
4885 * FIXME is this correct for the DispID variant?
4886 * The DispID spec doesn't really specify whether
4887 * this is the revision of the CEA extension or
4888 * the DispID CEA data block. And the only value
4889 * given as an example is 0.
4890 */
9e50b9d5
VS		 4891 return cea[1];
4892}
4893
aba58254
JN		 4894/*
4895 * CTA Data Block iterator.
4896 *
4897 * Iterate through all CTA Data Blocks in both EDID CTA Extensions and DisplayID
4898 * CTA Data Blocks.
4899 *
4900 * struct cea_db *db:
4901 * struct cea_db_iter iter;
4902 *
4903 * cea_db_iter_edid_begin(edid, &iter);
4904 * cea_db_iter_for_each(db, &iter) {
4905 * // do stuff with db
4906 * }
4907 * cea_db_iter_end(&iter);
4908 */
4909struct cea_db_iter {
4910 struct drm_edid_iter edid_iter;
4911 struct displayid_iter displayid_iter;
4912
4913 /* Current Data Block Collection. */
4914 const u8 *collection;
4915
4916 /* Current Data Block index in current collection. */
4917 int index;
4918
4919 /* End index in current collection. */
4920 int end;
4921};
4922
4923/* CTA-861-H section 7.4 CTA Data BLock Collection */
4924struct cea_db {
4925 u8 tag_length;
4926 u8 data[];
4927} __packed;
4928
49a62a29 4929static int cea_db_tag(const struct cea_db *db)
aba58254 4930{
aba58254
JN		 4931 return db->tag_length >> 5;
4932}
4933
4934static int cea_db_payload_len(const void *_db)
4935{
4936 /* FIXME: Transition to passing struct cea_db * everywhere. */
4937 const struct cea_db *db = _db;
4938
4939 return db->tag_length & 0x1f;
4940}
4941
4942static const void *cea_db_data(const struct cea_db *db)
4943{
4944 return db->data;
4945}
4946
a9ec4fd0
JN		 4947static bool cea_db_is_extended_tag(const struct cea_db *db, int tag)
4948{
4949 return cea_db_tag(db) == CTA_DB_EXTENDED_TAG &&
4950 cea_db_payload_len(db) >= 1 &&
4951 db->data[0] == tag;
4952}
4953
4954static bool cea_db_is_vendor(const struct cea_db *db, int vendor_oui)
4955{
4956 const u8 *data = cea_db_data(db);
4957
4958 return cea_db_tag(db) == CTA_DB_VENDOR &&
4959 cea_db_payload_len(db) >= 3 &&
4960 oui(data[2], data[1], data[0]) == vendor_oui;
4961}
4962
5e87b2e5
JN		 4963static void cea_db_iter_edid_begin(const struct drm_edid *drm_edid,
4964 struct cea_db_iter *iter)
aba58254
JN		 4965{
4966 memset(iter, 0, sizeof(*iter));
4967
bbded689 4968 drm_edid_iter_begin(drm_edid, &iter->edid_iter);
d9ba1b4c 4969 displayid_iter_edid_begin(drm_edid, &iter->displayid_iter);
aba58254
JN		 4970}
4971
4972static const struct cea_db *
4973__cea_db_iter_current_block(const struct cea_db_iter *iter)
4974{
4975 const struct cea_db *db;
4976
4977 if (!iter->collection)
4978 return NULL;
4979
4980 db = (const struct cea_db *)&iter->collection[iter->index];
4981
4982 if (iter->index + sizeof(*db) <= iter->end &&
4983 iter->index + sizeof(*db) + cea_db_payload_len(db) <= iter->end)
4984 return db;
4985
4986 return NULL;
4987}
4988
11a8d095
JN		 4989/*
4990 * References:
4991 * - CTA-861-H section 7.3.3 CTA Extension Version 3
4992 */
4993static int cea_db_collection_size(const u8 *cta)
4994{
4995 u8 d = cta[2];
4996
4997 if (d < 4 || d > 127)
4998 return 0;
4999
5000 return d - 4;
5001}
5002
aba58254
JN		 5003/*
5004 * References:
5005 * - VESA E-EDID v1.4
5006 * - CTA-861-H section 7.3.3 CTA Extension Version 3
5007 */
5008static const void *__cea_db_iter_edid_next(struct cea_db_iter *iter)
5009{
5010 const u8 *ext;
5011
5012 drm_edid_iter_for_each(ext, &iter->edid_iter) {
11a8d095
JN		 5013 int size;
5014
aba58254
JN		 5015 /* Only support CTA Extension revision 3+ */
5016 if (ext[0] != CEA_EXT || cea_revision(ext) < 3)
5017 continue;
5018
11a8d095
JN		 5019 size = cea_db_collection_size(ext);
5020 if (!size)
aba58254
JN		 5021 continue;
5022
11a8d095
JN		 5023 iter->index = 4;
5024 iter->end = iter->index + size;
5025
aba58254
JN		 5026 return ext;
5027 }
5028
5029 return NULL;
5030}
5031
5032/*
5033 * References:
5034 * - DisplayID v1.3 Appendix C: CEA Data Block within a DisplayID Data Block
5035 * - DisplayID v2.0 section 4.10 CTA DisplayID Data Block
5036 *
5037 * Note that the above do not specify any connection between DisplayID Data
5038 * Block revision and CTA Extension versions.
5039 */
5040static const void *__cea_db_iter_displayid_next(struct cea_db_iter *iter)
5041{
5042 const struct displayid_block *block;
5043
5044 displayid_iter_for_each(block, &iter->displayid_iter) {
5045 if (block->tag != DATA_BLOCK_CTA)
5046 continue;
5047
5048 /*
5049 * The displayid iterator has already verified the block bounds
5050 * in displayid_iter_block().
5051 */
5052 iter->index = sizeof(*block);
5053 iter->end = iter->index + block->num_bytes;
5054
5055 return block;
5056 }
5057
5058 return NULL;
5059}
5060
5061static const struct cea_db *__cea_db_iter_next(struct cea_db_iter *iter)
5062{
5063 const struct cea_db *db;
5064
5065 if (iter->collection) {
5066 /* Current collection should always be valid. */
5067 db = __cea_db_iter_current_block(iter);
5068 if (WARN_ON(!db)) {
5069 iter->collection = NULL;
5070 return NULL;
5071 }
5072
5073 /* Next block in CTA Data Block Collection */
5074 iter->index += sizeof(*db) + cea_db_payload_len(db);
5075
5076 db = __cea_db_iter_current_block(iter);
5077 if (db)
5078 return db;
5079 }
5080
5081 for (;;) {
5082 /*
5083 * Find the next CTA Data Block Collection. First iterate all
5084 * the EDID CTA Extensions, then all the DisplayID CTA blocks.
5085 *
5086 * Per DisplayID v1.3 Appendix B: DisplayID as an EDID
5087 * Extension, it's recommended that DisplayID extensions are
5088 * exposed after all of the CTA Extensions.
5089 */
5090 iter->collection = __cea_db_iter_edid_next(iter);
5091 if (!iter->collection)
5092 iter->collection = __cea_db_iter_displayid_next(iter);
5093
5094 if (!iter->collection)
5095 return NULL;
5096
5097 db = __cea_db_iter_current_block(iter);
5098 if (db)
5099 return db;
5100 }
5101}
5102
5103#define cea_db_iter_for_each(__db, __iter) \
5104 while (((__db) = __cea_db_iter_next(__iter)))
5105
5106static void cea_db_iter_end(struct cea_db_iter *iter)
5107{
5108 displayid_iter_end(&iter->displayid_iter);
5109 drm_edid_iter_end(&iter->edid_iter);
5110
5111 memset(iter, 0, sizeof(*iter));
5112}
5113
49a62a29 5114static bool cea_db_is_hdmi_vsdb(const struct cea_db *db)
7ebe1963 5115{
a9ec4fd0
JN		 5116 return cea_db_is_vendor(db, HDMI_IEEE_OUI) &&
5117 cea_db_payload_len(db) >= 5;
7ebe1963
LD		 5118}
5119
49a62a29 5120static bool cea_db_is_hdmi_forum_vsdb(const struct cea_db *db)
50dd1bd1 5121{
a9ec4fd0
JN		 5122 return cea_db_is_vendor(db, HDMI_FORUM_IEEE_OUI) &&
5123 cea_db_payload_len(db) >= 7;
50dd1bd1
TR		 5124}
5125
18e3c1d5
JN		 5126static bool cea_db_is_hdmi_forum_eeodb(const void *db)
5127{
5128 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_EEODB) &&
5129 cea_db_payload_len(db) >= 2;
5130}
5131
49a62a29 5132static bool cea_db_is_microsoft_vsdb(const struct cea_db *db)
2869f599 5133{
a9ec4fd0
JN		 5134 return cea_db_is_vendor(db, MICROSOFT_IEEE_OUI) &&
5135 cea_db_payload_len(db) == 21;
2869f599
PZ		 5136}
5137
49a62a29 5138static bool cea_db_is_vcdb(const struct cea_db *db)
1581b2df 5139{
a9ec4fd0
JN		 5140 return cea_db_is_extended_tag(db, CTA_EXT_DB_VIDEO_CAP) &&
5141 cea_db_payload_len(db) == 2;
1581b2df
VS		 5142}
5143
49a62a29 5144static bool cea_db_is_hdmi_forum_scdb(const struct cea_db *db)
115fcf58 5145{
a9ec4fd0
JN		 5146 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_SCDB) &&
5147 cea_db_payload_len(db) >= 7;
115fcf58
LS		 5148}
5149
49a62a29 5150static bool cea_db_is_y420cmdb(const struct cea_db *db)
832d4f2f 5151{
a9ec4fd0 5152 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_CAP_MAP);
832d4f2f
SS		 5153}
5154
49a62a29 5155static bool cea_db_is_y420vdb(const struct cea_db *db)
832d4f2f 5156{
a9ec4fd0
JN		 5157 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_DATA);
5158}
832d4f2f 5159
49a62a29 5160static bool cea_db_is_hdmi_hdr_metadata_block(const struct cea_db *db)
a9ec4fd0
JN		 5161{
5162 return cea_db_is_extended_tag(db, CTA_EXT_DB_HDR_STATIC_METADATA) &&
5163 cea_db_payload_len(db) >= 3;
832d4f2f
SS		 5164}
5165
18e3c1d5
JN		 5166/*
5167 * Get the HF-EEODB override extension block count from EDID.
5168 *
5169 * The passed in EDID may be partially read, as long as it has at least two
5170 * blocks (base block and one extension block) if EDID extension count is > 0.
5171 *
5172 * Note that this is *not* how you should parse CTA Data Blocks in general; this
5173 * is only to handle partially read EDIDs. Normally, use the CTA Data Block
5174 * iterators instead.
5175 *
5176 * References:
5177 * - HDMI 2.1 section 10.3.6 HDMI Forum EDID Extension Override Data Block
5178 */
5179static int edid_hfeeodb_extension_block_count(const struct edid *edid)
5180{
5181 const u8 *cta;
5182
5183 /* No extensions according to base block, no HF-EEODB. */
5184 if (!edid_extension_block_count(edid))
5185 return 0;
5186
5187 /* HF-EEODB is always in the first EDID extension block only */
5188 cta = edid_extension_block_data(edid, 0);
5189 if (edid_block_tag(cta) != CEA_EXT || cea_revision(cta) < 3)
5190 return 0;
5191
5192 /* Need to have the data block collection, and at least 3 bytes. */
5193 if (cea_db_collection_size(cta) < 3)
5194 return 0;
5195
5196 /*
5197 * Sinks that include the HF-EEODB in their E-EDID shall include one and
5198 * only one instance of the HF-EEODB in the E-EDID, occupying bytes 4
5199 * through 6 of Block 1 of the E-EDID.
5200 */
5201 if (!cea_db_is_hdmi_forum_eeodb(&cta[4]))
5202 return 0;
5203
5204 return cta[4 + 2];
5205}
5206
832d4f2f
SS		 5207static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector,
5208 const u8 *db)
5209{
5210 struct drm_display_info *info = &connector->display_info;
5211 struct drm_hdmi_info *hdmi = &info->hdmi;
5212 u8 map_len = cea_db_payload_len(db) - 1;
5213 u8 count;
5214 u64 map = 0;
5215
5216 if (map_len == 0) {
5217 /* All CEA modes support ycbcr420 sampling also.*/
5218 hdmi->y420_cmdb_map = U64_MAX;
c03d0b52 5219 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
832d4f2f
SS		 5220 return;
5221 }
5222
5223 /*
5224 * This map indicates which of the existing CEA block modes
5225 * from VDB can support YCBCR420 output too. So if bit=0 is
5226 * set, first mode from VDB can support YCBCR420 output too.
5227 * We will parse and keep this map, before parsing VDB itself
5228 * to avoid going through the same block again and again.
5229 *
5230 * Spec is not clear about max possible size of this block.
5231 * Clamping max bitmap block size at 8 bytes. Every byte can
5232 * address 8 CEA modes, in this way this map can address
5233 * 8*8 = first 64 SVDs.
5234 */
5235 if (WARN_ON_ONCE(map_len > 8))
5236 map_len = 8;
5237
5238 for (count = 0; count < map_len; count++)
5239 map |= (u64)db[2 + count] << (8 * count);
5240
5241 if (map)
c03d0b52 5242 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
832d4f2f
SS		 5243
5244 hdmi->y420_cmdb_map = map;
5245}
5246
40f71f5b
JN		 5247static int add_cea_modes(struct drm_connector *connector,
5248 const struct drm_edid *drm_edid)
54ac76f8 5249{
537d9ed2
JN		 5250 const struct cea_db *db;
5251 struct cea_db_iter iter;
54ac76f8
CS		 5252 int modes = 0;
5253
5e87b2e5 5254 cea_db_iter_edid_begin(drm_edid, &iter);
537d9ed2
JN		 5255 cea_db_iter_for_each(db, &iter) {
5256 const u8 *hdmi = NULL, *video = NULL;
5257 u8 hdmi_len = 0, video_len = 0;
5258
5259 if (cea_db_tag(db) == CTA_DB_VIDEO) {
5260 video = cea_db_data(db);
5261 video_len = cea_db_payload_len(db);
5262 modes += do_cea_modes(connector, video, video_len);
5263 } else if (cea_db_is_hdmi_vsdb(db)) {
5264 /* FIXME: Switch to use cea_db_data() */
5265 hdmi = (const u8 *)db;
5266 hdmi_len = cea_db_payload_len(db);
5267 } else if (cea_db_is_y420vdb(db)) {
5268 const u8 *vdb420 = cea_db_data(db) + 1;
5269
5270 /* Add 4:2:0(only) modes present in EDID */
5271 modes += do_y420vdb_modes(connector, vdb420,
5272 cea_db_payload_len(db) - 1);
54ac76f8 5273 }
54ac76f8 5274
537d9ed2
JN		 5275 /*
5276 * We parse the HDMI VSDB after having added the cea modes as we
5277 * will be patching their flags when the sink supports stereo
5278 * 3D.
5279 */
5280 if (hdmi)
5281 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len,
5282 video, video_len);
5283 }
5284 cea_db_iter_end(&iter);
c858cfca 5285
54ac76f8
CS		 5286 return modes;
5287}
5288
e1e7bc48
JN		 5289static void fixup_detailed_cea_mode_clock(struct drm_connector *connector,
5290 struct drm_display_mode *mode)
fa3a7340
VS		 5291{
5292 const struct drm_display_mode *cea_mode;
5293 int clock1, clock2, clock;
d9278b4c 5294 u8 vic;
fa3a7340
VS		 5295 const char *type;
5296
4c6bcf44
VS		 5297 /*
5298 * allow 5kHz clock difference either way to account for
5299 * the 10kHz clock resolution limit of detailed timings.
5300 */
d9278b4c
JN		 5301 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
5302 if (drm_valid_cea_vic(vic)) {
fa3a7340 5303 type = "CEA";
7befe621 5304 cea_mode = cea_mode_for_vic(vic);
fa3a7340
VS		 5305 clock1 = cea_mode->clock;
5306 clock2 = cea_mode_alternate_clock(cea_mode);
5307 } else {
d9278b4c
JN		 5308 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
5309 if (drm_valid_hdmi_vic(vic)) {
fa3a7340 5310 type = "HDMI";
d9278b4c 5311 cea_mode = &edid_4k_modes[vic];
fa3a7340
VS		 5312 clock1 = cea_mode->clock;
5313 clock2 = hdmi_mode_alternate_clock(cea_mode);
5314 } else {
5315 return;
5316 }
5317 }
5318
5319 /* pick whichever is closest */
5320 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
5321 clock = clock1;
5322 else
5323 clock = clock2;
5324
5325 if (mode->clock == clock)
5326 return;
5327
e1e7bc48
JN		 5328 drm_dbg_kms(connector->dev,
5329 "[CONNECTOR:%d:%s] detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
5330 connector->base.id, connector->name,
5331 type, vic, mode->clock, clock);
fa3a7340
VS		 5332 mode->clock = clock;
5333}
5334
82068ede
JH		 5335static void drm_calculate_luminance_range(struct drm_connector *connector)
5336{
5337 struct hdr_static_metadata *hdr_metadata = &connector->hdr_sink_metadata.hdmi_type1;
5338 struct drm_luminance_range_info *luminance_range =
5339 &connector->display_info.luminance_range;
5340 static const u8 pre_computed_values[] = {
5341 50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69,
5342 71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98
5343 };
5344 u32 max_avg, min_cll, max, min, q, r;
5345
5346 if (!(hdr_metadata->metadata_type & BIT(HDMI_STATIC_METADATA_TYPE1)))
5347 return;
5348
5349 max_avg = hdr_metadata->max_fall;
5350 min_cll = hdr_metadata->min_cll;
5351
5352 /*
5353 * From the specification (CTA-861-G), for calculating the maximum
5354 * luminance we need to use:
5355 * Luminance = 50*2**(CV/32)
5356 * Where CV is a one-byte value.
5357 * For calculating this expression we may need float point precision;
5358 * to avoid this complexity level, we take advantage that CV is divided
5359 * by a constant. From the Euclids division algorithm, we know that CV
5360 * can be written as: CV = 32*q + r. Next, we replace CV in the
5361 * Luminance expression and get 50*(2**q)*(2**(r/32)), hence we just
5362 * need to pre-compute the value of r/32. For pre-computing the values
5363 * We just used the following Ruby line:
5364 * (0...32).each {|cv| puts (50*2**(cv/32.0)).round}
5365 * The results of the above expressions can be verified at
5366 * pre_computed_values.
5367 */
5368 q = max_avg >> 5;
5369 r = max_avg % 32;
5370 max = (1 << q) * pre_computed_values[r];
5371
5372 /* min luminance: maxLum * (CV/255)^2 / 100 */
5373 q = DIV_ROUND_CLOSEST(min_cll, 255);
5374 min = max * DIV_ROUND_CLOSEST((q * q), 100);
5375
5376 luminance_range->min_luminance = min;
5377 luminance_range->max_luminance = max;
5378}
5379
e85959d6
US		 5380static uint8_t eotf_supported(const u8 *edid_ext)
5381{
5382 return edid_ext[2] &
5383 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
5384 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
b5e3eed1
VS		 5385 BIT(HDMI_EOTF_SMPTE_ST2084) |
5386 BIT(HDMI_EOTF_BT_2100_HLG));
e85959d6
US		 5387}
5388
5389static uint8_t hdr_metadata_type(const u8 *edid_ext)
5390{
5391 return edid_ext[3] &
5392 BIT(HDMI_STATIC_METADATA_TYPE1);
5393}
5394
5395static void
5396drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
5397{
5398 u16 len;
5399
5400 len = cea_db_payload_len(db);
5401
5402 connector->hdr_sink_metadata.hdmi_type1.eotf =
5403 eotf_supported(db);
5404 connector->hdr_sink_metadata.hdmi_type1.metadata_type =
5405 hdr_metadata_type(db);
5406
5407 if (len >= 4)
5408 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4];
5409 if (len >= 5)
5410 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5];
82068ede 5411 if (len >= 6) {
e85959d6 5412 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6];
82068ede
JH		 5413
5414 /* Calculate only when all values are available */
5415 drm_calculate_luminance_range(connector);
5416 }
e85959d6
US		 5417}
5418
76adaa34 5419static void
23ebf8b9 5420drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
76adaa34 5421{
8504072a 5422 u8 len = cea_db_payload_len(db);
76adaa34 5423
f7da7785
JN		 5424 if (len >= 6 && (db[6] & (1 << 7)))
5425 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
8504072a
VS		 5426 if (len >= 8) {
5427 connector->latency_present[0] = db[8] >> 7;
5428 connector->latency_present[1] = (db[8] >> 6) & 1;
5429 }
5430 if (len >= 9)
5431 connector->video_latency[0] = db[9];
5432 if (len >= 10)
5433 connector->audio_latency[0] = db[10];
5434 if (len >= 11)
5435 connector->video_latency[1] = db[11];
5436 if (len >= 12)
5437 connector->audio_latency[1] = db[12];
76adaa34 5438
e1e7bc48
JN		 5439 drm_dbg_kms(connector->dev,
5440 "[CONNECTOR:%d:%s] HDMI: latency present %d %d, video latency %d %d, audio latency %d %d\n",
5441 connector->base.id, connector->name,
5442 connector->latency_present[0], connector->latency_present[1],
5443 connector->video_latency[0], connector->video_latency[1],
5444 connector->audio_latency[0], connector->audio_latency[1]);
76adaa34
WF		 5445}
5446
5447static void
4194442d 5448monitor_name(const struct detailed_timing *timing, void *data)
76adaa34 5449{
4194442d
JN		 5450 const char **res = data;
5451
5452 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME))
a7a131ac
VS		 5453 return;
5454
4194442d 5455 *res = timing->data.other_data.data.str.str;
14f77fdd
VS		 5456}
5457
2c54f87c 5458static int get_monitor_name(const struct drm_edid *drm_edid, char name[13])
59f7c0fa 5459{
4194442d 5460 const char *edid_name = NULL;
59f7c0fa
JB		 5461 int mnl;
5462
2c54f87c 5463 if (!drm_edid || !name)
59f7c0fa
JB		 5464 return 0;
5465
45aa2336 5466 drm_for_each_detailed_block(drm_edid, monitor_name, &edid_name);
59f7c0fa
JB		 5467 for (mnl = 0; edid_name && mnl < 13; mnl++) {
5468 if (edid_name[mnl] == 0x0a)
5469 break;
5470
5471 name[mnl] = edid_name[mnl];
5472 }
5473
5474 return mnl;
5475}
5476
5477/**
5478 * drm_edid_get_monitor_name - fetch the monitor name from the edid
5479 * @edid: monitor EDID information
5480 * @name: pointer to a character array to hold the name of the monitor
5481 * @bufsize: The size of the name buffer (should be at least 14 chars.)
5482 *
5483 */
f4e558ec 5484void drm_edid_get_monitor_name(const struct edid *edid, char *name, int bufsize)
59f7c0fa 5485{
2c54f87c 5486 int name_length = 0;
4d23f484 5487
59f7c0fa
JB		 5488 if (bufsize <= 0)
5489 return;
5490
2c54f87c
JN		 5491 if (edid) {
5492 char buf[13];
5493 struct drm_edid drm_edid = {
5494 .edid = edid,
5495 .size = edid_size(edid),
5496 };
5497
5498 name_length = min(get_monitor_name(&drm_edid, buf), bufsize - 1);
5499 memcpy(name, buf, name_length);
5500 }
5501
59f7c0fa
JB		 5502 name[name_length] = '\0';
5503}
5504EXPORT_SYMBOL(drm_edid_get_monitor_name);
5505
42750d39
JN		 5506static void clear_eld(struct drm_connector *connector)
5507{
5508 memset(connector->eld, 0, sizeof(connector->eld));
5509
5510 connector->latency_present[0] = false;
5511 connector->latency_present[1] = false;
5512 connector->video_latency[0] = 0;
5513 connector->audio_latency[0] = 0;
5514 connector->video_latency[1] = 0;
5515 connector->audio_latency[1] = 0;
5516}
5517
79436a1c 5518/*
76adaa34
WF		 5519 * drm_edid_to_eld - build ELD from EDID
5520 * @connector: connector corresponding to the HDMI/DP sink
a2f9790d 5521 * @drm_edid: EDID to parse
76adaa34 5522 *
db6cf833 5523 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
1d1c3665 5524 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
76adaa34 5525 */
f4e558ec 5526static void drm_edid_to_eld(struct drm_connector *connector,
a2f9790d 5527 const struct drm_edid *drm_edid)
76adaa34 5528{
58304630 5529 const struct drm_display_info *info = &connector->display_info;
37852141
JN		 5530 const struct cea_db *db;
5531 struct cea_db_iter iter;
76adaa34 5532 uint8_t *eld = connector->eld;
7c018782 5533 int total_sad_count = 0;
76adaa34 5534 int mnl;
76adaa34 5535
42750d39 5536 clear_eld(connector);
85c91580 5537
a2f9790d 5538 if (!drm_edid)
e9bd0b84
JN		 5539 return;
5540
2c54f87c 5541 mnl = get_monitor_name(drm_edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
e1e7bc48
JN		 5542 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD monitor %s\n",
5543 connector->base.id, connector->name,
5544 &eld[DRM_ELD_MONITOR_NAME_STRING]);
59f7c0fa 5545
58304630 5546 eld[DRM_ELD_CEA_EDID_VER_MNL] = info->cea_rev << DRM_ELD_CEA_EDID_VER_SHIFT;
f7da7785 5547 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
76adaa34 5548
f7da7785 5549 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
76adaa34 5550
a2f9790d
JN		 5551 eld[DRM_ELD_MANUFACTURER_NAME0] = drm_edid->edid->mfg_id[0];
5552 eld[DRM_ELD_MANUFACTURER_NAME1] = drm_edid->edid->mfg_id[1];
5553 eld[DRM_ELD_PRODUCT_CODE0] = drm_edid->edid->prod_code[0];
5554 eld[DRM_ELD_PRODUCT_CODE1] = drm_edid->edid->prod_code[1];
76adaa34 5555
5e87b2e5 5556 cea_db_iter_edid_begin(drm_edid, &iter);
37852141
JN		 5557 cea_db_iter_for_each(db, &iter) {
5558 const u8 *data = cea_db_data(db);
5559 int len = cea_db_payload_len(db);
deec222e 5560 int sad_count;
9e50b9d5 5561
37852141
JN		 5562 switch (cea_db_tag(db)) {
5563 case CTA_DB_AUDIO:
5564 /* Audio Data Block, contains SADs */
5565 sad_count = min(len / 3, 15 - total_sad_count);
5566 if (sad_count >= 1)
5567 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
5568 data, sad_count * 3);
5569 total_sad_count += sad_count;
5570 break;
5571 case CTA_DB_SPEAKER:
5572 /* Speaker Allocation Data Block */
5573 if (len >= 1)
5574 eld[DRM_ELD_SPEAKER] = data[0];
5575 break;
5576 case CTA_DB_VENDOR:
5577 /* HDMI Vendor-Specific Data Block */
5578 if (cea_db_is_hdmi_vsdb(db))
5579 drm_parse_hdmi_vsdb_audio(connector, (const u8 *)db);
5580 break;
5581 default:
5582 break;
76adaa34 5583 }
9e50b9d5 5584 }
37852141
JN		 5585 cea_db_iter_end(&iter);
5586
f7da7785 5587 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
76adaa34 5588
1d1c3665
JN		 5589 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5590 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5591 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
5592 else
5593 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
76adaa34 5594
938fd8aa
JN		 5595 eld[DRM_ELD_BASELINE_ELD_LEN] =
5596 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
5597
e1e7bc48
JN		 5598 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD size %d, SAD count %d\n",
5599 connector->base.id, connector->name,
5600 drm_eld_size(eld), total_sad_count);
76adaa34 5601}
76adaa34 5602
bba4b647
JN		 5603static int _drm_edid_to_sad(const struct drm_edid *drm_edid,
5604 struct cea_sad **sads)
fe214163 5605{
b07debc2
JN		 5606 const struct cea_db *db;
5607 struct cea_db_iter iter;
fe214163 5608 int count = 0;
fe214163 5609
5e87b2e5 5610 cea_db_iter_edid_begin(drm_edid, &iter);
b07debc2 5611 cea_db_iter_for_each(db, &iter) {
9d72b7e2 5612 if (cea_db_tag(db) == CTA_DB_AUDIO) {
fe214163 5613 int j;
948de842 5614
b07debc2 5615 count = cea_db_payload_len(db) / 3; /* SAD is 3B */
fe214163
RM		 5616 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
5617 if (!*sads)
5618 return -ENOMEM;
5619 for (j = 0; j < count; j++) {
b07debc2 5620 const u8 *sad = &db->data[j * 3];
fe214163
RM		 5621
5622 (*sads)[j].format = (sad[0] & 0x78) >> 3;
5623 (*sads)[j].channels = sad[0] & 0x7;
5624 (*sads)[j].freq = sad[1] & 0x7F;
5625 (*sads)[j].byte2 = sad[2];
5626 }
5627 break;
5628 }
5629 }
b07debc2
JN		 5630 cea_db_iter_end(&iter);
5631
5632 DRM_DEBUG_KMS("Found %d Short Audio Descriptors\n", count);
fe214163
RM		 5633
5634 return count;
5635}
bba4b647
JN		 5636
5637/**
5638 * drm_edid_to_sad - extracts SADs from EDID
5639 * @edid: EDID to parse
5640 * @sads: pointer that will be set to the extracted SADs
5641 *
5642 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
5643 *
5644 * Note: The returned pointer needs to be freed using kfree().
5645 *
5646 * Return: The number of found SADs or negative number on error.
5647 */
5648int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads)
5649{
5650 struct drm_edid drm_edid;
5651
5652 return _drm_edid_to_sad(drm_edid_legacy_init(&drm_edid, edid), sads);
5653}
fe214163
RM		 5654EXPORT_SYMBOL(drm_edid_to_sad);
5655
02703451
JN		 5656static int _drm_edid_to_speaker_allocation(const struct drm_edid *drm_edid,
5657 u8 **sadb)
d105f476 5658{
ed317307
JN		 5659 const struct cea_db *db;
5660 struct cea_db_iter iter;
d105f476 5661 int count = 0;
d105f476 5662
5e87b2e5 5663 cea_db_iter_edid_begin(drm_edid, &iter);
ed317307
JN		 5664 cea_db_iter_for_each(db, &iter) {
5665 if (cea_db_tag(db) == CTA_DB_SPEAKER &&
5666 cea_db_payload_len(db) == 3) {
5667 *sadb = kmemdup(db->data, cea_db_payload_len(db),
5668 GFP_KERNEL);
5669 if (!*sadb)
5670 return -ENOMEM;
5671 count = cea_db_payload_len(db);
5672 break;
d105f476
AD		 5673 }
5674 }
ed317307
JN		 5675 cea_db_iter_end(&iter);
5676
5677 DRM_DEBUG_KMS("Found %d Speaker Allocation Data Blocks\n", count);
d105f476
AD		 5678
5679 return count;
5680}
02703451
JN		 5681
5682/**
5683 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
5684 * @edid: EDID to parse
5685 * @sadb: pointer to the speaker block
5686 *
5687 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
5688 *
5689 * Note: The returned pointer needs to be freed using kfree().
5690 *
5691 * Return: The number of found Speaker Allocation Blocks or negative number on
5692 * error.
5693 */
5694int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb)
5695{
5696 struct drm_edid drm_edid;
5697
5698 return _drm_edid_to_speaker_allocation(drm_edid_legacy_init(&drm_edid, edid),
5699 sadb);
5700}
d105f476
AD		 5701EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
5702
76adaa34 5703/**
db6cf833 5704 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
76adaa34
WF		 5705 * @connector: connector associated with the HDMI/DP sink
5706 * @mode: the display mode
db6cf833
TR		 5707 *
5708 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
5709 * the sink doesn't support audio or video.
76adaa34
WF		 5710 */
5711int drm_av_sync_delay(struct drm_connector *connector,
3a818d35 5712 const struct drm_display_mode *mode)
76adaa34
WF		 5713{
5714 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
5715 int a, v;
5716
5717 if (!connector->latency_present[0])
5718 return 0;
5719 if (!connector->latency_present[1])
5720 i = 0;
5721
5722 a = connector->audio_latency[i];
5723 v = connector->video_latency[i];
5724
5725 /*
5726 * HDMI/DP sink doesn't support audio or video?
5727 */
5728 if (a == 255 || v == 255)
5729 return 0;
5730
5731 /*
5732 * Convert raw EDID values to millisecond.
5733 * Treat unknown latency as 0ms.
5734 */
5735 if (a)
5736 a = min(2 * (a - 1), 500);
5737 if (v)
5738 v = min(2 * (v - 1), 500);
5739
5740 return max(v - a, 0);
5741}
5742EXPORT_SYMBOL(drm_av_sync_delay);
5743
3176d092 5744static bool _drm_detect_hdmi_monitor(const struct drm_edid *drm_edid)
8fe9790d 5745{
4ce08703
JN		 5746 const struct cea_db *db;
5747 struct cea_db_iter iter;
5748 bool hdmi = false;
f23c20c8
ML		 5749
5750 /*
5751 * Because HDMI identifier is in Vendor Specific Block,
5752 * search it from all data blocks of CEA extension.
5753 */
5e87b2e5 5754 cea_db_iter_edid_begin(drm_edid, &iter);
4ce08703
JN		 5755 cea_db_iter_for_each(db, &iter) {
5756 if (cea_db_is_hdmi_vsdb(db)) {
5757 hdmi = true;
5758 break;
5759 }
f23c20c8 5760 }
4ce08703 5761 cea_db_iter_end(&iter);
f23c20c8 5762
4ce08703 5763 return hdmi;
f23c20c8 5764}
3176d092
JN		 5765
5766/**
5767 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
5768 * @edid: monitor EDID information
5769 *
5770 * Parse the CEA extension according to CEA-861-B.
5771 *
5772 * Drivers that have added the modes parsed from EDID to drm_display_info
5773 * should use &drm_display_info.is_hdmi instead of calling this function.
5774 *
5775 * Return: True if the monitor is HDMI, false if not or unknown.
5776 */
5777bool drm_detect_hdmi_monitor(const struct edid *edid)
5778{
5779 struct drm_edid drm_edid;
5780
5781 return _drm_detect_hdmi_monitor(drm_edid_legacy_init(&drm_edid, edid));
5782}
f23c20c8
ML		 5783EXPORT_SYMBOL(drm_detect_hdmi_monitor);
5784
0c057877 5785static bool _drm_detect_monitor_audio(const struct drm_edid *drm_edid)
8fe9790d 5786{
705bec3e 5787 struct drm_edid_iter edid_iter;
9975af04
JN		 5788 const struct cea_db *db;
5789 struct cea_db_iter iter;
43d16d84 5790 const u8 *edid_ext;
8fe9790d 5791 bool has_audio = false;
8fe9790d 5792
bbded689 5793 drm_edid_iter_begin(drm_edid, &edid_iter);
705bec3e
JN		 5794 drm_edid_iter_for_each(edid_ext, &edid_iter) {
5795 if (edid_ext[0] == CEA_EXT) {
5796 has_audio = edid_ext[3] & EDID_BASIC_AUDIO;
5797 if (has_audio)
5798 break;
5799 }
5800 }
5801 drm_edid_iter_end(&edid_iter);
8fe9790d
ZW		 5802
5803 if (has_audio) {
5804 DRM_DEBUG_KMS("Monitor has basic audio support\n");
5805 goto end;
5806 }
5807
5e87b2e5 5808 cea_db_iter_edid_begin(drm_edid, &iter);
9975af04
JN		 5809 cea_db_iter_for_each(db, &iter) {
5810 if (cea_db_tag(db) == CTA_DB_AUDIO) {
5811 const u8 *data = cea_db_data(db);
5812 int i;
8fe9790d 5813
9975af04 5814 for (i = 0; i < cea_db_payload_len(db); i += 3)
8fe9790d 5815 DRM_DEBUG_KMS("CEA audio format %d\n",
9975af04
JN		 5816 (data[i] >> 3) & 0xf);
5817 has_audio = true;
5818 break;
8fe9790d
ZW		 5819 }
5820 }
9975af04
JN		 5821 cea_db_iter_end(&iter);
5822
8fe9790d
ZW		 5823end:
5824 return has_audio;
5825}
0c057877
JN		 5826
5827/**
5828 * drm_detect_monitor_audio - check monitor audio capability
5829 * @edid: EDID block to scan
5830 *
5831 * Monitor should have CEA extension block.
5832 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
5833 * audio' only. If there is any audio extension block and supported
5834 * audio format, assume at least 'basic audio' support, even if 'basic
5835 * audio' is not defined in EDID.
5836 *
5837 * Return: True if the monitor supports audio, false otherwise.
5838 */
5839bool drm_detect_monitor_audio(const struct edid *edid)
5840{
5841 struct drm_edid drm_edid;
5842
5843 return _drm_detect_monitor_audio(drm_edid_legacy_init(&drm_edid, edid));
5844}
8fe9790d
ZW		 5845EXPORT_SYMBOL(drm_detect_monitor_audio);
5846
b1edd6a6 5847
c8127cf0
VS		 5848/**
5849 * drm_default_rgb_quant_range - default RGB quantization range
5850 * @mode: display mode
5851 *
5852 * Determine the default RGB quantization range for the mode,
5853 * as specified in CEA-861.
5854 *
5855 * Return: The default RGB quantization range for the mode
5856 */
5857enum hdmi_quantization_range
5858drm_default_rgb_quant_range(const struct drm_display_mode *mode)
5859{
5860 /* All CEA modes other than VIC 1 use limited quantization range. */
5861 return drm_match_cea_mode(mode) > 1 ?
5862 HDMI_QUANTIZATION_RANGE_LIMITED :
5863 HDMI_QUANTIZATION_RANGE_FULL;
5864}
5865EXPORT_SYMBOL(drm_default_rgb_quant_range);
5866
1581b2df
VS		 5867static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
5868{
5869 struct drm_display_info *info = &connector->display_info;
5870
e1e7bc48
JN		 5871 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] CEA VCDB 0x%02x\n",
5872 connector->base.id, connector->name, db[2]);
1581b2df
VS		 5873
5874 if (db[2] & EDID_CEA_VCDB_QS)
5875 info->rgb_quant_range_selectable = true;
5876}
5877
4499d488
SS		 5878static
5879void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane)
5880{
5881 switch (max_frl_rate) {
5882 case 1:
5883 *max_lanes = 3;
5884 *max_rate_per_lane = 3;
5885 break;
5886 case 2:
5887 *max_lanes = 3;
5888 *max_rate_per_lane = 6;
5889 break;
5890 case 3:
5891 *max_lanes = 4;
5892 *max_rate_per_lane = 6;
5893 break;
5894 case 4:
5895 *max_lanes = 4;
5896 *max_rate_per_lane = 8;
5897 break;
5898 case 5:
5899 *max_lanes = 4;
5900 *max_rate_per_lane = 10;
5901 break;
5902 case 6:
5903 *max_lanes = 4;
5904 *max_rate_per_lane = 12;
5905 break;
5906 case 0:
5907 default:
5908 *max_lanes = 0;
5909 *max_rate_per_lane = 0;
5910 }
5911}
5912
e6a9a2c3
SS		 5913static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
5914 const u8 *db)
5915{
5916 u8 dc_mask;
5917 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
5918
5919 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
9068e02f 5920 hdmi->y420_dc_modes = dc_mask;
e6a9a2c3
SS		 5921}
5922
5e706c4d
AN		 5923static void drm_parse_dsc_info(struct drm_hdmi_dsc_cap *hdmi_dsc,
5924 const u8 *hf_scds)
5925{
5e706c4d
AN		 5926 hdmi_dsc->v_1p2 = hf_scds[11] & DRM_EDID_DSC_1P2;
5927
5928 if (!hdmi_dsc->v_1p2)
5929 return;
5930
5931 hdmi_dsc->native_420 = hf_scds[11] & DRM_EDID_DSC_NATIVE_420;
5932 hdmi_dsc->all_bpp = hf_scds[11] & DRM_EDID_DSC_ALL_BPP;
5933
5934 if (hf_scds[11] & DRM_EDID_DSC_16BPC)
5935 hdmi_dsc->bpc_supported = 16;
5936 else if (hf_scds[11] & DRM_EDID_DSC_12BPC)
5937 hdmi_dsc->bpc_supported = 12;
5938 else if (hf_scds[11] & DRM_EDID_DSC_10BPC)
5939 hdmi_dsc->bpc_supported = 10;
5940 else
5941 /* Supports min 8 BPC if DSC 1.2 is supported*/
5942 hdmi_dsc->bpc_supported = 8;
5943
a07e6f56
AN		 5944 if (cea_db_payload_len(hf_scds) >= 12 && hf_scds[12]) {
5945 u8 dsc_max_slices;
5946 u8 dsc_max_frl_rate;
5e706c4d 5947
a07e6f56
AN		 5948 dsc_max_frl_rate = (hf_scds[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4;
5949 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes,
5950 &hdmi_dsc->max_frl_rate_per_lane);
5e706c4d 5951
a07e6f56
AN		 5952 dsc_max_slices = hf_scds[12] & DRM_EDID_DSC_MAX_SLICES;
5953
5954 switch (dsc_max_slices) {
5955 case 1:
5956 hdmi_dsc->max_slices = 1;
5957 hdmi_dsc->clk_per_slice = 340;
5958 break;
5959 case 2:
5960 hdmi_dsc->max_slices = 2;
5961 hdmi_dsc->clk_per_slice = 340;
5962 break;
5963 case 3:
5964 hdmi_dsc->max_slices = 4;
5965 hdmi_dsc->clk_per_slice = 340;
5966 break;
5967 case 4:
5968 hdmi_dsc->max_slices = 8;
5969 hdmi_dsc->clk_per_slice = 340;
5970 break;
5971 case 5:
5972 hdmi_dsc->max_slices = 8;
5973 hdmi_dsc->clk_per_slice = 400;
5974 break;
5975 case 6:
5976 hdmi_dsc->max_slices = 12;
5977 hdmi_dsc->clk_per_slice = 400;
5978 break;
5979 case 7:
5980 hdmi_dsc->max_slices = 16;
5981 hdmi_dsc->clk_per_slice = 400;
5982 break;
5983 case 0:
5984 default:
5985 hdmi_dsc->max_slices = 0;
5986 hdmi_dsc->clk_per_slice = 0;
5987 }
5e706c4d 5988 }
a07e6f56
AN		 5989
5990 if (cea_db_payload_len(hf_scds) >= 13 && hf_scds[13])
5991 hdmi_dsc->total_chunk_kbytes = hf_scds[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES;
5e706c4d
AN		 5992}
5993
d8cb49d2
JN		 5994/* Sink Capability Data Structure */
5995static void drm_parse_hdmi_forum_scds(struct drm_connector *connector,
5996 const u8 *hf_scds)
afa1c763 5997{
62c58af3
SS		 5998 struct drm_display_info *display = &connector->display_info;
5999 struct drm_hdmi_info *hdmi = &display->hdmi;
a07e6f56 6000 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap;
5e931c88
AN		 6001 int max_tmds_clock = 0;
6002 u8 max_frl_rate = 0;
6003 bool dsc_support = false;
afa1c763 6004
f1781e9b
VS		 6005 display->has_hdmi_infoframe = true;
6006
d8cb49d2 6007 if (hf_scds[6] & 0x80) {
afa1c763 6008 hdmi->scdc.supported = true;
d8cb49d2 6009 if (hf_scds[6] & 0x40)
afa1c763
SS		 6010 hdmi->scdc.read_request = true;
6011 }
62c58af3
SS		 6012
6013 /*
6014 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
6015 * And as per the spec, three factors confirm this:
6016 * * Availability of a HF-VSDB block in EDID (check)
6017 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
6018 * * SCDC support available (let's check)
6019 * Lets check it out.
6020 */
6021
d8cb49d2 6022 if (hf_scds[5]) {
62c58af3
SS		 6023 struct drm_scdc *scdc = &hdmi->scdc;
6024
5e931c88
AN		 6025 /* max clock is 5000 KHz times block value */
6026 max_tmds_clock = hf_scds[5] * 5000;
6027
62c58af3
SS		 6028 if (max_tmds_clock > 340000) {
6029 display->max_tmds_clock = max_tmds_clock;
62c58af3
SS		 6030 }
6031
6032 if (scdc->supported) {
6033 scdc->scrambling.supported = true;
6034
dbe2d2bf 6035 /* Few sinks support scrambling for clocks < 340M */
d8cb49d2 6036 if ((hf_scds[6] & 0x8))
62c58af3
SS		 6037 scdc->scrambling.low_rates = true;
6038 }
6039 }
e6a9a2c3 6040
d8cb49d2 6041 if (hf_scds[7]) {
d8cb49d2 6042 max_frl_rate = (hf_scds[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4;
4499d488
SS		 6043 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes,
6044 &hdmi->max_frl_rate_per_lane);
6045 }
6046
d8cb49d2 6047 drm_parse_ycbcr420_deep_color_info(connector, hf_scds);
a07e6f56 6048
5e931c88 6049 if (cea_db_payload_len(hf_scds) >= 11 && hf_scds[11]) {
a07e6f56 6050 drm_parse_dsc_info(hdmi_dsc, hf_scds);
5e931c88
AN		 6051 dsc_support = true;
6052 }
6053
6054 drm_dbg_kms(connector->dev,
66d17ecd
JN		 6055 "[CONNECTOR:%d:%s] HF-VSDB: max TMDS clock: %d KHz, HDMI 2.1 support: %s, DSC 1.2 support: %s\n",
6056 connector->base.id, connector->name,
5e931c88 6057 max_tmds_clock, str_yes_no(max_frl_rate), str_yes_no(dsc_support));
afa1c763
SS		 6058}
6059
1cea146a
VS		 6060static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
6061 const u8 *hdmi)
d0c94692 6062{
1826750f 6063 struct drm_display_info *info = &connector->display_info;
d0c94692
MK		 6064 unsigned int dc_bpc = 0;
6065
1cea146a
VS		 6066 /* HDMI supports at least 8 bpc */
6067 info->bpc = 8;
d0c94692 6068
1cea146a
VS		 6069 if (cea_db_payload_len(hdmi) < 6)
6070 return;
6071
6072 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
6073 dc_bpc = 10;
4adc33f3 6074 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_30;
e1e7bc48
JN		 6075 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 30.\n",
6076 connector->base.id, connector->name);
1cea146a
VS		 6077 }
6078
6079 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
6080 dc_bpc = 12;
4adc33f3 6081 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_36;
e1e7bc48
JN		 6082 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 36.\n",
6083 connector->base.id, connector->name);
1cea146a
VS		 6084 }
6085
6086 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
6087 dc_bpc = 16;
4adc33f3 6088 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_48;
e1e7bc48
JN		 6089 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 48.\n",
6090 connector->base.id, connector->name);
1cea146a
VS		 6091 }
6092
6093 if (dc_bpc == 0) {
e1e7bc48
JN		 6094 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] No deep color support on this HDMI sink.\n",
6095 connector->base.id, connector->name);
1cea146a
VS		 6096 return;
6097 }
6098
e1e7bc48
JN		 6099 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Assigning HDMI sink color depth as %d bpc.\n",
6100 connector->base.id, connector->name, dc_bpc);
1cea146a 6101 info->bpc = dc_bpc;
d0c94692 6102
1cea146a
VS		 6103 /* YCRCB444 is optional according to spec. */
6104 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
4adc33f3 6105 info->edid_hdmi_ycbcr444_dc_modes = info->edid_hdmi_rgb444_dc_modes;
e1e7bc48
JN		 6106 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does YCRCB444 in deep color.\n",
6107 connector->base.id, connector->name);
1cea146a 6108 }
d0c94692 6109
1cea146a
VS		 6110 /*
6111 * Spec says that if any deep color mode is supported at all,
6112 * then deep color 36 bit must be supported.
6113 */
6114 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
e1e7bc48
JN		 6115 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink should do DC_36, but does not!\n",
6116 connector->base.id, connector->name);
1cea146a
VS		 6117 }
6118}
d0c94692 6119
23ebf8b9
VS		 6120static void
6121drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
6122{
6123 struct drm_display_info *info = &connector->display_info;
6124 u8 len = cea_db_payload_len(db);
6125
a92d083d
LP		 6126 info->is_hdmi = true;
6127
23ebf8b9
VS		 6128 if (len >= 6)
6129 info->dvi_dual = db[6] & 1;
6130 if (len >= 7)
6131 info->max_tmds_clock = db[7] * 5000;
6132
e1e7bc48
JN		 6133 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI: DVI dual %d, max TMDS clock %d kHz\n",
6134 connector->base.id, connector->name,
6135 info->dvi_dual, info->max_tmds_clock);
23ebf8b9
VS		 6136
6137 drm_parse_hdmi_deep_color_info(connector, db);
6138}
6139
2869f599
PZ		 6140/*
6141 * See EDID extension for head-mounted and specialized monitors, specified at:
6142 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/specialized-monitors-edid-extension
6143 */
6144static void drm_parse_microsoft_vsdb(struct drm_connector *connector,
6145 const u8 *db)
6146{
6147 struct drm_display_info *info = &connector->display_info;
6148 u8 version = db[4];
6149 bool desktop_usage = db[5] & BIT(6);
6150
6151 /* Version 1 and 2 for HMDs, version 3 flags desktop usage explicitly */
6152 if (version == 1 || version == 2 || (version == 3 && !desktop_usage))
6153 info->non_desktop = true;
6154
66d17ecd
JN		 6155 drm_dbg_kms(connector->dev,
6156 "[CONNECTOR:%d:%s] HMD or specialized display VSDB version %u: 0x%02x\n",
6157 connector->base.id, connector->name, version, db[5]);
2869f599
PZ		 6158}
6159
1cea146a 6160static void drm_parse_cea_ext(struct drm_connector *connector,
e42192b4 6161 const struct drm_edid *drm_edid)
1cea146a
VS		 6162{
6163 struct drm_display_info *info = &connector->display_info;
8db73897 6164 struct drm_edid_iter edid_iter;
dfc03125
JN		 6165 const struct cea_db *db;
6166 struct cea_db_iter iter;
1cea146a 6167 const u8 *edid_ext;
d0c94692 6168
bbded689 6169 drm_edid_iter_begin(drm_edid, &edid_iter);
8db73897
JN		 6170 drm_edid_iter_for_each(edid_ext, &edid_iter) {
6171 if (edid_ext[0] != CEA_EXT)
6172 continue;
d0c94692 6173
8db73897
JN		 6174 if (!info->cea_rev)
6175 info->cea_rev = edid_ext[1];
d0c94692 6176
8db73897 6177 if (info->cea_rev != edid_ext[1])
e1e7bc48
JN		 6178 drm_dbg_kms(connector->dev,
6179 "[CONNECTOR:%d:%s] CEA extension version mismatch %u != %u\n",
6180 connector->base.id, connector->name,
6181 info->cea_rev, edid_ext[1]);
7344bad7 6182
8db73897
JN		 6183 /* The existence of a CTA extension should imply RGB support */
6184 info->color_formats = DRM_COLOR_FORMAT_RGB444;
7344bad7
JN		 6185 if (edid_ext[3] & EDID_CEA_YCRCB444)
6186 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
6187 if (edid_ext[3] & EDID_CEA_YCRCB422)
6188 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
6189 }
8db73897 6190 drm_edid_iter_end(&edid_iter);
1cea146a 6191
5e87b2e5 6192 cea_db_iter_edid_begin(drm_edid, &iter);
dfc03125
JN		 6193 cea_db_iter_for_each(db, &iter) {
6194 /* FIXME: convert parsers to use struct cea_db */
6195 const u8 *data = (const u8 *)db;
1cea146a 6196
23ebf8b9 6197 if (cea_db_is_hdmi_vsdb(db))
dfc03125 6198 drm_parse_hdmi_vsdb_video(connector, data);
be982415
JN		 6199 else if (cea_db_is_hdmi_forum_vsdb(db) ||
6200 cea_db_is_hdmi_forum_scdb(db))
dfc03125 6201 drm_parse_hdmi_forum_scds(connector, data);
be982415 6202 else if (cea_db_is_microsoft_vsdb(db))
dfc03125 6203 drm_parse_microsoft_vsdb(connector, data);
be982415 6204 else if (cea_db_is_y420cmdb(db))
dfc03125 6205 drm_parse_y420cmdb_bitmap(connector, data);
be982415 6206 else if (cea_db_is_vcdb(db))
dfc03125 6207 drm_parse_vcdb(connector, data);
be982415 6208 else if (cea_db_is_hdmi_hdr_metadata_block(db))
dfc03125 6209 drm_parse_hdr_metadata_block(connector, data);
1cea146a 6210 }
dfc03125 6211 cea_db_iter_end(&iter);
d0c94692
MK		 6212}
6213
a1d11d1e 6214static
c7943bb3 6215void get_monitor_range(const struct detailed_timing *timing, void *c)
a1d11d1e 6216{
c7943bb3
VS		 6217 struct detailed_mode_closure *closure = c;
6218 struct drm_display_info *info = &closure->connector->display_info;
6219 struct drm_monitor_range_info *monitor_range = &info->monitor_range;
a1d11d1e
MN		 6220 const struct detailed_non_pixel *data = &timing->data.other_data;
6221 const struct detailed_data_monitor_range *range = &data->data.range;
c7943bb3 6222 const struct edid *edid = closure->drm_edid->edid;
a1d11d1e 6223
e379814b 6224 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
a1d11d1e
MN		 6225 return;
6226
6227 /*
67d7469a
VS		 6228 * These limits are used to determine the VRR refresh
6229 * rate range. Only the "range limits only" variant
6230 * of the range descriptor seems to guarantee that
6231 * any and all timings are accepted by the sink, as
6232 * opposed to just timings conforming to the indicated
6233 * formula (GTF/GTF2/CVT). Thus other variants of the
6234 * range descriptor are not accepted here.
a1d11d1e
MN		 6235 */
6236 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG)
6237 return;
6238
6239 monitor_range->min_vfreq = range->min_vfreq;
6240 monitor_range->max_vfreq = range->max_vfreq;
c7943bb3
VS		 6241
6242 if (edid->revision >= 4) {
6243 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ)
6244 monitor_range->min_vfreq += 255;
6245 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MAX_VFREQ)
6246 monitor_range->max_vfreq += 255;
6247 }
a1d11d1e
MN		 6248}
6249
e42192b4
JN		 6250static void drm_get_monitor_range(struct drm_connector *connector,
6251 const struct drm_edid *drm_edid)
a1d11d1e 6252{
c7943bb3
VS		 6253 const struct drm_display_info *info = &connector->display_info;
6254 struct detailed_mode_closure closure = {
6255 .connector = connector,
6256 .drm_edid = drm_edid,
6257 };
a1d11d1e 6258
dd3abfe4 6259 if (drm_edid->edid->revision < 4)
ca2582c6
VS		 6260 return;
6261
6262 if (!(drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ))
a1d11d1e
MN		 6263 return;
6264
c7943bb3 6265 drm_for_each_detailed_block(drm_edid, get_monitor_range, &closure);
a1d11d1e 6266
e1e7bc48
JN		 6267 drm_dbg_kms(connector->dev,
6268 "[CONNECTOR:%d:%s] Supported Monitor Refresh rate range is %d Hz - %d Hz\n",
6269 connector->base.id, connector->name,
6270 info->monitor_range.min_vfreq, info->monitor_range.max_vfreq);
a1d11d1e
MN		 6271}
6272
18a9cbbe
JN		 6273static void drm_parse_vesa_mso_data(struct drm_connector *connector,
6274 const struct displayid_block *block)
6275{
6276 struct displayid_vesa_vendor_specific_block *vesa =
6277 (struct displayid_vesa_vendor_specific_block *)block;
6278 struct drm_display_info *info = &connector->display_info;
6279
6280 if (block->num_bytes < 3) {
66d17ecd
JN		 6281 drm_dbg_kms(connector->dev,
6282 "[CONNECTOR:%d:%s] Unexpected vendor block size %u\n",
6283 connector->base.id, connector->name, block->num_bytes);
18a9cbbe
JN		 6284 return;
6285 }
6286
6287 if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI)
6288 return;
6289
6290 if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
66d17ecd
JN		 6291 drm_dbg_kms(connector->dev,
6292 "[CONNECTOR:%d:%s] Unexpected VESA vendor block size\n",
6293 connector->base.id, connector->name);
18a9cbbe
JN		 6294 return;
6295 }
6296
6297 switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
6298 default:
66d17ecd
JN		 6299 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved MSO mode value\n",
6300 connector->base.id, connector->name);
18a9cbbe
JN		 6301 fallthrough;
6302 case 0:
6303 info->mso_stream_count = 0;
6304 break;
6305 case 1:
6306 info->mso_stream_count = 2; /* 2 or 4 links */
6307 break;
6308 case 2:
6309 info->mso_stream_count = 4; /* 4 links */
6310 break;
6311 }
6312
6313 if (!info->mso_stream_count) {
6314 info->mso_pixel_overlap = 0;
6315 return;
6316 }
6317
6318 info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
6319 if (info->mso_pixel_overlap > 8) {
66d17ecd
JN		 6320 drm_dbg_kms(connector->dev,
6321 "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n",
6322 connector->base.id, connector->name,
18a9cbbe
JN		 6323 info->mso_pixel_overlap);
6324 info->mso_pixel_overlap = 8;
6325 }
6326
66d17ecd
JN		 6327 drm_dbg_kms(connector->dev,
6328 "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n",
6329 connector->base.id, connector->name,
18a9cbbe
JN		 6330 info->mso_stream_count, info->mso_pixel_overlap);
6331}
6332
e42192b4
JN		 6333static void drm_update_mso(struct drm_connector *connector,
6334 const struct drm_edid *drm_edid)
18a9cbbe
JN		 6335{
6336 const struct displayid_block *block;
6337 struct displayid_iter iter;
6338
d9ba1b4c 6339 displayid_iter_edid_begin(drm_edid, &iter);
18a9cbbe
JN		 6340 displayid_iter_for_each(block, &iter) {
6341 if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC)
6342 drm_parse_vesa_mso_data(connector, block);
6343 }
6344 displayid_iter_end(&iter);
6345}
6346
170178fe
KP		 6347/* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
6348 * all of the values which would have been set from EDID
6349 */
02b16fbc 6350static void drm_reset_display_info(struct drm_connector *connector)
170178fe
KP		 6351{
6352 struct drm_display_info *info = &connector->display_info;
6353
6354 info->width_mm = 0;
6355 info->height_mm = 0;
6356
6357 info->bpc = 0;
6358 info->color_formats = 0;
6359 info->cea_rev = 0;
6360 info->max_tmds_clock = 0;
6361 info->dvi_dual = false;
a92d083d 6362 info->is_hdmi = false;
170178fe 6363 info->has_hdmi_infoframe = false;
1581b2df 6364 info->rgb_quant_range_selectable = false;
1f6b8eef 6365 memset(&info->hdmi, 0, sizeof(info->hdmi));
170178fe 6366
70c0b80d
MR		 6367 info->edid_hdmi_rgb444_dc_modes = 0;
6368 info->edid_hdmi_ycbcr444_dc_modes = 0;
6369
170178fe 6370 info->non_desktop = 0;
a1d11d1e 6371 memset(&info->monitor_range, 0, sizeof(info->monitor_range));
82068ede 6372 memset(&info->luminance_range, 0, sizeof(info->luminance_range));
18a9cbbe
JN		 6373
6374 info->mso_stream_count = 0;
6375 info->mso_pixel_overlap = 0;
aa193f7e 6376 info->max_dsc_bpp = 0;
170178fe 6377}
170178fe 6378
e42192b4
JN		 6379static u32 update_display_info(struct drm_connector *connector,
6380 const struct drm_edid *drm_edid)
3b11228b 6381{
1826750f 6382 struct drm_display_info *info = &connector->display_info;
e42192b4 6383 const struct edid *edid = drm_edid->edid;
ebec9a7b 6384
e42192b4 6385 u32 quirks = edid_get_quirks(drm_edid);
170178fe 6386
1f6b8eef
VS		 6387 drm_reset_display_info(connector);
6388
3b11228b
JB		 6389 info->width_mm = edid->width_cm * 10;
6390 info->height_mm = edid->height_cm * 10;
6391
e42192b4 6392 drm_get_monitor_range(connector, drm_edid);
a1d11d1e 6393
a988bc72 6394 if (edid->revision < 3)
ce99534e 6395 goto out;
3b11228b
JB		 6396
6397 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
ce99534e 6398 goto out;
3b11228b 6399
ecbd4912 6400 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
e42192b4 6401 drm_parse_cea_ext(connector, drm_edid);
d0c94692 6402
210a021d
MK		 6403 /*
6404 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
6405 *
6406 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
6407 * tells us to assume 8 bpc color depth if the EDID doesn't have
6408 * extensions which tell otherwise.
6409 */
3bde449f
VS		 6410 if (info->bpc == 0 && edid->revision == 3 &&
6411 edid->input & DRM_EDID_DIGITAL_DFP_1_X) {
210a021d 6412 info->bpc = 8;
e1e7bc48
JN		 6413 drm_dbg_kms(connector->dev,
6414 "[CONNECTOR:%d:%s] Assigning DFP sink color depth as %d bpc.\n",
6415 connector->base.id, connector->name, info->bpc);
210a021d
MK		 6416 }
6417
a988bc72
LPC		 6418 /* Only defined for 1.4 with digital displays */
6419 if (edid->revision < 4)
ce99534e 6420 goto out;
a988bc72 6421
3b11228b
JB		 6422 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
6423 case DRM_EDID_DIGITAL_DEPTH_6:
6424 info->bpc = 6;
6425 break;
6426 case DRM_EDID_DIGITAL_DEPTH_8:
6427 info->bpc = 8;
6428 break;
6429 case DRM_EDID_DIGITAL_DEPTH_10:
6430 info->bpc = 10;
6431 break;
6432 case DRM_EDID_DIGITAL_DEPTH_12:
6433 info->bpc = 12;
6434 break;
6435 case DRM_EDID_DIGITAL_DEPTH_14:
6436 info->bpc = 14;
6437 break;
6438 case DRM_EDID_DIGITAL_DEPTH_16:
6439 info->bpc = 16;
6440 break;
6441 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
6442 default:
6443 info->bpc = 0;
6444 break;
6445 }
da05a5a7 6446
e1e7bc48
JN		 6447 drm_dbg_kms(connector->dev,
6448 "[CONNECTOR:%d:%s] Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
6449 connector->base.id, connector->name, info->bpc);
d0c94692 6450
ee58808d 6451 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
c03d0b52 6452 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
ee58808d 6453 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
c03d0b52 6454 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
18a9cbbe 6455
e42192b4 6456 drm_update_mso(connector, drm_edid);
18a9cbbe 6457
ce99534e
JN		 6458out:
6459 if (quirks & EDID_QUIRK_NON_DESKTOP) {
66d17ecd
JN		 6460 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Non-desktop display%s\n",
6461 connector->base.id, connector->name,
ce99534e
JN		 6462 info->non_desktop ? " (redundant quirk)" : "");
6463 info->non_desktop = true;
6464 }
6465
aa193f7e
HM		 6466 if (quirks & EDID_QUIRK_CAP_DSC_15BPP)
6467 info->max_dsc_bpp = 15;
6468
170178fe 6469 return quirks;
3b11228b
JB		 6470}
6471
a39ed680 6472static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
80ecb5d7
YB		 6473 struct displayid_detailed_timings_1 *timings,
6474 bool type_7)
a39ed680
DA		 6475{
6476 struct drm_display_mode *mode;
6477 unsigned pixel_clock = (timings->pixel_clock[0] |
6478 (timings->pixel_clock[1] << 8) |
6292b8ef 6479 (timings->pixel_clock[2] << 16)) + 1;
a39ed680
DA		 6480 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
6481 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
6482 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
6483 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
6484 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
6485 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
6486 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
6487 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
6488 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
6489 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
948de842 6490
a39ed680
DA		 6491 mode = drm_mode_create(dev);
6492 if (!mode)
6493 return NULL;
6494
80ecb5d7
YB		 6495 /* resolution is kHz for type VII, and 10 kHz for type I */
6496 mode->clock = type_7 ? pixel_clock : pixel_clock * 10;
a39ed680
DA		 6497 mode->hdisplay = hactive;
6498 mode->hsync_start = mode->hdisplay + hsync;
6499 mode->hsync_end = mode->hsync_start + hsync_width;
6500 mode->htotal = mode->hdisplay + hblank;
6501
6502 mode->vdisplay = vactive;
6503 mode->vsync_start = mode->vdisplay + vsync;
6504 mode->vsync_end = mode->vsync_start + vsync_width;
6505 mode->vtotal = mode->vdisplay + vblank;
6506
6507 mode->flags = 0;
6508 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
6509 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
6510 mode->type = DRM_MODE_TYPE_DRIVER;
6511
6512 if (timings->flags & 0x80)
6513 mode->type |= DRM_MODE_TYPE_PREFERRED;
a39ed680
DA		 6514 drm_mode_set_name(mode);
6515
6516 return mode;
6517}
6518
6519static int add_displayid_detailed_1_modes(struct drm_connector *connector,
43d16d84 6520 const struct displayid_block *block)
a39ed680
DA		 6521{
6522 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
6523 int i;
6524 int num_timings;
6525 struct drm_display_mode *newmode;
6526 int num_modes = 0;
80ecb5d7 6527 bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING;
a39ed680
DA		 6528 /* blocks must be multiple of 20 bytes length */
6529 if (block->num_bytes % 20)
6530 return 0;
6531
6532 num_timings = block->num_bytes / 20;
6533 for (i = 0; i < num_timings; i++) {
6534 struct displayid_detailed_timings_1 *timings = &det->timings[i];
6535
80ecb5d7 6536 newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7);
a39ed680
DA		 6537 if (!newmode)
6538 continue;
6539
6540 drm_mode_probed_add(connector, newmode);
6541 num_modes++;
6542 }
6543 return num_modes;
6544}
6545
6546static int add_displayid_detailed_modes(struct drm_connector *connector,
40f71f5b 6547 const struct drm_edid *drm_edid)
a39ed680 6548{
43d16d84 6549 const struct displayid_block *block;
5ef88dc5 6550 struct displayid_iter iter;
a39ed680
DA		 6551 int num_modes = 0;
6552
d9ba1b4c 6553 displayid_iter_edid_begin(drm_edid, &iter);
5ef88dc5 6554 displayid_iter_for_each(block, &iter) {
80ecb5d7
YB		 6555 if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING ||
6556 block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING)
5ef88dc5 6557 num_modes += add_displayid_detailed_1_modes(connector, block);
a39ed680 6558 }
5ef88dc5 6559 displayid_iter_end(&iter);
7f261afd 6560
a39ed680
DA		 6561 return num_modes;
6562}
6563
b71c0aaa
JN		 6564static int _drm_edid_connector_update(struct drm_connector *connector,
6565 const struct drm_edid *drm_edid)
f453ba04
DA		 6566{
6567 int num_modes = 0;
6568 u32 quirks;
6569
22a27e05 6570 if (!drm_edid) {
d10f7117 6571 drm_reset_display_info(connector);
c945b8c1 6572 clear_eld(connector);
f453ba04
DA		 6573 return 0;
6574 }
f453ba04 6575
0f0f8708
SS		 6576 /*
6577 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
6578 * To avoid multiple parsing of same block, lets parse that map
6579 * from sink info, before parsing CEA modes.
6580 */
e42192b4 6581 quirks = update_display_info(connector, drm_edid);
0f0f8708 6582
e42192b4 6583 /* Depends on info->cea_rev set by update_display_info() above */
a2f9790d 6584 drm_edid_to_eld(connector, drm_edid);
58304630 6585
c867df70
AJ		 6586 /*
6587 * EDID spec says modes should be preferred in this order:
6588 * - preferred detailed mode
6589 * - other detailed modes from base block
6590 * - detailed modes from extension blocks
6591 * - CVT 3-byte code modes
6592 * - standard timing codes
6593 * - established timing codes
6594 * - modes inferred from GTF or CVT range information
6595 *
13931579 6596 * We get this pretty much right.
c867df70
AJ		 6597 *
6598 * XXX order for additional mode types in extension blocks?
6599 */
40f71f5b
JN		 6600 num_modes += add_detailed_modes(connector, drm_edid, quirks);
6601 num_modes += add_cvt_modes(connector, drm_edid);
6602 num_modes += add_standard_modes(connector, drm_edid);
6603 num_modes += add_established_modes(connector, drm_edid);
6604 num_modes += add_cea_modes(connector, drm_edid);
6605 num_modes += add_alternate_cea_modes(connector, drm_edid);
6606 num_modes += add_displayid_detailed_modes(connector, drm_edid);
afd4429e 6607 if (drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ)
40f71f5b 6608 num_modes += add_inferred_modes(connector, drm_edid);
f453ba04
DA		 6609
6610 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
6611 edid_fixup_preferred(connector, quirks);
6612
e10aec65
MK		 6613 if (quirks & EDID_QUIRK_FORCE_6BPC)
6614 connector->display_info.bpc = 6;
6615
49d45a31
RM		 6616 if (quirks & EDID_QUIRK_FORCE_8BPC)
6617 connector->display_info.bpc = 8;
6618
e345da82
MK		 6619 if (quirks & EDID_QUIRK_FORCE_10BPC)
6620 connector->display_info.bpc = 10;
6621
bc5b9641
MK		 6622 if (quirks & EDID_QUIRK_FORCE_12BPC)
6623 connector->display_info.bpc = 12;
6624
f453ba04
DA		 6625 return num_modes;
6626}
f40ab034 6627
a819451e
JN		 6628static void _drm_update_tile_info(struct drm_connector *connector,
6629 const struct drm_edid *drm_edid);
02b16fbc 6630
b71c0aaa 6631static int _drm_edid_connector_property_update(struct drm_connector *connector,
a819451e 6632 const struct drm_edid *drm_edid)
02b16fbc
JN		 6633{
6634 struct drm_device *dev = connector->dev;
02b16fbc 6635 int ret;
02b16fbc 6636
02b16fbc 6637 if (connector->edid_blob_ptr) {
a819451e
JN		 6638 const struct edid *old_edid = connector->edid_blob_ptr->data;
6639
02b16fbc 6640 if (old_edid) {
a819451e 6641 if (!drm_edid_are_equal(drm_edid ? drm_edid->edid : NULL, old_edid)) {
f999b37e
JN		 6642 connector->epoch_counter++;
6643 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID changed, epoch counter %llu\n",
6644 connector->base.id, connector->name,
6645 connector->epoch_counter);
02b16fbc
JN		 6646 }
6647 }
6648 }
6649
02b16fbc
JN		 6650 ret = drm_property_replace_global_blob(dev,
6651 &connector->edid_blob_ptr,
a819451e
JN		 6652 drm_edid ? drm_edid->size : 0,
6653 drm_edid ? drm_edid->edid : NULL,
02b16fbc
JN		 6654 &connector->base,
6655 dev->mode_config.edid_property);
f999b37e
JN		 6656 if (ret) {
6657 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID property update failed (%d)\n",
6658 connector->base.id, connector->name, ret);
6659 goto out;
6660 }
6661
6662 ret = drm_object_property_set_value(&connector->base,
6663 dev->mode_config.non_desktop_property,
6664 connector->display_info.non_desktop);
6665 if (ret) {
6666 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Non-desktop property update failed (%d)\n",
6667 connector->base.id, connector->name, ret);
6668 goto out;
6669 }
6670
6671 ret = drm_connector_set_tile_property(connector);
6672 if (ret) {
6673 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Tile property update failed (%d)\n",
6674 connector->base.id, connector->name, ret);
6675 goto out;
6676 }
6677
6678out:
6679 return ret;
02b16fbc 6680}
a819451e 6681
b71c0aaa
JN		 6682/**
6683 * drm_edid_connector_update - Update connector information from EDID
6684 * @connector: Connector
6685 * @drm_edid: EDID
6686 *
6687 * Update the connector mode list, display info, ELD, HDR metadata, relevant
6688 * properties, etc. from the passed in EDID.
6689 *
6690 * If EDID is NULL, reset the information.
6691 *
6692 * Return: The number of modes added or 0 if we couldn't find any.
6693 */
6694int drm_edid_connector_update(struct drm_connector *connector,
6695 const struct drm_edid *drm_edid)
6696{
6697 int count;
6698
b71c0aaa
JN		 6699 count = _drm_edid_connector_update(connector, drm_edid);
6700
6701 _drm_update_tile_info(connector, drm_edid);
6702
6703 /* Note: Ignore errors for now. */
6704 _drm_edid_connector_property_update(connector, drm_edid);
6705
6706 return count;
6707}
6708EXPORT_SYMBOL(drm_edid_connector_update);
6709
6710static int _drm_connector_update_edid_property(struct drm_connector *connector,
6711 const struct drm_edid *drm_edid)
6712{
b71c0aaa
JN		 6713 /*
6714 * Set the display info, using edid if available, otherwise resetting
6715 * the values to defaults. This duplicates the work done in
6716 * drm_add_edid_modes, but that function is not consistently called
6717 * before this one in all drivers and the computation is cheap enough
6718 * that it seems better to duplicate it rather than attempt to ensure
6719 * some arbitrary ordering of calls.
6720 */
6721 if (drm_edid)
6722 update_display_info(connector, drm_edid);
6723 else
6724 drm_reset_display_info(connector);
6725
6726 _drm_update_tile_info(connector, drm_edid);
6727
6728 return _drm_edid_connector_property_update(connector, drm_edid);
6729}
6730
a819451e
JN		 6731/**
6732 * drm_connector_update_edid_property - update the edid property of a connector
6733 * @connector: drm connector
6734 * @edid: new value of the edid property
6735 *
6736 * This function creates a new blob modeset object and assigns its id to the
6737 * connector's edid property.
6738 * Since we also parse tile information from EDID's displayID block, we also
6739 * set the connector's tile property here. See drm_connector_set_tile_property()
6740 * for more details.
6741 *
b71c0aaa
JN		 6742 * This function is deprecated. Use drm_edid_connector_update() instead.
6743 *
a819451e
JN		 6744 * Returns:
6745 * Zero on success, negative errno on failure.
6746 */
6747int drm_connector_update_edid_property(struct drm_connector *connector,
6748 const struct edid *edid)
6749{
6750 struct drm_edid drm_edid;
6751
6752 return _drm_connector_update_edid_property(connector,
6753 drm_edid_legacy_init(&drm_edid, edid));
6754}
02b16fbc
JN		 6755EXPORT_SYMBOL(drm_connector_update_edid_property);
6756
f40ab034
JN		 6757/**
6758 * drm_add_edid_modes - add modes from EDID data, if available
6759 * @connector: connector we're probing
6760 * @edid: EDID data
6761 *
6762 * Add the specified modes to the connector's mode list. Also fills out the
6763 * &drm_display_info structure and ELD in @connector with any information which
6764 * can be derived from the edid.
6765 *
b71c0aaa
JN		 6766 * This function is deprecated. Use drm_edid_connector_update() instead.
6767 *
f40ab034
JN		 6768 * Return: The number of modes added or 0 if we couldn't find any.
6769 */
6770int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
6771{
22a27e05
JN		 6772 struct drm_edid drm_edid;
6773
f40ab034 6774 if (edid && !drm_edid_is_valid(edid)) {
66d17ecd
JN		 6775 drm_warn(connector->dev, "[CONNECTOR:%d:%s] EDID invalid.\n",
6776 connector->base.id, connector->name);
f40ab034
JN		 6777 edid = NULL;
6778 }
6779
b71c0aaa
JN		 6780 return _drm_edid_connector_update(connector,
6781 drm_edid_legacy_init(&drm_edid, edid));
f40ab034 6782}
f453ba04 6783EXPORT_SYMBOL(drm_add_edid_modes);
f0fda0a4
ZY		 6784
6785/**
6786 * drm_add_modes_noedid - add modes for the connectors without EDID
6787 * @connector: connector we're probing
6788 * @hdisplay: the horizontal display limit
6789 * @vdisplay: the vertical display limit
6790 *
6791 * Add the specified modes to the connector's mode list. Only when the
6792 * hdisplay/vdisplay is not beyond the given limit, it will be added.
6793 *
db6cf833 6794 * Return: The number of modes added or 0 if we couldn't find any.
f0fda0a4
ZY		 6795 */
6796int drm_add_modes_noedid(struct drm_connector *connector,
6797 int hdisplay, int vdisplay)
6798{
6799 int i, count, num_modes = 0;
b1f559ec 6800 struct drm_display_mode *mode;
f0fda0a4
ZY		 6801 struct drm_device *dev = connector->dev;
6802
fbb40b28 6803 count = ARRAY_SIZE(drm_dmt_modes);
f0fda0a4
ZY		 6804 if (hdisplay < 0)
6805 hdisplay = 0;
6806 if (vdisplay < 0)
6807 vdisplay = 0;
6808
6809 for (i = 0; i < count; i++) {
b1f559ec 6810 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
948de842 6811
f0fda0a4
ZY		 6812 if (hdisplay && vdisplay) {
6813 /*
6814 * Only when two are valid, they will be used to check
6815 * whether the mode should be added to the mode list of
6816 * the connector.
6817 */
6818 if (ptr->hdisplay > hdisplay ||
6819 ptr->vdisplay > vdisplay)
6820 continue;
6821 }
f985dedb
AJ		 6822 if (drm_mode_vrefresh(ptr) > 61)
6823 continue;
f0fda0a4
ZY		 6824 mode = drm_mode_duplicate(dev, ptr);
6825 if (mode) {
6826 drm_mode_probed_add(connector, mode);
6827 num_modes++;
6828 }
6829 }
6830 return num_modes;
6831}
6832EXPORT_SYMBOL(drm_add_modes_noedid);
10a85120 6833
db6cf833
TR		 6834/**
6835 * drm_set_preferred_mode - Sets the preferred mode of a connector
6836 * @connector: connector whose mode list should be processed
6837 * @hpref: horizontal resolution of preferred mode
6838 * @vpref: vertical resolution of preferred mode
6839 *
6840 * Marks a mode as preferred if it matches the resolution specified by @hpref
6841 * and @vpref.
6842 */
3cf70daf
GH		 6843void drm_set_preferred_mode(struct drm_connector *connector,
6844 int hpref, int vpref)
6845{
6846 struct drm_display_mode *mode;
6847
6848 list_for_each_entry(mode, &connector->probed_modes, head) {
db6cf833 6849 if (mode->hdisplay == hpref &&
9d3de138 6850 mode->vdisplay == vpref)
3cf70daf
GH		 6851 mode->type |= DRM_MODE_TYPE_PREFERRED;
6852 }
6853}
6854EXPORT_SYMBOL(drm_set_preferred_mode);
6855
192a3aa0 6856static bool is_hdmi2_sink(const struct drm_connector *connector)
13d0add3
VS		 6857{
6858 /*
6859 * FIXME: sil-sii8620 doesn't have a connector around when
6860 * we need one, so we have to be prepared for a NULL connector.
6861 */
6862 if (!connector)
6863 return true;
6864
6865 return connector->display_info.hdmi.scdc.supported ||
c03d0b52 6866 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR420;
13d0add3
VS		 6867}
6868
192a3aa0 6869static u8 drm_mode_hdmi_vic(const struct drm_connector *connector,
949561eb
VS		 6870 const struct drm_display_mode *mode)
6871{
6872 bool has_hdmi_infoframe = connector ?
6873 connector->display_info.has_hdmi_infoframe : false;
6874
6875 if (!has_hdmi_infoframe)
6876 return 0;
6877
6878 /* No HDMI VIC when signalling 3D video format */
6879 if (mode->flags & DRM_MODE_FLAG_3D_MASK)
6880 return 0;
6881
6882 return drm_match_hdmi_mode(mode);
6883}
6884
192a3aa0 6885static u8 drm_mode_cea_vic(const struct drm_connector *connector,
cfd6f8c3
VS		 6886 const struct drm_display_mode *mode)
6887{
cfd6f8c3
VS		 6888 u8 vic;
6889
6890 /*
6891 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
6892 * we should send its VIC in vendor infoframes, else send the
6893 * VIC in AVI infoframes. Lets check if this mode is present in
6894 * HDMI 1.4b 4K modes
6895 */
949561eb 6896 if (drm_mode_hdmi_vic(connector, mode))
cfd6f8c3
VS		 6897 return 0;
6898
6899 vic = drm_match_cea_mode(mode);
6900
6901 /*
6902 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
6903 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
6904 * have to make sure we dont break HDMI 1.4 sinks.
6905 */
6906 if (!is_hdmi2_sink(connector) && vic > 64)
6907 return 0;
6908
6909 return vic;
6910}
6911
10a85120
TR		 6912/**
6913 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
6914 * data from a DRM display mode
6915 * @frame: HDMI AVI infoframe
13d0add3 6916 * @connector: the connector
10a85120
TR		 6917 * @mode: DRM display mode
6918 *
db6cf833 6919 * Return: 0 on success or a negative error code on failure.
10a85120
TR		 6920 */
6921int
6922drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
192a3aa0 6923 const struct drm_connector *connector,
13d0add3 6924 const struct drm_display_mode *mode)
10a85120 6925{
a9c266c2 6926 enum hdmi_picture_aspect picture_aspect;
d2b43473 6927 u8 vic, hdmi_vic;
10a85120
TR		 6928
6929 if (!frame || !mode)
6930 return -EINVAL;
6931
5ee0caf1 6932 hdmi_avi_infoframe_init(frame);
10a85120 6933
bf02db99
DL		 6934 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
6935 frame->pixel_repeat = 1;
6936
d2b43473
WL		 6937 vic = drm_mode_cea_vic(connector, mode);
6938 hdmi_vic = drm_mode_hdmi_vic(connector, mode);
0c1f528c 6939
10a85120 6940 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
0967e6a5 6941
50525c33
SL		 6942 /*
6943 * As some drivers don't support atomic, we can't use connector state.
6944 * So just initialize the frame with default values, just the same way
6945 * as it's done with other properties here.
6946 */
6947 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
6948 frame->itc = 0;
6949
69ab6d35
VK		 6950 /*
6951 * Populate picture aspect ratio from either
d2b43473 6952 * user input (if specified) or from the CEA/HDMI mode lists.
69ab6d35 6953 */
a9c266c2 6954 picture_aspect = mode->picture_aspect_ratio;
d2b43473
WL		 6955 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) {
6956 if (vic)
6957 picture_aspect = drm_get_cea_aspect_ratio(vic);
6958 else if (hdmi_vic)
6959 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic);
6960 }
0967e6a5 6961
a9c266c2
VS		 6962 /*
6963 * The infoframe can't convey anything but none, 4:3
6964 * and 16:9, so if the user has asked for anything else
6965 * we can only satisfy it by specifying the right VIC.
6966 */
6967 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
d2b43473
WL		 6968 if (vic) {
6969 if (picture_aspect != drm_get_cea_aspect_ratio(vic))
6970 return -EINVAL;
6971 } else if (hdmi_vic) {
6972 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic))
6973 return -EINVAL;
6974 } else {
a9c266c2 6975 return -EINVAL;
d2b43473
WL		 6976 }
6977
a9c266c2
VS		 6978 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
6979 }
6980
d2b43473 6981 frame->video_code = vic;
a9c266c2 6982 frame->picture_aspect = picture_aspect;
10a85120 6983 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
24d01805 6984 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
10a85120
TR		 6985
6986 return 0;
6987}
6988EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
83dd0008 6989
a2ce26f8
VS		 6990/**
6991 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
6992 * quantization range information
6993 * @frame: HDMI AVI infoframe
13d0add3 6994 * @connector: the connector
779c4c28 6995 * @mode: DRM display mode
a2ce26f8 6996 * @rgb_quant_range: RGB quantization range (Q)
a2ce26f8
VS		 6997 */
6998void
6999drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
192a3aa0 7000 const struct drm_connector *connector,
779c4c28 7001 const struct drm_display_mode *mode,
1581b2df 7002 enum hdmi_quantization_range rgb_quant_range)
a2ce26f8 7003{
1581b2df
VS		 7004 const struct drm_display_info *info = &connector->display_info;
7005
a2ce26f8
VS		 7006 /*
7007 * CEA-861:
7008 * "A Source shall not send a non-zero Q value that does not correspond
7009 * to the default RGB Quantization Range for the transmitted Picture
7010 * unless the Sink indicates support for the Q bit in a Video
7011 * Capabilities Data Block."
779c4c28
VS		 7012 *
7013 * HDMI 2.0 recommends sending non-zero Q when it does match the
7014 * default RGB quantization range for the mode, even when QS=0.
a2ce26f8 7015 */
1581b2df 7016 if (info->rgb_quant_range_selectable ||
779c4c28 7017 rgb_quant_range == drm_default_rgb_quant_range(mode))
a2ce26f8
VS		 7018 frame->quantization_range = rgb_quant_range;
7019 else
7020 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
fcc8a22c
VS		 7021
7022 /*
7023 * CEA-861-F:
7024 * "When transmitting any RGB colorimetry, the Source should set the
7025 * YQ-field to match the RGB Quantization Range being transmitted
7026 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
7027 * set YQ=1) and the Sink shall ignore the YQ-field."
9271c0ca
VS		 7028 *
7029 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
7030 * by non-zero YQ when receiving RGB. There doesn't seem to be any
7031 * good way to tell which version of CEA-861 the sink supports, so
7032 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
96c92551 7033 * on CEA-861-F.
fcc8a22c 7034 */
13d0add3 7035 if (!is_hdmi2_sink(connector) ||
9271c0ca 7036 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
fcc8a22c
VS		 7037 frame->ycc_quantization_range =
7038 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
7039 else
7040 frame->ycc_quantization_range =
7041 HDMI_YCC_QUANTIZATION_RANGE_FULL;
a2ce26f8
VS		 7042}
7043EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
7044
4eed4a0a
DL		 7045static enum hdmi_3d_structure
7046s3d_structure_from_display_mode(const struct drm_display_mode *mode)
7047{
7048 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
7049
7050 switch (layout) {
7051 case DRM_MODE_FLAG_3D_FRAME_PACKING:
7052 return HDMI_3D_STRUCTURE_FRAME_PACKING;
7053 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
7054 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
7055 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
7056 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
7057 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
7058 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
7059 case DRM_MODE_FLAG_3D_L_DEPTH:
7060 return HDMI_3D_STRUCTURE_L_DEPTH;
7061 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
7062 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
7063 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
7064 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
7065 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
7066 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
7067 default:
7068 return HDMI_3D_STRUCTURE_INVALID;
7069 }
7070}
7071
83dd0008
LD		 7072/**
7073 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
7074 * data from a DRM display mode
7075 * @frame: HDMI vendor infoframe
f1781e9b 7076 * @connector: the connector
83dd0008
LD		 7077 * @mode: DRM display mode
7078 *
7079 * Note that there's is a need to send HDMI vendor infoframes only when using a
7080 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
7081 * function will return -EINVAL, error that can be safely ignored.
7082 *
db6cf833 7083 * Return: 0 on success or a negative error code on failure.
83dd0008
LD		 7084 */
7085int
7086drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
192a3aa0 7087 const struct drm_connector *connector,
83dd0008
LD		 7088 const struct drm_display_mode *mode)
7089{
f1781e9b
VS		 7090 /*
7091 * FIXME: sil-sii8620 doesn't have a connector around when
7092 * we need one, so we have to be prepared for a NULL connector.
7093 */
7094 bool has_hdmi_infoframe = connector ?
7095 connector->display_info.has_hdmi_infoframe : false;
83dd0008 7096 int err;
83dd0008
LD		 7097
7098 if (!frame || !mode)
7099 return -EINVAL;
7100
f1781e9b
VS		 7101 if (!has_hdmi_infoframe)
7102 return -EINVAL;
7103
949561eb
VS		 7104 err = hdmi_vendor_infoframe_init(frame);
7105 if (err < 0)
7106 return err;
4eed4a0a 7107
f1781e9b
VS		 7108 /*
7109 * Even if it's not absolutely necessary to send the infoframe
7110 * (ie.vic==0 and s3d_struct==0) we will still send it if we
7111 * know that the sink can handle it. This is based on a
7112 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
0ae865ef 7113 * have trouble realizing that they should switch from 3D to 2D
f1781e9b
VS		 7114 * mode if the source simply stops sending the infoframe when
7115 * it wants to switch from 3D to 2D.
7116 */
949561eb 7117 frame->vic = drm_mode_hdmi_vic(connector, mode);
f1781e9b 7118 frame->s3d_struct = s3d_structure_from_display_mode(mode);
83dd0008
LD		 7119
7120 return 0;
7121}
7122EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
40d9b043 7123
7f261afd
VS		 7124static void drm_parse_tiled_block(struct drm_connector *connector,
7125 const struct displayid_block *block)
5e546cd5 7126{
092c367a 7127 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
5e546cd5
DA		 7128 u16 w, h;
7129 u8 tile_v_loc, tile_h_loc;
7130 u8 num_v_tile, num_h_tile;
7131 struct drm_tile_group *tg;
7132
7133 w = tile->tile_size[0] | tile->tile_size[1] << 8;
7134 h = tile->tile_size[2] | tile->tile_size[3] << 8;
7135
7136 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
7137 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
7138 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
7139 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
7140
7141 connector->has_tile = true;
7142 if (tile->tile_cap & 0x80)
7143 connector->tile_is_single_monitor = true;
7144
7145 connector->num_h_tile = num_h_tile + 1;
7146 connector->num_v_tile = num_v_tile + 1;
7147 connector->tile_h_loc = tile_h_loc;
7148 connector->tile_v_loc = tile_v_loc;
7149 connector->tile_h_size = w + 1;
7150 connector->tile_v_size = h + 1;
7151
e1e7bc48
JN		 7152 drm_dbg_kms(connector->dev,
7153 "[CONNECTOR:%d:%s] tile cap 0x%x, size %dx%d, num tiles %dx%d, location %dx%d, vend %c%c%c",
7154 connector->base.id, connector->name,
7155 tile->tile_cap,
7156 connector->tile_h_size, connector->tile_v_size,
7157 connector->num_h_tile, connector->num_v_tile,
7158 connector->tile_h_loc, connector->tile_v_loc,
7159 tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
5e546cd5
DA		 7160
7161 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
392f9fcb 7162 if (!tg)
5e546cd5 7163 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
5e546cd5 7164 if (!tg)
7f261afd 7165 return;
5e546cd5
DA		 7166
7167 if (connector->tile_group != tg) {
7168 /* if we haven't got a pointer,
7169 take the reference, drop ref to old tile group */
392f9fcb 7170 if (connector->tile_group)
5e546cd5 7171 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5e546cd5 7172 connector->tile_group = tg;
392f9fcb 7173 } else {
5e546cd5
DA		 7174 /* if same tile group, then release the ref we just took. */
7175 drm_mode_put_tile_group(connector->dev, tg);
392f9fcb 7176 }
5e546cd5
DA		 7177}
7178
c7b2dee4
JN		 7179static void _drm_update_tile_info(struct drm_connector *connector,
7180 const struct drm_edid *drm_edid)
40d9b043 7181{
bfd4e192
JN		 7182 const struct displayid_block *block;
7183 struct displayid_iter iter;
36881184 7184
40d9b043 7185 connector->has_tile = false;
7f261afd 7186
d9ba1b4c 7187 displayid_iter_edid_begin(drm_edid, &iter);
bfd4e192
JN		 7188 displayid_iter_for_each(block, &iter) {
7189 if (block->tag == DATA_BLOCK_TILED_DISPLAY)
7190 drm_parse_tiled_block(connector, block);
40d9b043 7191 }
bfd4e192 7192 displayid_iter_end(&iter);
40d9b043 7193
7f261afd 7194 if (!connector->has_tile && connector->tile_group) {
40d9b043
DA		 7195 drm_mode_put_tile_group(connector->dev, connector->tile_group);
7196 connector->tile_group = NULL;
7197 }
40d9b043 7198}
Linux 6.x block layer and io_uring tree(s)