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f453ba04 DA |
1 | /* |
2 | * Copyright (c) 2006 Luc Verhaegen (quirks list) | |
3 | * Copyright (c) 2007-2008 Intel Corporation | |
4 | * Jesse Barnes <jesse.barnes@intel.com> | |
61e57a8d | 5 | * Copyright 2010 Red Hat, Inc. |
f453ba04 DA |
6 | * |
7 | * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from | |
8 | * FB layer. | |
9 | * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> | |
10 | * | |
11 | * Permission is hereby granted, free of charge, to any person obtaining a | |
12 | * copy of this software and associated documentation files (the "Software"), | |
13 | * to deal in the Software without restriction, including without limitation | |
14 | * the rights to use, copy, modify, merge, publish, distribute, sub license, | |
15 | * and/or sell copies of the Software, and to permit persons to whom the | |
16 | * Software is furnished to do so, subject to the following conditions: | |
17 | * | |
18 | * The above copyright notice and this permission notice (including the | |
19 | * next paragraph) shall be included in all copies or substantial portions | |
20 | * of the Software. | |
21 | * | |
22 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
23 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
24 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
25 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
26 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
27 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
28 | * DEALINGS IN THE SOFTWARE. | |
29 | */ | |
30 | #include <linux/kernel.h> | |
5a0e3ad6 | 31 | #include <linux/slab.h> |
10a85120 | 32 | #include <linux/hdmi.h> |
f453ba04 | 33 | #include <linux/i2c.h> |
47819ba2 | 34 | #include <linux/module.h> |
760285e7 DH |
35 | #include <drm/drmP.h> |
36 | #include <drm/drm_edid.h> | |
f453ba04 | 37 | |
13931579 AJ |
38 | #define version_greater(edid, maj, min) \ |
39 | (((edid)->version > (maj)) || \ | |
40 | ((edid)->version == (maj) && (edid)->revision > (min))) | |
f453ba04 | 41 | |
d1ff6409 AJ |
42 | #define EDID_EST_TIMINGS 16 |
43 | #define EDID_STD_TIMINGS 8 | |
44 | #define EDID_DETAILED_TIMINGS 4 | |
f453ba04 DA |
45 | |
46 | /* | |
47 | * EDID blocks out in the wild have a variety of bugs, try to collect | |
48 | * them here (note that userspace may work around broken monitors first, | |
49 | * but fixes should make their way here so that the kernel "just works" | |
50 | * on as many displays as possible). | |
51 | */ | |
52 | ||
53 | /* First detailed mode wrong, use largest 60Hz mode */ | |
54 | #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) | |
55 | /* Reported 135MHz pixel clock is too high, needs adjustment */ | |
56 | #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) | |
57 | /* Prefer the largest mode at 75 Hz */ | |
58 | #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) | |
59 | /* Detail timing is in cm not mm */ | |
60 | #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) | |
61 | /* Detailed timing descriptors have bogus size values, so just take the | |
62 | * maximum size and use that. | |
63 | */ | |
64 | #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) | |
65 | /* Monitor forgot to set the first detailed is preferred bit. */ | |
66 | #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5) | |
67 | /* use +hsync +vsync for detailed mode */ | |
68 | #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) | |
bc42aabc AJ |
69 | /* Force reduced-blanking timings for detailed modes */ |
70 | #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) | |
49d45a31 RM |
71 | /* Force 8bpc */ |
72 | #define EDID_QUIRK_FORCE_8BPC (1 << 8) | |
bc5b9641 MK |
73 | /* Force 12bpc */ |
74 | #define EDID_QUIRK_FORCE_12BPC (1 << 9) | |
3c537889 | 75 | |
13931579 AJ |
76 | struct detailed_mode_closure { |
77 | struct drm_connector *connector; | |
78 | struct edid *edid; | |
79 | bool preferred; | |
80 | u32 quirks; | |
81 | int modes; | |
82 | }; | |
f453ba04 | 83 | |
5c61259e ZY |
84 | #define LEVEL_DMT 0 |
85 | #define LEVEL_GTF 1 | |
7a374350 AJ |
86 | #define LEVEL_GTF2 2 |
87 | #define LEVEL_CVT 3 | |
5c61259e | 88 | |
f453ba04 | 89 | static struct edid_quirk { |
c51a3fd6 | 90 | char vendor[4]; |
f453ba04 DA |
91 | int product_id; |
92 | u32 quirks; | |
93 | } edid_quirk_list[] = { | |
94 | /* Acer AL1706 */ | |
95 | { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, | |
96 | /* Acer F51 */ | |
97 | { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, | |
98 | /* Unknown Acer */ | |
99 | { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, | |
100 | ||
101 | /* Belinea 10 15 55 */ | |
102 | { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, | |
103 | { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, | |
104 | ||
105 | /* Envision Peripherals, Inc. EN-7100e */ | |
106 | { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, | |
ba1163de AJ |
107 | /* Envision EN2028 */ |
108 | { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, | |
f453ba04 DA |
109 | |
110 | /* Funai Electronics PM36B */ | |
111 | { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | | |
112 | EDID_QUIRK_DETAILED_IN_CM }, | |
113 | ||
114 | /* LG Philips LCD LP154W01-A5 */ | |
115 | { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, | |
116 | { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, | |
117 | ||
118 | /* Philips 107p5 CRT */ | |
119 | { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, | |
120 | ||
121 | /* Proview AY765C */ | |
122 | { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, | |
123 | ||
124 | /* Samsung SyncMaster 205BW. Note: irony */ | |
125 | { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, | |
126 | /* Samsung SyncMaster 22[5-6]BW */ | |
127 | { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, | |
128 | { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, | |
bc42aabc | 129 | |
bc5b9641 MK |
130 | /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ |
131 | { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC }, | |
132 | ||
bc42aabc AJ |
133 | /* ViewSonic VA2026w */ |
134 | { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, | |
118bdbd8 AD |
135 | |
136 | /* Medion MD 30217 PG */ | |
137 | { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, | |
49d45a31 RM |
138 | |
139 | /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ | |
140 | { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, | |
f453ba04 DA |
141 | }; |
142 | ||
a6b21831 TR |
143 | /* |
144 | * Autogenerated from the DMT spec. | |
145 | * This table is copied from xfree86/modes/xf86EdidModes.c. | |
146 | */ | |
147 | static const struct drm_display_mode drm_dmt_modes[] = { | |
148 | /* 640x350@85Hz */ | |
149 | { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, | |
150 | 736, 832, 0, 350, 382, 385, 445, 0, | |
151 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
152 | /* 640x400@85Hz */ | |
153 | { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, | |
154 | 736, 832, 0, 400, 401, 404, 445, 0, | |
155 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
156 | /* 720x400@85Hz */ | |
157 | { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, | |
158 | 828, 936, 0, 400, 401, 404, 446, 0, | |
159 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
160 | /* 640x480@60Hz */ | |
161 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, | |
162 | 752, 800, 0, 480, 489, 492, 525, 0, | |
163 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
164 | /* 640x480@72Hz */ | |
165 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, | |
166 | 704, 832, 0, 480, 489, 492, 520, 0, | |
167 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
168 | /* 640x480@75Hz */ | |
169 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, | |
170 | 720, 840, 0, 480, 481, 484, 500, 0, | |
171 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
172 | /* 640x480@85Hz */ | |
173 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, | |
174 | 752, 832, 0, 480, 481, 484, 509, 0, | |
175 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
176 | /* 800x600@56Hz */ | |
177 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, | |
178 | 896, 1024, 0, 600, 601, 603, 625, 0, | |
179 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
180 | /* 800x600@60Hz */ | |
181 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, | |
182 | 968, 1056, 0, 600, 601, 605, 628, 0, | |
183 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
184 | /* 800x600@72Hz */ | |
185 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, | |
186 | 976, 1040, 0, 600, 637, 643, 666, 0, | |
187 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
188 | /* 800x600@75Hz */ | |
189 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, | |
190 | 896, 1056, 0, 600, 601, 604, 625, 0, | |
191 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
192 | /* 800x600@85Hz */ | |
193 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, | |
194 | 896, 1048, 0, 600, 601, 604, 631, 0, | |
195 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
196 | /* 800x600@120Hz RB */ | |
197 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, | |
198 | 880, 960, 0, 600, 603, 607, 636, 0, | |
199 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
200 | /* 848x480@60Hz */ | |
201 | { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, | |
202 | 976, 1088, 0, 480, 486, 494, 517, 0, | |
203 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
204 | /* 1024x768@43Hz, interlace */ | |
205 | { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, | |
206 | 1208, 1264, 0, 768, 768, 772, 817, 0, | |
207 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | | |
208 | DRM_MODE_FLAG_INTERLACE) }, | |
209 | /* 1024x768@60Hz */ | |
210 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, | |
211 | 1184, 1344, 0, 768, 771, 777, 806, 0, | |
212 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
213 | /* 1024x768@70Hz */ | |
214 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, | |
215 | 1184, 1328, 0, 768, 771, 777, 806, 0, | |
216 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
217 | /* 1024x768@75Hz */ | |
218 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, | |
219 | 1136, 1312, 0, 768, 769, 772, 800, 0, | |
220 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
221 | /* 1024x768@85Hz */ | |
222 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, | |
223 | 1168, 1376, 0, 768, 769, 772, 808, 0, | |
224 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
225 | /* 1024x768@120Hz RB */ | |
226 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, | |
227 | 1104, 1184, 0, 768, 771, 775, 813, 0, | |
228 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
229 | /* 1152x864@75Hz */ | |
230 | { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, | |
231 | 1344, 1600, 0, 864, 865, 868, 900, 0, | |
232 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
233 | /* 1280x768@60Hz RB */ | |
234 | { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, | |
235 | 1360, 1440, 0, 768, 771, 778, 790, 0, | |
236 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
237 | /* 1280x768@60Hz */ | |
238 | { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, | |
239 | 1472, 1664, 0, 768, 771, 778, 798, 0, | |
240 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
241 | /* 1280x768@75Hz */ | |
242 | { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, | |
243 | 1488, 1696, 0, 768, 771, 778, 805, 0, | |
244 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
245 | /* 1280x768@85Hz */ | |
246 | { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, | |
247 | 1496, 1712, 0, 768, 771, 778, 809, 0, | |
248 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
249 | /* 1280x768@120Hz RB */ | |
250 | { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, | |
251 | 1360, 1440, 0, 768, 771, 778, 813, 0, | |
252 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
253 | /* 1280x800@60Hz RB */ | |
254 | { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, | |
255 | 1360, 1440, 0, 800, 803, 809, 823, 0, | |
256 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
257 | /* 1280x800@60Hz */ | |
258 | { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, | |
259 | 1480, 1680, 0, 800, 803, 809, 831, 0, | |
260 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
261 | /* 1280x800@75Hz */ | |
262 | { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, | |
263 | 1488, 1696, 0, 800, 803, 809, 838, 0, | |
264 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
265 | /* 1280x800@85Hz */ | |
266 | { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, | |
267 | 1496, 1712, 0, 800, 803, 809, 843, 0, | |
268 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
269 | /* 1280x800@120Hz RB */ | |
270 | { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, | |
271 | 1360, 1440, 0, 800, 803, 809, 847, 0, | |
272 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
273 | /* 1280x960@60Hz */ | |
274 | { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, | |
275 | 1488, 1800, 0, 960, 961, 964, 1000, 0, | |
276 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
277 | /* 1280x960@85Hz */ | |
278 | { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, | |
279 | 1504, 1728, 0, 960, 961, 964, 1011, 0, | |
280 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
281 | /* 1280x960@120Hz RB */ | |
282 | { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, | |
283 | 1360, 1440, 0, 960, 963, 967, 1017, 0, | |
284 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
285 | /* 1280x1024@60Hz */ | |
286 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, | |
287 | 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, | |
288 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
289 | /* 1280x1024@75Hz */ | |
290 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, | |
291 | 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, | |
292 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
293 | /* 1280x1024@85Hz */ | |
294 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, | |
295 | 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, | |
296 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
297 | /* 1280x1024@120Hz RB */ | |
298 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, | |
299 | 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, | |
300 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
301 | /* 1360x768@60Hz */ | |
302 | { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, | |
303 | 1536, 1792, 0, 768, 771, 777, 795, 0, | |
304 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
305 | /* 1360x768@120Hz RB */ | |
306 | { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, | |
307 | 1440, 1520, 0, 768, 771, 776, 813, 0, | |
308 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
309 | /* 1400x1050@60Hz RB */ | |
310 | { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, | |
311 | 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, | |
312 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
313 | /* 1400x1050@60Hz */ | |
314 | { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, | |
315 | 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, | |
316 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
317 | /* 1400x1050@75Hz */ | |
318 | { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, | |
319 | 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, | |
320 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
321 | /* 1400x1050@85Hz */ | |
322 | { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, | |
323 | 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, | |
324 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
325 | /* 1400x1050@120Hz RB */ | |
326 | { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, | |
327 | 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, | |
328 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
329 | /* 1440x900@60Hz RB */ | |
330 | { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, | |
331 | 1520, 1600, 0, 900, 903, 909, 926, 0, | |
332 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
333 | /* 1440x900@60Hz */ | |
334 | { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, | |
335 | 1672, 1904, 0, 900, 903, 909, 934, 0, | |
336 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
337 | /* 1440x900@75Hz */ | |
338 | { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, | |
339 | 1688, 1936, 0, 900, 903, 909, 942, 0, | |
340 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
341 | /* 1440x900@85Hz */ | |
342 | { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, | |
343 | 1696, 1952, 0, 900, 903, 909, 948, 0, | |
344 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
345 | /* 1440x900@120Hz RB */ | |
346 | { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, | |
347 | 1520, 1600, 0, 900, 903, 909, 953, 0, | |
348 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
349 | /* 1600x1200@60Hz */ | |
350 | { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, | |
351 | 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, | |
352 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
353 | /* 1600x1200@65Hz */ | |
354 | { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, | |
355 | 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, | |
356 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
357 | /* 1600x1200@70Hz */ | |
358 | { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, | |
359 | 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, | |
360 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
361 | /* 1600x1200@75Hz */ | |
362 | { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, | |
363 | 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, | |
364 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
365 | /* 1600x1200@85Hz */ | |
366 | { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, | |
367 | 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, | |
368 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
369 | /* 1600x1200@120Hz RB */ | |
370 | { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, | |
371 | 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, | |
372 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
373 | /* 1680x1050@60Hz RB */ | |
374 | { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, | |
375 | 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, | |
376 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
377 | /* 1680x1050@60Hz */ | |
378 | { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, | |
379 | 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, | |
380 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
381 | /* 1680x1050@75Hz */ | |
382 | { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, | |
383 | 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, | |
384 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
385 | /* 1680x1050@85Hz */ | |
386 | { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, | |
387 | 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, | |
388 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
389 | /* 1680x1050@120Hz RB */ | |
390 | { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, | |
391 | 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, | |
392 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
393 | /* 1792x1344@60Hz */ | |
394 | { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, | |
395 | 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, | |
396 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
397 | /* 1792x1344@75Hz */ | |
398 | { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, | |
399 | 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, | |
400 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
401 | /* 1792x1344@120Hz RB */ | |
402 | { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, | |
403 | 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, | |
404 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
405 | /* 1856x1392@60Hz */ | |
406 | { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, | |
407 | 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, | |
408 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
409 | /* 1856x1392@75Hz */ | |
410 | { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, | |
411 | 2208, 2560, 0, 1392, 1395, 1399, 1500, 0, | |
412 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
413 | /* 1856x1392@120Hz RB */ | |
414 | { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, | |
415 | 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, | |
416 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
417 | /* 1920x1200@60Hz RB */ | |
418 | { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, | |
419 | 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, | |
420 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
421 | /* 1920x1200@60Hz */ | |
422 | { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, | |
423 | 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, | |
424 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
425 | /* 1920x1200@75Hz */ | |
426 | { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, | |
427 | 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, | |
428 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
429 | /* 1920x1200@85Hz */ | |
430 | { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, | |
431 | 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, | |
432 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
433 | /* 1920x1200@120Hz RB */ | |
434 | { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, | |
435 | 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, | |
436 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
437 | /* 1920x1440@60Hz */ | |
438 | { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, | |
439 | 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, | |
440 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
441 | /* 1920x1440@75Hz */ | |
442 | { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, | |
443 | 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, | |
444 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
445 | /* 1920x1440@120Hz RB */ | |
446 | { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, | |
447 | 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, | |
448 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
449 | /* 2560x1600@60Hz RB */ | |
450 | { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, | |
451 | 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, | |
452 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
453 | /* 2560x1600@60Hz */ | |
454 | { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, | |
455 | 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, | |
456 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
457 | /* 2560x1600@75HZ */ | |
458 | { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, | |
459 | 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, | |
460 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
461 | /* 2560x1600@85HZ */ | |
462 | { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, | |
463 | 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, | |
464 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
465 | /* 2560x1600@120Hz RB */ | |
466 | { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, | |
467 | 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, | |
468 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
469 | }; | |
470 | ||
e7bfa5c4 VS |
471 | /* |
472 | * These more or less come from the DMT spec. The 720x400 modes are | |
473 | * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 | |
474 | * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode | |
475 | * should be 1152x870, again for the Mac, but instead we use the x864 DMT | |
476 | * mode. | |
477 | * | |
478 | * The DMT modes have been fact-checked; the rest are mild guesses. | |
479 | */ | |
a6b21831 TR |
480 | static const struct drm_display_mode edid_est_modes[] = { |
481 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, | |
482 | 968, 1056, 0, 600, 601, 605, 628, 0, | |
483 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ | |
484 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, | |
485 | 896, 1024, 0, 600, 601, 603, 625, 0, | |
486 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ | |
487 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, | |
488 | 720, 840, 0, 480, 481, 484, 500, 0, | |
489 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ | |
490 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, | |
491 | 704, 832, 0, 480, 489, 491, 520, 0, | |
492 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ | |
493 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, | |
494 | 768, 864, 0, 480, 483, 486, 525, 0, | |
495 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ | |
496 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25200, 640, 656, | |
497 | 752, 800, 0, 480, 490, 492, 525, 0, | |
498 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ | |
499 | { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, | |
500 | 846, 900, 0, 400, 421, 423, 449, 0, | |
501 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ | |
502 | { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, | |
503 | 846, 900, 0, 400, 412, 414, 449, 0, | |
504 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ | |
505 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, | |
506 | 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, | |
507 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ | |
508 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78800, 1024, 1040, | |
509 | 1136, 1312, 0, 768, 769, 772, 800, 0, | |
510 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ | |
511 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, | |
512 | 1184, 1328, 0, 768, 771, 777, 806, 0, | |
513 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ | |
514 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, | |
515 | 1184, 1344, 0, 768, 771, 777, 806, 0, | |
516 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ | |
517 | { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, | |
518 | 1208, 1264, 0, 768, 768, 776, 817, 0, | |
519 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ | |
520 | { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, | |
521 | 928, 1152, 0, 624, 625, 628, 667, 0, | |
522 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ | |
523 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, | |
524 | 896, 1056, 0, 600, 601, 604, 625, 0, | |
525 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ | |
526 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, | |
527 | 976, 1040, 0, 600, 637, 643, 666, 0, | |
528 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ | |
529 | { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, | |
530 | 1344, 1600, 0, 864, 865, 868, 900, 0, | |
531 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ | |
532 | }; | |
533 | ||
534 | struct minimode { | |
535 | short w; | |
536 | short h; | |
537 | short r; | |
538 | short rb; | |
539 | }; | |
540 | ||
541 | static const struct minimode est3_modes[] = { | |
542 | /* byte 6 */ | |
543 | { 640, 350, 85, 0 }, | |
544 | { 640, 400, 85, 0 }, | |
545 | { 720, 400, 85, 0 }, | |
546 | { 640, 480, 85, 0 }, | |
547 | { 848, 480, 60, 0 }, | |
548 | { 800, 600, 85, 0 }, | |
549 | { 1024, 768, 85, 0 }, | |
550 | { 1152, 864, 75, 0 }, | |
551 | /* byte 7 */ | |
552 | { 1280, 768, 60, 1 }, | |
553 | { 1280, 768, 60, 0 }, | |
554 | { 1280, 768, 75, 0 }, | |
555 | { 1280, 768, 85, 0 }, | |
556 | { 1280, 960, 60, 0 }, | |
557 | { 1280, 960, 85, 0 }, | |
558 | { 1280, 1024, 60, 0 }, | |
559 | { 1280, 1024, 85, 0 }, | |
560 | /* byte 8 */ | |
561 | { 1360, 768, 60, 0 }, | |
562 | { 1440, 900, 60, 1 }, | |
563 | { 1440, 900, 60, 0 }, | |
564 | { 1440, 900, 75, 0 }, | |
565 | { 1440, 900, 85, 0 }, | |
566 | { 1400, 1050, 60, 1 }, | |
567 | { 1400, 1050, 60, 0 }, | |
568 | { 1400, 1050, 75, 0 }, | |
569 | /* byte 9 */ | |
570 | { 1400, 1050, 85, 0 }, | |
571 | { 1680, 1050, 60, 1 }, | |
572 | { 1680, 1050, 60, 0 }, | |
573 | { 1680, 1050, 75, 0 }, | |
574 | { 1680, 1050, 85, 0 }, | |
575 | { 1600, 1200, 60, 0 }, | |
576 | { 1600, 1200, 65, 0 }, | |
577 | { 1600, 1200, 70, 0 }, | |
578 | /* byte 10 */ | |
579 | { 1600, 1200, 75, 0 }, | |
580 | { 1600, 1200, 85, 0 }, | |
581 | { 1792, 1344, 60, 0 }, | |
c068b32a | 582 | { 1792, 1344, 75, 0 }, |
a6b21831 TR |
583 | { 1856, 1392, 60, 0 }, |
584 | { 1856, 1392, 75, 0 }, | |
585 | { 1920, 1200, 60, 1 }, | |
586 | { 1920, 1200, 60, 0 }, | |
587 | /* byte 11 */ | |
588 | { 1920, 1200, 75, 0 }, | |
589 | { 1920, 1200, 85, 0 }, | |
590 | { 1920, 1440, 60, 0 }, | |
591 | { 1920, 1440, 75, 0 }, | |
592 | }; | |
593 | ||
594 | static const struct minimode extra_modes[] = { | |
595 | { 1024, 576, 60, 0 }, | |
596 | { 1366, 768, 60, 0 }, | |
597 | { 1600, 900, 60, 0 }, | |
598 | { 1680, 945, 60, 0 }, | |
599 | { 1920, 1080, 60, 0 }, | |
600 | { 2048, 1152, 60, 0 }, | |
601 | { 2048, 1536, 60, 0 }, | |
602 | }; | |
603 | ||
604 | /* | |
605 | * Probably taken from CEA-861 spec. | |
606 | * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c. | |
607 | */ | |
608 | static const struct drm_display_mode edid_cea_modes[] = { | |
609 | /* 1 - 640x480@60Hz */ | |
610 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, | |
611 | 752, 800, 0, 480, 490, 492, 525, 0, | |
ee7925bb | 612 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 613 | .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
a6b21831 TR |
614 | /* 2 - 720x480@60Hz */ |
615 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, | |
616 | 798, 858, 0, 480, 489, 495, 525, 0, | |
ee7925bb | 617 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 618 | .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
a6b21831 TR |
619 | /* 3 - 720x480@60Hz */ |
620 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, | |
621 | 798, 858, 0, 480, 489, 495, 525, 0, | |
ee7925bb | 622 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 623 | .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
624 | /* 4 - 1280x720@60Hz */ |
625 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, | |
626 | 1430, 1650, 0, 720, 725, 730, 750, 0, | |
ee7925bb | 627 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
985e5dc2 | 628 | .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
629 | /* 5 - 1920x1080i@60Hz */ |
630 | { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, | |
631 | 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, | |
632 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | | |
ee7925bb | 633 | DRM_MODE_FLAG_INTERLACE), |
985e5dc2 | 634 | .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
635 | /* 6 - 1440x480i@60Hz */ |
636 | { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478, | |
637 | 1602, 1716, 0, 480, 488, 494, 525, 0, | |
638 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | | |
ee7925bb | 639 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
985e5dc2 | 640 | .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
a6b21831 TR |
641 | /* 7 - 1440x480i@60Hz */ |
642 | { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478, | |
643 | 1602, 1716, 0, 480, 488, 494, 525, 0, | |
644 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | | |
ee7925bb | 645 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
985e5dc2 | 646 | .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
647 | /* 8 - 1440x240@60Hz */ |
648 | { DRM_MODE("1440x240", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478, | |
649 | 1602, 1716, 0, 240, 244, 247, 262, 0, | |
650 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | | |
ee7925bb | 651 | DRM_MODE_FLAG_DBLCLK), |
985e5dc2 | 652 | .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
a6b21831 TR |
653 | /* 9 - 1440x240@60Hz */ |
654 | { DRM_MODE("1440x240", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478, | |
655 | 1602, 1716, 0, 240, 244, 247, 262, 0, | |
656 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | | |
ee7925bb | 657 | DRM_MODE_FLAG_DBLCLK), |
985e5dc2 | 658 | .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
659 | /* 10 - 2880x480i@60Hz */ |
660 | { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, | |
661 | 3204, 3432, 0, 480, 488, 494, 525, 0, | |
662 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | | |
ee7925bb | 663 | DRM_MODE_FLAG_INTERLACE), |
985e5dc2 | 664 | .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
a6b21831 TR |
665 | /* 11 - 2880x480i@60Hz */ |
666 | { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, | |
667 | 3204, 3432, 0, 480, 488, 494, 525, 0, | |
668 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | | |
ee7925bb | 669 | DRM_MODE_FLAG_INTERLACE), |
985e5dc2 | 670 | .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
671 | /* 12 - 2880x240@60Hz */ |
672 | { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, | |
673 | 3204, 3432, 0, 240, 244, 247, 262, 0, | |
ee7925bb | 674 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 675 | .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
a6b21831 TR |
676 | /* 13 - 2880x240@60Hz */ |
677 | { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, | |
678 | 3204, 3432, 0, 240, 244, 247, 262, 0, | |
ee7925bb | 679 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 680 | .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
681 | /* 14 - 1440x480@60Hz */ |
682 | { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, | |
683 | 1596, 1716, 0, 480, 489, 495, 525, 0, | |
ee7925bb | 684 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 685 | .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
a6b21831 TR |
686 | /* 15 - 1440x480@60Hz */ |
687 | { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, | |
688 | 1596, 1716, 0, 480, 489, 495, 525, 0, | |
ee7925bb | 689 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 690 | .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
691 | /* 16 - 1920x1080@60Hz */ |
692 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, | |
693 | 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, | |
ee7925bb | 694 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
985e5dc2 | 695 | .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
696 | /* 17 - 720x576@50Hz */ |
697 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, | |
698 | 796, 864, 0, 576, 581, 586, 625, 0, | |
ee7925bb | 699 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 700 | .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
a6b21831 TR |
701 | /* 18 - 720x576@50Hz */ |
702 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, | |
703 | 796, 864, 0, 576, 581, 586, 625, 0, | |
ee7925bb | 704 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 705 | .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
706 | /* 19 - 1280x720@50Hz */ |
707 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, | |
708 | 1760, 1980, 0, 720, 725, 730, 750, 0, | |
ee7925bb | 709 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
985e5dc2 | 710 | .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
711 | /* 20 - 1920x1080i@50Hz */ |
712 | { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, | |
713 | 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, | |
714 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | | |
ee7925bb | 715 | DRM_MODE_FLAG_INTERLACE), |
985e5dc2 | 716 | .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
717 | /* 21 - 1440x576i@50Hz */ |
718 | { DRM_MODE("1440x576i", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464, | |
719 | 1590, 1728, 0, 576, 580, 586, 625, 0, | |
720 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | | |
ee7925bb | 721 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
985e5dc2 | 722 | .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
a6b21831 TR |
723 | /* 22 - 1440x576i@50Hz */ |
724 | { DRM_MODE("1440x576i", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464, | |
725 | 1590, 1728, 0, 576, 580, 586, 625, 0, | |
726 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | | |
ee7925bb | 727 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
985e5dc2 | 728 | .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
729 | /* 23 - 1440x288@50Hz */ |
730 | { DRM_MODE("1440x288", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464, | |
731 | 1590, 1728, 0, 288, 290, 293, 312, 0, | |
732 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | | |
ee7925bb | 733 | DRM_MODE_FLAG_DBLCLK), |
985e5dc2 | 734 | .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
a6b21831 TR |
735 | /* 24 - 1440x288@50Hz */ |
736 | { DRM_MODE("1440x288", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464, | |
737 | 1590, 1728, 0, 288, 290, 293, 312, 0, | |
738 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | | |
ee7925bb | 739 | DRM_MODE_FLAG_DBLCLK), |
985e5dc2 | 740 | .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
741 | /* 25 - 2880x576i@50Hz */ |
742 | { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, | |
743 | 3180, 3456, 0, 576, 580, 586, 625, 0, | |
744 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | | |
ee7925bb | 745 | DRM_MODE_FLAG_INTERLACE), |
985e5dc2 | 746 | .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
a6b21831 TR |
747 | /* 26 - 2880x576i@50Hz */ |
748 | { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, | |
749 | 3180, 3456, 0, 576, 580, 586, 625, 0, | |
750 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | | |
ee7925bb | 751 | DRM_MODE_FLAG_INTERLACE), |
985e5dc2 | 752 | .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
753 | /* 27 - 2880x288@50Hz */ |
754 | { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, | |
755 | 3180, 3456, 0, 288, 290, 293, 312, 0, | |
ee7925bb | 756 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 757 | .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
a6b21831 TR |
758 | /* 28 - 2880x288@50Hz */ |
759 | { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, | |
760 | 3180, 3456, 0, 288, 290, 293, 312, 0, | |
ee7925bb | 761 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 762 | .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
763 | /* 29 - 1440x576@50Hz */ |
764 | { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, | |
765 | 1592, 1728, 0, 576, 581, 586, 625, 0, | |
ee7925bb | 766 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 767 | .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
a6b21831 TR |
768 | /* 30 - 1440x576@50Hz */ |
769 | { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, | |
770 | 1592, 1728, 0, 576, 581, 586, 625, 0, | |
ee7925bb | 771 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 772 | .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
773 | /* 31 - 1920x1080@50Hz */ |
774 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, | |
775 | 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, | |
ee7925bb | 776 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
985e5dc2 | 777 | .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
778 | /* 32 - 1920x1080@24Hz */ |
779 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, | |
780 | 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, | |
ee7925bb | 781 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
985e5dc2 | 782 | .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
783 | /* 33 - 1920x1080@25Hz */ |
784 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, | |
785 | 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, | |
ee7925bb | 786 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
985e5dc2 | 787 | .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
788 | /* 34 - 1920x1080@30Hz */ |
789 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, | |
790 | 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, | |
ee7925bb | 791 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
985e5dc2 | 792 | .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
793 | /* 35 - 2880x480@60Hz */ |
794 | { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, | |
795 | 3192, 3432, 0, 480, 489, 495, 525, 0, | |
ee7925bb | 796 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 797 | .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
a6b21831 TR |
798 | /* 36 - 2880x480@60Hz */ |
799 | { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, | |
800 | 3192, 3432, 0, 480, 489, 495, 525, 0, | |
ee7925bb | 801 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 802 | .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
803 | /* 37 - 2880x576@50Hz */ |
804 | { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, | |
805 | 3184, 3456, 0, 576, 581, 586, 625, 0, | |
ee7925bb | 806 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 807 | .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
a6b21831 TR |
808 | /* 38 - 2880x576@50Hz */ |
809 | { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, | |
810 | 3184, 3456, 0, 576, 581, 586, 625, 0, | |
ee7925bb | 811 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 812 | .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
813 | /* 39 - 1920x1080i@50Hz */ |
814 | { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, | |
815 | 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, | |
816 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | | |
ee7925bb | 817 | DRM_MODE_FLAG_INTERLACE), |
985e5dc2 | 818 | .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
819 | /* 40 - 1920x1080i@100Hz */ |
820 | { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, | |
821 | 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, | |
822 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | | |
ee7925bb | 823 | DRM_MODE_FLAG_INTERLACE), |
985e5dc2 | 824 | .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
825 | /* 41 - 1280x720@100Hz */ |
826 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, | |
827 | 1760, 1980, 0, 720, 725, 730, 750, 0, | |
ee7925bb | 828 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
985e5dc2 | 829 | .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
830 | /* 42 - 720x576@100Hz */ |
831 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, | |
832 | 796, 864, 0, 576, 581, 586, 625, 0, | |
ee7925bb | 833 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 834 | .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
a6b21831 TR |
835 | /* 43 - 720x576@100Hz */ |
836 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, | |
837 | 796, 864, 0, 576, 581, 586, 625, 0, | |
ee7925bb | 838 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 839 | .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
840 | /* 44 - 1440x576i@100Hz */ |
841 | { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, | |
842 | 1590, 1728, 0, 576, 580, 586, 625, 0, | |
843 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | | |
ee7925bb | 844 | DRM_MODE_FLAG_DBLCLK), |
985e5dc2 | 845 | .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
a6b21831 TR |
846 | /* 45 - 1440x576i@100Hz */ |
847 | { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, | |
848 | 1590, 1728, 0, 576, 580, 586, 625, 0, | |
849 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | | |
ee7925bb | 850 | DRM_MODE_FLAG_DBLCLK), |
985e5dc2 | 851 | .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
852 | /* 46 - 1920x1080i@120Hz */ |
853 | { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, | |
854 | 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, | |
855 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | | |
ee7925bb | 856 | DRM_MODE_FLAG_INTERLACE), |
985e5dc2 | 857 | .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
858 | /* 47 - 1280x720@120Hz */ |
859 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, | |
860 | 1430, 1650, 0, 720, 725, 730, 750, 0, | |
ee7925bb | 861 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
985e5dc2 | 862 | .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
863 | /* 48 - 720x480@120Hz */ |
864 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, | |
865 | 798, 858, 0, 480, 489, 495, 525, 0, | |
ee7925bb | 866 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 867 | .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
a6b21831 TR |
868 | /* 49 - 720x480@120Hz */ |
869 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, | |
870 | 798, 858, 0, 480, 489, 495, 525, 0, | |
ee7925bb | 871 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 872 | .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
873 | /* 50 - 1440x480i@120Hz */ |
874 | { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1478, | |
875 | 1602, 1716, 0, 480, 488, 494, 525, 0, | |
876 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | | |
ee7925bb | 877 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
985e5dc2 | 878 | .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
a6b21831 TR |
879 | /* 51 - 1440x480i@120Hz */ |
880 | { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1478, | |
881 | 1602, 1716, 0, 480, 488, 494, 525, 0, | |
882 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | | |
ee7925bb | 883 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
985e5dc2 | 884 | .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
885 | /* 52 - 720x576@200Hz */ |
886 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, | |
887 | 796, 864, 0, 576, 581, 586, 625, 0, | |
ee7925bb | 888 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 889 | .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
a6b21831 TR |
890 | /* 53 - 720x576@200Hz */ |
891 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, | |
892 | 796, 864, 0, 576, 581, 586, 625, 0, | |
ee7925bb | 893 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 894 | .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
895 | /* 54 - 1440x576i@200Hz */ |
896 | { DRM_MODE("1440x576i", DRM_MODE_TYPE_DRIVER, 108000, 1440, 1464, | |
897 | 1590, 1728, 0, 576, 580, 586, 625, 0, | |
898 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | | |
ee7925bb | 899 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
985e5dc2 | 900 | .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
a6b21831 TR |
901 | /* 55 - 1440x576i@200Hz */ |
902 | { DRM_MODE("1440x576i", DRM_MODE_TYPE_DRIVER, 108000, 1440, 1464, | |
903 | 1590, 1728, 0, 576, 580, 586, 625, 0, | |
904 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | | |
ee7925bb | 905 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
985e5dc2 | 906 | .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
907 | /* 56 - 720x480@240Hz */ |
908 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, | |
909 | 798, 858, 0, 480, 489, 495, 525, 0, | |
ee7925bb | 910 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 911 | .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
a6b21831 TR |
912 | /* 57 - 720x480@240Hz */ |
913 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, | |
914 | 798, 858, 0, 480, 489, 495, 525, 0, | |
ee7925bb | 915 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 916 | .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
917 | /* 58 - 1440x480i@240 */ |
918 | { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 108000, 1440, 1478, | |
919 | 1602, 1716, 0, 480, 488, 494, 525, 0, | |
920 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | | |
ee7925bb | 921 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
985e5dc2 | 922 | .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
a6b21831 TR |
923 | /* 59 - 1440x480i@240 */ |
924 | { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 108000, 1440, 1478, | |
925 | 1602, 1716, 0, 480, 488, 494, 525, 0, | |
926 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | | |
ee7925bb | 927 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
985e5dc2 | 928 | .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
929 | /* 60 - 1280x720@24Hz */ |
930 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, | |
931 | 3080, 3300, 0, 720, 725, 730, 750, 0, | |
ee7925bb | 932 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
985e5dc2 | 933 | .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
934 | /* 61 - 1280x720@25Hz */ |
935 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, | |
936 | 3740, 3960, 0, 720, 725, 730, 750, 0, | |
ee7925bb | 937 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
985e5dc2 | 938 | .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
939 | /* 62 - 1280x720@30Hz */ |
940 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, | |
941 | 3080, 3300, 0, 720, 725, 730, 750, 0, | |
ee7925bb | 942 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
985e5dc2 | 943 | .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
944 | /* 63 - 1920x1080@120Hz */ |
945 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, | |
946 | 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, | |
ee7925bb | 947 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
985e5dc2 | 948 | .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
949 | /* 64 - 1920x1080@100Hz */ |
950 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, | |
951 | 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, | |
ee7925bb | 952 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
985e5dc2 | 953 | .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
954 | }; |
955 | ||
7ebe1963 LD |
956 | /* |
957 | * HDMI 1.4 4k modes. | |
958 | */ | |
959 | static const struct drm_display_mode edid_4k_modes[] = { | |
960 | /* 1 - 3840x2160@30Hz */ | |
961 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, | |
962 | 3840, 4016, 4104, 4400, 0, | |
963 | 2160, 2168, 2178, 2250, 0, | |
964 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
965 | .vrefresh = 30, }, | |
966 | /* 2 - 3840x2160@25Hz */ | |
967 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, | |
968 | 3840, 4896, 4984, 5280, 0, | |
969 | 2160, 2168, 2178, 2250, 0, | |
970 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
971 | .vrefresh = 25, }, | |
972 | /* 3 - 3840x2160@24Hz */ | |
973 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, | |
974 | 3840, 5116, 5204, 5500, 0, | |
975 | 2160, 2168, 2178, 2250, 0, | |
976 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
977 | .vrefresh = 24, }, | |
978 | /* 4 - 4096x2160@24Hz (SMPTE) */ | |
979 | { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, | |
980 | 4096, 5116, 5204, 5500, 0, | |
981 | 2160, 2168, 2178, 2250, 0, | |
982 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
983 | .vrefresh = 24, }, | |
984 | }; | |
985 | ||
61e57a8d | 986 | /*** DDC fetch and block validation ***/ |
f453ba04 | 987 | |
083ae056 AJ |
988 | static const u8 edid_header[] = { |
989 | 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 | |
990 | }; | |
f453ba04 | 991 | |
db6cf833 TR |
992 | /** |
993 | * drm_edid_header_is_valid - sanity check the header of the base EDID block | |
994 | * @raw_edid: pointer to raw base EDID block | |
995 | * | |
996 | * Sanity check the header of the base EDID block. | |
997 | * | |
998 | * Return: 8 if the header is perfect, down to 0 if it's totally wrong. | |
051963d4 TR |
999 | */ |
1000 | int drm_edid_header_is_valid(const u8 *raw_edid) | |
1001 | { | |
1002 | int i, score = 0; | |
1003 | ||
1004 | for (i = 0; i < sizeof(edid_header); i++) | |
1005 | if (raw_edid[i] == edid_header[i]) | |
1006 | score++; | |
1007 | ||
1008 | return score; | |
1009 | } | |
1010 | EXPORT_SYMBOL(drm_edid_header_is_valid); | |
1011 | ||
47819ba2 AJ |
1012 | static int edid_fixup __read_mostly = 6; |
1013 | module_param_named(edid_fixup, edid_fixup, int, 0400); | |
1014 | MODULE_PARM_DESC(edid_fixup, | |
1015 | "Minimum number of valid EDID header bytes (0-8, default 6)"); | |
051963d4 | 1016 | |
db6cf833 TR |
1017 | /** |
1018 | * drm_edid_block_valid - Sanity check the EDID block (base or extension) | |
1019 | * @raw_edid: pointer to raw EDID block | |
1020 | * @block: type of block to validate (0 for base, extension otherwise) | |
1021 | * @print_bad_edid: if true, dump bad EDID blocks to the console | |
1022 | * | |
1023 | * Validate a base or extension EDID block and optionally dump bad blocks to | |
1024 | * the console. | |
1025 | * | |
1026 | * Return: True if the block is valid, false otherwise. | |
f453ba04 | 1027 | */ |
0b2443ed | 1028 | bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid) |
f453ba04 | 1029 | { |
61e57a8d | 1030 | int i; |
f453ba04 | 1031 | u8 csum = 0; |
61e57a8d | 1032 | struct edid *edid = (struct edid *)raw_edid; |
f453ba04 | 1033 | |
fe2ef780 SWK |
1034 | if (WARN_ON(!raw_edid)) |
1035 | return false; | |
1036 | ||
47819ba2 AJ |
1037 | if (edid_fixup > 8 || edid_fixup < 0) |
1038 | edid_fixup = 6; | |
1039 | ||
f89ec8a4 | 1040 | if (block == 0) { |
051963d4 | 1041 | int score = drm_edid_header_is_valid(raw_edid); |
61e57a8d | 1042 | if (score == 8) ; |
47819ba2 | 1043 | else if (score >= edid_fixup) { |
61e57a8d AJ |
1044 | DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); |
1045 | memcpy(raw_edid, edid_header, sizeof(edid_header)); | |
1046 | } else { | |
1047 | goto bad; | |
1048 | } | |
1049 | } | |
f453ba04 DA |
1050 | |
1051 | for (i = 0; i < EDID_LENGTH; i++) | |
1052 | csum += raw_edid[i]; | |
1053 | if (csum) { | |
0b2443ed JG |
1054 | if (print_bad_edid) { |
1055 | DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum); | |
1056 | } | |
4a638b4e AJ |
1057 | |
1058 | /* allow CEA to slide through, switches mangle this */ | |
1059 | if (raw_edid[0] != 0x02) | |
1060 | goto bad; | |
f453ba04 DA |
1061 | } |
1062 | ||
61e57a8d AJ |
1063 | /* per-block-type checks */ |
1064 | switch (raw_edid[0]) { | |
1065 | case 0: /* base */ | |
1066 | if (edid->version != 1) { | |
1067 | DRM_ERROR("EDID has major version %d, instead of 1\n", edid->version); | |
1068 | goto bad; | |
1069 | } | |
862b89c0 | 1070 | |
61e57a8d AJ |
1071 | if (edid->revision > 4) |
1072 | DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n"); | |
1073 | break; | |
862b89c0 | 1074 | |
61e57a8d AJ |
1075 | default: |
1076 | break; | |
1077 | } | |
47ee4ccf | 1078 | |
fe2ef780 | 1079 | return true; |
f453ba04 DA |
1080 | |
1081 | bad: | |
fe2ef780 | 1082 | if (print_bad_edid) { |
f49dadb8 | 1083 | printk(KERN_ERR "Raw EDID:\n"); |
0aff47f2 TV |
1084 | print_hex_dump(KERN_ERR, " \t", DUMP_PREFIX_NONE, 16, 1, |
1085 | raw_edid, EDID_LENGTH, false); | |
f453ba04 | 1086 | } |
fe2ef780 | 1087 | return false; |
f453ba04 | 1088 | } |
da0df92b | 1089 | EXPORT_SYMBOL(drm_edid_block_valid); |
61e57a8d AJ |
1090 | |
1091 | /** | |
1092 | * drm_edid_is_valid - sanity check EDID data | |
1093 | * @edid: EDID data | |
1094 | * | |
1095 | * Sanity-check an entire EDID record (including extensions) | |
db6cf833 TR |
1096 | * |
1097 | * Return: True if the EDID data is valid, false otherwise. | |
61e57a8d AJ |
1098 | */ |
1099 | bool drm_edid_is_valid(struct edid *edid) | |
1100 | { | |
1101 | int i; | |
1102 | u8 *raw = (u8 *)edid; | |
1103 | ||
1104 | if (!edid) | |
1105 | return false; | |
1106 | ||
1107 | for (i = 0; i <= edid->extensions; i++) | |
0b2443ed | 1108 | if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true)) |
61e57a8d AJ |
1109 | return false; |
1110 | ||
1111 | return true; | |
1112 | } | |
3c537889 | 1113 | EXPORT_SYMBOL(drm_edid_is_valid); |
f453ba04 | 1114 | |
61e57a8d AJ |
1115 | #define DDC_SEGMENT_ADDR 0x30 |
1116 | /** | |
db6cf833 TR |
1117 | * drm_do_probe_ddc_edid() - get EDID information via I2C |
1118 | * @adapter: I2C device adaptor | |
fc66811c DV |
1119 | * @buf: EDID data buffer to be filled |
1120 | * @block: 128 byte EDID block to start fetching from | |
1121 | * @len: EDID data buffer length to fetch | |
1122 | * | |
db6cf833 | 1123 | * Try to fetch EDID information by calling I2C driver functions. |
61e57a8d | 1124 | * |
db6cf833 | 1125 | * Return: 0 on success or -1 on failure. |
61e57a8d AJ |
1126 | */ |
1127 | static int | |
1128 | drm_do_probe_ddc_edid(struct i2c_adapter *adapter, unsigned char *buf, | |
1129 | int block, int len) | |
1130 | { | |
1131 | unsigned char start = block * EDID_LENGTH; | |
cd004b3f S |
1132 | unsigned char segment = block >> 1; |
1133 | unsigned char xfers = segment ? 3 : 2; | |
4819d2e4 CW |
1134 | int ret, retries = 5; |
1135 | ||
db6cf833 TR |
1136 | /* |
1137 | * The core I2C driver will automatically retry the transfer if the | |
4819d2e4 CW |
1138 | * adapter reports EAGAIN. However, we find that bit-banging transfers |
1139 | * are susceptible to errors under a heavily loaded machine and | |
1140 | * generate spurious NAKs and timeouts. Retrying the transfer | |
1141 | * of the individual block a few times seems to overcome this. | |
1142 | */ | |
1143 | do { | |
1144 | struct i2c_msg msgs[] = { | |
1145 | { | |
cd004b3f S |
1146 | .addr = DDC_SEGMENT_ADDR, |
1147 | .flags = 0, | |
1148 | .len = 1, | |
1149 | .buf = &segment, | |
1150 | }, { | |
4819d2e4 CW |
1151 | .addr = DDC_ADDR, |
1152 | .flags = 0, | |
1153 | .len = 1, | |
1154 | .buf = &start, | |
1155 | }, { | |
1156 | .addr = DDC_ADDR, | |
1157 | .flags = I2C_M_RD, | |
1158 | .len = len, | |
1159 | .buf = buf, | |
1160 | } | |
1161 | }; | |
cd004b3f | 1162 | |
db6cf833 TR |
1163 | /* |
1164 | * Avoid sending the segment addr to not upset non-compliant | |
1165 | * DDC monitors. | |
1166 | */ | |
cd004b3f S |
1167 | ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); |
1168 | ||
9292f37e ED |
1169 | if (ret == -ENXIO) { |
1170 | DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", | |
1171 | adapter->name); | |
1172 | break; | |
1173 | } | |
cd004b3f | 1174 | } while (ret != xfers && --retries); |
4819d2e4 | 1175 | |
cd004b3f | 1176 | return ret == xfers ? 0 : -1; |
61e57a8d AJ |
1177 | } |
1178 | ||
4a9a8b71 DA |
1179 | static bool drm_edid_is_zero(u8 *in_edid, int length) |
1180 | { | |
6311803b AM |
1181 | if (memchr_inv(in_edid, 0, length)) |
1182 | return false; | |
4a9a8b71 | 1183 | |
4a9a8b71 DA |
1184 | return true; |
1185 | } | |
1186 | ||
61e57a8d AJ |
1187 | static u8 * |
1188 | drm_do_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) | |
1189 | { | |
0ea75e23 | 1190 | int i, j = 0, valid_extensions = 0; |
61e57a8d | 1191 | u8 *block, *new; |
0b2443ed | 1192 | bool print_bad_edid = !connector->bad_edid_counter || (drm_debug & DRM_UT_KMS); |
61e57a8d AJ |
1193 | |
1194 | if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL) | |
1195 | return NULL; | |
1196 | ||
1197 | /* base block fetch */ | |
1198 | for (i = 0; i < 4; i++) { | |
1199 | if (drm_do_probe_ddc_edid(adapter, block, 0, EDID_LENGTH)) | |
1200 | goto out; | |
0b2443ed | 1201 | if (drm_edid_block_valid(block, 0, print_bad_edid)) |
61e57a8d | 1202 | break; |
4a9a8b71 DA |
1203 | if (i == 0 && drm_edid_is_zero(block, EDID_LENGTH)) { |
1204 | connector->null_edid_counter++; | |
1205 | goto carp; | |
1206 | } | |
61e57a8d AJ |
1207 | } |
1208 | if (i == 4) | |
1209 | goto carp; | |
1210 | ||
1211 | /* if there's no extensions, we're done */ | |
1212 | if (block[0x7e] == 0) | |
1213 | return block; | |
1214 | ||
1215 | new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL); | |
1216 | if (!new) | |
1217 | goto out; | |
1218 | block = new; | |
1219 | ||
1220 | for (j = 1; j <= block[0x7e]; j++) { | |
1221 | for (i = 0; i < 4; i++) { | |
0ea75e23 ST |
1222 | if (drm_do_probe_ddc_edid(adapter, |
1223 | block + (valid_extensions + 1) * EDID_LENGTH, | |
1224 | j, EDID_LENGTH)) | |
61e57a8d | 1225 | goto out; |
0b2443ed | 1226 | if (drm_edid_block_valid(block + (valid_extensions + 1) * EDID_LENGTH, j, print_bad_edid)) { |
0ea75e23 | 1227 | valid_extensions++; |
61e57a8d | 1228 | break; |
0ea75e23 | 1229 | } |
61e57a8d | 1230 | } |
f934ec8c ML |
1231 | |
1232 | if (i == 4 && print_bad_edid) { | |
0ea75e23 ST |
1233 | dev_warn(connector->dev->dev, |
1234 | "%s: Ignoring invalid EDID block %d.\n", | |
25933820 | 1235 | connector->name, j); |
f934ec8c ML |
1236 | |
1237 | connector->bad_edid_counter++; | |
1238 | } | |
0ea75e23 ST |
1239 | } |
1240 | ||
1241 | if (valid_extensions != block[0x7e]) { | |
1242 | block[EDID_LENGTH-1] += block[0x7e] - valid_extensions; | |
1243 | block[0x7e] = valid_extensions; | |
1244 | new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); | |
1245 | if (!new) | |
1246 | goto out; | |
1247 | block = new; | |
61e57a8d AJ |
1248 | } |
1249 | ||
1250 | return block; | |
1251 | ||
1252 | carp: | |
0b2443ed JG |
1253 | if (print_bad_edid) { |
1254 | dev_warn(connector->dev->dev, "%s: EDID block %d invalid.\n", | |
25933820 | 1255 | connector->name, j); |
0b2443ed JG |
1256 | } |
1257 | connector->bad_edid_counter++; | |
61e57a8d AJ |
1258 | |
1259 | out: | |
1260 | kfree(block); | |
1261 | return NULL; | |
1262 | } | |
1263 | ||
1264 | /** | |
db6cf833 TR |
1265 | * drm_probe_ddc() - probe DDC presence |
1266 | * @adapter: I2C adapter to probe | |
fc66811c | 1267 | * |
db6cf833 | 1268 | * Return: True on success, false on failure. |
61e57a8d | 1269 | */ |
fbff4690 | 1270 | bool |
61e57a8d AJ |
1271 | drm_probe_ddc(struct i2c_adapter *adapter) |
1272 | { | |
1273 | unsigned char out; | |
1274 | ||
1275 | return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); | |
1276 | } | |
fbff4690 | 1277 | EXPORT_SYMBOL(drm_probe_ddc); |
61e57a8d AJ |
1278 | |
1279 | /** | |
1280 | * drm_get_edid - get EDID data, if available | |
1281 | * @connector: connector we're probing | |
db6cf833 | 1282 | * @adapter: I2C adapter to use for DDC |
61e57a8d | 1283 | * |
db6cf833 | 1284 | * Poke the given I2C channel to grab EDID data if possible. If found, |
61e57a8d AJ |
1285 | * attach it to the connector. |
1286 | * | |
db6cf833 | 1287 | * Return: Pointer to valid EDID or NULL if we couldn't find any. |
61e57a8d AJ |
1288 | */ |
1289 | struct edid *drm_get_edid(struct drm_connector *connector, | |
1290 | struct i2c_adapter *adapter) | |
1291 | { | |
1292 | struct edid *edid = NULL; | |
1293 | ||
1294 | if (drm_probe_ddc(adapter)) | |
1295 | edid = (struct edid *)drm_do_get_edid(connector, adapter); | |
1296 | ||
61e57a8d | 1297 | return edid; |
61e57a8d AJ |
1298 | } |
1299 | EXPORT_SYMBOL(drm_get_edid); | |
1300 | ||
51f8da59 JN |
1301 | /** |
1302 | * drm_edid_duplicate - duplicate an EDID and the extensions | |
1303 | * @edid: EDID to duplicate | |
1304 | * | |
db6cf833 | 1305 | * Return: Pointer to duplicated EDID or NULL on allocation failure. |
51f8da59 JN |
1306 | */ |
1307 | struct edid *drm_edid_duplicate(const struct edid *edid) | |
1308 | { | |
1309 | return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL); | |
1310 | } | |
1311 | EXPORT_SYMBOL(drm_edid_duplicate); | |
1312 | ||
61e57a8d AJ |
1313 | /*** EDID parsing ***/ |
1314 | ||
f453ba04 DA |
1315 | /** |
1316 | * edid_vendor - match a string against EDID's obfuscated vendor field | |
1317 | * @edid: EDID to match | |
1318 | * @vendor: vendor string | |
1319 | * | |
1320 | * Returns true if @vendor is in @edid, false otherwise | |
1321 | */ | |
1322 | static bool edid_vendor(struct edid *edid, char *vendor) | |
1323 | { | |
1324 | char edid_vendor[3]; | |
1325 | ||
1326 | edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; | |
1327 | edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | | |
1328 | ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; | |
16456c87 | 1329 | edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; |
f453ba04 DA |
1330 | |
1331 | return !strncmp(edid_vendor, vendor, 3); | |
1332 | } | |
1333 | ||
1334 | /** | |
1335 | * edid_get_quirks - return quirk flags for a given EDID | |
1336 | * @edid: EDID to process | |
1337 | * | |
1338 | * This tells subsequent routines what fixes they need to apply. | |
1339 | */ | |
1340 | static u32 edid_get_quirks(struct edid *edid) | |
1341 | { | |
1342 | struct edid_quirk *quirk; | |
1343 | int i; | |
1344 | ||
1345 | for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { | |
1346 | quirk = &edid_quirk_list[i]; | |
1347 | ||
1348 | if (edid_vendor(edid, quirk->vendor) && | |
1349 | (EDID_PRODUCT_ID(edid) == quirk->product_id)) | |
1350 | return quirk->quirks; | |
1351 | } | |
1352 | ||
1353 | return 0; | |
1354 | } | |
1355 | ||
1356 | #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) | |
339d202c | 1357 | #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) |
f453ba04 | 1358 | |
f453ba04 DA |
1359 | /** |
1360 | * edid_fixup_preferred - set preferred modes based on quirk list | |
1361 | * @connector: has mode list to fix up | |
1362 | * @quirks: quirks list | |
1363 | * | |
1364 | * Walk the mode list for @connector, clearing the preferred status | |
1365 | * on existing modes and setting it anew for the right mode ala @quirks. | |
1366 | */ | |
1367 | static void edid_fixup_preferred(struct drm_connector *connector, | |
1368 | u32 quirks) | |
1369 | { | |
1370 | struct drm_display_mode *t, *cur_mode, *preferred_mode; | |
f890607b | 1371 | int target_refresh = 0; |
339d202c | 1372 | int cur_vrefresh, preferred_vrefresh; |
f453ba04 DA |
1373 | |
1374 | if (list_empty(&connector->probed_modes)) | |
1375 | return; | |
1376 | ||
1377 | if (quirks & EDID_QUIRK_PREFER_LARGE_60) | |
1378 | target_refresh = 60; | |
1379 | if (quirks & EDID_QUIRK_PREFER_LARGE_75) | |
1380 | target_refresh = 75; | |
1381 | ||
1382 | preferred_mode = list_first_entry(&connector->probed_modes, | |
1383 | struct drm_display_mode, head); | |
1384 | ||
1385 | list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { | |
1386 | cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; | |
1387 | ||
1388 | if (cur_mode == preferred_mode) | |
1389 | continue; | |
1390 | ||
1391 | /* Largest mode is preferred */ | |
1392 | if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) | |
1393 | preferred_mode = cur_mode; | |
1394 | ||
339d202c AD |
1395 | cur_vrefresh = cur_mode->vrefresh ? |
1396 | cur_mode->vrefresh : drm_mode_vrefresh(cur_mode); | |
1397 | preferred_vrefresh = preferred_mode->vrefresh ? | |
1398 | preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode); | |
f453ba04 DA |
1399 | /* At a given size, try to get closest to target refresh */ |
1400 | if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && | |
339d202c AD |
1401 | MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < |
1402 | MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { | |
f453ba04 DA |
1403 | preferred_mode = cur_mode; |
1404 | } | |
1405 | } | |
1406 | ||
1407 | preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; | |
1408 | } | |
1409 | ||
f6e252ba AJ |
1410 | static bool |
1411 | mode_is_rb(const struct drm_display_mode *mode) | |
1412 | { | |
1413 | return (mode->htotal - mode->hdisplay == 160) && | |
1414 | (mode->hsync_end - mode->hdisplay == 80) && | |
1415 | (mode->hsync_end - mode->hsync_start == 32) && | |
1416 | (mode->vsync_start - mode->vdisplay == 3); | |
1417 | } | |
1418 | ||
33c7531d AJ |
1419 | /* |
1420 | * drm_mode_find_dmt - Create a copy of a mode if present in DMT | |
1421 | * @dev: Device to duplicate against | |
1422 | * @hsize: Mode width | |
1423 | * @vsize: Mode height | |
1424 | * @fresh: Mode refresh rate | |
f6e252ba | 1425 | * @rb: Mode reduced-blanking-ness |
33c7531d AJ |
1426 | * |
1427 | * Walk the DMT mode list looking for a match for the given parameters. | |
db6cf833 TR |
1428 | * |
1429 | * Return: A newly allocated copy of the mode, or NULL if not found. | |
33c7531d | 1430 | */ |
1d42bbc8 | 1431 | struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, |
f6e252ba AJ |
1432 | int hsize, int vsize, int fresh, |
1433 | bool rb) | |
559ee21d | 1434 | { |
07a5e632 | 1435 | int i; |
559ee21d | 1436 | |
a6b21831 | 1437 | for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { |
b1f559ec | 1438 | const struct drm_display_mode *ptr = &drm_dmt_modes[i]; |
f8b46a05 AJ |
1439 | if (hsize != ptr->hdisplay) |
1440 | continue; | |
1441 | if (vsize != ptr->vdisplay) | |
1442 | continue; | |
1443 | if (fresh != drm_mode_vrefresh(ptr)) | |
1444 | continue; | |
f6e252ba AJ |
1445 | if (rb != mode_is_rb(ptr)) |
1446 | continue; | |
f8b46a05 AJ |
1447 | |
1448 | return drm_mode_duplicate(dev, ptr); | |
559ee21d | 1449 | } |
f8b46a05 AJ |
1450 | |
1451 | return NULL; | |
559ee21d | 1452 | } |
1d42bbc8 | 1453 | EXPORT_SYMBOL(drm_mode_find_dmt); |
23425cae | 1454 | |
d1ff6409 AJ |
1455 | typedef void detailed_cb(struct detailed_timing *timing, void *closure); |
1456 | ||
4d76a221 AJ |
1457 | static void |
1458 | cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) | |
1459 | { | |
1460 | int i, n = 0; | |
4966b2a9 | 1461 | u8 d = ext[0x02]; |
4d76a221 AJ |
1462 | u8 *det_base = ext + d; |
1463 | ||
4966b2a9 | 1464 | n = (127 - d) / 18; |
4d76a221 AJ |
1465 | for (i = 0; i < n; i++) |
1466 | cb((struct detailed_timing *)(det_base + 18 * i), closure); | |
1467 | } | |
1468 | ||
cbba98f8 AJ |
1469 | static void |
1470 | vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) | |
1471 | { | |
1472 | unsigned int i, n = min((int)ext[0x02], 6); | |
1473 | u8 *det_base = ext + 5; | |
1474 | ||
1475 | if (ext[0x01] != 1) | |
1476 | return; /* unknown version */ | |
1477 | ||
1478 | for (i = 0; i < n; i++) | |
1479 | cb((struct detailed_timing *)(det_base + 18 * i), closure); | |
1480 | } | |
1481 | ||
d1ff6409 AJ |
1482 | static void |
1483 | drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) | |
1484 | { | |
1485 | int i; | |
1486 | struct edid *edid = (struct edid *)raw_edid; | |
1487 | ||
1488 | if (edid == NULL) | |
1489 | return; | |
1490 | ||
1491 | for (i = 0; i < EDID_DETAILED_TIMINGS; i++) | |
1492 | cb(&(edid->detailed_timings[i]), closure); | |
1493 | ||
4d76a221 AJ |
1494 | for (i = 1; i <= raw_edid[0x7e]; i++) { |
1495 | u8 *ext = raw_edid + (i * EDID_LENGTH); | |
1496 | switch (*ext) { | |
1497 | case CEA_EXT: | |
1498 | cea_for_each_detailed_block(ext, cb, closure); | |
1499 | break; | |
cbba98f8 AJ |
1500 | case VTB_EXT: |
1501 | vtb_for_each_detailed_block(ext, cb, closure); | |
1502 | break; | |
4d76a221 AJ |
1503 | default: |
1504 | break; | |
1505 | } | |
1506 | } | |
d1ff6409 AJ |
1507 | } |
1508 | ||
1509 | static void | |
1510 | is_rb(struct detailed_timing *t, void *data) | |
1511 | { | |
1512 | u8 *r = (u8 *)t; | |
1513 | if (r[3] == EDID_DETAIL_MONITOR_RANGE) | |
1514 | if (r[15] & 0x10) | |
1515 | *(bool *)data = true; | |
1516 | } | |
1517 | ||
1518 | /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ | |
1519 | static bool | |
1520 | drm_monitor_supports_rb(struct edid *edid) | |
1521 | { | |
1522 | if (edid->revision >= 4) { | |
b196a498 | 1523 | bool ret = false; |
d1ff6409 AJ |
1524 | drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); |
1525 | return ret; | |
1526 | } | |
1527 | ||
1528 | return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); | |
1529 | } | |
1530 | ||
7a374350 AJ |
1531 | static void |
1532 | find_gtf2(struct detailed_timing *t, void *data) | |
1533 | { | |
1534 | u8 *r = (u8 *)t; | |
1535 | if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02) | |
1536 | *(u8 **)data = r; | |
1537 | } | |
1538 | ||
1539 | /* Secondary GTF curve kicks in above some break frequency */ | |
1540 | static int | |
1541 | drm_gtf2_hbreak(struct edid *edid) | |
1542 | { | |
1543 | u8 *r = NULL; | |
1544 | drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); | |
1545 | return r ? (r[12] * 2) : 0; | |
1546 | } | |
1547 | ||
1548 | static int | |
1549 | drm_gtf2_2c(struct edid *edid) | |
1550 | { | |
1551 | u8 *r = NULL; | |
1552 | drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); | |
1553 | return r ? r[13] : 0; | |
1554 | } | |
1555 | ||
1556 | static int | |
1557 | drm_gtf2_m(struct edid *edid) | |
1558 | { | |
1559 | u8 *r = NULL; | |
1560 | drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); | |
1561 | return r ? (r[15] << 8) + r[14] : 0; | |
1562 | } | |
1563 | ||
1564 | static int | |
1565 | drm_gtf2_k(struct edid *edid) | |
1566 | { | |
1567 | u8 *r = NULL; | |
1568 | drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); | |
1569 | return r ? r[16] : 0; | |
1570 | } | |
1571 | ||
1572 | static int | |
1573 | drm_gtf2_2j(struct edid *edid) | |
1574 | { | |
1575 | u8 *r = NULL; | |
1576 | drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); | |
1577 | return r ? r[17] : 0; | |
1578 | } | |
1579 | ||
1580 | /** | |
1581 | * standard_timing_level - get std. timing level(CVT/GTF/DMT) | |
1582 | * @edid: EDID block to scan | |
1583 | */ | |
1584 | static int standard_timing_level(struct edid *edid) | |
1585 | { | |
1586 | if (edid->revision >= 2) { | |
1587 | if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) | |
1588 | return LEVEL_CVT; | |
1589 | if (drm_gtf2_hbreak(edid)) | |
1590 | return LEVEL_GTF2; | |
1591 | return LEVEL_GTF; | |
1592 | } | |
1593 | return LEVEL_DMT; | |
1594 | } | |
1595 | ||
23425cae AJ |
1596 | /* |
1597 | * 0 is reserved. The spec says 0x01 fill for unused timings. Some old | |
1598 | * monitors fill with ascii space (0x20) instead. | |
1599 | */ | |
1600 | static int | |
1601 | bad_std_timing(u8 a, u8 b) | |
1602 | { | |
1603 | return (a == 0x00 && b == 0x00) || | |
1604 | (a == 0x01 && b == 0x01) || | |
1605 | (a == 0x20 && b == 0x20); | |
1606 | } | |
1607 | ||
f453ba04 DA |
1608 | /** |
1609 | * drm_mode_std - convert standard mode info (width, height, refresh) into mode | |
fc66811c DV |
1610 | * @connector: connector of for the EDID block |
1611 | * @edid: EDID block to scan | |
f453ba04 DA |
1612 | * @t: standard timing params |
1613 | * | |
1614 | * Take the standard timing params (in this case width, aspect, and refresh) | |
5c61259e | 1615 | * and convert them into a real mode using CVT/GTF/DMT. |
f453ba04 | 1616 | */ |
7ca6adb3 | 1617 | static struct drm_display_mode * |
7a374350 | 1618 | drm_mode_std(struct drm_connector *connector, struct edid *edid, |
464fdeca | 1619 | struct std_timing *t) |
f453ba04 | 1620 | { |
7ca6adb3 AJ |
1621 | struct drm_device *dev = connector->dev; |
1622 | struct drm_display_mode *m, *mode = NULL; | |
5c61259e ZY |
1623 | int hsize, vsize; |
1624 | int vrefresh_rate; | |
0454beab MD |
1625 | unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) |
1626 | >> EDID_TIMING_ASPECT_SHIFT; | |
5c61259e ZY |
1627 | unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) |
1628 | >> EDID_TIMING_VFREQ_SHIFT; | |
7a374350 | 1629 | int timing_level = standard_timing_level(edid); |
5c61259e | 1630 | |
23425cae AJ |
1631 | if (bad_std_timing(t->hsize, t->vfreq_aspect)) |
1632 | return NULL; | |
1633 | ||
5c61259e ZY |
1634 | /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ |
1635 | hsize = t->hsize * 8 + 248; | |
1636 | /* vrefresh_rate = vfreq + 60 */ | |
1637 | vrefresh_rate = vfreq + 60; | |
1638 | /* the vdisplay is calculated based on the aspect ratio */ | |
f066a17d | 1639 | if (aspect_ratio == 0) { |
464fdeca | 1640 | if (edid->revision < 3) |
f066a17d AJ |
1641 | vsize = hsize; |
1642 | else | |
1643 | vsize = (hsize * 10) / 16; | |
1644 | } else if (aspect_ratio == 1) | |
f453ba04 | 1645 | vsize = (hsize * 3) / 4; |
0454beab | 1646 | else if (aspect_ratio == 2) |
f453ba04 DA |
1647 | vsize = (hsize * 4) / 5; |
1648 | else | |
1649 | vsize = (hsize * 9) / 16; | |
a0910c8e AJ |
1650 | |
1651 | /* HDTV hack, part 1 */ | |
1652 | if (vrefresh_rate == 60 && | |
1653 | ((hsize == 1360 && vsize == 765) || | |
1654 | (hsize == 1368 && vsize == 769))) { | |
1655 | hsize = 1366; | |
1656 | vsize = 768; | |
1657 | } | |
1658 | ||
7ca6adb3 AJ |
1659 | /* |
1660 | * If this connector already has a mode for this size and refresh | |
1661 | * rate (because it came from detailed or CVT info), use that | |
1662 | * instead. This way we don't have to guess at interlace or | |
1663 | * reduced blanking. | |
1664 | */ | |
522032da | 1665 | list_for_each_entry(m, &connector->probed_modes, head) |
7ca6adb3 AJ |
1666 | if (m->hdisplay == hsize && m->vdisplay == vsize && |
1667 | drm_mode_vrefresh(m) == vrefresh_rate) | |
1668 | return NULL; | |
1669 | ||
a0910c8e AJ |
1670 | /* HDTV hack, part 2 */ |
1671 | if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { | |
1672 | mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, | |
d50ba256 | 1673 | false); |
559ee21d | 1674 | mode->hdisplay = 1366; |
a4967de6 AJ |
1675 | mode->hsync_start = mode->hsync_start - 1; |
1676 | mode->hsync_end = mode->hsync_end - 1; | |
559ee21d ZY |
1677 | return mode; |
1678 | } | |
a0910c8e | 1679 | |
559ee21d | 1680 | /* check whether it can be found in default mode table */ |
f6e252ba AJ |
1681 | if (drm_monitor_supports_rb(edid)) { |
1682 | mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, | |
1683 | true); | |
1684 | if (mode) | |
1685 | return mode; | |
1686 | } | |
1687 | mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); | |
559ee21d ZY |
1688 | if (mode) |
1689 | return mode; | |
1690 | ||
f6e252ba | 1691 | /* okay, generate it */ |
5c61259e ZY |
1692 | switch (timing_level) { |
1693 | case LEVEL_DMT: | |
5c61259e ZY |
1694 | break; |
1695 | case LEVEL_GTF: | |
1696 | mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); | |
1697 | break; | |
7a374350 AJ |
1698 | case LEVEL_GTF2: |
1699 | /* | |
1700 | * This is potentially wrong if there's ever a monitor with | |
1701 | * more than one ranges section, each claiming a different | |
1702 | * secondary GTF curve. Please don't do that. | |
1703 | */ | |
1704 | mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); | |
fc48f169 TI |
1705 | if (!mode) |
1706 | return NULL; | |
7a374350 | 1707 | if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { |
aefd330e | 1708 | drm_mode_destroy(dev, mode); |
7a374350 AJ |
1709 | mode = drm_gtf_mode_complex(dev, hsize, vsize, |
1710 | vrefresh_rate, 0, 0, | |
1711 | drm_gtf2_m(edid), | |
1712 | drm_gtf2_2c(edid), | |
1713 | drm_gtf2_k(edid), | |
1714 | drm_gtf2_2j(edid)); | |
1715 | } | |
1716 | break; | |
5c61259e | 1717 | case LEVEL_CVT: |
d50ba256 DA |
1718 | mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, |
1719 | false); | |
5c61259e ZY |
1720 | break; |
1721 | } | |
f453ba04 DA |
1722 | return mode; |
1723 | } | |
1724 | ||
b58db2c6 AJ |
1725 | /* |
1726 | * EDID is delightfully ambiguous about how interlaced modes are to be | |
1727 | * encoded. Our internal representation is of frame height, but some | |
1728 | * HDTV detailed timings are encoded as field height. | |
1729 | * | |
1730 | * The format list here is from CEA, in frame size. Technically we | |
1731 | * should be checking refresh rate too. Whatever. | |
1732 | */ | |
1733 | static void | |
1734 | drm_mode_do_interlace_quirk(struct drm_display_mode *mode, | |
1735 | struct detailed_pixel_timing *pt) | |
1736 | { | |
1737 | int i; | |
1738 | static const struct { | |
1739 | int w, h; | |
1740 | } cea_interlaced[] = { | |
1741 | { 1920, 1080 }, | |
1742 | { 720, 480 }, | |
1743 | { 1440, 480 }, | |
1744 | { 2880, 480 }, | |
1745 | { 720, 576 }, | |
1746 | { 1440, 576 }, | |
1747 | { 2880, 576 }, | |
1748 | }; | |
b58db2c6 AJ |
1749 | |
1750 | if (!(pt->misc & DRM_EDID_PT_INTERLACED)) | |
1751 | return; | |
1752 | ||
3c581411 | 1753 | for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { |
b58db2c6 AJ |
1754 | if ((mode->hdisplay == cea_interlaced[i].w) && |
1755 | (mode->vdisplay == cea_interlaced[i].h / 2)) { | |
1756 | mode->vdisplay *= 2; | |
1757 | mode->vsync_start *= 2; | |
1758 | mode->vsync_end *= 2; | |
1759 | mode->vtotal *= 2; | |
1760 | mode->vtotal |= 1; | |
1761 | } | |
1762 | } | |
1763 | ||
1764 | mode->flags |= DRM_MODE_FLAG_INTERLACE; | |
1765 | } | |
1766 | ||
f453ba04 DA |
1767 | /** |
1768 | * drm_mode_detailed - create a new mode from an EDID detailed timing section | |
1769 | * @dev: DRM device (needed to create new mode) | |
1770 | * @edid: EDID block | |
1771 | * @timing: EDID detailed timing info | |
1772 | * @quirks: quirks to apply | |
1773 | * | |
1774 | * An EDID detailed timing block contains enough info for us to create and | |
1775 | * return a new struct drm_display_mode. | |
1776 | */ | |
1777 | static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, | |
1778 | struct edid *edid, | |
1779 | struct detailed_timing *timing, | |
1780 | u32 quirks) | |
1781 | { | |
1782 | struct drm_display_mode *mode; | |
1783 | struct detailed_pixel_timing *pt = &timing->data.pixel_data; | |
0454beab MD |
1784 | unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; |
1785 | unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; | |
1786 | unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; | |
1787 | unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; | |
e14cbee4 MD |
1788 | unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; |
1789 | unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; | |
16dad1d7 | 1790 | unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; |
e14cbee4 | 1791 | unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); |
f453ba04 | 1792 | |
fc438966 | 1793 | /* ignore tiny modes */ |
0454beab | 1794 | if (hactive < 64 || vactive < 64) |
fc438966 AJ |
1795 | return NULL; |
1796 | ||
0454beab | 1797 | if (pt->misc & DRM_EDID_PT_STEREO) { |
c7d015f3 | 1798 | DRM_DEBUG_KMS("stereo mode not supported\n"); |
f453ba04 DA |
1799 | return NULL; |
1800 | } | |
0454beab | 1801 | if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { |
c7d015f3 | 1802 | DRM_DEBUG_KMS("composite sync not supported\n"); |
f453ba04 DA |
1803 | } |
1804 | ||
fcb45611 ZY |
1805 | /* it is incorrect if hsync/vsync width is zero */ |
1806 | if (!hsync_pulse_width || !vsync_pulse_width) { | |
1807 | DRM_DEBUG_KMS("Incorrect Detailed timing. " | |
1808 | "Wrong Hsync/Vsync pulse width\n"); | |
1809 | return NULL; | |
1810 | } | |
bc42aabc AJ |
1811 | |
1812 | if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { | |
1813 | mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); | |
1814 | if (!mode) | |
1815 | return NULL; | |
1816 | ||
1817 | goto set_size; | |
1818 | } | |
1819 | ||
f453ba04 DA |
1820 | mode = drm_mode_create(dev); |
1821 | if (!mode) | |
1822 | return NULL; | |
1823 | ||
f453ba04 | 1824 | if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) |
0454beab MD |
1825 | timing->pixel_clock = cpu_to_le16(1088); |
1826 | ||
1827 | mode->clock = le16_to_cpu(timing->pixel_clock) * 10; | |
1828 | ||
1829 | mode->hdisplay = hactive; | |
1830 | mode->hsync_start = mode->hdisplay + hsync_offset; | |
1831 | mode->hsync_end = mode->hsync_start + hsync_pulse_width; | |
1832 | mode->htotal = mode->hdisplay + hblank; | |
1833 | ||
1834 | mode->vdisplay = vactive; | |
1835 | mode->vsync_start = mode->vdisplay + vsync_offset; | |
1836 | mode->vsync_end = mode->vsync_start + vsync_pulse_width; | |
1837 | mode->vtotal = mode->vdisplay + vblank; | |
f453ba04 | 1838 | |
7064fef5 JB |
1839 | /* Some EDIDs have bogus h/vtotal values */ |
1840 | if (mode->hsync_end > mode->htotal) | |
1841 | mode->htotal = mode->hsync_end + 1; | |
1842 | if (mode->vsync_end > mode->vtotal) | |
1843 | mode->vtotal = mode->vsync_end + 1; | |
1844 | ||
b58db2c6 | 1845 | drm_mode_do_interlace_quirk(mode, pt); |
f453ba04 DA |
1846 | |
1847 | if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { | |
0454beab | 1848 | pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE; |
f453ba04 DA |
1849 | } |
1850 | ||
0454beab MD |
1851 | mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? |
1852 | DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; | |
1853 | mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? | |
1854 | DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; | |
f453ba04 | 1855 | |
bc42aabc | 1856 | set_size: |
e14cbee4 MD |
1857 | mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; |
1858 | mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; | |
f453ba04 DA |
1859 | |
1860 | if (quirks & EDID_QUIRK_DETAILED_IN_CM) { | |
1861 | mode->width_mm *= 10; | |
1862 | mode->height_mm *= 10; | |
1863 | } | |
1864 | ||
1865 | if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { | |
1866 | mode->width_mm = edid->width_cm * 10; | |
1867 | mode->height_mm = edid->height_cm * 10; | |
1868 | } | |
1869 | ||
bc42aabc | 1870 | mode->type = DRM_MODE_TYPE_DRIVER; |
c19b3b0f | 1871 | mode->vrefresh = drm_mode_vrefresh(mode); |
bc42aabc AJ |
1872 | drm_mode_set_name(mode); |
1873 | ||
f453ba04 DA |
1874 | return mode; |
1875 | } | |
1876 | ||
b17e52ef | 1877 | static bool |
b1f559ec CW |
1878 | mode_in_hsync_range(const struct drm_display_mode *mode, |
1879 | struct edid *edid, u8 *t) | |
b17e52ef AJ |
1880 | { |
1881 | int hsync, hmin, hmax; | |
1882 | ||
1883 | hmin = t[7]; | |
1884 | if (edid->revision >= 4) | |
1885 | hmin += ((t[4] & 0x04) ? 255 : 0); | |
1886 | hmax = t[8]; | |
1887 | if (edid->revision >= 4) | |
1888 | hmax += ((t[4] & 0x08) ? 255 : 0); | |
07a5e632 | 1889 | hsync = drm_mode_hsync(mode); |
07a5e632 | 1890 | |
b17e52ef AJ |
1891 | return (hsync <= hmax && hsync >= hmin); |
1892 | } | |
1893 | ||
1894 | static bool | |
b1f559ec CW |
1895 | mode_in_vsync_range(const struct drm_display_mode *mode, |
1896 | struct edid *edid, u8 *t) | |
b17e52ef AJ |
1897 | { |
1898 | int vsync, vmin, vmax; | |
1899 | ||
1900 | vmin = t[5]; | |
1901 | if (edid->revision >= 4) | |
1902 | vmin += ((t[4] & 0x01) ? 255 : 0); | |
1903 | vmax = t[6]; | |
1904 | if (edid->revision >= 4) | |
1905 | vmax += ((t[4] & 0x02) ? 255 : 0); | |
1906 | vsync = drm_mode_vrefresh(mode); | |
1907 | ||
1908 | return (vsync <= vmax && vsync >= vmin); | |
1909 | } | |
1910 | ||
1911 | static u32 | |
1912 | range_pixel_clock(struct edid *edid, u8 *t) | |
1913 | { | |
1914 | /* unspecified */ | |
1915 | if (t[9] == 0 || t[9] == 255) | |
1916 | return 0; | |
1917 | ||
1918 | /* 1.4 with CVT support gives us real precision, yay */ | |
1919 | if (edid->revision >= 4 && t[10] == 0x04) | |
1920 | return (t[9] * 10000) - ((t[12] >> 2) * 250); | |
1921 | ||
1922 | /* 1.3 is pathetic, so fuzz up a bit */ | |
1923 | return t[9] * 10000 + 5001; | |
1924 | } | |
1925 | ||
b17e52ef | 1926 | static bool |
b1f559ec | 1927 | mode_in_range(const struct drm_display_mode *mode, struct edid *edid, |
b17e52ef AJ |
1928 | struct detailed_timing *timing) |
1929 | { | |
1930 | u32 max_clock; | |
1931 | u8 *t = (u8 *)timing; | |
1932 | ||
1933 | if (!mode_in_hsync_range(mode, edid, t)) | |
07a5e632 AJ |
1934 | return false; |
1935 | ||
b17e52ef | 1936 | if (!mode_in_vsync_range(mode, edid, t)) |
07a5e632 AJ |
1937 | return false; |
1938 | ||
b17e52ef | 1939 | if ((max_clock = range_pixel_clock(edid, t))) |
07a5e632 AJ |
1940 | if (mode->clock > max_clock) |
1941 | return false; | |
b17e52ef AJ |
1942 | |
1943 | /* 1.4 max horizontal check */ | |
1944 | if (edid->revision >= 4 && t[10] == 0x04) | |
1945 | if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) | |
1946 | return false; | |
1947 | ||
1948 | if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) | |
1949 | return false; | |
07a5e632 AJ |
1950 | |
1951 | return true; | |
1952 | } | |
1953 | ||
7b668ebe TI |
1954 | static bool valid_inferred_mode(const struct drm_connector *connector, |
1955 | const struct drm_display_mode *mode) | |
1956 | { | |
1957 | struct drm_display_mode *m; | |
1958 | bool ok = false; | |
1959 | ||
1960 | list_for_each_entry(m, &connector->probed_modes, head) { | |
1961 | if (mode->hdisplay == m->hdisplay && | |
1962 | mode->vdisplay == m->vdisplay && | |
1963 | drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) | |
1964 | return false; /* duplicated */ | |
1965 | if (mode->hdisplay <= m->hdisplay && | |
1966 | mode->vdisplay <= m->vdisplay) | |
1967 | ok = true; | |
1968 | } | |
1969 | return ok; | |
1970 | } | |
1971 | ||
b17e52ef | 1972 | static int |
cd4cd3de | 1973 | drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid, |
b17e52ef | 1974 | struct detailed_timing *timing) |
07a5e632 AJ |
1975 | { |
1976 | int i, modes = 0; | |
1977 | struct drm_display_mode *newmode; | |
1978 | struct drm_device *dev = connector->dev; | |
1979 | ||
a6b21831 | 1980 | for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { |
7b668ebe TI |
1981 | if (mode_in_range(drm_dmt_modes + i, edid, timing) && |
1982 | valid_inferred_mode(connector, drm_dmt_modes + i)) { | |
07a5e632 AJ |
1983 | newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); |
1984 | if (newmode) { | |
1985 | drm_mode_probed_add(connector, newmode); | |
1986 | modes++; | |
1987 | } | |
1988 | } | |
1989 | } | |
1990 | ||
1991 | return modes; | |
1992 | } | |
1993 | ||
c09dedb7 TI |
1994 | /* fix up 1366x768 mode from 1368x768; |
1995 | * GFT/CVT can't express 1366 width which isn't dividable by 8 | |
1996 | */ | |
1997 | static void fixup_mode_1366x768(struct drm_display_mode *mode) | |
1998 | { | |
1999 | if (mode->hdisplay == 1368 && mode->vdisplay == 768) { | |
2000 | mode->hdisplay = 1366; | |
2001 | mode->hsync_start--; | |
2002 | mode->hsync_end--; | |
2003 | drm_mode_set_name(mode); | |
2004 | } | |
2005 | } | |
2006 | ||
b309bd37 AJ |
2007 | static int |
2008 | drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid, | |
2009 | struct detailed_timing *timing) | |
2010 | { | |
2011 | int i, modes = 0; | |
2012 | struct drm_display_mode *newmode; | |
2013 | struct drm_device *dev = connector->dev; | |
2014 | ||
a6b21831 | 2015 | for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { |
b309bd37 AJ |
2016 | const struct minimode *m = &extra_modes[i]; |
2017 | newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); | |
fc48f169 TI |
2018 | if (!newmode) |
2019 | return modes; | |
b309bd37 | 2020 | |
c09dedb7 | 2021 | fixup_mode_1366x768(newmode); |
7b668ebe TI |
2022 | if (!mode_in_range(newmode, edid, timing) || |
2023 | !valid_inferred_mode(connector, newmode)) { | |
b309bd37 AJ |
2024 | drm_mode_destroy(dev, newmode); |
2025 | continue; | |
2026 | } | |
2027 | ||
2028 | drm_mode_probed_add(connector, newmode); | |
2029 | modes++; | |
2030 | } | |
2031 | ||
2032 | return modes; | |
2033 | } | |
2034 | ||
2035 | static int | |
2036 | drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid, | |
2037 | struct detailed_timing *timing) | |
2038 | { | |
2039 | int i, modes = 0; | |
2040 | struct drm_display_mode *newmode; | |
2041 | struct drm_device *dev = connector->dev; | |
2042 | bool rb = drm_monitor_supports_rb(edid); | |
2043 | ||
a6b21831 | 2044 | for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { |
b309bd37 AJ |
2045 | const struct minimode *m = &extra_modes[i]; |
2046 | newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); | |
fc48f169 TI |
2047 | if (!newmode) |
2048 | return modes; | |
b309bd37 | 2049 | |
c09dedb7 | 2050 | fixup_mode_1366x768(newmode); |
7b668ebe TI |
2051 | if (!mode_in_range(newmode, edid, timing) || |
2052 | !valid_inferred_mode(connector, newmode)) { | |
b309bd37 AJ |
2053 | drm_mode_destroy(dev, newmode); |
2054 | continue; | |
2055 | } | |
2056 | ||
2057 | drm_mode_probed_add(connector, newmode); | |
2058 | modes++; | |
2059 | } | |
2060 | ||
2061 | return modes; | |
2062 | } | |
2063 | ||
13931579 AJ |
2064 | static void |
2065 | do_inferred_modes(struct detailed_timing *timing, void *c) | |
9340d8cf | 2066 | { |
13931579 AJ |
2067 | struct detailed_mode_closure *closure = c; |
2068 | struct detailed_non_pixel *data = &timing->data.other_data; | |
b309bd37 | 2069 | struct detailed_data_monitor_range *range = &data->data.range; |
9340d8cf | 2070 | |
cb21aafe AJ |
2071 | if (data->type != EDID_DETAIL_MONITOR_RANGE) |
2072 | return; | |
2073 | ||
2074 | closure->modes += drm_dmt_modes_for_range(closure->connector, | |
2075 | closure->edid, | |
2076 | timing); | |
b309bd37 AJ |
2077 | |
2078 | if (!version_greater(closure->edid, 1, 1)) | |
2079 | return; /* GTF not defined yet */ | |
2080 | ||
2081 | switch (range->flags) { | |
2082 | case 0x02: /* secondary gtf, XXX could do more */ | |
2083 | case 0x00: /* default gtf */ | |
2084 | closure->modes += drm_gtf_modes_for_range(closure->connector, | |
2085 | closure->edid, | |
2086 | timing); | |
2087 | break; | |
2088 | case 0x04: /* cvt, only in 1.4+ */ | |
2089 | if (!version_greater(closure->edid, 1, 3)) | |
2090 | break; | |
2091 | ||
2092 | closure->modes += drm_cvt_modes_for_range(closure->connector, | |
2093 | closure->edid, | |
2094 | timing); | |
2095 | break; | |
2096 | case 0x01: /* just the ranges, no formula */ | |
2097 | default: | |
2098 | break; | |
2099 | } | |
13931579 | 2100 | } |
69da3015 | 2101 | |
13931579 AJ |
2102 | static int |
2103 | add_inferred_modes(struct drm_connector *connector, struct edid *edid) | |
2104 | { | |
2105 | struct detailed_mode_closure closure = { | |
2106 | connector, edid, 0, 0, 0 | |
2107 | }; | |
9340d8cf | 2108 | |
13931579 AJ |
2109 | if (version_greater(edid, 1, 0)) |
2110 | drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, | |
2111 | &closure); | |
9340d8cf | 2112 | |
13931579 | 2113 | return closure.modes; |
9340d8cf AJ |
2114 | } |
2115 | ||
2255be14 AJ |
2116 | static int |
2117 | drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) | |
2118 | { | |
2119 | int i, j, m, modes = 0; | |
2120 | struct drm_display_mode *mode; | |
2121 | u8 *est = ((u8 *)timing) + 5; | |
2122 | ||
2123 | for (i = 0; i < 6; i++) { | |
891a7469 | 2124 | for (j = 7; j >= 0; j--) { |
2255be14 | 2125 | m = (i * 8) + (7 - j); |
3c581411 | 2126 | if (m >= ARRAY_SIZE(est3_modes)) |
2255be14 AJ |
2127 | break; |
2128 | if (est[i] & (1 << j)) { | |
1d42bbc8 DA |
2129 | mode = drm_mode_find_dmt(connector->dev, |
2130 | est3_modes[m].w, | |
2131 | est3_modes[m].h, | |
f6e252ba AJ |
2132 | est3_modes[m].r, |
2133 | est3_modes[m].rb); | |
2255be14 AJ |
2134 | if (mode) { |
2135 | drm_mode_probed_add(connector, mode); | |
2136 | modes++; | |
2137 | } | |
2138 | } | |
2139 | } | |
2140 | } | |
2141 | ||
2142 | return modes; | |
2143 | } | |
2144 | ||
13931579 AJ |
2145 | static void |
2146 | do_established_modes(struct detailed_timing *timing, void *c) | |
9cf00977 | 2147 | { |
13931579 | 2148 | struct detailed_mode_closure *closure = c; |
9cf00977 | 2149 | struct detailed_non_pixel *data = &timing->data.other_data; |
9cf00977 | 2150 | |
13931579 AJ |
2151 | if (data->type == EDID_DETAIL_EST_TIMINGS) |
2152 | closure->modes += drm_est3_modes(closure->connector, timing); | |
2153 | } | |
9cf00977 | 2154 | |
13931579 AJ |
2155 | /** |
2156 | * add_established_modes - get est. modes from EDID and add them | |
db6cf833 | 2157 | * @connector: connector to add mode(s) to |
13931579 AJ |
2158 | * @edid: EDID block to scan |
2159 | * | |
2160 | * Each EDID block contains a bitmap of the supported "established modes" list | |
2161 | * (defined above). Tease them out and add them to the global modes list. | |
2162 | */ | |
2163 | static int | |
2164 | add_established_modes(struct drm_connector *connector, struct edid *edid) | |
2165 | { | |
2166 | struct drm_device *dev = connector->dev; | |
2167 | unsigned long est_bits = edid->established_timings.t1 | | |
2168 | (edid->established_timings.t2 << 8) | | |
2169 | ((edid->established_timings.mfg_rsvd & 0x80) << 9); | |
2170 | int i, modes = 0; | |
2171 | struct detailed_mode_closure closure = { | |
2172 | connector, edid, 0, 0, 0 | |
2173 | }; | |
9cf00977 | 2174 | |
13931579 AJ |
2175 | for (i = 0; i <= EDID_EST_TIMINGS; i++) { |
2176 | if (est_bits & (1<<i)) { | |
2177 | struct drm_display_mode *newmode; | |
2178 | newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); | |
2179 | if (newmode) { | |
2180 | drm_mode_probed_add(connector, newmode); | |
2181 | modes++; | |
2182 | } | |
2183 | } | |
9cf00977 AJ |
2184 | } |
2185 | ||
13931579 AJ |
2186 | if (version_greater(edid, 1, 0)) |
2187 | drm_for_each_detailed_block((u8 *)edid, | |
2188 | do_established_modes, &closure); | |
2189 | ||
2190 | return modes + closure.modes; | |
2191 | } | |
2192 | ||
2193 | static void | |
2194 | do_standard_modes(struct detailed_timing *timing, void *c) | |
2195 | { | |
2196 | struct detailed_mode_closure *closure = c; | |
2197 | struct detailed_non_pixel *data = &timing->data.other_data; | |
2198 | struct drm_connector *connector = closure->connector; | |
2199 | struct edid *edid = closure->edid; | |
2200 | ||
2201 | if (data->type == EDID_DETAIL_STD_MODES) { | |
2202 | int i; | |
9cf00977 AJ |
2203 | for (i = 0; i < 6; i++) { |
2204 | struct std_timing *std; | |
2205 | struct drm_display_mode *newmode; | |
2206 | ||
2207 | std = &data->data.timings[i]; | |
464fdeca | 2208 | newmode = drm_mode_std(connector, edid, std); |
9cf00977 AJ |
2209 | if (newmode) { |
2210 | drm_mode_probed_add(connector, newmode); | |
13931579 | 2211 | closure->modes++; |
9cf00977 AJ |
2212 | } |
2213 | } | |
9cf00977 | 2214 | } |
9cf00977 AJ |
2215 | } |
2216 | ||
f453ba04 | 2217 | /** |
13931579 | 2218 | * add_standard_modes - get std. modes from EDID and add them |
db6cf833 | 2219 | * @connector: connector to add mode(s) to |
f453ba04 | 2220 | * @edid: EDID block to scan |
f453ba04 | 2221 | * |
13931579 AJ |
2222 | * Standard modes can be calculated using the appropriate standard (DMT, |
2223 | * GTF or CVT. Grab them from @edid and add them to the list. | |
f453ba04 | 2224 | */ |
13931579 AJ |
2225 | static int |
2226 | add_standard_modes(struct drm_connector *connector, struct edid *edid) | |
f453ba04 | 2227 | { |
9cf00977 | 2228 | int i, modes = 0; |
13931579 AJ |
2229 | struct detailed_mode_closure closure = { |
2230 | connector, edid, 0, 0, 0 | |
2231 | }; | |
2232 | ||
2233 | for (i = 0; i < EDID_STD_TIMINGS; i++) { | |
2234 | struct drm_display_mode *newmode; | |
2235 | ||
2236 | newmode = drm_mode_std(connector, edid, | |
464fdeca | 2237 | &edid->standard_timings[i]); |
13931579 AJ |
2238 | if (newmode) { |
2239 | drm_mode_probed_add(connector, newmode); | |
2240 | modes++; | |
2241 | } | |
2242 | } | |
2243 | ||
2244 | if (version_greater(edid, 1, 0)) | |
2245 | drm_for_each_detailed_block((u8 *)edid, do_standard_modes, | |
2246 | &closure); | |
2247 | ||
2248 | /* XXX should also look for standard codes in VTB blocks */ | |
2249 | ||
2250 | return modes + closure.modes; | |
2251 | } | |
f453ba04 | 2252 | |
13931579 AJ |
2253 | static int drm_cvt_modes(struct drm_connector *connector, |
2254 | struct detailed_timing *timing) | |
2255 | { | |
2256 | int i, j, modes = 0; | |
2257 | struct drm_display_mode *newmode; | |
2258 | struct drm_device *dev = connector->dev; | |
2259 | struct cvt_timing *cvt; | |
2260 | const int rates[] = { 60, 85, 75, 60, 50 }; | |
2261 | const u8 empty[3] = { 0, 0, 0 }; | |
a327f6b8 | 2262 | |
13931579 AJ |
2263 | for (i = 0; i < 4; i++) { |
2264 | int uninitialized_var(width), height; | |
2265 | cvt = &(timing->data.other_data.data.cvt[i]); | |
f453ba04 | 2266 | |
13931579 | 2267 | if (!memcmp(cvt->code, empty, 3)) |
9cf00977 | 2268 | continue; |
f453ba04 | 2269 | |
13931579 AJ |
2270 | height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; |
2271 | switch (cvt->code[1] & 0x0c) { | |
2272 | case 0x00: | |
2273 | width = height * 4 / 3; | |
2274 | break; | |
2275 | case 0x04: | |
2276 | width = height * 16 / 9; | |
2277 | break; | |
2278 | case 0x08: | |
2279 | width = height * 16 / 10; | |
2280 | break; | |
2281 | case 0x0c: | |
2282 | width = height * 15 / 9; | |
2283 | break; | |
2284 | } | |
2285 | ||
2286 | for (j = 1; j < 5; j++) { | |
2287 | if (cvt->code[2] & (1 << j)) { | |
2288 | newmode = drm_cvt_mode(dev, width, height, | |
2289 | rates[j], j == 0, | |
2290 | false, false); | |
2291 | if (newmode) { | |
2292 | drm_mode_probed_add(connector, newmode); | |
2293 | modes++; | |
2294 | } | |
2295 | } | |
2296 | } | |
f453ba04 DA |
2297 | } |
2298 | ||
2299 | return modes; | |
2300 | } | |
9cf00977 | 2301 | |
13931579 AJ |
2302 | static void |
2303 | do_cvt_mode(struct detailed_timing *timing, void *c) | |
882f0219 | 2304 | { |
13931579 AJ |
2305 | struct detailed_mode_closure *closure = c; |
2306 | struct detailed_non_pixel *data = &timing->data.other_data; | |
882f0219 | 2307 | |
13931579 AJ |
2308 | if (data->type == EDID_DETAIL_CVT_3BYTE) |
2309 | closure->modes += drm_cvt_modes(closure->connector, timing); | |
2310 | } | |
882f0219 | 2311 | |
13931579 AJ |
2312 | static int |
2313 | add_cvt_modes(struct drm_connector *connector, struct edid *edid) | |
2314 | { | |
2315 | struct detailed_mode_closure closure = { | |
2316 | connector, edid, 0, 0, 0 | |
2317 | }; | |
882f0219 | 2318 | |
13931579 AJ |
2319 | if (version_greater(edid, 1, 2)) |
2320 | drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); | |
882f0219 | 2321 | |
13931579 | 2322 | /* XXX should also look for CVT codes in VTB blocks */ |
882f0219 | 2323 | |
13931579 AJ |
2324 | return closure.modes; |
2325 | } | |
2326 | ||
2327 | static void | |
2328 | do_detailed_mode(struct detailed_timing *timing, void *c) | |
2329 | { | |
2330 | struct detailed_mode_closure *closure = c; | |
2331 | struct drm_display_mode *newmode; | |
2332 | ||
2333 | if (timing->pixel_clock) { | |
2334 | newmode = drm_mode_detailed(closure->connector->dev, | |
2335 | closure->edid, timing, | |
2336 | closure->quirks); | |
2337 | if (!newmode) | |
2338 | return; | |
2339 | ||
2340 | if (closure->preferred) | |
2341 | newmode->type |= DRM_MODE_TYPE_PREFERRED; | |
2342 | ||
2343 | drm_mode_probed_add(closure->connector, newmode); | |
2344 | closure->modes++; | |
2345 | closure->preferred = 0; | |
882f0219 | 2346 | } |
13931579 | 2347 | } |
882f0219 | 2348 | |
13931579 AJ |
2349 | /* |
2350 | * add_detailed_modes - Add modes from detailed timings | |
2351 | * @connector: attached connector | |
2352 | * @edid: EDID block to scan | |
2353 | * @quirks: quirks to apply | |
2354 | */ | |
2355 | static int | |
2356 | add_detailed_modes(struct drm_connector *connector, struct edid *edid, | |
2357 | u32 quirks) | |
2358 | { | |
2359 | struct detailed_mode_closure closure = { | |
2360 | connector, | |
2361 | edid, | |
2362 | 1, | |
2363 | quirks, | |
2364 | 0 | |
2365 | }; | |
2366 | ||
2367 | if (closure.preferred && !version_greater(edid, 1, 3)) | |
2368 | closure.preferred = | |
2369 | (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); | |
2370 | ||
2371 | drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); | |
2372 | ||
2373 | return closure.modes; | |
882f0219 | 2374 | } |
f453ba04 | 2375 | |
8fe9790d | 2376 | #define AUDIO_BLOCK 0x01 |
54ac76f8 | 2377 | #define VIDEO_BLOCK 0x02 |
f23c20c8 | 2378 | #define VENDOR_BLOCK 0x03 |
76adaa34 | 2379 | #define SPEAKER_BLOCK 0x04 |
b1edd6a6 | 2380 | #define VIDEO_CAPABILITY_BLOCK 0x07 |
8fe9790d | 2381 | #define EDID_BASIC_AUDIO (1 << 6) |
a988bc72 LPC |
2382 | #define EDID_CEA_YCRCB444 (1 << 5) |
2383 | #define EDID_CEA_YCRCB422 (1 << 4) | |
b1edd6a6 | 2384 | #define EDID_CEA_VCDB_QS (1 << 6) |
8fe9790d | 2385 | |
d4e4a31d | 2386 | /* |
8fe9790d | 2387 | * Search EDID for CEA extension block. |
f23c20c8 | 2388 | */ |
d4e4a31d | 2389 | static u8 *drm_find_cea_extension(struct edid *edid) |
f23c20c8 | 2390 | { |
8fe9790d ZW |
2391 | u8 *edid_ext = NULL; |
2392 | int i; | |
f23c20c8 ML |
2393 | |
2394 | /* No EDID or EDID extensions */ | |
2395 | if (edid == NULL || edid->extensions == 0) | |
8fe9790d | 2396 | return NULL; |
f23c20c8 | 2397 | |
f23c20c8 | 2398 | /* Find CEA extension */ |
7466f4cc | 2399 | for (i = 0; i < edid->extensions; i++) { |
8fe9790d ZW |
2400 | edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1); |
2401 | if (edid_ext[0] == CEA_EXT) | |
f23c20c8 ML |
2402 | break; |
2403 | } | |
2404 | ||
7466f4cc | 2405 | if (i == edid->extensions) |
8fe9790d ZW |
2406 | return NULL; |
2407 | ||
2408 | return edid_ext; | |
2409 | } | |
2410 | ||
e6e79209 VS |
2411 | /* |
2412 | * Calculate the alternate clock for the CEA mode | |
2413 | * (60Hz vs. 59.94Hz etc.) | |
2414 | */ | |
2415 | static unsigned int | |
2416 | cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) | |
2417 | { | |
2418 | unsigned int clock = cea_mode->clock; | |
2419 | ||
2420 | if (cea_mode->vrefresh % 6 != 0) | |
2421 | return clock; | |
2422 | ||
2423 | /* | |
2424 | * edid_cea_modes contains the 59.94Hz | |
2425 | * variant for 240 and 480 line modes, | |
2426 | * and the 60Hz variant otherwise. | |
2427 | */ | |
2428 | if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) | |
2429 | clock = clock * 1001 / 1000; | |
2430 | else | |
2431 | clock = DIV_ROUND_UP(clock * 1000, 1001); | |
2432 | ||
2433 | return clock; | |
2434 | } | |
2435 | ||
18316c8c TR |
2436 | /** |
2437 | * drm_match_cea_mode - look for a CEA mode matching given mode | |
2438 | * @to_match: display mode | |
2439 | * | |
db6cf833 | 2440 | * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 |
18316c8c | 2441 | * mode. |
a4799037 | 2442 | */ |
18316c8c | 2443 | u8 drm_match_cea_mode(const struct drm_display_mode *to_match) |
a4799037 | 2444 | { |
a4799037 SM |
2445 | u8 mode; |
2446 | ||
a90b590e VS |
2447 | if (!to_match->clock) |
2448 | return 0; | |
2449 | ||
a6b21831 | 2450 | for (mode = 0; mode < ARRAY_SIZE(edid_cea_modes); mode++) { |
a90b590e VS |
2451 | const struct drm_display_mode *cea_mode = &edid_cea_modes[mode]; |
2452 | unsigned int clock1, clock2; | |
2453 | ||
a90b590e | 2454 | /* Check both 60Hz and 59.94Hz */ |
e6e79209 VS |
2455 | clock1 = cea_mode->clock; |
2456 | clock2 = cea_mode_alternate_clock(cea_mode); | |
a4799037 | 2457 | |
a90b590e VS |
2458 | if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || |
2459 | KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && | |
f2ecf2e3 | 2460 | drm_mode_equal_no_clocks_no_stereo(to_match, cea_mode)) |
a4799037 SM |
2461 | return mode + 1; |
2462 | } | |
2463 | return 0; | |
2464 | } | |
2465 | EXPORT_SYMBOL(drm_match_cea_mode); | |
2466 | ||
0967e6a5 VK |
2467 | /** |
2468 | * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to | |
2469 | * the input VIC from the CEA mode list | |
2470 | * @video_code: ID given to each of the CEA modes | |
2471 | * | |
2472 | * Returns picture aspect ratio | |
2473 | */ | |
2474 | enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) | |
2475 | { | |
2476 | /* return picture aspect ratio for video_code - 1 to access the | |
2477 | * right array element | |
2478 | */ | |
2479 | return edid_cea_modes[video_code-1].picture_aspect_ratio; | |
2480 | } | |
2481 | EXPORT_SYMBOL(drm_get_cea_aspect_ratio); | |
2482 | ||
3f2f6533 LD |
2483 | /* |
2484 | * Calculate the alternate clock for HDMI modes (those from the HDMI vendor | |
2485 | * specific block). | |
2486 | * | |
2487 | * It's almost like cea_mode_alternate_clock(), we just need to add an | |
2488 | * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this | |
2489 | * one. | |
2490 | */ | |
2491 | static unsigned int | |
2492 | hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) | |
2493 | { | |
2494 | if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160) | |
2495 | return hdmi_mode->clock; | |
2496 | ||
2497 | return cea_mode_alternate_clock(hdmi_mode); | |
2498 | } | |
2499 | ||
2500 | /* | |
2501 | * drm_match_hdmi_mode - look for a HDMI mode matching given mode | |
2502 | * @to_match: display mode | |
2503 | * | |
2504 | * An HDMI mode is one defined in the HDMI vendor specific block. | |
2505 | * | |
2506 | * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. | |
2507 | */ | |
2508 | static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) | |
2509 | { | |
2510 | u8 mode; | |
2511 | ||
2512 | if (!to_match->clock) | |
2513 | return 0; | |
2514 | ||
2515 | for (mode = 0; mode < ARRAY_SIZE(edid_4k_modes); mode++) { | |
2516 | const struct drm_display_mode *hdmi_mode = &edid_4k_modes[mode]; | |
2517 | unsigned int clock1, clock2; | |
2518 | ||
2519 | /* Make sure to also match alternate clocks */ | |
2520 | clock1 = hdmi_mode->clock; | |
2521 | clock2 = hdmi_mode_alternate_clock(hdmi_mode); | |
2522 | ||
2523 | if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || | |
2524 | KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && | |
f2ecf2e3 | 2525 | drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode)) |
3f2f6533 LD |
2526 | return mode + 1; |
2527 | } | |
2528 | return 0; | |
2529 | } | |
2530 | ||
e6e79209 VS |
2531 | static int |
2532 | add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid) | |
2533 | { | |
2534 | struct drm_device *dev = connector->dev; | |
2535 | struct drm_display_mode *mode, *tmp; | |
2536 | LIST_HEAD(list); | |
2537 | int modes = 0; | |
2538 | ||
2539 | /* Don't add CEA modes if the CEA extension block is missing */ | |
2540 | if (!drm_find_cea_extension(edid)) | |
2541 | return 0; | |
2542 | ||
2543 | /* | |
2544 | * Go through all probed modes and create a new mode | |
2545 | * with the alternate clock for certain CEA modes. | |
2546 | */ | |
2547 | list_for_each_entry(mode, &connector->probed_modes, head) { | |
3f2f6533 | 2548 | const struct drm_display_mode *cea_mode = NULL; |
e6e79209 | 2549 | struct drm_display_mode *newmode; |
3f2f6533 | 2550 | u8 mode_idx = drm_match_cea_mode(mode) - 1; |
e6e79209 VS |
2551 | unsigned int clock1, clock2; |
2552 | ||
3f2f6533 LD |
2553 | if (mode_idx < ARRAY_SIZE(edid_cea_modes)) { |
2554 | cea_mode = &edid_cea_modes[mode_idx]; | |
2555 | clock2 = cea_mode_alternate_clock(cea_mode); | |
2556 | } else { | |
2557 | mode_idx = drm_match_hdmi_mode(mode) - 1; | |
2558 | if (mode_idx < ARRAY_SIZE(edid_4k_modes)) { | |
2559 | cea_mode = &edid_4k_modes[mode_idx]; | |
2560 | clock2 = hdmi_mode_alternate_clock(cea_mode); | |
2561 | } | |
2562 | } | |
e6e79209 | 2563 | |
3f2f6533 LD |
2564 | if (!cea_mode) |
2565 | continue; | |
e6e79209 VS |
2566 | |
2567 | clock1 = cea_mode->clock; | |
e6e79209 VS |
2568 | |
2569 | if (clock1 == clock2) | |
2570 | continue; | |
2571 | ||
2572 | if (mode->clock != clock1 && mode->clock != clock2) | |
2573 | continue; | |
2574 | ||
2575 | newmode = drm_mode_duplicate(dev, cea_mode); | |
2576 | if (!newmode) | |
2577 | continue; | |
2578 | ||
27130212 DL |
2579 | /* Carry over the stereo flags */ |
2580 | newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; | |
2581 | ||
e6e79209 VS |
2582 | /* |
2583 | * The current mode could be either variant. Make | |
2584 | * sure to pick the "other" clock for the new mode. | |
2585 | */ | |
2586 | if (mode->clock != clock1) | |
2587 | newmode->clock = clock1; | |
2588 | else | |
2589 | newmode->clock = clock2; | |
2590 | ||
2591 | list_add_tail(&newmode->head, &list); | |
2592 | } | |
2593 | ||
2594 | list_for_each_entry_safe(mode, tmp, &list, head) { | |
2595 | list_del(&mode->head); | |
2596 | drm_mode_probed_add(connector, mode); | |
2597 | modes++; | |
2598 | } | |
2599 | ||
2600 | return modes; | |
2601 | } | |
a4799037 | 2602 | |
aff04ace TW |
2603 | static struct drm_display_mode * |
2604 | drm_display_mode_from_vic_index(struct drm_connector *connector, | |
2605 | const u8 *video_db, u8 video_len, | |
2606 | u8 video_index) | |
54ac76f8 CS |
2607 | { |
2608 | struct drm_device *dev = connector->dev; | |
aff04ace | 2609 | struct drm_display_mode *newmode; |
13ac3f55 | 2610 | u8 cea_mode; |
54ac76f8 | 2611 | |
aff04ace TW |
2612 | if (video_db == NULL || video_index >= video_len) |
2613 | return NULL; | |
2614 | ||
2615 | /* CEA modes are numbered 1..127 */ | |
2616 | cea_mode = (video_db[video_index] & 127) - 1; | |
2617 | if (cea_mode >= ARRAY_SIZE(edid_cea_modes)) | |
2618 | return NULL; | |
2619 | ||
2620 | newmode = drm_mode_duplicate(dev, &edid_cea_modes[cea_mode]); | |
409bbf1e DL |
2621 | if (!newmode) |
2622 | return NULL; | |
2623 | ||
aff04ace TW |
2624 | newmode->vrefresh = 0; |
2625 | ||
2626 | return newmode; | |
2627 | } | |
2628 | ||
2629 | static int | |
2630 | do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) | |
2631 | { | |
2632 | int i, modes = 0; | |
2633 | ||
2634 | for (i = 0; i < len; i++) { | |
2635 | struct drm_display_mode *mode; | |
2636 | mode = drm_display_mode_from_vic_index(connector, db, len, i); | |
2637 | if (mode) { | |
2638 | drm_mode_probed_add(connector, mode); | |
2639 | modes++; | |
54ac76f8 CS |
2640 | } |
2641 | } | |
2642 | ||
2643 | return modes; | |
2644 | } | |
2645 | ||
c858cfca DL |
2646 | struct stereo_mandatory_mode { |
2647 | int width, height, vrefresh; | |
2648 | unsigned int flags; | |
2649 | }; | |
2650 | ||
2651 | static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { | |
f7e121b7 DL |
2652 | { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, |
2653 | { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, | |
c858cfca DL |
2654 | { 1920, 1080, 50, |
2655 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, | |
2656 | { 1920, 1080, 60, | |
2657 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, | |
f7e121b7 DL |
2658 | { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, |
2659 | { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, | |
2660 | { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, | |
2661 | { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } | |
c858cfca DL |
2662 | }; |
2663 | ||
2664 | static bool | |
2665 | stereo_match_mandatory(const struct drm_display_mode *mode, | |
2666 | const struct stereo_mandatory_mode *stereo_mode) | |
2667 | { | |
2668 | unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; | |
2669 | ||
2670 | return mode->hdisplay == stereo_mode->width && | |
2671 | mode->vdisplay == stereo_mode->height && | |
2672 | interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && | |
2673 | drm_mode_vrefresh(mode) == stereo_mode->vrefresh; | |
2674 | } | |
2675 | ||
c858cfca DL |
2676 | static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) |
2677 | { | |
2678 | struct drm_device *dev = connector->dev; | |
2679 | const struct drm_display_mode *mode; | |
2680 | struct list_head stereo_modes; | |
f7e121b7 | 2681 | int modes = 0, i; |
c858cfca DL |
2682 | |
2683 | INIT_LIST_HEAD(&stereo_modes); | |
2684 | ||
2685 | list_for_each_entry(mode, &connector->probed_modes, head) { | |
f7e121b7 DL |
2686 | for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { |
2687 | const struct stereo_mandatory_mode *mandatory; | |
c858cfca DL |
2688 | struct drm_display_mode *new_mode; |
2689 | ||
f7e121b7 DL |
2690 | if (!stereo_match_mandatory(mode, |
2691 | &stereo_mandatory_modes[i])) | |
2692 | continue; | |
c858cfca | 2693 | |
f7e121b7 | 2694 | mandatory = &stereo_mandatory_modes[i]; |
c858cfca DL |
2695 | new_mode = drm_mode_duplicate(dev, mode); |
2696 | if (!new_mode) | |
2697 | continue; | |
2698 | ||
f7e121b7 | 2699 | new_mode->flags |= mandatory->flags; |
c858cfca DL |
2700 | list_add_tail(&new_mode->head, &stereo_modes); |
2701 | modes++; | |
f7e121b7 | 2702 | } |
c858cfca DL |
2703 | } |
2704 | ||
2705 | list_splice_tail(&stereo_modes, &connector->probed_modes); | |
2706 | ||
2707 | return modes; | |
2708 | } | |
2709 | ||
1deee8d7 DL |
2710 | static int add_hdmi_mode(struct drm_connector *connector, u8 vic) |
2711 | { | |
2712 | struct drm_device *dev = connector->dev; | |
2713 | struct drm_display_mode *newmode; | |
2714 | ||
2715 | vic--; /* VICs start at 1 */ | |
2716 | if (vic >= ARRAY_SIZE(edid_4k_modes)) { | |
2717 | DRM_ERROR("Unknown HDMI VIC: %d\n", vic); | |
2718 | return 0; | |
2719 | } | |
2720 | ||
2721 | newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); | |
2722 | if (!newmode) | |
2723 | return 0; | |
2724 | ||
2725 | drm_mode_probed_add(connector, newmode); | |
2726 | ||
2727 | return 1; | |
2728 | } | |
2729 | ||
fbf46025 TW |
2730 | static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, |
2731 | const u8 *video_db, u8 video_len, u8 video_index) | |
2732 | { | |
fbf46025 TW |
2733 | struct drm_display_mode *newmode; |
2734 | int modes = 0; | |
fbf46025 TW |
2735 | |
2736 | if (structure & (1 << 0)) { | |
aff04ace TW |
2737 | newmode = drm_display_mode_from_vic_index(connector, video_db, |
2738 | video_len, | |
2739 | video_index); | |
fbf46025 TW |
2740 | if (newmode) { |
2741 | newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; | |
2742 | drm_mode_probed_add(connector, newmode); | |
2743 | modes++; | |
2744 | } | |
2745 | } | |
2746 | if (structure & (1 << 6)) { | |
aff04ace TW |
2747 | newmode = drm_display_mode_from_vic_index(connector, video_db, |
2748 | video_len, | |
2749 | video_index); | |
fbf46025 TW |
2750 | if (newmode) { |
2751 | newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; | |
2752 | drm_mode_probed_add(connector, newmode); | |
2753 | modes++; | |
2754 | } | |
2755 | } | |
2756 | if (structure & (1 << 8)) { | |
aff04ace TW |
2757 | newmode = drm_display_mode_from_vic_index(connector, video_db, |
2758 | video_len, | |
2759 | video_index); | |
fbf46025 | 2760 | if (newmode) { |
89570eeb | 2761 | newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; |
fbf46025 TW |
2762 | drm_mode_probed_add(connector, newmode); |
2763 | modes++; | |
2764 | } | |
2765 | } | |
2766 | ||
2767 | return modes; | |
2768 | } | |
2769 | ||
7ebe1963 LD |
2770 | /* |
2771 | * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block | |
2772 | * @connector: connector corresponding to the HDMI sink | |
2773 | * @db: start of the CEA vendor specific block | |
2774 | * @len: length of the CEA block payload, ie. one can access up to db[len] | |
2775 | * | |
c858cfca DL |
2776 | * Parses the HDMI VSDB looking for modes to add to @connector. This function |
2777 | * also adds the stereo 3d modes when applicable. | |
7ebe1963 LD |
2778 | */ |
2779 | static int | |
fbf46025 TW |
2780 | do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, |
2781 | const u8 *video_db, u8 video_len) | |
7ebe1963 | 2782 | { |
0e5083aa | 2783 | int modes = 0, offset = 0, i, multi_present = 0, multi_len; |
fbf46025 TW |
2784 | u8 vic_len, hdmi_3d_len = 0; |
2785 | u16 mask; | |
2786 | u16 structure_all; | |
7ebe1963 LD |
2787 | |
2788 | if (len < 8) | |
2789 | goto out; | |
2790 | ||
2791 | /* no HDMI_Video_Present */ | |
2792 | if (!(db[8] & (1 << 5))) | |
2793 | goto out; | |
2794 | ||
2795 | /* Latency_Fields_Present */ | |
2796 | if (db[8] & (1 << 7)) | |
2797 | offset += 2; | |
2798 | ||
2799 | /* I_Latency_Fields_Present */ | |
2800 | if (db[8] & (1 << 6)) | |
2801 | offset += 2; | |
2802 | ||
2803 | /* the declared length is not long enough for the 2 first bytes | |
2804 | * of additional video format capabilities */ | |
c858cfca | 2805 | if (len < (8 + offset + 2)) |
7ebe1963 LD |
2806 | goto out; |
2807 | ||
c858cfca DL |
2808 | /* 3D_Present */ |
2809 | offset++; | |
fbf46025 | 2810 | if (db[8 + offset] & (1 << 7)) { |
c858cfca DL |
2811 | modes += add_hdmi_mandatory_stereo_modes(connector); |
2812 | ||
fbf46025 TW |
2813 | /* 3D_Multi_present */ |
2814 | multi_present = (db[8 + offset] & 0x60) >> 5; | |
2815 | } | |
2816 | ||
c858cfca | 2817 | offset++; |
7ebe1963 | 2818 | vic_len = db[8 + offset] >> 5; |
fbf46025 | 2819 | hdmi_3d_len = db[8 + offset] & 0x1f; |
7ebe1963 LD |
2820 | |
2821 | for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { | |
7ebe1963 LD |
2822 | u8 vic; |
2823 | ||
2824 | vic = db[9 + offset + i]; | |
1deee8d7 | 2825 | modes += add_hdmi_mode(connector, vic); |
7ebe1963 | 2826 | } |
fbf46025 TW |
2827 | offset += 1 + vic_len; |
2828 | ||
0e5083aa TW |
2829 | if (multi_present == 1) |
2830 | multi_len = 2; | |
2831 | else if (multi_present == 2) | |
2832 | multi_len = 4; | |
2833 | else | |
2834 | multi_len = 0; | |
fbf46025 | 2835 | |
0e5083aa | 2836 | if (len < (8 + offset + hdmi_3d_len - 1)) |
fbf46025 TW |
2837 | goto out; |
2838 | ||
0e5083aa | 2839 | if (hdmi_3d_len < multi_len) |
fbf46025 TW |
2840 | goto out; |
2841 | ||
0e5083aa TW |
2842 | if (multi_present == 1 || multi_present == 2) { |
2843 | /* 3D_Structure_ALL */ | |
2844 | structure_all = (db[8 + offset] << 8) | db[9 + offset]; | |
fbf46025 | 2845 | |
0e5083aa TW |
2846 | /* check if 3D_MASK is present */ |
2847 | if (multi_present == 2) | |
2848 | mask = (db[10 + offset] << 8) | db[11 + offset]; | |
2849 | else | |
2850 | mask = 0xffff; | |
2851 | ||
2852 | for (i = 0; i < 16; i++) { | |
2853 | if (mask & (1 << i)) | |
2854 | modes += add_3d_struct_modes(connector, | |
2855 | structure_all, | |
2856 | video_db, | |
2857 | video_len, i); | |
2858 | } | |
2859 | } | |
2860 | ||
2861 | offset += multi_len; | |
2862 | ||
2863 | for (i = 0; i < (hdmi_3d_len - multi_len); i++) { | |
2864 | int vic_index; | |
2865 | struct drm_display_mode *newmode = NULL; | |
2866 | unsigned int newflag = 0; | |
2867 | bool detail_present; | |
2868 | ||
2869 | detail_present = ((db[8 + offset + i] & 0x0f) > 7); | |
2870 | ||
2871 | if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) | |
2872 | break; | |
2873 | ||
2874 | /* 2D_VIC_order_X */ | |
2875 | vic_index = db[8 + offset + i] >> 4; | |
2876 | ||
2877 | /* 3D_Structure_X */ | |
2878 | switch (db[8 + offset + i] & 0x0f) { | |
2879 | case 0: | |
2880 | newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; | |
2881 | break; | |
2882 | case 6: | |
2883 | newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; | |
2884 | break; | |
2885 | case 8: | |
2886 | /* 3D_Detail_X */ | |
2887 | if ((db[9 + offset + i] >> 4) == 1) | |
2888 | newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; | |
2889 | break; | |
2890 | } | |
2891 | ||
2892 | if (newflag != 0) { | |
2893 | newmode = drm_display_mode_from_vic_index(connector, | |
2894 | video_db, | |
2895 | video_len, | |
2896 | vic_index); | |
2897 | ||
2898 | if (newmode) { | |
2899 | newmode->flags |= newflag; | |
2900 | drm_mode_probed_add(connector, newmode); | |
2901 | modes++; | |
2902 | } | |
2903 | } | |
2904 | ||
2905 | if (detail_present) | |
2906 | i++; | |
fbf46025 | 2907 | } |
7ebe1963 LD |
2908 | |
2909 | out: | |
2910 | return modes; | |
2911 | } | |
2912 | ||
9e50b9d5 VS |
2913 | static int |
2914 | cea_db_payload_len(const u8 *db) | |
2915 | { | |
2916 | return db[0] & 0x1f; | |
2917 | } | |
2918 | ||
2919 | static int | |
2920 | cea_db_tag(const u8 *db) | |
2921 | { | |
2922 | return db[0] >> 5; | |
2923 | } | |
2924 | ||
2925 | static int | |
2926 | cea_revision(const u8 *cea) | |
2927 | { | |
2928 | return cea[1]; | |
2929 | } | |
2930 | ||
2931 | static int | |
2932 | cea_db_offsets(const u8 *cea, int *start, int *end) | |
2933 | { | |
2934 | /* Data block offset in CEA extension block */ | |
2935 | *start = 4; | |
2936 | *end = cea[2]; | |
2937 | if (*end == 0) | |
2938 | *end = 127; | |
2939 | if (*end < 4 || *end > 127) | |
2940 | return -ERANGE; | |
2941 | return 0; | |
2942 | } | |
2943 | ||
7ebe1963 LD |
2944 | static bool cea_db_is_hdmi_vsdb(const u8 *db) |
2945 | { | |
2946 | int hdmi_id; | |
2947 | ||
2948 | if (cea_db_tag(db) != VENDOR_BLOCK) | |
2949 | return false; | |
2950 | ||
2951 | if (cea_db_payload_len(db) < 5) | |
2952 | return false; | |
2953 | ||
2954 | hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); | |
2955 | ||
6cb3b7f1 | 2956 | return hdmi_id == HDMI_IEEE_OUI; |
7ebe1963 LD |
2957 | } |
2958 | ||
9e50b9d5 VS |
2959 | #define for_each_cea_db(cea, i, start, end) \ |
2960 | for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) | |
2961 | ||
54ac76f8 CS |
2962 | static int |
2963 | add_cea_modes(struct drm_connector *connector, struct edid *edid) | |
2964 | { | |
13ac3f55 | 2965 | const u8 *cea = drm_find_cea_extension(edid); |
fbf46025 TW |
2966 | const u8 *db, *hdmi = NULL, *video = NULL; |
2967 | u8 dbl, hdmi_len, video_len = 0; | |
54ac76f8 CS |
2968 | int modes = 0; |
2969 | ||
9e50b9d5 VS |
2970 | if (cea && cea_revision(cea) >= 3) { |
2971 | int i, start, end; | |
2972 | ||
2973 | if (cea_db_offsets(cea, &start, &end)) | |
2974 | return 0; | |
2975 | ||
2976 | for_each_cea_db(cea, i, start, end) { | |
2977 | db = &cea[i]; | |
2978 | dbl = cea_db_payload_len(db); | |
2979 | ||
fbf46025 TW |
2980 | if (cea_db_tag(db) == VIDEO_BLOCK) { |
2981 | video = db + 1; | |
2982 | video_len = dbl; | |
2983 | modes += do_cea_modes(connector, video, dbl); | |
2984 | } | |
c858cfca DL |
2985 | else if (cea_db_is_hdmi_vsdb(db)) { |
2986 | hdmi = db; | |
2987 | hdmi_len = dbl; | |
2988 | } | |
54ac76f8 CS |
2989 | } |
2990 | } | |
2991 | ||
c858cfca DL |
2992 | /* |
2993 | * We parse the HDMI VSDB after having added the cea modes as we will | |
2994 | * be patching their flags when the sink supports stereo 3D. | |
2995 | */ | |
2996 | if (hdmi) | |
fbf46025 TW |
2997 | modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video, |
2998 | video_len); | |
c858cfca | 2999 | |
54ac76f8 CS |
3000 | return modes; |
3001 | } | |
3002 | ||
76adaa34 | 3003 | static void |
8504072a | 3004 | parse_hdmi_vsdb(struct drm_connector *connector, const u8 *db) |
76adaa34 | 3005 | { |
8504072a | 3006 | u8 len = cea_db_payload_len(db); |
76adaa34 | 3007 | |
8504072a VS |
3008 | if (len >= 6) { |
3009 | connector->eld[5] |= (db[6] >> 7) << 1; /* Supports_AI */ | |
3010 | connector->dvi_dual = db[6] & 1; | |
3011 | } | |
3012 | if (len >= 7) | |
3013 | connector->max_tmds_clock = db[7] * 5; | |
3014 | if (len >= 8) { | |
3015 | connector->latency_present[0] = db[8] >> 7; | |
3016 | connector->latency_present[1] = (db[8] >> 6) & 1; | |
3017 | } | |
3018 | if (len >= 9) | |
3019 | connector->video_latency[0] = db[9]; | |
3020 | if (len >= 10) | |
3021 | connector->audio_latency[0] = db[10]; | |
3022 | if (len >= 11) | |
3023 | connector->video_latency[1] = db[11]; | |
3024 | if (len >= 12) | |
3025 | connector->audio_latency[1] = db[12]; | |
76adaa34 | 3026 | |
670c1ef6 | 3027 | DRM_DEBUG_KMS("HDMI: DVI dual %d, " |
76adaa34 WF |
3028 | "max TMDS clock %d, " |
3029 | "latency present %d %d, " | |
3030 | "video latency %d %d, " | |
3031 | "audio latency %d %d\n", | |
3032 | connector->dvi_dual, | |
3033 | connector->max_tmds_clock, | |
3034 | (int) connector->latency_present[0], | |
3035 | (int) connector->latency_present[1], | |
3036 | connector->video_latency[0], | |
3037 | connector->video_latency[1], | |
3038 | connector->audio_latency[0], | |
3039 | connector->audio_latency[1]); | |
3040 | } | |
3041 | ||
3042 | static void | |
3043 | monitor_name(struct detailed_timing *t, void *data) | |
3044 | { | |
3045 | if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME) | |
3046 | *(u8 **)data = t->data.other_data.data.str.str; | |
14f77fdd VS |
3047 | } |
3048 | ||
76adaa34 WF |
3049 | /** |
3050 | * drm_edid_to_eld - build ELD from EDID | |
3051 | * @connector: connector corresponding to the HDMI/DP sink | |
3052 | * @edid: EDID to parse | |
3053 | * | |
db6cf833 TR |
3054 | * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The |
3055 | * Conn_Type, HDCP and Port_ID ELD fields are left for the graphics driver to | |
3056 | * fill in. | |
76adaa34 WF |
3057 | */ |
3058 | void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) | |
3059 | { | |
3060 | uint8_t *eld = connector->eld; | |
3061 | u8 *cea; | |
3062 | u8 *name; | |
3063 | u8 *db; | |
3064 | int sad_count = 0; | |
3065 | int mnl; | |
3066 | int dbl; | |
3067 | ||
3068 | memset(eld, 0, sizeof(connector->eld)); | |
3069 | ||
3070 | cea = drm_find_cea_extension(edid); | |
3071 | if (!cea) { | |
3072 | DRM_DEBUG_KMS("ELD: no CEA Extension found\n"); | |
3073 | return; | |
3074 | } | |
3075 | ||
3076 | name = NULL; | |
3077 | drm_for_each_detailed_block((u8 *)edid, monitor_name, &name); | |
3078 | for (mnl = 0; name && mnl < 13; mnl++) { | |
3079 | if (name[mnl] == 0x0a) | |
3080 | break; | |
3081 | eld[20 + mnl] = name[mnl]; | |
3082 | } | |
3083 | eld[4] = (cea[1] << 5) | mnl; | |
3084 | DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20); | |
3085 | ||
3086 | eld[0] = 2 << 3; /* ELD version: 2 */ | |
3087 | ||
3088 | eld[16] = edid->mfg_id[0]; | |
3089 | eld[17] = edid->mfg_id[1]; | |
3090 | eld[18] = edid->prod_code[0]; | |
3091 | eld[19] = edid->prod_code[1]; | |
3092 | ||
9e50b9d5 VS |
3093 | if (cea_revision(cea) >= 3) { |
3094 | int i, start, end; | |
3095 | ||
3096 | if (cea_db_offsets(cea, &start, &end)) { | |
3097 | start = 0; | |
3098 | end = 0; | |
3099 | } | |
3100 | ||
3101 | for_each_cea_db(cea, i, start, end) { | |
3102 | db = &cea[i]; | |
3103 | dbl = cea_db_payload_len(db); | |
3104 | ||
3105 | switch (cea_db_tag(db)) { | |
a0ab734d CS |
3106 | case AUDIO_BLOCK: |
3107 | /* Audio Data Block, contains SADs */ | |
3108 | sad_count = dbl / 3; | |
9e50b9d5 VS |
3109 | if (dbl >= 1) |
3110 | memcpy(eld + 20 + mnl, &db[1], dbl); | |
a0ab734d CS |
3111 | break; |
3112 | case SPEAKER_BLOCK: | |
9e50b9d5 VS |
3113 | /* Speaker Allocation Data Block */ |
3114 | if (dbl >= 1) | |
3115 | eld[7] = db[1]; | |
a0ab734d CS |
3116 | break; |
3117 | case VENDOR_BLOCK: | |
3118 | /* HDMI Vendor-Specific Data Block */ | |
14f77fdd | 3119 | if (cea_db_is_hdmi_vsdb(db)) |
a0ab734d CS |
3120 | parse_hdmi_vsdb(connector, db); |
3121 | break; | |
3122 | default: | |
3123 | break; | |
3124 | } | |
76adaa34 | 3125 | } |
9e50b9d5 | 3126 | } |
76adaa34 WF |
3127 | eld[5] |= sad_count << 4; |
3128 | eld[2] = (20 + mnl + sad_count * 3 + 3) / 4; | |
3129 | ||
3130 | DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", (int)eld[2], sad_count); | |
3131 | } | |
3132 | EXPORT_SYMBOL(drm_edid_to_eld); | |
3133 | ||
fe214163 RM |
3134 | /** |
3135 | * drm_edid_to_sad - extracts SADs from EDID | |
3136 | * @edid: EDID to parse | |
3137 | * @sads: pointer that will be set to the extracted SADs | |
3138 | * | |
3139 | * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. | |
fe214163 | 3140 | * |
db6cf833 TR |
3141 | * Note: The returned pointer needs to be freed using kfree(). |
3142 | * | |
3143 | * Return: The number of found SADs or negative number on error. | |
fe214163 RM |
3144 | */ |
3145 | int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads) | |
3146 | { | |
3147 | int count = 0; | |
3148 | int i, start, end, dbl; | |
3149 | u8 *cea; | |
3150 | ||
3151 | cea = drm_find_cea_extension(edid); | |
3152 | if (!cea) { | |
3153 | DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); | |
3154 | return -ENOENT; | |
3155 | } | |
3156 | ||
3157 | if (cea_revision(cea) < 3) { | |
3158 | DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); | |
3159 | return -ENOTSUPP; | |
3160 | } | |
3161 | ||
3162 | if (cea_db_offsets(cea, &start, &end)) { | |
3163 | DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); | |
3164 | return -EPROTO; | |
3165 | } | |
3166 | ||
3167 | for_each_cea_db(cea, i, start, end) { | |
3168 | u8 *db = &cea[i]; | |
3169 | ||
3170 | if (cea_db_tag(db) == AUDIO_BLOCK) { | |
3171 | int j; | |
3172 | dbl = cea_db_payload_len(db); | |
3173 | ||
3174 | count = dbl / 3; /* SAD is 3B */ | |
3175 | *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); | |
3176 | if (!*sads) | |
3177 | return -ENOMEM; | |
3178 | for (j = 0; j < count; j++) { | |
3179 | u8 *sad = &db[1 + j * 3]; | |
3180 | ||
3181 | (*sads)[j].format = (sad[0] & 0x78) >> 3; | |
3182 | (*sads)[j].channels = sad[0] & 0x7; | |
3183 | (*sads)[j].freq = sad[1] & 0x7F; | |
3184 | (*sads)[j].byte2 = sad[2]; | |
3185 | } | |
3186 | break; | |
3187 | } | |
3188 | } | |
3189 | ||
3190 | return count; | |
3191 | } | |
3192 | EXPORT_SYMBOL(drm_edid_to_sad); | |
3193 | ||
d105f476 AD |
3194 | /** |
3195 | * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID | |
3196 | * @edid: EDID to parse | |
3197 | * @sadb: pointer to the speaker block | |
3198 | * | |
3199 | * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. | |
d105f476 | 3200 | * |
db6cf833 TR |
3201 | * Note: The returned pointer needs to be freed using kfree(). |
3202 | * | |
3203 | * Return: The number of found Speaker Allocation Blocks or negative number on | |
3204 | * error. | |
d105f476 AD |
3205 | */ |
3206 | int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb) | |
3207 | { | |
3208 | int count = 0; | |
3209 | int i, start, end, dbl; | |
3210 | const u8 *cea; | |
3211 | ||
3212 | cea = drm_find_cea_extension(edid); | |
3213 | if (!cea) { | |
3214 | DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); | |
3215 | return -ENOENT; | |
3216 | } | |
3217 | ||
3218 | if (cea_revision(cea) < 3) { | |
3219 | DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); | |
3220 | return -ENOTSUPP; | |
3221 | } | |
3222 | ||
3223 | if (cea_db_offsets(cea, &start, &end)) { | |
3224 | DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); | |
3225 | return -EPROTO; | |
3226 | } | |
3227 | ||
3228 | for_each_cea_db(cea, i, start, end) { | |
3229 | const u8 *db = &cea[i]; | |
3230 | ||
3231 | if (cea_db_tag(db) == SPEAKER_BLOCK) { | |
3232 | dbl = cea_db_payload_len(db); | |
3233 | ||
3234 | /* Speaker Allocation Data Block */ | |
3235 | if (dbl == 3) { | |
89086bca | 3236 | *sadb = kmemdup(&db[1], dbl, GFP_KERNEL); |
618e3776 AD |
3237 | if (!*sadb) |
3238 | return -ENOMEM; | |
d105f476 AD |
3239 | count = dbl; |
3240 | break; | |
3241 | } | |
3242 | } | |
3243 | } | |
3244 | ||
3245 | return count; | |
3246 | } | |
3247 | EXPORT_SYMBOL(drm_edid_to_speaker_allocation); | |
3248 | ||
76adaa34 | 3249 | /** |
db6cf833 | 3250 | * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay |
76adaa34 WF |
3251 | * @connector: connector associated with the HDMI/DP sink |
3252 | * @mode: the display mode | |
db6cf833 TR |
3253 | * |
3254 | * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if | |
3255 | * the sink doesn't support audio or video. | |
76adaa34 WF |
3256 | */ |
3257 | int drm_av_sync_delay(struct drm_connector *connector, | |
3258 | struct drm_display_mode *mode) | |
3259 | { | |
3260 | int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); | |
3261 | int a, v; | |
3262 | ||
3263 | if (!connector->latency_present[0]) | |
3264 | return 0; | |
3265 | if (!connector->latency_present[1]) | |
3266 | i = 0; | |
3267 | ||
3268 | a = connector->audio_latency[i]; | |
3269 | v = connector->video_latency[i]; | |
3270 | ||
3271 | /* | |
3272 | * HDMI/DP sink doesn't support audio or video? | |
3273 | */ | |
3274 | if (a == 255 || v == 255) | |
3275 | return 0; | |
3276 | ||
3277 | /* | |
3278 | * Convert raw EDID values to millisecond. | |
3279 | * Treat unknown latency as 0ms. | |
3280 | */ | |
3281 | if (a) | |
3282 | a = min(2 * (a - 1), 500); | |
3283 | if (v) | |
3284 | v = min(2 * (v - 1), 500); | |
3285 | ||
3286 | return max(v - a, 0); | |
3287 | } | |
3288 | EXPORT_SYMBOL(drm_av_sync_delay); | |
3289 | ||
3290 | /** | |
3291 | * drm_select_eld - select one ELD from multiple HDMI/DP sinks | |
3292 | * @encoder: the encoder just changed display mode | |
3293 | * @mode: the adjusted display mode | |
3294 | * | |
3295 | * It's possible for one encoder to be associated with multiple HDMI/DP sinks. | |
3296 | * The policy is now hard coded to simply use the first HDMI/DP sink's ELD. | |
db6cf833 TR |
3297 | * |
3298 | * Return: The connector associated with the first HDMI/DP sink that has ELD | |
3299 | * attached to it. | |
76adaa34 WF |
3300 | */ |
3301 | struct drm_connector *drm_select_eld(struct drm_encoder *encoder, | |
3302 | struct drm_display_mode *mode) | |
3303 | { | |
3304 | struct drm_connector *connector; | |
3305 | struct drm_device *dev = encoder->dev; | |
3306 | ||
6e9f798d | 3307 | WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); |
008f4045 | 3308 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
6e9f798d | 3309 | |
76adaa34 WF |
3310 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) |
3311 | if (connector->encoder == encoder && connector->eld[0]) | |
3312 | return connector; | |
3313 | ||
3314 | return NULL; | |
3315 | } | |
3316 | EXPORT_SYMBOL(drm_select_eld); | |
3317 | ||
8fe9790d | 3318 | /** |
db6cf833 | 3319 | * drm_detect_hdmi_monitor - detect whether monitor is HDMI |
8fe9790d ZW |
3320 | * @edid: monitor EDID information |
3321 | * | |
3322 | * Parse the CEA extension according to CEA-861-B. | |
db6cf833 TR |
3323 | * |
3324 | * Return: True if the monitor is HDMI, false if not or unknown. | |
8fe9790d ZW |
3325 | */ |
3326 | bool drm_detect_hdmi_monitor(struct edid *edid) | |
3327 | { | |
3328 | u8 *edid_ext; | |
14f77fdd | 3329 | int i; |
8fe9790d | 3330 | int start_offset, end_offset; |
8fe9790d ZW |
3331 | |
3332 | edid_ext = drm_find_cea_extension(edid); | |
3333 | if (!edid_ext) | |
14f77fdd | 3334 | return false; |
f23c20c8 | 3335 | |
9e50b9d5 | 3336 | if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) |
14f77fdd | 3337 | return false; |
f23c20c8 ML |
3338 | |
3339 | /* | |
3340 | * Because HDMI identifier is in Vendor Specific Block, | |
3341 | * search it from all data blocks of CEA extension. | |
3342 | */ | |
9e50b9d5 | 3343 | for_each_cea_db(edid_ext, i, start_offset, end_offset) { |
14f77fdd VS |
3344 | if (cea_db_is_hdmi_vsdb(&edid_ext[i])) |
3345 | return true; | |
f23c20c8 ML |
3346 | } |
3347 | ||
14f77fdd | 3348 | return false; |
f23c20c8 ML |
3349 | } |
3350 | EXPORT_SYMBOL(drm_detect_hdmi_monitor); | |
3351 | ||
8fe9790d ZW |
3352 | /** |
3353 | * drm_detect_monitor_audio - check monitor audio capability | |
fc66811c | 3354 | * @edid: EDID block to scan |
8fe9790d ZW |
3355 | * |
3356 | * Monitor should have CEA extension block. | |
3357 | * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic | |
3358 | * audio' only. If there is any audio extension block and supported | |
3359 | * audio format, assume at least 'basic audio' support, even if 'basic | |
3360 | * audio' is not defined in EDID. | |
3361 | * | |
db6cf833 | 3362 | * Return: True if the monitor supports audio, false otherwise. |
8fe9790d ZW |
3363 | */ |
3364 | bool drm_detect_monitor_audio(struct edid *edid) | |
3365 | { | |
3366 | u8 *edid_ext; | |
3367 | int i, j; | |
3368 | bool has_audio = false; | |
3369 | int start_offset, end_offset; | |
3370 | ||
3371 | edid_ext = drm_find_cea_extension(edid); | |
3372 | if (!edid_ext) | |
3373 | goto end; | |
3374 | ||
3375 | has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); | |
3376 | ||
3377 | if (has_audio) { | |
3378 | DRM_DEBUG_KMS("Monitor has basic audio support\n"); | |
3379 | goto end; | |
3380 | } | |
3381 | ||
9e50b9d5 VS |
3382 | if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) |
3383 | goto end; | |
8fe9790d | 3384 | |
9e50b9d5 VS |
3385 | for_each_cea_db(edid_ext, i, start_offset, end_offset) { |
3386 | if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { | |
8fe9790d | 3387 | has_audio = true; |
9e50b9d5 | 3388 | for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3) |
8fe9790d ZW |
3389 | DRM_DEBUG_KMS("CEA audio format %d\n", |
3390 | (edid_ext[i + j] >> 3) & 0xf); | |
3391 | goto end; | |
3392 | } | |
3393 | } | |
3394 | end: | |
3395 | return has_audio; | |
3396 | } | |
3397 | EXPORT_SYMBOL(drm_detect_monitor_audio); | |
3398 | ||
b1edd6a6 VS |
3399 | /** |
3400 | * drm_rgb_quant_range_selectable - is RGB quantization range selectable? | |
fc66811c | 3401 | * @edid: EDID block to scan |
b1edd6a6 VS |
3402 | * |
3403 | * Check whether the monitor reports the RGB quantization range selection | |
3404 | * as supported. The AVI infoframe can then be used to inform the monitor | |
3405 | * which quantization range (full or limited) is used. | |
db6cf833 TR |
3406 | * |
3407 | * Return: True if the RGB quantization range is selectable, false otherwise. | |
b1edd6a6 VS |
3408 | */ |
3409 | bool drm_rgb_quant_range_selectable(struct edid *edid) | |
3410 | { | |
3411 | u8 *edid_ext; | |
3412 | int i, start, end; | |
3413 | ||
3414 | edid_ext = drm_find_cea_extension(edid); | |
3415 | if (!edid_ext) | |
3416 | return false; | |
3417 | ||
3418 | if (cea_db_offsets(edid_ext, &start, &end)) | |
3419 | return false; | |
3420 | ||
3421 | for_each_cea_db(edid_ext, i, start, end) { | |
3422 | if (cea_db_tag(&edid_ext[i]) == VIDEO_CAPABILITY_BLOCK && | |
3423 | cea_db_payload_len(&edid_ext[i]) == 2) { | |
3424 | DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]); | |
3425 | return edid_ext[i + 2] & EDID_CEA_VCDB_QS; | |
3426 | } | |
3427 | } | |
3428 | ||
3429 | return false; | |
3430 | } | |
3431 | EXPORT_SYMBOL(drm_rgb_quant_range_selectable); | |
3432 | ||
d0c94692 MK |
3433 | /** |
3434 | * drm_assign_hdmi_deep_color_info - detect whether monitor supports | |
3435 | * hdmi deep color modes and update drm_display_info if so. | |
3436 | * | |
3437 | * @edid: monitor EDID information | |
3438 | * @info: Updated with maximum supported deep color bpc and color format | |
3439 | * if deep color supported. | |
3440 | * | |
3441 | * Parse the CEA extension according to CEA-861-B. | |
3442 | * Return true if HDMI deep color supported, false if not or unknown. | |
3443 | */ | |
3444 | static bool drm_assign_hdmi_deep_color_info(struct edid *edid, | |
3445 | struct drm_display_info *info, | |
3446 | struct drm_connector *connector) | |
3447 | { | |
3448 | u8 *edid_ext, *hdmi; | |
3449 | int i; | |
3450 | int start_offset, end_offset; | |
3451 | unsigned int dc_bpc = 0; | |
3452 | ||
3453 | edid_ext = drm_find_cea_extension(edid); | |
3454 | if (!edid_ext) | |
3455 | return false; | |
3456 | ||
3457 | if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) | |
3458 | return false; | |
3459 | ||
3460 | /* | |
3461 | * Because HDMI identifier is in Vendor Specific Block, | |
3462 | * search it from all data blocks of CEA extension. | |
3463 | */ | |
3464 | for_each_cea_db(edid_ext, i, start_offset, end_offset) { | |
3465 | if (cea_db_is_hdmi_vsdb(&edid_ext[i])) { | |
3466 | /* HDMI supports at least 8 bpc */ | |
3467 | info->bpc = 8; | |
3468 | ||
3469 | hdmi = &edid_ext[i]; | |
3470 | if (cea_db_payload_len(hdmi) < 6) | |
3471 | return false; | |
3472 | ||
3473 | if (hdmi[6] & DRM_EDID_HDMI_DC_30) { | |
3474 | dc_bpc = 10; | |
5d02626d | 3475 | info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30; |
d0c94692 | 3476 | DRM_DEBUG("%s: HDMI sink does deep color 30.\n", |
25933820 | 3477 | connector->name); |
d0c94692 MK |
3478 | } |
3479 | ||
3480 | if (hdmi[6] & DRM_EDID_HDMI_DC_36) { | |
3481 | dc_bpc = 12; | |
5d02626d | 3482 | info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36; |
d0c94692 | 3483 | DRM_DEBUG("%s: HDMI sink does deep color 36.\n", |
25933820 | 3484 | connector->name); |
d0c94692 MK |
3485 | } |
3486 | ||
3487 | if (hdmi[6] & DRM_EDID_HDMI_DC_48) { | |
3488 | dc_bpc = 16; | |
5d02626d | 3489 | info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48; |
d0c94692 | 3490 | DRM_DEBUG("%s: HDMI sink does deep color 48.\n", |
25933820 | 3491 | connector->name); |
d0c94692 MK |
3492 | } |
3493 | ||
3494 | if (dc_bpc > 0) { | |
3495 | DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n", | |
25933820 | 3496 | connector->name, dc_bpc); |
d0c94692 MK |
3497 | info->bpc = dc_bpc; |
3498 | ||
3499 | /* | |
3500 | * Deep color support mandates RGB444 support for all video | |
3501 | * modes and forbids YCRCB422 support for all video modes per | |
3502 | * HDMI 1.3 spec. | |
3503 | */ | |
3504 | info->color_formats = DRM_COLOR_FORMAT_RGB444; | |
3505 | ||
3506 | /* YCRCB444 is optional according to spec. */ | |
3507 | if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { | |
3508 | info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; | |
3509 | DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n", | |
25933820 | 3510 | connector->name); |
d0c94692 MK |
3511 | } |
3512 | ||
3513 | /* | |
3514 | * Spec says that if any deep color mode is supported at all, | |
3515 | * then deep color 36 bit must be supported. | |
3516 | */ | |
3517 | if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { | |
3518 | DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n", | |
25933820 | 3519 | connector->name); |
d0c94692 MK |
3520 | } |
3521 | ||
3522 | return true; | |
3523 | } | |
3524 | else { | |
3525 | DRM_DEBUG("%s: No deep color support on this HDMI sink.\n", | |
25933820 | 3526 | connector->name); |
d0c94692 MK |
3527 | } |
3528 | } | |
3529 | } | |
3530 | ||
3531 | return false; | |
3532 | } | |
3533 | ||
3b11228b JB |
3534 | /** |
3535 | * drm_add_display_info - pull display info out if present | |
3536 | * @edid: EDID data | |
3537 | * @info: display info (attached to connector) | |
d0c94692 | 3538 | * @connector: connector whose edid is used to build display info |
3b11228b JB |
3539 | * |
3540 | * Grab any available display info and stuff it into the drm_display_info | |
3541 | * structure that's part of the connector. Useful for tracking bpp and | |
3542 | * color spaces. | |
3543 | */ | |
3544 | static void drm_add_display_info(struct edid *edid, | |
d0c94692 MK |
3545 | struct drm_display_info *info, |
3546 | struct drm_connector *connector) | |
3b11228b | 3547 | { |
ebec9a7b JB |
3548 | u8 *edid_ext; |
3549 | ||
3b11228b JB |
3550 | info->width_mm = edid->width_cm * 10; |
3551 | info->height_mm = edid->height_cm * 10; | |
3552 | ||
3553 | /* driver figures it out in this case */ | |
3554 | info->bpc = 0; | |
da05a5a7 | 3555 | info->color_formats = 0; |
3b11228b | 3556 | |
a988bc72 | 3557 | if (edid->revision < 3) |
3b11228b JB |
3558 | return; |
3559 | ||
3560 | if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) | |
3561 | return; | |
3562 | ||
a988bc72 LPC |
3563 | /* Get data from CEA blocks if present */ |
3564 | edid_ext = drm_find_cea_extension(edid); | |
3565 | if (edid_ext) { | |
3566 | info->cea_rev = edid_ext[1]; | |
3567 | ||
3568 | /* The existence of a CEA block should imply RGB support */ | |
3569 | info->color_formats = DRM_COLOR_FORMAT_RGB444; | |
3570 | if (edid_ext[3] & EDID_CEA_YCRCB444) | |
3571 | info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; | |
3572 | if (edid_ext[3] & EDID_CEA_YCRCB422) | |
3573 | info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; | |
3574 | } | |
3575 | ||
d0c94692 MK |
3576 | /* HDMI deep color modes supported? Assign to info, if so */ |
3577 | drm_assign_hdmi_deep_color_info(edid, info, connector); | |
3578 | ||
a988bc72 LPC |
3579 | /* Only defined for 1.4 with digital displays */ |
3580 | if (edid->revision < 4) | |
3581 | return; | |
3582 | ||
3b11228b JB |
3583 | switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { |
3584 | case DRM_EDID_DIGITAL_DEPTH_6: | |
3585 | info->bpc = 6; | |
3586 | break; | |
3587 | case DRM_EDID_DIGITAL_DEPTH_8: | |
3588 | info->bpc = 8; | |
3589 | break; | |
3590 | case DRM_EDID_DIGITAL_DEPTH_10: | |
3591 | info->bpc = 10; | |
3592 | break; | |
3593 | case DRM_EDID_DIGITAL_DEPTH_12: | |
3594 | info->bpc = 12; | |
3595 | break; | |
3596 | case DRM_EDID_DIGITAL_DEPTH_14: | |
3597 | info->bpc = 14; | |
3598 | break; | |
3599 | case DRM_EDID_DIGITAL_DEPTH_16: | |
3600 | info->bpc = 16; | |
3601 | break; | |
3602 | case DRM_EDID_DIGITAL_DEPTH_UNDEF: | |
3603 | default: | |
3604 | info->bpc = 0; | |
3605 | break; | |
3606 | } | |
da05a5a7 | 3607 | |
d0c94692 | 3608 | DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n", |
25933820 | 3609 | connector->name, info->bpc); |
d0c94692 | 3610 | |
a988bc72 | 3611 | info->color_formats |= DRM_COLOR_FORMAT_RGB444; |
ee58808d LPC |
3612 | if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) |
3613 | info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; | |
3614 | if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) | |
3615 | info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; | |
3b11228b JB |
3616 | } |
3617 | ||
f453ba04 DA |
3618 | /** |
3619 | * drm_add_edid_modes - add modes from EDID data, if available | |
3620 | * @connector: connector we're probing | |
db6cf833 | 3621 | * @edid: EDID data |
f453ba04 DA |
3622 | * |
3623 | * Add the specified modes to the connector's mode list. | |
3624 | * | |
db6cf833 | 3625 | * Return: The number of modes added or 0 if we couldn't find any. |
f453ba04 DA |
3626 | */ |
3627 | int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) | |
3628 | { | |
3629 | int num_modes = 0; | |
3630 | u32 quirks; | |
3631 | ||
3632 | if (edid == NULL) { | |
3633 | return 0; | |
3634 | } | |
3c537889 | 3635 | if (!drm_edid_is_valid(edid)) { |
dcdb1674 | 3636 | dev_warn(connector->dev->dev, "%s: EDID invalid.\n", |
25933820 | 3637 | connector->name); |
f453ba04 DA |
3638 | return 0; |
3639 | } | |
3640 | ||
3641 | quirks = edid_get_quirks(edid); | |
3642 | ||
c867df70 AJ |
3643 | /* |
3644 | * EDID spec says modes should be preferred in this order: | |
3645 | * - preferred detailed mode | |
3646 | * - other detailed modes from base block | |
3647 | * - detailed modes from extension blocks | |
3648 | * - CVT 3-byte code modes | |
3649 | * - standard timing codes | |
3650 | * - established timing codes | |
3651 | * - modes inferred from GTF or CVT range information | |
3652 | * | |
13931579 | 3653 | * We get this pretty much right. |
c867df70 AJ |
3654 | * |
3655 | * XXX order for additional mode types in extension blocks? | |
3656 | */ | |
13931579 AJ |
3657 | num_modes += add_detailed_modes(connector, edid, quirks); |
3658 | num_modes += add_cvt_modes(connector, edid); | |
c867df70 AJ |
3659 | num_modes += add_standard_modes(connector, edid); |
3660 | num_modes += add_established_modes(connector, edid); | |
196e077d PZ |
3661 | if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) |
3662 | num_modes += add_inferred_modes(connector, edid); | |
54ac76f8 | 3663 | num_modes += add_cea_modes(connector, edid); |
e6e79209 | 3664 | num_modes += add_alternate_cea_modes(connector, edid); |
f453ba04 DA |
3665 | |
3666 | if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) | |
3667 | edid_fixup_preferred(connector, quirks); | |
3668 | ||
d0c94692 | 3669 | drm_add_display_info(edid, &connector->display_info, connector); |
f453ba04 | 3670 | |
49d45a31 RM |
3671 | if (quirks & EDID_QUIRK_FORCE_8BPC) |
3672 | connector->display_info.bpc = 8; | |
3673 | ||
bc5b9641 MK |
3674 | if (quirks & EDID_QUIRK_FORCE_12BPC) |
3675 | connector->display_info.bpc = 12; | |
3676 | ||
f453ba04 DA |
3677 | return num_modes; |
3678 | } | |
3679 | EXPORT_SYMBOL(drm_add_edid_modes); | |
f0fda0a4 ZY |
3680 | |
3681 | /** | |
3682 | * drm_add_modes_noedid - add modes for the connectors without EDID | |
3683 | * @connector: connector we're probing | |
3684 | * @hdisplay: the horizontal display limit | |
3685 | * @vdisplay: the vertical display limit | |
3686 | * | |
3687 | * Add the specified modes to the connector's mode list. Only when the | |
3688 | * hdisplay/vdisplay is not beyond the given limit, it will be added. | |
3689 | * | |
db6cf833 | 3690 | * Return: The number of modes added or 0 if we couldn't find any. |
f0fda0a4 ZY |
3691 | */ |
3692 | int drm_add_modes_noedid(struct drm_connector *connector, | |
3693 | int hdisplay, int vdisplay) | |
3694 | { | |
3695 | int i, count, num_modes = 0; | |
b1f559ec | 3696 | struct drm_display_mode *mode; |
f0fda0a4 ZY |
3697 | struct drm_device *dev = connector->dev; |
3698 | ||
3699 | count = sizeof(drm_dmt_modes) / sizeof(struct drm_display_mode); | |
3700 | if (hdisplay < 0) | |
3701 | hdisplay = 0; | |
3702 | if (vdisplay < 0) | |
3703 | vdisplay = 0; | |
3704 | ||
3705 | for (i = 0; i < count; i++) { | |
b1f559ec | 3706 | const struct drm_display_mode *ptr = &drm_dmt_modes[i]; |
f0fda0a4 ZY |
3707 | if (hdisplay && vdisplay) { |
3708 | /* | |
3709 | * Only when two are valid, they will be used to check | |
3710 | * whether the mode should be added to the mode list of | |
3711 | * the connector. | |
3712 | */ | |
3713 | if (ptr->hdisplay > hdisplay || | |
3714 | ptr->vdisplay > vdisplay) | |
3715 | continue; | |
3716 | } | |
f985dedb AJ |
3717 | if (drm_mode_vrefresh(ptr) > 61) |
3718 | continue; | |
f0fda0a4 ZY |
3719 | mode = drm_mode_duplicate(dev, ptr); |
3720 | if (mode) { | |
3721 | drm_mode_probed_add(connector, mode); | |
3722 | num_modes++; | |
3723 | } | |
3724 | } | |
3725 | return num_modes; | |
3726 | } | |
3727 | EXPORT_SYMBOL(drm_add_modes_noedid); | |
10a85120 | 3728 | |
db6cf833 TR |
3729 | /** |
3730 | * drm_set_preferred_mode - Sets the preferred mode of a connector | |
3731 | * @connector: connector whose mode list should be processed | |
3732 | * @hpref: horizontal resolution of preferred mode | |
3733 | * @vpref: vertical resolution of preferred mode | |
3734 | * | |
3735 | * Marks a mode as preferred if it matches the resolution specified by @hpref | |
3736 | * and @vpref. | |
3737 | */ | |
3cf70daf GH |
3738 | void drm_set_preferred_mode(struct drm_connector *connector, |
3739 | int hpref, int vpref) | |
3740 | { | |
3741 | struct drm_display_mode *mode; | |
3742 | ||
3743 | list_for_each_entry(mode, &connector->probed_modes, head) { | |
db6cf833 | 3744 | if (mode->hdisplay == hpref && |
9d3de138 | 3745 | mode->vdisplay == vpref) |
3cf70daf GH |
3746 | mode->type |= DRM_MODE_TYPE_PREFERRED; |
3747 | } | |
3748 | } | |
3749 | EXPORT_SYMBOL(drm_set_preferred_mode); | |
3750 | ||
10a85120 TR |
3751 | /** |
3752 | * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with | |
3753 | * data from a DRM display mode | |
3754 | * @frame: HDMI AVI infoframe | |
3755 | * @mode: DRM display mode | |
3756 | * | |
db6cf833 | 3757 | * Return: 0 on success or a negative error code on failure. |
10a85120 TR |
3758 | */ |
3759 | int | |
3760 | drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, | |
3761 | const struct drm_display_mode *mode) | |
3762 | { | |
3763 | int err; | |
3764 | ||
3765 | if (!frame || !mode) | |
3766 | return -EINVAL; | |
3767 | ||
3768 | err = hdmi_avi_infoframe_init(frame); | |
3769 | if (err < 0) | |
3770 | return err; | |
3771 | ||
bf02db99 DL |
3772 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
3773 | frame->pixel_repeat = 1; | |
3774 | ||
10a85120 | 3775 | frame->video_code = drm_match_cea_mode(mode); |
10a85120 TR |
3776 | |
3777 | frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; | |
0967e6a5 | 3778 | |
69ab6d35 VK |
3779 | /* |
3780 | * Populate picture aspect ratio from either | |
3781 | * user input (if specified) or from the CEA mode list. | |
3782 | */ | |
3783 | if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 || | |
3784 | mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9) | |
3785 | frame->picture_aspect = mode->picture_aspect_ratio; | |
3786 | else if (frame->video_code > 0) | |
0967e6a5 VK |
3787 | frame->picture_aspect = drm_get_cea_aspect_ratio( |
3788 | frame->video_code); | |
3789 | ||
10a85120 | 3790 | frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; |
24d01805 | 3791 | frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; |
10a85120 TR |
3792 | |
3793 | return 0; | |
3794 | } | |
3795 | EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); | |
83dd0008 | 3796 | |
4eed4a0a DL |
3797 | static enum hdmi_3d_structure |
3798 | s3d_structure_from_display_mode(const struct drm_display_mode *mode) | |
3799 | { | |
3800 | u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; | |
3801 | ||
3802 | switch (layout) { | |
3803 | case DRM_MODE_FLAG_3D_FRAME_PACKING: | |
3804 | return HDMI_3D_STRUCTURE_FRAME_PACKING; | |
3805 | case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: | |
3806 | return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; | |
3807 | case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: | |
3808 | return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; | |
3809 | case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: | |
3810 | return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; | |
3811 | case DRM_MODE_FLAG_3D_L_DEPTH: | |
3812 | return HDMI_3D_STRUCTURE_L_DEPTH; | |
3813 | case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: | |
3814 | return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; | |
3815 | case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: | |
3816 | return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; | |
3817 | case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: | |
3818 | return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; | |
3819 | default: | |
3820 | return HDMI_3D_STRUCTURE_INVALID; | |
3821 | } | |
3822 | } | |
3823 | ||
83dd0008 LD |
3824 | /** |
3825 | * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with | |
3826 | * data from a DRM display mode | |
3827 | * @frame: HDMI vendor infoframe | |
3828 | * @mode: DRM display mode | |
3829 | * | |
3830 | * Note that there's is a need to send HDMI vendor infoframes only when using a | |
3831 | * 4k or stereoscopic 3D mode. So when giving any other mode as input this | |
3832 | * function will return -EINVAL, error that can be safely ignored. | |
3833 | * | |
db6cf833 | 3834 | * Return: 0 on success or a negative error code on failure. |
83dd0008 LD |
3835 | */ |
3836 | int | |
3837 | drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, | |
3838 | const struct drm_display_mode *mode) | |
3839 | { | |
3840 | int err; | |
4eed4a0a | 3841 | u32 s3d_flags; |
83dd0008 LD |
3842 | u8 vic; |
3843 | ||
3844 | if (!frame || !mode) | |
3845 | return -EINVAL; | |
3846 | ||
3847 | vic = drm_match_hdmi_mode(mode); | |
4eed4a0a DL |
3848 | s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK; |
3849 | ||
3850 | if (!vic && !s3d_flags) | |
3851 | return -EINVAL; | |
3852 | ||
3853 | if (vic && s3d_flags) | |
83dd0008 LD |
3854 | return -EINVAL; |
3855 | ||
3856 | err = hdmi_vendor_infoframe_init(frame); | |
3857 | if (err < 0) | |
3858 | return err; | |
3859 | ||
4eed4a0a DL |
3860 | if (vic) |
3861 | frame->vic = vic; | |
3862 | else | |
3863 | frame->s3d_struct = s3d_structure_from_display_mode(mode); | |
83dd0008 LD |
3864 | |
3865 | return 0; | |
3866 | } | |
3867 | EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); |