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drm/vgem: Replace opencoded version of drm_gem_dumb_map_offset()
[linux-2.6-block.git] / drivers / gpu / drm / drm_dp_helper.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2009 Keith Packard
3 *
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
13 *
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20 * OF THIS SOFTWARE.
21 */
22
a4fc5ed6 23#include <linux/delay.h>
a4fc5ed6 24#include <linux/errno.h>
a4fc5ed6 25#include <linux/i2c.h>
580fc13f
JN		 26#include <linux/init.h>
27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/sched.h>
96106c97 30#include <linux/seq_file.h>
580fc13f 31
760285e7 32#include <drm/drm_dp_helper.h>
580fc13f
JN		 33#include <drm/drm_print.h>
34#include <drm/drm_vblank.h>
2f221a5e 35#include <drm/drm_dp_mst_helper.h>
a4fc5ed6 36
e15c8f4b
DV		 37#include "drm_crtc_helper_internal.h"
38
28164fda
DV		 39/**
40 * DOC: dp helpers
41 *
42 * These functions contain some common logic and helpers at various abstraction
43 * levels to deal with Display Port sink devices and related things like DP aux
44 * channel transfers, EDID reading over DP aux channels, decoding certain DPCD
45 * blocks, ...
46 */
47
1ffdff13 48/* Helpers for DP link training */
0aec2881 49static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r)
1ffdff13
DV		 50{
51 return link_status[r - DP_LANE0_1_STATUS];
52}
53
0aec2881 54static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE],
1ffdff13
DV		 55 int lane)
56{
57 int i = DP_LANE0_1_STATUS + (lane >> 1);
58 int s = (lane & 1) * 4;
59 u8 l = dp_link_status(link_status, i);
948de842 60
1ffdff13
DV		 61 return (l >> s) & 0xf;
62}
63
0aec2881 64bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
1ffdff13
DV		 65 int lane_count)
66{
67 u8 lane_align;
68 u8 lane_status;
69 int lane;
70
71 lane_align = dp_link_status(link_status,
72 DP_LANE_ALIGN_STATUS_UPDATED);
73 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
74 return false;
75 for (lane = 0; lane < lane_count; lane++) {
76 lane_status = dp_get_lane_status(link_status, lane);
77 if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
78 return false;
79 }
80 return true;
81}
82EXPORT_SYMBOL(drm_dp_channel_eq_ok);
83
0aec2881 84bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
1ffdff13
DV		 85 int lane_count)
86{
87 int lane;
88 u8 lane_status;
89
90 for (lane = 0; lane < lane_count; lane++) {
91 lane_status = dp_get_lane_status(link_status, lane);
92 if ((lane_status & DP_LANE_CR_DONE) == 0)
93 return false;
94 }
95 return true;
96}
97EXPORT_SYMBOL(drm_dp_clock_recovery_ok);
0f037bde 98
0aec2881 99u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
0f037bde
DV		 100 int lane)
101{
102 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
103 int s = ((lane & 1) ?
104 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
105 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
106 u8 l = dp_link_status(link_status, i);
107
108 return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
109}
110EXPORT_SYMBOL(drm_dp_get_adjust_request_voltage);
111
0aec2881 112u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
0f037bde
DV		 113 int lane)
114{
115 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
116 int s = ((lane & 1) ?
117 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
118 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
119 u8 l = dp_link_status(link_status, i);
120
121 return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
122}
123EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis);
124
79465e0f
TR		 125u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZE],
126 unsigned int lane)
127{
128 unsigned int offset = DP_ADJUST_REQUEST_POST_CURSOR2;
129 u8 value = dp_link_status(link_status, offset);
130
131 return (value >> (lane << 1)) & 0x3;
132}
133EXPORT_SYMBOL(drm_dp_get_adjust_request_post_cursor);
134
fc6b4204
TR		 135void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
136{
137 unsigned long rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
138 DP_TRAINING_AUX_RD_MASK;
2f065d8a
MA		 139
140 if (rd_interval > 4)
fc6b4204 141 DRM_DEBUG_KMS("AUX interval %lu, out of range (max 4)\n",
2f065d8a
MA		 142 rd_interval);
143
144 if (rd_interval == 0 || dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
fc6b4204 145 rd_interval = 100;
1a644cd4 146 else
fc6b4204
TR		 147 rd_interval *= 4 * USEC_PER_MSEC;
148
149 usleep_range(rd_interval, rd_interval * 2);
1a644cd4
DV		 150}
151EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);
152
fc6b4204
TR		 153void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
154{
155 unsigned long rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
156 DP_TRAINING_AUX_RD_MASK;
2f065d8a
MA		 157
158 if (rd_interval > 4)
fc6b4204 159 DRM_DEBUG_KMS("AUX interval %lu, out of range (max 4)\n",
2f065d8a
MA		 160 rd_interval);
161
162 if (rd_interval == 0)
fc6b4204 163 rd_interval = 400;
1a644cd4 164 else
fc6b4204
TR		 165 rd_interval *= 4 * USEC_PER_MSEC;
166
167 usleep_range(rd_interval, rd_interval * 2);
1a644cd4
DV		 168}
169EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
3b5c662e
DV		 170
171u8 drm_dp_link_rate_to_bw_code(int link_rate)
172{
57a1b089
SP		 173 /* Spec says link_bw = link_rate / 0.27Gbps */
174 return link_rate / 27000;
3b5c662e
DV		 175}
176EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code);
177
178int drm_dp_bw_code_to_link_rate(u8 link_bw)
179{
57a1b089
SP		 180 /* Spec says link_rate = link_bw * 0.27Gbps */
181 return link_bw * 27000;
3b5c662e
DV		 182}
183EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate);
c197db75 184
79a2b161
VS		 185#define AUX_RETRY_INTERVAL 500 /* us */
186
a18b2192
LP		 187static inline void
188drm_dp_dump_access(const struct drm_dp_aux *aux,
189 u8 request, uint offset, void *buffer, int ret)
190{
191 const char *arrow = request == DP_AUX_NATIVE_READ ? "->" : "<-";
192
193 if (ret > 0)
b6467446
JN		 194 DRM_DEBUG_DP("%s: 0x%05x AUX %s (ret=%3d) %*ph\n",
195 aux->name, offset, arrow, ret, min(ret, 20), buffer);
a18b2192 196 else
b6467446
JN		 197 DRM_DEBUG_DP("%s: 0x%05x AUX %s (ret=%3d)\n",
198 aux->name, offset, arrow, ret);
a18b2192
LP		 199}
200
c197db75
TR		 201/**
202 * DOC: dp helpers
203 *
204 * The DisplayPort AUX channel is an abstraction to allow generic, driver-
205 * independent access to AUX functionality. Drivers can take advantage of
206 * this by filling in the fields of the drm_dp_aux structure.
207 *
208 * Transactions are described using a hardware-independent drm_dp_aux_msg
209 * structure, which is passed into a driver's .transfer() implementation.
210 * Both native and I2C-over-AUX transactions are supported.
c197db75
TR		 211 */
212
213static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8 request,
214 unsigned int offset, void *buffer, size_t size)
215{
216 struct drm_dp_aux_msg msg;
82922da3
L		 217 unsigned int retry, native_reply;
218 int err = 0, ret = 0;
c197db75
TR		 219
220 memset(&msg, 0, sizeof(msg));
221 msg.address = offset;
222 msg.request = request;
223 msg.buffer = buffer;
224 msg.size = size;
225
7779c5e2
RC		 226 mutex_lock(&aux->hw_mutex);
227
c197db75
TR		 228 /*
229 * The specification doesn't give any recommendation on how often to
19a93f04
DA		 230 * retry native transactions. We used to retry 7 times like for
231 * aux i2c transactions but real world devices this wasn't
232 * sufficient, bump to 32 which makes Dell 4k monitors happier.
c197db75 233 */
19a93f04 234 for (retry = 0; retry < 32; retry++) {
82922da3 235 if (ret != 0 && ret != -ETIMEDOUT) {
e1083ff3
L		 236 usleep_range(AUX_RETRY_INTERVAL,
237 AUX_RETRY_INTERVAL + 100);
238 }
4f71d0cb 239
82922da3 240 ret = aux->transfer(aux, &msg);
a1f5524a 241 if (ret >= 0) {
82922da3
L		 242 native_reply = msg.reply & DP_AUX_NATIVE_REPLY_MASK;
243 if (native_reply == DP_AUX_NATIVE_REPLY_ACK) {
244 if (ret == size)
245 goto unlock;
c197db75 246
82922da3
L		 247 ret = -EPROTO;
248 } else
249 ret = -EIO;
c197db75 250 }
82922da3
L		 251
252 /*
253 * We want the error we return to be the error we received on
254 * the first transaction, since we may get a different error the
255 * next time we retry
256 */
257 if (!err)
258 err = ret;
c197db75
TR		 259 }
260
29f21e04 261 DRM_DEBUG_KMS("Too many retries, giving up. First error: %d\n", err);
82922da3 262 ret = err;
7779c5e2
RC		 263
264unlock:
265 mutex_unlock(&aux->hw_mutex);
82922da3 266 return ret;
c197db75
TR		 267}
268
269/**
270 * drm_dp_dpcd_read() - read a series of bytes from the DPCD
2f221a5e 271 * @aux: DisplayPort AUX channel (SST or MST)
c197db75
TR		 272 * @offset: address of the (first) register to read
273 * @buffer: buffer to store the register values
274 * @size: number of bytes in @buffer
275 *
276 * Returns the number of bytes transferred on success, or a negative error
277 * code on failure. -EIO is returned if the request was NAKed by the sink or
278 * if the retry count was exceeded. If not all bytes were transferred, this
279 * function returns -EPROTO. Errors from the underlying AUX channel transfer
280 * function, with the exception of -EBUSY (which causes the transaction to
281 * be retried), are propagated to the caller.
282 */
283ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
284 void *buffer, size_t size)
285{
f808f633
L		 286 int ret;
287
288 /*
289 * HP ZR24w corrupts the first DPCD access after entering power save
290 * mode. Eg. on a read, the entire buffer will be filled with the same
291 * byte. Do a throw away read to avoid corrupting anything we care
292 * about. Afterwards things will work correctly until the monitor
293 * gets woken up and subsequently re-enters power save mode.
294 *
295 * The user pressing any button on the monitor is enough to wake it
296 * up, so there is no particularly good place to do the workaround.
297 * We just have to do it before any DPCD access and hope that the
298 * monitor doesn't power down exactly after the throw away read.
299 */
2f221a5e
DF		 300 if (!aux->is_remote) {
301 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, DP_DPCD_REV,
302 buffer, 1);
303 if (ret != 1)
304 goto out;
305 }
f808f633 306
2f221a5e
DF		 307 if (aux->is_remote)
308 ret = drm_dp_mst_dpcd_read(aux, offset, buffer, size);
309 else
310 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset,
311 buffer, size);
a18b2192
LP		 312
313out:
314 drm_dp_dump_access(aux, DP_AUX_NATIVE_READ, offset, buffer, ret);
315 return ret;
c197db75
TR		 316}
317EXPORT_SYMBOL(drm_dp_dpcd_read);
318
319/**
320 * drm_dp_dpcd_write() - write a series of bytes to the DPCD
2f221a5e 321 * @aux: DisplayPort AUX channel (SST or MST)
c197db75
TR		 322 * @offset: address of the (first) register to write
323 * @buffer: buffer containing the values to write
324 * @size: number of bytes in @buffer
325 *
326 * Returns the number of bytes transferred on success, or a negative error
327 * code on failure. -EIO is returned if the request was NAKed by the sink or
328 * if the retry count was exceeded. If not all bytes were transferred, this
329 * function returns -EPROTO. Errors from the underlying AUX channel transfer
330 * function, with the exception of -EBUSY (which causes the transaction to
331 * be retried), are propagated to the caller.
332 */
333ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
334 void *buffer, size_t size)
335{
a18b2192
LP		 336 int ret;
337
2f221a5e
DF		 338 if (aux->is_remote)
339 ret = drm_dp_mst_dpcd_write(aux, offset, buffer, size);
340 else
341 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_WRITE, offset,
342 buffer, size);
343
a18b2192
LP		 344 drm_dp_dump_access(aux, DP_AUX_NATIVE_WRITE, offset, buffer, ret);
345 return ret;
c197db75
TR		 346}
347EXPORT_SYMBOL(drm_dp_dpcd_write);
8d4adc6a
TR		 348
349/**
350 * drm_dp_dpcd_read_link_status() - read DPCD link status (bytes 0x202-0x207)
351 * @aux: DisplayPort AUX channel
352 * @status: buffer to store the link status in (must be at least 6 bytes)
353 *
354 * Returns the number of bytes transferred on success or a negative error
355 * code on failure.
356 */
357int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
358 u8 status[DP_LINK_STATUS_SIZE])
359{
360 return drm_dp_dpcd_read(aux, DP_LANE0_1_STATUS, status,
361 DP_LINK_STATUS_SIZE);
362}
363EXPORT_SYMBOL(drm_dp_dpcd_read_link_status);
516c0f7c 364
e11f5bd8
JFZ		 365/**
366 * drm_dp_send_real_edid_checksum() - send back real edid checksum value
367 * @aux: DisplayPort AUX channel
368 * @real_edid_checksum: real edid checksum for the last block
369 *
370 * Returns:
371 * True on success
372 */
373bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux,
374 u8 real_edid_checksum)
375{
376 u8 link_edid_read = 0, auto_test_req = 0, test_resp = 0;
377
378 if (drm_dp_dpcd_read(aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
379 &auto_test_req, 1) < 1) {
380 DRM_ERROR("DPCD failed read at register 0x%x\n",
381 DP_DEVICE_SERVICE_IRQ_VECTOR);
382 return false;
383 }
384 auto_test_req &= DP_AUTOMATED_TEST_REQUEST;
385
386 if (drm_dp_dpcd_read(aux, DP_TEST_REQUEST, &link_edid_read, 1) < 1) {
387 DRM_ERROR("DPCD failed read at register 0x%x\n",
388 DP_TEST_REQUEST);
389 return false;
390 }
391 link_edid_read &= DP_TEST_LINK_EDID_READ;
392
393 if (!auto_test_req || !link_edid_read) {
394 DRM_DEBUG_KMS("Source DUT does not support TEST_EDID_READ\n");
395 return false;
396 }
397
398 if (drm_dp_dpcd_write(aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
399 &auto_test_req, 1) < 1) {
400 DRM_ERROR("DPCD failed write at register 0x%x\n",
401 DP_DEVICE_SERVICE_IRQ_VECTOR);
402 return false;
403 }
404
405 /* send back checksum for the last edid extension block data */
406 if (drm_dp_dpcd_write(aux, DP_TEST_EDID_CHECKSUM,
407 &real_edid_checksum, 1) < 1) {
408 DRM_ERROR("DPCD failed write at register 0x%x\n",
409 DP_TEST_EDID_CHECKSUM);
410 return false;
411 }
412
413 test_resp |= DP_TEST_EDID_CHECKSUM_WRITE;
414 if (drm_dp_dpcd_write(aux, DP_TEST_RESPONSE, &test_resp, 1) < 1) {
415 DRM_ERROR("DPCD failed write at register 0x%x\n",
416 DP_TEST_RESPONSE);
417 return false;
418 }
419
420 return true;
421}
422EXPORT_SYMBOL(drm_dp_send_real_edid_checksum);
423
1c29bd3d
MK		 424/**
425 * drm_dp_downstream_max_clock() - extract branch device max
426 * pixel rate for legacy VGA
427 * converter or max TMDS clock
428 * rate for others
429 * @dpcd: DisplayPort configuration data
430 * @port_cap: port capabilities
431 *
432 * Returns max clock in kHz on success or 0 if max clock not defined
433 */
434int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
435 const u8 port_cap[4])
436{
437 int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
438 bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
439 DP_DETAILED_CAP_INFO_AVAILABLE;
440
441 if (!detailed_cap_info)
442 return 0;
443
444 switch (type) {
445 case DP_DS_PORT_TYPE_VGA:
446 return port_cap[1] * 8 * 1000;
447 case DP_DS_PORT_TYPE_DVI:
448 case DP_DS_PORT_TYPE_HDMI:
449 case DP_DS_PORT_TYPE_DP_DUALMODE:
450 return port_cap[1] * 2500;
451 default:
452 return 0;
453 }
454}
455EXPORT_SYMBOL(drm_dp_downstream_max_clock);
456
7529d6af
MK		 457/**
458 * drm_dp_downstream_max_bpc() - extract branch device max
459 * bits per component
460 * @dpcd: DisplayPort configuration data
461 * @port_cap: port capabilities
462 *
463 * Returns max bpc on success or 0 if max bpc not defined
464 */
465int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
466 const u8 port_cap[4])
467{
468 int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
469 bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
470 DP_DETAILED_CAP_INFO_AVAILABLE;
471 int bpc;
472
473 if (!detailed_cap_info)
474 return 0;
475
476 switch (type) {
477 case DP_DS_PORT_TYPE_VGA:
478 case DP_DS_PORT_TYPE_DVI:
479 case DP_DS_PORT_TYPE_HDMI:
480 case DP_DS_PORT_TYPE_DP_DUALMODE:
481 bpc = port_cap[2] & DP_DS_MAX_BPC_MASK;
482
483 switch (bpc) {
484 case DP_DS_8BPC:
485 return 8;
486 case DP_DS_10BPC:
487 return 10;
488 case DP_DS_12BPC:
489 return 12;
490 case DP_DS_16BPC:
491 return 16;
492 }
e9c0c874 493 /* fall through */
7529d6af
MK		 494 default:
495 return 0;
496 }
497}
498EXPORT_SYMBOL(drm_dp_downstream_max_bpc);
499
266d783b
MK		 500/**
501 * drm_dp_downstream_id() - identify branch device
502 * @aux: DisplayPort AUX channel
3442d9ee 503 * @id: DisplayPort branch device id
266d783b
MK		 504 *
505 * Returns branch device id on success or NULL on failure
506 */
507int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6])
508{
509 return drm_dp_dpcd_read(aux, DP_BRANCH_ID, id, 6);
510}
511EXPORT_SYMBOL(drm_dp_downstream_id);
512
80209e5f
MK		 513/**
514 * drm_dp_downstream_debug() - debug DP branch devices
515 * @m: pointer for debugfs file
516 * @dpcd: DisplayPort configuration data
517 * @port_cap: port capabilities
518 * @aux: DisplayPort AUX channel
519 *
520 */
521void drm_dp_downstream_debug(struct seq_file *m,
522 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
523 const u8 port_cap[4], struct drm_dp_aux *aux)
524{
525 bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
526 DP_DETAILED_CAP_INFO_AVAILABLE;
527 int clk;
528 int bpc;
967003bb 529 char id[7];
80209e5f
MK		 530 int len;
531 uint8_t rev[2];
532 int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
b4c32073 533 bool branch_device = drm_dp_is_branch(dpcd);
80209e5f
MK		 534
535 seq_printf(m, "\tDP branch device present: %s\n",
536 branch_device ? "yes" : "no");
537
538 if (!branch_device)
539 return;
540
541 switch (type) {
542 case DP_DS_PORT_TYPE_DP:
543 seq_puts(m, "\t\tType: DisplayPort\n");
544 break;
545 case DP_DS_PORT_TYPE_VGA:
546 seq_puts(m, "\t\tType: VGA\n");
547 break;
548 case DP_DS_PORT_TYPE_DVI:
549 seq_puts(m, "\t\tType: DVI\n");
550 break;
551 case DP_DS_PORT_TYPE_HDMI:
552 seq_puts(m, "\t\tType: HDMI\n");
553 break;
554 case DP_DS_PORT_TYPE_NON_EDID:
555 seq_puts(m, "\t\tType: others without EDID support\n");
556 break;
557 case DP_DS_PORT_TYPE_DP_DUALMODE:
558 seq_puts(m, "\t\tType: DP++\n");
559 break;
560 case DP_DS_PORT_TYPE_WIRELESS:
561 seq_puts(m, "\t\tType: Wireless\n");
562 break;
563 default:
564 seq_puts(m, "\t\tType: N/A\n");
565 }
566
967003bb 567 memset(id, 0, sizeof(id));
80209e5f
MK		 568 drm_dp_downstream_id(aux, id);
569 seq_printf(m, "\t\tID: %s\n", id);
570
571 len = drm_dp_dpcd_read(aux, DP_BRANCH_HW_REV, &rev[0], 1);
572 if (len > 0)
573 seq_printf(m, "\t\tHW: %d.%d\n",
574 (rev[0] & 0xf0) >> 4, rev[0] & 0xf);
575
c11a93f5 576 len = drm_dp_dpcd_read(aux, DP_BRANCH_SW_REV, rev, 2);
80209e5f
MK		 577 if (len > 0)
578 seq_printf(m, "\t\tSW: %d.%d\n", rev[0], rev[1]);
579
580 if (detailed_cap_info) {
581 clk = drm_dp_downstream_max_clock(dpcd, port_cap);
582
583 if (clk > 0) {
584 if (type == DP_DS_PORT_TYPE_VGA)
585 seq_printf(m, "\t\tMax dot clock: %d kHz\n", clk);
586 else
587 seq_printf(m, "\t\tMax TMDS clock: %d kHz\n", clk);
588 }
589
590 bpc = drm_dp_downstream_max_bpc(dpcd, port_cap);
591
592 if (bpc > 0)
593 seq_printf(m, "\t\tMax bpc: %d\n", bpc);
594 }
595}
596EXPORT_SYMBOL(drm_dp_downstream_debug);
597
88759686
TR		 598/*
599 * I2C-over-AUX implementation
600 */
601
602static u32 drm_dp_i2c_functionality(struct i2c_adapter *adapter)
603{
604 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
605 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
606 I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
607 I2C_FUNC_10BIT_ADDR;
608}
609
68ec2a2a
VS		 610static void drm_dp_i2c_msg_write_status_update(struct drm_dp_aux_msg *msg)
611{
612 /*
613 * In case of i2c defer or short i2c ack reply to a write,
614 * we need to switch to WRITE_STATUS_UPDATE to drain the
615 * rest of the message
616 */
617 if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_WRITE) {
618 msg->request &= DP_AUX_I2C_MOT;
619 msg->request |= DP_AUX_I2C_WRITE_STATUS_UPDATE;
620 }
621}
622
4efa83c8
VS		 623#define AUX_PRECHARGE_LEN 10 /* 10 to 16 */
624#define AUX_SYNC_LEN (16 + 4) /* preamble + AUX_SYNC_END */
625#define AUX_STOP_LEN 4
626#define AUX_CMD_LEN 4
627#define AUX_ADDRESS_LEN 20
628#define AUX_REPLY_PAD_LEN 4
629#define AUX_LENGTH_LEN 8
630
631/*
632 * Calculate the duration of the AUX request/reply in usec. Gives the
633 * "best" case estimate, ie. successful while as short as possible.
634 */
635static int drm_dp_aux_req_duration(const struct drm_dp_aux_msg *msg)
636{
637 int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN +
638 AUX_CMD_LEN + AUX_ADDRESS_LEN + AUX_LENGTH_LEN;
639
640 if ((msg->request & DP_AUX_I2C_READ) == 0)
641 len += msg->size * 8;
642
643 return len;
644}
645
646static int drm_dp_aux_reply_duration(const struct drm_dp_aux_msg *msg)
647{
648 int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN +
649 AUX_CMD_LEN + AUX_REPLY_PAD_LEN;
650
651 /*
652 * For read we expect what was asked. For writes there will
653 * be 0 or 1 data bytes. Assume 0 for the "best" case.
654 */
655 if (msg->request & DP_AUX_I2C_READ)
656 len += msg->size * 8;
657
658 return len;
659}
660
661#define I2C_START_LEN 1
662#define I2C_STOP_LEN 1
663#define I2C_ADDR_LEN 9 /* ADDRESS + R/W + ACK/NACK */
664#define I2C_DATA_LEN 9 /* DATA + ACK/NACK */
665
666/*
667 * Calculate the length of the i2c transfer in usec, assuming
668 * the i2c bus speed is as specified. Gives the the "worst"
669 * case estimate, ie. successful while as long as possible.
670 * Doesn't account the the "MOT" bit, and instead assumes each
671 * message includes a START, ADDRESS and STOP. Neither does it
672 * account for additional random variables such as clock stretching.
673 */
674static int drm_dp_i2c_msg_duration(const struct drm_dp_aux_msg *msg,
675 int i2c_speed_khz)
676{
677 /* AUX bitrate is 1MHz, i2c bitrate as specified */
678 return DIV_ROUND_UP((I2C_START_LEN + I2C_ADDR_LEN +
679 msg->size * I2C_DATA_LEN +
680 I2C_STOP_LEN) * 1000, i2c_speed_khz);
681}
682
683/*
684 * Deterine how many retries should be attempted to successfully transfer
685 * the specified message, based on the estimated durations of the
686 * i2c and AUX transfers.
687 */
688static int drm_dp_i2c_retry_count(const struct drm_dp_aux_msg *msg,
689 int i2c_speed_khz)
690{
691 int aux_time_us = drm_dp_aux_req_duration(msg) +
692 drm_dp_aux_reply_duration(msg);
693 int i2c_time_us = drm_dp_i2c_msg_duration(msg, i2c_speed_khz);
694
695 return DIV_ROUND_UP(i2c_time_us, aux_time_us + AUX_RETRY_INTERVAL);
696}
697
f36203be
VS		 698/*
699 * FIXME currently assumes 10 kHz as some real world devices seem
700 * to require it. We should query/set the speed via DPCD if supported.
701 */
702static int dp_aux_i2c_speed_khz __read_mostly = 10;
703module_param_unsafe(dp_aux_i2c_speed_khz, int, 0644);
704MODULE_PARM_DESC(dp_aux_i2c_speed_khz,
705 "Assumed speed of the i2c bus in kHz, (1-400, default 10)");
706
88759686
TR		 707/*
708 * Transfer a single I2C-over-AUX message and handle various error conditions,
732d50b4 709 * retrying the transaction as appropriate. It is assumed that the
6806cdf9 710 * &drm_dp_aux.transfer function does not modify anything in the msg other than the
732d50b4 711 * reply field.
1d002fa7
SF		 712 *
713 * Returns bytes transferred on success, or a negative error code on failure.
88759686
TR		 714 */
715static int drm_dp_i2c_do_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
716{
396aa445 717 unsigned int retry, defer_i2c;
1d002fa7 718 int ret;
88759686
TR		 719 /*
720 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device
721 * is required to retry at least seven times upon receiving AUX_DEFER
722 * before giving up the AUX transaction.
4efa83c8
VS		 723 *
724 * We also try to account for the i2c bus speed.
88759686 725 */
f36203be 726 int max_retries = max(7, drm_dp_i2c_retry_count(msg, dp_aux_i2c_speed_khz));
4efa83c8
VS		 727
728 for (retry = 0, defer_i2c = 0; retry < (max_retries + defer_i2c); retry++) {
1d002fa7 729 ret = aux->transfer(aux, msg);
1d002fa7
SF		 730 if (ret < 0) {
731 if (ret == -EBUSY)
88759686
TR		 732 continue;
733
9622c38f
L		 734 /*
735 * While timeouts can be errors, they're usually normal
736 * behavior (for instance, when a driver tries to
737 * communicate with a non-existant DisplayPort device).
738 * Avoid spamming the kernel log with timeout errors.
739 */
740 if (ret == -ETIMEDOUT)
741 DRM_DEBUG_KMS_RATELIMITED("transaction timed out\n");
742 else
743 DRM_DEBUG_KMS("transaction failed: %d\n", ret);
744
1d002fa7 745 return ret;
88759686
TR		 746 }
747
88759686
TR		 748
749 switch (msg->reply & DP_AUX_NATIVE_REPLY_MASK) {
750 case DP_AUX_NATIVE_REPLY_ACK:
751 /*
752 * For I2C-over-AUX transactions this isn't enough, we
753 * need to check for the I2C ACK reply.
754 */
755 break;
756
757 case DP_AUX_NATIVE_REPLY_NACK:
fb8c5e49 758 DRM_DEBUG_KMS("native nack (result=%d, size=%zu)\n", ret, msg->size);
88759686
TR		 759 return -EREMOTEIO;
760
761 case DP_AUX_NATIVE_REPLY_DEFER:
747552b9 762 DRM_DEBUG_KMS("native defer\n");
88759686
TR		 763 /*
764 * We could check for I2C bit rate capabilities and if
765 * available adjust this interval. We could also be
766 * more careful with DP-to-legacy adapters where a
767 * long legacy cable may force very low I2C bit rates.
768 *
769 * For now just defer for long enough to hopefully be
770 * safe for all use-cases.
771 */
79a2b161 772 usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100);
88759686
TR		 773 continue;
774
775 default:
776 DRM_ERROR("invalid native reply %#04x\n", msg->reply);
777 return -EREMOTEIO;
778 }
779
780 switch (msg->reply & DP_AUX_I2C_REPLY_MASK) {
781 case DP_AUX_I2C_REPLY_ACK:
782 /*
783 * Both native ACK and I2C ACK replies received. We
784 * can assume the transfer was successful.
785 */
68ec2a2a
VS		 786 if (ret != msg->size)
787 drm_dp_i2c_msg_write_status_update(msg);
1d002fa7 788 return ret;
88759686
TR		 789
790 case DP_AUX_I2C_REPLY_NACK:
22e6de70
PZ		 791 DRM_DEBUG_KMS("I2C nack (result=%d, size=%zu)\n",
792 ret, msg->size);
e9cf6194 793 aux->i2c_nack_count++;
88759686
TR		 794 return -EREMOTEIO;
795
796 case DP_AUX_I2C_REPLY_DEFER:
797 DRM_DEBUG_KMS("I2C defer\n");
396aa445
TP		 798 /* DP Compliance Test 4.2.2.5 Requirement:
799 * Must have at least 7 retries for I2C defers on the
800 * transaction to pass this test
801 */
e9cf6194 802 aux->i2c_defer_count++;
396aa445
TP		 803 if (defer_i2c < 7)
804 defer_i2c++;
79a2b161 805 usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100);
68ec2a2a 806 drm_dp_i2c_msg_write_status_update(msg);
646db260 807
88759686
TR		 808 continue;
809
810 default:
811 DRM_ERROR("invalid I2C reply %#04x\n", msg->reply);
812 return -EREMOTEIO;
813 }
814 }
815
743b1e32 816 DRM_DEBUG_KMS("too many retries, giving up\n");
88759686
TR		 817 return -EREMOTEIO;
818}
819
68ec2a2a
VS		 820static void drm_dp_i2c_msg_set_request(struct drm_dp_aux_msg *msg,
821 const struct i2c_msg *i2c_msg)
822{
823 msg->request = (i2c_msg->flags & I2C_M_RD) ?
824 DP_AUX_I2C_READ : DP_AUX_I2C_WRITE;
da279eb9
VS		 825 if (!(i2c_msg->flags & I2C_M_STOP))
826 msg->request |= DP_AUX_I2C_MOT;
68ec2a2a
VS		 827}
828
1d002fa7
SF		 829/*
830 * Keep retrying drm_dp_i2c_do_msg until all data has been transferred.
831 *
832 * Returns an error code on failure, or a recommended transfer size on success.
833 */
834static int drm_dp_i2c_drain_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *orig_msg)
835{
836 int err, ret = orig_msg->size;
837 struct drm_dp_aux_msg msg = *orig_msg;
838
839 while (msg.size > 0) {
840 err = drm_dp_i2c_do_msg(aux, &msg);
841 if (err <= 0)
842 return err == 0 ? -EPROTO : err;
843
844 if (err < msg.size && err < ret) {
845 DRM_DEBUG_KMS("Partial I2C reply: requested %zu bytes got %d bytes\n",
846 msg.size, err);
847 ret = err;
848 }
849
850 msg.size -= err;
851 msg.buffer += err;
852 }
853
854 return ret;
855}
856
857/*
858 * Bizlink designed DP->DVI-D Dual Link adapters require the I2C over AUX
859 * packets to be as large as possible. If not, the I2C transactions never
860 * succeed. Hence the default is maximum.
861 */
862static int dp_aux_i2c_transfer_size __read_mostly = DP_AUX_MAX_PAYLOAD_BYTES;
863module_param_unsafe(dp_aux_i2c_transfer_size, int, 0644);
864MODULE_PARM_DESC(dp_aux_i2c_transfer_size,
865 "Number of bytes to transfer in a single I2C over DP AUX CH message, (1-16, default 16)");
866
88759686
TR		 867static int drm_dp_i2c_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs,
868 int num)
869{
870 struct drm_dp_aux *aux = adapter->algo_data;
871 unsigned int i, j;
1d002fa7 872 unsigned transfer_size;
ccdb516e
AD		 873 struct drm_dp_aux_msg msg;
874 int err = 0;
88759686 875
1d002fa7
SF		 876 dp_aux_i2c_transfer_size = clamp(dp_aux_i2c_transfer_size, 1, DP_AUX_MAX_PAYLOAD_BYTES);
877
ccdb516e 878 memset(&msg, 0, sizeof(msg));
88759686 879
ccdb516e
AD		 880 for (i = 0; i < num; i++) {
881 msg.address = msgs[i].addr;
68ec2a2a 882 drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
ccdb516e
AD		 883 /* Send a bare address packet to start the transaction.
884 * Zero sized messages specify an address only (bare
885 * address) transaction.
886 */
887 msg.buffer = NULL;
888 msg.size = 0;
889 err = drm_dp_i2c_do_msg(aux, &msg);
68ec2a2a
VS		 890
891 /*
892 * Reset msg.request in case in case it got
893 * changed into a WRITE_STATUS_UPDATE.
894 */
895 drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
896
ccdb516e
AD		 897 if (err < 0)
898 break;
1d002fa7
SF		 899 /* We want each transaction to be as large as possible, but
900 * we'll go to smaller sizes if the hardware gives us a
901 * short reply.
88759686 902 */
1d002fa7
SF		 903 transfer_size = dp_aux_i2c_transfer_size;
904 for (j = 0; j < msgs[i].len; j += msg.size) {
88759686 905 msg.buffer = msgs[i].buf + j;
1d002fa7 906 msg.size = min(transfer_size, msgs[i].len - j);
88759686 907
1d002fa7 908 err = drm_dp_i2c_drain_msg(aux, &msg);
68ec2a2a
VS		 909
910 /*
911 * Reset msg.request in case in case it got
912 * changed into a WRITE_STATUS_UPDATE.
913 */
914 drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
915
88759686 916 if (err < 0)
ccdb516e 917 break;
1d002fa7 918 transfer_size = err;
88759686 919 }
ccdb516e
AD		 920 if (err < 0)
921 break;
88759686 922 }
ccdb516e
AD		 923 if (err >= 0)
924 err = num;
925 /* Send a bare address packet to close out the transaction.
926 * Zero sized messages specify an address only (bare
927 * address) transaction.
928 */
929 msg.request &= ~DP_AUX_I2C_MOT;
930 msg.buffer = NULL;
931 msg.size = 0;
932 (void)drm_dp_i2c_do_msg(aux, &msg);
88759686 933
ccdb516e 934 return err;
88759686
TR		 935}
936
937static const struct i2c_algorithm drm_dp_i2c_algo = {
938 .functionality = drm_dp_i2c_functionality,
939 .master_xfer = drm_dp_i2c_xfer,
940};
941
0c2f6f1a
CW		 942static struct drm_dp_aux *i2c_to_aux(struct i2c_adapter *i2c)
943{
944 return container_of(i2c, struct drm_dp_aux, ddc);
945}
946
947static void lock_bus(struct i2c_adapter *i2c, unsigned int flags)
948{
949 mutex_lock(&i2c_to_aux(i2c)->hw_mutex);
950}
951
952static int trylock_bus(struct i2c_adapter *i2c, unsigned int flags)
953{
954 return mutex_trylock(&i2c_to_aux(i2c)->hw_mutex);
955}
956
957static void unlock_bus(struct i2c_adapter *i2c, unsigned int flags)
958{
959 mutex_unlock(&i2c_to_aux(i2c)->hw_mutex);
960}
961
d1ed7985
PR		 962static const struct i2c_lock_operations drm_dp_i2c_lock_ops = {
963 .lock_bus = lock_bus,
964 .trylock_bus = trylock_bus,
965 .unlock_bus = unlock_bus,
966};
967
79c1da7c
TV		 968static int drm_dp_aux_get_crc(struct drm_dp_aux *aux, u8 *crc)
969{
970 u8 buf, count;
971 int ret;
972
973 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
974 if (ret < 0)
975 return ret;
976
977 WARN_ON(!(buf & DP_TEST_SINK_START));
978
979 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK_MISC, &buf);
980 if (ret < 0)
981 return ret;
982
983 count = buf & DP_TEST_COUNT_MASK;
984 if (count == aux->crc_count)
985 return -EAGAIN; /* No CRC yet */
986
987 aux->crc_count = count;
988
989 /*
990 * At DP_TEST_CRC_R_CR, there's 6 bytes containing CRC data, 2 bytes
991 * per component (RGB or CrYCb).
992 */
993 ret = drm_dp_dpcd_read(aux, DP_TEST_CRC_R_CR, crc, 6);
994 if (ret < 0)
995 return ret;
996
997 return 0;
998}
999
1000static void drm_dp_aux_crc_work(struct work_struct *work)
1001{
1002 struct drm_dp_aux *aux = container_of(work, struct drm_dp_aux,
1003 crc_work);
1004 struct drm_crtc *crtc;
1005 u8 crc_bytes[6];
1006 uint32_t crcs[3];
1007 int ret;
1008
1009 if (WARN_ON(!aux->crtc))
1010 return;
1011
1012 crtc = aux->crtc;
1013 while (crtc->crc.opened) {
1014 drm_crtc_wait_one_vblank(crtc);
1015 if (!crtc->crc.opened)
1016 break;
1017
1018 ret = drm_dp_aux_get_crc(aux, crc_bytes);
1019 if (ret == -EAGAIN) {
1020 usleep_range(1000, 2000);
1021 ret = drm_dp_aux_get_crc(aux, crc_bytes);
1022 }
1023
1024 if (ret == -EAGAIN) {
1025 DRM_DEBUG_KMS("Get CRC failed after retrying: %d\n",
1026 ret);
1027 continue;
1028 } else if (ret) {
1029 DRM_DEBUG_KMS("Failed to get a CRC: %d\n", ret);
1030 continue;
1031 }
1032
1033 crcs[0] = crc_bytes[0] | crc_bytes[1] << 8;
1034 crcs[1] = crc_bytes[2] | crc_bytes[3] << 8;
1035 crcs[2] = crc_bytes[4] | crc_bytes[5] << 8;
1036 drm_crtc_add_crc_entry(crtc, false, 0, crcs);
1037 }
1038}
1039
c908b1c4
DDZ		 1040/**
1041 * drm_dp_remote_aux_init() - minimally initialise a remote aux channel
1042 * @aux: DisplayPort AUX channel
1043 *
1044 * Used for remote aux channel in general. Merely initialize the crc work
1045 * struct.
1046 */
1047void drm_dp_remote_aux_init(struct drm_dp_aux *aux)
1048{
1049 INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work);
1050}
1051EXPORT_SYMBOL(drm_dp_remote_aux_init);
1052
88759686 1053/**
acd8f414 1054 * drm_dp_aux_init() - minimally initialise an aux channel
88759686
TR		 1055 * @aux: DisplayPort AUX channel
1056 *
acd8f414
CW		 1057 * If you need to use the drm_dp_aux's i2c adapter prior to registering it
1058 * with the outside world, call drm_dp_aux_init() first. You must still
1059 * call drm_dp_aux_register() once the connector has been registered to
1060 * allow userspace access to the auxiliary DP channel.
88759686 1061 */
acd8f414 1062void drm_dp_aux_init(struct drm_dp_aux *aux)
88759686 1063{
4f71d0cb 1064 mutex_init(&aux->hw_mutex);
2c6d1fff 1065 mutex_init(&aux->cec.lock);
79c1da7c 1066 INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work);
4f71d0cb 1067
88759686
TR		 1068 aux->ddc.algo = &drm_dp_i2c_algo;
1069 aux->ddc.algo_data = aux;
1070 aux->ddc.retries = 3;
1071
d1ed7985 1072 aux->ddc.lock_ops = &drm_dp_i2c_lock_ops;
acd8f414
CW		 1073}
1074EXPORT_SYMBOL(drm_dp_aux_init);
1075
1076/**
1077 * drm_dp_aux_register() - initialise and register aux channel
1078 * @aux: DisplayPort AUX channel
1079 *
1080 * Automatically calls drm_dp_aux_init() if this hasn't been done yet.
69b22f51
DV		 1081 * This should only be called when the underlying &struct drm_connector is
1082 * initialiazed already. Therefore the best place to call this is from
1083 * &drm_connector_funcs.late_register. Not that drivers which don't follow this
1084 * will Oops when CONFIG_DRM_DP_AUX_CHARDEV is enabled.
1085 *
1086 * Drivers which need to use the aux channel before that point (e.g. at driver
1087 * load time, before drm_dev_register() has been called) need to call
1088 * drm_dp_aux_init().
acd8f414
CW		 1089 *
1090 * Returns 0 on success or a negative error code on failure.
1091 */
1092int drm_dp_aux_register(struct drm_dp_aux *aux)
1093{
1094 int ret;
1095
1096 if (!aux->ddc.algo)
1097 drm_dp_aux_init(aux);
0c2f6f1a 1098
88759686
TR		 1099 aux->ddc.class = I2C_CLASS_DDC;
1100 aux->ddc.owner = THIS_MODULE;
1101 aux->ddc.dev.parent = aux->dev;
88759686 1102
9dc40560
JN		 1103 strlcpy(aux->ddc.name, aux->name ? aux->name : dev_name(aux->dev),
1104 sizeof(aux->ddc.name));
88759686 1105
e94cb37b
RA		 1106 ret = drm_dp_aux_register_devnode(aux);
1107 if (ret)
1108 return ret;
1109
1110 ret = i2c_add_adapter(&aux->ddc);
1111 if (ret) {
1112 drm_dp_aux_unregister_devnode(aux);
1113 return ret;
1114 }
1115
1116 return 0;
88759686 1117}
4f71d0cb 1118EXPORT_SYMBOL(drm_dp_aux_register);
88759686
TR		 1119
1120/**
4f71d0cb 1121 * drm_dp_aux_unregister() - unregister an AUX adapter
88759686
TR		 1122 * @aux: DisplayPort AUX channel
1123 */
4f71d0cb 1124void drm_dp_aux_unregister(struct drm_dp_aux *aux)
88759686 1125{
e94cb37b 1126 drm_dp_aux_unregister_devnode(aux);
88759686
TR		 1127 i2c_del_adapter(&aux->ddc);
1128}
4f71d0cb 1129EXPORT_SYMBOL(drm_dp_aux_unregister);
6608804b
VS		 1130
1131#define PSR_SETUP_TIME(x) [DP_PSR_SETUP_TIME_ ## x >> DP_PSR_SETUP_TIME_SHIFT] = (x)
1132
1133/**
1134 * drm_dp_psr_setup_time() - PSR setup in time usec
1135 * @psr_cap: PSR capabilities from DPCD
1136 *
1137 * Returns:
1138 * PSR setup time for the panel in microseconds, negative
1139 * error code on failure.
1140 */
1141int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE])
1142{
1143 static const u16 psr_setup_time_us[] = {
1144 PSR_SETUP_TIME(330),
1145 PSR_SETUP_TIME(275),
bdcc02cf 1146 PSR_SETUP_TIME(220),
6608804b
VS		 1147 PSR_SETUP_TIME(165),
1148 PSR_SETUP_TIME(110),
1149 PSR_SETUP_TIME(55),
1150 PSR_SETUP_TIME(0),
1151 };
1152 int i;
1153
1154 i = (psr_cap[1] & DP_PSR_SETUP_TIME_MASK) >> DP_PSR_SETUP_TIME_SHIFT;
1155 if (i >= ARRAY_SIZE(psr_setup_time_us))
1156 return -EINVAL;
1157
1158 return psr_setup_time_us[i];
1159}
1160EXPORT_SYMBOL(drm_dp_psr_setup_time);
1161
1162#undef PSR_SETUP_TIME
79c1da7c
TV		 1163
1164/**
1165 * drm_dp_start_crc() - start capture of frame CRCs
1166 * @aux: DisplayPort AUX channel
0621ce1d 1167 * @crtc: CRTC displaying the frames whose CRCs are to be captured
79c1da7c
TV		 1168 *
1169 * Returns 0 on success or a negative error code on failure.
1170 */
1171int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc)
1172{
1173 u8 buf;
1174 int ret;
1175
1176 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
1177 if (ret < 0)
1178 return ret;
1179
1180 ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK, buf | DP_TEST_SINK_START);
1181 if (ret < 0)
1182 return ret;
1183
1184 aux->crc_count = 0;
1185 aux->crtc = crtc;
1186 schedule_work(&aux->crc_work);
1187
1188 return 0;
1189}
1190EXPORT_SYMBOL(drm_dp_start_crc);
1191
1192/**
1193 * drm_dp_stop_crc() - stop capture of frame CRCs
1194 * @aux: DisplayPort AUX channel
1195 *
1196 * Returns 0 on success or a negative error code on failure.
1197 */
1198int drm_dp_stop_crc(struct drm_dp_aux *aux)
1199{
1200 u8 buf;
1201 int ret;
1202
1203 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
1204 if (ret < 0)
1205 return ret;
1206
1207 ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK, buf & ~DP_TEST_SINK_START);
1208 if (ret < 0)
1209 return ret;
1210
1211 flush_work(&aux->crc_work);
1212 aux->crtc = NULL;
1213
1214 return 0;
1215}
1216EXPORT_SYMBOL(drm_dp_stop_crc);
118b90f3 1217
76fa998a
JN		 1218struct dpcd_quirk {
1219 u8 oui[3];
0b49bbbd 1220 u8 device_id[6];
76fa998a
JN		 1221 bool is_branch;
1222 u32 quirks;
1223};
1224
1225#define OUI(first, second, third) { (first), (second), (third) }
0b49bbbd
LS		 1226#define DEVICE_ID(first, second, third, fourth, fifth, sixth) \
1227 { (first), (second), (third), (fourth), (fifth), (sixth) }
1228
1229#define DEVICE_ID_ANY DEVICE_ID(0, 0, 0, 0, 0, 0)
76fa998a
JN		 1230
1231static const struct dpcd_quirk dpcd_quirk_list[] = {
1232 /* Analogix 7737 needs reduced M and N at HBR2 link rates */
53ca2edc 1233 { OUI(0x00, 0x22, 0xb9), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_CONSTANT_N) },
e884818c
LS		 1234 /* LG LP140WF6-SPM1 eDP panel */
1235 { OUI(0x00, 0x22, 0xb9), DEVICE_ID('s', 'i', 'v', 'a', 'r', 'T'), false, BIT(DP_DPCD_QUIRK_CONSTANT_N) },
7c5c641a 1236 /* Apple panels need some additional handling to support PSR */
7974033e
VS		 1237 { OUI(0x00, 0x10, 0xfa), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_NO_PSR) },
1238 /* CH7511 seems to leave SINK_COUNT zeroed */
1239 { OUI(0x00, 0x00, 0x00), DEVICE_ID('C', 'H', '7', '5', '1', '1'), false, BIT(DP_DPCD_QUIRK_NO_SINK_COUNT) },
5b03f9d8
ML		 1240 /* Synaptics DP1.4 MST hubs can support DSC without virtual DPCD */
1241 { OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) },
639e0db2
MK		 1242 /* Apple MacBookPro 2017 15 inch eDP Retina panel reports too low DP_MAX_LINK_RATE */
1243 { OUI(0x00, 0x10, 0xfa), DEVICE_ID(101, 68, 21, 101, 98, 97), false, BIT(DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS) },
76fa998a
JN		 1244};
1245
1246#undef OUI
1247
1248/*
1249 * Get a bit mask of DPCD quirks for the sink/branch device identified by
1250 * ident. The quirk data is shared but it's up to the drivers to act on the
1251 * data.
1252 *
1253 * For now, only the OUI (first three bytes) is used, but this may be extended
1254 * to device identification string and hardware/firmware revisions later.
1255 */
1256static u32
1257drm_dp_get_quirks(const struct drm_dp_dpcd_ident *ident, bool is_branch)
1258{
1259 const struct dpcd_quirk *quirk;
1260 u32 quirks = 0;
1261 int i;
0b49bbbd 1262 u8 any_device[] = DEVICE_ID_ANY;
76fa998a
JN		 1263
1264 for (i = 0; i < ARRAY_SIZE(dpcd_quirk_list); i++) {
1265 quirk = &dpcd_quirk_list[i];
1266
1267 if (quirk->is_branch != is_branch)
1268 continue;
1269
1270 if (memcmp(quirk->oui, ident->oui, sizeof(ident->oui)) != 0)
1271 continue;
1272
0b49bbbd
LS		 1273 if (memcmp(quirk->device_id, any_device, sizeof(any_device)) != 0 &&
1274 memcmp(quirk->device_id, ident->device_id, sizeof(ident->device_id)) != 0)
1275 continue;
1276
76fa998a
JN		 1277 quirks |= quirk->quirks;
1278 }
1279
1280 return quirks;
1281}
1282
0b49bbbd
LS		 1283#undef DEVICE_ID_ANY
1284#undef DEVICE_ID
1285
0883ce81
LP		 1286struct edid_quirk {
1287 u8 mfg_id[2];
1288 u8 prod_id[2];
1289 u32 quirks;
1290};
1291
1292#define MFG(first, second) { (first), (second) }
1293#define PROD_ID(first, second) { (first), (second) }
1294
1295/*
1296 * Some devices have unreliable OUIDs where they don't set the device ID
1297 * correctly, and as a result we need to use the EDID for finding additional
1298 * DP quirks in such cases.
1299 */
1300static const struct edid_quirk edid_quirk_list[] = {
17f5d579
LP		 1301 /* Optional 4K AMOLED panel in the ThinkPad X1 Extreme 2nd Generation
1302 * only supports DPCD backlight controls
1303 */
1304 { MFG(0x4c, 0x83), PROD_ID(0x41, 0x41), BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) },
ba518bbd
LP		 1305 /*
1306 * Some Dell CML 2020 systems have panels support both AUX and PWM
1307 * backlight control, and some only support AUX backlight control. All
1308 * said panels start up in AUX mode by default, and we don't have any
1309 * support for disabling HDR mode on these panels which would be
1310 * required to switch to PWM backlight control mode (plus, I'm not
1311 * even sure we want PWM backlight controls over DPCD backlight
1312 * controls anyway...). Until we have a better way of detecting these,
1313 * force DPCD backlight mode on all of them.
1314 */
1315 { MFG(0x06, 0xaf), PROD_ID(0x9b, 0x32), BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) },
1316 { MFG(0x06, 0xaf), PROD_ID(0xeb, 0x41), BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) },
1317 { MFG(0x4d, 0x10), PROD_ID(0xc7, 0x14), BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) },
1318 { MFG(0x4d, 0x10), PROD_ID(0xe6, 0x14), BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) },
0df3ff45 1319 { MFG(0x4c, 0x83), PROD_ID(0x47, 0x41), BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) },
0883ce81
LP		 1320};
1321
1322#undef MFG
1323#undef PROD_ID
1324
1325/**
1326 * drm_dp_get_edid_quirks() - Check the EDID of a DP device to find additional
1327 * DP-specific quirks
1328 * @edid: The EDID to check
1329 *
1330 * While OUIDs are meant to be used to recognize a DisplayPort device, a lot
1331 * of manufacturers don't seem to like following standards and neglect to fill
1332 * the dev-ID in, making it impossible to only use OUIDs for determining
1333 * quirks in some cases. This function can be used to check the EDID and look
1334 * up any additional DP quirks. The bits returned by this function correspond
1335 * to the quirk bits in &drm_dp_quirk.
1336 *
1337 * Returns: a bitmask of quirks, if any. The driver can check this using
1338 * drm_dp_has_quirk().
1339 */
1340u32 drm_dp_get_edid_quirks(const struct edid *edid)
1341{
1342 const struct edid_quirk *quirk;
1343 u32 quirks = 0;
1344 int i;
1345
1346 if (!edid)
1347 return 0;
1348
1349 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
1350 quirk = &edid_quirk_list[i];
1351 if (memcmp(quirk->mfg_id, edid->mfg_id,
1352 sizeof(edid->mfg_id)) == 0 &&
1353 memcmp(quirk->prod_id, edid->prod_code,
1354 sizeof(edid->prod_code)) == 0)
1355 quirks |= quirk->quirks;
1356 }
1357
1358 DRM_DEBUG_KMS("DP sink: EDID mfg %*phD prod-ID %*phD quirks: 0x%04x\n",
1359 (int)sizeof(edid->mfg_id), edid->mfg_id,
1360 (int)sizeof(edid->prod_code), edid->prod_code, quirks);
1361
1362 return quirks;
1363}
1364EXPORT_SYMBOL(drm_dp_get_edid_quirks);
1365
118b90f3
JN		 1366/**
1367 * drm_dp_read_desc - read sink/branch descriptor from DPCD
1368 * @aux: DisplayPort AUX channel
fedbfcc6 1369 * @desc: Device descriptor to fill from DPCD
118b90f3
JN		 1370 * @is_branch: true for branch devices, false for sink devices
1371 *
1372 * Read DPCD 0x400 (sink) or 0x500 (branch) into @desc. Also debug log the
1373 * identification.
1374 *
1375 * Returns 0 on success or a negative error code on failure.
1376 */
1377int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
1378 bool is_branch)
1379{
1380 struct drm_dp_dpcd_ident *ident = &desc->ident;
1381 unsigned int offset = is_branch ? DP_BRANCH_OUI : DP_SINK_OUI;
1382 int ret, dev_id_len;
1383
1384 ret = drm_dp_dpcd_read(aux, offset, ident, sizeof(*ident));
1385 if (ret < 0)
1386 return ret;
1387
76fa998a
JN		 1388 desc->quirks = drm_dp_get_quirks(ident, is_branch);
1389
118b90f3
JN		 1390 dev_id_len = strnlen(ident->device_id, sizeof(ident->device_id));
1391
76fa998a 1392 DRM_DEBUG_KMS("DP %s: OUI %*phD dev-ID %*pE HW-rev %d.%d SW-rev %d.%d quirks 0x%04x\n",
118b90f3
JN		 1393 is_branch ? "branch" : "sink",
1394 (int)sizeof(ident->oui), ident->oui,
1395 dev_id_len, ident->device_id,
1396 ident->hw_rev >> 4, ident->hw_rev & 0xf,
76fa998a
JN		 1397 ident->sw_major_rev, ident->sw_minor_rev,
1398 desc->quirks);
118b90f3
JN		 1399
1400 return 0;
1401}
1402EXPORT_SYMBOL(drm_dp_read_desc);
05756500
MN		 1403
1404/**
05bad235
MN		 1405 * drm_dp_dsc_sink_max_slice_count() - Get the max slice count
1406 * supported by the DSC sink.
1407 * @dsc_dpcd: DSC capabilities from DPCD
1408 * @is_edp: true if its eDP, false for DP
1409 *
1410 * Read the slice capabilities DPCD register from DSC sink to get
1411 * the maximum slice count supported. This is used to populate
1412 * the DSC parameters in the &struct drm_dsc_config by the driver.
1413 * Driver creates an infoframe using these parameters to populate
1414 * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC
1415 * infoframe using the helper function drm_dsc_pps_infoframe_pack()
1416 *
1417 * Returns:
1418 * Maximum slice count supported by DSC sink or 0 its invalid
05756500
MN		 1419 */
1420u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
1421 bool is_edp)
1422{
1423 u8 slice_cap1 = dsc_dpcd[DP_DSC_SLICE_CAP_1 - DP_DSC_SUPPORT];
1424
1425 if (is_edp) {
1426 /* For eDP, register DSC_SLICE_CAPABILITIES_1 gives slice count */
1427 if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
1428 return 4;
1429 if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
1430 return 2;
1431 if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
1432 return 1;
1433 } else {
1434 /* For DP, use values from DSC_SLICE_CAP_1 and DSC_SLICE_CAP2 */
1435 u8 slice_cap2 = dsc_dpcd[DP_DSC_SLICE_CAP_2 - DP_DSC_SUPPORT];
1436
1437 if (slice_cap2 & DP_DSC_24_PER_DP_DSC_SINK)
1438 return 24;
1439 if (slice_cap2 & DP_DSC_20_PER_DP_DSC_SINK)
1440 return 20;
1441 if (slice_cap2 & DP_DSC_16_PER_DP_DSC_SINK)
1442 return 16;
1443 if (slice_cap1 & DP_DSC_12_PER_DP_DSC_SINK)
1444 return 12;
1445 if (slice_cap1 & DP_DSC_10_PER_DP_DSC_SINK)
1446 return 10;
1447 if (slice_cap1 & DP_DSC_8_PER_DP_DSC_SINK)
1448 return 8;
1449 if (slice_cap1 & DP_DSC_6_PER_DP_DSC_SINK)
1450 return 6;
1451 if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
1452 return 4;
1453 if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
1454 return 2;
1455 if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
1456 return 1;
1457 }
1458
1459 return 0;
1460}
1461EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_count);
1462
05bad235
MN		 1463/**
1464 * drm_dp_dsc_sink_line_buf_depth() - Get the line buffer depth in bits
1465 * @dsc_dpcd: DSC capabilities from DPCD
1466 *
1467 * Read the DSC DPCD register to parse the line buffer depth in bits which is
1468 * number of bits of precision within the decoder line buffer supported by
1469 * the DSC sink. This is used to populate the DSC parameters in the
1470 * &struct drm_dsc_config by the driver.
1471 * Driver creates an infoframe using these parameters to populate
1472 * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC
1473 * infoframe using the helper function drm_dsc_pps_infoframe_pack()
1474 *
1475 * Returns:
1476 * Line buffer depth supported by DSC panel or 0 its invalid
1477 */
05756500
MN		 1478u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
1479{
1480 u8 line_buf_depth = dsc_dpcd[DP_DSC_LINE_BUF_BIT_DEPTH - DP_DSC_SUPPORT];
1481
1482 switch (line_buf_depth & DP_DSC_LINE_BUF_BIT_DEPTH_MASK) {
1483 case DP_DSC_LINE_BUF_BIT_DEPTH_9:
1484 return 9;
1485 case DP_DSC_LINE_BUF_BIT_DEPTH_10:
1486 return 10;
1487 case DP_DSC_LINE_BUF_BIT_DEPTH_11:
1488 return 11;
1489 case DP_DSC_LINE_BUF_BIT_DEPTH_12:
1490 return 12;
1491 case DP_DSC_LINE_BUF_BIT_DEPTH_13:
1492 return 13;
1493 case DP_DSC_LINE_BUF_BIT_DEPTH_14:
1494 return 14;
1495 case DP_DSC_LINE_BUF_BIT_DEPTH_15:
1496 return 15;
1497 case DP_DSC_LINE_BUF_BIT_DEPTH_16:
1498 return 16;
1499 case DP_DSC_LINE_BUF_BIT_DEPTH_8:
1500 return 8;
1501 }
1502
1503 return 0;
1504}
1505EXPORT_SYMBOL(drm_dp_dsc_sink_line_buf_depth);
1506
05bad235
MN		 1507/**
1508 * drm_dp_dsc_sink_supported_input_bpcs() - Get all the input bits per component
1509 * values supported by the DSC sink.
1510 * @dsc_dpcd: DSC capabilities from DPCD
1511 * @dsc_bpc: An array to be filled by this helper with supported
1512 * input bpcs.
1513 *
1514 * Read the DSC DPCD from the sink device to parse the supported bits per
1515 * component values. This is used to populate the DSC parameters
1516 * in the &struct drm_dsc_config by the driver.
1517 * Driver creates an infoframe using these parameters to populate
1518 * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC
1519 * infoframe using the helper function drm_dsc_pps_infoframe_pack()
1520 *
1521 * Returns:
1522 * Number of input BPC values parsed from the DPCD
1523 */
4d4101c8
MN		 1524int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
1525 u8 dsc_bpc[3])
05756500 1526{
4d4101c8 1527 int num_bpc = 0;
05756500
MN		 1528 u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT];
1529
1530 if (color_depth & DP_DSC_12_BPC)
4d4101c8 1531 dsc_bpc[num_bpc++] = 12;
05756500 1532 if (color_depth & DP_DSC_10_BPC)
4d4101c8 1533 dsc_bpc[num_bpc++] = 10;
05756500 1534 if (color_depth & DP_DSC_8_BPC)
4d4101c8 1535 dsc_bpc[num_bpc++] = 8;
05756500 1536
4d4101c8 1537 return num_bpc;
05756500 1538}
4d4101c8 1539EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
4342f839
AM		 1540
1541/**
1542 * drm_dp_get_phy_test_pattern() - get the requested pattern from the sink.
1543 * @aux: DisplayPort AUX channel
1544 * @data: DP phy compliance test parameters.
1545 *
1546 * Returns 0 on success or a negative error code on failure.
1547 */
1548int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
1549 struct drm_dp_phy_test_params *data)
1550{
1551 int err;
1552 u8 rate, lanes;
1553
1554 err = drm_dp_dpcd_readb(aux, DP_TEST_LINK_RATE, &rate);
1555 if (err < 0)
1556 return err;
1557 data->link_rate = drm_dp_bw_code_to_link_rate(rate);
1558
1559 err = drm_dp_dpcd_readb(aux, DP_TEST_LANE_COUNT, &lanes);
1560 if (err < 0)
1561 return err;
1562 data->num_lanes = lanes & DP_MAX_LANE_COUNT_MASK;
1563
1564 if (lanes & DP_ENHANCED_FRAME_CAP)
1565 data->enhanced_frame_cap = true;
1566
1567 err = drm_dp_dpcd_readb(aux, DP_PHY_TEST_PATTERN, &data->phy_pattern);
1568 if (err < 0)
1569 return err;
1570
1571 switch (data->phy_pattern) {
1572 case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
1573 err = drm_dp_dpcd_read(aux, DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
1574 &data->custom80, sizeof(data->custom80));
1575 if (err < 0)
1576 return err;
1577
1578 break;
1579 case DP_PHY_TEST_PATTERN_CP2520:
1580 err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET,
1581 &data->hbr2_reset,
1582 sizeof(data->hbr2_reset));
1583 if (err < 0)
1584 return err;
1585 }
1586
1587 return 0;
1588}
1589EXPORT_SYMBOL(drm_dp_get_phy_test_pattern);
1590
1591/**
1592 * drm_dp_set_phy_test_pattern() - set the pattern to the sink.
1593 * @aux: DisplayPort AUX channel
1594 * @data: DP phy compliance test parameters.
af69bf55 1595 * @dp_rev: DP revision to use for compliance testing
4342f839
AM		 1596 *
1597 * Returns 0 on success or a negative error code on failure.
1598 */
1599int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
1600 struct drm_dp_phy_test_params *data, u8 dp_rev)
1601{
1602 int err, i;
1603 u8 link_config[2];
1604 u8 test_pattern;
1605
1606 link_config[0] = drm_dp_link_rate_to_bw_code(data->link_rate);
1607 link_config[1] = data->num_lanes;
1608 if (data->enhanced_frame_cap)
1609 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
1610 err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, link_config, 2);
1611 if (err < 0)
1612 return err;
1613
1614 test_pattern = data->phy_pattern;
1615 if (dp_rev < 0x12) {
1616 test_pattern = (test_pattern << 2) &
1617 DP_LINK_QUAL_PATTERN_11_MASK;
1618 err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET,
1619 test_pattern);
1620 if (err < 0)
1621 return err;
1622 } else {
1623 for (i = 0; i < data->num_lanes; i++) {
1624 err = drm_dp_dpcd_writeb(aux,
1625 DP_LINK_QUAL_LANE0_SET + i,
1626 test_pattern);
1627 if (err < 0)
1628 return err;
1629 }
1630 }
1631
1632 return 0;
1633}
1634EXPORT_SYMBOL(drm_dp_set_phy_test_pattern);
2ba6221c
GM		 1635
1636static const char *dp_pixelformat_get_name(enum dp_pixelformat pixelformat)
1637{
1638 if (pixelformat < 0 || pixelformat > DP_PIXELFORMAT_RESERVED)
1639 return "Invalid";
1640
1641 switch (pixelformat) {
1642 case DP_PIXELFORMAT_RGB:
1643 return "RGB";
1644 case DP_PIXELFORMAT_YUV444:
1645 return "YUV444";
1646 case DP_PIXELFORMAT_YUV422:
1647 return "YUV422";
1648 case DP_PIXELFORMAT_YUV420:
1649 return "YUV420";
1650 case DP_PIXELFORMAT_Y_ONLY:
1651 return "Y_ONLY";
1652 case DP_PIXELFORMAT_RAW:
1653 return "RAW";
1654 default:
1655 return "Reserved";
1656 }
1657}
1658
1659static const char *dp_colorimetry_get_name(enum dp_pixelformat pixelformat,
1660 enum dp_colorimetry colorimetry)
1661{
1662 if (pixelformat < 0 || pixelformat > DP_PIXELFORMAT_RESERVED)
1663 return "Invalid";
1664
1665 switch (colorimetry) {
1666 case DP_COLORIMETRY_DEFAULT:
1667 switch (pixelformat) {
1668 case DP_PIXELFORMAT_RGB:
1669 return "sRGB";
1670 case DP_PIXELFORMAT_YUV444:
1671 case DP_PIXELFORMAT_YUV422:
1672 case DP_PIXELFORMAT_YUV420:
1673 return "BT.601";
1674 case DP_PIXELFORMAT_Y_ONLY:
1675 return "DICOM PS3.14";
1676 case DP_PIXELFORMAT_RAW:
1677 return "Custom Color Profile";
1678 default:
1679 return "Reserved";
1680 }
1681 case DP_COLORIMETRY_RGB_WIDE_FIXED: /* and DP_COLORIMETRY_BT709_YCC */
1682 switch (pixelformat) {
1683 case DP_PIXELFORMAT_RGB:
1684 return "Wide Fixed";
1685 case DP_PIXELFORMAT_YUV444:
1686 case DP_PIXELFORMAT_YUV422:
1687 case DP_PIXELFORMAT_YUV420:
1688 return "BT.709";
1689 default:
1690 return "Reserved";
1691 }
1692 case DP_COLORIMETRY_RGB_WIDE_FLOAT: /* and DP_COLORIMETRY_XVYCC_601 */
1693 switch (pixelformat) {
1694 case DP_PIXELFORMAT_RGB:
1695 return "Wide Float";
1696 case DP_PIXELFORMAT_YUV444:
1697 case DP_PIXELFORMAT_YUV422:
1698 case DP_PIXELFORMAT_YUV420:
1699 return "xvYCC 601";
1700 default:
1701 return "Reserved";
1702 }
1703 case DP_COLORIMETRY_OPRGB: /* and DP_COLORIMETRY_XVYCC_709 */
1704 switch (pixelformat) {
1705 case DP_PIXELFORMAT_RGB:
1706 return "OpRGB";
1707 case DP_PIXELFORMAT_YUV444:
1708 case DP_PIXELFORMAT_YUV422:
1709 case DP_PIXELFORMAT_YUV420:
1710 return "xvYCC 709";
1711 default:
1712 return "Reserved";
1713 }
1714 case DP_COLORIMETRY_DCI_P3_RGB: /* and DP_COLORIMETRY_SYCC_601 */
1715 switch (pixelformat) {
1716 case DP_PIXELFORMAT_RGB:
1717 return "DCI-P3";
1718 case DP_PIXELFORMAT_YUV444:
1719 case DP_PIXELFORMAT_YUV422:
1720 case DP_PIXELFORMAT_YUV420:
1721 return "sYCC 601";
1722 default:
1723 return "Reserved";
1724 }
1725 case DP_COLORIMETRY_RGB_CUSTOM: /* and DP_COLORIMETRY_OPYCC_601 */
1726 switch (pixelformat) {
1727 case DP_PIXELFORMAT_RGB:
1728 return "Custom Profile";
1729 case DP_PIXELFORMAT_YUV444:
1730 case DP_PIXELFORMAT_YUV422:
1731 case DP_PIXELFORMAT_YUV420:
1732 return "OpYCC 601";
1733 default:
1734 return "Reserved";
1735 }
1736 case DP_COLORIMETRY_BT2020_RGB: /* and DP_COLORIMETRY_BT2020_CYCC */
1737 switch (pixelformat) {
1738 case DP_PIXELFORMAT_RGB:
1739 return "BT.2020 RGB";
1740 case DP_PIXELFORMAT_YUV444:
1741 case DP_PIXELFORMAT_YUV422:
1742 case DP_PIXELFORMAT_YUV420:
1743 return "BT.2020 CYCC";
1744 default:
1745 return "Reserved";
1746 }
1747 case DP_COLORIMETRY_BT2020_YCC:
1748 switch (pixelformat) {
1749 case DP_PIXELFORMAT_YUV444:
1750 case DP_PIXELFORMAT_YUV422:
1751 case DP_PIXELFORMAT_YUV420:
1752 return "BT.2020 YCC";
1753 default:
1754 return "Reserved";
1755 }
1756 default:
1757 return "Invalid";
1758 }
1759}
1760
1761static const char *dp_dynamic_range_get_name(enum dp_dynamic_range dynamic_range)
1762{
1763 switch (dynamic_range) {
1764 case DP_DYNAMIC_RANGE_VESA:
1765 return "VESA range";
1766 case DP_DYNAMIC_RANGE_CTA:
1767 return "CTA range";
1768 default:
1769 return "Invalid";
1770 }
1771}
1772
1773static const char *dp_content_type_get_name(enum dp_content_type content_type)
1774{
1775 switch (content_type) {
1776 case DP_CONTENT_TYPE_NOT_DEFINED:
1777 return "Not defined";
1778 case DP_CONTENT_TYPE_GRAPHICS:
1779 return "Graphics";
1780 case DP_CONTENT_TYPE_PHOTO:
1781 return "Photo";
1782 case DP_CONTENT_TYPE_VIDEO:
1783 return "Video";
1784 case DP_CONTENT_TYPE_GAME:
1785 return "Game";
1786 default:
1787 return "Reserved";
1788 }
1789}
1790
1791void drm_dp_vsc_sdp_log(const char *level, struct device *dev,
1792 const struct drm_dp_vsc_sdp *vsc)
1793{
1794#define DP_SDP_LOG(fmt, ...) dev_printk(level, dev, fmt, ##__VA_ARGS__)
1795 DP_SDP_LOG("DP SDP: %s, revision %u, length %u\n", "VSC",
1796 vsc->revision, vsc->length);
1797 DP_SDP_LOG(" pixelformat: %s\n",
1798 dp_pixelformat_get_name(vsc->pixelformat));
1799 DP_SDP_LOG(" colorimetry: %s\n",
1800 dp_colorimetry_get_name(vsc->pixelformat, vsc->colorimetry));
1801 DP_SDP_LOG(" bpc: %u\n", vsc->bpc);
1802 DP_SDP_LOG(" dynamic range: %s\n",
1803 dp_dynamic_range_get_name(vsc->dynamic_range));
1804 DP_SDP_LOG(" content type: %s\n",
1805 dp_content_type_get_name(vsc->content_type));
1806#undef DP_SDP_LOG
1807}
1808EXPORT_SYMBOL(drm_dp_vsc_sdp_log);
Linux 6.x block layer and io_uring tree(s)