[linux-2.6-block.git] / drivers / gpu / drm / drm_cache.c

/**************************************************************************
 *
 * Copyright (c) 2006-2007 Tungsten Graphics, Inc., Cedar Park, TX., USA
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
 * USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 **************************************************************************/
/*
 * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
 */

#include <linux/export.h>
#include <drm/drmP.h>

#if defined(CONFIG_X86)
#include <asm/smp.h>

/*
 * clflushopt is an unordered instruction which needs fencing with mfence or
 * sfence to avoid ordering issues.  For drm_clflush_page this fencing happens
 * in the caller.
 */
static void
drm_clflush_page(struct page *page)
{
	uint8_t *page_virtual;
	unsigned int i;
	const int size = boot_cpu_data.x86_clflush_size;

	if (unlikely(page == NULL))
		return;

	page_virtual = kmap_atomic(page);
	for (i = 0; i < PAGE_SIZE; i += size)
		clflushopt(page_virtual + i);
	kunmap_atomic(page_virtual);
}

static void drm_cache_flush_clflush(struct page *pages[],
				    unsigned long num_pages)
{
	unsigned long i;

	mb();
	for (i = 0; i < num_pages; i++)
		drm_clflush_page(*pages++);
	mb();
}
#endif

void
drm_clflush_pages(struct page *pages[], unsigned long num_pages)
{

#if defined(CONFIG_X86)
	if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
		drm_cache_flush_clflush(pages, num_pages);
		return;
	}

	if (wbinvd_on_all_cpus())
		printk(KERN_ERR "Timed out waiting for cache flush.\n");

#elif defined(__powerpc__)
	unsigned long i;
	for (i = 0; i < num_pages; i++) {
		struct page *page = pages[i];
		void *page_virtual;

		if (unlikely(page == NULL))
			continue;

		page_virtual = kmap_atomic(page);
		flush_dcache_range((unsigned long)page_virtual,
				   (unsigned long)page_virtual + PAGE_SIZE);
		kunmap_atomic(page_virtual);
	}
#else
	printk(KERN_ERR "Architecture has no drm_cache.c support\n");
	WARN_ON_ONCE(1);
#endif
}
EXPORT_SYMBOL(drm_clflush_pages);

void
drm_clflush_sg(struct sg_table *st)
{
#if defined(CONFIG_X86)
	if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
		struct sg_page_iter sg_iter;

		mb();
		for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
			drm_clflush_page(sg_page_iter_page(&sg_iter));
		mb();

		return;
	}

	if (wbinvd_on_all_cpus())
		printk(KERN_ERR "Timed out waiting for cache flush.\n");
#else
	printk(KERN_ERR "Architecture has no drm_cache.c support\n");
	WARN_ON_ONCE(1);
#endif
}
EXPORT_SYMBOL(drm_clflush_sg);

void
drm_clflush_virt_range(void *addr, unsigned long length)
{
#if defined(CONFIG_X86)
	if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
		const int size = boot_cpu_data.x86_clflush_size;
		void *end = addr + length;
		addr = (void *)(((unsigned long)addr) & -size);
		mb();
		for (; addr < end; addr += size)
			clflushopt(addr);
		mb();
		return;
	}

	if (wbinvd_on_all_cpus())
		printk(KERN_ERR "Timed out waiting for cache flush.\n");
#else
	printk(KERN_ERR "Architecture has no drm_cache.c support\n");
	WARN_ON_ONCE(1);
#endif
}
EXPORT_SYMBOL(drm_clflush_virt_range);
Commit	Line	Data
673a394b EA	1	/**************************************************************************
	2	*
	3	* Copyright (c) 2006-2007 Tungsten Graphics, Inc., Cedar Park, TX., USA
	4	* All Rights Reserved.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the
	8	* "Software"), to deal in the Software without restriction, including
	9	* without limitation the rights to use, copy, modify, merge, publish,
	10	* distribute, sub license, and/or sell copies of the Software, and to
	11	* permit persons to whom the Software is furnished to do so, subject to
	12	* the following conditions:
	13	*
	14	* The above copyright notice and this permission notice (including the
	15	* next paragraph) shall be included in all copies or substantial portions
	16	* of the Software.
	17	*
	18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	19	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	20	* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
	21	* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
	22	* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
	23	* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
	24	* USE OR OTHER DEALINGS IN THE SOFTWARE.
	25	*
	26	**************************************************************************/
	27	/*
	28	* Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
	29	*/
	30
2d1a8a48	31	#include <linux/export.h>
760285e7	32	#include <drm/drmP.h>
673a394b EA	33
673a394b EA	34	#if defined(CONFIG_X86)
b04d4a38	35	#include <asm/smp.h>
2a0c772f RZ	36
	37	/*
	38	* clflushopt is an unordered instruction which needs fencing with mfence or
	39	* sfence to avoid ordering issues. For drm_clflush_page this fencing happens
	40	* in the caller.
	41	*/
673a394b EA	42	static void
	43	drm_clflush_page(struct page *page)
	44	{
	45	uint8_t *page_virtual;
	46	unsigned int i;
87229ad9	47	const int size = boot_cpu_data.x86_clflush_size;
673a394b EA	48
	49	if (unlikely(page == NULL))
	50	return;
	51
1c9c20f6	52	page_virtual = kmap_atomic(page);
87229ad9	53	for (i = 0; i < PAGE_SIZE; i += size)
2a0c772f	54	clflushopt(page_virtual + i);
1c9c20f6	55	kunmap_atomic(page_virtual);
673a394b	56	}
673a394b	57
c9c97b8c DA	58	static void drm_cache_flush_clflush(struct page *pages[],
	59	unsigned long num_pages)
	60	{
	61	unsigned long i;
	62
	63	mb();
	64	for (i = 0; i < num_pages; i++)
	65	drm_clflush_page(*pages++);
	66	mb();
	67	}
c9c97b8c	68	#endif
ed017d9f	69
673a394b EA	70	void
	71	drm_clflush_pages(struct page *pages[], unsigned long num_pages)
	72	{
	73
	74	#if defined(CONFIG_X86)
906bf7fd	75	if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
c9c97b8c	76	drm_cache_flush_clflush(pages, num_pages);
673a394b EA	77	return;
673a394b EA	78	}
673a394b	79
b04d4a38	80	if (wbinvd_on_all_cpus())
c9c97b8c DA	81	printk(KERN_ERR "Timed out waiting for cache flush.\n");
	82
	83	#elif defined(__powerpc__)
	84	unsigned long i;
	85	for (i = 0; i < num_pages; i++) {
	86	struct page *page = pages[i];
	87	void *page_virtual;
	88
	89	if (unlikely(page == NULL))
	90	continue;
	91
1c9c20f6	92	page_virtual = kmap_atomic(page);
c9c97b8c DA	93	flush_dcache_range((unsigned long)page_virtual,
c9c97b8c DA	94	(unsigned long)page_virtual + PAGE_SIZE);
1c9c20f6	95	kunmap_atomic(page_virtual);
c9c97b8c DA	96	}
c9c97b8c DA	97	#else
ed017d9f DA	98	printk(KERN_ERR "Architecture has no drm_cache.c support\n");
ed017d9f DA	99	WARN_ON_ONCE(1);
e0f0754f	100	#endif
673a394b EA	101	}
673a394b EA	102	EXPORT_SYMBOL(drm_clflush_pages);
6d5cd9cb	103
9da3da66 CW	104	void
	105	drm_clflush_sg(struct sg_table *st)
	106	{
	107	#if defined(CONFIG_X86)
906bf7fd	108	if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
f5ddf697	109	struct sg_page_iter sg_iter;
9da3da66 CW	110
9da3da66 CW	111	mb();
f5ddf697	112	for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
2db76d7c	113	drm_clflush_page(sg_page_iter_page(&sg_iter));
9da3da66 CW	114	mb();
	115
	116	return;
	117	}
	118
b04d4a38	119	if (wbinvd_on_all_cpus())
9da3da66 CW	120	printk(KERN_ERR "Timed out waiting for cache flush.\n");
	121	#else
	122	printk(KERN_ERR "Architecture has no drm_cache.c support\n");
	123	WARN_ON_ONCE(1);
	124	#endif
	125	}
	126	EXPORT_SYMBOL(drm_clflush_sg);
	127
6d5cd9cb	128	void
c2d15359	129	drm_clflush_virt_range(void *addr, unsigned long length)
6d5cd9cb DV	130	{
6d5cd9cb DV	131	#if defined(CONFIG_X86)
906bf7fd	132	if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
afcd950c	133	const int size = boot_cpu_data.x86_clflush_size;
c2d15359	134	void *end = addr + length;
afcd950c	135	addr = (void *)(((unsigned long)addr) & -size);
6d5cd9cb	136	mb();
afcd950c	137	for (; addr < end; addr += size)
79270968	138	clflushopt(addr);
6d5cd9cb DV	139	mb();
	140	return;
	141	}
	142
b04d4a38	143	if (wbinvd_on_all_cpus())
6d5cd9cb DV	144	printk(KERN_ERR "Timed out waiting for cache flush.\n");
	145	#else
	146	printk(KERN_ERR "Architecture has no drm_cache.c support\n");
	147	WARN_ON_ONCE(1);
	148	#endif
	149	}
	150	EXPORT_SYMBOL(drm_clflush_virt_range);