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673a394b EA |
1 | /************************************************************************** |
2 | * | |
3 | * Copyright (c) 2006-2007 Tungsten Graphics, Inc., Cedar Park, TX., USA | |
4 | * All Rights Reserved. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the | |
8 | * "Software"), to deal in the Software without restriction, including | |
9 | * without limitation the rights to use, copy, modify, merge, publish, | |
10 | * distribute, sub license, and/or sell copies of the Software, and to | |
11 | * permit persons to whom the Software is furnished to do so, subject to | |
12 | * the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice (including the | |
15 | * next paragraph) shall be included in all copies or substantial portions | |
16 | * of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | |
22 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | |
23 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | |
24 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | |
25 | * | |
26 | **************************************************************************/ | |
27 | /* | |
28 | * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com> | |
29 | */ | |
30 | ||
2d1a8a48 | 31 | #include <linux/export.h> |
b46b54a5 CW |
32 | #include <linux/highmem.h> |
33 | ||
34 | #include <drm/drm_cache.h> | |
673a394b EA |
35 | |
36 | #if defined(CONFIG_X86) | |
b04d4a38 | 37 | #include <asm/smp.h> |
2a0c772f RZ |
38 | |
39 | /* | |
40 | * clflushopt is an unordered instruction which needs fencing with mfence or | |
41 | * sfence to avoid ordering issues. For drm_clflush_page this fencing happens | |
42 | * in the caller. | |
43 | */ | |
673a394b EA |
44 | static void |
45 | drm_clflush_page(struct page *page) | |
46 | { | |
47 | uint8_t *page_virtual; | |
48 | unsigned int i; | |
87229ad9 | 49 | const int size = boot_cpu_data.x86_clflush_size; |
673a394b EA |
50 | |
51 | if (unlikely(page == NULL)) | |
52 | return; | |
53 | ||
1c9c20f6 | 54 | page_virtual = kmap_atomic(page); |
87229ad9 | 55 | for (i = 0; i < PAGE_SIZE; i += size) |
2a0c772f | 56 | clflushopt(page_virtual + i); |
1c9c20f6 | 57 | kunmap_atomic(page_virtual); |
673a394b | 58 | } |
673a394b | 59 | |
c9c97b8c DA |
60 | static void drm_cache_flush_clflush(struct page *pages[], |
61 | unsigned long num_pages) | |
62 | { | |
63 | unsigned long i; | |
64 | ||
65 | mb(); | |
66 | for (i = 0; i < num_pages; i++) | |
67 | drm_clflush_page(*pages++); | |
68 | mb(); | |
69 | } | |
c9c97b8c | 70 | #endif |
ed017d9f | 71 | |
f0e36723 GKB |
72 | /** |
73 | * drm_clflush_pages - Flush dcache lines of a set of pages. | |
74 | * @pages: List of pages to be flushed. | |
75 | * @num_pages: Number of pages in the array. | |
76 | * | |
77 | * Flush every data cache line entry that points to an address belonging | |
78 | * to a page in the array. | |
79 | */ | |
673a394b EA |
80 | void |
81 | drm_clflush_pages(struct page *pages[], unsigned long num_pages) | |
82 | { | |
83 | ||
84 | #if defined(CONFIG_X86) | |
906bf7fd | 85 | if (static_cpu_has(X86_FEATURE_CLFLUSH)) { |
c9c97b8c | 86 | drm_cache_flush_clflush(pages, num_pages); |
673a394b EA |
87 | return; |
88 | } | |
673a394b | 89 | |
b04d4a38 | 90 | if (wbinvd_on_all_cpus()) |
499447db | 91 | pr_err("Timed out waiting for cache flush\n"); |
c9c97b8c DA |
92 | |
93 | #elif defined(__powerpc__) | |
94 | unsigned long i; | |
95 | for (i = 0; i < num_pages; i++) { | |
96 | struct page *page = pages[i]; | |
97 | void *page_virtual; | |
98 | ||
99 | if (unlikely(page == NULL)) | |
100 | continue; | |
101 | ||
1c9c20f6 | 102 | page_virtual = kmap_atomic(page); |
c9c97b8c DA |
103 | flush_dcache_range((unsigned long)page_virtual, |
104 | (unsigned long)page_virtual + PAGE_SIZE); | |
1c9c20f6 | 105 | kunmap_atomic(page_virtual); |
c9c97b8c DA |
106 | } |
107 | #else | |
499447db | 108 | pr_err("Architecture has no drm_cache.c support\n"); |
ed017d9f | 109 | WARN_ON_ONCE(1); |
e0f0754f | 110 | #endif |
673a394b EA |
111 | } |
112 | EXPORT_SYMBOL(drm_clflush_pages); | |
6d5cd9cb | 113 | |
f0e36723 GKB |
114 | /** |
115 | * drm_clflush_sg - Flush dcache lines pointing to a scather-gather. | |
116 | * @st: struct sg_table. | |
117 | * | |
118 | * Flush every data cache line entry that points to an address in the | |
119 | * sg. | |
120 | */ | |
9da3da66 CW |
121 | void |
122 | drm_clflush_sg(struct sg_table *st) | |
123 | { | |
124 | #if defined(CONFIG_X86) | |
906bf7fd | 125 | if (static_cpu_has(X86_FEATURE_CLFLUSH)) { |
f5ddf697 | 126 | struct sg_page_iter sg_iter; |
9da3da66 CW |
127 | |
128 | mb(); | |
f5ddf697 | 129 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) |
2db76d7c | 130 | drm_clflush_page(sg_page_iter_page(&sg_iter)); |
9da3da66 CW |
131 | mb(); |
132 | ||
133 | return; | |
134 | } | |
135 | ||
b04d4a38 | 136 | if (wbinvd_on_all_cpus()) |
499447db | 137 | pr_err("Timed out waiting for cache flush\n"); |
9da3da66 | 138 | #else |
499447db | 139 | pr_err("Architecture has no drm_cache.c support\n"); |
9da3da66 CW |
140 | WARN_ON_ONCE(1); |
141 | #endif | |
142 | } | |
143 | EXPORT_SYMBOL(drm_clflush_sg); | |
144 | ||
f0e36723 GKB |
145 | /** |
146 | * drm_clflush_virt_range - Flush dcache lines of a region | |
147 | * @addr: Initial kernel memory address. | |
148 | * @length: Region size. | |
149 | * | |
150 | * Flush every data cache line entry that points to an address in the | |
151 | * region requested. | |
152 | */ | |
6d5cd9cb | 153 | void |
c2d15359 | 154 | drm_clflush_virt_range(void *addr, unsigned long length) |
6d5cd9cb DV |
155 | { |
156 | #if defined(CONFIG_X86) | |
906bf7fd | 157 | if (static_cpu_has(X86_FEATURE_CLFLUSH)) { |
afcd950c | 158 | const int size = boot_cpu_data.x86_clflush_size; |
c2d15359 | 159 | void *end = addr + length; |
afcd950c | 160 | addr = (void *)(((unsigned long)addr) & -size); |
6d5cd9cb | 161 | mb(); |
afcd950c | 162 | for (; addr < end; addr += size) |
79270968 | 163 | clflushopt(addr); |
396f5d62 | 164 | clflushopt(end - 1); /* force serialisation */ |
6d5cd9cb DV |
165 | mb(); |
166 | return; | |
167 | } | |
168 | ||
b04d4a38 | 169 | if (wbinvd_on_all_cpus()) |
499447db | 170 | pr_err("Timed out waiting for cache flush\n"); |
6d5cd9cb | 171 | #else |
499447db | 172 | pr_err("Architecture has no drm_cache.c support\n"); |
6d5cd9cb DV |
173 | WARN_ON_ONCE(1); |
174 | #endif | |
175 | } | |
176 | EXPORT_SYMBOL(drm_clflush_virt_range); |