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f9aa76a8 DA |
1 | /* |
2 | * Copyright 2012 Red Hat | |
3 | * | |
4 | * This file is subject to the terms and conditions of the GNU General | |
5 | * Public License version 2. See the file COPYING in the main | |
6 | * directory of this archive for more details. | |
7 | * | |
8 | * Authors: Matthew Garrett | |
9 | * Dave Airlie | |
10 | */ | |
760285e7 DH |
11 | #include <drm/drmP.h> |
12 | #include <drm/drm_crtc_helper.h> | |
f9aa76a8 DA |
13 | |
14 | #include "cirrus_drv.h" | |
15 | ||
16 | ||
17 | static void cirrus_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
18 | { | |
19 | struct cirrus_framebuffer *cirrus_fb = to_cirrus_framebuffer(fb); | |
20 | if (cirrus_fb->obj) | |
21 | drm_gem_object_unreference_unlocked(cirrus_fb->obj); | |
22 | drm_framebuffer_cleanup(fb); | |
23 | kfree(fb); | |
24 | } | |
25 | ||
f9aa76a8 DA |
26 | static const struct drm_framebuffer_funcs cirrus_fb_funcs = { |
27 | .destroy = cirrus_user_framebuffer_destroy, | |
f9aa76a8 DA |
28 | }; |
29 | ||
30 | int cirrus_framebuffer_init(struct drm_device *dev, | |
31 | struct cirrus_framebuffer *gfb, | |
1eb83451 | 32 | const struct drm_mode_fb_cmd2 *mode_cmd, |
f9aa76a8 DA |
33 | struct drm_gem_object *obj) |
34 | { | |
35 | int ret; | |
36 | ||
c7d73f6a DV |
37 | drm_helper_mode_fill_fb_struct(&gfb->base, mode_cmd); |
38 | gfb->obj = obj; | |
f9aa76a8 DA |
39 | ret = drm_framebuffer_init(dev, &gfb->base, &cirrus_fb_funcs); |
40 | if (ret) { | |
41 | DRM_ERROR("drm_framebuffer_init failed: %d\n", ret); | |
42 | return ret; | |
43 | } | |
f9aa76a8 DA |
44 | return 0; |
45 | } | |
46 | ||
47 | static struct drm_framebuffer * | |
48 | cirrus_user_framebuffer_create(struct drm_device *dev, | |
49 | struct drm_file *filp, | |
1eb83451 | 50 | const struct drm_mode_fb_cmd2 *mode_cmd) |
f9aa76a8 | 51 | { |
8975626e | 52 | struct cirrus_device *cdev = dev->dev_private; |
f9aa76a8 DA |
53 | struct drm_gem_object *obj; |
54 | struct cirrus_framebuffer *cirrus_fb; | |
55 | int ret; | |
56 | u32 bpp, depth; | |
57 | ||
58 | drm_fb_get_bpp_depth(mode_cmd->pixel_format, &depth, &bpp); | |
8975626e ZR |
59 | |
60 | if (!cirrus_check_framebuffer(cdev, mode_cmd->width, mode_cmd->height, | |
61 | bpp, mode_cmd->pitches[0])) | |
f9aa76a8 DA |
62 | return ERR_PTR(-EINVAL); |
63 | ||
64 | obj = drm_gem_object_lookup(dev, filp, mode_cmd->handles[0]); | |
65 | if (obj == NULL) | |
66 | return ERR_PTR(-ENOENT); | |
67 | ||
68 | cirrus_fb = kzalloc(sizeof(*cirrus_fb), GFP_KERNEL); | |
69 | if (!cirrus_fb) { | |
70 | drm_gem_object_unreference_unlocked(obj); | |
71 | return ERR_PTR(-ENOMEM); | |
72 | } | |
73 | ||
74 | ret = cirrus_framebuffer_init(dev, cirrus_fb, mode_cmd, obj); | |
75 | if (ret) { | |
76 | drm_gem_object_unreference_unlocked(obj); | |
77 | kfree(cirrus_fb); | |
78 | return ERR_PTR(ret); | |
79 | } | |
80 | return &cirrus_fb->base; | |
81 | } | |
82 | ||
83 | static const struct drm_mode_config_funcs cirrus_mode_funcs = { | |
84 | .fb_create = cirrus_user_framebuffer_create, | |
85 | }; | |
86 | ||
87 | /* Unmap the framebuffer from the core and release the memory */ | |
88 | static void cirrus_vram_fini(struct cirrus_device *cdev) | |
89 | { | |
90 | iounmap(cdev->rmmio); | |
91 | cdev->rmmio = NULL; | |
92 | if (cdev->mc.vram_base) | |
93 | release_mem_region(cdev->mc.vram_base, cdev->mc.vram_size); | |
94 | } | |
95 | ||
96 | /* Map the framebuffer from the card and configure the core */ | |
97 | static int cirrus_vram_init(struct cirrus_device *cdev) | |
98 | { | |
99 | /* BAR 0 is VRAM */ | |
100 | cdev->mc.vram_base = pci_resource_start(cdev->dev->pdev, 0); | |
8975626e | 101 | cdev->mc.vram_size = pci_resource_len(cdev->dev->pdev, 0); |
f9aa76a8 DA |
102 | |
103 | if (!request_mem_region(cdev->mc.vram_base, cdev->mc.vram_size, | |
104 | "cirrusdrmfb_vram")) { | |
105 | DRM_ERROR("can't reserve VRAM\n"); | |
106 | return -ENXIO; | |
107 | } | |
108 | ||
109 | return 0; | |
110 | } | |
111 | ||
112 | /* | |
113 | * Our emulated hardware has two sets of memory. One is video RAM and can | |
114 | * simply be used as a linear framebuffer - the other provides mmio access | |
115 | * to the display registers. The latter can also be accessed via IO port | |
116 | * access, but we map the range and use mmio to program them instead | |
117 | */ | |
118 | ||
119 | int cirrus_device_init(struct cirrus_device *cdev, | |
120 | struct drm_device *ddev, | |
121 | struct pci_dev *pdev, uint32_t flags) | |
122 | { | |
123 | int ret; | |
124 | ||
125 | cdev->dev = ddev; | |
126 | cdev->flags = flags; | |
127 | ||
128 | /* Hardcode the number of CRTCs to 1 */ | |
129 | cdev->num_crtc = 1; | |
130 | ||
131 | /* BAR 0 is the framebuffer, BAR 1 contains registers */ | |
132 | cdev->rmmio_base = pci_resource_start(cdev->dev->pdev, 1); | |
133 | cdev->rmmio_size = pci_resource_len(cdev->dev->pdev, 1); | |
134 | ||
135 | if (!request_mem_region(cdev->rmmio_base, cdev->rmmio_size, | |
136 | "cirrusdrmfb_mmio")) { | |
137 | DRM_ERROR("can't reserve mmio registers\n"); | |
138 | return -ENOMEM; | |
139 | } | |
140 | ||
141 | cdev->rmmio = ioremap(cdev->rmmio_base, cdev->rmmio_size); | |
142 | ||
143 | if (cdev->rmmio == NULL) | |
144 | return -ENOMEM; | |
145 | ||
146 | ret = cirrus_vram_init(cdev); | |
147 | if (ret) { | |
148 | release_mem_region(cdev->rmmio_base, cdev->rmmio_size); | |
149 | return ret; | |
150 | } | |
151 | ||
152 | return 0; | |
153 | } | |
154 | ||
155 | void cirrus_device_fini(struct cirrus_device *cdev) | |
156 | { | |
157 | release_mem_region(cdev->rmmio_base, cdev->rmmio_size); | |
158 | cirrus_vram_fini(cdev); | |
159 | } | |
160 | ||
161 | /* | |
162 | * Functions here will be called by the core once it's bound the driver to | |
163 | * a PCI device | |
164 | */ | |
165 | ||
166 | int cirrus_driver_load(struct drm_device *dev, unsigned long flags) | |
167 | { | |
168 | struct cirrus_device *cdev; | |
169 | int r; | |
170 | ||
171 | cdev = kzalloc(sizeof(struct cirrus_device), GFP_KERNEL); | |
172 | if (cdev == NULL) | |
173 | return -ENOMEM; | |
174 | dev->dev_private = (void *)cdev; | |
175 | ||
176 | r = cirrus_device_init(cdev, dev, dev->pdev, flags); | |
177 | if (r) { | |
178 | dev_err(&dev->pdev->dev, "Fatal error during GPU init: %d\n", r); | |
179 | goto out; | |
180 | } | |
181 | ||
182 | r = cirrus_mm_init(cdev); | |
a7ca52e1 | 183 | if (r) { |
f9aa76a8 | 184 | dev_err(&dev->pdev->dev, "fatal err on mm init\n"); |
a7ca52e1 ZR |
185 | goto out; |
186 | } | |
f9aa76a8 DA |
187 | |
188 | r = cirrus_modeset_init(cdev); | |
a7ca52e1 | 189 | if (r) { |
f9aa76a8 | 190 | dev_err(&dev->pdev->dev, "Fatal error during modeset init: %d\n", r); |
a7ca52e1 ZR |
191 | goto out; |
192 | } | |
f9aa76a8 DA |
193 | |
194 | dev->mode_config.funcs = (void *)&cirrus_mode_funcs; | |
a7ca52e1 ZR |
195 | |
196 | return 0; | |
f9aa76a8 | 197 | out: |
a7ca52e1 | 198 | cirrus_driver_unload(dev); |
f9aa76a8 DA |
199 | return r; |
200 | } | |
201 | ||
202 | int cirrus_driver_unload(struct drm_device *dev) | |
203 | { | |
204 | struct cirrus_device *cdev = dev->dev_private; | |
205 | ||
206 | if (cdev == NULL) | |
207 | return 0; | |
208 | cirrus_modeset_fini(cdev); | |
209 | cirrus_mm_fini(cdev); | |
210 | cirrus_device_fini(cdev); | |
211 | kfree(cdev); | |
212 | dev->dev_private = NULL; | |
213 | return 0; | |
214 | } | |
215 | ||
216 | int cirrus_gem_create(struct drm_device *dev, | |
217 | u32 size, bool iskernel, | |
218 | struct drm_gem_object **obj) | |
219 | { | |
220 | struct cirrus_bo *cirrusbo; | |
221 | int ret; | |
222 | ||
223 | *obj = NULL; | |
224 | ||
225 | size = roundup(size, PAGE_SIZE); | |
226 | if (size == 0) | |
227 | return -EINVAL; | |
228 | ||
229 | ret = cirrus_bo_create(dev, size, 0, 0, &cirrusbo); | |
230 | if (ret) { | |
231 | if (ret != -ERESTARTSYS) | |
232 | DRM_ERROR("failed to allocate GEM object\n"); | |
233 | return ret; | |
234 | } | |
235 | *obj = &cirrusbo->gem; | |
236 | return 0; | |
237 | } | |
238 | ||
239 | int cirrus_dumb_create(struct drm_file *file, | |
240 | struct drm_device *dev, | |
241 | struct drm_mode_create_dumb *args) | |
242 | { | |
243 | int ret; | |
244 | struct drm_gem_object *gobj; | |
245 | u32 handle; | |
246 | ||
247 | args->pitch = args->width * ((args->bpp + 7) / 8); | |
248 | args->size = args->pitch * args->height; | |
249 | ||
250 | ret = cirrus_gem_create(dev, args->size, false, | |
251 | &gobj); | |
252 | if (ret) | |
253 | return ret; | |
254 | ||
255 | ret = drm_gem_handle_create(file, gobj, &handle); | |
256 | drm_gem_object_unreference_unlocked(gobj); | |
257 | if (ret) | |
258 | return ret; | |
259 | ||
260 | args->handle = handle; | |
261 | return 0; | |
262 | } | |
263 | ||
70d5422b | 264 | static void cirrus_bo_unref(struct cirrus_bo **bo) |
f9aa76a8 DA |
265 | { |
266 | struct ttm_buffer_object *tbo; | |
267 | ||
268 | if ((*bo) == NULL) | |
269 | return; | |
270 | ||
271 | tbo = &((*bo)->bo); | |
272 | ttm_bo_unref(&tbo); | |
275c6322 | 273 | *bo = NULL; |
f9aa76a8 DA |
274 | } |
275 | ||
276 | void cirrus_gem_free_object(struct drm_gem_object *obj) | |
277 | { | |
278 | struct cirrus_bo *cirrus_bo = gem_to_cirrus_bo(obj); | |
279 | ||
f9aa76a8 DA |
280 | cirrus_bo_unref(&cirrus_bo); |
281 | } | |
282 | ||
283 | ||
284 | static inline u64 cirrus_bo_mmap_offset(struct cirrus_bo *bo) | |
285 | { | |
72525b3f | 286 | return drm_vma_node_offset_addr(&bo->bo.vma_node); |
f9aa76a8 DA |
287 | } |
288 | ||
289 | int | |
290 | cirrus_dumb_mmap_offset(struct drm_file *file, | |
291 | struct drm_device *dev, | |
292 | uint32_t handle, | |
293 | uint64_t *offset) | |
294 | { | |
295 | struct drm_gem_object *obj; | |
f9aa76a8 DA |
296 | struct cirrus_bo *bo; |
297 | ||
f9aa76a8 | 298 | obj = drm_gem_object_lookup(dev, file, handle); |
6cc56234 DV |
299 | if (obj == NULL) |
300 | return -ENOENT; | |
f9aa76a8 DA |
301 | |
302 | bo = gem_to_cirrus_bo(obj); | |
303 | *offset = cirrus_bo_mmap_offset(bo); | |
304 | ||
6cc56234 | 305 | drm_gem_object_unreference_unlocked(obj); |
f9aa76a8 | 306 | |
6cc56234 | 307 | return 0; |
f9aa76a8 | 308 | } |
8975626e ZR |
309 | |
310 | bool cirrus_check_framebuffer(struct cirrus_device *cdev, int width, int height, | |
311 | int bpp, int pitch) | |
312 | { | |
313 | const int max_pitch = 0x1FF << 3; /* (4096 - 1) & ~111b bytes */ | |
314 | const int max_size = cdev->mc.vram_size; | |
315 | ||
7f551b1e TI |
316 | if (bpp > cirrus_bpp) |
317 | return false; | |
8975626e ZR |
318 | if (bpp > 32) |
319 | return false; | |
320 | ||
321 | if (pitch > max_pitch) | |
322 | return false; | |
323 | ||
324 | if (pitch * height > max_size) | |
325 | return false; | |
326 | ||
327 | return true; | |
328 | } |