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drm/bridge: sn65dsi83: Switch to devm MIPI-DSI helpers
[linux-block.git] / drivers / gpu / drm / bridge / ti-sn65dsi83.c
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ceb515ba
MV		 1// SPDX-License-Identifier: GPL-2.0
2/*
3 * TI SN65DSI83,84,85 driver
4 *
5 * Currently supported:
6 * - SN65DSI83
7 * = 1x Single-link DSI ~ 1x Single-link LVDS
8 * - Supported
9 * - Single-link LVDS mode tested
10 * - SN65DSI84
11 * = 1x Single-link DSI ~ 2x Single-link or 1x Dual-link LVDS
12 * - Supported
13 * - Dual-link LVDS mode tested
14 * - 2x Single-link LVDS mode unsupported
15 * (should be easy to add by someone who has the HW)
16 * - SN65DSI85
17 * = 2x Single-link or 1x Dual-link DSI ~ 2x Single-link or 1x Dual-link LVDS
18 * - Unsupported
19 * (should be easy to add by someone who has the HW)
20 *
21 * Copyright (C) 2021 Marek Vasut <marex@denx.de>
22 *
23 * Based on previous work of:
24 * Valentin Raevsky <valentin@compulab.co.il>
25 * Philippe Schenker <philippe.schenker@toradex.com>
26 */
27
28#include <linux/bits.h>
29#include <linux/clk.h>
30#include <linux/gpio/consumer.h>
31#include <linux/i2c.h>
32#include <linux/module.h>
33#include <linux/of_device.h>
34#include <linux/of_graph.h>
35#include <linux/regmap.h>
36
37#include <drm/drm_atomic_helper.h>
38#include <drm/drm_bridge.h>
39#include <drm/drm_mipi_dsi.h>
40#include <drm/drm_of.h>
41#include <drm/drm_panel.h>
42#include <drm/drm_print.h>
43#include <drm/drm_probe_helper.h>
44
45/* ID registers */
46#define REG_ID(n) (0x00 + (n))
47/* Reset and clock registers */
48#define REG_RC_RESET 0x09
49#define REG_RC_RESET_SOFT_RESET BIT(0)
50#define REG_RC_LVDS_PLL 0x0a
51#define REG_RC_LVDS_PLL_PLL_EN_STAT BIT(7)
52#define REG_RC_LVDS_PLL_LVDS_CLK_RANGE(n) (((n) & 0x7) << 1)
53#define REG_RC_LVDS_PLL_HS_CLK_SRC_DPHY BIT(0)
54#define REG_RC_DSI_CLK 0x0b
55#define REG_RC_DSI_CLK_DSI_CLK_DIVIDER(n) (((n) & 0x1f) << 3)
56#define REG_RC_DSI_CLK_REFCLK_MULTIPLIER(n) ((n) & 0x3)
57#define REG_RC_PLL_EN 0x0d
58#define REG_RC_PLL_EN_PLL_EN BIT(0)
59/* DSI registers */
60#define REG_DSI_LANE 0x10
61#define REG_DSI_LANE_LEFT_RIGHT_PIXELS BIT(7) /* DSI85-only */
62#define REG_DSI_LANE_DSI_CHANNEL_MODE_DUAL 0 /* DSI85-only */
63#define REG_DSI_LANE_DSI_CHANNEL_MODE_2SINGLE BIT(6) /* DSI85-only */
64#define REG_DSI_LANE_DSI_CHANNEL_MODE_SINGLE BIT(5)
65#define REG_DSI_LANE_CHA_DSI_LANES(n) (((n) & 0x3) << 3)
66#define REG_DSI_LANE_CHB_DSI_LANES(n) (((n) & 0x3) << 1)
67#define REG_DSI_LANE_SOT_ERR_TOL_DIS BIT(0)
68#define REG_DSI_EQ 0x11
69#define REG_DSI_EQ_CHA_DSI_DATA_EQ(n) (((n) & 0x3) << 6)
70#define REG_DSI_EQ_CHA_DSI_CLK_EQ(n) (((n) & 0x3) << 2)
71#define REG_DSI_CLK 0x12
72#define REG_DSI_CLK_CHA_DSI_CLK_RANGE(n) ((n) & 0xff)
73/* LVDS registers */
74#define REG_LVDS_FMT 0x18
75#define REG_LVDS_FMT_DE_NEG_POLARITY BIT(7)
76#define REG_LVDS_FMT_HS_NEG_POLARITY BIT(6)
77#define REG_LVDS_FMT_VS_NEG_POLARITY BIT(5)
78#define REG_LVDS_FMT_LVDS_LINK_CFG BIT(4) /* 0:AB 1:A-only */
79#define REG_LVDS_FMT_CHA_24BPP_MODE BIT(3)
80#define REG_LVDS_FMT_CHB_24BPP_MODE BIT(2)
81#define REG_LVDS_FMT_CHA_24BPP_FORMAT1 BIT(1)
82#define REG_LVDS_FMT_CHB_24BPP_FORMAT1 BIT(0)
83#define REG_LVDS_VCOM 0x19
84#define REG_LVDS_VCOM_CHA_LVDS_VOCM BIT(6)
85#define REG_LVDS_VCOM_CHB_LVDS_VOCM BIT(4)
86#define REG_LVDS_VCOM_CHA_LVDS_VOD_SWING(n) (((n) & 0x3) << 2)
87#define REG_LVDS_VCOM_CHB_LVDS_VOD_SWING(n) ((n) & 0x3)
88#define REG_LVDS_LANE 0x1a
89#define REG_LVDS_LANE_EVEN_ODD_SWAP BIT(6)
90#define REG_LVDS_LANE_CHA_REVERSE_LVDS BIT(5)
91#define REG_LVDS_LANE_CHB_REVERSE_LVDS BIT(4)
92#define REG_LVDS_LANE_CHA_LVDS_TERM BIT(1)
93#define REG_LVDS_LANE_CHB_LVDS_TERM BIT(0)
94#define REG_LVDS_CM 0x1b
95#define REG_LVDS_CM_CHA_LVDS_CM_ADJUST(n) (((n) & 0x3) << 4)
96#define REG_LVDS_CM_CHB_LVDS_CM_ADJUST(n) ((n) & 0x3)
97/* Video registers */
98#define REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW 0x20
99#define REG_VID_CHA_ACTIVE_LINE_LENGTH_HIGH 0x21
100#define REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW 0x24
101#define REG_VID_CHA_VERTICAL_DISPLAY_SIZE_HIGH 0x25
102#define REG_VID_CHA_SYNC_DELAY_LOW 0x28
103#define REG_VID_CHA_SYNC_DELAY_HIGH 0x29
104#define REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW 0x2c
105#define REG_VID_CHA_HSYNC_PULSE_WIDTH_HIGH 0x2d
106#define REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW 0x30
107#define REG_VID_CHA_VSYNC_PULSE_WIDTH_HIGH 0x31
108#define REG_VID_CHA_HORIZONTAL_BACK_PORCH 0x34
109#define REG_VID_CHA_VERTICAL_BACK_PORCH 0x36
110#define REG_VID_CHA_HORIZONTAL_FRONT_PORCH 0x38
111#define REG_VID_CHA_VERTICAL_FRONT_PORCH 0x3a
112#define REG_VID_CHA_TEST_PATTERN 0x3c
113/* IRQ registers */
114#define REG_IRQ_GLOBAL 0xe0
115#define REG_IRQ_GLOBAL_IRQ_EN BIT(0)
116#define REG_IRQ_EN 0xe1
117#define REG_IRQ_EN_CHA_SYNCH_ERR_EN BIT(7)
118#define REG_IRQ_EN_CHA_CRC_ERR_EN BIT(6)
119#define REG_IRQ_EN_CHA_UNC_ECC_ERR_EN BIT(5)
120#define REG_IRQ_EN_CHA_COR_ECC_ERR_EN BIT(4)
121#define REG_IRQ_EN_CHA_LLP_ERR_EN BIT(3)
122#define REG_IRQ_EN_CHA_SOT_BIT_ERR_EN BIT(2)
123#define REG_IRQ_EN_CHA_PLL_UNLOCK_EN BIT(0)
124#define REG_IRQ_STAT 0xe5
125#define REG_IRQ_STAT_CHA_SYNCH_ERR BIT(7)
126#define REG_IRQ_STAT_CHA_CRC_ERR BIT(6)
127#define REG_IRQ_STAT_CHA_UNC_ECC_ERR BIT(5)
128#define REG_IRQ_STAT_CHA_COR_ECC_ERR BIT(4)
129#define REG_IRQ_STAT_CHA_LLP_ERR BIT(3)
130#define REG_IRQ_STAT_CHA_SOT_BIT_ERR BIT(2)
131#define REG_IRQ_STAT_CHA_PLL_UNLOCK BIT(0)
132
133enum sn65dsi83_model {
134 MODEL_SN65DSI83,
135 MODEL_SN65DSI84,
136};
137
138struct sn65dsi83 {
139 struct drm_bridge bridge;
ceb515ba
MV		 140 struct device *dev;
141 struct regmap *regmap;
142 struct device_node *host_node;
143 struct mipi_dsi_device *dsi;
144 struct drm_bridge *panel_bridge;
145 struct gpio_desc *enable_gpio;
146 int dsi_lanes;
147 bool lvds_dual_link;
148 bool lvds_dual_link_even_odd_swap;
ceb515ba
MV		 149};
150
151static const struct regmap_range sn65dsi83_readable_ranges[] = {
152 regmap_reg_range(REG_ID(0), REG_ID(8)),
153 regmap_reg_range(REG_RC_LVDS_PLL, REG_RC_DSI_CLK),
154 regmap_reg_range(REG_RC_PLL_EN, REG_RC_PLL_EN),
155 regmap_reg_range(REG_DSI_LANE, REG_DSI_CLK),
156 regmap_reg_range(REG_LVDS_FMT, REG_LVDS_CM),
157 regmap_reg_range(REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW,
158 REG_VID_CHA_ACTIVE_LINE_LENGTH_HIGH),
159 regmap_reg_range(REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW,
160 REG_VID_CHA_VERTICAL_DISPLAY_SIZE_HIGH),
161 regmap_reg_range(REG_VID_CHA_SYNC_DELAY_LOW,
162 REG_VID_CHA_SYNC_DELAY_HIGH),
163 regmap_reg_range(REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW,
164 REG_VID_CHA_HSYNC_PULSE_WIDTH_HIGH),
165 regmap_reg_range(REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW,
166 REG_VID_CHA_VSYNC_PULSE_WIDTH_HIGH),
167 regmap_reg_range(REG_VID_CHA_HORIZONTAL_BACK_PORCH,
168 REG_VID_CHA_HORIZONTAL_BACK_PORCH),
169 regmap_reg_range(REG_VID_CHA_VERTICAL_BACK_PORCH,
170 REG_VID_CHA_VERTICAL_BACK_PORCH),
171 regmap_reg_range(REG_VID_CHA_HORIZONTAL_FRONT_PORCH,
172 REG_VID_CHA_HORIZONTAL_FRONT_PORCH),
173 regmap_reg_range(REG_VID_CHA_VERTICAL_FRONT_PORCH,
174 REG_VID_CHA_VERTICAL_FRONT_PORCH),
175 regmap_reg_range(REG_VID_CHA_TEST_PATTERN, REG_VID_CHA_TEST_PATTERN),
176 regmap_reg_range(REG_IRQ_GLOBAL, REG_IRQ_EN),
177 regmap_reg_range(REG_IRQ_STAT, REG_IRQ_STAT),
178};
179
180static const struct regmap_access_table sn65dsi83_readable_table = {
181 .yes_ranges = sn65dsi83_readable_ranges,
182 .n_yes_ranges = ARRAY_SIZE(sn65dsi83_readable_ranges),
183};
184
185static const struct regmap_range sn65dsi83_writeable_ranges[] = {
186 regmap_reg_range(REG_RC_RESET, REG_RC_DSI_CLK),
187 regmap_reg_range(REG_RC_PLL_EN, REG_RC_PLL_EN),
188 regmap_reg_range(REG_DSI_LANE, REG_DSI_CLK),
189 regmap_reg_range(REG_LVDS_FMT, REG_LVDS_CM),
190 regmap_reg_range(REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW,
191 REG_VID_CHA_ACTIVE_LINE_LENGTH_HIGH),
192 regmap_reg_range(REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW,
193 REG_VID_CHA_VERTICAL_DISPLAY_SIZE_HIGH),
194 regmap_reg_range(REG_VID_CHA_SYNC_DELAY_LOW,
195 REG_VID_CHA_SYNC_DELAY_HIGH),
196 regmap_reg_range(REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW,
197 REG_VID_CHA_HSYNC_PULSE_WIDTH_HIGH),
198 regmap_reg_range(REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW,
199 REG_VID_CHA_VSYNC_PULSE_WIDTH_HIGH),
200 regmap_reg_range(REG_VID_CHA_HORIZONTAL_BACK_PORCH,
201 REG_VID_CHA_HORIZONTAL_BACK_PORCH),
202 regmap_reg_range(REG_VID_CHA_VERTICAL_BACK_PORCH,
203 REG_VID_CHA_VERTICAL_BACK_PORCH),
204 regmap_reg_range(REG_VID_CHA_HORIZONTAL_FRONT_PORCH,
205 REG_VID_CHA_HORIZONTAL_FRONT_PORCH),
206 regmap_reg_range(REG_VID_CHA_VERTICAL_FRONT_PORCH,
207 REG_VID_CHA_VERTICAL_FRONT_PORCH),
208 regmap_reg_range(REG_VID_CHA_TEST_PATTERN, REG_VID_CHA_TEST_PATTERN),
209 regmap_reg_range(REG_IRQ_GLOBAL, REG_IRQ_EN),
210 regmap_reg_range(REG_IRQ_STAT, REG_IRQ_STAT),
211};
212
213static const struct regmap_access_table sn65dsi83_writeable_table = {
214 .yes_ranges = sn65dsi83_writeable_ranges,
215 .n_yes_ranges = ARRAY_SIZE(sn65dsi83_writeable_ranges),
216};
217
218static const struct regmap_range sn65dsi83_volatile_ranges[] = {
219 regmap_reg_range(REG_RC_RESET, REG_RC_RESET),
220 regmap_reg_range(REG_RC_LVDS_PLL, REG_RC_LVDS_PLL),
221 regmap_reg_range(REG_IRQ_STAT, REG_IRQ_STAT),
222};
223
224static const struct regmap_access_table sn65dsi83_volatile_table = {
225 .yes_ranges = sn65dsi83_volatile_ranges,
226 .n_yes_ranges = ARRAY_SIZE(sn65dsi83_volatile_ranges),
227};
228
229static const struct regmap_config sn65dsi83_regmap_config = {
230 .reg_bits = 8,
231 .val_bits = 8,
232 .rd_table = &sn65dsi83_readable_table,
233 .wr_table = &sn65dsi83_writeable_table,
234 .volatile_table = &sn65dsi83_volatile_table,
235 .cache_type = REGCACHE_RBTREE,
236 .max_register = REG_IRQ_STAT,
237};
238
239static struct sn65dsi83 *bridge_to_sn65dsi83(struct drm_bridge *bridge)
240{
241 return container_of(bridge, struct sn65dsi83, bridge);
242}
243
244static int sn65dsi83_attach(struct drm_bridge *bridge,
245 enum drm_bridge_attach_flags flags)
246{
247 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge);
248 struct device *dev = ctx->dev;
249 struct mipi_dsi_device *dsi;
250 struct mipi_dsi_host *host;
251 int ret = 0;
252
253 const struct mipi_dsi_device_info info = {
254 .type = "sn65dsi83",
255 .channel = 0,
256 .node = NULL,
257 };
258
259 host = of_find_mipi_dsi_host_by_node(ctx->host_node);
260 if (!host) {
261 dev_err(dev, "failed to find dsi host\n");
262 return -EPROBE_DEFER;
263 }
264
6cae235e 265 dsi = devm_mipi_dsi_device_register_full(dev, host, &info);
ceb515ba
MV		 266 if (IS_ERR(dsi)) {
267 return dev_err_probe(dev, PTR_ERR(dsi),
268 "failed to create dsi device\n");
269 }
270
271 ctx->dsi = dsi;
272
273 dsi->lanes = ctx->dsi_lanes;
274 dsi->format = MIPI_DSI_FMT_RGB888;
275 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST;
276
6cae235e 277 ret = devm_mipi_dsi_attach(dev, dsi);
ceb515ba
MV		 278 if (ret < 0) {
279 dev_err(dev, "failed to attach dsi to host\n");
6cae235e 280 return ret;
ceb515ba
MV		 281 }
282
283 return drm_bridge_attach(bridge->encoder, ctx->panel_bridge,
284 &ctx->bridge, flags);
ceb515ba
MV		 285}
286
24417d5b
MV		 287static void sn65dsi83_detach(struct drm_bridge *bridge)
288{
289 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge);
290
291 if (!ctx->dsi)
292 return;
293
24417d5b
MV		 294 ctx->dsi = NULL;
295}
296
7f0b7f5e
LP		 297static u8 sn65dsi83_get_lvds_range(struct sn65dsi83 *ctx,
298 const struct drm_display_mode *mode)
ceb515ba
MV		 299{
300 /*
301 * The encoding of the LVDS_CLK_RANGE is as follows:
302 * 000 - 25 MHz <= LVDS_CLK < 37.5 MHz
303 * 001 - 37.5 MHz <= LVDS_CLK < 62.5 MHz
304 * 010 - 62.5 MHz <= LVDS_CLK < 87.5 MHz
305 * 011 - 87.5 MHz <= LVDS_CLK < 112.5 MHz
306 * 100 - 112.5 MHz <= LVDS_CLK < 137.5 MHz
307 * 101 - 137.5 MHz <= LVDS_CLK <= 154 MHz
308 * which is a range of 12.5MHz..162.5MHz in 50MHz steps, except that
309 * the ends of the ranges are clamped to the supported range. Since
310 * sn65dsi83_mode_valid() already filters the valid modes and limits
311 * the clock to 25..154 MHz, the range calculation can be simplified
312 * as follows:
313 */
7f0b7f5e 314 int mode_clock = mode->clock;
ceb515ba
MV		 315
316 if (ctx->lvds_dual_link)
317 mode_clock /= 2;
318
319 return (mode_clock - 12500) / 25000;
320}
321
7f0b7f5e
LP		 322static u8 sn65dsi83_get_dsi_range(struct sn65dsi83 *ctx,
323 const struct drm_display_mode *mode)
ceb515ba
MV		 324{
325 /*
326 * The encoding of the CHA_DSI_CLK_RANGE is as follows:
327 * 0x00 through 0x07 - Reserved
328 * 0x08 - 40 <= DSI_CLK < 45 MHz
329 * 0x09 - 45 <= DSI_CLK < 50 MHz
330 * ...
331 * 0x63 - 495 <= DSI_CLK < 500 MHz
332 * 0x64 - 500 MHz
333 * 0x65 through 0xFF - Reserved
334 * which is DSI clock in 5 MHz steps, clamped to 40..500 MHz.
335 * The DSI clock are calculated as:
336 * DSI_CLK = mode clock * bpp / dsi_data_lanes / 2
337 * the 2 is there because the bus is DDR.
338 */
7f0b7f5e 339 return DIV_ROUND_UP(clamp((unsigned int)mode->clock *
ceb515ba
MV		 340 mipi_dsi_pixel_format_to_bpp(ctx->dsi->format) /
341 ctx->dsi_lanes / 2, 40000U, 500000U), 5000U);
342}
343
344static u8 sn65dsi83_get_dsi_div(struct sn65dsi83 *ctx)
345{
346 /* The divider is (DSI_CLK / LVDS_CLK) - 1, which really is: */
347 unsigned int dsi_div = mipi_dsi_pixel_format_to_bpp(ctx->dsi->format);
348
349 dsi_div /= ctx->dsi_lanes;
350
351 if (!ctx->lvds_dual_link)
352 dsi_div /= 2;
353
354 return dsi_div - 1;
355}
356
a6ea7d26
LP		 357static void sn65dsi83_atomic_enable(struct drm_bridge *bridge,
358 struct drm_bridge_state *old_bridge_state)
ceb515ba
MV		 359{
360 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge);
03ea01c0
LP		 361 struct drm_atomic_state *state = old_bridge_state->base.state;
362 const struct drm_bridge_state *bridge_state;
1451d0e9
LP		 363 const struct drm_crtc_state *crtc_state;
364 const struct drm_display_mode *mode;
365 struct drm_connector *connector;
366 struct drm_crtc *crtc;
03ea01c0
LP		 367 bool lvds_format_24bpp;
368 bool lvds_format_jeida;
ceb515ba 369 unsigned int pval;
241a9e23 370 __le16 le16val;
ceb515ba
MV		 371 u16 val;
372 int ret;
373
30a46873
MV		 374 /* Deassert reset */
375 gpiod_set_value(ctx->enable_gpio, 1);
376 usleep_range(1000, 1100);
377
03ea01c0
LP		 378 /* Get the LVDS format from the bridge state. */
379 bridge_state = drm_atomic_get_new_bridge_state(state, bridge);
380
381 switch (bridge_state->output_bus_cfg.format) {
382 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
383 lvds_format_24bpp = false;
384 lvds_format_jeida = true;
385 break;
386 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
387 lvds_format_24bpp = true;
388 lvds_format_jeida = true;
389 break;
390 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
391 lvds_format_24bpp = true;
392 lvds_format_jeida = false;
393 break;
394 default:
395 /*
396 * Some bridges still don't set the correct
397 * LVDS bus pixel format, use SPWG24 default
398 * format until those are fixed.
399 */
400 lvds_format_24bpp = true;
401 lvds_format_jeida = false;
402 dev_warn(ctx->dev,
403 "Unsupported LVDS bus format 0x%04x, please check output bridge driver. Falling back to SPWG24.\n",
404 bridge_state->output_bus_cfg.format);
405 break;
406 }
407
1451d0e9
LP		 408 /*
409 * Retrieve the CRTC adjusted mode. This requires a little dance to go
410 * from the bridge to the encoder, to the connector and to the CRTC.
411 */
412 connector = drm_atomic_get_new_connector_for_encoder(state,
413 bridge->encoder);
414 crtc = drm_atomic_get_new_connector_state(state, connector)->crtc;
415 crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
416 mode = &crtc_state->adjusted_mode;
417
ceb515ba
MV		 418 /* Clear reset, disable PLL */
419 regmap_write(ctx->regmap, REG_RC_RESET, 0x00);
420 regmap_write(ctx->regmap, REG_RC_PLL_EN, 0x00);
421
422 /* Reference clock derived from DSI link clock. */
423 regmap_write(ctx->regmap, REG_RC_LVDS_PLL,
1451d0e9 424 REG_RC_LVDS_PLL_LVDS_CLK_RANGE(sn65dsi83_get_lvds_range(ctx, mode)) |
96b7182d 425 REG_RC_LVDS_PLL_HS_CLK_SRC_DPHY);
ceb515ba 426 regmap_write(ctx->regmap, REG_DSI_CLK,
1451d0e9 427 REG_DSI_CLK_CHA_DSI_CLK_RANGE(sn65dsi83_get_dsi_range(ctx, mode)));
ceb515ba 428 regmap_write(ctx->regmap, REG_RC_DSI_CLK,
96b7182d 429 REG_RC_DSI_CLK_DSI_CLK_DIVIDER(sn65dsi83_get_dsi_div(ctx)));
ceb515ba
MV		 430
431 /* Set number of DSI lanes and LVDS link config. */
432 regmap_write(ctx->regmap, REG_DSI_LANE,
96b7182d
MV		 433 REG_DSI_LANE_DSI_CHANNEL_MODE_SINGLE |
434 REG_DSI_LANE_CHA_DSI_LANES(~(ctx->dsi_lanes - 1)) |
435 /* CHB is DSI85-only, set to default on DSI83/DSI84 */
436 REG_DSI_LANE_CHB_DSI_LANES(3));
ceb515ba
MV		 437 /* No equalization. */
438 regmap_write(ctx->regmap, REG_DSI_EQ, 0x00);
439
440 /* Set up sync signal polarity. */
1451d0e9 441 val = (mode->flags & DRM_MODE_FLAG_NHSYNC ?
ceb515ba 442 REG_LVDS_FMT_HS_NEG_POLARITY : 0) |
1451d0e9 443 (mode->flags & DRM_MODE_FLAG_NVSYNC ?
ceb515ba
MV		 444 REG_LVDS_FMT_VS_NEG_POLARITY : 0);
445
446 /* Set up bits-per-pixel, 18bpp or 24bpp. */
03ea01c0 447 if (lvds_format_24bpp) {
ceb515ba
MV		 448 val |= REG_LVDS_FMT_CHA_24BPP_MODE;
449 if (ctx->lvds_dual_link)
450 val |= REG_LVDS_FMT_CHB_24BPP_MODE;
451 }
452
453 /* Set up LVDS format, JEIDA/Format 1 or SPWG/Format 2 */
03ea01c0 454 if (lvds_format_jeida) {
ceb515ba
MV		 455 val |= REG_LVDS_FMT_CHA_24BPP_FORMAT1;
456 if (ctx->lvds_dual_link)
457 val |= REG_LVDS_FMT_CHB_24BPP_FORMAT1;
458 }
459
460 /* Set up LVDS output config (DSI84,DSI85) */
461 if (!ctx->lvds_dual_link)
462 val |= REG_LVDS_FMT_LVDS_LINK_CFG;
463
464 regmap_write(ctx->regmap, REG_LVDS_FMT, val);
465 regmap_write(ctx->regmap, REG_LVDS_VCOM, 0x05);
466 regmap_write(ctx->regmap, REG_LVDS_LANE,
96b7182d
MV		 467 (ctx->lvds_dual_link_even_odd_swap ?
468 REG_LVDS_LANE_EVEN_ODD_SWAP : 0) |
469 REG_LVDS_LANE_CHA_LVDS_TERM |
470 REG_LVDS_LANE_CHB_LVDS_TERM);
ceb515ba
MV		 471 regmap_write(ctx->regmap, REG_LVDS_CM, 0x00);
472
1451d0e9 473 le16val = cpu_to_le16(mode->hdisplay);
ceb515ba 474 regmap_bulk_write(ctx->regmap, REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW,
241a9e23 475 &le16val, 2);
1451d0e9 476 le16val = cpu_to_le16(mode->vdisplay);
ceb515ba 477 regmap_bulk_write(ctx->regmap, REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW,
241a9e23 478 &le16val, 2);
ceb515ba 479 /* 32 + 1 pixel clock to ensure proper operation */
241a9e23
MV		 480 le16val = cpu_to_le16(32 + 1);
481 regmap_bulk_write(ctx->regmap, REG_VID_CHA_SYNC_DELAY_LOW, &le16val, 2);
1451d0e9 482 le16val = cpu_to_le16(mode->hsync_end - mode->hsync_start);
ceb515ba 483 regmap_bulk_write(ctx->regmap, REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW,
241a9e23 484 &le16val, 2);
1451d0e9 485 le16val = cpu_to_le16(mode->vsync_end - mode->vsync_start);
ceb515ba 486 regmap_bulk_write(ctx->regmap, REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW,
241a9e23 487 &le16val, 2);
ceb515ba 488 regmap_write(ctx->regmap, REG_VID_CHA_HORIZONTAL_BACK_PORCH,
1451d0e9 489 mode->htotal - mode->hsync_end);
ceb515ba 490 regmap_write(ctx->regmap, REG_VID_CHA_VERTICAL_BACK_PORCH,
1451d0e9 491 mode->vtotal - mode->vsync_end);
ceb515ba 492 regmap_write(ctx->regmap, REG_VID_CHA_HORIZONTAL_FRONT_PORCH,
1451d0e9 493 mode->hsync_start - mode->hdisplay);
ceb515ba 494 regmap_write(ctx->regmap, REG_VID_CHA_VERTICAL_FRONT_PORCH,
1451d0e9 495 mode->vsync_start - mode->vdisplay);
ceb515ba
MV		 496 regmap_write(ctx->regmap, REG_VID_CHA_TEST_PATTERN, 0x00);
497
498 /* Enable PLL */
499 regmap_write(ctx->regmap, REG_RC_PLL_EN, REG_RC_PLL_EN_PLL_EN);
500 usleep_range(3000, 4000);
501 ret = regmap_read_poll_timeout(ctx->regmap, REG_RC_LVDS_PLL, pval,
96b7182d
MV		 502 pval & REG_RC_LVDS_PLL_PLL_EN_STAT,
503 1000, 100000);
ceb515ba
MV		 504 if (ret) {
505 dev_err(ctx->dev, "failed to lock PLL, ret=%i\n", ret);
506 /* On failure, disable PLL again and exit. */
507 regmap_write(ctx->regmap, REG_RC_PLL_EN, 0x00);
508 return;
509 }
510
511 /* Trigger reset after CSR register update. */
512 regmap_write(ctx->regmap, REG_RC_RESET, REG_RC_RESET_SOFT_RESET);
513
514 /* Clear all errors that got asserted during initialization. */
515 regmap_read(ctx->regmap, REG_IRQ_STAT, &pval);
516 regmap_write(ctx->regmap, REG_IRQ_STAT, pval);
517}
518
a6ea7d26
LP		 519static void sn65dsi83_atomic_disable(struct drm_bridge *bridge,
520 struct drm_bridge_state *old_bridge_state)
ceb515ba
MV		 521{
522 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge);
523
30a46873 524 /* Put the chip in reset, pull EN line low, and assure 10ms reset low timing. */
ceb515ba 525 gpiod_set_value(ctx->enable_gpio, 0);
30a46873
MV		 526 usleep_range(10000, 11000);
527
528 regcache_mark_dirty(ctx->regmap);
ceb515ba
MV		 529}
530
531static enum drm_mode_status
532sn65dsi83_mode_valid(struct drm_bridge *bridge,
533 const struct drm_display_info *info,
534 const struct drm_display_mode *mode)
535{
536 /* LVDS output clock range 25..154 MHz */
537 if (mode->clock < 25000)
538 return MODE_CLOCK_LOW;
539 if (mode->clock > 154000)
540 return MODE_CLOCK_HIGH;
541
542 return MODE_OK;
543}
544
db8b7ca5
MV		 545#define MAX_INPUT_SEL_FORMATS 1
546
547static u32 *
548sn65dsi83_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
549 struct drm_bridge_state *bridge_state,
550 struct drm_crtc_state *crtc_state,
551 struct drm_connector_state *conn_state,
552 u32 output_fmt,
553 unsigned int *num_input_fmts)
554{
555 u32 *input_fmts;
556
557 *num_input_fmts = 0;
558
559 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
560 GFP_KERNEL);
561 if (!input_fmts)
562 return NULL;
563
564 /* This is the DSI-end bus format */
565 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
566 *num_input_fmts = 1;
567
568 return input_fmts;
569}
570
ceb515ba 571static const struct drm_bridge_funcs sn65dsi83_funcs = {
a6ea7d26 572 .attach = sn65dsi83_attach,
24417d5b 573 .detach = sn65dsi83_detach,
a6ea7d26
LP		 574 .atomic_enable = sn65dsi83_atomic_enable,
575 .atomic_disable = sn65dsi83_atomic_disable,
a6ea7d26 576 .mode_valid = sn65dsi83_mode_valid,
db8b7ca5
MV		 577
578 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
579 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
580 .atomic_reset = drm_atomic_helper_bridge_reset,
581 .atomic_get_input_bus_fmts = sn65dsi83_atomic_get_input_bus_fmts,
ceb515ba
MV		 582};
583
584static int sn65dsi83_parse_dt(struct sn65dsi83 *ctx, enum sn65dsi83_model model)
585{
586 struct drm_bridge *panel_bridge;
587 struct device *dev = ctx->dev;
588 struct device_node *endpoint;
589 struct drm_panel *panel;
590 int ret;
591
592 endpoint = of_graph_get_endpoint_by_regs(dev->of_node, 0, 0);
593 ctx->dsi_lanes = of_property_count_u32_elems(endpoint, "data-lanes");
594 ctx->host_node = of_graph_get_remote_port_parent(endpoint);
595 of_node_put(endpoint);
596
597 if (ctx->dsi_lanes < 0 || ctx->dsi_lanes > 4)
598 return -EINVAL;
599 if (!ctx->host_node)
600 return -ENODEV;
601
602 ctx->lvds_dual_link = false;
603 ctx->lvds_dual_link_even_odd_swap = false;
604 if (model != MODEL_SN65DSI83) {
605 struct device_node *port2, *port3;
606 int dual_link;
607
608 port2 = of_graph_get_port_by_id(dev->of_node, 2);
609 port3 = of_graph_get_port_by_id(dev->of_node, 3);
610 dual_link = drm_of_lvds_get_dual_link_pixel_order(port2, port3);
611 of_node_put(port2);
612 of_node_put(port3);
613
614 if (dual_link == DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS) {
615 ctx->lvds_dual_link = true;
616 /* Odd pixels to LVDS Channel A, even pixels to B */
617 ctx->lvds_dual_link_even_odd_swap = false;
618 } else if (dual_link == DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS) {
619 ctx->lvds_dual_link = true;
620 /* Even pixels to LVDS Channel A, odd pixels to B */
621 ctx->lvds_dual_link_even_odd_swap = true;
622 }
623 }
624
625 ret = drm_of_find_panel_or_bridge(dev->of_node, 2, 0, &panel, &panel_bridge);
626 if (ret < 0)
627 return ret;
628 if (panel) {
629 panel_bridge = devm_drm_panel_bridge_add(dev, panel);
630 if (IS_ERR(panel_bridge))
631 return PTR_ERR(panel_bridge);
632 }
633
634 ctx->panel_bridge = panel_bridge;
635
636 return 0;
637}
638
639static int sn65dsi83_probe(struct i2c_client *client,
640 const struct i2c_device_id *id)
641{
642 struct device *dev = &client->dev;
643 enum sn65dsi83_model model;
644 struct sn65dsi83 *ctx;
645 int ret;
646
647 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
648 if (!ctx)
649 return -ENOMEM;
650
651 ctx->dev = dev;
652
653 if (dev->of_node) {
654 model = (enum sn65dsi83_model)(uintptr_t)
655 of_device_get_match_data(dev);
656 } else {
657 model = id->driver_data;
658 }
659
30a46873 660 /* Put the chip in reset, pull EN line low, and assure 10ms reset low timing. */
ceb515ba
MV		 661 ctx->enable_gpio = devm_gpiod_get(ctx->dev, "enable", GPIOD_OUT_LOW);
662 if (IS_ERR(ctx->enable_gpio))
663 return PTR_ERR(ctx->enable_gpio);
664
30a46873
MV		 665 usleep_range(10000, 11000);
666
ceb515ba
MV		 667 ret = sn65dsi83_parse_dt(ctx, model);
668 if (ret)
669 return ret;
670
671 ctx->regmap = devm_regmap_init_i2c(client, &sn65dsi83_regmap_config);
672 if (IS_ERR(ctx->regmap))
673 return PTR_ERR(ctx->regmap);
674
675 dev_set_drvdata(dev, ctx);
676 i2c_set_clientdata(client, ctx);
677
678 ctx->bridge.funcs = &sn65dsi83_funcs;
679 ctx->bridge.of_node = dev->of_node;
680 drm_bridge_add(&ctx->bridge);
681
682 return 0;
683}
684
685static int sn65dsi83_remove(struct i2c_client *client)
686{
687 struct sn65dsi83 *ctx = i2c_get_clientdata(client);
688
c05f1a4e 689 drm_bridge_remove(&ctx->bridge);
ceb515ba
MV		 690 of_node_put(ctx->host_node);
691
692 return 0;
693}
694
695static struct i2c_device_id sn65dsi83_id[] = {
696 { "ti,sn65dsi83", MODEL_SN65DSI83 },
697 { "ti,sn65dsi84", MODEL_SN65DSI84 },
698 {},
699};
700MODULE_DEVICE_TABLE(i2c, sn65dsi83_id);
701
702static const struct of_device_id sn65dsi83_match_table[] = {
703 { .compatible = "ti,sn65dsi83", .data = (void *)MODEL_SN65DSI83 },
704 { .compatible = "ti,sn65dsi84", .data = (void *)MODEL_SN65DSI84 },
705 {},
706};
707MODULE_DEVICE_TABLE(of, sn65dsi83_match_table);
708
709static struct i2c_driver sn65dsi83_driver = {
710 .probe = sn65dsi83_probe,
711 .remove = sn65dsi83_remove,
712 .id_table = sn65dsi83_id,
713 .driver = {
714 .name = "sn65dsi83",
715 .of_match_table = sn65dsi83_match_table,
716 },
717};
718module_i2c_driver(sn65dsi83_driver);
719
720MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
721MODULE_DESCRIPTION("TI SN65DSI83 DSI to LVDS bridge driver");
722MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)