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drm: Clarify definition of the DRM_BUS_FLAG_(PIXDATA|SYNC)_* macros
[linux-block.git] / drivers / gpu / drm / bridge / tc358767.c
CommitLineData
7caff0fc
AG		 1/*
2 * tc358767 eDP bridge driver
3 *
4 * Copyright (C) 2016 CogentEmbedded Inc
5 * Author: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
6 *
7 * Copyright (C) 2016 Pengutronix, Philipp Zabel <p.zabel@pengutronix.de>
8 *
2f51be09
AG		 9 * Copyright (C) 2016 Zodiac Inflight Innovations
10 *
7caff0fc
AG		 11 * Initially based on: drivers/gpu/drm/i2c/tda998x_drv.c
12 *
13 * Copyright (C) 2012 Texas Instruments
14 * Author: Rob Clark <robdclark@gmail.com>
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 */
26
27#include <linux/clk.h>
28#include <linux/device.h>
29#include <linux/gpio/consumer.h>
30#include <linux/i2c.h>
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/regmap.h>
34#include <linux/slab.h>
35
36#include <drm/drm_atomic_helper.h>
7caff0fc
AG		 37#include <drm/drm_dp_helper.h>
38#include <drm/drm_edid.h>
39#include <drm/drm_of.h>
40#include <drm/drm_panel.h>
fcd70cd3 41#include <drm/drm_probe_helper.h>
7caff0fc
AG		 42
43/* Registers */
44
45/* Display Parallel Interface */
46#define DPIPXLFMT 0x0440
47#define VS_POL_ACTIVE_LOW (1 << 10)
48#define HS_POL_ACTIVE_LOW (1 << 9)
49#define DE_POL_ACTIVE_HIGH (0 << 8)
50#define SUB_CFG_TYPE_CONFIG1 (0 << 2) /* LSB aligned */
51#define SUB_CFG_TYPE_CONFIG2 (1 << 2) /* Loosely Packed */
52#define SUB_CFG_TYPE_CONFIG3 (2 << 2) /* LSB aligned 8-bit */
53#define DPI_BPP_RGB888 (0 << 0)
54#define DPI_BPP_RGB666 (1 << 0)
55#define DPI_BPP_RGB565 (2 << 0)
56
57/* Video Path */
58#define VPCTRL0 0x0450
59#define OPXLFMT_RGB666 (0 << 8)
60#define OPXLFMT_RGB888 (1 << 8)
61#define FRMSYNC_DISABLED (0 << 4) /* Video Timing Gen Disabled */
62#define FRMSYNC_ENABLED (1 << 4) /* Video Timing Gen Enabled */
63#define MSF_DISABLED (0 << 0) /* Magic Square FRC disabled */
64#define MSF_ENABLED (1 << 0) /* Magic Square FRC enabled */
65#define HTIM01 0x0454
66#define HTIM02 0x0458
67#define VTIM01 0x045c
68#define VTIM02 0x0460
69#define VFUEN0 0x0464
70#define VFUEN BIT(0) /* Video Frame Timing Upload */
71
72/* System */
73#define TC_IDREG 0x0500
74#define SYSCTRL 0x0510
75#define DP0_AUDSRC_NO_INPUT (0 << 3)
76#define DP0_AUDSRC_I2S_RX (1 << 3)
77#define DP0_VIDSRC_NO_INPUT (0 << 0)
78#define DP0_VIDSRC_DSI_RX (1 << 0)
79#define DP0_VIDSRC_DPI_RX (2 << 0)
80#define DP0_VIDSRC_COLOR_BAR (3 << 0)
81
82/* Control */
83#define DP0CTL 0x0600
84#define VID_MN_GEN BIT(6) /* Auto-generate M/N values */
85#define EF_EN BIT(5) /* Enable Enhanced Framing */
86#define VID_EN BIT(1) /* Video transmission enable */
87#define DP_EN BIT(0) /* Enable DPTX function */
88
89/* Clocks */
90#define DP0_VIDMNGEN0 0x0610
91#define DP0_VIDMNGEN1 0x0614
92#define DP0_VMNGENSTATUS 0x0618
93
94/* Main Channel */
95#define DP0_SECSAMPLE 0x0640
96#define DP0_VIDSYNCDELAY 0x0644
97#define DP0_TOTALVAL 0x0648
98#define DP0_STARTVAL 0x064c
99#define DP0_ACTIVEVAL 0x0650
100#define DP0_SYNCVAL 0x0654
7923e09c
TV		 101#define SYNCVAL_HS_POL_ACTIVE_LOW (1 << 15)
102#define SYNCVAL_VS_POL_ACTIVE_LOW (1 << 31)
7caff0fc 103#define DP0_MISC 0x0658
f3b8adbe 104#define TU_SIZE_RECOMMENDED (63) /* LSCLK cycles per TU */
7caff0fc
AG		 105#define BPC_6 (0 << 5)
106#define BPC_8 (1 << 5)
107
108/* AUX channel */
109#define DP0_AUXCFG0 0x0660
110#define DP0_AUXCFG1 0x0664
111#define AUX_RX_FILTER_EN BIT(16)
112
113#define DP0_AUXADDR 0x0668
114#define DP0_AUXWDATA(i) (0x066c + (i) * 4)
115#define DP0_AUXRDATA(i) (0x067c + (i) * 4)
116#define DP0_AUXSTATUS 0x068c
117#define AUX_STATUS_MASK 0xf0
118#define AUX_STATUS_SHIFT 4
119#define AUX_TIMEOUT BIT(1)
120#define AUX_BUSY BIT(0)
121#define DP0_AUXI2CADR 0x0698
122
123/* Link Training */
124#define DP0_SRCCTRL 0x06a0
125#define DP0_SRCCTRL_SCRMBLDIS BIT(13)
126#define DP0_SRCCTRL_EN810B BIT(12)
127#define DP0_SRCCTRL_NOTP (0 << 8)
128#define DP0_SRCCTRL_TP1 (1 << 8)
129#define DP0_SRCCTRL_TP2 (2 << 8)
130#define DP0_SRCCTRL_LANESKEW BIT(7)
131#define DP0_SRCCTRL_SSCG BIT(3)
132#define DP0_SRCCTRL_LANES_1 (0 << 2)
133#define DP0_SRCCTRL_LANES_2 (1 << 2)
134#define DP0_SRCCTRL_BW27 (1 << 1)
135#define DP0_SRCCTRL_BW162 (0 << 1)
136#define DP0_SRCCTRL_AUTOCORRECT BIT(0)
137#define DP0_LTSTAT 0x06d0
138#define LT_LOOPDONE BIT(13)
139#define LT_STATUS_MASK (0x1f << 8)
140#define LT_CHANNEL1_EQ_BITS (DP_CHANNEL_EQ_BITS << 4)
141#define LT_INTERLANE_ALIGN_DONE BIT(3)
142#define LT_CHANNEL0_EQ_BITS (DP_CHANNEL_EQ_BITS)
143#define DP0_SNKLTCHGREQ 0x06d4
144#define DP0_LTLOOPCTRL 0x06d8
145#define DP0_SNKLTCTRL 0x06e4
146
adf41098
TV		 147#define DP1_SRCCTRL 0x07a0
148
7caff0fc
AG		 149/* PHY */
150#define DP_PHY_CTRL 0x0800
151#define DP_PHY_RST BIT(28) /* DP PHY Global Soft Reset */
152#define BGREN BIT(25) /* AUX PHY BGR Enable */
153#define PWR_SW_EN BIT(24) /* PHY Power Switch Enable */
154#define PHY_M1_RST BIT(12) /* Reset PHY1 Main Channel */
155#define PHY_RDY BIT(16) /* PHY Main Channels Ready */
156#define PHY_M0_RST BIT(8) /* Reset PHY0 Main Channel */
adf41098 157#define PHY_2LANE BIT(2) /* PHY Enable 2 lanes */
7caff0fc
AG		 158#define PHY_A0_EN BIT(1) /* PHY Aux Channel0 Enable */
159#define PHY_M0_EN BIT(0) /* PHY Main Channel0 Enable */
160
161/* PLL */
162#define DP0_PLLCTRL 0x0900
163#define DP1_PLLCTRL 0x0904 /* not defined in DS */
164#define PXL_PLLCTRL 0x0908
165#define PLLUPDATE BIT(2)
166#define PLLBYP BIT(1)
167#define PLLEN BIT(0)
168#define PXL_PLLPARAM 0x0914
169#define IN_SEL_REFCLK (0 << 14)
170#define SYS_PLLPARAM 0x0918
171#define REF_FREQ_38M4 (0 << 8) /* 38.4 MHz */
172#define REF_FREQ_19M2 (1 << 8) /* 19.2 MHz */
173#define REF_FREQ_26M (2 << 8) /* 26 MHz */
174#define REF_FREQ_13M (3 << 8) /* 13 MHz */
175#define SYSCLK_SEL_LSCLK (0 << 4)
176#define LSCLK_DIV_1 (0 << 0)
177#define LSCLK_DIV_2 (1 << 0)
178
179/* Test & Debug */
180#define TSTCTL 0x0a00
181#define PLL_DBG 0x0a04
182
183static bool tc_test_pattern;
184module_param_named(test, tc_test_pattern, bool, 0644);
185
186struct tc_edp_link {
187 struct drm_dp_link base;
188 u8 assr;
189 int scrambler_dis;
190 int spread;
191 int coding8b10b;
192 u8 swing;
193 u8 preemp;
194};
195
196struct tc_data {
197 struct device *dev;
198 struct regmap *regmap;
199 struct drm_dp_aux aux;
200
201 struct drm_bridge bridge;
202 struct drm_connector connector;
203 struct drm_panel *panel;
204
205 /* link settings */
206 struct tc_edp_link link;
207
208 /* display edid */
209 struct edid *edid;
210 /* current mode */
63f8f3ba 211 const struct drm_display_mode *mode;
7caff0fc
AG		 212
213 u32 rev;
214 u8 assr;
215
216 struct gpio_desc *sd_gpio;
217 struct gpio_desc *reset_gpio;
218 struct clk *refclk;
219};
220
221static inline struct tc_data *aux_to_tc(struct drm_dp_aux *a)
222{
223 return container_of(a, struct tc_data, aux);
224}
225
226static inline struct tc_data *bridge_to_tc(struct drm_bridge *b)
227{
228 return container_of(b, struct tc_data, bridge);
229}
230
231static inline struct tc_data *connector_to_tc(struct drm_connector *c)
232{
233 return container_of(c, struct tc_data, connector);
234}
235
236/* Simple macros to avoid repeated error checks */
237#define tc_write(reg, var) \
238 do { \
239 ret = regmap_write(tc->regmap, reg, var); \
240 if (ret) \
241 goto err; \
242 } while (0)
243#define tc_read(reg, var) \
244 do { \
245 ret = regmap_read(tc->regmap, reg, var); \
246 if (ret) \
247 goto err; \
248 } while (0)
249
250static inline int tc_poll_timeout(struct regmap *map, unsigned int addr,
251 unsigned int cond_mask,
252 unsigned int cond_value,
253 unsigned long sleep_us, u64 timeout_us)
254{
255 ktime_t timeout = ktime_add_us(ktime_get(), timeout_us);
256 unsigned int val;
257 int ret;
258
259 for (;;) {
260 ret = regmap_read(map, addr, &val);
261 if (ret)
262 break;
263 if ((val & cond_mask) == cond_value)
264 break;
265 if (timeout_us && ktime_compare(ktime_get(), timeout) > 0) {
266 ret = regmap_read(map, addr, &val);
267 break;
268 }
269 if (sleep_us)
270 usleep_range((sleep_us >> 2) + 1, sleep_us);
271 }
272 return ret ?: (((val & cond_mask) == cond_value) ? 0 : -ETIMEDOUT);
273}
274
275static int tc_aux_wait_busy(struct tc_data *tc, unsigned int timeout_ms)
276{
277 return tc_poll_timeout(tc->regmap, DP0_AUXSTATUS, AUX_BUSY, 0,
278 1000, 1000 * timeout_ms);
279}
280
281static int tc_aux_get_status(struct tc_data *tc, u8 *reply)
282{
283 int ret;
284 u32 value;
285
286 ret = regmap_read(tc->regmap, DP0_AUXSTATUS, &value);
287 if (ret < 0)
288 return ret;
289 if (value & AUX_BUSY) {
290 if (value & AUX_TIMEOUT) {
291 dev_err(tc->dev, "i2c access timeout!\n");
292 return -ETIMEDOUT;
293 }
294 return -EBUSY;
295 }
296
297 *reply = (value & AUX_STATUS_MASK) >> AUX_STATUS_SHIFT;
298 return 0;
299}
300
301static ssize_t tc_aux_transfer(struct drm_dp_aux *aux,
302 struct drm_dp_aux_msg *msg)
303{
304 struct tc_data *tc = aux_to_tc(aux);
305 size_t size = min_t(size_t, 8, msg->size);
306 u8 request = msg->request & ~DP_AUX_I2C_MOT;
307 u8 *buf = msg->buffer;
308 u32 tmp = 0;
309 int i = 0;
310 int ret;
311
312 if (size == 0)
313 return 0;
314
315 ret = tc_aux_wait_busy(tc, 100);
316 if (ret)
317 goto err;
318
319 if (request == DP_AUX_I2C_WRITE || request == DP_AUX_NATIVE_WRITE) {
320 /* Store data */
321 while (i < size) {
322 if (request == DP_AUX_NATIVE_WRITE)
323 tmp = tmp | (buf[i] << (8 * (i & 0x3)));
324 else
325 tmp = (tmp << 8) | buf[i];
326 i++;
327 if (((i % 4) == 0) || (i == size)) {
9217c1ab 328 tc_write(DP0_AUXWDATA((i - 1) >> 2), tmp);
7caff0fc
AG		 329 tmp = 0;
330 }
331 }
332 } else if (request != DP_AUX_I2C_READ &&
333 request != DP_AUX_NATIVE_READ) {
334 return -EINVAL;
335 }
336
337 /* Store address */
338 tc_write(DP0_AUXADDR, msg->address);
339 /* Start transfer */
340 tc_write(DP0_AUXCFG0, ((size - 1) << 8) | request);
341
342 ret = tc_aux_wait_busy(tc, 100);
343 if (ret)
344 goto err;
345
346 ret = tc_aux_get_status(tc, &msg->reply);
347 if (ret)
348 goto err;
349
350 if (request == DP_AUX_I2C_READ || request == DP_AUX_NATIVE_READ) {
351 /* Read data */
352 while (i < size) {
353 if ((i % 4) == 0)
354 tc_read(DP0_AUXRDATA(i >> 2), &tmp);
355 buf[i] = tmp & 0xff;
356 tmp = tmp >> 8;
357 i++;
358 }
359 }
360
361 return size;
362err:
363 return ret;
364}
365
366static const char * const training_pattern1_errors[] = {
367 "No errors",
368 "Aux write error",
369 "Aux read error",
370 "Max voltage reached error",
371 "Loop counter expired error",
372 "res", "res", "res"
373};
374
375static const char * const training_pattern2_errors[] = {
376 "No errors",
377 "Aux write error",
378 "Aux read error",
379 "Clock recovery failed error",
380 "Loop counter expired error",
381 "res", "res", "res"
382};
383
384static u32 tc_srcctrl(struct tc_data *tc)
385{
386 /*
387 * No training pattern, skew lane 1 data by two LSCLK cycles with
388 * respect to lane 0 data, AutoCorrect Mode = 0
389 */
390 u32 reg = DP0_SRCCTRL_NOTP | DP0_SRCCTRL_LANESKEW;
391
392 if (tc->link.scrambler_dis)
393 reg |= DP0_SRCCTRL_SCRMBLDIS; /* Scrambler Disabled */
394 if (tc->link.coding8b10b)
395 /* Enable 8/10B Encoder (TxData[19:16] not used) */
396 reg |= DP0_SRCCTRL_EN810B;
397 if (tc->link.spread)
398 reg |= DP0_SRCCTRL_SSCG; /* Spread Spectrum Enable */
399 if (tc->link.base.num_lanes == 2)
400 reg |= DP0_SRCCTRL_LANES_2; /* Two Main Channel Lanes */
401 if (tc->link.base.rate != 162000)
402 reg |= DP0_SRCCTRL_BW27; /* 2.7 Gbps link */
403 return reg;
404}
405
406static void tc_wait_pll_lock(struct tc_data *tc)
407{
408 /* Wait for PLL to lock: up to 2.09 ms, depending on refclk */
409 usleep_range(3000, 6000);
410}
411
412static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock)
413{
414 int ret;
415 int i_pre, best_pre = 1;
416 int i_post, best_post = 1;
417 int div, best_div = 1;
418 int mul, best_mul = 1;
419 int delta, best_delta;
420 int ext_div[] = {1, 2, 3, 5, 7};
421 int best_pixelclock = 0;
422 int vco_hi = 0;
423
424 dev_dbg(tc->dev, "PLL: requested %d pixelclock, ref %d\n", pixelclock,
425 refclk);
426 best_delta = pixelclock;
427 /* Loop over all possible ext_divs, skipping invalid configurations */
428 for (i_pre = 0; i_pre < ARRAY_SIZE(ext_div); i_pre++) {
429 /*
430 * refclk / ext_pre_div should be in the 1 to 200 MHz range.
431 * We don't allow any refclk > 200 MHz, only check lower bounds.
432 */
433 if (refclk / ext_div[i_pre] < 1000000)
434 continue;
435 for (i_post = 0; i_post < ARRAY_SIZE(ext_div); i_post++) {
436 for (div = 1; div <= 16; div++) {
437 u32 clk;
438 u64 tmp;
439
440 tmp = pixelclock * ext_div[i_pre] *
441 ext_div[i_post] * div;
442 do_div(tmp, refclk);
443 mul = tmp;
444
445 /* Check limits */
446 if ((mul < 1) || (mul > 128))
447 continue;
448
449 clk = (refclk / ext_div[i_pre] / div) * mul;
450 /*
451 * refclk * mul / (ext_pre_div * pre_div)
452 * should be in the 150 to 650 MHz range
453 */
454 if ((clk > 650000000) || (clk < 150000000))
455 continue;
456
457 clk = clk / ext_div[i_post];
458 delta = clk - pixelclock;
459
460 if (abs(delta) < abs(best_delta)) {
461 best_pre = i_pre;
462 best_post = i_post;
463 best_div = div;
464 best_mul = mul;
465 best_delta = delta;
466 best_pixelclock = clk;
467 }
468 }
469 }
470 }
471 if (best_pixelclock == 0) {
472 dev_err(tc->dev, "Failed to calc clock for %d pixelclock\n",
473 pixelclock);
474 return -EINVAL;
475 }
476
477 dev_dbg(tc->dev, "PLL: got %d, delta %d\n", best_pixelclock,
478 best_delta);
479 dev_dbg(tc->dev, "PLL: %d / %d / %d * %d / %d\n", refclk,
480 ext_div[best_pre], best_div, best_mul, ext_div[best_post]);
481
482 /* if VCO >= 300 MHz */
483 if (refclk / ext_div[best_pre] / best_div * best_mul >= 300000000)
484 vco_hi = 1;
485 /* see DS */
486 if (best_div == 16)
487 best_div = 0;
488 if (best_mul == 128)
489 best_mul = 0;
490
491 /* Power up PLL and switch to bypass */
492 tc_write(PXL_PLLCTRL, PLLBYP | PLLEN);
493
494 tc_write(PXL_PLLPARAM,
495 (vco_hi << 24) | /* For PLL VCO >= 300 MHz = 1 */
496 (ext_div[best_pre] << 20) | /* External Pre-divider */
497 (ext_div[best_post] << 16) | /* External Post-divider */
498 IN_SEL_REFCLK | /* Use RefClk as PLL input */
499 (best_div << 8) | /* Divider for PLL RefClk */
500 (best_mul << 0)); /* Multiplier for PLL */
501
502 /* Force PLL parameter update and disable bypass */
503 tc_write(PXL_PLLCTRL, PLLUPDATE | PLLEN);
504
505 tc_wait_pll_lock(tc);
506
507 return 0;
508err:
509 return ret;
510}
511
512static int tc_pxl_pll_dis(struct tc_data *tc)
513{
514 /* Enable PLL bypass, power down PLL */
515 return regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP);
516}
517
518static int tc_stream_clock_calc(struct tc_data *tc)
519{
520 int ret;
521 /*
522 * If the Stream clock and Link Symbol clock are
523 * asynchronous with each other, the value of M changes over
524 * time. This way of generating link clock and stream
525 * clock is called Asynchronous Clock mode. The value M
526 * must change while the value N stays constant. The
527 * value of N in this Asynchronous Clock mode must be set
528 * to 2^15 or 32,768.
529 *
530 * LSCLK = 1/10 of high speed link clock
531 *
532 * f_STRMCLK = M/N * f_LSCLK
533 * M/N = f_STRMCLK / f_LSCLK
534 *
535 */
536 tc_write(DP0_VIDMNGEN1, 32768);
537
538 return 0;
539err:
540 return ret;
541}
542
543static int tc_aux_link_setup(struct tc_data *tc)
544{
545 unsigned long rate;
546 u32 value;
547 int ret;
4d9d54a7 548 u32 dp_phy_ctrl;
7caff0fc
AG		 549
550 rate = clk_get_rate(tc->refclk);
551 switch (rate) {
552 case 38400000:
553 value = REF_FREQ_38M4;
554 break;
555 case 26000000:
556 value = REF_FREQ_26M;
557 break;
558 case 19200000:
559 value = REF_FREQ_19M2;
560 break;
561 case 13000000:
562 value = REF_FREQ_13M;
563 break;
564 default:
565 dev_err(tc->dev, "Invalid refclk rate: %lu Hz\n", rate);
566 return -EINVAL;
567 }
568
569 /* Setup DP-PHY / PLL */
570 value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2;
571 tc_write(SYS_PLLPARAM, value);
572
4d9d54a7
TV		 573 dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_A0_EN;
574 if (tc->link.base.num_lanes == 2)
575 dp_phy_ctrl |= PHY_2LANE;
576 tc_write(DP_PHY_CTRL, dp_phy_ctrl);
7caff0fc
AG		 577
578 /*
579 * Initially PLLs are in bypass. Force PLL parameter update,
580 * disable PLL bypass, enable PLL
581 */
582 tc_write(DP0_PLLCTRL, PLLUPDATE | PLLEN);
583 tc_wait_pll_lock(tc);
584
585 tc_write(DP1_PLLCTRL, PLLUPDATE | PLLEN);
586 tc_wait_pll_lock(tc);
587
588 ret = tc_poll_timeout(tc->regmap, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 1,
589 1000);
590 if (ret == -ETIMEDOUT) {
591 dev_err(tc->dev, "Timeout waiting for PHY to become ready");
592 return ret;
593 } else if (ret)
594 goto err;
595
596 /* Setup AUX link */
597 tc_write(DP0_AUXCFG1, AUX_RX_FILTER_EN |
598 (0x06 << 8) | /* Aux Bit Period Calculator Threshold */
599 (0x3f << 0)); /* Aux Response Timeout Timer */
600
601 return 0;
602err:
603 dev_err(tc->dev, "tc_aux_link_setup failed: %d\n", ret);
604 return ret;
605}
606
607static int tc_get_display_props(struct tc_data *tc)
608{
609 int ret;
610 /* temp buffer */
611 u8 tmp[8];
612
613 /* Read DP Rx Link Capability */
614 ret = drm_dp_link_probe(&tc->aux, &tc->link.base);
615 if (ret < 0)
616 goto err_dpcd_read;
cffd2b16
AG		 617 if (tc->link.base.rate != 162000 && tc->link.base.rate != 270000) {
618 dev_dbg(tc->dev, "Falling to 2.7 Gbps rate\n");
619 tc->link.base.rate = 270000;
620 }
621
622 if (tc->link.base.num_lanes > 2) {
623 dev_dbg(tc->dev, "Falling to 2 lanes\n");
624 tc->link.base.num_lanes = 2;
625 }
7caff0fc
AG		 626
627 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAX_DOWNSPREAD, tmp);
628 if (ret < 0)
629 goto err_dpcd_read;
630 tc->link.spread = tmp[0] & BIT(0); /* 0.5% down spread */
631
632 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAIN_LINK_CHANNEL_CODING, tmp);
633 if (ret < 0)
634 goto err_dpcd_read;
635 tc->link.coding8b10b = tmp[0] & BIT(0);
636 tc->link.scrambler_dis = 0;
637 /* read assr */
638 ret = drm_dp_dpcd_readb(&tc->aux, DP_EDP_CONFIGURATION_SET, tmp);
639 if (ret < 0)
640 goto err_dpcd_read;
641 tc->link.assr = tmp[0] & DP_ALTERNATE_SCRAMBLER_RESET_ENABLE;
642
643 dev_dbg(tc->dev, "DPCD rev: %d.%d, rate: %s, lanes: %d, framing: %s\n",
644 tc->link.base.revision >> 4, tc->link.base.revision & 0x0f,
645 (tc->link.base.rate == 162000) ? "1.62Gbps" : "2.7Gbps",
646 tc->link.base.num_lanes,
647 (tc->link.base.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) ?
648 "enhanced" : "non-enhanced");
649 dev_dbg(tc->dev, "ANSI 8B/10B: %d\n", tc->link.coding8b10b);
650 dev_dbg(tc->dev, "Display ASSR: %d, TC358767 ASSR: %d\n",
651 tc->link.assr, tc->assr);
652
653 return 0;
654
655err_dpcd_read:
656 dev_err(tc->dev, "failed to read DPCD: %d\n", ret);
657 return ret;
7caff0fc
AG		 658}
659
63f8f3ba
LP		 660static int tc_set_video_mode(struct tc_data *tc,
661 const struct drm_display_mode *mode)
7caff0fc
AG		 662{
663 int ret;
664 int vid_sync_dly;
665 int max_tu_symbol;
666
667 int left_margin = mode->htotal - mode->hsync_end;
668 int right_margin = mode->hsync_start - mode->hdisplay;
669 int hsync_len = mode->hsync_end - mode->hsync_start;
670 int upper_margin = mode->vtotal - mode->vsync_end;
671 int lower_margin = mode->vsync_start - mode->vdisplay;
672 int vsync_len = mode->vsync_end - mode->vsync_start;
673
66d1c3b9
AG		 674 /*
675 * Recommended maximum number of symbols transferred in a transfer unit:
676 * DIV_ROUND_UP((input active video bandwidth in bytes) * tu_size,
677 * (output active video bandwidth in bytes))
678 * Must be less than tu_size.
679 */
680 max_tu_symbol = TU_SIZE_RECOMMENDED - 1;
681
7caff0fc
AG		 682 dev_dbg(tc->dev, "set mode %dx%d\n",
683 mode->hdisplay, mode->vdisplay);
684 dev_dbg(tc->dev, "H margin %d,%d sync %d\n",
685 left_margin, right_margin, hsync_len);
686 dev_dbg(tc->dev, "V margin %d,%d sync %d\n",
687 upper_margin, lower_margin, vsync_len);
688 dev_dbg(tc->dev, "total: %dx%d\n", mode->htotal, mode->vtotal);
689
690
66d1c3b9
AG		 691 /*
692 * LCD Ctl Frame Size
693 * datasheet is not clear of vsdelay in case of DPI
694 * assume we do not need any delay when DPI is a source of
695 * sync signals
696 */
697 tc_write(VPCTRL0, (0 << 20) /* VSDELAY */ |
7caff0fc 698 OPXLFMT_RGB888 | FRMSYNC_DISABLED | MSF_DISABLED);
66d1c3b9
AG		 699 tc_write(HTIM01, (ALIGN(left_margin, 2) << 16) | /* H back porch */
700 (ALIGN(hsync_len, 2) << 0)); /* Hsync */
701 tc_write(HTIM02, (ALIGN(right_margin, 2) << 16) | /* H front porch */
702 (ALIGN(mode->hdisplay, 2) << 0)); /* width */
7caff0fc
AG		 703 tc_write(VTIM01, (upper_margin << 16) | /* V back porch */
704 (vsync_len << 0)); /* Vsync */
705 tc_write(VTIM02, (lower_margin << 16) | /* V front porch */
706 (mode->vdisplay << 0)); /* height */
707 tc_write(VFUEN0, VFUEN); /* update settings */
708
709 /* Test pattern settings */
710 tc_write(TSTCTL,
711 (120 << 24) | /* Red Color component value */
712 (20 << 16) | /* Green Color component value */
713 (99 << 8) | /* Blue Color component value */
714 (1 << 4) | /* Enable I2C Filter */
715 (2 << 0) | /* Color bar Mode */
716 0);
717
718 /* DP Main Stream Attributes */
719 vid_sync_dly = hsync_len + left_margin + mode->hdisplay;
720 tc_write(DP0_VIDSYNCDELAY,
66d1c3b9 721 (max_tu_symbol << 16) | /* thresh_dly */
7caff0fc
AG		 722 (vid_sync_dly << 0));
723
724 tc_write(DP0_TOTALVAL, (mode->vtotal << 16) | (mode->htotal));
725
726 tc_write(DP0_STARTVAL,
727 ((upper_margin + vsync_len) << 16) |
728 ((left_margin + hsync_len) << 0));
729
730 tc_write(DP0_ACTIVEVAL, (mode->vdisplay << 16) | (mode->hdisplay));
731
7923e09c
TV		 732 tc_write(DP0_SYNCVAL, (vsync_len << 16) | (hsync_len << 0) |
733 ((mode->flags & DRM_MODE_FLAG_NHSYNC) ? SYNCVAL_HS_POL_ACTIVE_LOW : 0) |
734 ((mode->flags & DRM_MODE_FLAG_NVSYNC) ? SYNCVAL_VS_POL_ACTIVE_LOW : 0));
7caff0fc
AG		 735
736 tc_write(DPIPXLFMT, VS_POL_ACTIVE_LOW | HS_POL_ACTIVE_LOW |
737 DE_POL_ACTIVE_HIGH | SUB_CFG_TYPE_CONFIG1 | DPI_BPP_RGB888);
738
f3b8adbe
AG		 739 tc_write(DP0_MISC, (max_tu_symbol << 23) | (TU_SIZE_RECOMMENDED << 16) |
740 BPC_8);
7caff0fc
AG		 741
742 return 0;
743err:
744 return ret;
745}
746
747static int tc_link_training(struct tc_data *tc, int pattern)
748{
749 const char * const *errors;
750 u32 srcctrl = tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS |
751 DP0_SRCCTRL_AUTOCORRECT;
752 int timeout;
753 int retry;
754 u32 value;
755 int ret;
756
757 if (pattern == DP_TRAINING_PATTERN_1) {
758 srcctrl |= DP0_SRCCTRL_TP1;
759 errors = training_pattern1_errors;
760 } else {
761 srcctrl |= DP0_SRCCTRL_TP2;
762 errors = training_pattern2_errors;
763 }
764
765 /* Set DPCD 0x102 for Training Part 1 or 2 */
766 tc_write(DP0_SNKLTCTRL, DP_LINK_SCRAMBLING_DISABLE | pattern);
767
768 tc_write(DP0_LTLOOPCTRL,
769 (0x0f << 28) | /* Defer Iteration Count */
770 (0x0f << 24) | /* Loop Iteration Count */
771 (0x0d << 0)); /* Loop Timer Delay */
772
773 retry = 5;
774 do {
775 /* Set DP0 Training Pattern */
776 tc_write(DP0_SRCCTRL, srcctrl);
777
778 /* Enable DP0 to start Link Training */
779 tc_write(DP0CTL, DP_EN);
780
781 /* wait */
782 timeout = 1000;
783 do {
784 tc_read(DP0_LTSTAT, &value);
785 udelay(1);
786 } while ((!(value & LT_LOOPDONE)) && (--timeout));
787 if (timeout == 0) {
788 dev_err(tc->dev, "Link training timeout!\n");
789 } else {
790 int pattern = (value >> 11) & 0x3;
791 int error = (value >> 8) & 0x7;
792
793 dev_dbg(tc->dev,
794 "Link training phase %d done after %d uS: %s\n",
795 pattern, 1000 - timeout, errors[error]);
796 if (pattern == DP_TRAINING_PATTERN_1 && error == 0)
797 break;
798 if (pattern == DP_TRAINING_PATTERN_2) {
799 value &= LT_CHANNEL1_EQ_BITS |
800 LT_INTERLANE_ALIGN_DONE |
801 LT_CHANNEL0_EQ_BITS;
802 /* in case of two lanes */
803 if ((tc->link.base.num_lanes == 2) &&
804 (value == (LT_CHANNEL1_EQ_BITS |
805 LT_INTERLANE_ALIGN_DONE |
806 LT_CHANNEL0_EQ_BITS)))
807 break;
808 /* in case of one line */
809 if ((tc->link.base.num_lanes == 1) &&
810 (value == (LT_INTERLANE_ALIGN_DONE |
811 LT_CHANNEL0_EQ_BITS)))
812 break;
813 }
814 }
815 /* restart */
816 tc_write(DP0CTL, 0);
817 usleep_range(10, 20);
818 } while (--retry);
819 if (retry == 0) {
820 dev_err(tc->dev, "Failed to finish training phase %d\n",
821 pattern);
822 }
823
824 return 0;
825err:
826 return ret;
827}
828
829static int tc_main_link_setup(struct tc_data *tc)
830{
831 struct drm_dp_aux *aux = &tc->aux;
832 struct device *dev = tc->dev;
833 unsigned int rate;
834 u32 dp_phy_ctrl;
835 int timeout;
7caff0fc
AG		 836 u32 value;
837 int ret;
838 u8 tmp[8];
839
840 /* display mode should be set at this point */
841 if (!tc->mode)
842 return -EINVAL;
843
9a63bd6f
TV		 844 tc_write(DP0_SRCCTRL, tc_srcctrl(tc));
845 /* SSCG and BW27 on DP1 must be set to the same as on DP0 */
846 tc_write(DP1_SRCCTRL,
847 (tc->link.spread ? DP0_SRCCTRL_SSCG : 0) |
848 ((tc->link.base.rate != 162000) ? DP0_SRCCTRL_BW27 : 0));
7caff0fc
AG		 849
850 rate = clk_get_rate(tc->refclk);
851 switch (rate) {
852 case 38400000:
853 value = REF_FREQ_38M4;
854 break;
855 case 26000000:
856 value = REF_FREQ_26M;
857 break;
858 case 19200000:
859 value = REF_FREQ_19M2;
860 break;
861 case 13000000:
862 value = REF_FREQ_13M;
863 break;
864 default:
865 return -EINVAL;
866 }
867 value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2;
868 tc_write(SYS_PLLPARAM, value);
adf41098 869
7caff0fc 870 /* Setup Main Link */
4d9d54a7
TV		 871 dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_A0_EN | PHY_M0_EN;
872 if (tc->link.base.num_lanes == 2)
873 dp_phy_ctrl |= PHY_2LANE;
7caff0fc
AG		 874 tc_write(DP_PHY_CTRL, dp_phy_ctrl);
875 msleep(100);
876
877 /* PLL setup */
878 tc_write(DP0_PLLCTRL, PLLUPDATE | PLLEN);
879 tc_wait_pll_lock(tc);
880
881 tc_write(DP1_PLLCTRL, PLLUPDATE | PLLEN);
882 tc_wait_pll_lock(tc);
883
884 /* PXL PLL setup */
885 if (tc_test_pattern) {
886 ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk),
887 1000 * tc->mode->clock);
888 if (ret)
889 goto err;
890 }
891
892 /* Reset/Enable Main Links */
893 dp_phy_ctrl |= DP_PHY_RST | PHY_M1_RST | PHY_M0_RST;
894 tc_write(DP_PHY_CTRL, dp_phy_ctrl);
895 usleep_range(100, 200);
896 dp_phy_ctrl &= ~(DP_PHY_RST | PHY_M1_RST | PHY_M0_RST);
897 tc_write(DP_PHY_CTRL, dp_phy_ctrl);
898
899 timeout = 1000;
900 do {
901 tc_read(DP_PHY_CTRL, &value);
902 udelay(1);
903 } while ((!(value & PHY_RDY)) && (--timeout));
904
905 if (timeout == 0) {
906 dev_err(dev, "timeout waiting for phy become ready");
907 return -ETIMEDOUT;
908 }
909
910 /* Set misc: 8 bits per color */
911 ret = regmap_update_bits(tc->regmap, DP0_MISC, BPC_8, BPC_8);
912 if (ret)
913 goto err;
914
915 /*
916 * ASSR mode
917 * on TC358767 side ASSR configured through strap pin
918 * seems there is no way to change this setting from SW
919 *
920 * check is tc configured for same mode
921 */
922 if (tc->assr != tc->link.assr) {
923 dev_dbg(dev, "Trying to set display to ASSR: %d\n",
924 tc->assr);
925 /* try to set ASSR on display side */
926 tmp[0] = tc->assr;
927 ret = drm_dp_dpcd_writeb(aux, DP_EDP_CONFIGURATION_SET, tmp[0]);
928 if (ret < 0)
929 goto err_dpcd_read;
930 /* read back */
931 ret = drm_dp_dpcd_readb(aux, DP_EDP_CONFIGURATION_SET, tmp);
932 if (ret < 0)
933 goto err_dpcd_read;
934
935 if (tmp[0] != tc->assr) {
87291e5d 936 dev_dbg(dev, "Failed to switch display ASSR to %d, falling back to unscrambled mode\n",
7caff0fc
AG		 937 tc->assr);
938 /* trying with disabled scrambler */
939 tc->link.scrambler_dis = 1;
940 }
941 }
942
943 /* Setup Link & DPRx Config for Training */
944 ret = drm_dp_link_configure(aux, &tc->link.base);
945 if (ret < 0)
946 goto err_dpcd_write;
947
948 /* DOWNSPREAD_CTRL */
949 tmp[0] = tc->link.spread ? DP_SPREAD_AMP_0_5 : 0x00;
950 /* MAIN_LINK_CHANNEL_CODING_SET */
951 tmp[1] = tc->link.coding8b10b ? DP_SET_ANSI_8B10B : 0x00;
952 ret = drm_dp_dpcd_write(aux, DP_DOWNSPREAD_CTRL, tmp, 2);
953 if (ret < 0)
954 goto err_dpcd_write;
955
956 ret = tc_link_training(tc, DP_TRAINING_PATTERN_1);
957 if (ret)
958 goto err;
959
960 ret = tc_link_training(tc, DP_TRAINING_PATTERN_2);
961 if (ret)
962 goto err;
963
964 /* Clear DPCD 0x102 */
965 /* Note: Can Not use DP0_SNKLTCTRL (0x06E4) short cut */
966 tmp[0] = tc->link.scrambler_dis ? DP_LINK_SCRAMBLING_DISABLE : 0x00;
967 ret = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, tmp[0]);
968 if (ret < 0)
969 goto err_dpcd_write;
970
971 /* Clear Training Pattern, set AutoCorrect Mode = 1 */
972 tc_write(DP0_SRCCTRL, tc_srcctrl(tc) | DP0_SRCCTRL_AUTOCORRECT);
973
974 /* Wait */
975 timeout = 100;
976 do {
977 udelay(1);
978 /* Read DPCD 0x202-0x207 */
979 ret = drm_dp_dpcd_read_link_status(aux, tmp + 2);
980 if (ret < 0)
981 goto err_dpcd_read;
4dbd6c03
AG		 982 } while ((--timeout) &&
983 !(drm_dp_channel_eq_ok(tmp + 2, tc->link.base.num_lanes)));
7caff0fc
AG		 984
985 if (timeout == 0) {
986 /* Read DPCD 0x200-0x201 */
987 ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT, tmp, 2);
988 if (ret < 0)
989 goto err_dpcd_read;
4dbd6c03 990 dev_err(dev, "channel(s) EQ not ok\n");
7caff0fc
AG		 991 dev_info(dev, "0x0200 SINK_COUNT: 0x%02x\n", tmp[0]);
992 dev_info(dev, "0x0201 DEVICE_SERVICE_IRQ_VECTOR: 0x%02x\n",
993 tmp[1]);
994 dev_info(dev, "0x0202 LANE0_1_STATUS: 0x%02x\n", tmp[2]);
995 dev_info(dev, "0x0204 LANE_ALIGN_STATUS_UPDATED: 0x%02x\n",
996 tmp[4]);
997 dev_info(dev, "0x0205 SINK_STATUS: 0x%02x\n", tmp[5]);
998 dev_info(dev, "0x0206 ADJUST_REQUEST_LANE0_1: 0x%02x\n",
999 tmp[6]);
1000
7caff0fc
AG		 1001 return -EAGAIN;
1002 }
1003
1004 ret = tc_set_video_mode(tc, tc->mode);
1005 if (ret)
1006 goto err;
1007
1008 /* Set M/N */
1009 ret = tc_stream_clock_calc(tc);
1010 if (ret)
1011 goto err;
1012
1013 return 0;
1014err_dpcd_read:
1015 dev_err(tc->dev, "Failed to read DPCD: %d\n", ret);
1016 return ret;
1017err_dpcd_write:
1018 dev_err(tc->dev, "Failed to write DPCD: %d\n", ret);
1019err:
1020 return ret;
1021}
1022
1023static int tc_main_link_stream(struct tc_data *tc, int state)
1024{
1025 int ret;
1026 u32 value;
1027
1028 dev_dbg(tc->dev, "stream: %d\n", state);
1029
1030 if (state) {
1031 value = VID_MN_GEN | DP_EN;
1032 if (tc->link.base.capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
1033 value |= EF_EN;
1034 tc_write(DP0CTL, value);
1035 /*
1036 * VID_EN assertion should be delayed by at least N * LSCLK
1037 * cycles from the time VID_MN_GEN is enabled in order to
1038 * generate stable values for VID_M. LSCLK is 270 MHz or
1039 * 162 MHz, VID_N is set to 32768 in tc_stream_clock_calc(),
1040 * so a delay of at least 203 us should suffice.
1041 */
1042 usleep_range(500, 1000);
1043 value |= VID_EN;
1044 tc_write(DP0CTL, value);
1045 /* Set input interface */
1046 value = DP0_AUDSRC_NO_INPUT;
1047 if (tc_test_pattern)
1048 value |= DP0_VIDSRC_COLOR_BAR;
1049 else
1050 value |= DP0_VIDSRC_DPI_RX;
1051 tc_write(SYSCTRL, value);
1052 } else {
1053 tc_write(DP0CTL, 0);
1054 }
1055
1056 return 0;
1057err:
1058 return ret;
1059}
1060
7caff0fc
AG		 1061static void tc_bridge_pre_enable(struct drm_bridge *bridge)
1062{
1063 struct tc_data *tc = bridge_to_tc(bridge);
1064
1065 drm_panel_prepare(tc->panel);
1066}
1067
1068static void tc_bridge_enable(struct drm_bridge *bridge)
1069{
1070 struct tc_data *tc = bridge_to_tc(bridge);
1071 int ret;
1072
1073 ret = tc_main_link_setup(tc);
1074 if (ret < 0) {
1075 dev_err(tc->dev, "main link setup error: %d\n", ret);
1076 return;
1077 }
1078
1079 ret = tc_main_link_stream(tc, 1);
1080 if (ret < 0) {
1081 dev_err(tc->dev, "main link stream start error: %d\n", ret);
1082 return;
1083 }
1084
1085 drm_panel_enable(tc->panel);
1086}
1087
1088static void tc_bridge_disable(struct drm_bridge *bridge)
1089{
1090 struct tc_data *tc = bridge_to_tc(bridge);
1091 int ret;
1092
1093 drm_panel_disable(tc->panel);
1094
1095 ret = tc_main_link_stream(tc, 0);
1096 if (ret < 0)
1097 dev_err(tc->dev, "main link stream stop error: %d\n", ret);
1098}
1099
1100static void tc_bridge_post_disable(struct drm_bridge *bridge)
1101{
1102 struct tc_data *tc = bridge_to_tc(bridge);
1103
1104 drm_panel_unprepare(tc->panel);
1105}
1106
1107static bool tc_bridge_mode_fixup(struct drm_bridge *bridge,
1108 const struct drm_display_mode *mode,
1109 struct drm_display_mode *adj)
1110{
1111 /* Fixup sync polarities, both hsync and vsync are active low */
1112 adj->flags = mode->flags;
1113 adj->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
1114 adj->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
1115
1116 return true;
1117}
1118
114b3ac8 1119static enum drm_mode_status tc_connector_mode_valid(struct drm_connector *connector,
7caff0fc
AG		 1120 struct drm_display_mode *mode)
1121{
51b9e62e
TV		 1122 struct tc_data *tc = connector_to_tc(connector);
1123 u32 req, avail;
1124 u32 bits_per_pixel = 24;
1125
99fc8e96
AG		 1126 /* DPI interface clock limitation: upto 154 MHz */
1127 if (mode->clock > 154000)
1128 return MODE_CLOCK_HIGH;
1129
51b9e62e
TV		 1130 req = mode->clock * bits_per_pixel / 8;
1131 avail = tc->link.base.num_lanes * tc->link.base.rate;
1132
1133 if (req > avail)
1134 return MODE_BAD;
1135
7caff0fc
AG		 1136 return MODE_OK;
1137}
1138
1139static void tc_bridge_mode_set(struct drm_bridge *bridge,
63f8f3ba
LP		 1140 const struct drm_display_mode *mode,
1141 const struct drm_display_mode *adj)
7caff0fc
AG		 1142{
1143 struct tc_data *tc = bridge_to_tc(bridge);
1144
1145 tc->mode = mode;
1146}
1147
1148static int tc_connector_get_modes(struct drm_connector *connector)
1149{
1150 struct tc_data *tc = connector_to_tc(connector);
1151 struct edid *edid;
1152 unsigned int count;
1153
1154 if (tc->panel && tc->panel->funcs && tc->panel->funcs->get_modes) {
1155 count = tc->panel->funcs->get_modes(tc->panel);
1156 if (count > 0)
1157 return count;
1158 }
1159
1160 edid = drm_get_edid(connector, &tc->aux.ddc);
1161
1162 kfree(tc->edid);
1163 tc->edid = edid;
1164 if (!edid)
1165 return 0;
1166
c555f023 1167 drm_connector_update_edid_property(connector, edid);
7caff0fc
AG		 1168 count = drm_add_edid_modes(connector, edid);
1169
1170 return count;
1171}
1172
1173static void tc_connector_set_polling(struct tc_data *tc,
1174 struct drm_connector *connector)
1175{
1176 /* TODO: add support for HPD */
1177 connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1178 DRM_CONNECTOR_POLL_DISCONNECT;
1179}
1180
1181static struct drm_encoder *
1182tc_connector_best_encoder(struct drm_connector *connector)
1183{
1184 struct tc_data *tc = connector_to_tc(connector);
1185
1186 return tc->bridge.encoder;
1187}
1188
1189static const struct drm_connector_helper_funcs tc_connector_helper_funcs = {
1190 .get_modes = tc_connector_get_modes,
1191 .mode_valid = tc_connector_mode_valid,
1192 .best_encoder = tc_connector_best_encoder,
1193};
1194
7caff0fc 1195static const struct drm_connector_funcs tc_connector_funcs = {
7caff0fc 1196 .fill_modes = drm_helper_probe_single_connector_modes,
fdd8326a 1197 .destroy = drm_connector_cleanup,
7caff0fc
AG		 1198 .reset = drm_atomic_helper_connector_reset,
1199 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1200 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1201};
1202
1203static int tc_bridge_attach(struct drm_bridge *bridge)
1204{
1205 u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24;
1206 struct tc_data *tc = bridge_to_tc(bridge);
1207 struct drm_device *drm = bridge->dev;
1208 int ret;
1209
1210 /* Create eDP connector */
1211 drm_connector_helper_add(&tc->connector, &tc_connector_helper_funcs);
1212 ret = drm_connector_init(drm, &tc->connector, &tc_connector_funcs,
f8c15790
TV		 1213 tc->panel ? DRM_MODE_CONNECTOR_eDP :
1214 DRM_MODE_CONNECTOR_DisplayPort);
7caff0fc
AG		 1215 if (ret)
1216 return ret;
1217
1218 if (tc->panel)
1219 drm_panel_attach(tc->panel, &tc->connector);
1220
1221 drm_display_info_set_bus_formats(&tc->connector.display_info,
1222 &bus_format, 1);
4842379c
TV		 1223 tc->connector.display_info.bus_flags =
1224 DRM_BUS_FLAG_DE_HIGH |
1225 DRM_BUS_FLAG_PIXDATA_NEGEDGE |
1226 DRM_BUS_FLAG_SYNC_NEGEDGE;
cde4c44d 1227 drm_connector_attach_encoder(&tc->connector, tc->bridge.encoder);
7caff0fc
AG		 1228
1229 return 0;
1230}
1231
1232static const struct drm_bridge_funcs tc_bridge_funcs = {
1233 .attach = tc_bridge_attach,
1234 .mode_set = tc_bridge_mode_set,
1235 .pre_enable = tc_bridge_pre_enable,
1236 .enable = tc_bridge_enable,
1237 .disable = tc_bridge_disable,
1238 .post_disable = tc_bridge_post_disable,
1239 .mode_fixup = tc_bridge_mode_fixup,
1240};
1241
1242static bool tc_readable_reg(struct device *dev, unsigned int reg)
1243{
1244 return reg != SYSCTRL;
1245}
1246
1247static const struct regmap_range tc_volatile_ranges[] = {
1248 regmap_reg_range(DP0_AUXWDATA(0), DP0_AUXSTATUS),
1249 regmap_reg_range(DP0_LTSTAT, DP0_SNKLTCHGREQ),
1250 regmap_reg_range(DP_PHY_CTRL, DP_PHY_CTRL),
1251 regmap_reg_range(DP0_PLLCTRL, PXL_PLLCTRL),
1252 regmap_reg_range(VFUEN0, VFUEN0),
1253};
1254
1255static const struct regmap_access_table tc_volatile_table = {
1256 .yes_ranges = tc_volatile_ranges,
1257 .n_yes_ranges = ARRAY_SIZE(tc_volatile_ranges),
1258};
1259
1260static bool tc_writeable_reg(struct device *dev, unsigned int reg)
1261{
1262 return (reg != TC_IDREG) &&
1263 (reg != DP0_LTSTAT) &&
1264 (reg != DP0_SNKLTCHGREQ);
1265}
1266
1267static const struct regmap_config tc_regmap_config = {
1268 .name = "tc358767",
1269 .reg_bits = 16,
1270 .val_bits = 32,
1271 .reg_stride = 4,
1272 .max_register = PLL_DBG,
1273 .cache_type = REGCACHE_RBTREE,
1274 .readable_reg = tc_readable_reg,
1275 .volatile_table = &tc_volatile_table,
1276 .writeable_reg = tc_writeable_reg,
1277 .reg_format_endian = REGMAP_ENDIAN_BIG,
1278 .val_format_endian = REGMAP_ENDIAN_LITTLE,
1279};
1280
1281static int tc_probe(struct i2c_client *client, const struct i2c_device_id *id)
1282{
1283 struct device *dev = &client->dev;
7caff0fc
AG		 1284 struct tc_data *tc;
1285 int ret;
1286
1287 tc = devm_kzalloc(dev, sizeof(*tc), GFP_KERNEL);
1288 if (!tc)
1289 return -ENOMEM;
1290
1291 tc->dev = dev;
1292
1293 /* port@2 is the output port */
ebc94461 1294 ret = drm_of_find_panel_or_bridge(dev->of_node, 2, 0, &tc->panel, NULL);
d630213f 1295 if (ret && ret != -ENODEV)
ebc94461 1296 return ret;
7caff0fc
AG		 1297
1298 /* Shut down GPIO is optional */
1299 tc->sd_gpio = devm_gpiod_get_optional(dev, "shutdown", GPIOD_OUT_HIGH);
1300 if (IS_ERR(tc->sd_gpio))
1301 return PTR_ERR(tc->sd_gpio);
1302
1303 if (tc->sd_gpio) {
1304 gpiod_set_value_cansleep(tc->sd_gpio, 0);
1305 usleep_range(5000, 10000);
1306 }
1307
1308 /* Reset GPIO is optional */
1309 tc->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
1310 if (IS_ERR(tc->reset_gpio))
1311 return PTR_ERR(tc->reset_gpio);
1312
1313 if (tc->reset_gpio) {
1314 gpiod_set_value_cansleep(tc->reset_gpio, 1);
1315 usleep_range(5000, 10000);
1316 }
1317
1318 tc->refclk = devm_clk_get(dev, "ref");
1319 if (IS_ERR(tc->refclk)) {
1320 ret = PTR_ERR(tc->refclk);
1321 dev_err(dev, "Failed to get refclk: %d\n", ret);
1322 return ret;
1323 }
1324
1325 tc->regmap = devm_regmap_init_i2c(client, &tc_regmap_config);
1326 if (IS_ERR(tc->regmap)) {
1327 ret = PTR_ERR(tc->regmap);
1328 dev_err(dev, "Failed to initialize regmap: %d\n", ret);
1329 return ret;
1330 }
1331
1332 ret = regmap_read(tc->regmap, TC_IDREG, &tc->rev);
1333 if (ret) {
1334 dev_err(tc->dev, "can not read device ID: %d\n", ret);
1335 return ret;
1336 }
1337
1338 if ((tc->rev != 0x6601) && (tc->rev != 0x6603)) {
1339 dev_err(tc->dev, "invalid device ID: 0x%08x\n", tc->rev);
1340 return -EINVAL;
1341 }
1342
1343 tc->assr = (tc->rev == 0x6601); /* Enable ASSR for eDP panels */
1344
1345 ret = tc_aux_link_setup(tc);
1346 if (ret)
1347 return ret;
1348
1349 /* Register DP AUX channel */
1350 tc->aux.name = "TC358767 AUX i2c adapter";
1351 tc->aux.dev = tc->dev;
1352 tc->aux.transfer = tc_aux_transfer;
1353 ret = drm_dp_aux_register(&tc->aux);
1354 if (ret)
1355 return ret;
1356
1357 ret = tc_get_display_props(tc);
1358 if (ret)
1359 goto err_unregister_aux;
1360
1361 tc_connector_set_polling(tc, &tc->connector);
1362
1363 tc->bridge.funcs = &tc_bridge_funcs;
1364 tc->bridge.of_node = dev->of_node;
dc01732e 1365 drm_bridge_add(&tc->bridge);
7caff0fc
AG		 1366
1367 i2c_set_clientdata(client, tc);
1368
1369 return 0;
1370err_unregister_aux:
1371 drm_dp_aux_unregister(&tc->aux);
1372 return ret;
1373}
1374
1375static int tc_remove(struct i2c_client *client)
1376{
1377 struct tc_data *tc = i2c_get_clientdata(client);
1378
1379 drm_bridge_remove(&tc->bridge);
1380 drm_dp_aux_unregister(&tc->aux);
1381
1382 tc_pxl_pll_dis(tc);
1383
1384 return 0;
1385}
1386
1387static const struct i2c_device_id tc358767_i2c_ids[] = {
1388 { "tc358767", 0 },
1389 { }
1390};
1391MODULE_DEVICE_TABLE(i2c, tc358767_i2c_ids);
1392
1393static const struct of_device_id tc358767_of_ids[] = {
1394 { .compatible = "toshiba,tc358767", },
1395 { }
1396};
1397MODULE_DEVICE_TABLE(of, tc358767_of_ids);
1398
1399static struct i2c_driver tc358767_driver = {
1400 .driver = {
1401 .name = "tc358767",
1402 .of_match_table = tc358767_of_ids,
1403 },
1404 .id_table = tc358767_i2c_ids,
1405 .probe = tc_probe,
1406 .remove = tc_remove,
1407};
1408module_i2c_driver(tc358767_driver);
1409
1410MODULE_AUTHOR("Andrey Gusakov <andrey.gusakov@cogentembedded.com>");
1411MODULE_DESCRIPTION("tc358767 eDP encoder driver");
1412MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)