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drm/bridge: dw-hdmi: set channel count in the infoframes
[linux-2.6-block.git] / drivers / gpu / drm / bridge / synopsys / dw-hdmi.c
CommitLineData
2874c5fd 1// SPDX-License-Identifier: GPL-2.0-or-later
9aaf880e 2/*
3efc2fa3
VZ		 3 * DesignWare High-Definition Multimedia Interface (HDMI) driver
4 *
5 * Copyright (C) 2013-2015 Mentor Graphics Inc.
9aaf880e 6 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
3efc2fa3 7 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
9aaf880e 8 */
95b60804 9#include <linux/clk.h>
9aaf880e
FE		 10#include <linux/delay.h>
11#include <linux/err.h>
5a819ed6 12#include <linux/hdmi.h>
95b60804
SR		 13#include <linux/irq.h>
14#include <linux/module.h>
6bcf4953 15#include <linux/mutex.h>
9aaf880e 16#include <linux/of_device.h>
50f9495e 17#include <linux/pinctrl/consumer.h>
80e2f979 18#include <linux/regmap.h>
95b60804 19#include <linux/dma-mapping.h>
b90120a9 20#include <linux/spinlock.h>
9aaf880e 21
95b60804
SR		 22#include <media/cec-notifier.h>
23
24#include <uapi/linux/media-bus-format.h>
25#include <uapi/linux/videodev2.h>
26
27#include <drm/bridge/dw_hdmi.h>
2c5b2ccc 28#include <drm/drm_atomic_helper.h>
9aaf880e
FE		 29#include <drm/drm_edid.h>
30#include <drm/drm_encoder_slave.h>
95b60804
SR		 31#include <drm/drm_of.h>
32#include <drm/drm_print.h>
fcd70cd3 33#include <drm/drm_probe_helper.h>
95b60804 34#include <drm/drm_scdc_helper.h>
def23aa7 35
248a86fc 36#include "dw-hdmi-audio.h"
a616e63c 37#include "dw-hdmi-cec.h"
95b60804 38#include "dw-hdmi.h"
e84b8d75 39
94bb4dc1 40#define DDC_SEGMENT_ADDR 0x30
e84b8d75 41
9aaf880e
FE		 42#define HDMI_EDID_LEN 512
43
264fce6c
NA		 44/* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */
45#define SCDC_MIN_SOURCE_VERSION 0x1
46
47#define HDMI14_MAX_TMDSCLK 340000000
48
9aaf880e
FE		 49enum hdmi_datamap {
50 RGB444_8B = 0x01,
51 RGB444_10B = 0x03,
52 RGB444_12B = 0x05,
53 RGB444_16B = 0x07,
54 YCbCr444_8B = 0x09,
55 YCbCr444_10B = 0x0B,
56 YCbCr444_12B = 0x0D,
57 YCbCr444_16B = 0x0F,
58 YCbCr422_8B = 0x16,
59 YCbCr422_10B = 0x14,
60 YCbCr422_12B = 0x12,
61};
62
9aaf880e
FE		 63static const u16 csc_coeff_default[3][4] = {
64 { 0x2000, 0x0000, 0x0000, 0x0000 },
65 { 0x0000, 0x2000, 0x0000, 0x0000 },
66 { 0x0000, 0x0000, 0x2000, 0x0000 }
67};
68
69static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
70 { 0x2000, 0x6926, 0x74fd, 0x010e },
71 { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
72 { 0x2000, 0x0000, 0x38b4, 0x7e3b }
73};
74
75static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
76 { 0x2000, 0x7106, 0x7a02, 0x00a7 },
77 { 0x2000, 0x3264, 0x0000, 0x7e6d },
78 { 0x2000, 0x0000, 0x3b61, 0x7e25 }
79};
80
81static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
82 { 0x2591, 0x1322, 0x074b, 0x0000 },
83 { 0x6535, 0x2000, 0x7acc, 0x0200 },
84 { 0x6acd, 0x7534, 0x2000, 0x0200 }
85};
86
87static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
88 { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
89 { 0x62f0, 0x2000, 0x7d11, 0x0200 },
90 { 0x6756, 0x78ab, 0x2000, 0x0200 }
91};
92
93struct hdmi_vmode {
9aaf880e
FE		 94 bool mdataenablepolarity;
95
96 unsigned int mpixelclock;
97 unsigned int mpixelrepetitioninput;
98 unsigned int mpixelrepetitionoutput;
ba9877e2 99 unsigned int mtmdsclock;
9aaf880e
FE		 100};
101
102struct hdmi_data_info {
def23aa7
NA		 103 unsigned int enc_in_bus_format;
104 unsigned int enc_out_bus_format;
105 unsigned int enc_in_encoding;
106 unsigned int enc_out_encoding;
9aaf880e
FE		 107 unsigned int pix_repet_factor;
108 unsigned int hdcp_enable;
109 struct hdmi_vmode video_mode;
110};
111
3efc2fa3
VZ		 112struct dw_hdmi_i2c {
113 struct i2c_adapter adap;
114
115 struct mutex lock; /* used to serialize data transfers */
116 struct completion cmp;
117 u8 stat;
118
119 u8 slave_reg;
120 bool is_regaddr;
94bb4dc1 121 bool is_segment;
3efc2fa3
VZ		 122};
123
faba6c3c
LP		 124struct dw_hdmi_phy_data {
125 enum dw_hdmi_phy_type type;
126 const char *name;
b0e583e5 127 unsigned int gen;
faba6c3c 128 bool has_svsret;
2ef9dfed
KB		 129 int (*configure)(struct dw_hdmi *hdmi,
130 const struct dw_hdmi_plat_data *pdata,
131 unsigned long mpixelclock);
faba6c3c
LP		 132};
133
b21f4b65 134struct dw_hdmi {
9aaf880e 135 struct drm_connector connector;
70c963ec 136 struct drm_bridge bridge;
9aaf880e 137
be41fc55
LP		 138 unsigned int version;
139
140 struct platform_device *audio;
a616e63c 141 struct platform_device *cec;
9aaf880e
FE		 142 struct device *dev;
143 struct clk *isfr_clk;
144 struct clk *iahb_clk;
ebe32c3e 145 struct clk *cec_clk;
3efc2fa3 146 struct dw_hdmi_i2c *i2c;
9aaf880e
FE		 147
148 struct hdmi_data_info hdmi_data;
b21f4b65
AY		 149 const struct dw_hdmi_plat_data *plat_data;
150
9aaf880e
FE		 151 int vic;
152
153 u8 edid[HDMI_EDID_LEN];
9aaf880e 154
f1585f6e
LP		 155 struct {
156 const struct dw_hdmi_phy_ops *ops;
157 const char *name;
158 void *data;
159 bool enabled;
160 } phy;
faba6c3c 161
9aaf880e
FE		 162 struct drm_display_mode previous_mode;
163
9aaf880e
FE		 164 struct i2c_adapter *ddc;
165 void __iomem *regs;
05b1342f 166 bool sink_is_hdmi;
f709ec07 167 bool sink_has_audio;
9aaf880e 168
50f9495e
DA		 169 struct pinctrl *pinctrl;
170 struct pinctrl_state *default_state;
171 struct pinctrl_state *unwedge_state;
172
b872a8e1 173 struct mutex mutex; /* for state below and previous_mode */
381f05a7 174 enum drm_connector_force force; /* mutex-protected force state */
b872a8e1 175 bool disabled; /* DRM has disabled our bridge */
381f05a7 176 bool bridge_is_on; /* indicates the bridge is on */
aeac23bd
RK		 177 bool rxsense; /* rxsense state */
178 u8 phy_mask; /* desired phy int mask settings */
7cc4ab22 179 u8 mc_clkdis; /* clock disable register */
b872a8e1 180
b90120a9 181 spinlock_t audio_lock;
6bcf4953 182 struct mutex audio_mutex;
9aaf880e 183 unsigned int sample_rate;
b90120a9
RK		 184 unsigned int audio_cts;
185 unsigned int audio_n;
186 bool audio_enable;
0cd9d142 187
80e2f979
NA		 188 unsigned int reg_shift;
189 struct regmap *regm;
a7d555d2
RP		 190 void (*enable_audio)(struct dw_hdmi *hdmi);
191 void (*disable_audio)(struct dw_hdmi *hdmi);
e84b8d75
RK		 192
193 struct cec_notifier *cec_notifier;
9aaf880e
FE		 194};
195
aeac23bd
RK		 196#define HDMI_IH_PHY_STAT0_RX_SENSE \
197 (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \
198 HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3)
199
200#define HDMI_PHY_RX_SENSE \
201 (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \
202 HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3)
203
0cd9d142
AY		 204static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
205{
80e2f979 206 regmap_write(hdmi->regm, offset << hdmi->reg_shift, val);
0cd9d142
AY		 207}
208
209static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
210{
80e2f979
NA		 211 unsigned int val = 0;
212
213 regmap_read(hdmi->regm, offset << hdmi->reg_shift, &val);
214
215 return val;
0cd9d142
AY		 216}
217
b21f4b65 218static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
812bc615 219{
80e2f979 220 regmap_update_bits(hdmi->regm, reg << hdmi->reg_shift, mask, data);
812bc615
RK		 221}
222
b21f4b65 223static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
b5878339 224 u8 shift, u8 mask)
9aaf880e 225{
812bc615 226 hdmi_modb(hdmi, data << shift, mask, reg);
9aaf880e
FE		 227}
228
3efc2fa3
VZ		 229static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi)
230{
99d02ed5
DA		 231 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
232 HDMI_PHY_I2CM_INT_ADDR);
233
234 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
235 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
236 HDMI_PHY_I2CM_CTLINT_ADDR);
237
3efc2fa3
VZ		 238 /* Software reset */
239 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ);
240
241 /* Set Standard Mode speed (determined to be 100KHz on iMX6) */
242 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_DIV);
243
244 /* Set done, not acknowledged and arbitration interrupt polarities */
245 hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT);
246 hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL,
247 HDMI_I2CM_CTLINT);
248
249 /* Clear DONE and ERROR interrupts */
250 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
251 HDMI_IH_I2CM_STAT0);
252
253 /* Mute DONE and ERROR interrupts */
254 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
255 HDMI_IH_MUTE_I2CM_STAT0);
256}
257
50f9495e
DA		 258static bool dw_hdmi_i2c_unwedge(struct dw_hdmi *hdmi)
259{
260 /* If no unwedge state then give up */
0bd79f91 261 if (!hdmi->unwedge_state)
50f9495e
DA		 262 return false;
263
264 dev_info(hdmi->dev, "Attempting to unwedge stuck i2c bus\n");
265
266 /*
267 * This is a huge hack to workaround a problem where the dw_hdmi i2c
268 * bus could sometimes get wedged. Once wedged there doesn't appear
269 * to be any way to unwedge it (including the HDMI_I2CM_SOFTRSTZ)
270 * other than pulsing the SDA line.
271 *
272 * We appear to be able to pulse the SDA line (in the eyes of dw_hdmi)
273 * by:
274 * 1. Remux the pin as a GPIO output, driven low.
275 * 2. Wait a little while. 1 ms seems to work, but we'll do 10.
276 * 3. Immediately jump to remux the pin as dw_hdmi i2c again.
277 *
278 * At the moment of remuxing, the line will still be low due to its
279 * recent stint as an output, but then it will be pulled high by the
280 * (presumed) external pullup. dw_hdmi seems to see this as a rising
281 * edge and that seems to get it out of its jam.
282 *
283 * This wedging was only ever seen on one TV, and only on one of
284 * its HDMI ports. It happened when the TV was powered on while the
285 * device was plugged in. A scope trace shows the TV bringing both SDA
286 * and SCL low, then bringing them both back up at roughly the same
287 * time. Presumably this confuses dw_hdmi because it saw activity but
288 * no real STOP (maybe it thinks there's another master on the bus?).
289 * Giving it a clean rising edge of SDA while SCL is already high
290 * presumably makes dw_hdmi see a STOP which seems to bring dw_hdmi out
291 * of its stupor.
292 *
293 * Note that after coming back alive, transfers seem to immediately
294 * resume, so if we unwedge due to a timeout we should wait a little
295 * longer for our transfer to finish, since it might have just started
296 * now.
297 */
298 pinctrl_select_state(hdmi->pinctrl, hdmi->unwedge_state);
299 msleep(10);
300 pinctrl_select_state(hdmi->pinctrl, hdmi->default_state);
301
302 return true;
303}
304
305static int dw_hdmi_i2c_wait(struct dw_hdmi *hdmi)
306{
307 struct dw_hdmi_i2c *i2c = hdmi->i2c;
308 int stat;
309
310 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
311 if (!stat) {
312 /* If we can't unwedge, return timeout */
313 if (!dw_hdmi_i2c_unwedge(hdmi))
314 return -EAGAIN;
315
316 /* We tried to unwedge; give it another chance */
317 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
318 if (!stat)
319 return -EAGAIN;
320 }
321
322 /* Check for error condition on the bus */
323 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
324 return -EIO;
325
326 return 0;
327}
328
3efc2fa3
VZ		 329static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi,
330 unsigned char *buf, unsigned int length)
331{
332 struct dw_hdmi_i2c *i2c = hdmi->i2c;
50f9495e 333 int ret;
3efc2fa3
VZ		 334
335 if (!i2c->is_regaddr) {
336 dev_dbg(hdmi->dev, "set read register address to 0\n");
337 i2c->slave_reg = 0x00;
338 i2c->is_regaddr = true;
339 }
340
341 while (length--) {
342 reinit_completion(&i2c->cmp);
343
344 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
94bb4dc1
NY		 345 if (i2c->is_segment)
346 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT,
347 HDMI_I2CM_OPERATION);
348 else
349 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
350 HDMI_I2CM_OPERATION);
3efc2fa3 351
50f9495e
DA		 352 ret = dw_hdmi_i2c_wait(hdmi);
353 if (ret)
354 return ret;
3efc2fa3
VZ		 355
356 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI);
357 }
94bb4dc1 358 i2c->is_segment = false;
3efc2fa3
VZ		 359
360 return 0;
361}
362
363static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi,
364 unsigned char *buf, unsigned int length)
365{
366 struct dw_hdmi_i2c *i2c = hdmi->i2c;
50f9495e 367 int ret;
3efc2fa3
VZ		 368
369 if (!i2c->is_regaddr) {
370 /* Use the first write byte as register address */
371 i2c->slave_reg = buf[0];
372 length--;
373 buf++;
374 i2c->is_regaddr = true;
375 }
376
377 while (length--) {
378 reinit_completion(&i2c->cmp);
379
380 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO);
381 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
382 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE,
383 HDMI_I2CM_OPERATION);
384
50f9495e
DA		 385 ret = dw_hdmi_i2c_wait(hdmi);
386 if (ret)
387 return ret;
3efc2fa3
VZ		 388 }
389
390 return 0;
391}
392
393static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap,
394 struct i2c_msg *msgs, int num)
395{
396 struct dw_hdmi *hdmi = i2c_get_adapdata(adap);
397 struct dw_hdmi_i2c *i2c = hdmi->i2c;
398 u8 addr = msgs[0].addr;
399 int i, ret = 0;
400
401 dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr);
402
403 for (i = 0; i < num; i++) {
3efc2fa3
VZ		 404 if (msgs[i].len == 0) {
405 dev_dbg(hdmi->dev,
406 "unsupported transfer %d/%d, no data\n",
407 i + 1, num);
408 return -EOPNOTSUPP;
409 }
410 }
411
412 mutex_lock(&i2c->lock);
413
414 /* Unmute DONE and ERROR interrupts */
415 hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0);
416
417 /* Set slave device address taken from the first I2C message */
418 hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE);
419
420 /* Set slave device register address on transfer */
421 i2c->is_regaddr = false;
422
94bb4dc1
NY		 423 /* Set segment pointer for I2C extended read mode operation */
424 i2c->is_segment = false;
425
3efc2fa3
VZ		 426 for (i = 0; i < num; i++) {
427 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n",
428 i + 1, num, msgs[i].len, msgs[i].flags);
94bb4dc1
NY		 429 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) {
430 i2c->is_segment = true;
431 hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR);
432 hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR);
433 } else {
434 if (msgs[i].flags & I2C_M_RD)
435 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf,
436 msgs[i].len);
437 else
438 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf,
439 msgs[i].len);
440 }
3efc2fa3
VZ		 441 if (ret < 0)
442 break;
443 }
444
445 if (!ret)
446 ret = num;
447
448 /* Mute DONE and ERROR interrupts */
449 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
450 HDMI_IH_MUTE_I2CM_STAT0);
451
452 mutex_unlock(&i2c->lock);
453
454 return ret;
455}
456
457static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter)
458{
459 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
460}
461
462static const struct i2c_algorithm dw_hdmi_algorithm = {
463 .master_xfer = dw_hdmi_i2c_xfer,
464 .functionality = dw_hdmi_i2c_func,
465};
466
467static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi)
468{
469 struct i2c_adapter *adap;
470 struct dw_hdmi_i2c *i2c;
471 int ret;
472
473 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
474 if (!i2c)
475 return ERR_PTR(-ENOMEM);
476
477 mutex_init(&i2c->lock);
478 init_completion(&i2c->cmp);
479
480 adap = &i2c->adap;
481 adap->class = I2C_CLASS_DDC;
482 adap->owner = THIS_MODULE;
483 adap->dev.parent = hdmi->dev;
484 adap->algo = &dw_hdmi_algorithm;
485 strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name));
486 i2c_set_adapdata(adap, hdmi);
487
488 ret = i2c_add_adapter(adap);
489 if (ret) {
490 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
491 devm_kfree(hdmi->dev, i2c);
492 return ERR_PTR(ret);
493 }
494
495 hdmi->i2c = i2c;
496
497 dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
498
499 return adap;
500}
501
351e1354
RK		 502static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
503 unsigned int n)
9aaf880e 504{
622494a3
RK		 505 /* Must be set/cleared first */
506 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
9aaf880e
FE		 507
508 /* nshift factor = 0 */
812bc615 509 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
9aaf880e 510
fdbdcc83
NA		 511 /* Use automatic CTS generation mode when CTS is not set */
512 if (cts)
513 hdmi_writeb(hdmi, ((cts >> 16) &
514 HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
515 HDMI_AUD_CTS3_CTS_MANUAL,
516 HDMI_AUD_CTS3);
517 else
518 hdmi_writeb(hdmi, 0, HDMI_AUD_CTS3);
622494a3
RK		 519 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
520 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
521
522 hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
523 hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
524 hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
9aaf880e
FE		 525}
526
b195fbdb 527static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk)
9aaf880e
FE		 528{
529 unsigned int n = (128 * freq) / 1000;
d0c96d16
RK		 530 unsigned int mult = 1;
531
532 while (freq > 48000) {
533 mult *= 2;
534 freq /= 2;
535 }
9aaf880e
FE		 536
537 switch (freq) {
538 case 32000:
426701d0 539 if (pixel_clk == 25175000)
b195fbdb 540 n = 4576;
426701d0 541 else if (pixel_clk == 27027000)
b195fbdb 542 n = 4096;
426701d0 543 else if (pixel_clk == 74176000 || pixel_clk == 148352000)
9aaf880e
FE		 544 n = 11648;
545 else
546 n = 4096;
d0c96d16 547 n *= mult;
9aaf880e
FE		 548 break;
549
550 case 44100:
426701d0 551 if (pixel_clk == 25175000)
9aaf880e 552 n = 7007;
426701d0 553 else if (pixel_clk == 74176000)
9aaf880e 554 n = 17836;
426701d0 555 else if (pixel_clk == 148352000)
b195fbdb 556 n = 8918;
9aaf880e
FE		 557 else
558 n = 6272;
d0c96d16 559 n *= mult;
9aaf880e
FE		 560 break;
561
562 case 48000:
426701d0 563 if (pixel_clk == 25175000)
b195fbdb 564 n = 6864;
426701d0 565 else if (pixel_clk == 27027000)
b195fbdb 566 n = 6144;
426701d0 567 else if (pixel_clk == 74176000)
9aaf880e 568 n = 11648;
426701d0 569 else if (pixel_clk == 148352000)
b195fbdb 570 n = 5824;
9aaf880e
FE		 571 else
572 n = 6144;
d0c96d16 573 n *= mult;
9aaf880e
FE		 574 break;
575
576 default:
577 break;
578 }
579
580 return n;
581}
582
b21f4b65 583static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
b195fbdb 584 unsigned long pixel_clk, unsigned int sample_rate)
9aaf880e 585{
dfbdaf50 586 unsigned long ftdms = pixel_clk;
f879b38f 587 unsigned int n, cts;
fdbdcc83 588 u8 config3;
dfbdaf50 589 u64 tmp;
9aaf880e 590
b195fbdb 591 n = hdmi_compute_n(sample_rate, pixel_clk);
9aaf880e 592
fdbdcc83
NA		 593 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID);
594
595 /* Only compute CTS when using internal AHB audio */
596 if (config3 & HDMI_CONFIG3_AHBAUDDMA) {
597 /*
598 * Compute the CTS value from the N value. Note that CTS and N
599 * can be up to 20 bits in total, so we need 64-bit math. Also
600 * note that our TDMS clock is not fully accurate; it is
601 * accurate to kHz. This can introduce an unnecessary remainder
602 * in the calculation below, so we don't try to warn about that.
603 */
604 tmp = (u64)ftdms * n;
605 do_div(tmp, 128 * sample_rate);
606 cts = tmp;
607
608 dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
609 __func__, sample_rate,
610 ftdms / 1000000, (ftdms / 1000) % 1000,
611 n, cts);
612 } else {
613 cts = 0;
614 }
9aaf880e 615
b90120a9
RK		 616 spin_lock_irq(&hdmi->audio_lock);
617 hdmi->audio_n = n;
618 hdmi->audio_cts = cts;
619 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
620 spin_unlock_irq(&hdmi->audio_lock);
9aaf880e
FE		 621}
622
b21f4b65 623static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
9aaf880e 624{
6bcf4953 625 mutex_lock(&hdmi->audio_mutex);
b195fbdb 626 hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate);
6bcf4953 627 mutex_unlock(&hdmi->audio_mutex);
9aaf880e
FE		 628}
629
b21f4b65 630static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
9aaf880e 631{
6bcf4953 632 mutex_lock(&hdmi->audio_mutex);
ba9877e2 633 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock,
b195fbdb 634 hdmi->sample_rate);
6bcf4953 635 mutex_unlock(&hdmi->audio_mutex);
9aaf880e
FE		 636}
637
b5814fff
RK		 638void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
639{
640 mutex_lock(&hdmi->audio_mutex);
641 hdmi->sample_rate = rate;
ba9877e2 642 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock,
b195fbdb 643 hdmi->sample_rate);
b5814fff
RK		 644 mutex_unlock(&hdmi->audio_mutex);
645}
646EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate);
647
2a2a3d2f
JB		 648void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt)
649{
650 u8 layout;
651
652 mutex_lock(&hdmi->audio_mutex);
653
654 /*
655 * For >2 channel PCM audio, we need to select layout 1
656 * and set an appropriate channel map.
657 */
658 if (cnt > 2)
659 layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1;
660 else
661 layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0;
662
663 hdmi_modb(hdmi, layout, HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK,
664 HDMI_FC_AUDSCONF);
665
da5f5bc9
JB		 666 /* Set the audio infoframes channel count */
667 hdmi_modb(hdmi, (cnt - 1) << HDMI_FC_AUDICONF0_CC_OFFSET,
668 HDMI_FC_AUDICONF0_CC_MASK, HDMI_FC_AUDICONF0);
669
2a2a3d2f
JB		 670 mutex_unlock(&hdmi->audio_mutex);
671}
672EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_count);
673
674void dw_hdmi_set_channel_allocation(struct dw_hdmi *hdmi, unsigned int ca)
675{
676 mutex_lock(&hdmi->audio_mutex);
677
678 hdmi_writeb(hdmi, ca, HDMI_FC_AUDICONF2);
679
680 mutex_unlock(&hdmi->audio_mutex);
681}
682EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_allocation);
683
57fbc055
RP		 684static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi, bool enable)
685{
7cc4ab22
RK		 686 if (enable)
687 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE;
688 else
689 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_AUDCLK_DISABLE;
690 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
57fbc055
RP		 691}
692
a7d555d2
RP		 693static void dw_hdmi_ahb_audio_enable(struct dw_hdmi *hdmi)
694{
695 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
696}
697
698static void dw_hdmi_ahb_audio_disable(struct dw_hdmi *hdmi)
699{
700 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
701}
702
703static void dw_hdmi_i2s_audio_enable(struct dw_hdmi *hdmi)
704{
705 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
57fbc055
RP		 706 hdmi_enable_audio_clk(hdmi, true);
707}
708
709static void dw_hdmi_i2s_audio_disable(struct dw_hdmi *hdmi)
710{
711 hdmi_enable_audio_clk(hdmi, false);
a7d555d2
RP		 712}
713
b90120a9
RK		 714void dw_hdmi_audio_enable(struct dw_hdmi *hdmi)
715{
716 unsigned long flags;
717
718 spin_lock_irqsave(&hdmi->audio_lock, flags);
719 hdmi->audio_enable = true;
a7d555d2
RP		 720 if (hdmi->enable_audio)
721 hdmi->enable_audio(hdmi);
b90120a9
RK		 722 spin_unlock_irqrestore(&hdmi->audio_lock, flags);
723}
724EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable);
725
726void dw_hdmi_audio_disable(struct dw_hdmi *hdmi)
727{
728 unsigned long flags;
729
730 spin_lock_irqsave(&hdmi->audio_lock, flags);
731 hdmi->audio_enable = false;
a7d555d2
RP		 732 if (hdmi->disable_audio)
733 hdmi->disable_audio(hdmi);
b90120a9
RK		 734 spin_unlock_irqrestore(&hdmi->audio_lock, flags);
735}
736EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable);
737
def23aa7
NA		 738static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format)
739{
740 switch (bus_format) {
741 case MEDIA_BUS_FMT_RGB888_1X24:
742 case MEDIA_BUS_FMT_RGB101010_1X30:
743 case MEDIA_BUS_FMT_RGB121212_1X36:
744 case MEDIA_BUS_FMT_RGB161616_1X48:
745 return true;
746
747 default:
748 return false;
749 }
750}
751
752static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format)
753{
754 switch (bus_format) {
755 case MEDIA_BUS_FMT_YUV8_1X24:
756 case MEDIA_BUS_FMT_YUV10_1X30:
757 case MEDIA_BUS_FMT_YUV12_1X36:
758 case MEDIA_BUS_FMT_YUV16_1X48:
759 return true;
760
761 default:
762 return false;
763 }
764}
765
766static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format)
767{
768 switch (bus_format) {
769 case MEDIA_BUS_FMT_UYVY8_1X16:
770 case MEDIA_BUS_FMT_UYVY10_1X20:
771 case MEDIA_BUS_FMT_UYVY12_1X24:
772 return true;
773
774 default:
775 return false;
776 }
777}
778
ba9877e2
NA		 779static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format)
780{
781 switch (bus_format) {
782 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
783 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
784 case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
785 case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
786 return true;
787
788 default:
789 return false;
790 }
791}
792
def23aa7
NA		 793static int hdmi_bus_fmt_color_depth(unsigned int bus_format)
794{
795 switch (bus_format) {
796 case MEDIA_BUS_FMT_RGB888_1X24:
797 case MEDIA_BUS_FMT_YUV8_1X24:
798 case MEDIA_BUS_FMT_UYVY8_1X16:
799 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
800 return 8;
801
802 case MEDIA_BUS_FMT_RGB101010_1X30:
803 case MEDIA_BUS_FMT_YUV10_1X30:
804 case MEDIA_BUS_FMT_UYVY10_1X20:
805 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
806 return 10;
807
808 case MEDIA_BUS_FMT_RGB121212_1X36:
809 case MEDIA_BUS_FMT_YUV12_1X36:
810 case MEDIA_BUS_FMT_UYVY12_1X24:
811 case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
812 return 12;
813
814 case MEDIA_BUS_FMT_RGB161616_1X48:
815 case MEDIA_BUS_FMT_YUV16_1X48:
816 case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
817 return 16;
818
819 default:
820 return 0;
821 }
822}
823
9aaf880e
FE		 824/*
825 * this submodule is responsible for the video data synchronization.
826 * for example, for RGB 4:4:4 input, the data map is defined as
827 * pin{47~40} <==> R[7:0]
828 * pin{31~24} <==> G[7:0]
829 * pin{15~8} <==> B[7:0]
830 */
b21f4b65 831static void hdmi_video_sample(struct dw_hdmi *hdmi)
9aaf880e
FE		 832{
833 int color_format = 0;
834 u8 val;
835
def23aa7
NA		 836 switch (hdmi->hdmi_data.enc_in_bus_format) {
837 case MEDIA_BUS_FMT_RGB888_1X24:
838 color_format = 0x01;
839 break;
840 case MEDIA_BUS_FMT_RGB101010_1X30:
841 color_format = 0x03;
842 break;
843 case MEDIA_BUS_FMT_RGB121212_1X36:
844 color_format = 0x05;
845 break;
846 case MEDIA_BUS_FMT_RGB161616_1X48:
847 color_format = 0x07;
848 break;
849
850 case MEDIA_BUS_FMT_YUV8_1X24:
851 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
852 color_format = 0x09;
853 break;
854 case MEDIA_BUS_FMT_YUV10_1X30:
855 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
856 color_format = 0x0B;
857 break;
858 case MEDIA_BUS_FMT_YUV12_1X36:
859 case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
860 color_format = 0x0D;
861 break;
862 case MEDIA_BUS_FMT_YUV16_1X48:
863 case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
864 color_format = 0x0F;
865 break;
866
867 case MEDIA_BUS_FMT_UYVY8_1X16:
868 color_format = 0x16;
869 break;
870 case MEDIA_BUS_FMT_UYVY10_1X20:
871 color_format = 0x14;
872 break;
873 case MEDIA_BUS_FMT_UYVY12_1X24:
874 color_format = 0x12;
875 break;
876
877 default:
878 return;
9aaf880e
FE		 879 }
880
881 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
882 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
883 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
884 hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
885
886 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
887 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
888 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
889 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
890 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
891 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
892 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
893 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
894 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
895 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
896 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
897}
898
b21f4b65 899static int is_color_space_conversion(struct dw_hdmi *hdmi)
9aaf880e 900{
def23aa7 901 return hdmi->hdmi_data.enc_in_bus_format != hdmi->hdmi_data.enc_out_bus_format;
9aaf880e
FE		 902}
903
b21f4b65 904static int is_color_space_decimation(struct dw_hdmi *hdmi)
9aaf880e 905{
def23aa7 906 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
ba92b225 907 return 0;
def23aa7
NA		 908
909 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) ||
910 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format))
ba92b225 911 return 1;
def23aa7 912
ba92b225 913 return 0;
9aaf880e
FE		 914}
915
b21f4b65 916static int is_color_space_interpolation(struct dw_hdmi *hdmi)
9aaf880e 917{
def23aa7 918 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format))
ba92b225 919 return 0;
def23aa7
NA		 920
921 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
922 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
ba92b225 923 return 1;
def23aa7 924
ba92b225 925 return 0;
9aaf880e
FE		 926}
927
b21f4b65 928static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
9aaf880e
FE		 929{
930 const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
c082f9d7 931 unsigned i;
9aaf880e 932 u32 csc_scale = 1;
9aaf880e
FE		 933
934 if (is_color_space_conversion(hdmi)) {
def23aa7
NA		 935 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
936 if (hdmi->hdmi_data.enc_out_encoding ==
937 V4L2_YCBCR_ENC_601)
9aaf880e
FE		 938 csc_coeff = &csc_coeff_rgb_out_eitu601;
939 else
940 csc_coeff = &csc_coeff_rgb_out_eitu709;
def23aa7
NA		 941 } else if (hdmi_bus_fmt_is_rgb(
942 hdmi->hdmi_data.enc_in_bus_format)) {
943 if (hdmi->hdmi_data.enc_out_encoding ==
944 V4L2_YCBCR_ENC_601)
9aaf880e
FE		 945 csc_coeff = &csc_coeff_rgb_in_eitu601;
946 else
947 csc_coeff = &csc_coeff_rgb_in_eitu709;
948 csc_scale = 0;
949 }
950 }
951
c082f9d7
RK		 952 /* The CSC registers are sequential, alternating MSB then LSB */
953 for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
954 u16 coeff_a = (*csc_coeff)[0][i];
955 u16 coeff_b = (*csc_coeff)[1][i];
956 u16 coeff_c = (*csc_coeff)[2][i];
957
b5878339 958 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
c082f9d7
RK		 959 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
960 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
961 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
b5878339 962 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
c082f9d7
RK		 963 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
964 }
9aaf880e 965
812bc615
RK		 966 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
967 HDMI_CSC_SCALE);
9aaf880e
FE		 968}
969
b21f4b65 970static void hdmi_video_csc(struct dw_hdmi *hdmi)
9aaf880e
FE		 971{
972 int color_depth = 0;
973 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
974 int decimation = 0;
9aaf880e
FE		 975
976 /* YCC422 interpolation to 444 mode */
977 if (is_color_space_interpolation(hdmi))
978 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
979 else if (is_color_space_decimation(hdmi))
980 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
981
def23aa7
NA		 982 switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) {
983 case 8:
9aaf880e 984 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
def23aa7
NA		 985 break;
986 case 10:
9aaf880e 987 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
def23aa7
NA		 988 break;
989 case 12:
9aaf880e 990 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
def23aa7
NA		 991 break;
992 case 16:
9aaf880e 993 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
def23aa7
NA		 994 break;
995
996 default:
9aaf880e 997 return;
def23aa7 998 }
9aaf880e
FE		 999
1000 /* Configure the CSC registers */
1001 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
812bc615
RK		 1002 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
1003 HDMI_CSC_SCALE);
9aaf880e 1004
b21f4b65 1005 dw_hdmi_update_csc_coeffs(hdmi);
9aaf880e
FE		 1006}
1007
1008/*
1009 * HDMI video packetizer is used to packetize the data.
1010 * for example, if input is YCC422 mode or repeater is used,
1011 * data should be repacked this module can be bypassed.
1012 */
b21f4b65 1013static void hdmi_video_packetize(struct dw_hdmi *hdmi)
9aaf880e
FE		 1014{
1015 unsigned int color_depth = 0;
1016 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
1017 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
1018 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
bebdf664 1019 u8 val, vp_conf;
9aaf880e 1020
def23aa7 1021 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
ba9877e2
NA		 1022 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format) ||
1023 hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) {
def23aa7
NA		 1024 switch (hdmi_bus_fmt_color_depth(
1025 hdmi->hdmi_data.enc_out_bus_format)) {
1026 case 8:
9aaf880e
FE		 1027 color_depth = 4;
1028 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
def23aa7
NA		 1029 break;
1030 case 10:
9aaf880e 1031 color_depth = 5;
def23aa7
NA		 1032 break;
1033 case 12:
9aaf880e 1034 color_depth = 6;
def23aa7
NA		 1035 break;
1036 case 16:
9aaf880e 1037 color_depth = 7;
def23aa7
NA		 1038 break;
1039 default:
1040 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
b5878339 1041 }
def23aa7
NA		 1042 } else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) {
1043 switch (hdmi_bus_fmt_color_depth(
1044 hdmi->hdmi_data.enc_out_bus_format)) {
1045 case 0:
1046 case 8:
9aaf880e 1047 remap_size = HDMI_VP_REMAP_YCC422_16bit;
def23aa7
NA		 1048 break;
1049 case 10:
9aaf880e 1050 remap_size = HDMI_VP_REMAP_YCC422_20bit;
def23aa7
NA		 1051 break;
1052 case 12:
9aaf880e 1053 remap_size = HDMI_VP_REMAP_YCC422_24bit;
def23aa7
NA		 1054 break;
1055
1056 default:
9aaf880e 1057 return;
def23aa7 1058 }
9aaf880e 1059 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
b5878339 1060 } else {
9aaf880e 1061 return;
b5878339 1062 }
9aaf880e
FE		 1063
1064 /* set the packetizer registers */
1065 val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
1066 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
1067 ((hdmi_data->pix_repet_factor <<
1068 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
1069 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
1070 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
1071
812bc615
RK		 1072 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
1073 HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
9aaf880e
FE		 1074
1075 /* Data from pixel repeater block */
1076 if (hdmi_data->pix_repet_factor > 1) {
bebdf664
RK		 1077 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
1078 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
9aaf880e 1079 } else { /* data from packetizer block */
bebdf664
RK		 1080 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
1081 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
9aaf880e
FE		 1082 }
1083
bebdf664
RK		 1084 hdmi_modb(hdmi, vp_conf,
1085 HDMI_VP_CONF_PR_EN_MASK |
1086 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
1087
812bc615
RK		 1088 hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
1089 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
9aaf880e
FE		 1090
1091 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
1092
1093 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
bebdf664
RK		 1094 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
1095 HDMI_VP_CONF_PP_EN_ENABLE |
1096 HDMI_VP_CONF_YCC422_EN_DISABLE;
9aaf880e 1097 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
bebdf664
RK		 1098 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
1099 HDMI_VP_CONF_PP_EN_DISABLE |
1100 HDMI_VP_CONF_YCC422_EN_ENABLE;
9aaf880e 1101 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
bebdf664
RK		 1102 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
1103 HDMI_VP_CONF_PP_EN_DISABLE |
1104 HDMI_VP_CONF_YCC422_EN_DISABLE;
9aaf880e
FE		 1105 } else {
1106 return;
1107 }
1108
bebdf664
RK		 1109 hdmi_modb(hdmi, vp_conf,
1110 HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
1111 HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
1112
812bc615
RK		 1113 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
1114 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
1115 HDMI_VP_STUFF_PP_STUFFING_MASK |
1116 HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
9aaf880e 1117
812bc615
RK		 1118 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
1119 HDMI_VP_CONF);
9aaf880e
FE		 1120}
1121
f1585f6e
LP		 1122/* -----------------------------------------------------------------------------
1123 * Synopsys PHY Handling
1124 */
1125
b21f4b65 1126static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
b5878339 1127 unsigned char bit)
9aaf880e 1128{
812bc615
RK		 1129 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
1130 HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
9aaf880e
FE		 1131}
1132
b21f4b65 1133static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
9aaf880e 1134{
a4d3b8b0
AY		 1135 u32 val;
1136
1137 while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
9aaf880e
FE		 1138 if (msec-- == 0)
1139 return false;
0e6bcf3a 1140 udelay(1000);
9aaf880e 1141 }
a4d3b8b0
AY		 1142 hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
1143
9aaf880e
FE		 1144 return true;
1145}
1146
2ef9dfed
KB		 1147void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
1148 unsigned char addr)
9aaf880e
FE		 1149{
1150 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
1151 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
1152 hdmi_writeb(hdmi, (unsigned char)(data >> 8),
b5878339 1153 HDMI_PHY_I2CM_DATAO_1_ADDR);
9aaf880e 1154 hdmi_writeb(hdmi, (unsigned char)(data >> 0),
b5878339 1155 HDMI_PHY_I2CM_DATAO_0_ADDR);
9aaf880e 1156 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
b5878339 1157 HDMI_PHY_I2CM_OPERATION_ADDR);
9aaf880e
FE		 1158 hdmi_phy_wait_i2c_done(hdmi, 1000);
1159}
2ef9dfed 1160EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_write);
9aaf880e 1161
836f90f9
NA		 1162/* Filter out invalid setups to avoid configuring SCDC and scrambling */
1163static bool dw_hdmi_support_scdc(struct dw_hdmi *hdmi)
1164{
1165 struct drm_display_info *display = &hdmi->connector.display_info;
1166
1167 /* Completely disable SCDC support for older controllers */
1168 if (hdmi->version < 0x200a)
1169 return false;
1170
c4cba44e
JK		 1171 /* Disable if no DDC bus */
1172 if (!hdmi->ddc)
1173 return false;
1174
836f90f9
NA		 1175 /* Disable if SCDC is not supported, or if an HF-VSDB block is absent */
1176 if (!display->hdmi.scdc.supported ||
1177 !display->hdmi.scdc.scrambling.supported)
1178 return false;
1179
1180 /*
1181 * Disable if display only support low TMDS rates and scrambling
1182 * for low rates is not supported either
1183 */
1184 if (!display->hdmi.scdc.scrambling.low_rates &&
1185 display->max_tmds_clock <= 340000)
1186 return false;
1187
1188 return true;
1189}
1190
264fce6c
NA		 1191/*
1192 * HDMI2.0 Specifies the following procedure for High TMDS Bit Rates:
1193 * - The Source shall suspend transmission of the TMDS clock and data
1194 * - The Source shall write to the TMDS_Bit_Clock_Ratio bit to change it
1195 * from a 0 to a 1 or from a 1 to a 0
1196 * - The Source shall allow a minimum of 1 ms and a maximum of 100 ms from
1197 * the time the TMDS_Bit_Clock_Ratio bit is written until resuming
1198 * transmission of TMDS clock and data
1199 *
1200 * To respect the 100ms maximum delay, the dw_hdmi_set_high_tmds_clock_ratio()
1201 * helper should called right before enabling the TMDS Clock and Data in
1202 * the PHY configuration callback.
1203 */
1204void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi)
1205{
ba9877e2 1206 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock;
264fce6c
NA		 1207
1208 /* Control for TMDS Bit Period/TMDS Clock-Period Ratio */
836f90f9 1209 if (dw_hdmi_support_scdc(hdmi)) {
264fce6c
NA		 1210 if (mtmdsclock > HDMI14_MAX_TMDSCLK)
1211 drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 1);
1212 else
1213 drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 0);
1214 }
1215}
1216EXPORT_SYMBOL_GPL(dw_hdmi_set_high_tmds_clock_ratio);
1217
2fada109 1218static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable)
9aaf880e 1219{
2fada109 1220 hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0,
9aaf880e
FE		 1221 HDMI_PHY_CONF0_PDZ_OFFSET,
1222 HDMI_PHY_CONF0_PDZ_MASK);
1223}
1224
b21f4b65 1225static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
9aaf880e
FE		 1226{
1227 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1228 HDMI_PHY_CONF0_ENTMDS_OFFSET,
1229 HDMI_PHY_CONF0_ENTMDS_MASK);
1230}
1231
f4104e8f 1232static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable)
d346c14e
AY		 1233{
1234 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
f4104e8f
LP		 1235 HDMI_PHY_CONF0_SVSRET_OFFSET,
1236 HDMI_PHY_CONF0_SVSRET_MASK);
d346c14e
AY		 1237}
1238
5765916a 1239void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
9aaf880e
FE		 1240{
1241 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1242 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
1243 HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
1244}
5765916a 1245EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_pddq);
9aaf880e 1246
5765916a 1247void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
9aaf880e
FE		 1248{
1249 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1250 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
1251 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
1252}
5765916a 1253EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_txpwron);
9aaf880e 1254
b21f4b65 1255static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
9aaf880e
FE		 1256{
1257 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1258 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
1259 HDMI_PHY_CONF0_SELDATAENPOL_MASK);
1260}
1261
b21f4b65 1262static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
9aaf880e
FE		 1263{
1264 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1265 HDMI_PHY_CONF0_SELDIPIF_OFFSET,
1266 HDMI_PHY_CONF0_SELDIPIF_MASK);
1267}
1268
5765916a
JS		 1269void dw_hdmi_phy_reset(struct dw_hdmi *hdmi)
1270{
1271 /* PHY reset. The reset signal is active high on Gen2 PHYs. */
1272 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ);
1273 hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ);
1274}
1275EXPORT_SYMBOL_GPL(dw_hdmi_phy_reset);
1276
1277void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address)
1278{
1279 hdmi_phy_test_clear(hdmi, 1);
1280 hdmi_writeb(hdmi, address, HDMI_PHY_I2CM_SLAVE_ADDR);
1281 hdmi_phy_test_clear(hdmi, 0);
1282}
1283EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_set_addr);
1284
b0e583e5
LP		 1285static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi)
1286{
f1585f6e 1287 const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
b0e583e5
LP		 1288 unsigned int i;
1289 u16 val;
1290
1291 if (phy->gen == 1) {
1292 dw_hdmi_phy_enable_tmds(hdmi, 0);
1293 dw_hdmi_phy_enable_powerdown(hdmi, true);
1294 return;
1295 }
1296
1297 dw_hdmi_phy_gen2_txpwron(hdmi, 0);
1298
1299 /*
1300 * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went
1301 * to low power mode.
1302 */
1303 for (i = 0; i < 5; ++i) {
1304 val = hdmi_readb(hdmi, HDMI_PHY_STAT0);
1305 if (!(val & HDMI_PHY_TX_PHY_LOCK))
1306 break;
1307
1308 usleep_range(1000, 2000);
1309 }
1310
1311 if (val & HDMI_PHY_TX_PHY_LOCK)
1312 dev_warn(hdmi->dev, "PHY failed to power down\n");
1313 else
1314 dev_dbg(hdmi->dev, "PHY powered down in %u iterations\n", i);
1315
1316 dw_hdmi_phy_gen2_pddq(hdmi, 1);
1317}
1318
181e0ef0
LP		 1319static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi)
1320{
f1585f6e 1321 const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
181e0ef0
LP		 1322 unsigned int i;
1323 u8 val;
1324
1325 if (phy->gen == 1) {
1326 dw_hdmi_phy_enable_powerdown(hdmi, false);
1327
1328 /* Toggle TMDS enable. */
1329 dw_hdmi_phy_enable_tmds(hdmi, 0);
1330 dw_hdmi_phy_enable_tmds(hdmi, 1);
1331 return 0;
1332 }
1333
1334 dw_hdmi_phy_gen2_txpwron(hdmi, 1);
1335 dw_hdmi_phy_gen2_pddq(hdmi, 0);
1336
1337 /* Wait for PHY PLL lock */
1338 for (i = 0; i < 5; ++i) {
1339 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
1340 if (val)
1341 break;
1342
1343 usleep_range(1000, 2000);
1344 }
1345
1346 if (!val) {
1347 dev_err(hdmi->dev, "PHY PLL failed to lock\n");
1348 return -ETIMEDOUT;
1349 }
1350
1351 dev_dbg(hdmi->dev, "PHY PLL locked %u iterations\n", i);
1352 return 0;
1353}
1354
2ef9dfed
KB		 1355/*
1356 * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available
1357 * information the DWC MHL PHY has the same register layout and is thus also
1358 * supported by this function.
1359 */
1360static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi,
1361 const struct dw_hdmi_plat_data *pdata,
1362 unsigned long mpixelclock)
9aaf880e 1363{
39cc1535
RK		 1364 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
1365 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
1366 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
9aaf880e 1367
ba9877e2
NA		 1368 /* TOFIX Will need 420 specific PHY configuration tables */
1369
39cc1535
RK		 1370 /* PLL/MPLL Cfg - always match on final entry */
1371 for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
2ef9dfed 1372 if (mpixelclock <= mpll_config->mpixelclock)
39cc1535
RK		 1373 break;
1374
1375 for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
2ef9dfed 1376 if (mpixelclock <= curr_ctrl->mpixelclock)
39cc1535
RK		 1377 break;
1378
1379 for (; phy_config->mpixelclock != ~0UL; phy_config++)
2ef9dfed 1380 if (mpixelclock <= phy_config->mpixelclock)
39cc1535
RK		 1381 break;
1382
1383 if (mpll_config->mpixelclock == ~0UL ||
1384 curr_ctrl->mpixelclock == ~0UL ||
2ef9dfed 1385 phy_config->mpixelclock == ~0UL)
39cc1535 1386 return -EINVAL;
2ef9dfed
KB		 1387
1388 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce,
1389 HDMI_3D_TX_PHY_CPCE_CTRL);
1390 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp,
1391 HDMI_3D_TX_PHY_GMPCTRL);
1392 dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0],
1393 HDMI_3D_TX_PHY_CURRCTRL);
1394
1395 dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL);
1396 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK,
1397 HDMI_3D_TX_PHY_MSM_CTRL);
1398
1399 dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM);
1400 dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr,
1401 HDMI_3D_TX_PHY_CKSYMTXCTRL);
1402 dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr,
1403 HDMI_3D_TX_PHY_VLEVCTRL);
1404
1405 /* Override and disable clock termination. */
1406 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE,
1407 HDMI_3D_TX_PHY_CKCALCTRL);
1408
1409 return 0;
1410}
1411
1412static int hdmi_phy_configure(struct dw_hdmi *hdmi)
1413{
1414 const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1415 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
1416 unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock;
ba9877e2 1417 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock;
2ef9dfed 1418 int ret;
39cc1535 1419
b0e583e5 1420 dw_hdmi_phy_power_off(hdmi);
9aaf880e 1421
264fce6c
NA		 1422 dw_hdmi_set_high_tmds_clock_ratio(hdmi);
1423
2668db37 1424 /* Leave low power consumption mode by asserting SVSRET. */
f1585f6e 1425 if (phy->has_svsret)
2668db37
LP		 1426 dw_hdmi_phy_enable_svsret(hdmi, 1);
1427
5765916a 1428 dw_hdmi_phy_reset(hdmi);
9aaf880e
FE		 1429
1430 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
1431
5765916a 1432 dw_hdmi_phy_i2c_set_addr(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2);
9aaf880e 1433
2ef9dfed
KB		 1434 /* Write to the PHY as configured by the platform */
1435 if (pdata->configure_phy)
1436 ret = pdata->configure_phy(hdmi, pdata, mpixelclock);
1437 else
1438 ret = phy->configure(hdmi, pdata, mpixelclock);
1439 if (ret) {
1440 dev_err(hdmi->dev, "PHY configuration failed (clock %lu)\n",
1441 mpixelclock);
1442 return ret;
1443 }
9aaf880e 1444
264fce6c 1445 /* Wait for resuming transmission of TMDS clock and data */
ba9877e2 1446 if (mtmdsclock > HDMI14_MAX_TMDSCLK)
264fce6c
NA		 1447 msleep(100);
1448
181e0ef0 1449 return dw_hdmi_phy_power_on(hdmi);
9aaf880e
FE		 1450}
1451
f1585f6e
LP		 1452static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data,
1453 struct drm_display_mode *mode)
9aaf880e
FE		 1454{
1455 int i, ret;
9aaf880e
FE		 1456
1457 /* HDMI Phy spec says to do the phy initialization sequence twice */
1458 for (i = 0; i < 2; i++) {
b21f4b65
AY		 1459 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
1460 dw_hdmi_phy_sel_interface_control(hdmi, 0);
9aaf880e 1461
8b9e1c0d 1462 ret = hdmi_phy_configure(hdmi);
9aaf880e
FE		 1463 if (ret)
1464 return ret;
1465 }
1466
9aaf880e
FE		 1467 return 0;
1468}
1469
f1585f6e
LP		 1470static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data)
1471{
1472 dw_hdmi_phy_power_off(hdmi);
1473}
1474
5765916a
JS		 1475enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi,
1476 void *data)
f1585f6e
LP		 1477{
1478 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1479 connector_status_connected : connector_status_disconnected;
1480}
5765916a 1481EXPORT_SYMBOL_GPL(dw_hdmi_phy_read_hpd);
f1585f6e 1482
5765916a
JS		 1483void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data,
1484 bool force, bool disabled, bool rxsense)
386d3299
NA		 1485{
1486 u8 old_mask = hdmi->phy_mask;
1487
1488 if (force || disabled || !rxsense)
1489 hdmi->phy_mask |= HDMI_PHY_RX_SENSE;
1490 else
1491 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE;
1492
1493 if (old_mask != hdmi->phy_mask)
1494 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1495}
5765916a 1496EXPORT_SYMBOL_GPL(dw_hdmi_phy_update_hpd);
386d3299 1497
5765916a 1498void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data)
386d3299
NA		 1499{
1500 /*
1501 * Configure the PHY RX SENSE and HPD interrupts polarities and clear
1502 * any pending interrupt.
1503 */
1504 hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0);
1505 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1506 HDMI_IH_PHY_STAT0);
1507
1508 /* Enable cable hot plug irq. */
1509 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1510
1511 /* Clear and unmute interrupts. */
1512 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1513 HDMI_IH_PHY_STAT0);
1514 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
1515 HDMI_IH_MUTE_PHY_STAT0);
1516}
5765916a 1517EXPORT_SYMBOL_GPL(dw_hdmi_phy_setup_hpd);
386d3299 1518
f1585f6e
LP		 1519static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = {
1520 .init = dw_hdmi_phy_init,
1521 .disable = dw_hdmi_phy_disable,
1522 .read_hpd = dw_hdmi_phy_read_hpd,
386d3299
NA		 1523 .update_hpd = dw_hdmi_phy_update_hpd,
1524 .setup_hpd = dw_hdmi_phy_setup_hpd,
f1585f6e
LP		 1525};
1526
1527/* -----------------------------------------------------------------------------
1528 * HDMI TX Setup
1529 */
1530
b21f4b65 1531static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
9aaf880e 1532{
812bc615 1533 u8 de;
9aaf880e
FE		 1534
1535 if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
1536 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
1537 else
1538 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
1539
1540 /* disable rx detect */
812bc615
RK		 1541 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
1542 HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
9aaf880e 1543
812bc615 1544 hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
9aaf880e 1545
812bc615
RK		 1546 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
1547 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
9aaf880e
FE		 1548}
1549
d4ac4cb6 1550static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
9aaf880e 1551{
d4ac4cb6
RK		 1552 struct hdmi_avi_infoframe frame;
1553 u8 val;
9aaf880e 1554
d4ac4cb6 1555 /* Initialise info frame from DRM mode */
13d0add3
VS		 1556 drm_hdmi_avi_infoframe_from_display_mode(&frame,
1557 &hdmi->connector, mode);
9aaf880e 1558
def23aa7 1559 if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
d4ac4cb6 1560 frame.colorspace = HDMI_COLORSPACE_YUV444;
def23aa7 1561 else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
d4ac4cb6 1562 frame.colorspace = HDMI_COLORSPACE_YUV422;
ba9877e2
NA		 1563 else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
1564 frame.colorspace = HDMI_COLORSPACE_YUV420;
9aaf880e 1565 else
d4ac4cb6 1566 frame.colorspace = HDMI_COLORSPACE_RGB;
9aaf880e
FE		 1567
1568 /* Set up colorimetry */
def23aa7
NA		 1569 switch (hdmi->hdmi_data.enc_out_encoding) {
1570 case V4L2_YCBCR_ENC_601:
1571 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601)
1572 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1573 else
1574 frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
1575 frame.extended_colorimetry =
d4ac4cb6 1576 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
f40d6560 1577 break;
def23aa7
NA		 1578 case V4L2_YCBCR_ENC_709:
1579 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709)
1580 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1581 else
1582 frame.colorimetry = HDMI_COLORIMETRY_ITU_709;
1583 frame.extended_colorimetry =
d4ac4cb6 1584 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
def23aa7
NA		 1585 break;
1586 default: /* Carries no data */
1587 frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
1588 frame.extended_colorimetry =
1589 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1590 break;
9aaf880e
FE		 1591 }
1592
d4ac4cb6
RK		 1593 frame.scan_mode = HDMI_SCAN_MODE_NONE;
1594
1595 /*
1596 * The Designware IP uses a different byte format from standard
1597 * AVI info frames, though generally the bits are in the correct
1598 * bytes.
1599 */
1600
1601 /*
b0118e7d
JA		 1602 * AVI data byte 1 differences: Colorspace in bits 0,1 rather than 5,6,
1603 * scan info in bits 4,5 rather than 0,1 and active aspect present in
1604 * bit 6 rather than 4.
d4ac4cb6 1605 */
b0118e7d 1606 val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 3);
d4ac4cb6
RK		 1607 if (frame.active_aspect & 15)
1608 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT;
1609 if (frame.top_bar || frame.bottom_bar)
1610 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR;
1611 if (frame.left_bar || frame.right_bar)
1612 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR;
1613 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
1614
1615 /* AVI data byte 2 differences: none */
1616 val = ((frame.colorimetry & 0x3) << 6) |
1617 ((frame.picture_aspect & 0x3) << 4) |
1618 (frame.active_aspect & 0xf);
9aaf880e
FE		 1619 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
1620
d4ac4cb6
RK		 1621 /* AVI data byte 3 differences: none */
1622 val = ((frame.extended_colorimetry & 0x7) << 4) |
1623 ((frame.quantization_range & 0x3) << 2) |
1624 (frame.nups & 0x3);
1625 if (frame.itc)
1626 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID;
9aaf880e
FE		 1627 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
1628
d4ac4cb6
RK		 1629 /* AVI data byte 4 differences: none */
1630 val = frame.video_code & 0x7f;
1631 hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
9aaf880e
FE		 1632
1633 /* AVI Data Byte 5- set up input and output pixel repetition */
1634 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
1635 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
1636 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
1637 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
1638 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
1639 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
1640 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
1641
d4ac4cb6
RK		 1642 /*
1643 * AVI data byte 5 differences: content type in 0,1 rather than 4,5,
1644 * ycc range in bits 2,3 rather than 6,7
1645 */
1646 val = ((frame.ycc_quantization_range & 0x3) << 2) |
1647 (frame.content_type & 0x3);
9aaf880e
FE		 1648 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1649
1650 /* AVI Data Bytes 6-13 */
d4ac4cb6
RK		 1651 hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);
1652 hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1);
1653 hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);
1654 hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1);
1655 hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);
1656 hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1);
1657 hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);
1658 hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
9aaf880e
FE		 1659}
1660
9aa1eca0
NY		 1661static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi,
1662 struct drm_display_mode *mode)
1663{
1664 struct hdmi_vendor_infoframe frame;
1665 u8 buffer[10];
1666 ssize_t err;
1667
f1781e9b
VS		 1668 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame,
1669 &hdmi->connector,
1670 mode);
9aa1eca0
NY		 1671 if (err < 0)
1672 /*
1673 * Going into that statement does not means vendor infoframe
1674 * fails. It just informed us that vendor infoframe is not
1675 * needed for the selected mode. Only 4k or stereoscopic 3D
1676 * mode requires vendor infoframe. So just simply return.
1677 */
1678 return;
1679
1680 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
1681 if (err < 0) {
1682 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n",
1683 err);
1684 return;
1685 }
1686 hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
1687 HDMI_FC_DATAUTO0_VSD_MASK);
1688
1689 /* Set the length of HDMI vendor specific InfoFrame payload */
1690 hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE);
1691
1692 /* Set 24bit IEEE Registration Identifier */
1693 hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0);
1694 hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1);
1695 hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2);
1696
1697 /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */
1698 hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0);
1699 hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1);
1700
1701 if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF)
1702 hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2);
1703
1704 /* Packet frame interpolation */
1705 hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1);
1706
1707 /* Auto packets per frame and line spacing */
1708 hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2);
1709
1710 /* Configures the Frame Composer On RDRB mode */
1711 hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
1712 HDMI_FC_DATAUTO0_VSD_MASK);
1713}
1714
b21f4b65 1715static void hdmi_av_composer(struct dw_hdmi *hdmi,
9aaf880e
FE		 1716 const struct drm_display_mode *mode)
1717{
264fce6c
NA		 1718 u8 inv_val, bytes;
1719 struct drm_hdmi_info *hdmi_info = &hdmi->connector.display_info.hdmi;
9aaf880e
FE		 1720 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1721 int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
ba9877e2 1722 unsigned int vdisplay, hdisplay;
9aaf880e 1723
ba9877e2 1724 vmode->mtmdsclock = vmode->mpixelclock = mode->clock * 1000;
9aaf880e
FE		 1725
1726 dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1727
ba9877e2
NA		 1728 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
1729 vmode->mtmdsclock /= 2;
1730
9aaf880e 1731 /* Set up HDMI_FC_INVIDCONF */
264fce6c 1732 inv_val = (hdmi->hdmi_data.hdcp_enable ||
836f90f9
NA		 1733 (dw_hdmi_support_scdc(hdmi) &&
1734 (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK ||
1735 hdmi_info->scdc.scrambling.low_rates)) ?
9aaf880e
FE		 1736 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1737 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1738
b91eee8c 1739 inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
9aaf880e 1740 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
b91eee8c 1741 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW;
9aaf880e 1742
b91eee8c 1743 inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
9aaf880e 1744 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
b91eee8c 1745 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW;
9aaf880e
FE		 1746
1747 inv_val |= (vmode->mdataenablepolarity ?
1748 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1749 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1750
1751 if (hdmi->vic == 39)
1752 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1753 else
b91eee8c 1754 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
9aaf880e 1755 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
b91eee8c 1756 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
9aaf880e 1757
b91eee8c 1758 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
9aaf880e 1759 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
b91eee8c 1760 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
9aaf880e 1761
05b1342f
RK		 1762 inv_val |= hdmi->sink_is_hdmi ?
1763 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
1764 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE;
9aaf880e
FE		 1765
1766 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1767
ba9877e2
NA		 1768 hdisplay = mode->hdisplay;
1769 hblank = mode->htotal - mode->hdisplay;
1770 h_de_hs = mode->hsync_start - mode->hdisplay;
1771 hsync_len = mode->hsync_end - mode->hsync_start;
1772
1773 /*
1774 * When we're setting a YCbCr420 mode, we need
1775 * to adjust the horizontal timing to suit.
1776 */
1777 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) {
1778 hdisplay /= 2;
1779 hblank /= 2;
1780 h_de_hs /= 2;
1781 hsync_len /= 2;
1782 }
1783
e80b9f4e
RK		 1784 vdisplay = mode->vdisplay;
1785 vblank = mode->vtotal - mode->vdisplay;
1786 v_de_vs = mode->vsync_start - mode->vdisplay;
1787 vsync_len = mode->vsync_end - mode->vsync_start;
1788
1789 /*
1790 * When we're setting an interlaced mode, we need
1791 * to adjust the vertical timing to suit.
1792 */
1793 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1794 vdisplay /= 2;
1795 vblank /= 2;
1796 v_de_vs /= 2;
1797 vsync_len /= 2;
1798 }
1799
264fce6c 1800 /* Scrambling Control */
836f90f9 1801 if (dw_hdmi_support_scdc(hdmi)) {
ba9877e2 1802 if (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK ||
264fce6c
NA		 1803 hdmi_info->scdc.scrambling.low_rates) {
1804 /*
1805 * HDMI2.0 Specifies the following procedure:
1806 * After the Source Device has determined that
1807 * SCDC_Present is set (=1), the Source Device should
1808 * write the accurate Version of the Source Device
1809 * to the Source Version field in the SCDCS.
1810 * Source Devices compliant shall set the
1811 * Source Version = 1.
1812 */
c4cba44e 1813 drm_scdc_readb(hdmi->ddc, SCDC_SINK_VERSION,
264fce6c 1814 &bytes);
c4cba44e 1815 drm_scdc_writeb(hdmi->ddc, SCDC_SOURCE_VERSION,
264fce6c
NA		 1816 min_t(u8, bytes, SCDC_MIN_SOURCE_VERSION));
1817
1818 /* Enabled Scrambling in the Sink */
c4cba44e 1819 drm_scdc_set_scrambling(hdmi->ddc, 1);
264fce6c
NA		 1820
1821 /*
1822 * To activate the scrambler feature, you must ensure
1823 * that the quasi-static configuration bit
1824 * fc_invidconf.HDCP_keepout is set at configuration
1825 * time, before the required mc_swrstzreq.tmdsswrst_req
1826 * reset request is issued.
1827 */
1828 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
1829 HDMI_MC_SWRSTZ);
1830 hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL);
1831 } else {
1832 hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL);
1833 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
1834 HDMI_MC_SWRSTZ);
c4cba44e 1835 drm_scdc_set_scrambling(hdmi->ddc, 0);
264fce6c
NA		 1836 }
1837 }
1838
9aaf880e 1839 /* Set up horizontal active pixel width */
ba9877e2
NA		 1840 hdmi_writeb(hdmi, hdisplay >> 8, HDMI_FC_INHACTV1);
1841 hdmi_writeb(hdmi, hdisplay, HDMI_FC_INHACTV0);
9aaf880e
FE		 1842
1843 /* Set up vertical active lines */
e80b9f4e
RK		 1844 hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1);
1845 hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0);
9aaf880e
FE		 1846
1847 /* Set up horizontal blanking pixel region width */
9aaf880e
FE		 1848 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1849 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1850
1851 /* Set up vertical blanking pixel region width */
9aaf880e
FE		 1852 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1853
1854 /* Set up HSYNC active edge delay width (in pixel clks) */
9aaf880e
FE		 1855 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1856 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1857
1858 /* Set up VSYNC active edge delay (in lines) */
9aaf880e
FE		 1859 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1860
1861 /* Set up HSYNC active pulse width (in pixel clks) */
9aaf880e
FE		 1862 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1863 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1864
1865 /* Set up VSYNC active edge delay (in lines) */
9aaf880e
FE		 1866 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1867}
1868
9aaf880e 1869/* HDMI Initialization Step B.4 */
b21f4b65 1870static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
9aaf880e 1871{
9aaf880e
FE		 1872 /* control period minimum duration */
1873 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1874 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1875 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1876
1877 /* Set to fill TMDS data channels */
1878 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1879 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1880 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1881
1882 /* Enable pixel clock and tmds data path */
7cc4ab22
RK		 1883 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_HDCPCLK_DISABLE |
1884 HDMI_MC_CLKDIS_CSCCLK_DISABLE |
1885 HDMI_MC_CLKDIS_AUDCLK_DISABLE |
1886 HDMI_MC_CLKDIS_PREPCLK_DISABLE |
1887 HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1888 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1889 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
9aaf880e 1890
7cc4ab22
RK		 1891 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1892 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
9aaf880e
FE		 1893
1894 /* Enable csc path */
1895 if (is_color_space_conversion(hdmi)) {
7cc4ab22
RK		 1896 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1897 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
9aaf880e 1898 }
8b9e1c0d 1899
14247d7c
NA		 1900 /* Enable color space conversion if needed */
1901 if (is_color_space_conversion(hdmi))
8b9e1c0d
LP		 1902 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH,
1903 HDMI_MC_FLOWCTRL);
1904 else
1905 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS,
1906 HDMI_MC_FLOWCTRL);
9aaf880e
FE		 1907}
1908
9aaf880e 1909/* Workaround to clear the overflow condition */
b21f4b65 1910static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
9aaf880e 1911{
be41fc55
LP		 1912 unsigned int count;
1913 unsigned int i;
9aaf880e
FE		 1914 u8 val;
1915
be41fc55
LP		 1916 /*
1917 * Under some circumstances the Frame Composer arithmetic unit can miss
1918 * an FC register write due to being busy processing the previous one.
1919 * The issue can be worked around by issuing a TMDS software reset and
1920 * then write one of the FC registers several times.
1921 *
1922 * The number of iterations matters and depends on the HDMI TX revision
46d1b42b
JS		 1923 * (and possibly on the platform). So far i.MX6Q (v1.30a), i.MX6DL
1924 * (v1.31a) and multiple Allwinner SoCs (v1.32a) have been identified
1925 * as needing the workaround, with 4 iterations for v1.30a and 1
1926 * iteration for others.
9c305eb4
NA		 1927 * The Amlogic Meson GX SoCs (v2.01a) have been identified as needing
1928 * the workaround with a single iteration.
d15d9fd0
JK		 1929 * The Rockchip RK3288 SoC (v2.00a) and RK3328/RK3399 SoCs (v2.11a) have
1930 * been identified as needing the workaround with a single iteration.
be41fc55 1931 */
9aaf880e 1932
be41fc55
LP		 1933 switch (hdmi->version) {
1934 case 0x130a:
1935 count = 4;
1936 break;
1937 case 0x131a:
46d1b42b 1938 case 0x132a:
d15d9fd0 1939 case 0x200a:
9c305eb4 1940 case 0x201a:
d15d9fd0 1941 case 0x211a:
c8c78ac2 1942 case 0x212a:
be41fc55
LP		 1943 count = 1;
1944 break;
1945 default:
9aaf880e
FE		 1946 return;
1947 }
1948
be41fc55
LP		 1949 /* TMDS software reset */
1950 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1951
1952 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
1953 for (i = 0; i < count; i++)
9aaf880e
FE		 1954 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1955}
1956
b21f4b65 1957static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
9aaf880e
FE		 1958{
1959 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1960 HDMI_IH_MUTE_FC_STAT2);
1961}
1962
b21f4b65 1963static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
9aaf880e
FE		 1964{
1965 int ret;
1966
1967 hdmi_disable_overflow_interrupts(hdmi);
1968
1969 hdmi->vic = drm_match_cea_mode(mode);
1970
1971 if (!hdmi->vic) {
1972 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
9aaf880e
FE		 1973 } else {
1974 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
9aaf880e
FE		 1975 }
1976
1977 if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
b5878339
AY		 1978 (hdmi->vic == 21) || (hdmi->vic == 22) ||
1979 (hdmi->vic == 2) || (hdmi->vic == 3) ||
1980 (hdmi->vic == 17) || (hdmi->vic == 18))
def23aa7 1981 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601;
9aaf880e 1982 else
def23aa7 1983 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709;
9aaf880e 1984
d10ca826 1985 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
9aaf880e
FE		 1986 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
1987
def23aa7 1988 /* TOFIX: Get input format from plat data or fallback to RGB888 */
e20c29aa 1989 if (hdmi->plat_data->input_bus_format)
def23aa7
NA		 1990 hdmi->hdmi_data.enc_in_bus_format =
1991 hdmi->plat_data->input_bus_format;
1992 else
1993 hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
1994
1995 /* TOFIX: Get input encoding from plat data or fallback to none */
e20c29aa 1996 if (hdmi->plat_data->input_bus_encoding)
def23aa7
NA		 1997 hdmi->hdmi_data.enc_in_encoding =
1998 hdmi->plat_data->input_bus_encoding;
1999 else
2000 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT;
9aaf880e 2001
def23aa7
NA		 2002 /* TOFIX: Default to RGB888 output format */
2003 hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
9aaf880e 2004
9aaf880e
FE		 2005 hdmi->hdmi_data.pix_repet_factor = 0;
2006 hdmi->hdmi_data.hdcp_enable = 0;
2007 hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
2008
2009 /* HDMI Initialization Step B.1 */
2010 hdmi_av_composer(hdmi, mode);
2011
2012 /* HDMI Initializateion Step B.2 */
f1585f6e 2013 ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data, &hdmi->previous_mode);
9aaf880e
FE		 2014 if (ret)
2015 return ret;
f1585f6e 2016 hdmi->phy.enabled = true;
9aaf880e
FE		 2017
2018 /* HDMI Initialization Step B.3 */
b21f4b65 2019 dw_hdmi_enable_video_path(hdmi);
9aaf880e 2020
f709ec07
RK		 2021 if (hdmi->sink_has_audio) {
2022 dev_dbg(hdmi->dev, "sink has audio support\n");
9aaf880e
FE		 2023
2024 /* HDMI Initialization Step E - Configure audio */
2025 hdmi_clk_regenerator_update_pixel_clock(hdmi);
57fbc055 2026 hdmi_enable_audio_clk(hdmi, true);
f709ec07
RK		 2027 }
2028
2029 /* not for DVI mode */
2030 if (hdmi->sink_is_hdmi) {
2031 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
9aaf880e
FE		 2032
2033 /* HDMI Initialization Step F - Configure AVI InfoFrame */
d4ac4cb6 2034 hdmi_config_AVI(hdmi, mode);
9aa1eca0 2035 hdmi_config_vendor_specific_infoframe(hdmi, mode);
05b1342f
RK		 2036 } else {
2037 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
9aaf880e
FE		 2038 }
2039
2040 hdmi_video_packetize(hdmi);
2041 hdmi_video_csc(hdmi);
2042 hdmi_video_sample(hdmi);
2043 hdmi_tx_hdcp_config(hdmi);
2044
b21f4b65 2045 dw_hdmi_clear_overflow(hdmi);
9aaf880e
FE		 2046
2047 return 0;
2048}
2049
b21f4b65 2050static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
9aaf880e
FE		 2051{
2052 u8 ih_mute;
2053
2054 /*
2055 * Boot up defaults are:
2056 * HDMI_IH_MUTE = 0x03 (disabled)
2057 * HDMI_IH_MUTE_* = 0x00 (enabled)
2058 *
2059 * Disable top level interrupt bits in HDMI block
2060 */
2061 ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
2062 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
2063 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
2064
2065 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
2066
2067 /* by default mask all interrupts */
2068 hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
2069 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
2070 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
2071 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
2072 hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
2073 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
2074 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
2075 hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
2076 hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
2077 hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
2078 hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
2079 hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
9aaf880e
FE		 2080 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
2081 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
2082
2083 /* Disable interrupts in the IH_MUTE_* registers */
2084 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
2085 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
2086 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
2087 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
2088 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
2089 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
2090 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
2091 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
2092 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
2093 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
2094
2095 /* Enable top level interrupt bits in HDMI block */
2096 ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
2097 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
2098 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
2099}
2100
b21f4b65 2101static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
9aaf880e 2102{
381f05a7 2103 hdmi->bridge_is_on = true;
b21f4b65 2104 dw_hdmi_setup(hdmi, &hdmi->previous_mode);
9aaf880e
FE		 2105}
2106
b21f4b65 2107static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
9aaf880e 2108{
f1585f6e
LP		 2109 if (hdmi->phy.enabled) {
2110 hdmi->phy.ops->disable(hdmi, hdmi->phy.data);
2111 hdmi->phy.enabled = false;
2112 }
2113
381f05a7
RK		 2114 hdmi->bridge_is_on = false;
2115}
2116
2117static void dw_hdmi_update_power(struct dw_hdmi *hdmi)
2118{
2119 int force = hdmi->force;
2120
2121 if (hdmi->disabled) {
2122 force = DRM_FORCE_OFF;
2123 } else if (force == DRM_FORCE_UNSPECIFIED) {
aeac23bd 2124 if (hdmi->rxsense)
381f05a7
RK		 2125 force = DRM_FORCE_ON;
2126 else
2127 force = DRM_FORCE_OFF;
2128 }
2129
2130 if (force == DRM_FORCE_OFF) {
2131 if (hdmi->bridge_is_on)
2132 dw_hdmi_poweroff(hdmi);
2133 } else {
2134 if (!hdmi->bridge_is_on)
2135 dw_hdmi_poweron(hdmi);
2136 }
9aaf880e
FE		 2137}
2138
aeac23bd
RK		 2139/*
2140 * Adjust the detection of RXSENSE according to whether we have a forced
2141 * connection mode enabled, or whether we have been disabled. There is
2142 * no point processing RXSENSE interrupts if we have a forced connection
2143 * state, or DRM has us disabled.
2144 *
2145 * We also disable rxsense interrupts when we think we're disconnected
2146 * to avoid floating TDMS signals giving false rxsense interrupts.
2147 *
2148 * Note: we still need to listen for HPD interrupts even when DRM has us
2149 * disabled so that we can detect a connect event.
2150 */
2151static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi)
2152{
386d3299
NA		 2153 if (hdmi->phy.ops->update_hpd)
2154 hdmi->phy.ops->update_hpd(hdmi, hdmi->phy.data,
2155 hdmi->force, hdmi->disabled,
2156 hdmi->rxsense);
a23d6265
LP		 2157}
2158
b21f4b65
AY		 2159static enum drm_connector_status
2160dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
9aaf880e 2161{
b21f4b65 2162 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
d94905e0 2163 connector);
98dbeada 2164
381f05a7
RK		 2165 mutex_lock(&hdmi->mutex);
2166 hdmi->force = DRM_FORCE_UNSPECIFIED;
2167 dw_hdmi_update_power(hdmi);
aeac23bd 2168 dw_hdmi_update_phy_mask(hdmi);
381f05a7
RK		 2169 mutex_unlock(&hdmi->mutex);
2170
f1585f6e 2171 return hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data);
9aaf880e
FE		 2172}
2173
b21f4b65 2174static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
9aaf880e 2175{
b21f4b65 2176 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
9aaf880e
FE		 2177 connector);
2178 struct edid *edid;
6c7e66e6 2179 int ret = 0;
9aaf880e
FE		 2180
2181 if (!hdmi->ddc)
2182 return 0;
2183
2184 edid = drm_get_edid(connector, hdmi->ddc);
2185 if (edid) {
2186 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
2187 edid->width_cm, edid->height_cm);
2188
05b1342f 2189 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
f709ec07 2190 hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
c555f023 2191 drm_connector_update_edid_property(connector, edid);
e84b8d75 2192 cec_notifier_set_phys_addr_from_edid(hdmi->cec_notifier, edid);
9aaf880e
FE		 2193 ret = drm_add_edid_modes(connector, edid);
2194 kfree(edid);
2195 } else {
2196 dev_dbg(hdmi->dev, "failed to get edid\n");
2197 }
2198
6c7e66e6 2199 return ret;
9aaf880e
FE		 2200}
2201
381f05a7
RK		 2202static void dw_hdmi_connector_force(struct drm_connector *connector)
2203{
2204 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2205 connector);
2206
2207 mutex_lock(&hdmi->mutex);
2208 hdmi->force = connector->force;
2209 dw_hdmi_update_power(hdmi);
aeac23bd 2210 dw_hdmi_update_phy_mask(hdmi);
381f05a7
RK		 2211 mutex_unlock(&hdmi->mutex);
2212}
2213
dae91e4d 2214static const struct drm_connector_funcs dw_hdmi_connector_funcs = {
2c5b2ccc
MY		 2215 .fill_modes = drm_helper_probe_single_connector_modes,
2216 .detect = dw_hdmi_connector_detect,
fdd8326a 2217 .destroy = drm_connector_cleanup,
2c5b2ccc
MY		 2218 .force = dw_hdmi_connector_force,
2219 .reset = drm_atomic_helper_connector_reset,
2220 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
2221 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2222};
2223
dae91e4d 2224static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
b21f4b65 2225 .get_modes = dw_hdmi_connector_get_modes,
9aaf880e
FE		 2226};
2227
d2ae94ae
LP		 2228static int dw_hdmi_bridge_attach(struct drm_bridge *bridge)
2229{
2230 struct dw_hdmi *hdmi = bridge->driver_private;
2231 struct drm_encoder *encoder = bridge->encoder;
2232 struct drm_connector *connector = &hdmi->connector;
2233
2234 connector->interlace_allowed = 1;
2235 connector->polled = DRM_CONNECTOR_POLL_HPD;
2236
2237 drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs);
2238
9ebc4d21
AP		 2239 drm_connector_init_with_ddc(bridge->dev, connector,
2240 &dw_hdmi_connector_funcs,
2241 DRM_MODE_CONNECTOR_HDMIA,
2242 hdmi->ddc);
d2ae94ae 2243
cde4c44d 2244 drm_connector_attach_encoder(connector, encoder);
d2ae94ae
LP		 2245
2246 return 0;
2247}
2248
b0febde7
JA		 2249static enum drm_mode_status
2250dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge,
2251 const struct drm_display_mode *mode)
6ce2ca58
RP		 2252{
2253 struct dw_hdmi *hdmi = bridge->driver_private;
2254 struct drm_connector *connector = &hdmi->connector;
b0febde7 2255 enum drm_mode_status mode_status = MODE_OK;
6ce2ca58 2256
b0febde7
JA		 2257 /* We don't support double-clocked modes */
2258 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
2259 return MODE_BAD;
2260
2261 if (hdmi->plat_data->mode_valid)
2262 mode_status = hdmi->plat_data->mode_valid(connector, mode);
2263
2264 return mode_status;
6ce2ca58
RP		 2265}
2266
fd30b38c 2267static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
63f8f3ba
LP		 2268 const struct drm_display_mode *orig_mode,
2269 const struct drm_display_mode *mode)
fd30b38c
LP		 2270{
2271 struct dw_hdmi *hdmi = bridge->driver_private;
2272
2273 mutex_lock(&hdmi->mutex);
2274
2275 /* Store the display mode for plugin/DKMS poweron events */
2276 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
2277
2278 mutex_unlock(&hdmi->mutex);
2279}
2280
2281static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
2282{
2283 struct dw_hdmi *hdmi = bridge->driver_private;
2284
2285 mutex_lock(&hdmi->mutex);
2286 hdmi->disabled = true;
2287 dw_hdmi_update_power(hdmi);
2288 dw_hdmi_update_phy_mask(hdmi);
2289 mutex_unlock(&hdmi->mutex);
2290}
2291
2292static void dw_hdmi_bridge_enable(struct drm_bridge *bridge)
2293{
2294 struct dw_hdmi *hdmi = bridge->driver_private;
2295
2296 mutex_lock(&hdmi->mutex);
2297 hdmi->disabled = false;
2298 dw_hdmi_update_power(hdmi);
2299 dw_hdmi_update_phy_mask(hdmi);
2300 mutex_unlock(&hdmi->mutex);
2301}
2302
dae91e4d 2303static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
d2ae94ae 2304 .attach = dw_hdmi_bridge_attach,
b21f4b65
AY		 2305 .enable = dw_hdmi_bridge_enable,
2306 .disable = dw_hdmi_bridge_disable,
b21f4b65 2307 .mode_set = dw_hdmi_bridge_mode_set,
b0febde7 2308 .mode_valid = dw_hdmi_bridge_mode_valid,
3d1b35a3
AY		 2309};
2310
3efc2fa3
VZ		 2311static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi)
2312{
2313 struct dw_hdmi_i2c *i2c = hdmi->i2c;
2314 unsigned int stat;
2315
2316 stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0);
2317 if (!stat)
2318 return IRQ_NONE;
2319
2320 hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0);
2321
2322 i2c->stat = stat;
2323
2324 complete(&i2c->cmp);
2325
2326 return IRQ_HANDLED;
2327}
2328
b21f4b65 2329static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
d94905e0 2330{
b21f4b65 2331 struct dw_hdmi *hdmi = dev_id;
d94905e0 2332 u8 intr_stat;
3efc2fa3
VZ		 2333 irqreturn_t ret = IRQ_NONE;
2334
2335 if (hdmi->i2c)
2336 ret = dw_hdmi_i2c_irq(hdmi);
d94905e0
RK		 2337
2338 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
3efc2fa3 2339 if (intr_stat) {
d94905e0 2340 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
3efc2fa3
VZ		 2341 return IRQ_WAKE_THREAD;
2342 }
d94905e0 2343
3efc2fa3 2344 return ret;
d94905e0
RK		 2345}
2346
c32048d9 2347void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense)
386d3299
NA		 2348{
2349 mutex_lock(&hdmi->mutex);
2350
2351 if (!hdmi->force) {
2352 /*
2353 * If the RX sense status indicates we're disconnected,
2354 * clear the software rxsense status.
2355 */
2356 if (!rx_sense)
2357 hdmi->rxsense = false;
2358
2359 /*
2360 * Only set the software rxsense status when both
2361 * rxsense and hpd indicates we're connected.
2362 * This avoids what seems to be bad behaviour in
2363 * at least iMX6S versions of the phy.
2364 */
2365 if (hpd)
2366 hdmi->rxsense = true;
2367
2368 dw_hdmi_update_power(hdmi);
2369 dw_hdmi_update_phy_mask(hdmi);
2370 }
2371 mutex_unlock(&hdmi->mutex);
2372}
386d3299
NA		 2373EXPORT_SYMBOL_GPL(dw_hdmi_setup_rx_sense);
2374
b21f4b65 2375static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
9aaf880e 2376{
b21f4b65 2377 struct dw_hdmi *hdmi = dev_id;
aeac23bd 2378 u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat;
9aaf880e
FE		 2379
2380 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
9aaf880e 2381 phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
aeac23bd
RK		 2382 phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0);
2383
2384 phy_pol_mask = 0;
2385 if (intr_stat & HDMI_IH_PHY_STAT0_HPD)
2386 phy_pol_mask |= HDMI_PHY_HPD;
2387 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0)
2388 phy_pol_mask |= HDMI_PHY_RX_SENSE0;
2389 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1)
2390 phy_pol_mask |= HDMI_PHY_RX_SENSE1;
2391 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2)
2392 phy_pol_mask |= HDMI_PHY_RX_SENSE2;
2393 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3)
2394 phy_pol_mask |= HDMI_PHY_RX_SENSE3;
2395
2396 if (phy_pol_mask)
2397 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0);
9aaf880e 2398
aeac23bd
RK		 2399 /*
2400 * RX sense tells us whether the TDMS transmitters are detecting
2401 * load - in other words, there's something listening on the
2402 * other end of the link. Use this to decide whether we should
2403 * power on the phy as HPD may be toggled by the sink to merely
2404 * ask the source to re-read the EDID.
2405 */
2406 if (intr_stat &
e84b8d75 2407 (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) {
c32048d9
NA		 2408 dw_hdmi_setup_rx_sense(hdmi,
2409 phy_stat & HDMI_PHY_HPD,
2410 phy_stat & HDMI_PHY_RX_SENSE);
aeac23bd 2411
e84b8d75
RK		 2412 if ((phy_stat & (HDMI_PHY_RX_SENSE | HDMI_PHY_HPD)) == 0)
2413 cec_notifier_set_phys_addr(hdmi->cec_notifier,
2414 CEC_PHYS_ADDR_INVALID);
2415 }
2416
aeac23bd
RK		 2417 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
2418 dev_dbg(hdmi->dev, "EVENT=%s\n",
2419 phy_int_pol & HDMI_PHY_HPD ? "plugin" : "plugout");
ba5d7e61
LP		 2420 if (hdmi->bridge.dev)
2421 drm_helper_hpd_irq_event(hdmi->bridge.dev);
9aaf880e
FE		 2422 }
2423
2424 hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
aeac23bd
RK		 2425 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
2426 HDMI_IH_MUTE_PHY_STAT0);
9aaf880e
FE		 2427
2428 return IRQ_HANDLED;
2429}
2430
faba6c3c
LP		 2431static const struct dw_hdmi_phy_data dw_hdmi_phys[] = {
2432 {
2433 .type = DW_HDMI_PHY_DWC_HDMI_TX_PHY,
2434 .name = "DWC HDMI TX PHY",
b0e583e5 2435 .gen = 1,
faba6c3c
LP		 2436 }, {
2437 .type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC,
2438 .name = "DWC MHL PHY + HEAC PHY",
b0e583e5 2439 .gen = 2,
faba6c3c 2440 .has_svsret = true,
2ef9dfed 2441 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
faba6c3c
LP		 2442 }, {
2443 .type = DW_HDMI_PHY_DWC_MHL_PHY,
2444 .name = "DWC MHL PHY",
b0e583e5 2445 .gen = 2,
faba6c3c 2446 .has_svsret = true,
2ef9dfed 2447 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
faba6c3c
LP		 2448 }, {
2449 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC,
2450 .name = "DWC HDMI 3D TX PHY + HEAC PHY",
b0e583e5 2451 .gen = 2,
2ef9dfed 2452 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
faba6c3c
LP		 2453 }, {
2454 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY,
2455 .name = "DWC HDMI 3D TX PHY",
b0e583e5 2456 .gen = 2,
2ef9dfed 2457 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
faba6c3c
LP		 2458 }, {
2459 .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY,
2460 .name = "DWC HDMI 2.0 TX PHY",
b0e583e5 2461 .gen = 2,
faba6c3c 2462 .has_svsret = true,
c93f6092 2463 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2ef9dfed
KB		 2464 }, {
2465 .type = DW_HDMI_PHY_VENDOR_PHY,
2466 .name = "Vendor PHY",
faba6c3c
LP		 2467 }
2468};
2469
2470static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi)
2471{
2472 unsigned int i;
2473 u8 phy_type;
2474
8faff374
HS		 2475 phy_type = hdmi->plat_data->phy_force_vendor ?
2476 DW_HDMI_PHY_VENDOR_PHY :
2477 hdmi_readb(hdmi, HDMI_CONFIG2_ID);
faba6c3c 2478
f1585f6e
LP		 2479 if (phy_type == DW_HDMI_PHY_VENDOR_PHY) {
2480 /* Vendor PHYs require support from the glue layer. */
2481 if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) {
2482 dev_err(hdmi->dev,
2483 "Vendor HDMI PHY not supported by glue layer\n");
2484 return -ENODEV;
2485 }
2486
2487 hdmi->phy.ops = hdmi->plat_data->phy_ops;
2488 hdmi->phy.data = hdmi->plat_data->phy_data;
2489 hdmi->phy.name = hdmi->plat_data->phy_name;
2490 return 0;
2491 }
2492
2493 /* Synopsys PHYs are handled internally. */
faba6c3c
LP		 2494 for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) {
2495 if (dw_hdmi_phys[i].type == phy_type) {
f1585f6e
LP		 2496 hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops;
2497 hdmi->phy.name = dw_hdmi_phys[i].name;
2498 hdmi->phy.data = (void *)&dw_hdmi_phys[i];
2ef9dfed
KB		 2499
2500 if (!dw_hdmi_phys[i].configure &&
2501 !hdmi->plat_data->configure_phy) {
2502 dev_err(hdmi->dev, "%s requires platform support\n",
2503 hdmi->phy.name);
2504 return -ENODEV;
2505 }
2506
faba6c3c
LP		 2507 return 0;
2508 }
2509 }
2510
f1585f6e 2511 dev_err(hdmi->dev, "Unsupported HDMI PHY type (%02x)\n", phy_type);
faba6c3c
LP		 2512 return -ENODEV;
2513}
2514
a616e63c
RK		 2515static void dw_hdmi_cec_enable(struct dw_hdmi *hdmi)
2516{
2517 mutex_lock(&hdmi->mutex);
2518 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CECCLK_DISABLE;
2519 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2520 mutex_unlock(&hdmi->mutex);
2521}
2522
2523static void dw_hdmi_cec_disable(struct dw_hdmi *hdmi)
2524{
2525 mutex_lock(&hdmi->mutex);
2526 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CECCLK_DISABLE;
2527 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2528 mutex_unlock(&hdmi->mutex);
2529}
2530
2531static const struct dw_hdmi_cec_ops dw_hdmi_cec_ops = {
2532 .write = hdmi_writeb,
2533 .read = hdmi_readb,
2534 .enable = dw_hdmi_cec_enable,
2535 .disable = dw_hdmi_cec_disable,
2536};
2537
80e2f979
NA		 2538static const struct regmap_config hdmi_regmap_8bit_config = {
2539 .reg_bits = 32,
2540 .val_bits = 8,
2541 .reg_stride = 1,
2542 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR,
2543};
2544
2545static const struct regmap_config hdmi_regmap_32bit_config = {
2546 .reg_bits = 32,
2547 .val_bits = 32,
2548 .reg_stride = 4,
2549 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR << 2,
2550};
2551
99d02ed5
DA		 2552static void dw_hdmi_init_hw(struct dw_hdmi *hdmi)
2553{
2554 initialize_hdmi_ih_mutes(hdmi);
2555
2556 /*
2557 * Reset HDMI DDC I2C master controller and mute I2CM interrupts.
2558 * Even if we are using a separate i2c adapter doing this doesn't
2559 * hurt.
2560 */
2561 dw_hdmi_i2c_init(hdmi);
2562
2563 if (hdmi->phy.ops->setup_hpd)
2564 hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data);
2565}
2566
69497eb9
LP		 2567static struct dw_hdmi *
2568__dw_hdmi_probe(struct platform_device *pdev,
2569 const struct dw_hdmi_plat_data *plat_data)
9aaf880e 2570{
c608119d 2571 struct device *dev = &pdev->dev;
17b5001b 2572 struct device_node *np = dev->of_node;
7ed6c665 2573 struct platform_device_info pdevinfo;
9aaf880e 2574 struct device_node *ddc_node;
a616e63c 2575 struct dw_hdmi_cec_data cec;
b21f4b65 2576 struct dw_hdmi *hdmi;
80e2f979 2577 struct resource *iores = NULL;
c608119d 2578 int irq;
3d1b35a3 2579 int ret;
0cd9d142 2580 u32 val = 1;
0527e12e
LP		 2581 u8 prod_id0;
2582 u8 prod_id1;
2761ba6c 2583 u8 config0;
0c674948 2584 u8 config3;
9aaf880e 2585
17b5001b 2586 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
9aaf880e 2587 if (!hdmi)
69497eb9 2588 return ERR_PTR(-ENOMEM);
9aaf880e 2589
3d1b35a3 2590 hdmi->plat_data = plat_data;
17b5001b 2591 hdmi->dev = dev;
40678388 2592 hdmi->sample_rate = 48000;
b872a8e1 2593 hdmi->disabled = true;
aeac23bd
RK		 2594 hdmi->rxsense = true;
2595 hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE);
7cc4ab22 2596 hdmi->mc_clkdis = 0x7f;
9aaf880e 2597
b872a8e1 2598 mutex_init(&hdmi->mutex);
6bcf4953 2599 mutex_init(&hdmi->audio_mutex);
b90120a9 2600 spin_lock_init(&hdmi->audio_lock);
6bcf4953 2601
b5d45901 2602 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
9aaf880e 2603 if (ddc_node) {
9f04a1f2 2604 hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node);
c2c38488
AY		 2605 of_node_put(ddc_node);
2606 if (!hdmi->ddc) {
9aaf880e 2607 dev_dbg(hdmi->dev, "failed to read ddc node\n");
69497eb9 2608 return ERR_PTR(-EPROBE_DEFER);
c2c38488 2609 }
9aaf880e 2610
9aaf880e
FE		 2611 } else {
2612 dev_dbg(hdmi->dev, "no ddc property found\n");
2613 }
2614
80e2f979
NA		 2615 if (!plat_data->regm) {
2616 const struct regmap_config *reg_config;
2617
2618 of_property_read_u32(np, "reg-io-width", &val);
2619 switch (val) {
2620 case 4:
2621 reg_config = &hdmi_regmap_32bit_config;
2622 hdmi->reg_shift = 2;
2623 break;
2624 case 1:
2625 reg_config = &hdmi_regmap_8bit_config;
2626 break;
2627 default:
2628 dev_err(dev, "reg-io-width must be 1 or 4\n");
2629 return ERR_PTR(-EINVAL);
2630 }
2631
2632 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2633 hdmi->regs = devm_ioremap_resource(dev, iores);
2634 if (IS_ERR(hdmi->regs)) {
2635 ret = PTR_ERR(hdmi->regs);
2636 goto err_res;
2637 }
2638
2639 hdmi->regm = devm_regmap_init_mmio(dev, hdmi->regs, reg_config);
2640 if (IS_ERR(hdmi->regm)) {
2641 dev_err(dev, "Failed to configure regmap\n");
2642 ret = PTR_ERR(hdmi->regm);
2643 goto err_res;
2644 }
2645 } else {
2646 hdmi->regm = plat_data->regm;
9f04a1f2 2647 }
9aaf880e 2648
9aaf880e
FE		 2649 hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
2650 if (IS_ERR(hdmi->isfr_clk)) {
2651 ret = PTR_ERR(hdmi->isfr_clk);
b5878339 2652 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
9f04a1f2 2653 goto err_res;
9aaf880e
FE		 2654 }
2655
2656 ret = clk_prepare_enable(hdmi->isfr_clk);
2657 if (ret) {
b5878339 2658 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
9f04a1f2 2659 goto err_res;
9aaf880e
FE		 2660 }
2661
2662 hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
2663 if (IS_ERR(hdmi->iahb_clk)) {
2664 ret = PTR_ERR(hdmi->iahb_clk);
b5878339 2665 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
9aaf880e
FE		 2666 goto err_isfr;
2667 }
2668
2669 ret = clk_prepare_enable(hdmi->iahb_clk);
2670 if (ret) {
b5878339 2671 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
9aaf880e
FE		 2672 goto err_isfr;
2673 }
2674
ebe32c3e
PHH		 2675 hdmi->cec_clk = devm_clk_get(hdmi->dev, "cec");
2676 if (PTR_ERR(hdmi->cec_clk) == -ENOENT) {
2677 hdmi->cec_clk = NULL;
2678 } else if (IS_ERR(hdmi->cec_clk)) {
2679 ret = PTR_ERR(hdmi->cec_clk);
2680 if (ret != -EPROBE_DEFER)
2681 dev_err(hdmi->dev, "Cannot get HDMI cec clock: %d\n",
2682 ret);
2683
2684 hdmi->cec_clk = NULL;
2685 goto err_iahb;
2686 } else {
2687 ret = clk_prepare_enable(hdmi->cec_clk);
2688 if (ret) {
2689 dev_err(hdmi->dev, "Cannot enable HDMI cec clock: %d\n",
2690 ret);
2691 goto err_iahb;
2692 }
2693 }
2694
9aaf880e 2695 /* Product and revision IDs */
be41fc55
LP		 2696 hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8)
2697 | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0);
0527e12e
LP		 2698 prod_id0 = hdmi_readb(hdmi, HDMI_PRODUCT_ID0);
2699 prod_id1 = hdmi_readb(hdmi, HDMI_PRODUCT_ID1);
2700
2701 if (prod_id0 != HDMI_PRODUCT_ID0_HDMI_TX ||
2702 (prod_id1 & ~HDMI_PRODUCT_ID1_HDCP) != HDMI_PRODUCT_ID1_HDMI_TX) {
2703 dev_err(dev, "Unsupported HDMI controller (%04x:%02x:%02x)\n",
be41fc55 2704 hdmi->version, prod_id0, prod_id1);
0527e12e
LP		 2705 ret = -ENODEV;
2706 goto err_iahb;
2707 }
2708
faba6c3c
LP		 2709 ret = dw_hdmi_detect_phy(hdmi);
2710 if (ret < 0)
2711 goto err_iahb;
2712
2713 dev_info(dev, "Detected HDMI TX controller v%x.%03x %s HDCP (%s)\n",
be41fc55 2714 hdmi->version >> 12, hdmi->version & 0xfff,
faba6c3c 2715 prod_id1 & HDMI_PRODUCT_ID1_HDCP ? "with" : "without",
f1585f6e 2716 hdmi->phy.name);
9aaf880e 2717
99d02ed5 2718 dw_hdmi_init_hw(hdmi);
9aaf880e 2719
c608119d 2720 irq = platform_get_irq(pdev, 0);
69497eb9
LP		 2721 if (irq < 0) {
2722 ret = irq;
c608119d 2723 goto err_iahb;
69497eb9 2724 }
c608119d 2725
639a202c
PZ		 2726 ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
2727 dw_hdmi_irq, IRQF_SHARED,
2728 dev_name(dev), hdmi);
2729 if (ret)
b33ef619 2730 goto err_iahb;
639a202c 2731
e84b8d75
RK		 2732 hdmi->cec_notifier = cec_notifier_get(dev);
2733 if (!hdmi->cec_notifier) {
2734 ret = -ENOMEM;
2735 goto err_iahb;
2736 }
2737
9aaf880e
FE		 2738 /*
2739 * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
2740 * N and cts values before enabling phy
2741 */
2742 hdmi_init_clk_regenerator(hdmi);
2743
3efc2fa3
VZ		 2744 /* If DDC bus is not specified, try to register HDMI I2C bus */
2745 if (!hdmi->ddc) {
50f9495e
DA		 2746 /* Look for (optional) stuff related to unwedging */
2747 hdmi->pinctrl = devm_pinctrl_get(dev);
2748 if (!IS_ERR(hdmi->pinctrl)) {
2749 hdmi->unwedge_state =
2750 pinctrl_lookup_state(hdmi->pinctrl, "unwedge");
2751 hdmi->default_state =
2752 pinctrl_lookup_state(hdmi->pinctrl, "default");
2753
0bd79f91
DA		 2754 if (IS_ERR(hdmi->default_state) ||
2755 IS_ERR(hdmi->unwedge_state)) {
2756 if (!IS_ERR(hdmi->unwedge_state))
2757 dev_warn(dev,
2758 "Unwedge requires default pinctrl\n");
2759 hdmi->default_state = NULL;
2760 hdmi->unwedge_state = NULL;
50f9495e
DA		 2761 }
2762 }
2763
3efc2fa3
VZ		 2764 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi);
2765 if (IS_ERR(hdmi->ddc))
2766 hdmi->ddc = NULL;
2767 }
2768
69497eb9
LP		 2769 hdmi->bridge.driver_private = hdmi;
2770 hdmi->bridge.funcs = &dw_hdmi_bridge_funcs;
d5ad7843 2771#ifdef CONFIG_OF
69497eb9 2772 hdmi->bridge.of_node = pdev->dev.of_node;
d5ad7843 2773#endif
9aaf880e 2774
7ed6c665
RK		 2775 memset(&pdevinfo, 0, sizeof(pdevinfo));
2776 pdevinfo.parent = dev;
2777 pdevinfo.id = PLATFORM_DEVID_AUTO;
2778
2761ba6c 2779 config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID);
0c674948 2780 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID);
2761ba6c 2781
80e2f979 2782 if (iores && config3 & HDMI_CONFIG3_AHBAUDDMA) {
2761ba6c
KM		 2783 struct dw_hdmi_audio_data audio;
2784
7ed6c665
RK		 2785 audio.phys = iores->start;
2786 audio.base = hdmi->regs;
2787 audio.irq = irq;
2788 audio.hdmi = hdmi;
f5ce4057 2789 audio.eld = hdmi->connector.eld;
a7d555d2
RP		 2790 hdmi->enable_audio = dw_hdmi_ahb_audio_enable;
2791 hdmi->disable_audio = dw_hdmi_ahb_audio_disable;
7ed6c665
RK		 2792
2793 pdevinfo.name = "dw-hdmi-ahb-audio";
2794 pdevinfo.data = &audio;
2795 pdevinfo.size_data = sizeof(audio);
2796 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2797 hdmi->audio = platform_device_register_full(&pdevinfo);
2761ba6c
KM		 2798 } else if (config0 & HDMI_CONFIG0_I2S) {
2799 struct dw_hdmi_i2s_audio_data audio;
2800
2801 audio.hdmi = hdmi;
2802 audio.write = hdmi_writeb;
2803 audio.read = hdmi_readb;
a7d555d2 2804 hdmi->enable_audio = dw_hdmi_i2s_audio_enable;
57fbc055 2805 hdmi->disable_audio = dw_hdmi_i2s_audio_disable;
2761ba6c
KM		 2806
2807 pdevinfo.name = "dw-hdmi-i2s-audio";
2808 pdevinfo.data = &audio;
2809 pdevinfo.size_data = sizeof(audio);
2810 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2811 hdmi->audio = platform_device_register_full(&pdevinfo);
7ed6c665
RK		 2812 }
2813
a616e63c
RK		 2814 if (config0 & HDMI_CONFIG0_CEC) {
2815 cec.hdmi = hdmi;
2816 cec.ops = &dw_hdmi_cec_ops;
2817 cec.irq = irq;
2818
2819 pdevinfo.name = "dw-hdmi-cec";
2820 pdevinfo.data = &cec;
2821 pdevinfo.size_data = sizeof(cec);
2822 pdevinfo.dma_mask = 0;
2823
2824 hdmi->cec = platform_device_register_full(&pdevinfo);
2825 }
2826
69497eb9 2827 return hdmi;
9aaf880e
FE		 2828
2829err_iahb:
3efc2fa3
VZ		 2830 if (hdmi->i2c) {
2831 i2c_del_adapter(&hdmi->i2c->adap);
2832 hdmi->ddc = NULL;
2833 }
2834
e84b8d75
RK		 2835 if (hdmi->cec_notifier)
2836 cec_notifier_put(hdmi->cec_notifier);
2837
9aaf880e 2838 clk_disable_unprepare(hdmi->iahb_clk);
ebe32c3e
PHH		 2839 if (hdmi->cec_clk)
2840 clk_disable_unprepare(hdmi->cec_clk);
9aaf880e
FE		 2841err_isfr:
2842 clk_disable_unprepare(hdmi->isfr_clk);
9f04a1f2
VZ		 2843err_res:
2844 i2c_put_adapter(hdmi->ddc);
9aaf880e 2845
69497eb9 2846 return ERR_PTR(ret);
9aaf880e
FE		 2847}
2848
69497eb9 2849static void __dw_hdmi_remove(struct dw_hdmi *hdmi)
9aaf880e 2850{
7ed6c665
RK		 2851 if (hdmi->audio && !IS_ERR(hdmi->audio))
2852 platform_device_unregister(hdmi->audio);
a616e63c
RK		 2853 if (!IS_ERR(hdmi->cec))
2854 platform_device_unregister(hdmi->cec);
7ed6c665 2855
d94905e0
RK		 2856 /* Disable all interrupts */
2857 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
2858
e383bf85
HV		 2859 if (hdmi->cec_notifier)
2860 cec_notifier_put(hdmi->cec_notifier);
2861
9aaf880e
FE		 2862 clk_disable_unprepare(hdmi->iahb_clk);
2863 clk_disable_unprepare(hdmi->isfr_clk);
ebe32c3e
PHH		 2864 if (hdmi->cec_clk)
2865 clk_disable_unprepare(hdmi->cec_clk);
3efc2fa3
VZ		 2866
2867 if (hdmi->i2c)
2868 i2c_del_adapter(&hdmi->i2c->adap);
2869 else
2870 i2c_put_adapter(hdmi->ddc);
17b5001b 2871}
69497eb9
LP		 2872
2873/* -----------------------------------------------------------------------------
2874 * Probe/remove API, used from platforms based on the DRM bridge API.
2875 */
eea034af
JS		 2876struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
2877 const struct dw_hdmi_plat_data *plat_data)
69497eb9
LP		 2878{
2879 struct dw_hdmi *hdmi;
69497eb9
LP		 2880
2881 hdmi = __dw_hdmi_probe(pdev, plat_data);
2882 if (IS_ERR(hdmi))
eea034af 2883 return hdmi;
69497eb9 2884
b678682e 2885 drm_bridge_add(&hdmi->bridge);
69497eb9 2886
eea034af 2887 return hdmi;
69497eb9
LP		 2888}
2889EXPORT_SYMBOL_GPL(dw_hdmi_probe);
2890
eea034af 2891void dw_hdmi_remove(struct dw_hdmi *hdmi)
69497eb9 2892{
69497eb9
LP		 2893 drm_bridge_remove(&hdmi->bridge);
2894
2895 __dw_hdmi_remove(hdmi);
2896}
2897EXPORT_SYMBOL_GPL(dw_hdmi_remove);
2898
2899/* -----------------------------------------------------------------------------
2900 * Bind/unbind API, used from platforms based on the component framework.
2901 */
eea034af
JS		 2902struct dw_hdmi *dw_hdmi_bind(struct platform_device *pdev,
2903 struct drm_encoder *encoder,
2904 const struct dw_hdmi_plat_data *plat_data)
69497eb9
LP		 2905{
2906 struct dw_hdmi *hdmi;
2907 int ret;
2908
2909 hdmi = __dw_hdmi_probe(pdev, plat_data);
2910 if (IS_ERR(hdmi))
eea034af 2911 return hdmi;
69497eb9
LP		 2912
2913 ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL);
2914 if (ret) {
eea034af 2915 dw_hdmi_remove(hdmi);
69497eb9 2916 DRM_ERROR("Failed to initialize bridge with drm\n");
eea034af 2917 return ERR_PTR(ret);
69497eb9
LP		 2918 }
2919
eea034af 2920 return hdmi;
69497eb9
LP		 2921}
2922EXPORT_SYMBOL_GPL(dw_hdmi_bind);
2923
eea034af 2924void dw_hdmi_unbind(struct dw_hdmi *hdmi)
69497eb9 2925{
69497eb9
LP		 2926 __dw_hdmi_remove(hdmi);
2927}
b21f4b65 2928EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
9aaf880e 2929
99d02ed5
DA		 2930void dw_hdmi_resume(struct dw_hdmi *hdmi)
2931{
2932 dw_hdmi_init_hw(hdmi);
2933}
2934EXPORT_SYMBOL_GPL(dw_hdmi_resume);
2935
9aaf880e 2936MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
3d1b35a3
AY		 2937MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
2938MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
3efc2fa3 2939MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>");
b21f4b65 2940MODULE_DESCRIPTION("DW HDMI transmitter driver");
9aaf880e 2941MODULE_LICENSE("GPL");
b21f4b65 2942MODULE_ALIAS("platform:dw-hdmi");
Linux 6.x block layer and io_uring tree(s)