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drm: bridge: dw-hdmi: Report connector status using callback
[linux-2.6-block.git] / drivers / gpu / drm / bridge / synopsys / dw-hdmi.c
CommitLineData
2874c5fd 1// SPDX-License-Identifier: GPL-2.0-or-later
9aaf880e 2/*
3efc2fa3
VZ		 3 * DesignWare High-Definition Multimedia Interface (HDMI) driver
4 *
5 * Copyright (C) 2013-2015 Mentor Graphics Inc.
9aaf880e 6 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
3efc2fa3 7 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
9aaf880e 8 */
95b60804 9#include <linux/clk.h>
9aaf880e
FE		 10#include <linux/delay.h>
11#include <linux/err.h>
5a819ed6 12#include <linux/hdmi.h>
95b60804
SR		 13#include <linux/irq.h>
14#include <linux/module.h>
6bcf4953 15#include <linux/mutex.h>
9aaf880e 16#include <linux/of_device.h>
50f9495e 17#include <linux/pinctrl/consumer.h>
80e2f979 18#include <linux/regmap.h>
95b60804 19#include <linux/dma-mapping.h>
b90120a9 20#include <linux/spinlock.h>
9aaf880e 21
95b60804
SR		 22#include <media/cec-notifier.h>
23
24#include <uapi/linux/media-bus-format.h>
25#include <uapi/linux/videodev2.h>
26
27#include <drm/bridge/dw_hdmi.h>
2c5b2ccc 28#include <drm/drm_atomic_helper.h>
9aaf880e 29#include <drm/drm_edid.h>
95b60804
SR		 30#include <drm/drm_of.h>
31#include <drm/drm_print.h>
fcd70cd3 32#include <drm/drm_probe_helper.h>
95b60804 33#include <drm/drm_scdc_helper.h>
def23aa7 34
248a86fc 35#include "dw-hdmi-audio.h"
a616e63c 36#include "dw-hdmi-cec.h"
95b60804 37#include "dw-hdmi.h"
e84b8d75 38
94bb4dc1 39#define DDC_SEGMENT_ADDR 0x30
e84b8d75 40
9aaf880e
FE		 41#define HDMI_EDID_LEN 512
42
264fce6c
NA		 43/* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */
44#define SCDC_MIN_SOURCE_VERSION 0x1
45
46#define HDMI14_MAX_TMDSCLK 340000000
47
9aaf880e
FE		 48enum hdmi_datamap {
49 RGB444_8B = 0x01,
50 RGB444_10B = 0x03,
51 RGB444_12B = 0x05,
52 RGB444_16B = 0x07,
53 YCbCr444_8B = 0x09,
54 YCbCr444_10B = 0x0B,
55 YCbCr444_12B = 0x0D,
56 YCbCr444_16B = 0x0F,
57 YCbCr422_8B = 0x16,
58 YCbCr422_10B = 0x14,
59 YCbCr422_12B = 0x12,
60};
61
9aaf880e
FE		 62static const u16 csc_coeff_default[3][4] = {
63 { 0x2000, 0x0000, 0x0000, 0x0000 },
64 { 0x0000, 0x2000, 0x0000, 0x0000 },
65 { 0x0000, 0x0000, 0x2000, 0x0000 }
66};
67
68static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
69 { 0x2000, 0x6926, 0x74fd, 0x010e },
70 { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
71 { 0x2000, 0x0000, 0x38b4, 0x7e3b }
72};
73
74static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
75 { 0x2000, 0x7106, 0x7a02, 0x00a7 },
76 { 0x2000, 0x3264, 0x0000, 0x7e6d },
77 { 0x2000, 0x0000, 0x3b61, 0x7e25 }
78};
79
80static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
81 { 0x2591, 0x1322, 0x074b, 0x0000 },
82 { 0x6535, 0x2000, 0x7acc, 0x0200 },
83 { 0x6acd, 0x7534, 0x2000, 0x0200 }
84};
85
86static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
87 { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
88 { 0x62f0, 0x2000, 0x7d11, 0x0200 },
89 { 0x6756, 0x78ab, 0x2000, 0x0200 }
90};
91
92struct hdmi_vmode {
9aaf880e
FE		 93 bool mdataenablepolarity;
94
95 unsigned int mpixelclock;
96 unsigned int mpixelrepetitioninput;
97 unsigned int mpixelrepetitionoutput;
ba9877e2 98 unsigned int mtmdsclock;
9aaf880e
FE		 99};
100
101struct hdmi_data_info {
def23aa7
NA		 102 unsigned int enc_in_bus_format;
103 unsigned int enc_out_bus_format;
104 unsigned int enc_in_encoding;
105 unsigned int enc_out_encoding;
9aaf880e
FE		 106 unsigned int pix_repet_factor;
107 unsigned int hdcp_enable;
108 struct hdmi_vmode video_mode;
109};
110
3efc2fa3
VZ		 111struct dw_hdmi_i2c {
112 struct i2c_adapter adap;
113
114 struct mutex lock; /* used to serialize data transfers */
115 struct completion cmp;
116 u8 stat;
117
118 u8 slave_reg;
119 bool is_regaddr;
94bb4dc1 120 bool is_segment;
3efc2fa3
VZ		 121};
122
faba6c3c
LP		 123struct dw_hdmi_phy_data {
124 enum dw_hdmi_phy_type type;
125 const char *name;
b0e583e5 126 unsigned int gen;
faba6c3c 127 bool has_svsret;
2ef9dfed
KB		 128 int (*configure)(struct dw_hdmi *hdmi,
129 const struct dw_hdmi_plat_data *pdata,
130 unsigned long mpixelclock);
faba6c3c
LP		 131};
132
b21f4b65 133struct dw_hdmi {
9aaf880e 134 struct drm_connector connector;
70c963ec 135 struct drm_bridge bridge;
9aaf880e 136
be41fc55
LP		 137 unsigned int version;
138
139 struct platform_device *audio;
a616e63c 140 struct platform_device *cec;
9aaf880e
FE		 141 struct device *dev;
142 struct clk *isfr_clk;
143 struct clk *iahb_clk;
ebe32c3e 144 struct clk *cec_clk;
3efc2fa3 145 struct dw_hdmi_i2c *i2c;
9aaf880e
FE		 146
147 struct hdmi_data_info hdmi_data;
b21f4b65
AY		 148 const struct dw_hdmi_plat_data *plat_data;
149
9aaf880e
FE		 150 int vic;
151
152 u8 edid[HDMI_EDID_LEN];
9aaf880e 153
f1585f6e
LP		 154 struct {
155 const struct dw_hdmi_phy_ops *ops;
156 const char *name;
157 void *data;
158 bool enabled;
159 } phy;
faba6c3c 160
9aaf880e
FE		 161 struct drm_display_mode previous_mode;
162
9aaf880e
FE		 163 struct i2c_adapter *ddc;
164 void __iomem *regs;
05b1342f 165 bool sink_is_hdmi;
f709ec07 166 bool sink_has_audio;
9aaf880e 167
50f9495e
DA		 168 struct pinctrl *pinctrl;
169 struct pinctrl_state *default_state;
170 struct pinctrl_state *unwedge_state;
171
b872a8e1 172 struct mutex mutex; /* for state below and previous_mode */
381f05a7 173 enum drm_connector_force force; /* mutex-protected force state */
b872a8e1 174 bool disabled; /* DRM has disabled our bridge */
381f05a7 175 bool bridge_is_on; /* indicates the bridge is on */
aeac23bd
RK		 176 bool rxsense; /* rxsense state */
177 u8 phy_mask; /* desired phy int mask settings */
7cc4ab22 178 u8 mc_clkdis; /* clock disable register */
b872a8e1 179
b90120a9 180 spinlock_t audio_lock;
6bcf4953 181 struct mutex audio_mutex;
9aaf880e 182 unsigned int sample_rate;
b90120a9
RK		 183 unsigned int audio_cts;
184 unsigned int audio_n;
185 bool audio_enable;
0cd9d142 186
80e2f979
NA		 187 unsigned int reg_shift;
188 struct regmap *regm;
a7d555d2
RP		 189 void (*enable_audio)(struct dw_hdmi *hdmi);
190 void (*disable_audio)(struct dw_hdmi *hdmi);
e84b8d75 191
7070fe73 192 struct mutex cec_notifier_mutex;
e84b8d75 193 struct cec_notifier *cec_notifier;
a9c82d63
CYC		 194
195 hdmi_codec_plugged_cb plugged_cb;
196 struct device *codec_dev;
197 enum drm_connector_status last_connector_result;
9aaf880e
FE		 198};
199
aeac23bd
RK		 200#define HDMI_IH_PHY_STAT0_RX_SENSE \
201 (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \
202 HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3)
203
204#define HDMI_PHY_RX_SENSE \
205 (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \
206 HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3)
207
0cd9d142
AY		 208static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
209{
80e2f979 210 regmap_write(hdmi->regm, offset << hdmi->reg_shift, val);
0cd9d142
AY		 211}
212
213static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
214{
80e2f979
NA		 215 unsigned int val = 0;
216
217 regmap_read(hdmi->regm, offset << hdmi->reg_shift, &val);
218
219 return val;
0cd9d142
AY		 220}
221
a9c82d63
CYC		 222static void handle_plugged_change(struct dw_hdmi *hdmi, bool plugged)
223{
224 if (hdmi->plugged_cb && hdmi->codec_dev)
225 hdmi->plugged_cb(hdmi->codec_dev, plugged);
226}
227
228int dw_hdmi_set_plugged_cb(struct dw_hdmi *hdmi, hdmi_codec_plugged_cb fn,
229 struct device *codec_dev)
230{
231 bool plugged;
232
233 mutex_lock(&hdmi->mutex);
234 hdmi->plugged_cb = fn;
235 hdmi->codec_dev = codec_dev;
236 plugged = hdmi->last_connector_result == connector_status_connected;
237 handle_plugged_change(hdmi, plugged);
238 mutex_unlock(&hdmi->mutex);
239
240 return 0;
241}
242EXPORT_SYMBOL_GPL(dw_hdmi_set_plugged_cb);
243
b21f4b65 244static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
812bc615 245{
80e2f979 246 regmap_update_bits(hdmi->regm, reg << hdmi->reg_shift, mask, data);
812bc615
RK		 247}
248
b21f4b65 249static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
b5878339 250 u8 shift, u8 mask)
9aaf880e 251{
812bc615 252 hdmi_modb(hdmi, data << shift, mask, reg);
9aaf880e
FE		 253}
254
3efc2fa3
VZ		 255static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi)
256{
99d02ed5
DA		 257 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
258 HDMI_PHY_I2CM_INT_ADDR);
259
260 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
261 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
262 HDMI_PHY_I2CM_CTLINT_ADDR);
263
3efc2fa3
VZ		 264 /* Software reset */
265 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ);
266
267 /* Set Standard Mode speed (determined to be 100KHz on iMX6) */
268 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_DIV);
269
270 /* Set done, not acknowledged and arbitration interrupt polarities */
271 hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT);
272 hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL,
273 HDMI_I2CM_CTLINT);
274
275 /* Clear DONE and ERROR interrupts */
276 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
277 HDMI_IH_I2CM_STAT0);
278
279 /* Mute DONE and ERROR interrupts */
280 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
281 HDMI_IH_MUTE_I2CM_STAT0);
282}
283
50f9495e
DA		 284static bool dw_hdmi_i2c_unwedge(struct dw_hdmi *hdmi)
285{
286 /* If no unwedge state then give up */
0bd79f91 287 if (!hdmi->unwedge_state)
50f9495e
DA		 288 return false;
289
290 dev_info(hdmi->dev, "Attempting to unwedge stuck i2c bus\n");
291
292 /*
293 * This is a huge hack to workaround a problem where the dw_hdmi i2c
294 * bus could sometimes get wedged. Once wedged there doesn't appear
295 * to be any way to unwedge it (including the HDMI_I2CM_SOFTRSTZ)
296 * other than pulsing the SDA line.
297 *
298 * We appear to be able to pulse the SDA line (in the eyes of dw_hdmi)
299 * by:
300 * 1. Remux the pin as a GPIO output, driven low.
301 * 2. Wait a little while. 1 ms seems to work, but we'll do 10.
302 * 3. Immediately jump to remux the pin as dw_hdmi i2c again.
303 *
304 * At the moment of remuxing, the line will still be low due to its
305 * recent stint as an output, but then it will be pulled high by the
306 * (presumed) external pullup. dw_hdmi seems to see this as a rising
307 * edge and that seems to get it out of its jam.
308 *
309 * This wedging was only ever seen on one TV, and only on one of
310 * its HDMI ports. It happened when the TV was powered on while the
311 * device was plugged in. A scope trace shows the TV bringing both SDA
312 * and SCL low, then bringing them both back up at roughly the same
313 * time. Presumably this confuses dw_hdmi because it saw activity but
314 * no real STOP (maybe it thinks there's another master on the bus?).
315 * Giving it a clean rising edge of SDA while SCL is already high
316 * presumably makes dw_hdmi see a STOP which seems to bring dw_hdmi out
317 * of its stupor.
318 *
319 * Note that after coming back alive, transfers seem to immediately
320 * resume, so if we unwedge due to a timeout we should wait a little
321 * longer for our transfer to finish, since it might have just started
322 * now.
323 */
324 pinctrl_select_state(hdmi->pinctrl, hdmi->unwedge_state);
325 msleep(10);
326 pinctrl_select_state(hdmi->pinctrl, hdmi->default_state);
327
328 return true;
329}
330
331static int dw_hdmi_i2c_wait(struct dw_hdmi *hdmi)
332{
333 struct dw_hdmi_i2c *i2c = hdmi->i2c;
334 int stat;
335
336 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
337 if (!stat) {
338 /* If we can't unwedge, return timeout */
339 if (!dw_hdmi_i2c_unwedge(hdmi))
340 return -EAGAIN;
341
342 /* We tried to unwedge; give it another chance */
343 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
344 if (!stat)
345 return -EAGAIN;
346 }
347
348 /* Check for error condition on the bus */
349 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
350 return -EIO;
351
352 return 0;
353}
354
3efc2fa3
VZ		 355static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi,
356 unsigned char *buf, unsigned int length)
357{
358 struct dw_hdmi_i2c *i2c = hdmi->i2c;
50f9495e 359 int ret;
3efc2fa3
VZ		 360
361 if (!i2c->is_regaddr) {
362 dev_dbg(hdmi->dev, "set read register address to 0\n");
363 i2c->slave_reg = 0x00;
364 i2c->is_regaddr = true;
365 }
366
367 while (length--) {
368 reinit_completion(&i2c->cmp);
369
370 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
94bb4dc1
NY		 371 if (i2c->is_segment)
372 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT,
373 HDMI_I2CM_OPERATION);
374 else
375 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
376 HDMI_I2CM_OPERATION);
3efc2fa3 377
50f9495e
DA		 378 ret = dw_hdmi_i2c_wait(hdmi);
379 if (ret)
380 return ret;
3efc2fa3
VZ		 381
382 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI);
383 }
94bb4dc1 384 i2c->is_segment = false;
3efc2fa3
VZ		 385
386 return 0;
387}
388
389static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi,
390 unsigned char *buf, unsigned int length)
391{
392 struct dw_hdmi_i2c *i2c = hdmi->i2c;
50f9495e 393 int ret;
3efc2fa3
VZ		 394
395 if (!i2c->is_regaddr) {
396 /* Use the first write byte as register address */
397 i2c->slave_reg = buf[0];
398 length--;
399 buf++;
400 i2c->is_regaddr = true;
401 }
402
403 while (length--) {
404 reinit_completion(&i2c->cmp);
405
406 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO);
407 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
408 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE,
409 HDMI_I2CM_OPERATION);
410
50f9495e
DA		 411 ret = dw_hdmi_i2c_wait(hdmi);
412 if (ret)
413 return ret;
3efc2fa3
VZ		 414 }
415
416 return 0;
417}
418
419static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap,
420 struct i2c_msg *msgs, int num)
421{
422 struct dw_hdmi *hdmi = i2c_get_adapdata(adap);
423 struct dw_hdmi_i2c *i2c = hdmi->i2c;
424 u8 addr = msgs[0].addr;
425 int i, ret = 0;
426
427 dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr);
428
429 for (i = 0; i < num; i++) {
3efc2fa3
VZ		 430 if (msgs[i].len == 0) {
431 dev_dbg(hdmi->dev,
432 "unsupported transfer %d/%d, no data\n",
433 i + 1, num);
434 return -EOPNOTSUPP;
435 }
436 }
437
438 mutex_lock(&i2c->lock);
439
440 /* Unmute DONE and ERROR interrupts */
441 hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0);
442
443 /* Set slave device address taken from the first I2C message */
444 hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE);
445
446 /* Set slave device register address on transfer */
447 i2c->is_regaddr = false;
448
94bb4dc1
NY		 449 /* Set segment pointer for I2C extended read mode operation */
450 i2c->is_segment = false;
451
3efc2fa3
VZ		 452 for (i = 0; i < num; i++) {
453 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n",
454 i + 1, num, msgs[i].len, msgs[i].flags);
94bb4dc1
NY		 455 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) {
456 i2c->is_segment = true;
457 hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR);
458 hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR);
459 } else {
460 if (msgs[i].flags & I2C_M_RD)
461 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf,
462 msgs[i].len);
463 else
464 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf,
465 msgs[i].len);
466 }
3efc2fa3
VZ		 467 if (ret < 0)
468 break;
469 }
470
471 if (!ret)
472 ret = num;
473
474 /* Mute DONE and ERROR interrupts */
475 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
476 HDMI_IH_MUTE_I2CM_STAT0);
477
478 mutex_unlock(&i2c->lock);
479
480 return ret;
481}
482
483static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter)
484{
485 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
486}
487
488static const struct i2c_algorithm dw_hdmi_algorithm = {
489 .master_xfer = dw_hdmi_i2c_xfer,
490 .functionality = dw_hdmi_i2c_func,
491};
492
493static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi)
494{
495 struct i2c_adapter *adap;
496 struct dw_hdmi_i2c *i2c;
497 int ret;
498
499 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
500 if (!i2c)
501 return ERR_PTR(-ENOMEM);
502
503 mutex_init(&i2c->lock);
504 init_completion(&i2c->cmp);
505
506 adap = &i2c->adap;
507 adap->class = I2C_CLASS_DDC;
508 adap->owner = THIS_MODULE;
509 adap->dev.parent = hdmi->dev;
510 adap->algo = &dw_hdmi_algorithm;
511 strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name));
512 i2c_set_adapdata(adap, hdmi);
513
514 ret = i2c_add_adapter(adap);
515 if (ret) {
516 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
517 devm_kfree(hdmi->dev, i2c);
518 return ERR_PTR(ret);
519 }
520
521 hdmi->i2c = i2c;
522
523 dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
524
525 return adap;
526}
527
351e1354
RK		 528static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
529 unsigned int n)
9aaf880e 530{
622494a3
RK		 531 /* Must be set/cleared first */
532 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
9aaf880e
FE		 533
534 /* nshift factor = 0 */
812bc615 535 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
9aaf880e 536
fdbdcc83
NA		 537 /* Use automatic CTS generation mode when CTS is not set */
538 if (cts)
539 hdmi_writeb(hdmi, ((cts >> 16) &
540 HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
541 HDMI_AUD_CTS3_CTS_MANUAL,
542 HDMI_AUD_CTS3);
543 else
544 hdmi_writeb(hdmi, 0, HDMI_AUD_CTS3);
622494a3
RK		 545 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
546 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
547
548 hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
549 hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
550 hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
9aaf880e
FE		 551}
552
b195fbdb 553static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk)
9aaf880e
FE		 554{
555 unsigned int n = (128 * freq) / 1000;
d0c96d16
RK		 556 unsigned int mult = 1;
557
558 while (freq > 48000) {
559 mult *= 2;
560 freq /= 2;
561 }
9aaf880e
FE		 562
563 switch (freq) {
564 case 32000:
426701d0 565 if (pixel_clk == 25175000)
b195fbdb 566 n = 4576;
426701d0 567 else if (pixel_clk == 27027000)
b195fbdb 568 n = 4096;
426701d0 569 else if (pixel_clk == 74176000 || pixel_clk == 148352000)
9aaf880e
FE		 570 n = 11648;
571 else
572 n = 4096;
d0c96d16 573 n *= mult;
9aaf880e
FE		 574 break;
575
576 case 44100:
426701d0 577 if (pixel_clk == 25175000)
9aaf880e 578 n = 7007;
426701d0 579 else if (pixel_clk == 74176000)
9aaf880e 580 n = 17836;
426701d0 581 else if (pixel_clk == 148352000)
b195fbdb 582 n = 8918;
9aaf880e
FE		 583 else
584 n = 6272;
d0c96d16 585 n *= mult;
9aaf880e
FE		 586 break;
587
588 case 48000:
426701d0 589 if (pixel_clk == 25175000)
b195fbdb 590 n = 6864;
426701d0 591 else if (pixel_clk == 27027000)
b195fbdb 592 n = 6144;
426701d0 593 else if (pixel_clk == 74176000)
9aaf880e 594 n = 11648;
426701d0 595 else if (pixel_clk == 148352000)
b195fbdb 596 n = 5824;
9aaf880e
FE		 597 else
598 n = 6144;
d0c96d16 599 n *= mult;
9aaf880e
FE		 600 break;
601
602 default:
603 break;
604 }
605
606 return n;
607}
608
b21f4b65 609static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
b195fbdb 610 unsigned long pixel_clk, unsigned int sample_rate)
9aaf880e 611{
dfbdaf50 612 unsigned long ftdms = pixel_clk;
f879b38f 613 unsigned int n, cts;
fdbdcc83 614 u8 config3;
dfbdaf50 615 u64 tmp;
9aaf880e 616
b195fbdb 617 n = hdmi_compute_n(sample_rate, pixel_clk);
9aaf880e 618
fdbdcc83
NA		 619 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID);
620
621 /* Only compute CTS when using internal AHB audio */
622 if (config3 & HDMI_CONFIG3_AHBAUDDMA) {
623 /*
624 * Compute the CTS value from the N value. Note that CTS and N
625 * can be up to 20 bits in total, so we need 64-bit math. Also
626 * note that our TDMS clock is not fully accurate; it is
627 * accurate to kHz. This can introduce an unnecessary remainder
628 * in the calculation below, so we don't try to warn about that.
629 */
630 tmp = (u64)ftdms * n;
631 do_div(tmp, 128 * sample_rate);
632 cts = tmp;
633
634 dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
635 __func__, sample_rate,
636 ftdms / 1000000, (ftdms / 1000) % 1000,
637 n, cts);
638 } else {
639 cts = 0;
640 }
9aaf880e 641
b90120a9
RK		 642 spin_lock_irq(&hdmi->audio_lock);
643 hdmi->audio_n = n;
644 hdmi->audio_cts = cts;
645 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
646 spin_unlock_irq(&hdmi->audio_lock);
9aaf880e
FE		 647}
648
b21f4b65 649static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
9aaf880e 650{
6bcf4953 651 mutex_lock(&hdmi->audio_mutex);
b195fbdb 652 hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate);
6bcf4953 653 mutex_unlock(&hdmi->audio_mutex);
9aaf880e
FE		 654}
655
b21f4b65 656static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
9aaf880e 657{
6bcf4953 658 mutex_lock(&hdmi->audio_mutex);
ba9877e2 659 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock,
b195fbdb 660 hdmi->sample_rate);
6bcf4953 661 mutex_unlock(&hdmi->audio_mutex);
9aaf880e
FE		 662}
663
b5814fff
RK		 664void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
665{
666 mutex_lock(&hdmi->audio_mutex);
667 hdmi->sample_rate = rate;
ba9877e2 668 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock,
b195fbdb 669 hdmi->sample_rate);
b5814fff
RK		 670 mutex_unlock(&hdmi->audio_mutex);
671}
672EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate);
673
2a2a3d2f
JB		 674void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt)
675{
676 u8 layout;
677
678 mutex_lock(&hdmi->audio_mutex);
679
680 /*
681 * For >2 channel PCM audio, we need to select layout 1
682 * and set an appropriate channel map.
683 */
684 if (cnt > 2)
685 layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1;
686 else
687 layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0;
688
689 hdmi_modb(hdmi, layout, HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK,
690 HDMI_FC_AUDSCONF);
691
da5f5bc9
JB		 692 /* Set the audio infoframes channel count */
693 hdmi_modb(hdmi, (cnt - 1) << HDMI_FC_AUDICONF0_CC_OFFSET,
694 HDMI_FC_AUDICONF0_CC_MASK, HDMI_FC_AUDICONF0);
695
2a2a3d2f
JB		 696 mutex_unlock(&hdmi->audio_mutex);
697}
698EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_count);
699
700void dw_hdmi_set_channel_allocation(struct dw_hdmi *hdmi, unsigned int ca)
701{
702 mutex_lock(&hdmi->audio_mutex);
703
704 hdmi_writeb(hdmi, ca, HDMI_FC_AUDICONF2);
705
706 mutex_unlock(&hdmi->audio_mutex);
707}
708EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_allocation);
709
57fbc055
RP		 710static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi, bool enable)
711{
7cc4ab22
RK		 712 if (enable)
713 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE;
714 else
715 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_AUDCLK_DISABLE;
716 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
57fbc055
RP		 717}
718
a7d555d2
RP		 719static void dw_hdmi_ahb_audio_enable(struct dw_hdmi *hdmi)
720{
721 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
722}
723
724static void dw_hdmi_ahb_audio_disable(struct dw_hdmi *hdmi)
725{
726 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
727}
728
729static void dw_hdmi_i2s_audio_enable(struct dw_hdmi *hdmi)
730{
731 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
57fbc055
RP		 732 hdmi_enable_audio_clk(hdmi, true);
733}
734
735static void dw_hdmi_i2s_audio_disable(struct dw_hdmi *hdmi)
736{
737 hdmi_enable_audio_clk(hdmi, false);
a7d555d2
RP		 738}
739
b90120a9
RK		 740void dw_hdmi_audio_enable(struct dw_hdmi *hdmi)
741{
742 unsigned long flags;
743
744 spin_lock_irqsave(&hdmi->audio_lock, flags);
745 hdmi->audio_enable = true;
a7d555d2
RP		 746 if (hdmi->enable_audio)
747 hdmi->enable_audio(hdmi);
b90120a9
RK		 748 spin_unlock_irqrestore(&hdmi->audio_lock, flags);
749}
750EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable);
751
752void dw_hdmi_audio_disable(struct dw_hdmi *hdmi)
753{
754 unsigned long flags;
755
756 spin_lock_irqsave(&hdmi->audio_lock, flags);
757 hdmi->audio_enable = false;
a7d555d2
RP		 758 if (hdmi->disable_audio)
759 hdmi->disable_audio(hdmi);
b90120a9
RK		 760 spin_unlock_irqrestore(&hdmi->audio_lock, flags);
761}
762EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable);
763
def23aa7
NA		 764static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format)
765{
766 switch (bus_format) {
767 case MEDIA_BUS_FMT_RGB888_1X24:
768 case MEDIA_BUS_FMT_RGB101010_1X30:
769 case MEDIA_BUS_FMT_RGB121212_1X36:
770 case MEDIA_BUS_FMT_RGB161616_1X48:
771 return true;
772
773 default:
774 return false;
775 }
776}
777
778static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format)
779{
780 switch (bus_format) {
781 case MEDIA_BUS_FMT_YUV8_1X24:
782 case MEDIA_BUS_FMT_YUV10_1X30:
783 case MEDIA_BUS_FMT_YUV12_1X36:
784 case MEDIA_BUS_FMT_YUV16_1X48:
785 return true;
786
787 default:
788 return false;
789 }
790}
791
792static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format)
793{
794 switch (bus_format) {
795 case MEDIA_BUS_FMT_UYVY8_1X16:
796 case MEDIA_BUS_FMT_UYVY10_1X20:
797 case MEDIA_BUS_FMT_UYVY12_1X24:
798 return true;
799
800 default:
801 return false;
802 }
803}
804
ba9877e2
NA		 805static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format)
806{
807 switch (bus_format) {
808 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
809 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
810 case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
811 case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
812 return true;
813
814 default:
815 return false;
816 }
817}
818
def23aa7
NA		 819static int hdmi_bus_fmt_color_depth(unsigned int bus_format)
820{
821 switch (bus_format) {
822 case MEDIA_BUS_FMT_RGB888_1X24:
823 case MEDIA_BUS_FMT_YUV8_1X24:
824 case MEDIA_BUS_FMT_UYVY8_1X16:
825 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
826 return 8;
827
828 case MEDIA_BUS_FMT_RGB101010_1X30:
829 case MEDIA_BUS_FMT_YUV10_1X30:
830 case MEDIA_BUS_FMT_UYVY10_1X20:
831 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
832 return 10;
833
834 case MEDIA_BUS_FMT_RGB121212_1X36:
835 case MEDIA_BUS_FMT_YUV12_1X36:
836 case MEDIA_BUS_FMT_UYVY12_1X24:
837 case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
838 return 12;
839
840 case MEDIA_BUS_FMT_RGB161616_1X48:
841 case MEDIA_BUS_FMT_YUV16_1X48:
842 case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
843 return 16;
844
845 default:
846 return 0;
847 }
848}
849
9aaf880e
FE		 850/*
851 * this submodule is responsible for the video data synchronization.
852 * for example, for RGB 4:4:4 input, the data map is defined as
853 * pin{47~40} <==> R[7:0]
854 * pin{31~24} <==> G[7:0]
855 * pin{15~8} <==> B[7:0]
856 */
b21f4b65 857static void hdmi_video_sample(struct dw_hdmi *hdmi)
9aaf880e
FE		 858{
859 int color_format = 0;
860 u8 val;
861
def23aa7
NA		 862 switch (hdmi->hdmi_data.enc_in_bus_format) {
863 case MEDIA_BUS_FMT_RGB888_1X24:
864 color_format = 0x01;
865 break;
866 case MEDIA_BUS_FMT_RGB101010_1X30:
867 color_format = 0x03;
868 break;
869 case MEDIA_BUS_FMT_RGB121212_1X36:
870 color_format = 0x05;
871 break;
872 case MEDIA_BUS_FMT_RGB161616_1X48:
873 color_format = 0x07;
874 break;
875
876 case MEDIA_BUS_FMT_YUV8_1X24:
877 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
878 color_format = 0x09;
879 break;
880 case MEDIA_BUS_FMT_YUV10_1X30:
881 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
882 color_format = 0x0B;
883 break;
884 case MEDIA_BUS_FMT_YUV12_1X36:
885 case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
886 color_format = 0x0D;
887 break;
888 case MEDIA_BUS_FMT_YUV16_1X48:
889 case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
890 color_format = 0x0F;
891 break;
892
893 case MEDIA_BUS_FMT_UYVY8_1X16:
894 color_format = 0x16;
895 break;
896 case MEDIA_BUS_FMT_UYVY10_1X20:
897 color_format = 0x14;
898 break;
899 case MEDIA_BUS_FMT_UYVY12_1X24:
900 color_format = 0x12;
901 break;
902
903 default:
904 return;
9aaf880e
FE		 905 }
906
907 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
908 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
909 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
910 hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
911
912 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
913 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
914 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
915 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
916 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
917 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
918 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
919 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
920 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
921 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
922 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
923}
924
b21f4b65 925static int is_color_space_conversion(struct dw_hdmi *hdmi)
9aaf880e 926{
def23aa7 927 return hdmi->hdmi_data.enc_in_bus_format != hdmi->hdmi_data.enc_out_bus_format;
9aaf880e
FE		 928}
929
b21f4b65 930static int is_color_space_decimation(struct dw_hdmi *hdmi)
9aaf880e 931{
def23aa7 932 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
ba92b225 933 return 0;
def23aa7
NA		 934
935 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) ||
936 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format))
ba92b225 937 return 1;
def23aa7 938
ba92b225 939 return 0;
9aaf880e
FE		 940}
941
b21f4b65 942static int is_color_space_interpolation(struct dw_hdmi *hdmi)
9aaf880e 943{
def23aa7 944 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format))
ba92b225 945 return 0;
def23aa7
NA		 946
947 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
948 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
ba92b225 949 return 1;
def23aa7 950
ba92b225 951 return 0;
9aaf880e
FE		 952}
953
b21f4b65 954static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
9aaf880e
FE		 955{
956 const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
c082f9d7 957 unsigned i;
9aaf880e 958 u32 csc_scale = 1;
9aaf880e
FE		 959
960 if (is_color_space_conversion(hdmi)) {
def23aa7
NA		 961 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
962 if (hdmi->hdmi_data.enc_out_encoding ==
963 V4L2_YCBCR_ENC_601)
9aaf880e
FE		 964 csc_coeff = &csc_coeff_rgb_out_eitu601;
965 else
966 csc_coeff = &csc_coeff_rgb_out_eitu709;
def23aa7
NA		 967 } else if (hdmi_bus_fmt_is_rgb(
968 hdmi->hdmi_data.enc_in_bus_format)) {
969 if (hdmi->hdmi_data.enc_out_encoding ==
970 V4L2_YCBCR_ENC_601)
9aaf880e
FE		 971 csc_coeff = &csc_coeff_rgb_in_eitu601;
972 else
973 csc_coeff = &csc_coeff_rgb_in_eitu709;
974 csc_scale = 0;
975 }
976 }
977
c082f9d7
RK		 978 /* The CSC registers are sequential, alternating MSB then LSB */
979 for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
980 u16 coeff_a = (*csc_coeff)[0][i];
981 u16 coeff_b = (*csc_coeff)[1][i];
982 u16 coeff_c = (*csc_coeff)[2][i];
983
b5878339 984 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
c082f9d7
RK		 985 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
986 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
987 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
b5878339 988 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
c082f9d7
RK		 989 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
990 }
9aaf880e 991
812bc615
RK		 992 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
993 HDMI_CSC_SCALE);
9aaf880e
FE		 994}
995
b21f4b65 996static void hdmi_video_csc(struct dw_hdmi *hdmi)
9aaf880e
FE		 997{
998 int color_depth = 0;
999 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
1000 int decimation = 0;
9aaf880e
FE		 1001
1002 /* YCC422 interpolation to 444 mode */
1003 if (is_color_space_interpolation(hdmi))
1004 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
1005 else if (is_color_space_decimation(hdmi))
1006 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
1007
def23aa7
NA		 1008 switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) {
1009 case 8:
9aaf880e 1010 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
def23aa7
NA		 1011 break;
1012 case 10:
9aaf880e 1013 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
def23aa7
NA		 1014 break;
1015 case 12:
9aaf880e 1016 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
def23aa7
NA		 1017 break;
1018 case 16:
9aaf880e 1019 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
def23aa7
NA		 1020 break;
1021
1022 default:
9aaf880e 1023 return;
def23aa7 1024 }
9aaf880e
FE		 1025
1026 /* Configure the CSC registers */
1027 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
812bc615
RK		 1028 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
1029 HDMI_CSC_SCALE);
9aaf880e 1030
b21f4b65 1031 dw_hdmi_update_csc_coeffs(hdmi);
9aaf880e
FE		 1032}
1033
1034/*
1035 * HDMI video packetizer is used to packetize the data.
1036 * for example, if input is YCC422 mode or repeater is used,
1037 * data should be repacked this module can be bypassed.
1038 */
b21f4b65 1039static void hdmi_video_packetize(struct dw_hdmi *hdmi)
9aaf880e
FE		 1040{
1041 unsigned int color_depth = 0;
1042 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
1043 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
1044 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
bebdf664 1045 u8 val, vp_conf;
9aaf880e 1046
def23aa7 1047 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
ba9877e2
NA		 1048 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format) ||
1049 hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) {
def23aa7
NA		 1050 switch (hdmi_bus_fmt_color_depth(
1051 hdmi->hdmi_data.enc_out_bus_format)) {
1052 case 8:
9aaf880e
FE		 1053 color_depth = 4;
1054 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
def23aa7
NA		 1055 break;
1056 case 10:
9aaf880e 1057 color_depth = 5;
def23aa7
NA		 1058 break;
1059 case 12:
9aaf880e 1060 color_depth = 6;
def23aa7
NA		 1061 break;
1062 case 16:
9aaf880e 1063 color_depth = 7;
def23aa7
NA		 1064 break;
1065 default:
1066 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
b5878339 1067 }
def23aa7
NA		 1068 } else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) {
1069 switch (hdmi_bus_fmt_color_depth(
1070 hdmi->hdmi_data.enc_out_bus_format)) {
1071 case 0:
1072 case 8:
9aaf880e 1073 remap_size = HDMI_VP_REMAP_YCC422_16bit;
def23aa7
NA		 1074 break;
1075 case 10:
9aaf880e 1076 remap_size = HDMI_VP_REMAP_YCC422_20bit;
def23aa7
NA		 1077 break;
1078 case 12:
9aaf880e 1079 remap_size = HDMI_VP_REMAP_YCC422_24bit;
def23aa7
NA		 1080 break;
1081
1082 default:
9aaf880e 1083 return;
def23aa7 1084 }
9aaf880e 1085 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
b5878339 1086 } else {
9aaf880e 1087 return;
b5878339 1088 }
9aaf880e
FE		 1089
1090 /* set the packetizer registers */
1091 val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
1092 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
1093 ((hdmi_data->pix_repet_factor <<
1094 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
1095 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
1096 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
1097
812bc615
RK		 1098 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
1099 HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
9aaf880e
FE		 1100
1101 /* Data from pixel repeater block */
1102 if (hdmi_data->pix_repet_factor > 1) {
bebdf664
RK		 1103 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
1104 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
9aaf880e 1105 } else { /* data from packetizer block */
bebdf664
RK		 1106 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
1107 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
9aaf880e
FE		 1108 }
1109
bebdf664
RK		 1110 hdmi_modb(hdmi, vp_conf,
1111 HDMI_VP_CONF_PR_EN_MASK |
1112 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
1113
812bc615
RK		 1114 hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
1115 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
9aaf880e
FE		 1116
1117 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
1118
1119 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
bebdf664
RK		 1120 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
1121 HDMI_VP_CONF_PP_EN_ENABLE |
1122 HDMI_VP_CONF_YCC422_EN_DISABLE;
9aaf880e 1123 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
bebdf664
RK		 1124 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
1125 HDMI_VP_CONF_PP_EN_DISABLE |
1126 HDMI_VP_CONF_YCC422_EN_ENABLE;
9aaf880e 1127 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
bebdf664
RK		 1128 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
1129 HDMI_VP_CONF_PP_EN_DISABLE |
1130 HDMI_VP_CONF_YCC422_EN_DISABLE;
9aaf880e
FE		 1131 } else {
1132 return;
1133 }
1134
bebdf664
RK		 1135 hdmi_modb(hdmi, vp_conf,
1136 HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
1137 HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
1138
812bc615
RK		 1139 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
1140 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
1141 HDMI_VP_STUFF_PP_STUFFING_MASK |
1142 HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
9aaf880e 1143
812bc615
RK		 1144 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
1145 HDMI_VP_CONF);
9aaf880e
FE		 1146}
1147
f1585f6e
LP		 1148/* -----------------------------------------------------------------------------
1149 * Synopsys PHY Handling
1150 */
1151
b21f4b65 1152static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
b5878339 1153 unsigned char bit)
9aaf880e 1154{
812bc615
RK		 1155 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
1156 HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
9aaf880e
FE		 1157}
1158
b21f4b65 1159static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
9aaf880e 1160{
a4d3b8b0
AY		 1161 u32 val;
1162
1163 while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
9aaf880e
FE		 1164 if (msec-- == 0)
1165 return false;
0e6bcf3a 1166 udelay(1000);
9aaf880e 1167 }
a4d3b8b0
AY		 1168 hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
1169
9aaf880e
FE		 1170 return true;
1171}
1172
2ef9dfed
KB		 1173void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
1174 unsigned char addr)
9aaf880e
FE		 1175{
1176 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
1177 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
1178 hdmi_writeb(hdmi, (unsigned char)(data >> 8),
b5878339 1179 HDMI_PHY_I2CM_DATAO_1_ADDR);
9aaf880e 1180 hdmi_writeb(hdmi, (unsigned char)(data >> 0),
b5878339 1181 HDMI_PHY_I2CM_DATAO_0_ADDR);
9aaf880e 1182 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
b5878339 1183 HDMI_PHY_I2CM_OPERATION_ADDR);
9aaf880e
FE		 1184 hdmi_phy_wait_i2c_done(hdmi, 1000);
1185}
2ef9dfed 1186EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_write);
9aaf880e 1187
836f90f9
NA		 1188/* Filter out invalid setups to avoid configuring SCDC and scrambling */
1189static bool dw_hdmi_support_scdc(struct dw_hdmi *hdmi)
1190{
1191 struct drm_display_info *display = &hdmi->connector.display_info;
1192
1193 /* Completely disable SCDC support for older controllers */
1194 if (hdmi->version < 0x200a)
1195 return false;
1196
c4cba44e
JK		 1197 /* Disable if no DDC bus */
1198 if (!hdmi->ddc)
1199 return false;
1200
836f90f9
NA		 1201 /* Disable if SCDC is not supported, or if an HF-VSDB block is absent */
1202 if (!display->hdmi.scdc.supported ||
1203 !display->hdmi.scdc.scrambling.supported)
1204 return false;
1205
1206 /*
1207 * Disable if display only support low TMDS rates and scrambling
1208 * for low rates is not supported either
1209 */
1210 if (!display->hdmi.scdc.scrambling.low_rates &&
1211 display->max_tmds_clock <= 340000)
1212 return false;
1213
1214 return true;
1215}
1216
264fce6c
NA		 1217/*
1218 * HDMI2.0 Specifies the following procedure for High TMDS Bit Rates:
1219 * - The Source shall suspend transmission of the TMDS clock and data
1220 * - The Source shall write to the TMDS_Bit_Clock_Ratio bit to change it
1221 * from a 0 to a 1 or from a 1 to a 0
1222 * - The Source shall allow a minimum of 1 ms and a maximum of 100 ms from
1223 * the time the TMDS_Bit_Clock_Ratio bit is written until resuming
1224 * transmission of TMDS clock and data
1225 *
1226 * To respect the 100ms maximum delay, the dw_hdmi_set_high_tmds_clock_ratio()
1227 * helper should called right before enabling the TMDS Clock and Data in
1228 * the PHY configuration callback.
1229 */
1230void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi)
1231{
ba9877e2 1232 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock;
264fce6c
NA		 1233
1234 /* Control for TMDS Bit Period/TMDS Clock-Period Ratio */
836f90f9 1235 if (dw_hdmi_support_scdc(hdmi)) {
264fce6c
NA		 1236 if (mtmdsclock > HDMI14_MAX_TMDSCLK)
1237 drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 1);
1238 else
1239 drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 0);
1240 }
1241}
1242EXPORT_SYMBOL_GPL(dw_hdmi_set_high_tmds_clock_ratio);
1243
2fada109 1244static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable)
9aaf880e 1245{
2fada109 1246 hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0,
9aaf880e
FE		 1247 HDMI_PHY_CONF0_PDZ_OFFSET,
1248 HDMI_PHY_CONF0_PDZ_MASK);
1249}
1250
b21f4b65 1251static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
9aaf880e
FE		 1252{
1253 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1254 HDMI_PHY_CONF0_ENTMDS_OFFSET,
1255 HDMI_PHY_CONF0_ENTMDS_MASK);
1256}
1257
f4104e8f 1258static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable)
d346c14e
AY		 1259{
1260 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
f4104e8f
LP		 1261 HDMI_PHY_CONF0_SVSRET_OFFSET,
1262 HDMI_PHY_CONF0_SVSRET_MASK);
d346c14e
AY		 1263}
1264
5765916a 1265void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
9aaf880e
FE		 1266{
1267 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1268 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
1269 HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
1270}
5765916a 1271EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_pddq);
9aaf880e 1272
5765916a 1273void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
9aaf880e
FE		 1274{
1275 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1276 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
1277 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
1278}
5765916a 1279EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_txpwron);
9aaf880e 1280
b21f4b65 1281static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
9aaf880e
FE		 1282{
1283 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1284 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
1285 HDMI_PHY_CONF0_SELDATAENPOL_MASK);
1286}
1287
b21f4b65 1288static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
9aaf880e
FE		 1289{
1290 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1291 HDMI_PHY_CONF0_SELDIPIF_OFFSET,
1292 HDMI_PHY_CONF0_SELDIPIF_MASK);
1293}
1294
5765916a
JS		 1295void dw_hdmi_phy_reset(struct dw_hdmi *hdmi)
1296{
1297 /* PHY reset. The reset signal is active high on Gen2 PHYs. */
1298 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ);
1299 hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ);
1300}
1301EXPORT_SYMBOL_GPL(dw_hdmi_phy_reset);
1302
1303void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address)
1304{
1305 hdmi_phy_test_clear(hdmi, 1);
1306 hdmi_writeb(hdmi, address, HDMI_PHY_I2CM_SLAVE_ADDR);
1307 hdmi_phy_test_clear(hdmi, 0);
1308}
1309EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_set_addr);
1310
b0e583e5
LP		 1311static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi)
1312{
f1585f6e 1313 const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
b0e583e5
LP		 1314 unsigned int i;
1315 u16 val;
1316
1317 if (phy->gen == 1) {
1318 dw_hdmi_phy_enable_tmds(hdmi, 0);
1319 dw_hdmi_phy_enable_powerdown(hdmi, true);
1320 return;
1321 }
1322
1323 dw_hdmi_phy_gen2_txpwron(hdmi, 0);
1324
1325 /*
1326 * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went
1327 * to low power mode.
1328 */
1329 for (i = 0; i < 5; ++i) {
1330 val = hdmi_readb(hdmi, HDMI_PHY_STAT0);
1331 if (!(val & HDMI_PHY_TX_PHY_LOCK))
1332 break;
1333
1334 usleep_range(1000, 2000);
1335 }
1336
1337 if (val & HDMI_PHY_TX_PHY_LOCK)
1338 dev_warn(hdmi->dev, "PHY failed to power down\n");
1339 else
1340 dev_dbg(hdmi->dev, "PHY powered down in %u iterations\n", i);
1341
1342 dw_hdmi_phy_gen2_pddq(hdmi, 1);
1343}
1344
181e0ef0
LP		 1345static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi)
1346{
f1585f6e 1347 const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
181e0ef0
LP		 1348 unsigned int i;
1349 u8 val;
1350
1351 if (phy->gen == 1) {
1352 dw_hdmi_phy_enable_powerdown(hdmi, false);
1353
1354 /* Toggle TMDS enable. */
1355 dw_hdmi_phy_enable_tmds(hdmi, 0);
1356 dw_hdmi_phy_enable_tmds(hdmi, 1);
1357 return 0;
1358 }
1359
1360 dw_hdmi_phy_gen2_txpwron(hdmi, 1);
1361 dw_hdmi_phy_gen2_pddq(hdmi, 0);
1362
1363 /* Wait for PHY PLL lock */
1364 for (i = 0; i < 5; ++i) {
1365 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
1366 if (val)
1367 break;
1368
1369 usleep_range(1000, 2000);
1370 }
1371
1372 if (!val) {
1373 dev_err(hdmi->dev, "PHY PLL failed to lock\n");
1374 return -ETIMEDOUT;
1375 }
1376
1377 dev_dbg(hdmi->dev, "PHY PLL locked %u iterations\n", i);
1378 return 0;
1379}
1380
2ef9dfed
KB		 1381/*
1382 * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available
1383 * information the DWC MHL PHY has the same register layout and is thus also
1384 * supported by this function.
1385 */
1386static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi,
1387 const struct dw_hdmi_plat_data *pdata,
1388 unsigned long mpixelclock)
9aaf880e 1389{
39cc1535
RK		 1390 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
1391 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
1392 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
9aaf880e 1393
ba9877e2
NA		 1394 /* TOFIX Will need 420 specific PHY configuration tables */
1395
39cc1535
RK		 1396 /* PLL/MPLL Cfg - always match on final entry */
1397 for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
2ef9dfed 1398 if (mpixelclock <= mpll_config->mpixelclock)
39cc1535
RK		 1399 break;
1400
1401 for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
2ef9dfed 1402 if (mpixelclock <= curr_ctrl->mpixelclock)
39cc1535
RK		 1403 break;
1404
1405 for (; phy_config->mpixelclock != ~0UL; phy_config++)
2ef9dfed 1406 if (mpixelclock <= phy_config->mpixelclock)
39cc1535
RK		 1407 break;
1408
1409 if (mpll_config->mpixelclock == ~0UL ||
1410 curr_ctrl->mpixelclock == ~0UL ||
2ef9dfed 1411 phy_config->mpixelclock == ~0UL)
39cc1535 1412 return -EINVAL;
2ef9dfed
KB		 1413
1414 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce,
1415 HDMI_3D_TX_PHY_CPCE_CTRL);
1416 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp,
1417 HDMI_3D_TX_PHY_GMPCTRL);
1418 dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0],
1419 HDMI_3D_TX_PHY_CURRCTRL);
1420
1421 dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL);
1422 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK,
1423 HDMI_3D_TX_PHY_MSM_CTRL);
1424
1425 dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM);
1426 dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr,
1427 HDMI_3D_TX_PHY_CKSYMTXCTRL);
1428 dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr,
1429 HDMI_3D_TX_PHY_VLEVCTRL);
1430
1431 /* Override and disable clock termination. */
1432 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE,
1433 HDMI_3D_TX_PHY_CKCALCTRL);
1434
1435 return 0;
1436}
1437
1438static int hdmi_phy_configure(struct dw_hdmi *hdmi)
1439{
1440 const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1441 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
1442 unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock;
ba9877e2 1443 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock;
2ef9dfed 1444 int ret;
39cc1535 1445
b0e583e5 1446 dw_hdmi_phy_power_off(hdmi);
9aaf880e 1447
264fce6c
NA		 1448 dw_hdmi_set_high_tmds_clock_ratio(hdmi);
1449
2668db37 1450 /* Leave low power consumption mode by asserting SVSRET. */
f1585f6e 1451 if (phy->has_svsret)
2668db37
LP		 1452 dw_hdmi_phy_enable_svsret(hdmi, 1);
1453
5765916a 1454 dw_hdmi_phy_reset(hdmi);
9aaf880e
FE		 1455
1456 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
1457
5765916a 1458 dw_hdmi_phy_i2c_set_addr(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2);
9aaf880e 1459
2ef9dfed
KB		 1460 /* Write to the PHY as configured by the platform */
1461 if (pdata->configure_phy)
1462 ret = pdata->configure_phy(hdmi, pdata, mpixelclock);
1463 else
1464 ret = phy->configure(hdmi, pdata, mpixelclock);
1465 if (ret) {
1466 dev_err(hdmi->dev, "PHY configuration failed (clock %lu)\n",
1467 mpixelclock);
1468 return ret;
1469 }
9aaf880e 1470
264fce6c 1471 /* Wait for resuming transmission of TMDS clock and data */
ba9877e2 1472 if (mtmdsclock > HDMI14_MAX_TMDSCLK)
264fce6c
NA		 1473 msleep(100);
1474
181e0ef0 1475 return dw_hdmi_phy_power_on(hdmi);
9aaf880e
FE		 1476}
1477
f1585f6e
LP		 1478static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data,
1479 struct drm_display_mode *mode)
9aaf880e
FE		 1480{
1481 int i, ret;
9aaf880e
FE		 1482
1483 /* HDMI Phy spec says to do the phy initialization sequence twice */
1484 for (i = 0; i < 2; i++) {
b21f4b65
AY		 1485 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
1486 dw_hdmi_phy_sel_interface_control(hdmi, 0);
9aaf880e 1487
8b9e1c0d 1488 ret = hdmi_phy_configure(hdmi);
9aaf880e
FE		 1489 if (ret)
1490 return ret;
1491 }
1492
9aaf880e
FE		 1493 return 0;
1494}
1495
f1585f6e
LP		 1496static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data)
1497{
1498 dw_hdmi_phy_power_off(hdmi);
1499}
1500
5765916a
JS		 1501enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi,
1502 void *data)
f1585f6e
LP		 1503{
1504 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1505 connector_status_connected : connector_status_disconnected;
1506}
5765916a 1507EXPORT_SYMBOL_GPL(dw_hdmi_phy_read_hpd);
f1585f6e 1508
5765916a
JS		 1509void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data,
1510 bool force, bool disabled, bool rxsense)
386d3299
NA		 1511{
1512 u8 old_mask = hdmi->phy_mask;
1513
1514 if (force || disabled || !rxsense)
1515 hdmi->phy_mask |= HDMI_PHY_RX_SENSE;
1516 else
1517 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE;
1518
1519 if (old_mask != hdmi->phy_mask)
1520 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1521}
5765916a 1522EXPORT_SYMBOL_GPL(dw_hdmi_phy_update_hpd);
386d3299 1523
5765916a 1524void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data)
386d3299
NA		 1525{
1526 /*
1527 * Configure the PHY RX SENSE and HPD interrupts polarities and clear
1528 * any pending interrupt.
1529 */
1530 hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0);
1531 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1532 HDMI_IH_PHY_STAT0);
1533
1534 /* Enable cable hot plug irq. */
1535 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1536
1537 /* Clear and unmute interrupts. */
1538 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1539 HDMI_IH_PHY_STAT0);
1540 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
1541 HDMI_IH_MUTE_PHY_STAT0);
1542}
5765916a 1543EXPORT_SYMBOL_GPL(dw_hdmi_phy_setup_hpd);
386d3299 1544
f1585f6e
LP		 1545static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = {
1546 .init = dw_hdmi_phy_init,
1547 .disable = dw_hdmi_phy_disable,
1548 .read_hpd = dw_hdmi_phy_read_hpd,
386d3299
NA		 1549 .update_hpd = dw_hdmi_phy_update_hpd,
1550 .setup_hpd = dw_hdmi_phy_setup_hpd,
f1585f6e
LP		 1551};
1552
1553/* -----------------------------------------------------------------------------
1554 * HDMI TX Setup
1555 */
1556
b21f4b65 1557static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
9aaf880e 1558{
812bc615 1559 u8 de;
9aaf880e
FE		 1560
1561 if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
1562 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
1563 else
1564 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
1565
1566 /* disable rx detect */
812bc615
RK		 1567 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
1568 HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
9aaf880e 1569
812bc615 1570 hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
9aaf880e 1571
812bc615
RK		 1572 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
1573 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
9aaf880e
FE		 1574}
1575
d4ac4cb6 1576static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
9aaf880e 1577{
d4ac4cb6
RK		 1578 struct hdmi_avi_infoframe frame;
1579 u8 val;
9aaf880e 1580
d4ac4cb6 1581 /* Initialise info frame from DRM mode */
13d0add3
VS		 1582 drm_hdmi_avi_infoframe_from_display_mode(&frame,
1583 &hdmi->connector, mode);
9aaf880e 1584
def23aa7 1585 if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
d4ac4cb6 1586 frame.colorspace = HDMI_COLORSPACE_YUV444;
def23aa7 1587 else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
d4ac4cb6 1588 frame.colorspace = HDMI_COLORSPACE_YUV422;
ba9877e2
NA		 1589 else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
1590 frame.colorspace = HDMI_COLORSPACE_YUV420;
9aaf880e 1591 else
d4ac4cb6 1592 frame.colorspace = HDMI_COLORSPACE_RGB;
9aaf880e
FE		 1593
1594 /* Set up colorimetry */
def23aa7
NA		 1595 switch (hdmi->hdmi_data.enc_out_encoding) {
1596 case V4L2_YCBCR_ENC_601:
1597 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601)
1598 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1599 else
1600 frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
1601 frame.extended_colorimetry =
d4ac4cb6 1602 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
f40d6560 1603 break;
def23aa7
NA		 1604 case V4L2_YCBCR_ENC_709:
1605 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709)
1606 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1607 else
1608 frame.colorimetry = HDMI_COLORIMETRY_ITU_709;
1609 frame.extended_colorimetry =
d4ac4cb6 1610 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
def23aa7
NA		 1611 break;
1612 default: /* Carries no data */
1613 frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
1614 frame.extended_colorimetry =
1615 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1616 break;
9aaf880e
FE		 1617 }
1618
d4ac4cb6
RK		 1619 frame.scan_mode = HDMI_SCAN_MODE_NONE;
1620
1621 /*
1622 * The Designware IP uses a different byte format from standard
1623 * AVI info frames, though generally the bits are in the correct
1624 * bytes.
1625 */
1626
1627 /*
b0118e7d
JA		 1628 * AVI data byte 1 differences: Colorspace in bits 0,1 rather than 5,6,
1629 * scan info in bits 4,5 rather than 0,1 and active aspect present in
1630 * bit 6 rather than 4.
d4ac4cb6 1631 */
b0118e7d 1632 val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 3);
d4ac4cb6
RK		 1633 if (frame.active_aspect & 15)
1634 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT;
1635 if (frame.top_bar || frame.bottom_bar)
1636 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR;
1637 if (frame.left_bar || frame.right_bar)
1638 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR;
1639 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
1640
1641 /* AVI data byte 2 differences: none */
1642 val = ((frame.colorimetry & 0x3) << 6) |
1643 ((frame.picture_aspect & 0x3) << 4) |
1644 (frame.active_aspect & 0xf);
9aaf880e
FE		 1645 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
1646
d4ac4cb6
RK		 1647 /* AVI data byte 3 differences: none */
1648 val = ((frame.extended_colorimetry & 0x7) << 4) |
1649 ((frame.quantization_range & 0x3) << 2) |
1650 (frame.nups & 0x3);
1651 if (frame.itc)
1652 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID;
9aaf880e
FE		 1653 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
1654
d4ac4cb6
RK		 1655 /* AVI data byte 4 differences: none */
1656 val = frame.video_code & 0x7f;
1657 hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
9aaf880e
FE		 1658
1659 /* AVI Data Byte 5- set up input and output pixel repetition */
1660 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
1661 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
1662 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
1663 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
1664 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
1665 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
1666 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
1667
d4ac4cb6
RK		 1668 /*
1669 * AVI data byte 5 differences: content type in 0,1 rather than 4,5,
1670 * ycc range in bits 2,3 rather than 6,7
1671 */
1672 val = ((frame.ycc_quantization_range & 0x3) << 2) |
1673 (frame.content_type & 0x3);
9aaf880e
FE		 1674 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1675
1676 /* AVI Data Bytes 6-13 */
d4ac4cb6
RK		 1677 hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);
1678 hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1);
1679 hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);
1680 hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1);
1681 hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);
1682 hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1);
1683 hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);
1684 hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
9aaf880e
FE		 1685}
1686
9aa1eca0
NY		 1687static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi,
1688 struct drm_display_mode *mode)
1689{
1690 struct hdmi_vendor_infoframe frame;
1691 u8 buffer[10];
1692 ssize_t err;
1693
f1781e9b
VS		 1694 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame,
1695 &hdmi->connector,
1696 mode);
9aa1eca0
NY		 1697 if (err < 0)
1698 /*
1699 * Going into that statement does not means vendor infoframe
1700 * fails. It just informed us that vendor infoframe is not
1701 * needed for the selected mode. Only 4k or stereoscopic 3D
1702 * mode requires vendor infoframe. So just simply return.
1703 */
1704 return;
1705
1706 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
1707 if (err < 0) {
1708 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n",
1709 err);
1710 return;
1711 }
1712 hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
1713 HDMI_FC_DATAUTO0_VSD_MASK);
1714
1715 /* Set the length of HDMI vendor specific InfoFrame payload */
1716 hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE);
1717
1718 /* Set 24bit IEEE Registration Identifier */
1719 hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0);
1720 hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1);
1721 hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2);
1722
1723 /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */
1724 hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0);
1725 hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1);
1726
1727 if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF)
1728 hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2);
1729
1730 /* Packet frame interpolation */
1731 hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1);
1732
1733 /* Auto packets per frame and line spacing */
1734 hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2);
1735
1736 /* Configures the Frame Composer On RDRB mode */
1737 hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
1738 HDMI_FC_DATAUTO0_VSD_MASK);
1739}
1740
b21f4b65 1741static void hdmi_av_composer(struct dw_hdmi *hdmi,
9aaf880e
FE		 1742 const struct drm_display_mode *mode)
1743{
264fce6c
NA		 1744 u8 inv_val, bytes;
1745 struct drm_hdmi_info *hdmi_info = &hdmi->connector.display_info.hdmi;
9aaf880e
FE		 1746 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1747 int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
ba9877e2 1748 unsigned int vdisplay, hdisplay;
9aaf880e 1749
ba9877e2 1750 vmode->mtmdsclock = vmode->mpixelclock = mode->clock * 1000;
9aaf880e
FE		 1751
1752 dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1753
ba9877e2
NA		 1754 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
1755 vmode->mtmdsclock /= 2;
1756
9aaf880e 1757 /* Set up HDMI_FC_INVIDCONF */
264fce6c 1758 inv_val = (hdmi->hdmi_data.hdcp_enable ||
836f90f9
NA		 1759 (dw_hdmi_support_scdc(hdmi) &&
1760 (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK ||
1761 hdmi_info->scdc.scrambling.low_rates)) ?
9aaf880e
FE		 1762 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1763 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1764
b91eee8c 1765 inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
9aaf880e 1766 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
b91eee8c 1767 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW;
9aaf880e 1768
b91eee8c 1769 inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
9aaf880e 1770 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
b91eee8c 1771 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW;
9aaf880e
FE		 1772
1773 inv_val |= (vmode->mdataenablepolarity ?
1774 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1775 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1776
1777 if (hdmi->vic == 39)
1778 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1779 else
b91eee8c 1780 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
9aaf880e 1781 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
b91eee8c 1782 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
9aaf880e 1783
b91eee8c 1784 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
9aaf880e 1785 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
b91eee8c 1786 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
9aaf880e 1787
05b1342f
RK		 1788 inv_val |= hdmi->sink_is_hdmi ?
1789 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
1790 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE;
9aaf880e
FE		 1791
1792 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1793
ba9877e2
NA		 1794 hdisplay = mode->hdisplay;
1795 hblank = mode->htotal - mode->hdisplay;
1796 h_de_hs = mode->hsync_start - mode->hdisplay;
1797 hsync_len = mode->hsync_end - mode->hsync_start;
1798
1799 /*
1800 * When we're setting a YCbCr420 mode, we need
1801 * to adjust the horizontal timing to suit.
1802 */
1803 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) {
1804 hdisplay /= 2;
1805 hblank /= 2;
1806 h_de_hs /= 2;
1807 hsync_len /= 2;
1808 }
1809
e80b9f4e
RK		 1810 vdisplay = mode->vdisplay;
1811 vblank = mode->vtotal - mode->vdisplay;
1812 v_de_vs = mode->vsync_start - mode->vdisplay;
1813 vsync_len = mode->vsync_end - mode->vsync_start;
1814
1815 /*
1816 * When we're setting an interlaced mode, we need
1817 * to adjust the vertical timing to suit.
1818 */
1819 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1820 vdisplay /= 2;
1821 vblank /= 2;
1822 v_de_vs /= 2;
1823 vsync_len /= 2;
1824 }
1825
264fce6c 1826 /* Scrambling Control */
836f90f9 1827 if (dw_hdmi_support_scdc(hdmi)) {
ba9877e2 1828 if (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK ||
264fce6c
NA		 1829 hdmi_info->scdc.scrambling.low_rates) {
1830 /*
1831 * HDMI2.0 Specifies the following procedure:
1832 * After the Source Device has determined that
1833 * SCDC_Present is set (=1), the Source Device should
1834 * write the accurate Version of the Source Device
1835 * to the Source Version field in the SCDCS.
1836 * Source Devices compliant shall set the
1837 * Source Version = 1.
1838 */
c4cba44e 1839 drm_scdc_readb(hdmi->ddc, SCDC_SINK_VERSION,
264fce6c 1840 &bytes);
c4cba44e 1841 drm_scdc_writeb(hdmi->ddc, SCDC_SOURCE_VERSION,
264fce6c
NA		 1842 min_t(u8, bytes, SCDC_MIN_SOURCE_VERSION));
1843
1844 /* Enabled Scrambling in the Sink */
c4cba44e 1845 drm_scdc_set_scrambling(hdmi->ddc, 1);
264fce6c
NA		 1846
1847 /*
1848 * To activate the scrambler feature, you must ensure
1849 * that the quasi-static configuration bit
1850 * fc_invidconf.HDCP_keepout is set at configuration
1851 * time, before the required mc_swrstzreq.tmdsswrst_req
1852 * reset request is issued.
1853 */
1854 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
1855 HDMI_MC_SWRSTZ);
1856 hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL);
1857 } else {
1858 hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL);
1859 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
1860 HDMI_MC_SWRSTZ);
c4cba44e 1861 drm_scdc_set_scrambling(hdmi->ddc, 0);
264fce6c
NA		 1862 }
1863 }
1864
9aaf880e 1865 /* Set up horizontal active pixel width */
ba9877e2
NA		 1866 hdmi_writeb(hdmi, hdisplay >> 8, HDMI_FC_INHACTV1);
1867 hdmi_writeb(hdmi, hdisplay, HDMI_FC_INHACTV0);
9aaf880e
FE		 1868
1869 /* Set up vertical active lines */
e80b9f4e
RK		 1870 hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1);
1871 hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0);
9aaf880e
FE		 1872
1873 /* Set up horizontal blanking pixel region width */
9aaf880e
FE		 1874 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1875 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1876
1877 /* Set up vertical blanking pixel region width */
9aaf880e
FE		 1878 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1879
1880 /* Set up HSYNC active edge delay width (in pixel clks) */
9aaf880e
FE		 1881 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1882 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1883
1884 /* Set up VSYNC active edge delay (in lines) */
9aaf880e
FE		 1885 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1886
1887 /* Set up HSYNC active pulse width (in pixel clks) */
9aaf880e
FE		 1888 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1889 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1890
1891 /* Set up VSYNC active edge delay (in lines) */
9aaf880e
FE		 1892 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1893}
1894
9aaf880e 1895/* HDMI Initialization Step B.4 */
b21f4b65 1896static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
9aaf880e 1897{
9aaf880e
FE		 1898 /* control period minimum duration */
1899 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1900 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1901 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1902
1903 /* Set to fill TMDS data channels */
1904 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1905 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1906 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1907
1908 /* Enable pixel clock and tmds data path */
7cc4ab22
RK		 1909 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_HDCPCLK_DISABLE |
1910 HDMI_MC_CLKDIS_CSCCLK_DISABLE |
1911 HDMI_MC_CLKDIS_AUDCLK_DISABLE |
1912 HDMI_MC_CLKDIS_PREPCLK_DISABLE |
1913 HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1914 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1915 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
9aaf880e 1916
7cc4ab22
RK		 1917 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1918 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
9aaf880e
FE		 1919
1920 /* Enable csc path */
1921 if (is_color_space_conversion(hdmi)) {
7cc4ab22
RK		 1922 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1923 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
9aaf880e 1924 }
8b9e1c0d 1925
14247d7c
NA		 1926 /* Enable color space conversion if needed */
1927 if (is_color_space_conversion(hdmi))
8b9e1c0d
LP		 1928 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH,
1929 HDMI_MC_FLOWCTRL);
1930 else
1931 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS,
1932 HDMI_MC_FLOWCTRL);
9aaf880e
FE		 1933}
1934
9aaf880e 1935/* Workaround to clear the overflow condition */
b21f4b65 1936static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
9aaf880e 1937{
be41fc55
LP		 1938 unsigned int count;
1939 unsigned int i;
9aaf880e
FE		 1940 u8 val;
1941
be41fc55
LP		 1942 /*
1943 * Under some circumstances the Frame Composer arithmetic unit can miss
1944 * an FC register write due to being busy processing the previous one.
1945 * The issue can be worked around by issuing a TMDS software reset and
1946 * then write one of the FC registers several times.
1947 *
1948 * The number of iterations matters and depends on the HDMI TX revision
46d1b42b
JS		 1949 * (and possibly on the platform). So far i.MX6Q (v1.30a), i.MX6DL
1950 * (v1.31a) and multiple Allwinner SoCs (v1.32a) have been identified
1951 * as needing the workaround, with 4 iterations for v1.30a and 1
1952 * iteration for others.
9c305eb4
NA		 1953 * The Amlogic Meson GX SoCs (v2.01a) have been identified as needing
1954 * the workaround with a single iteration.
d15d9fd0
JK		 1955 * The Rockchip RK3288 SoC (v2.00a) and RK3328/RK3399 SoCs (v2.11a) have
1956 * been identified as needing the workaround with a single iteration.
be41fc55 1957 */
9aaf880e 1958
be41fc55
LP		 1959 switch (hdmi->version) {
1960 case 0x130a:
1961 count = 4;
1962 break;
1963 case 0x131a:
46d1b42b 1964 case 0x132a:
d15d9fd0 1965 case 0x200a:
9c305eb4 1966 case 0x201a:
d15d9fd0 1967 case 0x211a:
c8c78ac2 1968 case 0x212a:
be41fc55
LP		 1969 count = 1;
1970 break;
1971 default:
9aaf880e
FE		 1972 return;
1973 }
1974
be41fc55
LP		 1975 /* TMDS software reset */
1976 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1977
1978 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
1979 for (i = 0; i < count; i++)
9aaf880e
FE		 1980 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1981}
1982
b21f4b65 1983static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
9aaf880e
FE		 1984{
1985 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1986 HDMI_IH_MUTE_FC_STAT2);
1987}
1988
b21f4b65 1989static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
9aaf880e
FE		 1990{
1991 int ret;
1992
1993 hdmi_disable_overflow_interrupts(hdmi);
1994
1995 hdmi->vic = drm_match_cea_mode(mode);
1996
1997 if (!hdmi->vic) {
1998 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
9aaf880e
FE		 1999 } else {
2000 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
9aaf880e
FE		 2001 }
2002
2003 if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
b5878339
AY		 2004 (hdmi->vic == 21) || (hdmi->vic == 22) ||
2005 (hdmi->vic == 2) || (hdmi->vic == 3) ||
2006 (hdmi->vic == 17) || (hdmi->vic == 18))
def23aa7 2007 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601;
9aaf880e 2008 else
def23aa7 2009 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709;
9aaf880e 2010
d10ca826 2011 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
9aaf880e
FE		 2012 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
2013
def23aa7 2014 /* TOFIX: Get input format from plat data or fallback to RGB888 */
e20c29aa 2015 if (hdmi->plat_data->input_bus_format)
def23aa7
NA		 2016 hdmi->hdmi_data.enc_in_bus_format =
2017 hdmi->plat_data->input_bus_format;
2018 else
2019 hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
2020
2021 /* TOFIX: Get input encoding from plat data or fallback to none */
e20c29aa 2022 if (hdmi->plat_data->input_bus_encoding)
def23aa7
NA		 2023 hdmi->hdmi_data.enc_in_encoding =
2024 hdmi->plat_data->input_bus_encoding;
2025 else
2026 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT;
9aaf880e 2027
def23aa7
NA		 2028 /* TOFIX: Default to RGB888 output format */
2029 hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
9aaf880e 2030
9aaf880e
FE		 2031 hdmi->hdmi_data.pix_repet_factor = 0;
2032 hdmi->hdmi_data.hdcp_enable = 0;
2033 hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
2034
2035 /* HDMI Initialization Step B.1 */
2036 hdmi_av_composer(hdmi, mode);
2037
2038 /* HDMI Initializateion Step B.2 */
f1585f6e 2039 ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data, &hdmi->previous_mode);
9aaf880e
FE		 2040 if (ret)
2041 return ret;
f1585f6e 2042 hdmi->phy.enabled = true;
9aaf880e
FE		 2043
2044 /* HDMI Initialization Step B.3 */
b21f4b65 2045 dw_hdmi_enable_video_path(hdmi);
9aaf880e 2046
f709ec07
RK		 2047 if (hdmi->sink_has_audio) {
2048 dev_dbg(hdmi->dev, "sink has audio support\n");
9aaf880e
FE		 2049
2050 /* HDMI Initialization Step E - Configure audio */
2051 hdmi_clk_regenerator_update_pixel_clock(hdmi);
57fbc055 2052 hdmi_enable_audio_clk(hdmi, true);
f709ec07
RK		 2053 }
2054
2055 /* not for DVI mode */
2056 if (hdmi->sink_is_hdmi) {
2057 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
9aaf880e
FE		 2058
2059 /* HDMI Initialization Step F - Configure AVI InfoFrame */
d4ac4cb6 2060 hdmi_config_AVI(hdmi, mode);
9aa1eca0 2061 hdmi_config_vendor_specific_infoframe(hdmi, mode);
05b1342f
RK		 2062 } else {
2063 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
9aaf880e
FE		 2064 }
2065
2066 hdmi_video_packetize(hdmi);
2067 hdmi_video_csc(hdmi);
2068 hdmi_video_sample(hdmi);
2069 hdmi_tx_hdcp_config(hdmi);
2070
b21f4b65 2071 dw_hdmi_clear_overflow(hdmi);
9aaf880e
FE		 2072
2073 return 0;
2074}
2075
b21f4b65 2076static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
9aaf880e
FE		 2077{
2078 u8 ih_mute;
2079
2080 /*
2081 * Boot up defaults are:
2082 * HDMI_IH_MUTE = 0x03 (disabled)
2083 * HDMI_IH_MUTE_* = 0x00 (enabled)
2084 *
2085 * Disable top level interrupt bits in HDMI block
2086 */
2087 ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
2088 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
2089 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
2090
2091 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
2092
2093 /* by default mask all interrupts */
2094 hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
2095 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
2096 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
2097 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
2098 hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
2099 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
2100 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
2101 hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
2102 hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
2103 hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
2104 hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
2105 hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
9aaf880e
FE		 2106 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
2107 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
2108
2109 /* Disable interrupts in the IH_MUTE_* registers */
2110 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
2111 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
2112 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
2113 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
2114 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
2115 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
2116 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
2117 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
2118 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
2119 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
2120
2121 /* Enable top level interrupt bits in HDMI block */
2122 ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
2123 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
2124 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
2125}
2126
b21f4b65 2127static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
9aaf880e 2128{
381f05a7 2129 hdmi->bridge_is_on = true;
b21f4b65 2130 dw_hdmi_setup(hdmi, &hdmi->previous_mode);
9aaf880e
FE		 2131}
2132
b21f4b65 2133static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
9aaf880e 2134{
f1585f6e
LP		 2135 if (hdmi->phy.enabled) {
2136 hdmi->phy.ops->disable(hdmi, hdmi->phy.data);
2137 hdmi->phy.enabled = false;
2138 }
2139
381f05a7
RK		 2140 hdmi->bridge_is_on = false;
2141}
2142
2143static void dw_hdmi_update_power(struct dw_hdmi *hdmi)
2144{
2145 int force = hdmi->force;
2146
2147 if (hdmi->disabled) {
2148 force = DRM_FORCE_OFF;
2149 } else if (force == DRM_FORCE_UNSPECIFIED) {
aeac23bd 2150 if (hdmi->rxsense)
381f05a7
RK		 2151 force = DRM_FORCE_ON;
2152 else
2153 force = DRM_FORCE_OFF;
2154 }
2155
2156 if (force == DRM_FORCE_OFF) {
2157 if (hdmi->bridge_is_on)
2158 dw_hdmi_poweroff(hdmi);
2159 } else {
2160 if (!hdmi->bridge_is_on)
2161 dw_hdmi_poweron(hdmi);
2162 }
9aaf880e
FE		 2163}
2164
aeac23bd
RK		 2165/*
2166 * Adjust the detection of RXSENSE according to whether we have a forced
2167 * connection mode enabled, or whether we have been disabled. There is
2168 * no point processing RXSENSE interrupts if we have a forced connection
2169 * state, or DRM has us disabled.
2170 *
2171 * We also disable rxsense interrupts when we think we're disconnected
2172 * to avoid floating TDMS signals giving false rxsense interrupts.
2173 *
2174 * Note: we still need to listen for HPD interrupts even when DRM has us
2175 * disabled so that we can detect a connect event.
2176 */
2177static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi)
2178{
386d3299
NA		 2179 if (hdmi->phy.ops->update_hpd)
2180 hdmi->phy.ops->update_hpd(hdmi, hdmi->phy.data,
2181 hdmi->force, hdmi->disabled,
2182 hdmi->rxsense);
a23d6265
LP		 2183}
2184
b21f4b65
AY		 2185static enum drm_connector_status
2186dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
9aaf880e 2187{
b21f4b65 2188 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
d94905e0 2189 connector);
a9c82d63 2190 enum drm_connector_status result;
98dbeada 2191
381f05a7
RK		 2192 mutex_lock(&hdmi->mutex);
2193 hdmi->force = DRM_FORCE_UNSPECIFIED;
2194 dw_hdmi_update_power(hdmi);
aeac23bd 2195 dw_hdmi_update_phy_mask(hdmi);
381f05a7
RK		 2196 mutex_unlock(&hdmi->mutex);
2197
a9c82d63
CYC		 2198 result = hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data);
2199
2200 mutex_lock(&hdmi->mutex);
2201 if (result != hdmi->last_connector_result) {
2202 dev_dbg(hdmi->dev, "read_hpd result: %d", result);
2203 handle_plugged_change(hdmi,
2204 result == connector_status_connected);
2205 hdmi->last_connector_result = result;
2206 }
2207 mutex_unlock(&hdmi->mutex);
2208
2209 return result;
9aaf880e
FE		 2210}
2211
b21f4b65 2212static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
9aaf880e 2213{
b21f4b65 2214 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
9aaf880e
FE		 2215 connector);
2216 struct edid *edid;
6c7e66e6 2217 int ret = 0;
9aaf880e
FE		 2218
2219 if (!hdmi->ddc)
2220 return 0;
2221
2222 edid = drm_get_edid(connector, hdmi->ddc);
2223 if (edid) {
2224 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
2225 edid->width_cm, edid->height_cm);
2226
05b1342f 2227 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
f709ec07 2228 hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
c555f023 2229 drm_connector_update_edid_property(connector, edid);
e84b8d75 2230 cec_notifier_set_phys_addr_from_edid(hdmi->cec_notifier, edid);
9aaf880e
FE		 2231 ret = drm_add_edid_modes(connector, edid);
2232 kfree(edid);
2233 } else {
2234 dev_dbg(hdmi->dev, "failed to get edid\n");
2235 }
2236
6c7e66e6 2237 return ret;
9aaf880e
FE		 2238}
2239
381f05a7
RK		 2240static void dw_hdmi_connector_force(struct drm_connector *connector)
2241{
2242 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2243 connector);
2244
2245 mutex_lock(&hdmi->mutex);
2246 hdmi->force = connector->force;
2247 dw_hdmi_update_power(hdmi);
aeac23bd 2248 dw_hdmi_update_phy_mask(hdmi);
381f05a7
RK		 2249 mutex_unlock(&hdmi->mutex);
2250}
2251
dae91e4d 2252static const struct drm_connector_funcs dw_hdmi_connector_funcs = {
2c5b2ccc
MY		 2253 .fill_modes = drm_helper_probe_single_connector_modes,
2254 .detect = dw_hdmi_connector_detect,
fdd8326a 2255 .destroy = drm_connector_cleanup,
2c5b2ccc
MY		 2256 .force = dw_hdmi_connector_force,
2257 .reset = drm_atomic_helper_connector_reset,
2258 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
2259 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2260};
2261
dae91e4d 2262static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
b21f4b65 2263 .get_modes = dw_hdmi_connector_get_modes,
9aaf880e
FE		 2264};
2265
d2ae94ae
LP		 2266static int dw_hdmi_bridge_attach(struct drm_bridge *bridge)
2267{
2268 struct dw_hdmi *hdmi = bridge->driver_private;
2269 struct drm_encoder *encoder = bridge->encoder;
2270 struct drm_connector *connector = &hdmi->connector;
7070fe73
DM		 2271 struct cec_connector_info conn_info;
2272 struct cec_notifier *notifier;
d2ae94ae
LP		 2273
2274 connector->interlace_allowed = 1;
2275 connector->polled = DRM_CONNECTOR_POLL_HPD;
2276
2277 drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs);
2278
9ebc4d21
AP		 2279 drm_connector_init_with_ddc(bridge->dev, connector,
2280 &dw_hdmi_connector_funcs,
2281 DRM_MODE_CONNECTOR_HDMIA,
2282 hdmi->ddc);
d2ae94ae 2283
cde4c44d 2284 drm_connector_attach_encoder(connector, encoder);
d2ae94ae 2285
7070fe73
DM		 2286 cec_fill_conn_info_from_drm(&conn_info, connector);
2287
2288 notifier = cec_notifier_conn_register(hdmi->dev, NULL, &conn_info);
2289 if (!notifier)
2290 return -ENOMEM;
2291
2292 mutex_lock(&hdmi->cec_notifier_mutex);
2293 hdmi->cec_notifier = notifier;
2294 mutex_unlock(&hdmi->cec_notifier_mutex);
2295
d2ae94ae
LP		 2296 return 0;
2297}
2298
7070fe73
DM		 2299static void dw_hdmi_bridge_detach(struct drm_bridge *bridge)
2300{
2301 struct dw_hdmi *hdmi = bridge->driver_private;
2302
2303 mutex_lock(&hdmi->cec_notifier_mutex);
2304 cec_notifier_conn_unregister(hdmi->cec_notifier);
2305 hdmi->cec_notifier = NULL;
2306 mutex_unlock(&hdmi->cec_notifier_mutex);
2307}
2308
b0febde7
JA		 2309static enum drm_mode_status
2310dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge,
2311 const struct drm_display_mode *mode)
6ce2ca58
RP		 2312{
2313 struct dw_hdmi *hdmi = bridge->driver_private;
2314 struct drm_connector *connector = &hdmi->connector;
b0febde7 2315 enum drm_mode_status mode_status = MODE_OK;
6ce2ca58 2316
b0febde7
JA		 2317 /* We don't support double-clocked modes */
2318 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
2319 return MODE_BAD;
2320
2321 if (hdmi->plat_data->mode_valid)
2322 mode_status = hdmi->plat_data->mode_valid(connector, mode);
2323
2324 return mode_status;
6ce2ca58
RP		 2325}
2326
fd30b38c 2327static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
63f8f3ba
LP		 2328 const struct drm_display_mode *orig_mode,
2329 const struct drm_display_mode *mode)
fd30b38c
LP		 2330{
2331 struct dw_hdmi *hdmi = bridge->driver_private;
2332
2333 mutex_lock(&hdmi->mutex);
2334
2335 /* Store the display mode for plugin/DKMS poweron events */
2336 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
2337
2338 mutex_unlock(&hdmi->mutex);
2339}
2340
2341static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
2342{
2343 struct dw_hdmi *hdmi = bridge->driver_private;
2344
2345 mutex_lock(&hdmi->mutex);
2346 hdmi->disabled = true;
2347 dw_hdmi_update_power(hdmi);
2348 dw_hdmi_update_phy_mask(hdmi);
2349 mutex_unlock(&hdmi->mutex);
2350}
2351
2352static void dw_hdmi_bridge_enable(struct drm_bridge *bridge)
2353{
2354 struct dw_hdmi *hdmi = bridge->driver_private;
2355
2356 mutex_lock(&hdmi->mutex);
2357 hdmi->disabled = false;
2358 dw_hdmi_update_power(hdmi);
2359 dw_hdmi_update_phy_mask(hdmi);
2360 mutex_unlock(&hdmi->mutex);
2361}
2362
dae91e4d 2363static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
d2ae94ae 2364 .attach = dw_hdmi_bridge_attach,
7070fe73 2365 .detach = dw_hdmi_bridge_detach,
b21f4b65
AY		 2366 .enable = dw_hdmi_bridge_enable,
2367 .disable = dw_hdmi_bridge_disable,
b21f4b65 2368 .mode_set = dw_hdmi_bridge_mode_set,
b0febde7 2369 .mode_valid = dw_hdmi_bridge_mode_valid,
3d1b35a3
AY		 2370};
2371
3efc2fa3
VZ		 2372static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi)
2373{
2374 struct dw_hdmi_i2c *i2c = hdmi->i2c;
2375 unsigned int stat;
2376
2377 stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0);
2378 if (!stat)
2379 return IRQ_NONE;
2380
2381 hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0);
2382
2383 i2c->stat = stat;
2384
2385 complete(&i2c->cmp);
2386
2387 return IRQ_HANDLED;
2388}
2389
b21f4b65 2390static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
d94905e0 2391{
b21f4b65 2392 struct dw_hdmi *hdmi = dev_id;
d94905e0 2393 u8 intr_stat;
3efc2fa3
VZ		 2394 irqreturn_t ret = IRQ_NONE;
2395
2396 if (hdmi->i2c)
2397 ret = dw_hdmi_i2c_irq(hdmi);
d94905e0
RK		 2398
2399 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
3efc2fa3 2400 if (intr_stat) {
d94905e0 2401 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
3efc2fa3
VZ		 2402 return IRQ_WAKE_THREAD;
2403 }
d94905e0 2404
3efc2fa3 2405 return ret;
d94905e0
RK		 2406}
2407
c32048d9 2408void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense)
386d3299
NA		 2409{
2410 mutex_lock(&hdmi->mutex);
2411
2412 if (!hdmi->force) {
2413 /*
2414 * If the RX sense status indicates we're disconnected,
2415 * clear the software rxsense status.
2416 */
2417 if (!rx_sense)
2418 hdmi->rxsense = false;
2419
2420 /*
2421 * Only set the software rxsense status when both
2422 * rxsense and hpd indicates we're connected.
2423 * This avoids what seems to be bad behaviour in
2424 * at least iMX6S versions of the phy.
2425 */
2426 if (hpd)
2427 hdmi->rxsense = true;
2428
2429 dw_hdmi_update_power(hdmi);
2430 dw_hdmi_update_phy_mask(hdmi);
2431 }
2432 mutex_unlock(&hdmi->mutex);
2433}
386d3299
NA		 2434EXPORT_SYMBOL_GPL(dw_hdmi_setup_rx_sense);
2435
b21f4b65 2436static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
9aaf880e 2437{
b21f4b65 2438 struct dw_hdmi *hdmi = dev_id;
aeac23bd 2439 u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat;
9aaf880e
FE		 2440
2441 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
9aaf880e 2442 phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
aeac23bd
RK		 2443 phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0);
2444
2445 phy_pol_mask = 0;
2446 if (intr_stat & HDMI_IH_PHY_STAT0_HPD)
2447 phy_pol_mask |= HDMI_PHY_HPD;
2448 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0)
2449 phy_pol_mask |= HDMI_PHY_RX_SENSE0;
2450 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1)
2451 phy_pol_mask |= HDMI_PHY_RX_SENSE1;
2452 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2)
2453 phy_pol_mask |= HDMI_PHY_RX_SENSE2;
2454 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3)
2455 phy_pol_mask |= HDMI_PHY_RX_SENSE3;
2456
2457 if (phy_pol_mask)
2458 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0);
9aaf880e 2459
aeac23bd
RK		 2460 /*
2461 * RX sense tells us whether the TDMS transmitters are detecting
2462 * load - in other words, there's something listening on the
2463 * other end of the link. Use this to decide whether we should
2464 * power on the phy as HPD may be toggled by the sink to merely
2465 * ask the source to re-read the EDID.
2466 */
2467 if (intr_stat &
e84b8d75 2468 (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) {
c32048d9
NA		 2469 dw_hdmi_setup_rx_sense(hdmi,
2470 phy_stat & HDMI_PHY_HPD,
2471 phy_stat & HDMI_PHY_RX_SENSE);
aeac23bd 2472
7070fe73
DM		 2473 if ((phy_stat & (HDMI_PHY_RX_SENSE | HDMI_PHY_HPD)) == 0) {
2474 mutex_lock(&hdmi->cec_notifier_mutex);
2475 cec_notifier_phys_addr_invalidate(hdmi->cec_notifier);
2476 mutex_unlock(&hdmi->cec_notifier_mutex);
2477 }
e84b8d75
RK		 2478 }
2479
aeac23bd
RK		 2480 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
2481 dev_dbg(hdmi->dev, "EVENT=%s\n",
2482 phy_int_pol & HDMI_PHY_HPD ? "plugin" : "plugout");
ba5d7e61
LP		 2483 if (hdmi->bridge.dev)
2484 drm_helper_hpd_irq_event(hdmi->bridge.dev);
9aaf880e
FE		 2485 }
2486
2487 hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
aeac23bd
RK		 2488 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
2489 HDMI_IH_MUTE_PHY_STAT0);
9aaf880e
FE		 2490
2491 return IRQ_HANDLED;
2492}
2493
faba6c3c
LP		 2494static const struct dw_hdmi_phy_data dw_hdmi_phys[] = {
2495 {
2496 .type = DW_HDMI_PHY_DWC_HDMI_TX_PHY,
2497 .name = "DWC HDMI TX PHY",
b0e583e5 2498 .gen = 1,
faba6c3c
LP		 2499 }, {
2500 .type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC,
2501 .name = "DWC MHL PHY + HEAC PHY",
b0e583e5 2502 .gen = 2,
faba6c3c 2503 .has_svsret = true,
2ef9dfed 2504 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
faba6c3c
LP		 2505 }, {
2506 .type = DW_HDMI_PHY_DWC_MHL_PHY,
2507 .name = "DWC MHL PHY",
b0e583e5 2508 .gen = 2,
faba6c3c 2509 .has_svsret = true,
2ef9dfed 2510 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
faba6c3c
LP		 2511 }, {
2512 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC,
2513 .name = "DWC HDMI 3D TX PHY + HEAC PHY",
b0e583e5 2514 .gen = 2,
2ef9dfed 2515 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
faba6c3c
LP		 2516 }, {
2517 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY,
2518 .name = "DWC HDMI 3D TX PHY",
b0e583e5 2519 .gen = 2,
2ef9dfed 2520 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
faba6c3c
LP		 2521 }, {
2522 .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY,
2523 .name = "DWC HDMI 2.0 TX PHY",
b0e583e5 2524 .gen = 2,
faba6c3c 2525 .has_svsret = true,
c93f6092 2526 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2ef9dfed
KB		 2527 }, {
2528 .type = DW_HDMI_PHY_VENDOR_PHY,
2529 .name = "Vendor PHY",
faba6c3c
LP		 2530 }
2531};
2532
2533static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi)
2534{
2535 unsigned int i;
2536 u8 phy_type;
2537
8faff374
HS		 2538 phy_type = hdmi->plat_data->phy_force_vendor ?
2539 DW_HDMI_PHY_VENDOR_PHY :
2540 hdmi_readb(hdmi, HDMI_CONFIG2_ID);
faba6c3c 2541
f1585f6e
LP		 2542 if (phy_type == DW_HDMI_PHY_VENDOR_PHY) {
2543 /* Vendor PHYs require support from the glue layer. */
2544 if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) {
2545 dev_err(hdmi->dev,
2546 "Vendor HDMI PHY not supported by glue layer\n");
2547 return -ENODEV;
2548 }
2549
2550 hdmi->phy.ops = hdmi->plat_data->phy_ops;
2551 hdmi->phy.data = hdmi->plat_data->phy_data;
2552 hdmi->phy.name = hdmi->plat_data->phy_name;
2553 return 0;
2554 }
2555
2556 /* Synopsys PHYs are handled internally. */
faba6c3c
LP		 2557 for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) {
2558 if (dw_hdmi_phys[i].type == phy_type) {
f1585f6e
LP		 2559 hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops;
2560 hdmi->phy.name = dw_hdmi_phys[i].name;
2561 hdmi->phy.data = (void *)&dw_hdmi_phys[i];
2ef9dfed
KB		 2562
2563 if (!dw_hdmi_phys[i].configure &&
2564 !hdmi->plat_data->configure_phy) {
2565 dev_err(hdmi->dev, "%s requires platform support\n",
2566 hdmi->phy.name);
2567 return -ENODEV;
2568 }
2569
faba6c3c
LP		 2570 return 0;
2571 }
2572 }
2573
f1585f6e 2574 dev_err(hdmi->dev, "Unsupported HDMI PHY type (%02x)\n", phy_type);
faba6c3c
LP		 2575 return -ENODEV;
2576}
2577
a616e63c
RK		 2578static void dw_hdmi_cec_enable(struct dw_hdmi *hdmi)
2579{
2580 mutex_lock(&hdmi->mutex);
2581 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CECCLK_DISABLE;
2582 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2583 mutex_unlock(&hdmi->mutex);
2584}
2585
2586static void dw_hdmi_cec_disable(struct dw_hdmi *hdmi)
2587{
2588 mutex_lock(&hdmi->mutex);
2589 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CECCLK_DISABLE;
2590 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2591 mutex_unlock(&hdmi->mutex);
2592}
2593
2594static const struct dw_hdmi_cec_ops dw_hdmi_cec_ops = {
2595 .write = hdmi_writeb,
2596 .read = hdmi_readb,
2597 .enable = dw_hdmi_cec_enable,
2598 .disable = dw_hdmi_cec_disable,
2599};
2600
80e2f979
NA		 2601static const struct regmap_config hdmi_regmap_8bit_config = {
2602 .reg_bits = 32,
2603 .val_bits = 8,
2604 .reg_stride = 1,
2605 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR,
2606};
2607
2608static const struct regmap_config hdmi_regmap_32bit_config = {
2609 .reg_bits = 32,
2610 .val_bits = 32,
2611 .reg_stride = 4,
2612 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR << 2,
2613};
2614
99d02ed5
DA		 2615static void dw_hdmi_init_hw(struct dw_hdmi *hdmi)
2616{
2617 initialize_hdmi_ih_mutes(hdmi);
2618
2619 /*
2620 * Reset HDMI DDC I2C master controller and mute I2CM interrupts.
2621 * Even if we are using a separate i2c adapter doing this doesn't
2622 * hurt.
2623 */
2624 dw_hdmi_i2c_init(hdmi);
2625
2626 if (hdmi->phy.ops->setup_hpd)
2627 hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data);
2628}
2629
69497eb9
LP		 2630static struct dw_hdmi *
2631__dw_hdmi_probe(struct platform_device *pdev,
2632 const struct dw_hdmi_plat_data *plat_data)
9aaf880e 2633{
c608119d 2634 struct device *dev = &pdev->dev;
17b5001b 2635 struct device_node *np = dev->of_node;
7ed6c665 2636 struct platform_device_info pdevinfo;
9aaf880e 2637 struct device_node *ddc_node;
a616e63c 2638 struct dw_hdmi_cec_data cec;
b21f4b65 2639 struct dw_hdmi *hdmi;
80e2f979 2640 struct resource *iores = NULL;
c608119d 2641 int irq;
3d1b35a3 2642 int ret;
0cd9d142 2643 u32 val = 1;
0527e12e
LP		 2644 u8 prod_id0;
2645 u8 prod_id1;
2761ba6c 2646 u8 config0;
0c674948 2647 u8 config3;
9aaf880e 2648
17b5001b 2649 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
9aaf880e 2650 if (!hdmi)
69497eb9 2651 return ERR_PTR(-ENOMEM);
9aaf880e 2652
3d1b35a3 2653 hdmi->plat_data = plat_data;
17b5001b 2654 hdmi->dev = dev;
40678388 2655 hdmi->sample_rate = 48000;
b872a8e1 2656 hdmi->disabled = true;
aeac23bd
RK		 2657 hdmi->rxsense = true;
2658 hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE);
7cc4ab22 2659 hdmi->mc_clkdis = 0x7f;
a9c82d63 2660 hdmi->last_connector_result = connector_status_disconnected;
9aaf880e 2661
b872a8e1 2662 mutex_init(&hdmi->mutex);
6bcf4953 2663 mutex_init(&hdmi->audio_mutex);
7070fe73 2664 mutex_init(&hdmi->cec_notifier_mutex);
b90120a9 2665 spin_lock_init(&hdmi->audio_lock);
6bcf4953 2666
b5d45901 2667 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
9aaf880e 2668 if (ddc_node) {
9f04a1f2 2669 hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node);
c2c38488
AY		 2670 of_node_put(ddc_node);
2671 if (!hdmi->ddc) {
9aaf880e 2672 dev_dbg(hdmi->dev, "failed to read ddc node\n");
69497eb9 2673 return ERR_PTR(-EPROBE_DEFER);
c2c38488 2674 }
9aaf880e 2675
9aaf880e
FE		 2676 } else {
2677 dev_dbg(hdmi->dev, "no ddc property found\n");
2678 }
2679
80e2f979
NA		 2680 if (!plat_data->regm) {
2681 const struct regmap_config *reg_config;
2682
2683 of_property_read_u32(np, "reg-io-width", &val);
2684 switch (val) {
2685 case 4:
2686 reg_config = &hdmi_regmap_32bit_config;
2687 hdmi->reg_shift = 2;
2688 break;
2689 case 1:
2690 reg_config = &hdmi_regmap_8bit_config;
2691 break;
2692 default:
2693 dev_err(dev, "reg-io-width must be 1 or 4\n");
2694 return ERR_PTR(-EINVAL);
2695 }
2696
2697 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2698 hdmi->regs = devm_ioremap_resource(dev, iores);
2699 if (IS_ERR(hdmi->regs)) {
2700 ret = PTR_ERR(hdmi->regs);
2701 goto err_res;
2702 }
2703
2704 hdmi->regm = devm_regmap_init_mmio(dev, hdmi->regs, reg_config);
2705 if (IS_ERR(hdmi->regm)) {
2706 dev_err(dev, "Failed to configure regmap\n");
2707 ret = PTR_ERR(hdmi->regm);
2708 goto err_res;
2709 }
2710 } else {
2711 hdmi->regm = plat_data->regm;
9f04a1f2 2712 }
9aaf880e 2713
9aaf880e
FE		 2714 hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
2715 if (IS_ERR(hdmi->isfr_clk)) {
2716 ret = PTR_ERR(hdmi->isfr_clk);
b5878339 2717 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
9f04a1f2 2718 goto err_res;
9aaf880e
FE		 2719 }
2720
2721 ret = clk_prepare_enable(hdmi->isfr_clk);
2722 if (ret) {
b5878339 2723 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
9f04a1f2 2724 goto err_res;
9aaf880e
FE		 2725 }
2726
2727 hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
2728 if (IS_ERR(hdmi->iahb_clk)) {
2729 ret = PTR_ERR(hdmi->iahb_clk);
b5878339 2730 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
9aaf880e
FE		 2731 goto err_isfr;
2732 }
2733
2734 ret = clk_prepare_enable(hdmi->iahb_clk);
2735 if (ret) {
b5878339 2736 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
9aaf880e
FE		 2737 goto err_isfr;
2738 }
2739
ebe32c3e
PHH		 2740 hdmi->cec_clk = devm_clk_get(hdmi->dev, "cec");
2741 if (PTR_ERR(hdmi->cec_clk) == -ENOENT) {
2742 hdmi->cec_clk = NULL;
2743 } else if (IS_ERR(hdmi->cec_clk)) {
2744 ret = PTR_ERR(hdmi->cec_clk);
2745 if (ret != -EPROBE_DEFER)
2746 dev_err(hdmi->dev, "Cannot get HDMI cec clock: %d\n",
2747 ret);
2748
2749 hdmi->cec_clk = NULL;
2750 goto err_iahb;
2751 } else {
2752 ret = clk_prepare_enable(hdmi->cec_clk);
2753 if (ret) {
2754 dev_err(hdmi->dev, "Cannot enable HDMI cec clock: %d\n",
2755 ret);
2756 goto err_iahb;
2757 }
2758 }
2759
9aaf880e 2760 /* Product and revision IDs */
be41fc55
LP		 2761 hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8)
2762 | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0);
0527e12e
LP		 2763 prod_id0 = hdmi_readb(hdmi, HDMI_PRODUCT_ID0);
2764 prod_id1 = hdmi_readb(hdmi, HDMI_PRODUCT_ID1);
2765
2766 if (prod_id0 != HDMI_PRODUCT_ID0_HDMI_TX ||
2767 (prod_id1 & ~HDMI_PRODUCT_ID1_HDCP) != HDMI_PRODUCT_ID1_HDMI_TX) {
2768 dev_err(dev, "Unsupported HDMI controller (%04x:%02x:%02x)\n",
be41fc55 2769 hdmi->version, prod_id0, prod_id1);
0527e12e
LP		 2770 ret = -ENODEV;
2771 goto err_iahb;
2772 }
2773
faba6c3c
LP		 2774 ret = dw_hdmi_detect_phy(hdmi);
2775 if (ret < 0)
2776 goto err_iahb;
2777
2778 dev_info(dev, "Detected HDMI TX controller v%x.%03x %s HDCP (%s)\n",
be41fc55 2779 hdmi->version >> 12, hdmi->version & 0xfff,
faba6c3c 2780 prod_id1 & HDMI_PRODUCT_ID1_HDCP ? "with" : "without",
f1585f6e 2781 hdmi->phy.name);
9aaf880e 2782
99d02ed5 2783 dw_hdmi_init_hw(hdmi);
9aaf880e 2784
c608119d 2785 irq = platform_get_irq(pdev, 0);
69497eb9
LP		 2786 if (irq < 0) {
2787 ret = irq;
c608119d 2788 goto err_iahb;
69497eb9 2789 }
c608119d 2790
639a202c
PZ		 2791 ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
2792 dw_hdmi_irq, IRQF_SHARED,
2793 dev_name(dev), hdmi);
2794 if (ret)
b33ef619 2795 goto err_iahb;
639a202c 2796
9aaf880e
FE		 2797 /*
2798 * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
2799 * N and cts values before enabling phy
2800 */
2801 hdmi_init_clk_regenerator(hdmi);
2802
3efc2fa3
VZ		 2803 /* If DDC bus is not specified, try to register HDMI I2C bus */
2804 if (!hdmi->ddc) {
50f9495e
DA		 2805 /* Look for (optional) stuff related to unwedging */
2806 hdmi->pinctrl = devm_pinctrl_get(dev);
2807 if (!IS_ERR(hdmi->pinctrl)) {
2808 hdmi->unwedge_state =
2809 pinctrl_lookup_state(hdmi->pinctrl, "unwedge");
2810 hdmi->default_state =
2811 pinctrl_lookup_state(hdmi->pinctrl, "default");
2812
0bd79f91
DA		 2813 if (IS_ERR(hdmi->default_state) ||
2814 IS_ERR(hdmi->unwedge_state)) {
2815 if (!IS_ERR(hdmi->unwedge_state))
2816 dev_warn(dev,
2817 "Unwedge requires default pinctrl\n");
2818 hdmi->default_state = NULL;
2819 hdmi->unwedge_state = NULL;
50f9495e
DA		 2820 }
2821 }
2822
3efc2fa3
VZ		 2823 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi);
2824 if (IS_ERR(hdmi->ddc))
2825 hdmi->ddc = NULL;
2826 }
2827
69497eb9
LP		 2828 hdmi->bridge.driver_private = hdmi;
2829 hdmi->bridge.funcs = &dw_hdmi_bridge_funcs;
d5ad7843 2830#ifdef CONFIG_OF
69497eb9 2831 hdmi->bridge.of_node = pdev->dev.of_node;
d5ad7843 2832#endif
9aaf880e 2833
7ed6c665
RK		 2834 memset(&pdevinfo, 0, sizeof(pdevinfo));
2835 pdevinfo.parent = dev;
2836 pdevinfo.id = PLATFORM_DEVID_AUTO;
2837
2761ba6c 2838 config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID);
0c674948 2839 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID);
2761ba6c 2840
80e2f979 2841 if (iores && config3 & HDMI_CONFIG3_AHBAUDDMA) {
2761ba6c
KM		 2842 struct dw_hdmi_audio_data audio;
2843
7ed6c665
RK		 2844 audio.phys = iores->start;
2845 audio.base = hdmi->regs;
2846 audio.irq = irq;
2847 audio.hdmi = hdmi;
f5ce4057 2848 audio.eld = hdmi->connector.eld;
a7d555d2
RP		 2849 hdmi->enable_audio = dw_hdmi_ahb_audio_enable;
2850 hdmi->disable_audio = dw_hdmi_ahb_audio_disable;
7ed6c665
RK		 2851
2852 pdevinfo.name = "dw-hdmi-ahb-audio";
2853 pdevinfo.data = &audio;
2854 pdevinfo.size_data = sizeof(audio);
2855 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2856 hdmi->audio = platform_device_register_full(&pdevinfo);
2761ba6c
KM		 2857 } else if (config0 & HDMI_CONFIG0_I2S) {
2858 struct dw_hdmi_i2s_audio_data audio;
2859
2860 audio.hdmi = hdmi;
fc1ca6e0 2861 audio.eld = hdmi->connector.eld;
2761ba6c
KM		 2862 audio.write = hdmi_writeb;
2863 audio.read = hdmi_readb;
a7d555d2 2864 hdmi->enable_audio = dw_hdmi_i2s_audio_enable;
57fbc055 2865 hdmi->disable_audio = dw_hdmi_i2s_audio_disable;
2761ba6c
KM		 2866
2867 pdevinfo.name = "dw-hdmi-i2s-audio";
2868 pdevinfo.data = &audio;
2869 pdevinfo.size_data = sizeof(audio);
2870 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2871 hdmi->audio = platform_device_register_full(&pdevinfo);
7ed6c665
RK		 2872 }
2873
a616e63c
RK		 2874 if (config0 & HDMI_CONFIG0_CEC) {
2875 cec.hdmi = hdmi;
2876 cec.ops = &dw_hdmi_cec_ops;
2877 cec.irq = irq;
2878
2879 pdevinfo.name = "dw-hdmi-cec";
2880 pdevinfo.data = &cec;
2881 pdevinfo.size_data = sizeof(cec);
2882 pdevinfo.dma_mask = 0;
2883
2884 hdmi->cec = platform_device_register_full(&pdevinfo);
2885 }
2886
69497eb9 2887 return hdmi;
9aaf880e
FE		 2888
2889err_iahb:
3efc2fa3
VZ		 2890 if (hdmi->i2c) {
2891 i2c_del_adapter(&hdmi->i2c->adap);
2892 hdmi->ddc = NULL;
2893 }
2894
9aaf880e 2895 clk_disable_unprepare(hdmi->iahb_clk);
ebe32c3e
PHH		 2896 if (hdmi->cec_clk)
2897 clk_disable_unprepare(hdmi->cec_clk);
9aaf880e
FE		 2898err_isfr:
2899 clk_disable_unprepare(hdmi->isfr_clk);
9f04a1f2
VZ		 2900err_res:
2901 i2c_put_adapter(hdmi->ddc);
9aaf880e 2902
69497eb9 2903 return ERR_PTR(ret);
9aaf880e
FE		 2904}
2905
69497eb9 2906static void __dw_hdmi_remove(struct dw_hdmi *hdmi)
9aaf880e 2907{
7ed6c665
RK		 2908 if (hdmi->audio && !IS_ERR(hdmi->audio))
2909 platform_device_unregister(hdmi->audio);
a616e63c
RK		 2910 if (!IS_ERR(hdmi->cec))
2911 platform_device_unregister(hdmi->cec);
7ed6c665 2912
d94905e0
RK		 2913 /* Disable all interrupts */
2914 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
2915
9aaf880e
FE		 2916 clk_disable_unprepare(hdmi->iahb_clk);
2917 clk_disable_unprepare(hdmi->isfr_clk);
ebe32c3e
PHH		 2918 if (hdmi->cec_clk)
2919 clk_disable_unprepare(hdmi->cec_clk);
3efc2fa3
VZ		 2920
2921 if (hdmi->i2c)
2922 i2c_del_adapter(&hdmi->i2c->adap);
2923 else
2924 i2c_put_adapter(hdmi->ddc);
17b5001b 2925}
69497eb9
LP		 2926
2927/* -----------------------------------------------------------------------------
2928 * Probe/remove API, used from platforms based on the DRM bridge API.
2929 */
eea034af
JS		 2930struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
2931 const struct dw_hdmi_plat_data *plat_data)
69497eb9
LP		 2932{
2933 struct dw_hdmi *hdmi;
69497eb9
LP		 2934
2935 hdmi = __dw_hdmi_probe(pdev, plat_data);
2936 if (IS_ERR(hdmi))
eea034af 2937 return hdmi;
69497eb9 2938
b678682e 2939 drm_bridge_add(&hdmi->bridge);
69497eb9 2940
eea034af 2941 return hdmi;
69497eb9
LP		 2942}
2943EXPORT_SYMBOL_GPL(dw_hdmi_probe);
2944
eea034af 2945void dw_hdmi_remove(struct dw_hdmi *hdmi)
69497eb9 2946{
69497eb9
LP		 2947 drm_bridge_remove(&hdmi->bridge);
2948
2949 __dw_hdmi_remove(hdmi);
2950}
2951EXPORT_SYMBOL_GPL(dw_hdmi_remove);
2952
2953/* -----------------------------------------------------------------------------
2954 * Bind/unbind API, used from platforms based on the component framework.
2955 */
eea034af
JS		 2956struct dw_hdmi *dw_hdmi_bind(struct platform_device *pdev,
2957 struct drm_encoder *encoder,
2958 const struct dw_hdmi_plat_data *plat_data)
69497eb9
LP		 2959{
2960 struct dw_hdmi *hdmi;
2961 int ret;
2962
2963 hdmi = __dw_hdmi_probe(pdev, plat_data);
2964 if (IS_ERR(hdmi))
eea034af 2965 return hdmi;
69497eb9
LP		 2966
2967 ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL);
2968 if (ret) {
eea034af 2969 dw_hdmi_remove(hdmi);
69497eb9 2970 DRM_ERROR("Failed to initialize bridge with drm\n");
eea034af 2971 return ERR_PTR(ret);
69497eb9
LP		 2972 }
2973
eea034af 2974 return hdmi;
69497eb9
LP		 2975}
2976EXPORT_SYMBOL_GPL(dw_hdmi_bind);
2977
eea034af 2978void dw_hdmi_unbind(struct dw_hdmi *hdmi)
69497eb9 2979{
69497eb9
LP		 2980 __dw_hdmi_remove(hdmi);
2981}
b21f4b65 2982EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
9aaf880e 2983
99d02ed5
DA		 2984void dw_hdmi_resume(struct dw_hdmi *hdmi)
2985{
2986 dw_hdmi_init_hw(hdmi);
2987}
2988EXPORT_SYMBOL_GPL(dw_hdmi_resume);
2989
9aaf880e 2990MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
3d1b35a3
AY		 2991MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
2992MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
3efc2fa3 2993MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>");
b21f4b65 2994MODULE_DESCRIPTION("DW HDMI transmitter driver");
9aaf880e 2995MODULE_LICENSE("GPL");
b21f4b65 2996MODULE_ALIAS("platform:dw-hdmi");
Linux 6.x block layer and io_uring tree(s)