Commit | Line | Data |
---|---|---|
9aaf880e | 1 | /* |
3efc2fa3 VZ |
2 | * DesignWare High-Definition Multimedia Interface (HDMI) driver |
3 | * | |
4 | * Copyright (C) 2013-2015 Mentor Graphics Inc. | |
9aaf880e | 5 | * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. |
3efc2fa3 | 6 | * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de> |
9aaf880e FE |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
9aaf880e | 13 | */ |
b21f4b65 | 14 | #include <linux/module.h> |
9aaf880e FE |
15 | #include <linux/irq.h> |
16 | #include <linux/delay.h> | |
17 | #include <linux/err.h> | |
18 | #include <linux/clk.h> | |
5a819ed6 | 19 | #include <linux/hdmi.h> |
6bcf4953 | 20 | #include <linux/mutex.h> |
9aaf880e | 21 | #include <linux/of_device.h> |
80e2f979 | 22 | #include <linux/regmap.h> |
b90120a9 | 23 | #include <linux/spinlock.h> |
9aaf880e | 24 | |
3d1b35a3 | 25 | #include <drm/drm_of.h> |
9aaf880e | 26 | #include <drm/drmP.h> |
2c5b2ccc | 27 | #include <drm/drm_atomic_helper.h> |
9aaf880e FE |
28 | #include <drm/drm_crtc_helper.h> |
29 | #include <drm/drm_edid.h> | |
30 | #include <drm/drm_encoder_slave.h> | |
b21f4b65 | 31 | #include <drm/bridge/dw_hdmi.h> |
9aaf880e | 32 | |
def23aa7 NA |
33 | #include <uapi/linux/media-bus-format.h> |
34 | #include <uapi/linux/videodev2.h> | |
35 | ||
248a86fc TR |
36 | #include "dw-hdmi.h" |
37 | #include "dw-hdmi-audio.h" | |
a616e63c | 38 | #include "dw-hdmi-cec.h" |
9aaf880e | 39 | |
e84b8d75 RK |
40 | #include <media/cec-notifier.h> |
41 | ||
94bb4dc1 | 42 | #define DDC_SEGMENT_ADDR 0x30 |
e84b8d75 | 43 | |
9aaf880e FE |
44 | #define HDMI_EDID_LEN 512 |
45 | ||
9aaf880e FE |
46 | enum hdmi_datamap { |
47 | RGB444_8B = 0x01, | |
48 | RGB444_10B = 0x03, | |
49 | RGB444_12B = 0x05, | |
50 | RGB444_16B = 0x07, | |
51 | YCbCr444_8B = 0x09, | |
52 | YCbCr444_10B = 0x0B, | |
53 | YCbCr444_12B = 0x0D, | |
54 | YCbCr444_16B = 0x0F, | |
55 | YCbCr422_8B = 0x16, | |
56 | YCbCr422_10B = 0x14, | |
57 | YCbCr422_12B = 0x12, | |
58 | }; | |
59 | ||
9aaf880e FE |
60 | static const u16 csc_coeff_default[3][4] = { |
61 | { 0x2000, 0x0000, 0x0000, 0x0000 }, | |
62 | { 0x0000, 0x2000, 0x0000, 0x0000 }, | |
63 | { 0x0000, 0x0000, 0x2000, 0x0000 } | |
64 | }; | |
65 | ||
66 | static const u16 csc_coeff_rgb_out_eitu601[3][4] = { | |
67 | { 0x2000, 0x6926, 0x74fd, 0x010e }, | |
68 | { 0x2000, 0x2cdd, 0x0000, 0x7e9a }, | |
69 | { 0x2000, 0x0000, 0x38b4, 0x7e3b } | |
70 | }; | |
71 | ||
72 | static const u16 csc_coeff_rgb_out_eitu709[3][4] = { | |
73 | { 0x2000, 0x7106, 0x7a02, 0x00a7 }, | |
74 | { 0x2000, 0x3264, 0x0000, 0x7e6d }, | |
75 | { 0x2000, 0x0000, 0x3b61, 0x7e25 } | |
76 | }; | |
77 | ||
78 | static const u16 csc_coeff_rgb_in_eitu601[3][4] = { | |
79 | { 0x2591, 0x1322, 0x074b, 0x0000 }, | |
80 | { 0x6535, 0x2000, 0x7acc, 0x0200 }, | |
81 | { 0x6acd, 0x7534, 0x2000, 0x0200 } | |
82 | }; | |
83 | ||
84 | static const u16 csc_coeff_rgb_in_eitu709[3][4] = { | |
85 | { 0x2dc5, 0x0d9b, 0x049e, 0x0000 }, | |
86 | { 0x62f0, 0x2000, 0x7d11, 0x0200 }, | |
87 | { 0x6756, 0x78ab, 0x2000, 0x0200 } | |
88 | }; | |
89 | ||
90 | struct hdmi_vmode { | |
9aaf880e FE |
91 | bool mdataenablepolarity; |
92 | ||
93 | unsigned int mpixelclock; | |
94 | unsigned int mpixelrepetitioninput; | |
95 | unsigned int mpixelrepetitionoutput; | |
96 | }; | |
97 | ||
98 | struct hdmi_data_info { | |
def23aa7 NA |
99 | unsigned int enc_in_bus_format; |
100 | unsigned int enc_out_bus_format; | |
101 | unsigned int enc_in_encoding; | |
102 | unsigned int enc_out_encoding; | |
9aaf880e FE |
103 | unsigned int pix_repet_factor; |
104 | unsigned int hdcp_enable; | |
105 | struct hdmi_vmode video_mode; | |
106 | }; | |
107 | ||
3efc2fa3 VZ |
108 | struct dw_hdmi_i2c { |
109 | struct i2c_adapter adap; | |
110 | ||
111 | struct mutex lock; /* used to serialize data transfers */ | |
112 | struct completion cmp; | |
113 | u8 stat; | |
114 | ||
115 | u8 slave_reg; | |
116 | bool is_regaddr; | |
94bb4dc1 | 117 | bool is_segment; |
3efc2fa3 VZ |
118 | }; |
119 | ||
faba6c3c LP |
120 | struct dw_hdmi_phy_data { |
121 | enum dw_hdmi_phy_type type; | |
122 | const char *name; | |
b0e583e5 | 123 | unsigned int gen; |
faba6c3c | 124 | bool has_svsret; |
2ef9dfed KB |
125 | int (*configure)(struct dw_hdmi *hdmi, |
126 | const struct dw_hdmi_plat_data *pdata, | |
127 | unsigned long mpixelclock); | |
faba6c3c LP |
128 | }; |
129 | ||
b21f4b65 | 130 | struct dw_hdmi { |
9aaf880e | 131 | struct drm_connector connector; |
70c963ec | 132 | struct drm_bridge bridge; |
9aaf880e | 133 | |
be41fc55 LP |
134 | unsigned int version; |
135 | ||
136 | struct platform_device *audio; | |
a616e63c | 137 | struct platform_device *cec; |
9aaf880e FE |
138 | struct device *dev; |
139 | struct clk *isfr_clk; | |
140 | struct clk *iahb_clk; | |
ebe32c3e | 141 | struct clk *cec_clk; |
3efc2fa3 | 142 | struct dw_hdmi_i2c *i2c; |
9aaf880e FE |
143 | |
144 | struct hdmi_data_info hdmi_data; | |
b21f4b65 AY |
145 | const struct dw_hdmi_plat_data *plat_data; |
146 | ||
9aaf880e FE |
147 | int vic; |
148 | ||
149 | u8 edid[HDMI_EDID_LEN]; | |
9aaf880e | 150 | |
f1585f6e LP |
151 | struct { |
152 | const struct dw_hdmi_phy_ops *ops; | |
153 | const char *name; | |
154 | void *data; | |
155 | bool enabled; | |
156 | } phy; | |
faba6c3c | 157 | |
9aaf880e FE |
158 | struct drm_display_mode previous_mode; |
159 | ||
9aaf880e FE |
160 | struct i2c_adapter *ddc; |
161 | void __iomem *regs; | |
05b1342f | 162 | bool sink_is_hdmi; |
f709ec07 | 163 | bool sink_has_audio; |
9aaf880e | 164 | |
b872a8e1 | 165 | struct mutex mutex; /* for state below and previous_mode */ |
381f05a7 | 166 | enum drm_connector_force force; /* mutex-protected force state */ |
b872a8e1 | 167 | bool disabled; /* DRM has disabled our bridge */ |
381f05a7 | 168 | bool bridge_is_on; /* indicates the bridge is on */ |
aeac23bd RK |
169 | bool rxsense; /* rxsense state */ |
170 | u8 phy_mask; /* desired phy int mask settings */ | |
7cc4ab22 | 171 | u8 mc_clkdis; /* clock disable register */ |
b872a8e1 | 172 | |
b90120a9 | 173 | spinlock_t audio_lock; |
6bcf4953 | 174 | struct mutex audio_mutex; |
9aaf880e | 175 | unsigned int sample_rate; |
b90120a9 RK |
176 | unsigned int audio_cts; |
177 | unsigned int audio_n; | |
178 | bool audio_enable; | |
0cd9d142 | 179 | |
80e2f979 NA |
180 | unsigned int reg_shift; |
181 | struct regmap *regm; | |
a7d555d2 RP |
182 | void (*enable_audio)(struct dw_hdmi *hdmi); |
183 | void (*disable_audio)(struct dw_hdmi *hdmi); | |
e84b8d75 RK |
184 | |
185 | struct cec_notifier *cec_notifier; | |
9aaf880e FE |
186 | }; |
187 | ||
aeac23bd RK |
188 | #define HDMI_IH_PHY_STAT0_RX_SENSE \ |
189 | (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \ | |
190 | HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3) | |
191 | ||
192 | #define HDMI_PHY_RX_SENSE \ | |
193 | (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \ | |
194 | HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3) | |
195 | ||
0cd9d142 AY |
196 | static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset) |
197 | { | |
80e2f979 | 198 | regmap_write(hdmi->regm, offset << hdmi->reg_shift, val); |
0cd9d142 AY |
199 | } |
200 | ||
201 | static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset) | |
202 | { | |
80e2f979 NA |
203 | unsigned int val = 0; |
204 | ||
205 | regmap_read(hdmi->regm, offset << hdmi->reg_shift, &val); | |
206 | ||
207 | return val; | |
0cd9d142 AY |
208 | } |
209 | ||
b21f4b65 | 210 | static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg) |
812bc615 | 211 | { |
80e2f979 | 212 | regmap_update_bits(hdmi->regm, reg << hdmi->reg_shift, mask, data); |
812bc615 RK |
213 | } |
214 | ||
b21f4b65 | 215 | static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg, |
b5878339 | 216 | u8 shift, u8 mask) |
9aaf880e | 217 | { |
812bc615 | 218 | hdmi_modb(hdmi, data << shift, mask, reg); |
9aaf880e FE |
219 | } |
220 | ||
3efc2fa3 VZ |
221 | static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi) |
222 | { | |
223 | /* Software reset */ | |
224 | hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ); | |
225 | ||
226 | /* Set Standard Mode speed (determined to be 100KHz on iMX6) */ | |
227 | hdmi_writeb(hdmi, 0x00, HDMI_I2CM_DIV); | |
228 | ||
229 | /* Set done, not acknowledged and arbitration interrupt polarities */ | |
230 | hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT); | |
231 | hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL, | |
232 | HDMI_I2CM_CTLINT); | |
233 | ||
234 | /* Clear DONE and ERROR interrupts */ | |
235 | hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, | |
236 | HDMI_IH_I2CM_STAT0); | |
237 | ||
238 | /* Mute DONE and ERROR interrupts */ | |
239 | hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, | |
240 | HDMI_IH_MUTE_I2CM_STAT0); | |
241 | } | |
242 | ||
243 | static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi, | |
244 | unsigned char *buf, unsigned int length) | |
245 | { | |
246 | struct dw_hdmi_i2c *i2c = hdmi->i2c; | |
247 | int stat; | |
248 | ||
249 | if (!i2c->is_regaddr) { | |
250 | dev_dbg(hdmi->dev, "set read register address to 0\n"); | |
251 | i2c->slave_reg = 0x00; | |
252 | i2c->is_regaddr = true; | |
253 | } | |
254 | ||
255 | while (length--) { | |
256 | reinit_completion(&i2c->cmp); | |
257 | ||
258 | hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); | |
94bb4dc1 NY |
259 | if (i2c->is_segment) |
260 | hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT, | |
261 | HDMI_I2CM_OPERATION); | |
262 | else | |
263 | hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ, | |
264 | HDMI_I2CM_OPERATION); | |
3efc2fa3 VZ |
265 | |
266 | stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); | |
267 | if (!stat) | |
268 | return -EAGAIN; | |
269 | ||
270 | /* Check for error condition on the bus */ | |
271 | if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR) | |
272 | return -EIO; | |
273 | ||
274 | *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI); | |
275 | } | |
94bb4dc1 | 276 | i2c->is_segment = false; |
3efc2fa3 VZ |
277 | |
278 | return 0; | |
279 | } | |
280 | ||
281 | static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi, | |
282 | unsigned char *buf, unsigned int length) | |
283 | { | |
284 | struct dw_hdmi_i2c *i2c = hdmi->i2c; | |
285 | int stat; | |
286 | ||
287 | if (!i2c->is_regaddr) { | |
288 | /* Use the first write byte as register address */ | |
289 | i2c->slave_reg = buf[0]; | |
290 | length--; | |
291 | buf++; | |
292 | i2c->is_regaddr = true; | |
293 | } | |
294 | ||
295 | while (length--) { | |
296 | reinit_completion(&i2c->cmp); | |
297 | ||
298 | hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO); | |
299 | hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); | |
300 | hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE, | |
301 | HDMI_I2CM_OPERATION); | |
302 | ||
303 | stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); | |
304 | if (!stat) | |
305 | return -EAGAIN; | |
306 | ||
307 | /* Check for error condition on the bus */ | |
308 | if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR) | |
309 | return -EIO; | |
310 | } | |
311 | ||
312 | return 0; | |
313 | } | |
314 | ||
315 | static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap, | |
316 | struct i2c_msg *msgs, int num) | |
317 | { | |
318 | struct dw_hdmi *hdmi = i2c_get_adapdata(adap); | |
319 | struct dw_hdmi_i2c *i2c = hdmi->i2c; | |
320 | u8 addr = msgs[0].addr; | |
321 | int i, ret = 0; | |
322 | ||
323 | dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr); | |
324 | ||
325 | for (i = 0; i < num; i++) { | |
3efc2fa3 VZ |
326 | if (msgs[i].len == 0) { |
327 | dev_dbg(hdmi->dev, | |
328 | "unsupported transfer %d/%d, no data\n", | |
329 | i + 1, num); | |
330 | return -EOPNOTSUPP; | |
331 | } | |
332 | } | |
333 | ||
334 | mutex_lock(&i2c->lock); | |
335 | ||
336 | /* Unmute DONE and ERROR interrupts */ | |
337 | hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0); | |
338 | ||
339 | /* Set slave device address taken from the first I2C message */ | |
340 | hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE); | |
341 | ||
342 | /* Set slave device register address on transfer */ | |
343 | i2c->is_regaddr = false; | |
344 | ||
94bb4dc1 NY |
345 | /* Set segment pointer for I2C extended read mode operation */ |
346 | i2c->is_segment = false; | |
347 | ||
3efc2fa3 VZ |
348 | for (i = 0; i < num; i++) { |
349 | dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n", | |
350 | i + 1, num, msgs[i].len, msgs[i].flags); | |
94bb4dc1 NY |
351 | if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) { |
352 | i2c->is_segment = true; | |
353 | hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR); | |
354 | hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR); | |
355 | } else { | |
356 | if (msgs[i].flags & I2C_M_RD) | |
357 | ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf, | |
358 | msgs[i].len); | |
359 | else | |
360 | ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf, | |
361 | msgs[i].len); | |
362 | } | |
3efc2fa3 VZ |
363 | if (ret < 0) |
364 | break; | |
365 | } | |
366 | ||
367 | if (!ret) | |
368 | ret = num; | |
369 | ||
370 | /* Mute DONE and ERROR interrupts */ | |
371 | hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, | |
372 | HDMI_IH_MUTE_I2CM_STAT0); | |
373 | ||
374 | mutex_unlock(&i2c->lock); | |
375 | ||
376 | return ret; | |
377 | } | |
378 | ||
379 | static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter) | |
380 | { | |
381 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; | |
382 | } | |
383 | ||
384 | static const struct i2c_algorithm dw_hdmi_algorithm = { | |
385 | .master_xfer = dw_hdmi_i2c_xfer, | |
386 | .functionality = dw_hdmi_i2c_func, | |
387 | }; | |
388 | ||
389 | static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi) | |
390 | { | |
391 | struct i2c_adapter *adap; | |
392 | struct dw_hdmi_i2c *i2c; | |
393 | int ret; | |
394 | ||
395 | i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL); | |
396 | if (!i2c) | |
397 | return ERR_PTR(-ENOMEM); | |
398 | ||
399 | mutex_init(&i2c->lock); | |
400 | init_completion(&i2c->cmp); | |
401 | ||
402 | adap = &i2c->adap; | |
403 | adap->class = I2C_CLASS_DDC; | |
404 | adap->owner = THIS_MODULE; | |
405 | adap->dev.parent = hdmi->dev; | |
406 | adap->algo = &dw_hdmi_algorithm; | |
407 | strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name)); | |
408 | i2c_set_adapdata(adap, hdmi); | |
409 | ||
410 | ret = i2c_add_adapter(adap); | |
411 | if (ret) { | |
412 | dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name); | |
413 | devm_kfree(hdmi->dev, i2c); | |
414 | return ERR_PTR(ret); | |
415 | } | |
416 | ||
417 | hdmi->i2c = i2c; | |
418 | ||
419 | dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name); | |
420 | ||
421 | return adap; | |
422 | } | |
423 | ||
351e1354 RK |
424 | static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts, |
425 | unsigned int n) | |
9aaf880e | 426 | { |
622494a3 RK |
427 | /* Must be set/cleared first */ |
428 | hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); | |
9aaf880e FE |
429 | |
430 | /* nshift factor = 0 */ | |
812bc615 | 431 | hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3); |
9aaf880e | 432 | |
9aaf880e FE |
433 | hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) | |
434 | HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); | |
622494a3 RK |
435 | hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2); |
436 | hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1); | |
437 | ||
438 | hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3); | |
439 | hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2); | |
440 | hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1); | |
9aaf880e FE |
441 | } |
442 | ||
b195fbdb | 443 | static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk) |
9aaf880e FE |
444 | { |
445 | unsigned int n = (128 * freq) / 1000; | |
d0c96d16 RK |
446 | unsigned int mult = 1; |
447 | ||
448 | while (freq > 48000) { | |
449 | mult *= 2; | |
450 | freq /= 2; | |
451 | } | |
9aaf880e FE |
452 | |
453 | switch (freq) { | |
454 | case 32000: | |
426701d0 | 455 | if (pixel_clk == 25175000) |
b195fbdb | 456 | n = 4576; |
426701d0 | 457 | else if (pixel_clk == 27027000) |
b195fbdb | 458 | n = 4096; |
426701d0 | 459 | else if (pixel_clk == 74176000 || pixel_clk == 148352000) |
9aaf880e FE |
460 | n = 11648; |
461 | else | |
462 | n = 4096; | |
d0c96d16 | 463 | n *= mult; |
9aaf880e FE |
464 | break; |
465 | ||
466 | case 44100: | |
426701d0 | 467 | if (pixel_clk == 25175000) |
9aaf880e | 468 | n = 7007; |
426701d0 | 469 | else if (pixel_clk == 74176000) |
9aaf880e | 470 | n = 17836; |
426701d0 | 471 | else if (pixel_clk == 148352000) |
b195fbdb | 472 | n = 8918; |
9aaf880e FE |
473 | else |
474 | n = 6272; | |
d0c96d16 | 475 | n *= mult; |
9aaf880e FE |
476 | break; |
477 | ||
478 | case 48000: | |
426701d0 | 479 | if (pixel_clk == 25175000) |
b195fbdb | 480 | n = 6864; |
426701d0 | 481 | else if (pixel_clk == 27027000) |
b195fbdb | 482 | n = 6144; |
426701d0 | 483 | else if (pixel_clk == 74176000) |
9aaf880e | 484 | n = 11648; |
426701d0 | 485 | else if (pixel_clk == 148352000) |
b195fbdb | 486 | n = 5824; |
9aaf880e FE |
487 | else |
488 | n = 6144; | |
d0c96d16 | 489 | n *= mult; |
9aaf880e FE |
490 | break; |
491 | ||
492 | default: | |
493 | break; | |
494 | } | |
495 | ||
496 | return n; | |
497 | } | |
498 | ||
b21f4b65 | 499 | static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi, |
b195fbdb | 500 | unsigned long pixel_clk, unsigned int sample_rate) |
9aaf880e | 501 | { |
dfbdaf50 | 502 | unsigned long ftdms = pixel_clk; |
f879b38f | 503 | unsigned int n, cts; |
dfbdaf50 | 504 | u64 tmp; |
9aaf880e | 505 | |
b195fbdb | 506 | n = hdmi_compute_n(sample_rate, pixel_clk); |
9aaf880e | 507 | |
dfbdaf50 RK |
508 | /* |
509 | * Compute the CTS value from the N value. Note that CTS and N | |
510 | * can be up to 20 bits in total, so we need 64-bit math. Also | |
511 | * note that our TDMS clock is not fully accurate; it is accurate | |
512 | * to kHz. This can introduce an unnecessary remainder in the | |
513 | * calculation below, so we don't try to warn about that. | |
514 | */ | |
515 | tmp = (u64)ftdms * n; | |
516 | do_div(tmp, 128 * sample_rate); | |
517 | cts = tmp; | |
518 | ||
519 | dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n", | |
520 | __func__, sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000, | |
521 | n, cts); | |
9aaf880e | 522 | |
b90120a9 RK |
523 | spin_lock_irq(&hdmi->audio_lock); |
524 | hdmi->audio_n = n; | |
525 | hdmi->audio_cts = cts; | |
526 | hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0); | |
527 | spin_unlock_irq(&hdmi->audio_lock); | |
9aaf880e FE |
528 | } |
529 | ||
b21f4b65 | 530 | static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi) |
9aaf880e | 531 | { |
6bcf4953 | 532 | mutex_lock(&hdmi->audio_mutex); |
b195fbdb | 533 | hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate); |
6bcf4953 | 534 | mutex_unlock(&hdmi->audio_mutex); |
9aaf880e FE |
535 | } |
536 | ||
b21f4b65 | 537 | static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi) |
9aaf880e | 538 | { |
6bcf4953 | 539 | mutex_lock(&hdmi->audio_mutex); |
f879b38f | 540 | hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock, |
b195fbdb | 541 | hdmi->sample_rate); |
6bcf4953 | 542 | mutex_unlock(&hdmi->audio_mutex); |
9aaf880e FE |
543 | } |
544 | ||
b5814fff RK |
545 | void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate) |
546 | { | |
547 | mutex_lock(&hdmi->audio_mutex); | |
548 | hdmi->sample_rate = rate; | |
549 | hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock, | |
b195fbdb | 550 | hdmi->sample_rate); |
b5814fff RK |
551 | mutex_unlock(&hdmi->audio_mutex); |
552 | } | |
553 | EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate); | |
554 | ||
57fbc055 RP |
555 | static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi, bool enable) |
556 | { | |
7cc4ab22 RK |
557 | if (enable) |
558 | hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE; | |
559 | else | |
560 | hdmi->mc_clkdis |= HDMI_MC_CLKDIS_AUDCLK_DISABLE; | |
561 | hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); | |
57fbc055 RP |
562 | } |
563 | ||
a7d555d2 RP |
564 | static void dw_hdmi_ahb_audio_enable(struct dw_hdmi *hdmi) |
565 | { | |
566 | hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n); | |
567 | } | |
568 | ||
569 | static void dw_hdmi_ahb_audio_disable(struct dw_hdmi *hdmi) | |
570 | { | |
571 | hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0); | |
572 | } | |
573 | ||
574 | static void dw_hdmi_i2s_audio_enable(struct dw_hdmi *hdmi) | |
575 | { | |
576 | hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n); | |
57fbc055 RP |
577 | hdmi_enable_audio_clk(hdmi, true); |
578 | } | |
579 | ||
580 | static void dw_hdmi_i2s_audio_disable(struct dw_hdmi *hdmi) | |
581 | { | |
582 | hdmi_enable_audio_clk(hdmi, false); | |
a7d555d2 RP |
583 | } |
584 | ||
b90120a9 RK |
585 | void dw_hdmi_audio_enable(struct dw_hdmi *hdmi) |
586 | { | |
587 | unsigned long flags; | |
588 | ||
589 | spin_lock_irqsave(&hdmi->audio_lock, flags); | |
590 | hdmi->audio_enable = true; | |
a7d555d2 RP |
591 | if (hdmi->enable_audio) |
592 | hdmi->enable_audio(hdmi); | |
b90120a9 RK |
593 | spin_unlock_irqrestore(&hdmi->audio_lock, flags); |
594 | } | |
595 | EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable); | |
596 | ||
597 | void dw_hdmi_audio_disable(struct dw_hdmi *hdmi) | |
598 | { | |
599 | unsigned long flags; | |
600 | ||
601 | spin_lock_irqsave(&hdmi->audio_lock, flags); | |
602 | hdmi->audio_enable = false; | |
a7d555d2 RP |
603 | if (hdmi->disable_audio) |
604 | hdmi->disable_audio(hdmi); | |
b90120a9 RK |
605 | spin_unlock_irqrestore(&hdmi->audio_lock, flags); |
606 | } | |
607 | EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable); | |
608 | ||
def23aa7 NA |
609 | static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format) |
610 | { | |
611 | switch (bus_format) { | |
612 | case MEDIA_BUS_FMT_RGB888_1X24: | |
613 | case MEDIA_BUS_FMT_RGB101010_1X30: | |
614 | case MEDIA_BUS_FMT_RGB121212_1X36: | |
615 | case MEDIA_BUS_FMT_RGB161616_1X48: | |
616 | return true; | |
617 | ||
618 | default: | |
619 | return false; | |
620 | } | |
621 | } | |
622 | ||
623 | static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format) | |
624 | { | |
625 | switch (bus_format) { | |
626 | case MEDIA_BUS_FMT_YUV8_1X24: | |
627 | case MEDIA_BUS_FMT_YUV10_1X30: | |
628 | case MEDIA_BUS_FMT_YUV12_1X36: | |
629 | case MEDIA_BUS_FMT_YUV16_1X48: | |
630 | return true; | |
631 | ||
632 | default: | |
633 | return false; | |
634 | } | |
635 | } | |
636 | ||
637 | static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format) | |
638 | { | |
639 | switch (bus_format) { | |
640 | case MEDIA_BUS_FMT_UYVY8_1X16: | |
641 | case MEDIA_BUS_FMT_UYVY10_1X20: | |
642 | case MEDIA_BUS_FMT_UYVY12_1X24: | |
643 | return true; | |
644 | ||
645 | default: | |
646 | return false; | |
647 | } | |
648 | } | |
649 | ||
def23aa7 NA |
650 | static int hdmi_bus_fmt_color_depth(unsigned int bus_format) |
651 | { | |
652 | switch (bus_format) { | |
653 | case MEDIA_BUS_FMT_RGB888_1X24: | |
654 | case MEDIA_BUS_FMT_YUV8_1X24: | |
655 | case MEDIA_BUS_FMT_UYVY8_1X16: | |
656 | case MEDIA_BUS_FMT_UYYVYY8_0_5X24: | |
657 | return 8; | |
658 | ||
659 | case MEDIA_BUS_FMT_RGB101010_1X30: | |
660 | case MEDIA_BUS_FMT_YUV10_1X30: | |
661 | case MEDIA_BUS_FMT_UYVY10_1X20: | |
662 | case MEDIA_BUS_FMT_UYYVYY10_0_5X30: | |
663 | return 10; | |
664 | ||
665 | case MEDIA_BUS_FMT_RGB121212_1X36: | |
666 | case MEDIA_BUS_FMT_YUV12_1X36: | |
667 | case MEDIA_BUS_FMT_UYVY12_1X24: | |
668 | case MEDIA_BUS_FMT_UYYVYY12_0_5X36: | |
669 | return 12; | |
670 | ||
671 | case MEDIA_BUS_FMT_RGB161616_1X48: | |
672 | case MEDIA_BUS_FMT_YUV16_1X48: | |
673 | case MEDIA_BUS_FMT_UYYVYY16_0_5X48: | |
674 | return 16; | |
675 | ||
676 | default: | |
677 | return 0; | |
678 | } | |
679 | } | |
680 | ||
9aaf880e FE |
681 | /* |
682 | * this submodule is responsible for the video data synchronization. | |
683 | * for example, for RGB 4:4:4 input, the data map is defined as | |
684 | * pin{47~40} <==> R[7:0] | |
685 | * pin{31~24} <==> G[7:0] | |
686 | * pin{15~8} <==> B[7:0] | |
687 | */ | |
b21f4b65 | 688 | static void hdmi_video_sample(struct dw_hdmi *hdmi) |
9aaf880e FE |
689 | { |
690 | int color_format = 0; | |
691 | u8 val; | |
692 | ||
def23aa7 NA |
693 | switch (hdmi->hdmi_data.enc_in_bus_format) { |
694 | case MEDIA_BUS_FMT_RGB888_1X24: | |
695 | color_format = 0x01; | |
696 | break; | |
697 | case MEDIA_BUS_FMT_RGB101010_1X30: | |
698 | color_format = 0x03; | |
699 | break; | |
700 | case MEDIA_BUS_FMT_RGB121212_1X36: | |
701 | color_format = 0x05; | |
702 | break; | |
703 | case MEDIA_BUS_FMT_RGB161616_1X48: | |
704 | color_format = 0x07; | |
705 | break; | |
706 | ||
707 | case MEDIA_BUS_FMT_YUV8_1X24: | |
708 | case MEDIA_BUS_FMT_UYYVYY8_0_5X24: | |
709 | color_format = 0x09; | |
710 | break; | |
711 | case MEDIA_BUS_FMT_YUV10_1X30: | |
712 | case MEDIA_BUS_FMT_UYYVYY10_0_5X30: | |
713 | color_format = 0x0B; | |
714 | break; | |
715 | case MEDIA_BUS_FMT_YUV12_1X36: | |
716 | case MEDIA_BUS_FMT_UYYVYY12_0_5X36: | |
717 | color_format = 0x0D; | |
718 | break; | |
719 | case MEDIA_BUS_FMT_YUV16_1X48: | |
720 | case MEDIA_BUS_FMT_UYYVYY16_0_5X48: | |
721 | color_format = 0x0F; | |
722 | break; | |
723 | ||
724 | case MEDIA_BUS_FMT_UYVY8_1X16: | |
725 | color_format = 0x16; | |
726 | break; | |
727 | case MEDIA_BUS_FMT_UYVY10_1X20: | |
728 | color_format = 0x14; | |
729 | break; | |
730 | case MEDIA_BUS_FMT_UYVY12_1X24: | |
731 | color_format = 0x12; | |
732 | break; | |
733 | ||
734 | default: | |
735 | return; | |
9aaf880e FE |
736 | } |
737 | ||
738 | val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE | | |
739 | ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) & | |
740 | HDMI_TX_INVID0_VIDEO_MAPPING_MASK); | |
741 | hdmi_writeb(hdmi, val, HDMI_TX_INVID0); | |
742 | ||
743 | /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */ | |
744 | val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE | | |
745 | HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE | | |
746 | HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE; | |
747 | hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING); | |
748 | hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0); | |
749 | hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1); | |
750 | hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0); | |
751 | hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1); | |
752 | hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0); | |
753 | hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1); | |
754 | } | |
755 | ||
b21f4b65 | 756 | static int is_color_space_conversion(struct dw_hdmi *hdmi) |
9aaf880e | 757 | { |
def23aa7 | 758 | return hdmi->hdmi_data.enc_in_bus_format != hdmi->hdmi_data.enc_out_bus_format; |
9aaf880e FE |
759 | } |
760 | ||
b21f4b65 | 761 | static int is_color_space_decimation(struct dw_hdmi *hdmi) |
9aaf880e | 762 | { |
def23aa7 | 763 | if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) |
ba92b225 | 764 | return 0; |
def23aa7 NA |
765 | |
766 | if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) || | |
767 | hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format)) | |
ba92b225 | 768 | return 1; |
def23aa7 | 769 | |
ba92b225 | 770 | return 0; |
9aaf880e FE |
771 | } |
772 | ||
b21f4b65 | 773 | static int is_color_space_interpolation(struct dw_hdmi *hdmi) |
9aaf880e | 774 | { |
def23aa7 | 775 | if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format)) |
ba92b225 | 776 | return 0; |
def23aa7 NA |
777 | |
778 | if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || | |
779 | hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) | |
ba92b225 | 780 | return 1; |
def23aa7 | 781 | |
ba92b225 | 782 | return 0; |
9aaf880e FE |
783 | } |
784 | ||
b21f4b65 | 785 | static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi) |
9aaf880e FE |
786 | { |
787 | const u16 (*csc_coeff)[3][4] = &csc_coeff_default; | |
c082f9d7 | 788 | unsigned i; |
9aaf880e | 789 | u32 csc_scale = 1; |
9aaf880e FE |
790 | |
791 | if (is_color_space_conversion(hdmi)) { | |
def23aa7 NA |
792 | if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) { |
793 | if (hdmi->hdmi_data.enc_out_encoding == | |
794 | V4L2_YCBCR_ENC_601) | |
9aaf880e FE |
795 | csc_coeff = &csc_coeff_rgb_out_eitu601; |
796 | else | |
797 | csc_coeff = &csc_coeff_rgb_out_eitu709; | |
def23aa7 NA |
798 | } else if (hdmi_bus_fmt_is_rgb( |
799 | hdmi->hdmi_data.enc_in_bus_format)) { | |
800 | if (hdmi->hdmi_data.enc_out_encoding == | |
801 | V4L2_YCBCR_ENC_601) | |
9aaf880e FE |
802 | csc_coeff = &csc_coeff_rgb_in_eitu601; |
803 | else | |
804 | csc_coeff = &csc_coeff_rgb_in_eitu709; | |
805 | csc_scale = 0; | |
806 | } | |
807 | } | |
808 | ||
c082f9d7 RK |
809 | /* The CSC registers are sequential, alternating MSB then LSB */ |
810 | for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) { | |
811 | u16 coeff_a = (*csc_coeff)[0][i]; | |
812 | u16 coeff_b = (*csc_coeff)[1][i]; | |
813 | u16 coeff_c = (*csc_coeff)[2][i]; | |
814 | ||
b5878339 | 815 | hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2); |
c082f9d7 RK |
816 | hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2); |
817 | hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2); | |
818 | hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2); | |
b5878339 | 819 | hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2); |
c082f9d7 RK |
820 | hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2); |
821 | } | |
9aaf880e | 822 | |
812bc615 RK |
823 | hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK, |
824 | HDMI_CSC_SCALE); | |
9aaf880e FE |
825 | } |
826 | ||
b21f4b65 | 827 | static void hdmi_video_csc(struct dw_hdmi *hdmi) |
9aaf880e FE |
828 | { |
829 | int color_depth = 0; | |
830 | int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE; | |
831 | int decimation = 0; | |
9aaf880e FE |
832 | |
833 | /* YCC422 interpolation to 444 mode */ | |
834 | if (is_color_space_interpolation(hdmi)) | |
835 | interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1; | |
836 | else if (is_color_space_decimation(hdmi)) | |
837 | decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3; | |
838 | ||
def23aa7 NA |
839 | switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) { |
840 | case 8: | |
9aaf880e | 841 | color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP; |
def23aa7 NA |
842 | break; |
843 | case 10: | |
9aaf880e | 844 | color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP; |
def23aa7 NA |
845 | break; |
846 | case 12: | |
9aaf880e | 847 | color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP; |
def23aa7 NA |
848 | break; |
849 | case 16: | |
9aaf880e | 850 | color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP; |
def23aa7 NA |
851 | break; |
852 | ||
853 | default: | |
9aaf880e | 854 | return; |
def23aa7 | 855 | } |
9aaf880e FE |
856 | |
857 | /* Configure the CSC registers */ | |
858 | hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG); | |
812bc615 RK |
859 | hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK, |
860 | HDMI_CSC_SCALE); | |
9aaf880e | 861 | |
b21f4b65 | 862 | dw_hdmi_update_csc_coeffs(hdmi); |
9aaf880e FE |
863 | } |
864 | ||
865 | /* | |
866 | * HDMI video packetizer is used to packetize the data. | |
867 | * for example, if input is YCC422 mode or repeater is used, | |
868 | * data should be repacked this module can be bypassed. | |
869 | */ | |
b21f4b65 | 870 | static void hdmi_video_packetize(struct dw_hdmi *hdmi) |
9aaf880e FE |
871 | { |
872 | unsigned int color_depth = 0; | |
873 | unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit; | |
874 | unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP; | |
875 | struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data; | |
bebdf664 | 876 | u8 val, vp_conf; |
9aaf880e | 877 | |
def23aa7 NA |
878 | if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || |
879 | hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) { | |
880 | switch (hdmi_bus_fmt_color_depth( | |
881 | hdmi->hdmi_data.enc_out_bus_format)) { | |
882 | case 8: | |
9aaf880e FE |
883 | color_depth = 4; |
884 | output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; | |
def23aa7 NA |
885 | break; |
886 | case 10: | |
9aaf880e | 887 | color_depth = 5; |
def23aa7 NA |
888 | break; |
889 | case 12: | |
9aaf880e | 890 | color_depth = 6; |
def23aa7 NA |
891 | break; |
892 | case 16: | |
9aaf880e | 893 | color_depth = 7; |
def23aa7 NA |
894 | break; |
895 | default: | |
896 | output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; | |
b5878339 | 897 | } |
def23aa7 NA |
898 | } else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) { |
899 | switch (hdmi_bus_fmt_color_depth( | |
900 | hdmi->hdmi_data.enc_out_bus_format)) { | |
901 | case 0: | |
902 | case 8: | |
9aaf880e | 903 | remap_size = HDMI_VP_REMAP_YCC422_16bit; |
def23aa7 NA |
904 | break; |
905 | case 10: | |
9aaf880e | 906 | remap_size = HDMI_VP_REMAP_YCC422_20bit; |
def23aa7 NA |
907 | break; |
908 | case 12: | |
9aaf880e | 909 | remap_size = HDMI_VP_REMAP_YCC422_24bit; |
def23aa7 NA |
910 | break; |
911 | ||
912 | default: | |
9aaf880e | 913 | return; |
def23aa7 | 914 | } |
9aaf880e | 915 | output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422; |
b5878339 | 916 | } else { |
9aaf880e | 917 | return; |
b5878339 | 918 | } |
9aaf880e FE |
919 | |
920 | /* set the packetizer registers */ | |
921 | val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) & | |
922 | HDMI_VP_PR_CD_COLOR_DEPTH_MASK) | | |
923 | ((hdmi_data->pix_repet_factor << | |
924 | HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) & | |
925 | HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK); | |
926 | hdmi_writeb(hdmi, val, HDMI_VP_PR_CD); | |
927 | ||
812bc615 RK |
928 | hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE, |
929 | HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF); | |
9aaf880e FE |
930 | |
931 | /* Data from pixel repeater block */ | |
932 | if (hdmi_data->pix_repet_factor > 1) { | |
bebdf664 RK |
933 | vp_conf = HDMI_VP_CONF_PR_EN_ENABLE | |
934 | HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER; | |
9aaf880e | 935 | } else { /* data from packetizer block */ |
bebdf664 RK |
936 | vp_conf = HDMI_VP_CONF_PR_EN_DISABLE | |
937 | HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER; | |
9aaf880e FE |
938 | } |
939 | ||
bebdf664 RK |
940 | hdmi_modb(hdmi, vp_conf, |
941 | HDMI_VP_CONF_PR_EN_MASK | | |
942 | HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF); | |
943 | ||
812bc615 RK |
944 | hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET, |
945 | HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF); | |
9aaf880e FE |
946 | |
947 | hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP); | |
948 | ||
949 | if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) { | |
bebdf664 RK |
950 | vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | |
951 | HDMI_VP_CONF_PP_EN_ENABLE | | |
952 | HDMI_VP_CONF_YCC422_EN_DISABLE; | |
9aaf880e | 953 | } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) { |
bebdf664 RK |
954 | vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | |
955 | HDMI_VP_CONF_PP_EN_DISABLE | | |
956 | HDMI_VP_CONF_YCC422_EN_ENABLE; | |
9aaf880e | 957 | } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) { |
bebdf664 RK |
958 | vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE | |
959 | HDMI_VP_CONF_PP_EN_DISABLE | | |
960 | HDMI_VP_CONF_YCC422_EN_DISABLE; | |
9aaf880e FE |
961 | } else { |
962 | return; | |
963 | } | |
964 | ||
bebdf664 RK |
965 | hdmi_modb(hdmi, vp_conf, |
966 | HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK | | |
967 | HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF); | |
968 | ||
812bc615 RK |
969 | hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE | |
970 | HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE, | |
971 | HDMI_VP_STUFF_PP_STUFFING_MASK | | |
972 | HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF); | |
9aaf880e | 973 | |
812bc615 RK |
974 | hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK, |
975 | HDMI_VP_CONF); | |
9aaf880e FE |
976 | } |
977 | ||
f1585f6e LP |
978 | /* ----------------------------------------------------------------------------- |
979 | * Synopsys PHY Handling | |
980 | */ | |
981 | ||
b21f4b65 | 982 | static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi, |
b5878339 | 983 | unsigned char bit) |
9aaf880e | 984 | { |
812bc615 RK |
985 | hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET, |
986 | HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0); | |
9aaf880e FE |
987 | } |
988 | ||
b21f4b65 | 989 | static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec) |
9aaf880e | 990 | { |
a4d3b8b0 AY |
991 | u32 val; |
992 | ||
993 | while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) { | |
9aaf880e FE |
994 | if (msec-- == 0) |
995 | return false; | |
0e6bcf3a | 996 | udelay(1000); |
9aaf880e | 997 | } |
a4d3b8b0 AY |
998 | hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0); |
999 | ||
9aaf880e FE |
1000 | return true; |
1001 | } | |
1002 | ||
2ef9dfed KB |
1003 | void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data, |
1004 | unsigned char addr) | |
9aaf880e FE |
1005 | { |
1006 | hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0); | |
1007 | hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR); | |
1008 | hdmi_writeb(hdmi, (unsigned char)(data >> 8), | |
b5878339 | 1009 | HDMI_PHY_I2CM_DATAO_1_ADDR); |
9aaf880e | 1010 | hdmi_writeb(hdmi, (unsigned char)(data >> 0), |
b5878339 | 1011 | HDMI_PHY_I2CM_DATAO_0_ADDR); |
9aaf880e | 1012 | hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE, |
b5878339 | 1013 | HDMI_PHY_I2CM_OPERATION_ADDR); |
9aaf880e FE |
1014 | hdmi_phy_wait_i2c_done(hdmi, 1000); |
1015 | } | |
2ef9dfed | 1016 | EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_write); |
9aaf880e | 1017 | |
2fada109 | 1018 | static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable) |
9aaf880e | 1019 | { |
2fada109 | 1020 | hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0, |
9aaf880e FE |
1021 | HDMI_PHY_CONF0_PDZ_OFFSET, |
1022 | HDMI_PHY_CONF0_PDZ_MASK); | |
1023 | } | |
1024 | ||
b21f4b65 | 1025 | static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable) |
9aaf880e FE |
1026 | { |
1027 | hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, | |
1028 | HDMI_PHY_CONF0_ENTMDS_OFFSET, | |
1029 | HDMI_PHY_CONF0_ENTMDS_MASK); | |
1030 | } | |
1031 | ||
f4104e8f | 1032 | static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable) |
d346c14e AY |
1033 | { |
1034 | hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, | |
f4104e8f LP |
1035 | HDMI_PHY_CONF0_SVSRET_OFFSET, |
1036 | HDMI_PHY_CONF0_SVSRET_MASK); | |
d346c14e AY |
1037 | } |
1038 | ||
5765916a | 1039 | void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable) |
9aaf880e FE |
1040 | { |
1041 | hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, | |
1042 | HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET, | |
1043 | HDMI_PHY_CONF0_GEN2_PDDQ_MASK); | |
1044 | } | |
5765916a | 1045 | EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_pddq); |
9aaf880e | 1046 | |
5765916a | 1047 | void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable) |
9aaf880e FE |
1048 | { |
1049 | hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, | |
1050 | HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET, | |
1051 | HDMI_PHY_CONF0_GEN2_TXPWRON_MASK); | |
1052 | } | |
5765916a | 1053 | EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_txpwron); |
9aaf880e | 1054 | |
b21f4b65 | 1055 | static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable) |
9aaf880e FE |
1056 | { |
1057 | hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, | |
1058 | HDMI_PHY_CONF0_SELDATAENPOL_OFFSET, | |
1059 | HDMI_PHY_CONF0_SELDATAENPOL_MASK); | |
1060 | } | |
1061 | ||
b21f4b65 | 1062 | static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable) |
9aaf880e FE |
1063 | { |
1064 | hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, | |
1065 | HDMI_PHY_CONF0_SELDIPIF_OFFSET, | |
1066 | HDMI_PHY_CONF0_SELDIPIF_MASK); | |
1067 | } | |
1068 | ||
5765916a JS |
1069 | void dw_hdmi_phy_reset(struct dw_hdmi *hdmi) |
1070 | { | |
1071 | /* PHY reset. The reset signal is active high on Gen2 PHYs. */ | |
1072 | hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ); | |
1073 | hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ); | |
1074 | } | |
1075 | EXPORT_SYMBOL_GPL(dw_hdmi_phy_reset); | |
1076 | ||
1077 | void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address) | |
1078 | { | |
1079 | hdmi_phy_test_clear(hdmi, 1); | |
1080 | hdmi_writeb(hdmi, address, HDMI_PHY_I2CM_SLAVE_ADDR); | |
1081 | hdmi_phy_test_clear(hdmi, 0); | |
1082 | } | |
1083 | EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_set_addr); | |
1084 | ||
b0e583e5 LP |
1085 | static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi) |
1086 | { | |
f1585f6e | 1087 | const struct dw_hdmi_phy_data *phy = hdmi->phy.data; |
b0e583e5 LP |
1088 | unsigned int i; |
1089 | u16 val; | |
1090 | ||
1091 | if (phy->gen == 1) { | |
1092 | dw_hdmi_phy_enable_tmds(hdmi, 0); | |
1093 | dw_hdmi_phy_enable_powerdown(hdmi, true); | |
1094 | return; | |
1095 | } | |
1096 | ||
1097 | dw_hdmi_phy_gen2_txpwron(hdmi, 0); | |
1098 | ||
1099 | /* | |
1100 | * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went | |
1101 | * to low power mode. | |
1102 | */ | |
1103 | for (i = 0; i < 5; ++i) { | |
1104 | val = hdmi_readb(hdmi, HDMI_PHY_STAT0); | |
1105 | if (!(val & HDMI_PHY_TX_PHY_LOCK)) | |
1106 | break; | |
1107 | ||
1108 | usleep_range(1000, 2000); | |
1109 | } | |
1110 | ||
1111 | if (val & HDMI_PHY_TX_PHY_LOCK) | |
1112 | dev_warn(hdmi->dev, "PHY failed to power down\n"); | |
1113 | else | |
1114 | dev_dbg(hdmi->dev, "PHY powered down in %u iterations\n", i); | |
1115 | ||
1116 | dw_hdmi_phy_gen2_pddq(hdmi, 1); | |
1117 | } | |
1118 | ||
181e0ef0 LP |
1119 | static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi) |
1120 | { | |
f1585f6e | 1121 | const struct dw_hdmi_phy_data *phy = hdmi->phy.data; |
181e0ef0 LP |
1122 | unsigned int i; |
1123 | u8 val; | |
1124 | ||
1125 | if (phy->gen == 1) { | |
1126 | dw_hdmi_phy_enable_powerdown(hdmi, false); | |
1127 | ||
1128 | /* Toggle TMDS enable. */ | |
1129 | dw_hdmi_phy_enable_tmds(hdmi, 0); | |
1130 | dw_hdmi_phy_enable_tmds(hdmi, 1); | |
1131 | return 0; | |
1132 | } | |
1133 | ||
1134 | dw_hdmi_phy_gen2_txpwron(hdmi, 1); | |
1135 | dw_hdmi_phy_gen2_pddq(hdmi, 0); | |
1136 | ||
1137 | /* Wait for PHY PLL lock */ | |
1138 | for (i = 0; i < 5; ++i) { | |
1139 | val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK; | |
1140 | if (val) | |
1141 | break; | |
1142 | ||
1143 | usleep_range(1000, 2000); | |
1144 | } | |
1145 | ||
1146 | if (!val) { | |
1147 | dev_err(hdmi->dev, "PHY PLL failed to lock\n"); | |
1148 | return -ETIMEDOUT; | |
1149 | } | |
1150 | ||
1151 | dev_dbg(hdmi->dev, "PHY PLL locked %u iterations\n", i); | |
1152 | return 0; | |
1153 | } | |
1154 | ||
2ef9dfed KB |
1155 | /* |
1156 | * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available | |
1157 | * information the DWC MHL PHY has the same register layout and is thus also | |
1158 | * supported by this function. | |
1159 | */ | |
1160 | static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, | |
1161 | const struct dw_hdmi_plat_data *pdata, | |
1162 | unsigned long mpixelclock) | |
9aaf880e | 1163 | { |
39cc1535 RK |
1164 | const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg; |
1165 | const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr; | |
1166 | const struct dw_hdmi_phy_config *phy_config = pdata->phy_config; | |
9aaf880e | 1167 | |
39cc1535 RK |
1168 | /* PLL/MPLL Cfg - always match on final entry */ |
1169 | for (; mpll_config->mpixelclock != ~0UL; mpll_config++) | |
2ef9dfed | 1170 | if (mpixelclock <= mpll_config->mpixelclock) |
39cc1535 RK |
1171 | break; |
1172 | ||
1173 | for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++) | |
2ef9dfed | 1174 | if (mpixelclock <= curr_ctrl->mpixelclock) |
39cc1535 RK |
1175 | break; |
1176 | ||
1177 | for (; phy_config->mpixelclock != ~0UL; phy_config++) | |
2ef9dfed | 1178 | if (mpixelclock <= phy_config->mpixelclock) |
39cc1535 RK |
1179 | break; |
1180 | ||
1181 | if (mpll_config->mpixelclock == ~0UL || | |
1182 | curr_ctrl->mpixelclock == ~0UL || | |
2ef9dfed | 1183 | phy_config->mpixelclock == ~0UL) |
39cc1535 | 1184 | return -EINVAL; |
2ef9dfed KB |
1185 | |
1186 | dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce, | |
1187 | HDMI_3D_TX_PHY_CPCE_CTRL); | |
1188 | dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp, | |
1189 | HDMI_3D_TX_PHY_GMPCTRL); | |
1190 | dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0], | |
1191 | HDMI_3D_TX_PHY_CURRCTRL); | |
1192 | ||
1193 | dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL); | |
1194 | dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK, | |
1195 | HDMI_3D_TX_PHY_MSM_CTRL); | |
1196 | ||
1197 | dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM); | |
1198 | dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, | |
1199 | HDMI_3D_TX_PHY_CKSYMTXCTRL); | |
1200 | dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, | |
1201 | HDMI_3D_TX_PHY_VLEVCTRL); | |
1202 | ||
1203 | /* Override and disable clock termination. */ | |
1204 | dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE, | |
1205 | HDMI_3D_TX_PHY_CKCALCTRL); | |
1206 | ||
1207 | return 0; | |
1208 | } | |
1209 | ||
1210 | static int hdmi_phy_configure(struct dw_hdmi *hdmi) | |
1211 | { | |
1212 | const struct dw_hdmi_phy_data *phy = hdmi->phy.data; | |
1213 | const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; | |
1214 | unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock; | |
1215 | int ret; | |
39cc1535 | 1216 | |
b0e583e5 | 1217 | dw_hdmi_phy_power_off(hdmi); |
9aaf880e | 1218 | |
2668db37 | 1219 | /* Leave low power consumption mode by asserting SVSRET. */ |
f1585f6e | 1220 | if (phy->has_svsret) |
2668db37 LP |
1221 | dw_hdmi_phy_enable_svsret(hdmi, 1); |
1222 | ||
5765916a | 1223 | dw_hdmi_phy_reset(hdmi); |
9aaf880e FE |
1224 | |
1225 | hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST); | |
1226 | ||
5765916a | 1227 | dw_hdmi_phy_i2c_set_addr(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2); |
9aaf880e | 1228 | |
2ef9dfed KB |
1229 | /* Write to the PHY as configured by the platform */ |
1230 | if (pdata->configure_phy) | |
1231 | ret = pdata->configure_phy(hdmi, pdata, mpixelclock); | |
1232 | else | |
1233 | ret = phy->configure(hdmi, pdata, mpixelclock); | |
1234 | if (ret) { | |
1235 | dev_err(hdmi->dev, "PHY configuration failed (clock %lu)\n", | |
1236 | mpixelclock); | |
1237 | return ret; | |
1238 | } | |
9aaf880e | 1239 | |
181e0ef0 | 1240 | return dw_hdmi_phy_power_on(hdmi); |
9aaf880e FE |
1241 | } |
1242 | ||
f1585f6e LP |
1243 | static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data, |
1244 | struct drm_display_mode *mode) | |
9aaf880e FE |
1245 | { |
1246 | int i, ret; | |
9aaf880e FE |
1247 | |
1248 | /* HDMI Phy spec says to do the phy initialization sequence twice */ | |
1249 | for (i = 0; i < 2; i++) { | |
b21f4b65 AY |
1250 | dw_hdmi_phy_sel_data_en_pol(hdmi, 1); |
1251 | dw_hdmi_phy_sel_interface_control(hdmi, 0); | |
9aaf880e | 1252 | |
8b9e1c0d | 1253 | ret = hdmi_phy_configure(hdmi); |
9aaf880e FE |
1254 | if (ret) |
1255 | return ret; | |
1256 | } | |
1257 | ||
9aaf880e FE |
1258 | return 0; |
1259 | } | |
1260 | ||
f1585f6e LP |
1261 | static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data) |
1262 | { | |
1263 | dw_hdmi_phy_power_off(hdmi); | |
1264 | } | |
1265 | ||
5765916a JS |
1266 | enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, |
1267 | void *data) | |
f1585f6e LP |
1268 | { |
1269 | return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ? | |
1270 | connector_status_connected : connector_status_disconnected; | |
1271 | } | |
5765916a | 1272 | EXPORT_SYMBOL_GPL(dw_hdmi_phy_read_hpd); |
f1585f6e | 1273 | |
5765916a JS |
1274 | void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data, |
1275 | bool force, bool disabled, bool rxsense) | |
386d3299 NA |
1276 | { |
1277 | u8 old_mask = hdmi->phy_mask; | |
1278 | ||
1279 | if (force || disabled || !rxsense) | |
1280 | hdmi->phy_mask |= HDMI_PHY_RX_SENSE; | |
1281 | else | |
1282 | hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE; | |
1283 | ||
1284 | if (old_mask != hdmi->phy_mask) | |
1285 | hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0); | |
1286 | } | |
5765916a | 1287 | EXPORT_SYMBOL_GPL(dw_hdmi_phy_update_hpd); |
386d3299 | 1288 | |
5765916a | 1289 | void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data) |
386d3299 NA |
1290 | { |
1291 | /* | |
1292 | * Configure the PHY RX SENSE and HPD interrupts polarities and clear | |
1293 | * any pending interrupt. | |
1294 | */ | |
1295 | hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0); | |
1296 | hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, | |
1297 | HDMI_IH_PHY_STAT0); | |
1298 | ||
1299 | /* Enable cable hot plug irq. */ | |
1300 | hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0); | |
1301 | ||
1302 | /* Clear and unmute interrupts. */ | |
1303 | hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, | |
1304 | HDMI_IH_PHY_STAT0); | |
1305 | hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE), | |
1306 | HDMI_IH_MUTE_PHY_STAT0); | |
1307 | } | |
5765916a | 1308 | EXPORT_SYMBOL_GPL(dw_hdmi_phy_setup_hpd); |
386d3299 | 1309 | |
f1585f6e LP |
1310 | static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = { |
1311 | .init = dw_hdmi_phy_init, | |
1312 | .disable = dw_hdmi_phy_disable, | |
1313 | .read_hpd = dw_hdmi_phy_read_hpd, | |
386d3299 NA |
1314 | .update_hpd = dw_hdmi_phy_update_hpd, |
1315 | .setup_hpd = dw_hdmi_phy_setup_hpd, | |
f1585f6e LP |
1316 | }; |
1317 | ||
1318 | /* ----------------------------------------------------------------------------- | |
1319 | * HDMI TX Setup | |
1320 | */ | |
1321 | ||
b21f4b65 | 1322 | static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi) |
9aaf880e | 1323 | { |
812bc615 | 1324 | u8 de; |
9aaf880e FE |
1325 | |
1326 | if (hdmi->hdmi_data.video_mode.mdataenablepolarity) | |
1327 | de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH; | |
1328 | else | |
1329 | de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW; | |
1330 | ||
1331 | /* disable rx detect */ | |
812bc615 RK |
1332 | hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE, |
1333 | HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0); | |
9aaf880e | 1334 | |
812bc615 | 1335 | hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG); |
9aaf880e | 1336 | |
812bc615 RK |
1337 | hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE, |
1338 | HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1); | |
9aaf880e FE |
1339 | } |
1340 | ||
d4ac4cb6 | 1341 | static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode) |
9aaf880e | 1342 | { |
d4ac4cb6 RK |
1343 | struct hdmi_avi_infoframe frame; |
1344 | u8 val; | |
9aaf880e | 1345 | |
d4ac4cb6 | 1346 | /* Initialise info frame from DRM mode */ |
0c1f528c | 1347 | drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false); |
9aaf880e | 1348 | |
def23aa7 | 1349 | if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) |
d4ac4cb6 | 1350 | frame.colorspace = HDMI_COLORSPACE_YUV444; |
def23aa7 | 1351 | else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) |
d4ac4cb6 | 1352 | frame.colorspace = HDMI_COLORSPACE_YUV422; |
9aaf880e | 1353 | else |
d4ac4cb6 | 1354 | frame.colorspace = HDMI_COLORSPACE_RGB; |
9aaf880e FE |
1355 | |
1356 | /* Set up colorimetry */ | |
def23aa7 NA |
1357 | switch (hdmi->hdmi_data.enc_out_encoding) { |
1358 | case V4L2_YCBCR_ENC_601: | |
1359 | if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601) | |
1360 | frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; | |
1361 | else | |
1362 | frame.colorimetry = HDMI_COLORIMETRY_ITU_601; | |
1363 | frame.extended_colorimetry = | |
d4ac4cb6 | 1364 | HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; |
f40d6560 | 1365 | break; |
def23aa7 NA |
1366 | case V4L2_YCBCR_ENC_709: |
1367 | if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709) | |
1368 | frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; | |
1369 | else | |
1370 | frame.colorimetry = HDMI_COLORIMETRY_ITU_709; | |
1371 | frame.extended_colorimetry = | |
d4ac4cb6 | 1372 | HDMI_EXTENDED_COLORIMETRY_XV_YCC_709; |
def23aa7 NA |
1373 | break; |
1374 | default: /* Carries no data */ | |
1375 | frame.colorimetry = HDMI_COLORIMETRY_ITU_601; | |
1376 | frame.extended_colorimetry = | |
1377 | HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; | |
1378 | break; | |
9aaf880e FE |
1379 | } |
1380 | ||
d4ac4cb6 RK |
1381 | frame.scan_mode = HDMI_SCAN_MODE_NONE; |
1382 | ||
1383 | /* | |
1384 | * The Designware IP uses a different byte format from standard | |
1385 | * AVI info frames, though generally the bits are in the correct | |
1386 | * bytes. | |
1387 | */ | |
1388 | ||
1389 | /* | |
b0118e7d JA |
1390 | * AVI data byte 1 differences: Colorspace in bits 0,1 rather than 5,6, |
1391 | * scan info in bits 4,5 rather than 0,1 and active aspect present in | |
1392 | * bit 6 rather than 4. | |
d4ac4cb6 | 1393 | */ |
b0118e7d | 1394 | val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 3); |
d4ac4cb6 RK |
1395 | if (frame.active_aspect & 15) |
1396 | val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT; | |
1397 | if (frame.top_bar || frame.bottom_bar) | |
1398 | val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR; | |
1399 | if (frame.left_bar || frame.right_bar) | |
1400 | val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR; | |
1401 | hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0); | |
1402 | ||
1403 | /* AVI data byte 2 differences: none */ | |
1404 | val = ((frame.colorimetry & 0x3) << 6) | | |
1405 | ((frame.picture_aspect & 0x3) << 4) | | |
1406 | (frame.active_aspect & 0xf); | |
9aaf880e FE |
1407 | hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1); |
1408 | ||
d4ac4cb6 RK |
1409 | /* AVI data byte 3 differences: none */ |
1410 | val = ((frame.extended_colorimetry & 0x7) << 4) | | |
1411 | ((frame.quantization_range & 0x3) << 2) | | |
1412 | (frame.nups & 0x3); | |
1413 | if (frame.itc) | |
1414 | val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID; | |
9aaf880e FE |
1415 | hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2); |
1416 | ||
d4ac4cb6 RK |
1417 | /* AVI data byte 4 differences: none */ |
1418 | val = frame.video_code & 0x7f; | |
1419 | hdmi_writeb(hdmi, val, HDMI_FC_AVIVID); | |
9aaf880e FE |
1420 | |
1421 | /* AVI Data Byte 5- set up input and output pixel repetition */ | |
1422 | val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) << | |
1423 | HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) & | |
1424 | HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) | | |
1425 | ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput << | |
1426 | HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) & | |
1427 | HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK); | |
1428 | hdmi_writeb(hdmi, val, HDMI_FC_PRCONF); | |
1429 | ||
d4ac4cb6 RK |
1430 | /* |
1431 | * AVI data byte 5 differences: content type in 0,1 rather than 4,5, | |
1432 | * ycc range in bits 2,3 rather than 6,7 | |
1433 | */ | |
1434 | val = ((frame.ycc_quantization_range & 0x3) << 2) | | |
1435 | (frame.content_type & 0x3); | |
9aaf880e FE |
1436 | hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3); |
1437 | ||
1438 | /* AVI Data Bytes 6-13 */ | |
d4ac4cb6 RK |
1439 | hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0); |
1440 | hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1); | |
1441 | hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0); | |
1442 | hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1); | |
1443 | hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0); | |
1444 | hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1); | |
1445 | hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0); | |
1446 | hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1); | |
9aaf880e FE |
1447 | } |
1448 | ||
9aa1eca0 NY |
1449 | static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi, |
1450 | struct drm_display_mode *mode) | |
1451 | { | |
1452 | struct hdmi_vendor_infoframe frame; | |
1453 | u8 buffer[10]; | |
1454 | ssize_t err; | |
1455 | ||
f1781e9b VS |
1456 | err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, |
1457 | &hdmi->connector, | |
1458 | mode); | |
9aa1eca0 NY |
1459 | if (err < 0) |
1460 | /* | |
1461 | * Going into that statement does not means vendor infoframe | |
1462 | * fails. It just informed us that vendor infoframe is not | |
1463 | * needed for the selected mode. Only 4k or stereoscopic 3D | |
1464 | * mode requires vendor infoframe. So just simply return. | |
1465 | */ | |
1466 | return; | |
1467 | ||
1468 | err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer)); | |
1469 | if (err < 0) { | |
1470 | dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n", | |
1471 | err); | |
1472 | return; | |
1473 | } | |
1474 | hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, | |
1475 | HDMI_FC_DATAUTO0_VSD_MASK); | |
1476 | ||
1477 | /* Set the length of HDMI vendor specific InfoFrame payload */ | |
1478 | hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE); | |
1479 | ||
1480 | /* Set 24bit IEEE Registration Identifier */ | |
1481 | hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0); | |
1482 | hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1); | |
1483 | hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2); | |
1484 | ||
1485 | /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */ | |
1486 | hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0); | |
1487 | hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1); | |
1488 | ||
1489 | if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) | |
1490 | hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2); | |
1491 | ||
1492 | /* Packet frame interpolation */ | |
1493 | hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1); | |
1494 | ||
1495 | /* Auto packets per frame and line spacing */ | |
1496 | hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2); | |
1497 | ||
1498 | /* Configures the Frame Composer On RDRB mode */ | |
1499 | hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, | |
1500 | HDMI_FC_DATAUTO0_VSD_MASK); | |
1501 | } | |
1502 | ||
b21f4b65 | 1503 | static void hdmi_av_composer(struct dw_hdmi *hdmi, |
9aaf880e FE |
1504 | const struct drm_display_mode *mode) |
1505 | { | |
1506 | u8 inv_val; | |
1507 | struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode; | |
1508 | int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len; | |
e80b9f4e | 1509 | unsigned int vdisplay; |
9aaf880e | 1510 | |
9aaf880e FE |
1511 | vmode->mpixelclock = mode->clock * 1000; |
1512 | ||
1513 | dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock); | |
1514 | ||
1515 | /* Set up HDMI_FC_INVIDCONF */ | |
1516 | inv_val = (hdmi->hdmi_data.hdcp_enable ? | |
1517 | HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE : | |
1518 | HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE); | |
1519 | ||
b91eee8c | 1520 | inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ? |
9aaf880e | 1521 | HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH : |
b91eee8c | 1522 | HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW; |
9aaf880e | 1523 | |
b91eee8c | 1524 | inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ? |
9aaf880e | 1525 | HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH : |
b91eee8c | 1526 | HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW; |
9aaf880e FE |
1527 | |
1528 | inv_val |= (vmode->mdataenablepolarity ? | |
1529 | HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH : | |
1530 | HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW); | |
1531 | ||
1532 | if (hdmi->vic == 39) | |
1533 | inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH; | |
1534 | else | |
b91eee8c | 1535 | inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? |
9aaf880e | 1536 | HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH : |
b91eee8c | 1537 | HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW; |
9aaf880e | 1538 | |
b91eee8c | 1539 | inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? |
9aaf880e | 1540 | HDMI_FC_INVIDCONF_IN_I_P_INTERLACED : |
b91eee8c | 1541 | HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE; |
9aaf880e | 1542 | |
05b1342f RK |
1543 | inv_val |= hdmi->sink_is_hdmi ? |
1544 | HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE : | |
1545 | HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE; | |
9aaf880e FE |
1546 | |
1547 | hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF); | |
1548 | ||
e80b9f4e RK |
1549 | vdisplay = mode->vdisplay; |
1550 | vblank = mode->vtotal - mode->vdisplay; | |
1551 | v_de_vs = mode->vsync_start - mode->vdisplay; | |
1552 | vsync_len = mode->vsync_end - mode->vsync_start; | |
1553 | ||
1554 | /* | |
1555 | * When we're setting an interlaced mode, we need | |
1556 | * to adjust the vertical timing to suit. | |
1557 | */ | |
1558 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { | |
1559 | vdisplay /= 2; | |
1560 | vblank /= 2; | |
1561 | v_de_vs /= 2; | |
1562 | vsync_len /= 2; | |
1563 | } | |
1564 | ||
9aaf880e FE |
1565 | /* Set up horizontal active pixel width */ |
1566 | hdmi_writeb(hdmi, mode->hdisplay >> 8, HDMI_FC_INHACTV1); | |
1567 | hdmi_writeb(hdmi, mode->hdisplay, HDMI_FC_INHACTV0); | |
1568 | ||
1569 | /* Set up vertical active lines */ | |
e80b9f4e RK |
1570 | hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1); |
1571 | hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0); | |
9aaf880e FE |
1572 | |
1573 | /* Set up horizontal blanking pixel region width */ | |
1574 | hblank = mode->htotal - mode->hdisplay; | |
1575 | hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1); | |
1576 | hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0); | |
1577 | ||
1578 | /* Set up vertical blanking pixel region width */ | |
9aaf880e FE |
1579 | hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK); |
1580 | ||
1581 | /* Set up HSYNC active edge delay width (in pixel clks) */ | |
1582 | h_de_hs = mode->hsync_start - mode->hdisplay; | |
1583 | hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1); | |
1584 | hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0); | |
1585 | ||
1586 | /* Set up VSYNC active edge delay (in lines) */ | |
9aaf880e FE |
1587 | hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY); |
1588 | ||
1589 | /* Set up HSYNC active pulse width (in pixel clks) */ | |
1590 | hsync_len = mode->hsync_end - mode->hsync_start; | |
1591 | hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1); | |
1592 | hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0); | |
1593 | ||
1594 | /* Set up VSYNC active edge delay (in lines) */ | |
9aaf880e FE |
1595 | hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH); |
1596 | } | |
1597 | ||
9aaf880e | 1598 | /* HDMI Initialization Step B.4 */ |
b21f4b65 | 1599 | static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi) |
9aaf880e | 1600 | { |
9aaf880e FE |
1601 | /* control period minimum duration */ |
1602 | hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR); | |
1603 | hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR); | |
1604 | hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC); | |
1605 | ||
1606 | /* Set to fill TMDS data channels */ | |
1607 | hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM); | |
1608 | hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM); | |
1609 | hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM); | |
1610 | ||
1611 | /* Enable pixel clock and tmds data path */ | |
7cc4ab22 RK |
1612 | hdmi->mc_clkdis |= HDMI_MC_CLKDIS_HDCPCLK_DISABLE | |
1613 | HDMI_MC_CLKDIS_CSCCLK_DISABLE | | |
1614 | HDMI_MC_CLKDIS_AUDCLK_DISABLE | | |
1615 | HDMI_MC_CLKDIS_PREPCLK_DISABLE | | |
1616 | HDMI_MC_CLKDIS_TMDSCLK_DISABLE; | |
1617 | hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE; | |
1618 | hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); | |
9aaf880e | 1619 | |
7cc4ab22 RK |
1620 | hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE; |
1621 | hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); | |
9aaf880e FE |
1622 | |
1623 | /* Enable csc path */ | |
1624 | if (is_color_space_conversion(hdmi)) { | |
7cc4ab22 RK |
1625 | hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE; |
1626 | hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); | |
9aaf880e | 1627 | } |
8b9e1c0d | 1628 | |
14247d7c NA |
1629 | /* Enable color space conversion if needed */ |
1630 | if (is_color_space_conversion(hdmi)) | |
8b9e1c0d LP |
1631 | hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH, |
1632 | HDMI_MC_FLOWCTRL); | |
1633 | else | |
1634 | hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS, | |
1635 | HDMI_MC_FLOWCTRL); | |
9aaf880e FE |
1636 | } |
1637 | ||
9aaf880e | 1638 | /* Workaround to clear the overflow condition */ |
b21f4b65 | 1639 | static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi) |
9aaf880e | 1640 | { |
be41fc55 LP |
1641 | unsigned int count; |
1642 | unsigned int i; | |
9aaf880e FE |
1643 | u8 val; |
1644 | ||
be41fc55 LP |
1645 | /* |
1646 | * Under some circumstances the Frame Composer arithmetic unit can miss | |
1647 | * an FC register write due to being busy processing the previous one. | |
1648 | * The issue can be worked around by issuing a TMDS software reset and | |
1649 | * then write one of the FC registers several times. | |
1650 | * | |
1651 | * The number of iterations matters and depends on the HDMI TX revision | |
46d1b42b JS |
1652 | * (and possibly on the platform). So far i.MX6Q (v1.30a), i.MX6DL |
1653 | * (v1.31a) and multiple Allwinner SoCs (v1.32a) have been identified | |
1654 | * as needing the workaround, with 4 iterations for v1.30a and 1 | |
1655 | * iteration for others. | |
9c305eb4 NA |
1656 | * The Amlogic Meson GX SoCs (v2.01a) have been identified as needing |
1657 | * the workaround with a single iteration. | |
be41fc55 | 1658 | */ |
9aaf880e | 1659 | |
be41fc55 LP |
1660 | switch (hdmi->version) { |
1661 | case 0x130a: | |
1662 | count = 4; | |
1663 | break; | |
1664 | case 0x131a: | |
46d1b42b | 1665 | case 0x132a: |
9c305eb4 | 1666 | case 0x201a: |
c8c78ac2 | 1667 | case 0x212a: |
be41fc55 LP |
1668 | count = 1; |
1669 | break; | |
1670 | default: | |
9aaf880e FE |
1671 | return; |
1672 | } | |
1673 | ||
be41fc55 LP |
1674 | /* TMDS software reset */ |
1675 | hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ); | |
1676 | ||
1677 | val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF); | |
1678 | for (i = 0; i < count; i++) | |
9aaf880e FE |
1679 | hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF); |
1680 | } | |
1681 | ||
b21f4b65 | 1682 | static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi) |
9aaf880e FE |
1683 | { |
1684 | hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK, | |
1685 | HDMI_IH_MUTE_FC_STAT2); | |
1686 | } | |
1687 | ||
b21f4b65 | 1688 | static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode) |
9aaf880e FE |
1689 | { |
1690 | int ret; | |
1691 | ||
1692 | hdmi_disable_overflow_interrupts(hdmi); | |
1693 | ||
1694 | hdmi->vic = drm_match_cea_mode(mode); | |
1695 | ||
1696 | if (!hdmi->vic) { | |
1697 | dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n"); | |
9aaf880e FE |
1698 | } else { |
1699 | dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic); | |
9aaf880e FE |
1700 | } |
1701 | ||
1702 | if ((hdmi->vic == 6) || (hdmi->vic == 7) || | |
b5878339 AY |
1703 | (hdmi->vic == 21) || (hdmi->vic == 22) || |
1704 | (hdmi->vic == 2) || (hdmi->vic == 3) || | |
1705 | (hdmi->vic == 17) || (hdmi->vic == 18)) | |
def23aa7 | 1706 | hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601; |
9aaf880e | 1707 | else |
def23aa7 | 1708 | hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709; |
9aaf880e | 1709 | |
d10ca826 | 1710 | hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0; |
9aaf880e FE |
1711 | hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0; |
1712 | ||
def23aa7 | 1713 | /* TOFIX: Get input format from plat data or fallback to RGB888 */ |
e20c29aa | 1714 | if (hdmi->plat_data->input_bus_format) |
def23aa7 NA |
1715 | hdmi->hdmi_data.enc_in_bus_format = |
1716 | hdmi->plat_data->input_bus_format; | |
1717 | else | |
1718 | hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_RGB888_1X24; | |
1719 | ||
1720 | /* TOFIX: Get input encoding from plat data or fallback to none */ | |
e20c29aa | 1721 | if (hdmi->plat_data->input_bus_encoding) |
def23aa7 NA |
1722 | hdmi->hdmi_data.enc_in_encoding = |
1723 | hdmi->plat_data->input_bus_encoding; | |
1724 | else | |
1725 | hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT; | |
9aaf880e | 1726 | |
def23aa7 NA |
1727 | /* TOFIX: Default to RGB888 output format */ |
1728 | hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24; | |
9aaf880e | 1729 | |
9aaf880e FE |
1730 | hdmi->hdmi_data.pix_repet_factor = 0; |
1731 | hdmi->hdmi_data.hdcp_enable = 0; | |
1732 | hdmi->hdmi_data.video_mode.mdataenablepolarity = true; | |
1733 | ||
1734 | /* HDMI Initialization Step B.1 */ | |
1735 | hdmi_av_composer(hdmi, mode); | |
1736 | ||
1737 | /* HDMI Initializateion Step B.2 */ | |
f1585f6e | 1738 | ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data, &hdmi->previous_mode); |
9aaf880e FE |
1739 | if (ret) |
1740 | return ret; | |
f1585f6e | 1741 | hdmi->phy.enabled = true; |
9aaf880e FE |
1742 | |
1743 | /* HDMI Initialization Step B.3 */ | |
b21f4b65 | 1744 | dw_hdmi_enable_video_path(hdmi); |
9aaf880e | 1745 | |
f709ec07 RK |
1746 | if (hdmi->sink_has_audio) { |
1747 | dev_dbg(hdmi->dev, "sink has audio support\n"); | |
9aaf880e FE |
1748 | |
1749 | /* HDMI Initialization Step E - Configure audio */ | |
1750 | hdmi_clk_regenerator_update_pixel_clock(hdmi); | |
57fbc055 | 1751 | hdmi_enable_audio_clk(hdmi, true); |
f709ec07 RK |
1752 | } |
1753 | ||
1754 | /* not for DVI mode */ | |
1755 | if (hdmi->sink_is_hdmi) { | |
1756 | dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__); | |
9aaf880e FE |
1757 | |
1758 | /* HDMI Initialization Step F - Configure AVI InfoFrame */ | |
d4ac4cb6 | 1759 | hdmi_config_AVI(hdmi, mode); |
9aa1eca0 | 1760 | hdmi_config_vendor_specific_infoframe(hdmi, mode); |
05b1342f RK |
1761 | } else { |
1762 | dev_dbg(hdmi->dev, "%s DVI mode\n", __func__); | |
9aaf880e FE |
1763 | } |
1764 | ||
1765 | hdmi_video_packetize(hdmi); | |
1766 | hdmi_video_csc(hdmi); | |
1767 | hdmi_video_sample(hdmi); | |
1768 | hdmi_tx_hdcp_config(hdmi); | |
1769 | ||
b21f4b65 | 1770 | dw_hdmi_clear_overflow(hdmi); |
9aaf880e FE |
1771 | |
1772 | return 0; | |
1773 | } | |
1774 | ||
a23d6265 | 1775 | static void dw_hdmi_setup_i2c(struct dw_hdmi *hdmi) |
9aaf880e FE |
1776 | { |
1777 | hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL, | |
1778 | HDMI_PHY_I2CM_INT_ADDR); | |
1779 | ||
1780 | hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL | | |
1781 | HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL, | |
1782 | HDMI_PHY_I2CM_CTLINT_ADDR); | |
9aaf880e FE |
1783 | } |
1784 | ||
b21f4b65 | 1785 | static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi) |
9aaf880e FE |
1786 | { |
1787 | u8 ih_mute; | |
1788 | ||
1789 | /* | |
1790 | * Boot up defaults are: | |
1791 | * HDMI_IH_MUTE = 0x03 (disabled) | |
1792 | * HDMI_IH_MUTE_* = 0x00 (enabled) | |
1793 | * | |
1794 | * Disable top level interrupt bits in HDMI block | |
1795 | */ | |
1796 | ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) | | |
1797 | HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT | | |
1798 | HDMI_IH_MUTE_MUTE_ALL_INTERRUPT; | |
1799 | ||
1800 | hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE); | |
1801 | ||
1802 | /* by default mask all interrupts */ | |
1803 | hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK); | |
1804 | hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0); | |
1805 | hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1); | |
1806 | hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2); | |
1807 | hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0); | |
1808 | hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR); | |
1809 | hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR); | |
1810 | hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT); | |
1811 | hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT); | |
1812 | hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK); | |
1813 | hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK); | |
1814 | hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK); | |
9aaf880e FE |
1815 | hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT); |
1816 | hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT); | |
1817 | ||
1818 | /* Disable interrupts in the IH_MUTE_* registers */ | |
1819 | hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0); | |
1820 | hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1); | |
1821 | hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2); | |
1822 | hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0); | |
1823 | hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0); | |
1824 | hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0); | |
1825 | hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0); | |
1826 | hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0); | |
1827 | hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0); | |
1828 | hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0); | |
1829 | ||
1830 | /* Enable top level interrupt bits in HDMI block */ | |
1831 | ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT | | |
1832 | HDMI_IH_MUTE_MUTE_ALL_INTERRUPT); | |
1833 | hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE); | |
1834 | } | |
1835 | ||
b21f4b65 | 1836 | static void dw_hdmi_poweron(struct dw_hdmi *hdmi) |
9aaf880e | 1837 | { |
381f05a7 | 1838 | hdmi->bridge_is_on = true; |
b21f4b65 | 1839 | dw_hdmi_setup(hdmi, &hdmi->previous_mode); |
9aaf880e FE |
1840 | } |
1841 | ||
b21f4b65 | 1842 | static void dw_hdmi_poweroff(struct dw_hdmi *hdmi) |
9aaf880e | 1843 | { |
f1585f6e LP |
1844 | if (hdmi->phy.enabled) { |
1845 | hdmi->phy.ops->disable(hdmi, hdmi->phy.data); | |
1846 | hdmi->phy.enabled = false; | |
1847 | } | |
1848 | ||
381f05a7 RK |
1849 | hdmi->bridge_is_on = false; |
1850 | } | |
1851 | ||
1852 | static void dw_hdmi_update_power(struct dw_hdmi *hdmi) | |
1853 | { | |
1854 | int force = hdmi->force; | |
1855 | ||
1856 | if (hdmi->disabled) { | |
1857 | force = DRM_FORCE_OFF; | |
1858 | } else if (force == DRM_FORCE_UNSPECIFIED) { | |
aeac23bd | 1859 | if (hdmi->rxsense) |
381f05a7 RK |
1860 | force = DRM_FORCE_ON; |
1861 | else | |
1862 | force = DRM_FORCE_OFF; | |
1863 | } | |
1864 | ||
1865 | if (force == DRM_FORCE_OFF) { | |
1866 | if (hdmi->bridge_is_on) | |
1867 | dw_hdmi_poweroff(hdmi); | |
1868 | } else { | |
1869 | if (!hdmi->bridge_is_on) | |
1870 | dw_hdmi_poweron(hdmi); | |
1871 | } | |
9aaf880e FE |
1872 | } |
1873 | ||
aeac23bd RK |
1874 | /* |
1875 | * Adjust the detection of RXSENSE according to whether we have a forced | |
1876 | * connection mode enabled, or whether we have been disabled. There is | |
1877 | * no point processing RXSENSE interrupts if we have a forced connection | |
1878 | * state, or DRM has us disabled. | |
1879 | * | |
1880 | * We also disable rxsense interrupts when we think we're disconnected | |
1881 | * to avoid floating TDMS signals giving false rxsense interrupts. | |
1882 | * | |
1883 | * Note: we still need to listen for HPD interrupts even when DRM has us | |
1884 | * disabled so that we can detect a connect event. | |
1885 | */ | |
1886 | static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi) | |
1887 | { | |
386d3299 NA |
1888 | if (hdmi->phy.ops->update_hpd) |
1889 | hdmi->phy.ops->update_hpd(hdmi, hdmi->phy.data, | |
1890 | hdmi->force, hdmi->disabled, | |
1891 | hdmi->rxsense); | |
a23d6265 LP |
1892 | } |
1893 | ||
b21f4b65 AY |
1894 | static enum drm_connector_status |
1895 | dw_hdmi_connector_detect(struct drm_connector *connector, bool force) | |
9aaf880e | 1896 | { |
b21f4b65 | 1897 | struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, |
d94905e0 | 1898 | connector); |
98dbeada | 1899 | |
381f05a7 RK |
1900 | mutex_lock(&hdmi->mutex); |
1901 | hdmi->force = DRM_FORCE_UNSPECIFIED; | |
1902 | dw_hdmi_update_power(hdmi); | |
aeac23bd | 1903 | dw_hdmi_update_phy_mask(hdmi); |
381f05a7 RK |
1904 | mutex_unlock(&hdmi->mutex); |
1905 | ||
f1585f6e | 1906 | return hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data); |
9aaf880e FE |
1907 | } |
1908 | ||
b21f4b65 | 1909 | static int dw_hdmi_connector_get_modes(struct drm_connector *connector) |
9aaf880e | 1910 | { |
b21f4b65 | 1911 | struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, |
9aaf880e FE |
1912 | connector); |
1913 | struct edid *edid; | |
6c7e66e6 | 1914 | int ret = 0; |
9aaf880e FE |
1915 | |
1916 | if (!hdmi->ddc) | |
1917 | return 0; | |
1918 | ||
1919 | edid = drm_get_edid(connector, hdmi->ddc); | |
1920 | if (edid) { | |
1921 | dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n", | |
1922 | edid->width_cm, edid->height_cm); | |
1923 | ||
05b1342f | 1924 | hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid); |
f709ec07 | 1925 | hdmi->sink_has_audio = drm_detect_monitor_audio(edid); |
c555f023 | 1926 | drm_connector_update_edid_property(connector, edid); |
e84b8d75 | 1927 | cec_notifier_set_phys_addr_from_edid(hdmi->cec_notifier, edid); |
9aaf880e FE |
1928 | ret = drm_add_edid_modes(connector, edid); |
1929 | kfree(edid); | |
1930 | } else { | |
1931 | dev_dbg(hdmi->dev, "failed to get edid\n"); | |
1932 | } | |
1933 | ||
6c7e66e6 | 1934 | return ret; |
9aaf880e FE |
1935 | } |
1936 | ||
381f05a7 RK |
1937 | static void dw_hdmi_connector_force(struct drm_connector *connector) |
1938 | { | |
1939 | struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, | |
1940 | connector); | |
1941 | ||
1942 | mutex_lock(&hdmi->mutex); | |
1943 | hdmi->force = connector->force; | |
1944 | dw_hdmi_update_power(hdmi); | |
aeac23bd | 1945 | dw_hdmi_update_phy_mask(hdmi); |
381f05a7 RK |
1946 | mutex_unlock(&hdmi->mutex); |
1947 | } | |
1948 | ||
dae91e4d | 1949 | static const struct drm_connector_funcs dw_hdmi_connector_funcs = { |
2c5b2ccc MY |
1950 | .fill_modes = drm_helper_probe_single_connector_modes, |
1951 | .detect = dw_hdmi_connector_detect, | |
fdd8326a | 1952 | .destroy = drm_connector_cleanup, |
2c5b2ccc MY |
1953 | .force = dw_hdmi_connector_force, |
1954 | .reset = drm_atomic_helper_connector_reset, | |
1955 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, | |
1956 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, | |
1957 | }; | |
1958 | ||
dae91e4d | 1959 | static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = { |
b21f4b65 | 1960 | .get_modes = dw_hdmi_connector_get_modes, |
9aaf880e FE |
1961 | }; |
1962 | ||
d2ae94ae LP |
1963 | static int dw_hdmi_bridge_attach(struct drm_bridge *bridge) |
1964 | { | |
1965 | struct dw_hdmi *hdmi = bridge->driver_private; | |
1966 | struct drm_encoder *encoder = bridge->encoder; | |
1967 | struct drm_connector *connector = &hdmi->connector; | |
1968 | ||
1969 | connector->interlace_allowed = 1; | |
1970 | connector->polled = DRM_CONNECTOR_POLL_HPD; | |
1971 | ||
1972 | drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs); | |
1973 | ||
1974 | drm_connector_init(bridge->dev, connector, &dw_hdmi_connector_funcs, | |
1975 | DRM_MODE_CONNECTOR_HDMIA); | |
1976 | ||
cde4c44d | 1977 | drm_connector_attach_encoder(connector, encoder); |
d2ae94ae LP |
1978 | |
1979 | return 0; | |
1980 | } | |
1981 | ||
b0febde7 JA |
1982 | static enum drm_mode_status |
1983 | dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge, | |
1984 | const struct drm_display_mode *mode) | |
6ce2ca58 RP |
1985 | { |
1986 | struct dw_hdmi *hdmi = bridge->driver_private; | |
1987 | struct drm_connector *connector = &hdmi->connector; | |
b0febde7 | 1988 | enum drm_mode_status mode_status = MODE_OK; |
6ce2ca58 | 1989 | |
b0febde7 JA |
1990 | /* We don't support double-clocked modes */ |
1991 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) | |
1992 | return MODE_BAD; | |
1993 | ||
1994 | if (hdmi->plat_data->mode_valid) | |
1995 | mode_status = hdmi->plat_data->mode_valid(connector, mode); | |
1996 | ||
1997 | return mode_status; | |
6ce2ca58 RP |
1998 | } |
1999 | ||
fd30b38c LP |
2000 | static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge, |
2001 | struct drm_display_mode *orig_mode, | |
2002 | struct drm_display_mode *mode) | |
2003 | { | |
2004 | struct dw_hdmi *hdmi = bridge->driver_private; | |
2005 | ||
2006 | mutex_lock(&hdmi->mutex); | |
2007 | ||
2008 | /* Store the display mode for plugin/DKMS poweron events */ | |
2009 | memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode)); | |
2010 | ||
2011 | mutex_unlock(&hdmi->mutex); | |
2012 | } | |
2013 | ||
2014 | static void dw_hdmi_bridge_disable(struct drm_bridge *bridge) | |
2015 | { | |
2016 | struct dw_hdmi *hdmi = bridge->driver_private; | |
2017 | ||
2018 | mutex_lock(&hdmi->mutex); | |
2019 | hdmi->disabled = true; | |
2020 | dw_hdmi_update_power(hdmi); | |
2021 | dw_hdmi_update_phy_mask(hdmi); | |
2022 | mutex_unlock(&hdmi->mutex); | |
2023 | } | |
2024 | ||
2025 | static void dw_hdmi_bridge_enable(struct drm_bridge *bridge) | |
2026 | { | |
2027 | struct dw_hdmi *hdmi = bridge->driver_private; | |
2028 | ||
2029 | mutex_lock(&hdmi->mutex); | |
2030 | hdmi->disabled = false; | |
2031 | dw_hdmi_update_power(hdmi); | |
2032 | dw_hdmi_update_phy_mask(hdmi); | |
2033 | mutex_unlock(&hdmi->mutex); | |
2034 | } | |
2035 | ||
dae91e4d | 2036 | static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = { |
d2ae94ae | 2037 | .attach = dw_hdmi_bridge_attach, |
b21f4b65 AY |
2038 | .enable = dw_hdmi_bridge_enable, |
2039 | .disable = dw_hdmi_bridge_disable, | |
b21f4b65 | 2040 | .mode_set = dw_hdmi_bridge_mode_set, |
b0febde7 | 2041 | .mode_valid = dw_hdmi_bridge_mode_valid, |
3d1b35a3 AY |
2042 | }; |
2043 | ||
3efc2fa3 VZ |
2044 | static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi) |
2045 | { | |
2046 | struct dw_hdmi_i2c *i2c = hdmi->i2c; | |
2047 | unsigned int stat; | |
2048 | ||
2049 | stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0); | |
2050 | if (!stat) | |
2051 | return IRQ_NONE; | |
2052 | ||
2053 | hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0); | |
2054 | ||
2055 | i2c->stat = stat; | |
2056 | ||
2057 | complete(&i2c->cmp); | |
2058 | ||
2059 | return IRQ_HANDLED; | |
2060 | } | |
2061 | ||
b21f4b65 | 2062 | static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id) |
d94905e0 | 2063 | { |
b21f4b65 | 2064 | struct dw_hdmi *hdmi = dev_id; |
d94905e0 | 2065 | u8 intr_stat; |
3efc2fa3 VZ |
2066 | irqreturn_t ret = IRQ_NONE; |
2067 | ||
2068 | if (hdmi->i2c) | |
2069 | ret = dw_hdmi_i2c_irq(hdmi); | |
d94905e0 RK |
2070 | |
2071 | intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0); | |
3efc2fa3 | 2072 | if (intr_stat) { |
d94905e0 | 2073 | hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0); |
3efc2fa3 VZ |
2074 | return IRQ_WAKE_THREAD; |
2075 | } | |
d94905e0 | 2076 | |
3efc2fa3 | 2077 | return ret; |
d94905e0 RK |
2078 | } |
2079 | ||
c32048d9 | 2080 | void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense) |
386d3299 NA |
2081 | { |
2082 | mutex_lock(&hdmi->mutex); | |
2083 | ||
2084 | if (!hdmi->force) { | |
2085 | /* | |
2086 | * If the RX sense status indicates we're disconnected, | |
2087 | * clear the software rxsense status. | |
2088 | */ | |
2089 | if (!rx_sense) | |
2090 | hdmi->rxsense = false; | |
2091 | ||
2092 | /* | |
2093 | * Only set the software rxsense status when both | |
2094 | * rxsense and hpd indicates we're connected. | |
2095 | * This avoids what seems to be bad behaviour in | |
2096 | * at least iMX6S versions of the phy. | |
2097 | */ | |
2098 | if (hpd) | |
2099 | hdmi->rxsense = true; | |
2100 | ||
2101 | dw_hdmi_update_power(hdmi); | |
2102 | dw_hdmi_update_phy_mask(hdmi); | |
2103 | } | |
2104 | mutex_unlock(&hdmi->mutex); | |
2105 | } | |
386d3299 NA |
2106 | EXPORT_SYMBOL_GPL(dw_hdmi_setup_rx_sense); |
2107 | ||
b21f4b65 | 2108 | static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) |
9aaf880e | 2109 | { |
b21f4b65 | 2110 | struct dw_hdmi *hdmi = dev_id; |
aeac23bd | 2111 | u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat; |
9aaf880e FE |
2112 | |
2113 | intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0); | |
9aaf880e | 2114 | phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0); |
aeac23bd RK |
2115 | phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0); |
2116 | ||
2117 | phy_pol_mask = 0; | |
2118 | if (intr_stat & HDMI_IH_PHY_STAT0_HPD) | |
2119 | phy_pol_mask |= HDMI_PHY_HPD; | |
2120 | if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0) | |
2121 | phy_pol_mask |= HDMI_PHY_RX_SENSE0; | |
2122 | if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1) | |
2123 | phy_pol_mask |= HDMI_PHY_RX_SENSE1; | |
2124 | if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2) | |
2125 | phy_pol_mask |= HDMI_PHY_RX_SENSE2; | |
2126 | if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3) | |
2127 | phy_pol_mask |= HDMI_PHY_RX_SENSE3; | |
2128 | ||
2129 | if (phy_pol_mask) | |
2130 | hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0); | |
9aaf880e | 2131 | |
aeac23bd RK |
2132 | /* |
2133 | * RX sense tells us whether the TDMS transmitters are detecting | |
2134 | * load - in other words, there's something listening on the | |
2135 | * other end of the link. Use this to decide whether we should | |
2136 | * power on the phy as HPD may be toggled by the sink to merely | |
2137 | * ask the source to re-read the EDID. | |
2138 | */ | |
2139 | if (intr_stat & | |
e84b8d75 | 2140 | (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) { |
c32048d9 NA |
2141 | dw_hdmi_setup_rx_sense(hdmi, |
2142 | phy_stat & HDMI_PHY_HPD, | |
2143 | phy_stat & HDMI_PHY_RX_SENSE); | |
aeac23bd | 2144 | |
e84b8d75 RK |
2145 | if ((phy_stat & (HDMI_PHY_RX_SENSE | HDMI_PHY_HPD)) == 0) |
2146 | cec_notifier_set_phys_addr(hdmi->cec_notifier, | |
2147 | CEC_PHYS_ADDR_INVALID); | |
2148 | } | |
2149 | ||
aeac23bd RK |
2150 | if (intr_stat & HDMI_IH_PHY_STAT0_HPD) { |
2151 | dev_dbg(hdmi->dev, "EVENT=%s\n", | |
2152 | phy_int_pol & HDMI_PHY_HPD ? "plugin" : "plugout"); | |
ba5d7e61 LP |
2153 | if (hdmi->bridge.dev) |
2154 | drm_helper_hpd_irq_event(hdmi->bridge.dev); | |
9aaf880e FE |
2155 | } |
2156 | ||
2157 | hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0); | |
aeac23bd RK |
2158 | hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE), |
2159 | HDMI_IH_MUTE_PHY_STAT0); | |
9aaf880e FE |
2160 | |
2161 | return IRQ_HANDLED; | |
2162 | } | |
2163 | ||
faba6c3c LP |
2164 | static const struct dw_hdmi_phy_data dw_hdmi_phys[] = { |
2165 | { | |
2166 | .type = DW_HDMI_PHY_DWC_HDMI_TX_PHY, | |
2167 | .name = "DWC HDMI TX PHY", | |
b0e583e5 | 2168 | .gen = 1, |
faba6c3c LP |
2169 | }, { |
2170 | .type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC, | |
2171 | .name = "DWC MHL PHY + HEAC PHY", | |
b0e583e5 | 2172 | .gen = 2, |
faba6c3c | 2173 | .has_svsret = true, |
2ef9dfed | 2174 | .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, |
faba6c3c LP |
2175 | }, { |
2176 | .type = DW_HDMI_PHY_DWC_MHL_PHY, | |
2177 | .name = "DWC MHL PHY", | |
b0e583e5 | 2178 | .gen = 2, |
faba6c3c | 2179 | .has_svsret = true, |
2ef9dfed | 2180 | .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, |
faba6c3c LP |
2181 | }, { |
2182 | .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC, | |
2183 | .name = "DWC HDMI 3D TX PHY + HEAC PHY", | |
b0e583e5 | 2184 | .gen = 2, |
2ef9dfed | 2185 | .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, |
faba6c3c LP |
2186 | }, { |
2187 | .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY, | |
2188 | .name = "DWC HDMI 3D TX PHY", | |
b0e583e5 | 2189 | .gen = 2, |
2ef9dfed | 2190 | .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, |
faba6c3c LP |
2191 | }, { |
2192 | .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY, | |
2193 | .name = "DWC HDMI 2.0 TX PHY", | |
b0e583e5 | 2194 | .gen = 2, |
faba6c3c | 2195 | .has_svsret = true, |
c93f6092 | 2196 | .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, |
2ef9dfed KB |
2197 | }, { |
2198 | .type = DW_HDMI_PHY_VENDOR_PHY, | |
2199 | .name = "Vendor PHY", | |
faba6c3c LP |
2200 | } |
2201 | }; | |
2202 | ||
2203 | static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi) | |
2204 | { | |
2205 | unsigned int i; | |
2206 | u8 phy_type; | |
2207 | ||
8faff374 HS |
2208 | phy_type = hdmi->plat_data->phy_force_vendor ? |
2209 | DW_HDMI_PHY_VENDOR_PHY : | |
2210 | hdmi_readb(hdmi, HDMI_CONFIG2_ID); | |
faba6c3c | 2211 | |
f1585f6e LP |
2212 | if (phy_type == DW_HDMI_PHY_VENDOR_PHY) { |
2213 | /* Vendor PHYs require support from the glue layer. */ | |
2214 | if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) { | |
2215 | dev_err(hdmi->dev, | |
2216 | "Vendor HDMI PHY not supported by glue layer\n"); | |
2217 | return -ENODEV; | |
2218 | } | |
2219 | ||
2220 | hdmi->phy.ops = hdmi->plat_data->phy_ops; | |
2221 | hdmi->phy.data = hdmi->plat_data->phy_data; | |
2222 | hdmi->phy.name = hdmi->plat_data->phy_name; | |
2223 | return 0; | |
2224 | } | |
2225 | ||
2226 | /* Synopsys PHYs are handled internally. */ | |
faba6c3c LP |
2227 | for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) { |
2228 | if (dw_hdmi_phys[i].type == phy_type) { | |
f1585f6e LP |
2229 | hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops; |
2230 | hdmi->phy.name = dw_hdmi_phys[i].name; | |
2231 | hdmi->phy.data = (void *)&dw_hdmi_phys[i]; | |
2ef9dfed KB |
2232 | |
2233 | if (!dw_hdmi_phys[i].configure && | |
2234 | !hdmi->plat_data->configure_phy) { | |
2235 | dev_err(hdmi->dev, "%s requires platform support\n", | |
2236 | hdmi->phy.name); | |
2237 | return -ENODEV; | |
2238 | } | |
2239 | ||
faba6c3c LP |
2240 | return 0; |
2241 | } | |
2242 | } | |
2243 | ||
f1585f6e | 2244 | dev_err(hdmi->dev, "Unsupported HDMI PHY type (%02x)\n", phy_type); |
faba6c3c LP |
2245 | return -ENODEV; |
2246 | } | |
2247 | ||
a616e63c RK |
2248 | static void dw_hdmi_cec_enable(struct dw_hdmi *hdmi) |
2249 | { | |
2250 | mutex_lock(&hdmi->mutex); | |
2251 | hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CECCLK_DISABLE; | |
2252 | hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); | |
2253 | mutex_unlock(&hdmi->mutex); | |
2254 | } | |
2255 | ||
2256 | static void dw_hdmi_cec_disable(struct dw_hdmi *hdmi) | |
2257 | { | |
2258 | mutex_lock(&hdmi->mutex); | |
2259 | hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CECCLK_DISABLE; | |
2260 | hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); | |
2261 | mutex_unlock(&hdmi->mutex); | |
2262 | } | |
2263 | ||
2264 | static const struct dw_hdmi_cec_ops dw_hdmi_cec_ops = { | |
2265 | .write = hdmi_writeb, | |
2266 | .read = hdmi_readb, | |
2267 | .enable = dw_hdmi_cec_enable, | |
2268 | .disable = dw_hdmi_cec_disable, | |
2269 | }; | |
2270 | ||
80e2f979 NA |
2271 | static const struct regmap_config hdmi_regmap_8bit_config = { |
2272 | .reg_bits = 32, | |
2273 | .val_bits = 8, | |
2274 | .reg_stride = 1, | |
2275 | .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR, | |
2276 | }; | |
2277 | ||
2278 | static const struct regmap_config hdmi_regmap_32bit_config = { | |
2279 | .reg_bits = 32, | |
2280 | .val_bits = 32, | |
2281 | .reg_stride = 4, | |
2282 | .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR << 2, | |
2283 | }; | |
2284 | ||
69497eb9 LP |
2285 | static struct dw_hdmi * |
2286 | __dw_hdmi_probe(struct platform_device *pdev, | |
2287 | const struct dw_hdmi_plat_data *plat_data) | |
9aaf880e | 2288 | { |
c608119d | 2289 | struct device *dev = &pdev->dev; |
17b5001b | 2290 | struct device_node *np = dev->of_node; |
7ed6c665 | 2291 | struct platform_device_info pdevinfo; |
9aaf880e | 2292 | struct device_node *ddc_node; |
a616e63c | 2293 | struct dw_hdmi_cec_data cec; |
b21f4b65 | 2294 | struct dw_hdmi *hdmi; |
80e2f979 | 2295 | struct resource *iores = NULL; |
c608119d | 2296 | int irq; |
3d1b35a3 | 2297 | int ret; |
0cd9d142 | 2298 | u32 val = 1; |
0527e12e LP |
2299 | u8 prod_id0; |
2300 | u8 prod_id1; | |
2761ba6c | 2301 | u8 config0; |
0c674948 | 2302 | u8 config3; |
9aaf880e | 2303 | |
17b5001b | 2304 | hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); |
9aaf880e | 2305 | if (!hdmi) |
69497eb9 | 2306 | return ERR_PTR(-ENOMEM); |
9aaf880e | 2307 | |
3d1b35a3 | 2308 | hdmi->plat_data = plat_data; |
17b5001b | 2309 | hdmi->dev = dev; |
40678388 | 2310 | hdmi->sample_rate = 48000; |
b872a8e1 | 2311 | hdmi->disabled = true; |
aeac23bd RK |
2312 | hdmi->rxsense = true; |
2313 | hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE); | |
7cc4ab22 | 2314 | hdmi->mc_clkdis = 0x7f; |
9aaf880e | 2315 | |
b872a8e1 | 2316 | mutex_init(&hdmi->mutex); |
6bcf4953 | 2317 | mutex_init(&hdmi->audio_mutex); |
b90120a9 | 2318 | spin_lock_init(&hdmi->audio_lock); |
6bcf4953 | 2319 | |
b5d45901 | 2320 | ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0); |
9aaf880e | 2321 | if (ddc_node) { |
9f04a1f2 | 2322 | hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node); |
c2c38488 AY |
2323 | of_node_put(ddc_node); |
2324 | if (!hdmi->ddc) { | |
9aaf880e | 2325 | dev_dbg(hdmi->dev, "failed to read ddc node\n"); |
69497eb9 | 2326 | return ERR_PTR(-EPROBE_DEFER); |
c2c38488 | 2327 | } |
9aaf880e | 2328 | |
9aaf880e FE |
2329 | } else { |
2330 | dev_dbg(hdmi->dev, "no ddc property found\n"); | |
2331 | } | |
2332 | ||
80e2f979 NA |
2333 | if (!plat_data->regm) { |
2334 | const struct regmap_config *reg_config; | |
2335 | ||
2336 | of_property_read_u32(np, "reg-io-width", &val); | |
2337 | switch (val) { | |
2338 | case 4: | |
2339 | reg_config = &hdmi_regmap_32bit_config; | |
2340 | hdmi->reg_shift = 2; | |
2341 | break; | |
2342 | case 1: | |
2343 | reg_config = &hdmi_regmap_8bit_config; | |
2344 | break; | |
2345 | default: | |
2346 | dev_err(dev, "reg-io-width must be 1 or 4\n"); | |
2347 | return ERR_PTR(-EINVAL); | |
2348 | } | |
2349 | ||
2350 | iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
2351 | hdmi->regs = devm_ioremap_resource(dev, iores); | |
2352 | if (IS_ERR(hdmi->regs)) { | |
2353 | ret = PTR_ERR(hdmi->regs); | |
2354 | goto err_res; | |
2355 | } | |
2356 | ||
2357 | hdmi->regm = devm_regmap_init_mmio(dev, hdmi->regs, reg_config); | |
2358 | if (IS_ERR(hdmi->regm)) { | |
2359 | dev_err(dev, "Failed to configure regmap\n"); | |
2360 | ret = PTR_ERR(hdmi->regm); | |
2361 | goto err_res; | |
2362 | } | |
2363 | } else { | |
2364 | hdmi->regm = plat_data->regm; | |
9f04a1f2 | 2365 | } |
9aaf880e | 2366 | |
9aaf880e FE |
2367 | hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr"); |
2368 | if (IS_ERR(hdmi->isfr_clk)) { | |
2369 | ret = PTR_ERR(hdmi->isfr_clk); | |
b5878339 | 2370 | dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret); |
9f04a1f2 | 2371 | goto err_res; |
9aaf880e FE |
2372 | } |
2373 | ||
2374 | ret = clk_prepare_enable(hdmi->isfr_clk); | |
2375 | if (ret) { | |
b5878339 | 2376 | dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret); |
9f04a1f2 | 2377 | goto err_res; |
9aaf880e FE |
2378 | } |
2379 | ||
2380 | hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb"); | |
2381 | if (IS_ERR(hdmi->iahb_clk)) { | |
2382 | ret = PTR_ERR(hdmi->iahb_clk); | |
b5878339 | 2383 | dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret); |
9aaf880e FE |
2384 | goto err_isfr; |
2385 | } | |
2386 | ||
2387 | ret = clk_prepare_enable(hdmi->iahb_clk); | |
2388 | if (ret) { | |
b5878339 | 2389 | dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret); |
9aaf880e FE |
2390 | goto err_isfr; |
2391 | } | |
2392 | ||
ebe32c3e PHH |
2393 | hdmi->cec_clk = devm_clk_get(hdmi->dev, "cec"); |
2394 | if (PTR_ERR(hdmi->cec_clk) == -ENOENT) { | |
2395 | hdmi->cec_clk = NULL; | |
2396 | } else if (IS_ERR(hdmi->cec_clk)) { | |
2397 | ret = PTR_ERR(hdmi->cec_clk); | |
2398 | if (ret != -EPROBE_DEFER) | |
2399 | dev_err(hdmi->dev, "Cannot get HDMI cec clock: %d\n", | |
2400 | ret); | |
2401 | ||
2402 | hdmi->cec_clk = NULL; | |
2403 | goto err_iahb; | |
2404 | } else { | |
2405 | ret = clk_prepare_enable(hdmi->cec_clk); | |
2406 | if (ret) { | |
2407 | dev_err(hdmi->dev, "Cannot enable HDMI cec clock: %d\n", | |
2408 | ret); | |
2409 | goto err_iahb; | |
2410 | } | |
2411 | } | |
2412 | ||
9aaf880e | 2413 | /* Product and revision IDs */ |
be41fc55 LP |
2414 | hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8) |
2415 | | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0); | |
0527e12e LP |
2416 | prod_id0 = hdmi_readb(hdmi, HDMI_PRODUCT_ID0); |
2417 | prod_id1 = hdmi_readb(hdmi, HDMI_PRODUCT_ID1); | |
2418 | ||
2419 | if (prod_id0 != HDMI_PRODUCT_ID0_HDMI_TX || | |
2420 | (prod_id1 & ~HDMI_PRODUCT_ID1_HDCP) != HDMI_PRODUCT_ID1_HDMI_TX) { | |
2421 | dev_err(dev, "Unsupported HDMI controller (%04x:%02x:%02x)\n", | |
be41fc55 | 2422 | hdmi->version, prod_id0, prod_id1); |
0527e12e LP |
2423 | ret = -ENODEV; |
2424 | goto err_iahb; | |
2425 | } | |
2426 | ||
faba6c3c LP |
2427 | ret = dw_hdmi_detect_phy(hdmi); |
2428 | if (ret < 0) | |
2429 | goto err_iahb; | |
2430 | ||
2431 | dev_info(dev, "Detected HDMI TX controller v%x.%03x %s HDCP (%s)\n", | |
be41fc55 | 2432 | hdmi->version >> 12, hdmi->version & 0xfff, |
faba6c3c | 2433 | prod_id1 & HDMI_PRODUCT_ID1_HDCP ? "with" : "without", |
f1585f6e | 2434 | hdmi->phy.name); |
9aaf880e FE |
2435 | |
2436 | initialize_hdmi_ih_mutes(hdmi); | |
2437 | ||
c608119d | 2438 | irq = platform_get_irq(pdev, 0); |
69497eb9 LP |
2439 | if (irq < 0) { |
2440 | ret = irq; | |
c608119d | 2441 | goto err_iahb; |
69497eb9 | 2442 | } |
c608119d | 2443 | |
639a202c PZ |
2444 | ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq, |
2445 | dw_hdmi_irq, IRQF_SHARED, | |
2446 | dev_name(dev), hdmi); | |
2447 | if (ret) | |
b33ef619 | 2448 | goto err_iahb; |
639a202c | 2449 | |
e84b8d75 RK |
2450 | hdmi->cec_notifier = cec_notifier_get(dev); |
2451 | if (!hdmi->cec_notifier) { | |
2452 | ret = -ENOMEM; | |
2453 | goto err_iahb; | |
2454 | } | |
2455 | ||
9aaf880e FE |
2456 | /* |
2457 | * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator | |
2458 | * N and cts values before enabling phy | |
2459 | */ | |
2460 | hdmi_init_clk_regenerator(hdmi); | |
2461 | ||
3efc2fa3 VZ |
2462 | /* If DDC bus is not specified, try to register HDMI I2C bus */ |
2463 | if (!hdmi->ddc) { | |
2464 | hdmi->ddc = dw_hdmi_i2c_adapter(hdmi); | |
2465 | if (IS_ERR(hdmi->ddc)) | |
2466 | hdmi->ddc = NULL; | |
2467 | } | |
2468 | ||
69497eb9 LP |
2469 | hdmi->bridge.driver_private = hdmi; |
2470 | hdmi->bridge.funcs = &dw_hdmi_bridge_funcs; | |
d5ad7843 | 2471 | #ifdef CONFIG_OF |
69497eb9 | 2472 | hdmi->bridge.of_node = pdev->dev.of_node; |
d5ad7843 | 2473 | #endif |
9aaf880e | 2474 | |
a23d6265 | 2475 | dw_hdmi_setup_i2c(hdmi); |
386d3299 NA |
2476 | if (hdmi->phy.ops->setup_hpd) |
2477 | hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data); | |
9aaf880e | 2478 | |
7ed6c665 RK |
2479 | memset(&pdevinfo, 0, sizeof(pdevinfo)); |
2480 | pdevinfo.parent = dev; | |
2481 | pdevinfo.id = PLATFORM_DEVID_AUTO; | |
2482 | ||
2761ba6c | 2483 | config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID); |
0c674948 | 2484 | config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID); |
2761ba6c | 2485 | |
80e2f979 | 2486 | if (iores && config3 & HDMI_CONFIG3_AHBAUDDMA) { |
2761ba6c KM |
2487 | struct dw_hdmi_audio_data audio; |
2488 | ||
7ed6c665 RK |
2489 | audio.phys = iores->start; |
2490 | audio.base = hdmi->regs; | |
2491 | audio.irq = irq; | |
2492 | audio.hdmi = hdmi; | |
f5ce4057 | 2493 | audio.eld = hdmi->connector.eld; |
a7d555d2 RP |
2494 | hdmi->enable_audio = dw_hdmi_ahb_audio_enable; |
2495 | hdmi->disable_audio = dw_hdmi_ahb_audio_disable; | |
7ed6c665 RK |
2496 | |
2497 | pdevinfo.name = "dw-hdmi-ahb-audio"; | |
2498 | pdevinfo.data = &audio; | |
2499 | pdevinfo.size_data = sizeof(audio); | |
2500 | pdevinfo.dma_mask = DMA_BIT_MASK(32); | |
2501 | hdmi->audio = platform_device_register_full(&pdevinfo); | |
2761ba6c KM |
2502 | } else if (config0 & HDMI_CONFIG0_I2S) { |
2503 | struct dw_hdmi_i2s_audio_data audio; | |
2504 | ||
2505 | audio.hdmi = hdmi; | |
2506 | audio.write = hdmi_writeb; | |
2507 | audio.read = hdmi_readb; | |
a7d555d2 | 2508 | hdmi->enable_audio = dw_hdmi_i2s_audio_enable; |
57fbc055 | 2509 | hdmi->disable_audio = dw_hdmi_i2s_audio_disable; |
2761ba6c KM |
2510 | |
2511 | pdevinfo.name = "dw-hdmi-i2s-audio"; | |
2512 | pdevinfo.data = &audio; | |
2513 | pdevinfo.size_data = sizeof(audio); | |
2514 | pdevinfo.dma_mask = DMA_BIT_MASK(32); | |
2515 | hdmi->audio = platform_device_register_full(&pdevinfo); | |
7ed6c665 RK |
2516 | } |
2517 | ||
a616e63c RK |
2518 | if (config0 & HDMI_CONFIG0_CEC) { |
2519 | cec.hdmi = hdmi; | |
2520 | cec.ops = &dw_hdmi_cec_ops; | |
2521 | cec.irq = irq; | |
2522 | ||
2523 | pdevinfo.name = "dw-hdmi-cec"; | |
2524 | pdevinfo.data = &cec; | |
2525 | pdevinfo.size_data = sizeof(cec); | |
2526 | pdevinfo.dma_mask = 0; | |
2527 | ||
2528 | hdmi->cec = platform_device_register_full(&pdevinfo); | |
2529 | } | |
2530 | ||
3efc2fa3 VZ |
2531 | /* Reset HDMI DDC I2C master controller and mute I2CM interrupts */ |
2532 | if (hdmi->i2c) | |
2533 | dw_hdmi_i2c_init(hdmi); | |
2534 | ||
69497eb9 | 2535 | return hdmi; |
9aaf880e FE |
2536 | |
2537 | err_iahb: | |
3efc2fa3 VZ |
2538 | if (hdmi->i2c) { |
2539 | i2c_del_adapter(&hdmi->i2c->adap); | |
2540 | hdmi->ddc = NULL; | |
2541 | } | |
2542 | ||
e84b8d75 RK |
2543 | if (hdmi->cec_notifier) |
2544 | cec_notifier_put(hdmi->cec_notifier); | |
2545 | ||
9aaf880e | 2546 | clk_disable_unprepare(hdmi->iahb_clk); |
ebe32c3e PHH |
2547 | if (hdmi->cec_clk) |
2548 | clk_disable_unprepare(hdmi->cec_clk); | |
9aaf880e FE |
2549 | err_isfr: |
2550 | clk_disable_unprepare(hdmi->isfr_clk); | |
9f04a1f2 VZ |
2551 | err_res: |
2552 | i2c_put_adapter(hdmi->ddc); | |
9aaf880e | 2553 | |
69497eb9 | 2554 | return ERR_PTR(ret); |
9aaf880e FE |
2555 | } |
2556 | ||
69497eb9 | 2557 | static void __dw_hdmi_remove(struct dw_hdmi *hdmi) |
9aaf880e | 2558 | { |
7ed6c665 RK |
2559 | if (hdmi->audio && !IS_ERR(hdmi->audio)) |
2560 | platform_device_unregister(hdmi->audio); | |
a616e63c RK |
2561 | if (!IS_ERR(hdmi->cec)) |
2562 | platform_device_unregister(hdmi->cec); | |
7ed6c665 | 2563 | |
d94905e0 RK |
2564 | /* Disable all interrupts */ |
2565 | hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0); | |
2566 | ||
e383bf85 HV |
2567 | if (hdmi->cec_notifier) |
2568 | cec_notifier_put(hdmi->cec_notifier); | |
2569 | ||
9aaf880e FE |
2570 | clk_disable_unprepare(hdmi->iahb_clk); |
2571 | clk_disable_unprepare(hdmi->isfr_clk); | |
ebe32c3e PHH |
2572 | if (hdmi->cec_clk) |
2573 | clk_disable_unprepare(hdmi->cec_clk); | |
3efc2fa3 VZ |
2574 | |
2575 | if (hdmi->i2c) | |
2576 | i2c_del_adapter(&hdmi->i2c->adap); | |
2577 | else | |
2578 | i2c_put_adapter(hdmi->ddc); | |
17b5001b | 2579 | } |
69497eb9 LP |
2580 | |
2581 | /* ----------------------------------------------------------------------------- | |
2582 | * Probe/remove API, used from platforms based on the DRM bridge API. | |
2583 | */ | |
eea034af JS |
2584 | struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev, |
2585 | const struct dw_hdmi_plat_data *plat_data) | |
69497eb9 LP |
2586 | { |
2587 | struct dw_hdmi *hdmi; | |
69497eb9 LP |
2588 | |
2589 | hdmi = __dw_hdmi_probe(pdev, plat_data); | |
2590 | if (IS_ERR(hdmi)) | |
eea034af | 2591 | return hdmi; |
69497eb9 | 2592 | |
b678682e | 2593 | drm_bridge_add(&hdmi->bridge); |
69497eb9 | 2594 | |
eea034af | 2595 | return hdmi; |
69497eb9 LP |
2596 | } |
2597 | EXPORT_SYMBOL_GPL(dw_hdmi_probe); | |
2598 | ||
eea034af | 2599 | void dw_hdmi_remove(struct dw_hdmi *hdmi) |
69497eb9 | 2600 | { |
69497eb9 LP |
2601 | drm_bridge_remove(&hdmi->bridge); |
2602 | ||
2603 | __dw_hdmi_remove(hdmi); | |
2604 | } | |
2605 | EXPORT_SYMBOL_GPL(dw_hdmi_remove); | |
2606 | ||
2607 | /* ----------------------------------------------------------------------------- | |
2608 | * Bind/unbind API, used from platforms based on the component framework. | |
2609 | */ | |
eea034af JS |
2610 | struct dw_hdmi *dw_hdmi_bind(struct platform_device *pdev, |
2611 | struct drm_encoder *encoder, | |
2612 | const struct dw_hdmi_plat_data *plat_data) | |
69497eb9 LP |
2613 | { |
2614 | struct dw_hdmi *hdmi; | |
2615 | int ret; | |
2616 | ||
2617 | hdmi = __dw_hdmi_probe(pdev, plat_data); | |
2618 | if (IS_ERR(hdmi)) | |
eea034af | 2619 | return hdmi; |
69497eb9 LP |
2620 | |
2621 | ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL); | |
2622 | if (ret) { | |
eea034af | 2623 | dw_hdmi_remove(hdmi); |
69497eb9 | 2624 | DRM_ERROR("Failed to initialize bridge with drm\n"); |
eea034af | 2625 | return ERR_PTR(ret); |
69497eb9 LP |
2626 | } |
2627 | ||
eea034af | 2628 | return hdmi; |
69497eb9 LP |
2629 | } |
2630 | EXPORT_SYMBOL_GPL(dw_hdmi_bind); | |
2631 | ||
eea034af | 2632 | void dw_hdmi_unbind(struct dw_hdmi *hdmi) |
69497eb9 | 2633 | { |
69497eb9 LP |
2634 | __dw_hdmi_remove(hdmi); |
2635 | } | |
b21f4b65 | 2636 | EXPORT_SYMBOL_GPL(dw_hdmi_unbind); |
9aaf880e FE |
2637 | |
2638 | MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>"); | |
3d1b35a3 AY |
2639 | MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>"); |
2640 | MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>"); | |
3efc2fa3 | 2641 | MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>"); |
b21f4b65 | 2642 | MODULE_DESCRIPTION("DW HDMI transmitter driver"); |
9aaf880e | 2643 | MODULE_LICENSE("GPL"); |
b21f4b65 | 2644 | MODULE_ALIAS("platform:dw-hdmi"); |