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drm/sun4i: tcon top: Fix NULL/invalid pointer dereference in sun8i_tcon_top_un/bind
[linux-2.6-block.git] / drivers / gpu / drm / bridge / synopsys / dw-hdmi.c
CommitLineData
9aaf880e 1/*
3efc2fa3
VZ		 2 * DesignWare High-Definition Multimedia Interface (HDMI) driver
3 *
4 * Copyright (C) 2013-2015 Mentor Graphics Inc.
9aaf880e 5 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
3efc2fa3 6 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
9aaf880e
FE		 7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
9aaf880e 13 */
b21f4b65 14#include <linux/module.h>
9aaf880e
FE		 15#include <linux/irq.h>
16#include <linux/delay.h>
17#include <linux/err.h>
18#include <linux/clk.h>
5a819ed6 19#include <linux/hdmi.h>
6bcf4953 20#include <linux/mutex.h>
9aaf880e 21#include <linux/of_device.h>
80e2f979 22#include <linux/regmap.h>
b90120a9 23#include <linux/spinlock.h>
9aaf880e 24
3d1b35a3 25#include <drm/drm_of.h>
9aaf880e 26#include <drm/drmP.h>
2c5b2ccc 27#include <drm/drm_atomic_helper.h>
9aaf880e
FE		 28#include <drm/drm_edid.h>
29#include <drm/drm_encoder_slave.h>
264fce6c 30#include <drm/drm_scdc_helper.h>
fcd70cd3 31#include <drm/drm_probe_helper.h>
b21f4b65 32#include <drm/bridge/dw_hdmi.h>
9aaf880e 33
def23aa7
NA		 34#include <uapi/linux/media-bus-format.h>
35#include <uapi/linux/videodev2.h>
36
248a86fc
TR		 37#include "dw-hdmi.h"
38#include "dw-hdmi-audio.h"
a616e63c 39#include "dw-hdmi-cec.h"
9aaf880e 40
e84b8d75
RK		 41#include <media/cec-notifier.h>
42
94bb4dc1 43#define DDC_SEGMENT_ADDR 0x30
e84b8d75 44
9aaf880e
FE		 45#define HDMI_EDID_LEN 512
46
264fce6c
NA		 47/* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */
48#define SCDC_MIN_SOURCE_VERSION 0x1
49
50#define HDMI14_MAX_TMDSCLK 340000000
51
9aaf880e
FE		 52enum hdmi_datamap {
53 RGB444_8B = 0x01,
54 RGB444_10B = 0x03,
55 RGB444_12B = 0x05,
56 RGB444_16B = 0x07,
57 YCbCr444_8B = 0x09,
58 YCbCr444_10B = 0x0B,
59 YCbCr444_12B = 0x0D,
60 YCbCr444_16B = 0x0F,
61 YCbCr422_8B = 0x16,
62 YCbCr422_10B = 0x14,
63 YCbCr422_12B = 0x12,
64};
65
9aaf880e
FE		 66static const u16 csc_coeff_default[3][4] = {
67 { 0x2000, 0x0000, 0x0000, 0x0000 },
68 { 0x0000, 0x2000, 0x0000, 0x0000 },
69 { 0x0000, 0x0000, 0x2000, 0x0000 }
70};
71
72static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
73 { 0x2000, 0x6926, 0x74fd, 0x010e },
74 { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
75 { 0x2000, 0x0000, 0x38b4, 0x7e3b }
76};
77
78static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
79 { 0x2000, 0x7106, 0x7a02, 0x00a7 },
80 { 0x2000, 0x3264, 0x0000, 0x7e6d },
81 { 0x2000, 0x0000, 0x3b61, 0x7e25 }
82};
83
84static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
85 { 0x2591, 0x1322, 0x074b, 0x0000 },
86 { 0x6535, 0x2000, 0x7acc, 0x0200 },
87 { 0x6acd, 0x7534, 0x2000, 0x0200 }
88};
89
90static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
91 { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
92 { 0x62f0, 0x2000, 0x7d11, 0x0200 },
93 { 0x6756, 0x78ab, 0x2000, 0x0200 }
94};
95
96struct hdmi_vmode {
9aaf880e
FE		 97 bool mdataenablepolarity;
98
99 unsigned int mpixelclock;
100 unsigned int mpixelrepetitioninput;
101 unsigned int mpixelrepetitionoutput;
ba9877e2 102 unsigned int mtmdsclock;
9aaf880e
FE		 103};
104
105struct hdmi_data_info {
def23aa7
NA		 106 unsigned int enc_in_bus_format;
107 unsigned int enc_out_bus_format;
108 unsigned int enc_in_encoding;
109 unsigned int enc_out_encoding;
9aaf880e
FE		 110 unsigned int pix_repet_factor;
111 unsigned int hdcp_enable;
112 struct hdmi_vmode video_mode;
113};
114
3efc2fa3
VZ		 115struct dw_hdmi_i2c {
116 struct i2c_adapter adap;
117
118 struct mutex lock; /* used to serialize data transfers */
119 struct completion cmp;
120 u8 stat;
121
122 u8 slave_reg;
123 bool is_regaddr;
94bb4dc1 124 bool is_segment;
3efc2fa3
VZ		 125};
126
faba6c3c
LP		 127struct dw_hdmi_phy_data {
128 enum dw_hdmi_phy_type type;
129 const char *name;
b0e583e5 130 unsigned int gen;
faba6c3c 131 bool has_svsret;
2ef9dfed
KB		 132 int (*configure)(struct dw_hdmi *hdmi,
133 const struct dw_hdmi_plat_data *pdata,
134 unsigned long mpixelclock);
faba6c3c
LP		 135};
136
b21f4b65 137struct dw_hdmi {
9aaf880e 138 struct drm_connector connector;
70c963ec 139 struct drm_bridge bridge;
9aaf880e 140
be41fc55
LP		 141 unsigned int version;
142
143 struct platform_device *audio;
a616e63c 144 struct platform_device *cec;
9aaf880e
FE		 145 struct device *dev;
146 struct clk *isfr_clk;
147 struct clk *iahb_clk;
ebe32c3e 148 struct clk *cec_clk;
3efc2fa3 149 struct dw_hdmi_i2c *i2c;
9aaf880e
FE		 150
151 struct hdmi_data_info hdmi_data;
b21f4b65
AY		 152 const struct dw_hdmi_plat_data *plat_data;
153
9aaf880e
FE		 154 int vic;
155
156 u8 edid[HDMI_EDID_LEN];
9aaf880e 157
f1585f6e
LP		 158 struct {
159 const struct dw_hdmi_phy_ops *ops;
160 const char *name;
161 void *data;
162 bool enabled;
163 } phy;
faba6c3c 164
9aaf880e
FE		 165 struct drm_display_mode previous_mode;
166
9aaf880e
FE		 167 struct i2c_adapter *ddc;
168 void __iomem *regs;
05b1342f 169 bool sink_is_hdmi;
f709ec07 170 bool sink_has_audio;
9aaf880e 171
b872a8e1 172 struct mutex mutex; /* for state below and previous_mode */
381f05a7 173 enum drm_connector_force force; /* mutex-protected force state */
b872a8e1 174 bool disabled; /* DRM has disabled our bridge */
381f05a7 175 bool bridge_is_on; /* indicates the bridge is on */
aeac23bd
RK		 176 bool rxsense; /* rxsense state */
177 u8 phy_mask; /* desired phy int mask settings */
7cc4ab22 178 u8 mc_clkdis; /* clock disable register */
b872a8e1 179
b90120a9 180 spinlock_t audio_lock;
6bcf4953 181 struct mutex audio_mutex;
9aaf880e 182 unsigned int sample_rate;
b90120a9
RK		 183 unsigned int audio_cts;
184 unsigned int audio_n;
185 bool audio_enable;
0cd9d142 186
80e2f979
NA		 187 unsigned int reg_shift;
188 struct regmap *regm;
a7d555d2
RP		 189 void (*enable_audio)(struct dw_hdmi *hdmi);
190 void (*disable_audio)(struct dw_hdmi *hdmi);
e84b8d75
RK		 191
192 struct cec_notifier *cec_notifier;
9aaf880e
FE		 193};
194
aeac23bd
RK		 195#define HDMI_IH_PHY_STAT0_RX_SENSE \
196 (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \
197 HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3)
198
199#define HDMI_PHY_RX_SENSE \
200 (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \
201 HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3)
202
0cd9d142
AY		 203static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
204{
80e2f979 205 regmap_write(hdmi->regm, offset << hdmi->reg_shift, val);
0cd9d142
AY		 206}
207
208static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
209{
80e2f979
NA		 210 unsigned int val = 0;
211
212 regmap_read(hdmi->regm, offset << hdmi->reg_shift, &val);
213
214 return val;
0cd9d142
AY		 215}
216
b21f4b65 217static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
812bc615 218{
80e2f979 219 regmap_update_bits(hdmi->regm, reg << hdmi->reg_shift, mask, data);
812bc615
RK		 220}
221
b21f4b65 222static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
b5878339 223 u8 shift, u8 mask)
9aaf880e 224{
812bc615 225 hdmi_modb(hdmi, data << shift, mask, reg);
9aaf880e
FE		 226}
227
3efc2fa3
VZ		 228static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi)
229{
230 /* Software reset */
231 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ);
232
233 /* Set Standard Mode speed (determined to be 100KHz on iMX6) */
234 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_DIV);
235
236 /* Set done, not acknowledged and arbitration interrupt polarities */
237 hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT);
238 hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL,
239 HDMI_I2CM_CTLINT);
240
241 /* Clear DONE and ERROR interrupts */
242 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
243 HDMI_IH_I2CM_STAT0);
244
245 /* Mute DONE and ERROR interrupts */
246 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
247 HDMI_IH_MUTE_I2CM_STAT0);
248}
249
250static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi,
251 unsigned char *buf, unsigned int length)
252{
253 struct dw_hdmi_i2c *i2c = hdmi->i2c;
254 int stat;
255
256 if (!i2c->is_regaddr) {
257 dev_dbg(hdmi->dev, "set read register address to 0\n");
258 i2c->slave_reg = 0x00;
259 i2c->is_regaddr = true;
260 }
261
262 while (length--) {
263 reinit_completion(&i2c->cmp);
264
265 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
94bb4dc1
NY		 266 if (i2c->is_segment)
267 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT,
268 HDMI_I2CM_OPERATION);
269 else
270 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
271 HDMI_I2CM_OPERATION);
3efc2fa3
VZ		 272
273 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
274 if (!stat)
275 return -EAGAIN;
276
277 /* Check for error condition on the bus */
278 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
279 return -EIO;
280
281 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI);
282 }
94bb4dc1 283 i2c->is_segment = false;
3efc2fa3
VZ		 284
285 return 0;
286}
287
288static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi,
289 unsigned char *buf, unsigned int length)
290{
291 struct dw_hdmi_i2c *i2c = hdmi->i2c;
292 int stat;
293
294 if (!i2c->is_regaddr) {
295 /* Use the first write byte as register address */
296 i2c->slave_reg = buf[0];
297 length--;
298 buf++;
299 i2c->is_regaddr = true;
300 }
301
302 while (length--) {
303 reinit_completion(&i2c->cmp);
304
305 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO);
306 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
307 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE,
308 HDMI_I2CM_OPERATION);
309
310 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
311 if (!stat)
312 return -EAGAIN;
313
314 /* Check for error condition on the bus */
315 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
316 return -EIO;
317 }
318
319 return 0;
320}
321
322static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap,
323 struct i2c_msg *msgs, int num)
324{
325 struct dw_hdmi *hdmi = i2c_get_adapdata(adap);
326 struct dw_hdmi_i2c *i2c = hdmi->i2c;
327 u8 addr = msgs[0].addr;
328 int i, ret = 0;
329
330 dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr);
331
332 for (i = 0; i < num; i++) {
3efc2fa3
VZ		 333 if (msgs[i].len == 0) {
334 dev_dbg(hdmi->dev,
335 "unsupported transfer %d/%d, no data\n",
336 i + 1, num);
337 return -EOPNOTSUPP;
338 }
339 }
340
341 mutex_lock(&i2c->lock);
342
343 /* Unmute DONE and ERROR interrupts */
344 hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0);
345
346 /* Set slave device address taken from the first I2C message */
347 hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE);
348
349 /* Set slave device register address on transfer */
350 i2c->is_regaddr = false;
351
94bb4dc1
NY		 352 /* Set segment pointer for I2C extended read mode operation */
353 i2c->is_segment = false;
354
3efc2fa3
VZ		 355 for (i = 0; i < num; i++) {
356 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n",
357 i + 1, num, msgs[i].len, msgs[i].flags);
94bb4dc1
NY		 358 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) {
359 i2c->is_segment = true;
360 hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR);
361 hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR);
362 } else {
363 if (msgs[i].flags & I2C_M_RD)
364 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf,
365 msgs[i].len);
366 else
367 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf,
368 msgs[i].len);
369 }
3efc2fa3
VZ		 370 if (ret < 0)
371 break;
372 }
373
374 if (!ret)
375 ret = num;
376
377 /* Mute DONE and ERROR interrupts */
378 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
379 HDMI_IH_MUTE_I2CM_STAT0);
380
381 mutex_unlock(&i2c->lock);
382
383 return ret;
384}
385
386static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter)
387{
388 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
389}
390
391static const struct i2c_algorithm dw_hdmi_algorithm = {
392 .master_xfer = dw_hdmi_i2c_xfer,
393 .functionality = dw_hdmi_i2c_func,
394};
395
396static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi)
397{
398 struct i2c_adapter *adap;
399 struct dw_hdmi_i2c *i2c;
400 int ret;
401
402 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
403 if (!i2c)
404 return ERR_PTR(-ENOMEM);
405
406 mutex_init(&i2c->lock);
407 init_completion(&i2c->cmp);
408
409 adap = &i2c->adap;
410 adap->class = I2C_CLASS_DDC;
411 adap->owner = THIS_MODULE;
412 adap->dev.parent = hdmi->dev;
413 adap->algo = &dw_hdmi_algorithm;
414 strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name));
415 i2c_set_adapdata(adap, hdmi);
416
417 ret = i2c_add_adapter(adap);
418 if (ret) {
419 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
420 devm_kfree(hdmi->dev, i2c);
421 return ERR_PTR(ret);
422 }
423
424 hdmi->i2c = i2c;
425
426 dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
427
428 return adap;
429}
430
351e1354
RK		 431static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
432 unsigned int n)
9aaf880e 433{
622494a3
RK		 434 /* Must be set/cleared first */
435 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
9aaf880e
FE		 436
437 /* nshift factor = 0 */
812bc615 438 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
9aaf880e 439
9aaf880e
FE		 440 hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
441 HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
622494a3
RK		 442 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
443 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
444
445 hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
446 hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
447 hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
9aaf880e
FE		 448}
449
b195fbdb 450static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk)
9aaf880e
FE		 451{
452 unsigned int n = (128 * freq) / 1000;
d0c96d16
RK		 453 unsigned int mult = 1;
454
455 while (freq > 48000) {
456 mult *= 2;
457 freq /= 2;
458 }
9aaf880e
FE		 459
460 switch (freq) {
461 case 32000:
426701d0 462 if (pixel_clk == 25175000)
b195fbdb 463 n = 4576;
426701d0 464 else if (pixel_clk == 27027000)
b195fbdb 465 n = 4096;
426701d0 466 else if (pixel_clk == 74176000 || pixel_clk == 148352000)
9aaf880e
FE		 467 n = 11648;
468 else
469 n = 4096;
d0c96d16 470 n *= mult;
9aaf880e
FE		 471 break;
472
473 case 44100:
426701d0 474 if (pixel_clk == 25175000)
9aaf880e 475 n = 7007;
426701d0 476 else if (pixel_clk == 74176000)
9aaf880e 477 n = 17836;
426701d0 478 else if (pixel_clk == 148352000)
b195fbdb 479 n = 8918;
9aaf880e
FE		 480 else
481 n = 6272;
d0c96d16 482 n *= mult;
9aaf880e
FE		 483 break;
484
485 case 48000:
426701d0 486 if (pixel_clk == 25175000)
b195fbdb 487 n = 6864;
426701d0 488 else if (pixel_clk == 27027000)
b195fbdb 489 n = 6144;
426701d0 490 else if (pixel_clk == 74176000)
9aaf880e 491 n = 11648;
426701d0 492 else if (pixel_clk == 148352000)
b195fbdb 493 n = 5824;
9aaf880e
FE		 494 else
495 n = 6144;
d0c96d16 496 n *= mult;
9aaf880e
FE		 497 break;
498
499 default:
500 break;
501 }
502
503 return n;
504}
505
b21f4b65 506static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
b195fbdb 507 unsigned long pixel_clk, unsigned int sample_rate)
9aaf880e 508{
dfbdaf50 509 unsigned long ftdms = pixel_clk;
f879b38f 510 unsigned int n, cts;
dfbdaf50 511 u64 tmp;
9aaf880e 512
b195fbdb 513 n = hdmi_compute_n(sample_rate, pixel_clk);
9aaf880e 514
dfbdaf50
RK		 515 /*
516 * Compute the CTS value from the N value. Note that CTS and N
517 * can be up to 20 bits in total, so we need 64-bit math. Also
518 * note that our TDMS clock is not fully accurate; it is accurate
519 * to kHz. This can introduce an unnecessary remainder in the
520 * calculation below, so we don't try to warn about that.
521 */
522 tmp = (u64)ftdms * n;
523 do_div(tmp, 128 * sample_rate);
524 cts = tmp;
525
526 dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
527 __func__, sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000,
528 n, cts);
9aaf880e 529
b90120a9
RK		 530 spin_lock_irq(&hdmi->audio_lock);
531 hdmi->audio_n = n;
532 hdmi->audio_cts = cts;
533 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
534 spin_unlock_irq(&hdmi->audio_lock);
9aaf880e
FE		 535}
536
b21f4b65 537static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
9aaf880e 538{
6bcf4953 539 mutex_lock(&hdmi->audio_mutex);
b195fbdb 540 hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate);
6bcf4953 541 mutex_unlock(&hdmi->audio_mutex);
9aaf880e
FE		 542}
543
b21f4b65 544static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
9aaf880e 545{
6bcf4953 546 mutex_lock(&hdmi->audio_mutex);
ba9877e2 547 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock,
b195fbdb 548 hdmi->sample_rate);
6bcf4953 549 mutex_unlock(&hdmi->audio_mutex);
9aaf880e
FE		 550}
551
b5814fff
RK		 552void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
553{
554 mutex_lock(&hdmi->audio_mutex);
555 hdmi->sample_rate = rate;
ba9877e2 556 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock,
b195fbdb 557 hdmi->sample_rate);
b5814fff
RK		 558 mutex_unlock(&hdmi->audio_mutex);
559}
560EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate);
561
57fbc055
RP		 562static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi, bool enable)
563{
7cc4ab22
RK		 564 if (enable)
565 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE;
566 else
567 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_AUDCLK_DISABLE;
568 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
57fbc055
RP		 569}
570
a7d555d2
RP		 571static void dw_hdmi_ahb_audio_enable(struct dw_hdmi *hdmi)
572{
573 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
574}
575
576static void dw_hdmi_ahb_audio_disable(struct dw_hdmi *hdmi)
577{
578 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
579}
580
581static void dw_hdmi_i2s_audio_enable(struct dw_hdmi *hdmi)
582{
583 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
57fbc055
RP		 584 hdmi_enable_audio_clk(hdmi, true);
585}
586
587static void dw_hdmi_i2s_audio_disable(struct dw_hdmi *hdmi)
588{
589 hdmi_enable_audio_clk(hdmi, false);
a7d555d2
RP		 590}
591
b90120a9
RK		 592void dw_hdmi_audio_enable(struct dw_hdmi *hdmi)
593{
594 unsigned long flags;
595
596 spin_lock_irqsave(&hdmi->audio_lock, flags);
597 hdmi->audio_enable = true;
a7d555d2
RP		 598 if (hdmi->enable_audio)
599 hdmi->enable_audio(hdmi);
b90120a9
RK		 600 spin_unlock_irqrestore(&hdmi->audio_lock, flags);
601}
602EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable);
603
604void dw_hdmi_audio_disable(struct dw_hdmi *hdmi)
605{
606 unsigned long flags;
607
608 spin_lock_irqsave(&hdmi->audio_lock, flags);
609 hdmi->audio_enable = false;
a7d555d2
RP		 610 if (hdmi->disable_audio)
611 hdmi->disable_audio(hdmi);
b90120a9
RK		 612 spin_unlock_irqrestore(&hdmi->audio_lock, flags);
613}
614EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable);
615
def23aa7
NA		 616static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format)
617{
618 switch (bus_format) {
619 case MEDIA_BUS_FMT_RGB888_1X24:
620 case MEDIA_BUS_FMT_RGB101010_1X30:
621 case MEDIA_BUS_FMT_RGB121212_1X36:
622 case MEDIA_BUS_FMT_RGB161616_1X48:
623 return true;
624
625 default:
626 return false;
627 }
628}
629
630static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format)
631{
632 switch (bus_format) {
633 case MEDIA_BUS_FMT_YUV8_1X24:
634 case MEDIA_BUS_FMT_YUV10_1X30:
635 case MEDIA_BUS_FMT_YUV12_1X36:
636 case MEDIA_BUS_FMT_YUV16_1X48:
637 return true;
638
639 default:
640 return false;
641 }
642}
643
644static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format)
645{
646 switch (bus_format) {
647 case MEDIA_BUS_FMT_UYVY8_1X16:
648 case MEDIA_BUS_FMT_UYVY10_1X20:
649 case MEDIA_BUS_FMT_UYVY12_1X24:
650 return true;
651
652 default:
653 return false;
654 }
655}
656
ba9877e2
NA		 657static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format)
658{
659 switch (bus_format) {
660 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
661 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
662 case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
663 case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
664 return true;
665
666 default:
667 return false;
668 }
669}
670
def23aa7
NA		 671static int hdmi_bus_fmt_color_depth(unsigned int bus_format)
672{
673 switch (bus_format) {
674 case MEDIA_BUS_FMT_RGB888_1X24:
675 case MEDIA_BUS_FMT_YUV8_1X24:
676 case MEDIA_BUS_FMT_UYVY8_1X16:
677 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
678 return 8;
679
680 case MEDIA_BUS_FMT_RGB101010_1X30:
681 case MEDIA_BUS_FMT_YUV10_1X30:
682 case MEDIA_BUS_FMT_UYVY10_1X20:
683 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
684 return 10;
685
686 case MEDIA_BUS_FMT_RGB121212_1X36:
687 case MEDIA_BUS_FMT_YUV12_1X36:
688 case MEDIA_BUS_FMT_UYVY12_1X24:
689 case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
690 return 12;
691
692 case MEDIA_BUS_FMT_RGB161616_1X48:
693 case MEDIA_BUS_FMT_YUV16_1X48:
694 case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
695 return 16;
696
697 default:
698 return 0;
699 }
700}
701
9aaf880e
FE		 702/*
703 * this submodule is responsible for the video data synchronization.
704 * for example, for RGB 4:4:4 input, the data map is defined as
705 * pin{47~40} <==> R[7:0]
706 * pin{31~24} <==> G[7:0]
707 * pin{15~8} <==> B[7:0]
708 */
b21f4b65 709static void hdmi_video_sample(struct dw_hdmi *hdmi)
9aaf880e
FE		 710{
711 int color_format = 0;
712 u8 val;
713
def23aa7
NA		 714 switch (hdmi->hdmi_data.enc_in_bus_format) {
715 case MEDIA_BUS_FMT_RGB888_1X24:
716 color_format = 0x01;
717 break;
718 case MEDIA_BUS_FMT_RGB101010_1X30:
719 color_format = 0x03;
720 break;
721 case MEDIA_BUS_FMT_RGB121212_1X36:
722 color_format = 0x05;
723 break;
724 case MEDIA_BUS_FMT_RGB161616_1X48:
725 color_format = 0x07;
726 break;
727
728 case MEDIA_BUS_FMT_YUV8_1X24:
729 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
730 color_format = 0x09;
731 break;
732 case MEDIA_BUS_FMT_YUV10_1X30:
733 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
734 color_format = 0x0B;
735 break;
736 case MEDIA_BUS_FMT_YUV12_1X36:
737 case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
738 color_format = 0x0D;
739 break;
740 case MEDIA_BUS_FMT_YUV16_1X48:
741 case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
742 color_format = 0x0F;
743 break;
744
745 case MEDIA_BUS_FMT_UYVY8_1X16:
746 color_format = 0x16;
747 break;
748 case MEDIA_BUS_FMT_UYVY10_1X20:
749 color_format = 0x14;
750 break;
751 case MEDIA_BUS_FMT_UYVY12_1X24:
752 color_format = 0x12;
753 break;
754
755 default:
756 return;
9aaf880e
FE		 757 }
758
759 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
760 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
761 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
762 hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
763
764 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
765 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
766 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
767 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
768 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
769 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
770 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
771 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
772 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
773 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
774 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
775}
776
b21f4b65 777static int is_color_space_conversion(struct dw_hdmi *hdmi)
9aaf880e 778{
def23aa7 779 return hdmi->hdmi_data.enc_in_bus_format != hdmi->hdmi_data.enc_out_bus_format;
9aaf880e
FE		 780}
781
b21f4b65 782static int is_color_space_decimation(struct dw_hdmi *hdmi)
9aaf880e 783{
def23aa7 784 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
ba92b225 785 return 0;
def23aa7
NA		 786
787 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) ||
788 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format))
ba92b225 789 return 1;
def23aa7 790
ba92b225 791 return 0;
9aaf880e
FE		 792}
793
b21f4b65 794static int is_color_space_interpolation(struct dw_hdmi *hdmi)
9aaf880e 795{
def23aa7 796 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format))
ba92b225 797 return 0;
def23aa7
NA		 798
799 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
800 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
ba92b225 801 return 1;
def23aa7 802
ba92b225 803 return 0;
9aaf880e
FE		 804}
805
b21f4b65 806static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
9aaf880e
FE		 807{
808 const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
c082f9d7 809 unsigned i;
9aaf880e 810 u32 csc_scale = 1;
9aaf880e
FE		 811
812 if (is_color_space_conversion(hdmi)) {
def23aa7
NA		 813 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
814 if (hdmi->hdmi_data.enc_out_encoding ==
815 V4L2_YCBCR_ENC_601)
9aaf880e
FE		 816 csc_coeff = &csc_coeff_rgb_out_eitu601;
817 else
818 csc_coeff = &csc_coeff_rgb_out_eitu709;
def23aa7
NA		 819 } else if (hdmi_bus_fmt_is_rgb(
820 hdmi->hdmi_data.enc_in_bus_format)) {
821 if (hdmi->hdmi_data.enc_out_encoding ==
822 V4L2_YCBCR_ENC_601)
9aaf880e
FE		 823 csc_coeff = &csc_coeff_rgb_in_eitu601;
824 else
825 csc_coeff = &csc_coeff_rgb_in_eitu709;
826 csc_scale = 0;
827 }
828 }
829
c082f9d7
RK		 830 /* The CSC registers are sequential, alternating MSB then LSB */
831 for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
832 u16 coeff_a = (*csc_coeff)[0][i];
833 u16 coeff_b = (*csc_coeff)[1][i];
834 u16 coeff_c = (*csc_coeff)[2][i];
835
b5878339 836 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
c082f9d7
RK		 837 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
838 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
839 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
b5878339 840 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
c082f9d7
RK		 841 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
842 }
9aaf880e 843
812bc615
RK		 844 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
845 HDMI_CSC_SCALE);
9aaf880e
FE		 846}
847
b21f4b65 848static void hdmi_video_csc(struct dw_hdmi *hdmi)
9aaf880e
FE		 849{
850 int color_depth = 0;
851 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
852 int decimation = 0;
9aaf880e
FE		 853
854 /* YCC422 interpolation to 444 mode */
855 if (is_color_space_interpolation(hdmi))
856 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
857 else if (is_color_space_decimation(hdmi))
858 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
859
def23aa7
NA		 860 switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) {
861 case 8:
9aaf880e 862 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
def23aa7
NA		 863 break;
864 case 10:
9aaf880e 865 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
def23aa7
NA		 866 break;
867 case 12:
9aaf880e 868 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
def23aa7
NA		 869 break;
870 case 16:
9aaf880e 871 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
def23aa7
NA		 872 break;
873
874 default:
9aaf880e 875 return;
def23aa7 876 }
9aaf880e
FE		 877
878 /* Configure the CSC registers */
879 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
812bc615
RK		 880 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
881 HDMI_CSC_SCALE);
9aaf880e 882
b21f4b65 883 dw_hdmi_update_csc_coeffs(hdmi);
9aaf880e
FE		 884}
885
886/*
887 * HDMI video packetizer is used to packetize the data.
888 * for example, if input is YCC422 mode or repeater is used,
889 * data should be repacked this module can be bypassed.
890 */
b21f4b65 891static void hdmi_video_packetize(struct dw_hdmi *hdmi)
9aaf880e
FE		 892{
893 unsigned int color_depth = 0;
894 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
895 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
896 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
bebdf664 897 u8 val, vp_conf;
9aaf880e 898
def23aa7 899 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
ba9877e2
NA		 900 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format) ||
901 hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) {
def23aa7
NA		 902 switch (hdmi_bus_fmt_color_depth(
903 hdmi->hdmi_data.enc_out_bus_format)) {
904 case 8:
9aaf880e
FE		 905 color_depth = 4;
906 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
def23aa7
NA		 907 break;
908 case 10:
9aaf880e 909 color_depth = 5;
def23aa7
NA		 910 break;
911 case 12:
9aaf880e 912 color_depth = 6;
def23aa7
NA		 913 break;
914 case 16:
9aaf880e 915 color_depth = 7;
def23aa7
NA		 916 break;
917 default:
918 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
b5878339 919 }
def23aa7
NA		 920 } else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) {
921 switch (hdmi_bus_fmt_color_depth(
922 hdmi->hdmi_data.enc_out_bus_format)) {
923 case 0:
924 case 8:
9aaf880e 925 remap_size = HDMI_VP_REMAP_YCC422_16bit;
def23aa7
NA		 926 break;
927 case 10:
9aaf880e 928 remap_size = HDMI_VP_REMAP_YCC422_20bit;
def23aa7
NA		 929 break;
930 case 12:
9aaf880e 931 remap_size = HDMI_VP_REMAP_YCC422_24bit;
def23aa7
NA		 932 break;
933
934 default:
9aaf880e 935 return;
def23aa7 936 }
9aaf880e 937 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
b5878339 938 } else {
9aaf880e 939 return;
b5878339 940 }
9aaf880e
FE		 941
942 /* set the packetizer registers */
943 val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
944 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
945 ((hdmi_data->pix_repet_factor <<
946 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
947 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
948 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
949
812bc615
RK		 950 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
951 HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
9aaf880e
FE		 952
953 /* Data from pixel repeater block */
954 if (hdmi_data->pix_repet_factor > 1) {
bebdf664
RK		 955 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
956 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
9aaf880e 957 } else { /* data from packetizer block */
bebdf664
RK		 958 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
959 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
9aaf880e
FE		 960 }
961
bebdf664
RK		 962 hdmi_modb(hdmi, vp_conf,
963 HDMI_VP_CONF_PR_EN_MASK |
964 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
965
812bc615
RK		 966 hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
967 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
9aaf880e
FE		 968
969 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
970
971 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
bebdf664
RK		 972 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
973 HDMI_VP_CONF_PP_EN_ENABLE |
974 HDMI_VP_CONF_YCC422_EN_DISABLE;
9aaf880e 975 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
bebdf664
RK		 976 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
977 HDMI_VP_CONF_PP_EN_DISABLE |
978 HDMI_VP_CONF_YCC422_EN_ENABLE;
9aaf880e 979 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
bebdf664
RK		 980 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
981 HDMI_VP_CONF_PP_EN_DISABLE |
982 HDMI_VP_CONF_YCC422_EN_DISABLE;
9aaf880e
FE		 983 } else {
984 return;
985 }
986
bebdf664
RK		 987 hdmi_modb(hdmi, vp_conf,
988 HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
989 HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
990
812bc615
RK		 991 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
992 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
993 HDMI_VP_STUFF_PP_STUFFING_MASK |
994 HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
9aaf880e 995
812bc615
RK		 996 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
997 HDMI_VP_CONF);
9aaf880e
FE		 998}
999
f1585f6e
LP		 1000/* -----------------------------------------------------------------------------
1001 * Synopsys PHY Handling
1002 */
1003
b21f4b65 1004static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
b5878339 1005 unsigned char bit)
9aaf880e 1006{
812bc615
RK		 1007 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
1008 HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
9aaf880e
FE		 1009}
1010
b21f4b65 1011static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
9aaf880e 1012{
a4d3b8b0
AY		 1013 u32 val;
1014
1015 while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
9aaf880e
FE		 1016 if (msec-- == 0)
1017 return false;
0e6bcf3a 1018 udelay(1000);
9aaf880e 1019 }
a4d3b8b0
AY		 1020 hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
1021
9aaf880e
FE		 1022 return true;
1023}
1024
2ef9dfed
KB		 1025void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
1026 unsigned char addr)
9aaf880e
FE		 1027{
1028 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
1029 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
1030 hdmi_writeb(hdmi, (unsigned char)(data >> 8),
b5878339 1031 HDMI_PHY_I2CM_DATAO_1_ADDR);
9aaf880e 1032 hdmi_writeb(hdmi, (unsigned char)(data >> 0),
b5878339 1033 HDMI_PHY_I2CM_DATAO_0_ADDR);
9aaf880e 1034 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
b5878339 1035 HDMI_PHY_I2CM_OPERATION_ADDR);
9aaf880e
FE		 1036 hdmi_phy_wait_i2c_done(hdmi, 1000);
1037}
2ef9dfed 1038EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_write);
9aaf880e 1039
836f90f9
NA		 1040/* Filter out invalid setups to avoid configuring SCDC and scrambling */
1041static bool dw_hdmi_support_scdc(struct dw_hdmi *hdmi)
1042{
1043 struct drm_display_info *display = &hdmi->connector.display_info;
1044
1045 /* Completely disable SCDC support for older controllers */
1046 if (hdmi->version < 0x200a)
1047 return false;
1048
1049 /* Disable if SCDC is not supported, or if an HF-VSDB block is absent */
1050 if (!display->hdmi.scdc.supported ||
1051 !display->hdmi.scdc.scrambling.supported)
1052 return false;
1053
1054 /*
1055 * Disable if display only support low TMDS rates and scrambling
1056 * for low rates is not supported either
1057 */
1058 if (!display->hdmi.scdc.scrambling.low_rates &&
1059 display->max_tmds_clock <= 340000)
1060 return false;
1061
1062 return true;
1063}
1064
264fce6c
NA		 1065/*
1066 * HDMI2.0 Specifies the following procedure for High TMDS Bit Rates:
1067 * - The Source shall suspend transmission of the TMDS clock and data
1068 * - The Source shall write to the TMDS_Bit_Clock_Ratio bit to change it
1069 * from a 0 to a 1 or from a 1 to a 0
1070 * - The Source shall allow a minimum of 1 ms and a maximum of 100 ms from
1071 * the time the TMDS_Bit_Clock_Ratio bit is written until resuming
1072 * transmission of TMDS clock and data
1073 *
1074 * To respect the 100ms maximum delay, the dw_hdmi_set_high_tmds_clock_ratio()
1075 * helper should called right before enabling the TMDS Clock and Data in
1076 * the PHY configuration callback.
1077 */
1078void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi)
1079{
ba9877e2 1080 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock;
264fce6c
NA		 1081
1082 /* Control for TMDS Bit Period/TMDS Clock-Period Ratio */
836f90f9 1083 if (dw_hdmi_support_scdc(hdmi)) {
264fce6c
NA		 1084 if (mtmdsclock > HDMI14_MAX_TMDSCLK)
1085 drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 1);
1086 else
1087 drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 0);
1088 }
1089}
1090EXPORT_SYMBOL_GPL(dw_hdmi_set_high_tmds_clock_ratio);
1091
2fada109 1092static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable)
9aaf880e 1093{
2fada109 1094 hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0,
9aaf880e
FE		 1095 HDMI_PHY_CONF0_PDZ_OFFSET,
1096 HDMI_PHY_CONF0_PDZ_MASK);
1097}
1098
b21f4b65 1099static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
9aaf880e
FE		 1100{
1101 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1102 HDMI_PHY_CONF0_ENTMDS_OFFSET,
1103 HDMI_PHY_CONF0_ENTMDS_MASK);
1104}
1105
f4104e8f 1106static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable)
d346c14e
AY		 1107{
1108 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
f4104e8f
LP		 1109 HDMI_PHY_CONF0_SVSRET_OFFSET,
1110 HDMI_PHY_CONF0_SVSRET_MASK);
d346c14e
AY		 1111}
1112
5765916a 1113void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
9aaf880e
FE		 1114{
1115 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1116 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
1117 HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
1118}
5765916a 1119EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_pddq);
9aaf880e 1120
5765916a 1121void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
9aaf880e
FE		 1122{
1123 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1124 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
1125 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
1126}
5765916a 1127EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_txpwron);
9aaf880e 1128
b21f4b65 1129static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
9aaf880e
FE		 1130{
1131 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1132 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
1133 HDMI_PHY_CONF0_SELDATAENPOL_MASK);
1134}
1135
b21f4b65 1136static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
9aaf880e
FE		 1137{
1138 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1139 HDMI_PHY_CONF0_SELDIPIF_OFFSET,
1140 HDMI_PHY_CONF0_SELDIPIF_MASK);
1141}
1142
5765916a
JS		 1143void dw_hdmi_phy_reset(struct dw_hdmi *hdmi)
1144{
1145 /* PHY reset. The reset signal is active high on Gen2 PHYs. */
1146 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ);
1147 hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ);
1148}
1149EXPORT_SYMBOL_GPL(dw_hdmi_phy_reset);
1150
1151void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address)
1152{
1153 hdmi_phy_test_clear(hdmi, 1);
1154 hdmi_writeb(hdmi, address, HDMI_PHY_I2CM_SLAVE_ADDR);
1155 hdmi_phy_test_clear(hdmi, 0);
1156}
1157EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_set_addr);
1158
b0e583e5
LP		 1159static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi)
1160{
f1585f6e 1161 const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
b0e583e5
LP		 1162 unsigned int i;
1163 u16 val;
1164
1165 if (phy->gen == 1) {
1166 dw_hdmi_phy_enable_tmds(hdmi, 0);
1167 dw_hdmi_phy_enable_powerdown(hdmi, true);
1168 return;
1169 }
1170
1171 dw_hdmi_phy_gen2_txpwron(hdmi, 0);
1172
1173 /*
1174 * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went
1175 * to low power mode.
1176 */
1177 for (i = 0; i < 5; ++i) {
1178 val = hdmi_readb(hdmi, HDMI_PHY_STAT0);
1179 if (!(val & HDMI_PHY_TX_PHY_LOCK))
1180 break;
1181
1182 usleep_range(1000, 2000);
1183 }
1184
1185 if (val & HDMI_PHY_TX_PHY_LOCK)
1186 dev_warn(hdmi->dev, "PHY failed to power down\n");
1187 else
1188 dev_dbg(hdmi->dev, "PHY powered down in %u iterations\n", i);
1189
1190 dw_hdmi_phy_gen2_pddq(hdmi, 1);
1191}
1192
181e0ef0
LP		 1193static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi)
1194{
f1585f6e 1195 const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
181e0ef0
LP		 1196 unsigned int i;
1197 u8 val;
1198
1199 if (phy->gen == 1) {
1200 dw_hdmi_phy_enable_powerdown(hdmi, false);
1201
1202 /* Toggle TMDS enable. */
1203 dw_hdmi_phy_enable_tmds(hdmi, 0);
1204 dw_hdmi_phy_enable_tmds(hdmi, 1);
1205 return 0;
1206 }
1207
1208 dw_hdmi_phy_gen2_txpwron(hdmi, 1);
1209 dw_hdmi_phy_gen2_pddq(hdmi, 0);
1210
1211 /* Wait for PHY PLL lock */
1212 for (i = 0; i < 5; ++i) {
1213 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
1214 if (val)
1215 break;
1216
1217 usleep_range(1000, 2000);
1218 }
1219
1220 if (!val) {
1221 dev_err(hdmi->dev, "PHY PLL failed to lock\n");
1222 return -ETIMEDOUT;
1223 }
1224
1225 dev_dbg(hdmi->dev, "PHY PLL locked %u iterations\n", i);
1226 return 0;
1227}
1228
2ef9dfed
KB		 1229/*
1230 * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available
1231 * information the DWC MHL PHY has the same register layout and is thus also
1232 * supported by this function.
1233 */
1234static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi,
1235 const struct dw_hdmi_plat_data *pdata,
1236 unsigned long mpixelclock)
9aaf880e 1237{
39cc1535
RK		 1238 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
1239 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
1240 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
9aaf880e 1241
ba9877e2
NA		 1242 /* TOFIX Will need 420 specific PHY configuration tables */
1243
39cc1535
RK		 1244 /* PLL/MPLL Cfg - always match on final entry */
1245 for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
2ef9dfed 1246 if (mpixelclock <= mpll_config->mpixelclock)
39cc1535
RK		 1247 break;
1248
1249 for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
2ef9dfed 1250 if (mpixelclock <= curr_ctrl->mpixelclock)
39cc1535
RK		 1251 break;
1252
1253 for (; phy_config->mpixelclock != ~0UL; phy_config++)
2ef9dfed 1254 if (mpixelclock <= phy_config->mpixelclock)
39cc1535
RK		 1255 break;
1256
1257 if (mpll_config->mpixelclock == ~0UL ||
1258 curr_ctrl->mpixelclock == ~0UL ||
2ef9dfed 1259 phy_config->mpixelclock == ~0UL)
39cc1535 1260 return -EINVAL;
2ef9dfed
KB		 1261
1262 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce,
1263 HDMI_3D_TX_PHY_CPCE_CTRL);
1264 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp,
1265 HDMI_3D_TX_PHY_GMPCTRL);
1266 dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0],
1267 HDMI_3D_TX_PHY_CURRCTRL);
1268
1269 dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL);
1270 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK,
1271 HDMI_3D_TX_PHY_MSM_CTRL);
1272
1273 dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM);
1274 dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr,
1275 HDMI_3D_TX_PHY_CKSYMTXCTRL);
1276 dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr,
1277 HDMI_3D_TX_PHY_VLEVCTRL);
1278
1279 /* Override and disable clock termination. */
1280 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE,
1281 HDMI_3D_TX_PHY_CKCALCTRL);
1282
1283 return 0;
1284}
1285
1286static int hdmi_phy_configure(struct dw_hdmi *hdmi)
1287{
1288 const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1289 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
1290 unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock;
ba9877e2 1291 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock;
2ef9dfed 1292 int ret;
39cc1535 1293
b0e583e5 1294 dw_hdmi_phy_power_off(hdmi);
9aaf880e 1295
264fce6c
NA		 1296 dw_hdmi_set_high_tmds_clock_ratio(hdmi);
1297
2668db37 1298 /* Leave low power consumption mode by asserting SVSRET. */
f1585f6e 1299 if (phy->has_svsret)
2668db37
LP		 1300 dw_hdmi_phy_enable_svsret(hdmi, 1);
1301
5765916a 1302 dw_hdmi_phy_reset(hdmi);
9aaf880e
FE		 1303
1304 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
1305
5765916a 1306 dw_hdmi_phy_i2c_set_addr(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2);
9aaf880e 1307
2ef9dfed
KB		 1308 /* Write to the PHY as configured by the platform */
1309 if (pdata->configure_phy)
1310 ret = pdata->configure_phy(hdmi, pdata, mpixelclock);
1311 else
1312 ret = phy->configure(hdmi, pdata, mpixelclock);
1313 if (ret) {
1314 dev_err(hdmi->dev, "PHY configuration failed (clock %lu)\n",
1315 mpixelclock);
1316 return ret;
1317 }
9aaf880e 1318
264fce6c 1319 /* Wait for resuming transmission of TMDS clock and data */
ba9877e2 1320 if (mtmdsclock > HDMI14_MAX_TMDSCLK)
264fce6c
NA		 1321 msleep(100);
1322
181e0ef0 1323 return dw_hdmi_phy_power_on(hdmi);
9aaf880e
FE		 1324}
1325
f1585f6e
LP		 1326static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data,
1327 struct drm_display_mode *mode)
9aaf880e
FE		 1328{
1329 int i, ret;
9aaf880e
FE		 1330
1331 /* HDMI Phy spec says to do the phy initialization sequence twice */
1332 for (i = 0; i < 2; i++) {
b21f4b65
AY		 1333 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
1334 dw_hdmi_phy_sel_interface_control(hdmi, 0);
9aaf880e 1335
8b9e1c0d 1336 ret = hdmi_phy_configure(hdmi);
9aaf880e
FE		 1337 if (ret)
1338 return ret;
1339 }
1340
9aaf880e
FE		 1341 return 0;
1342}
1343
f1585f6e
LP		 1344static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data)
1345{
1346 dw_hdmi_phy_power_off(hdmi);
1347}
1348
5765916a
JS		 1349enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi,
1350 void *data)
f1585f6e
LP		 1351{
1352 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1353 connector_status_connected : connector_status_disconnected;
1354}
5765916a 1355EXPORT_SYMBOL_GPL(dw_hdmi_phy_read_hpd);
f1585f6e 1356
5765916a
JS		 1357void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data,
1358 bool force, bool disabled, bool rxsense)
386d3299
NA		 1359{
1360 u8 old_mask = hdmi->phy_mask;
1361
1362 if (force || disabled || !rxsense)
1363 hdmi->phy_mask |= HDMI_PHY_RX_SENSE;
1364 else
1365 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE;
1366
1367 if (old_mask != hdmi->phy_mask)
1368 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1369}
5765916a 1370EXPORT_SYMBOL_GPL(dw_hdmi_phy_update_hpd);
386d3299 1371
5765916a 1372void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data)
386d3299
NA		 1373{
1374 /*
1375 * Configure the PHY RX SENSE and HPD interrupts polarities and clear
1376 * any pending interrupt.
1377 */
1378 hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0);
1379 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1380 HDMI_IH_PHY_STAT0);
1381
1382 /* Enable cable hot plug irq. */
1383 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1384
1385 /* Clear and unmute interrupts. */
1386 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1387 HDMI_IH_PHY_STAT0);
1388 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
1389 HDMI_IH_MUTE_PHY_STAT0);
1390}
5765916a 1391EXPORT_SYMBOL_GPL(dw_hdmi_phy_setup_hpd);
386d3299 1392
f1585f6e
LP		 1393static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = {
1394 .init = dw_hdmi_phy_init,
1395 .disable = dw_hdmi_phy_disable,
1396 .read_hpd = dw_hdmi_phy_read_hpd,
386d3299
NA		 1397 .update_hpd = dw_hdmi_phy_update_hpd,
1398 .setup_hpd = dw_hdmi_phy_setup_hpd,
f1585f6e
LP		 1399};
1400
1401/* -----------------------------------------------------------------------------
1402 * HDMI TX Setup
1403 */
1404
b21f4b65 1405static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
9aaf880e 1406{
812bc615 1407 u8 de;
9aaf880e
FE		 1408
1409 if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
1410 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
1411 else
1412 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
1413
1414 /* disable rx detect */
812bc615
RK		 1415 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
1416 HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
9aaf880e 1417
812bc615 1418 hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
9aaf880e 1419
812bc615
RK		 1420 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
1421 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
9aaf880e
FE		 1422}
1423
d4ac4cb6 1424static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
9aaf880e 1425{
d4ac4cb6
RK		 1426 struct hdmi_avi_infoframe frame;
1427 u8 val;
9aaf880e 1428
d4ac4cb6 1429 /* Initialise info frame from DRM mode */
13d0add3
VS		 1430 drm_hdmi_avi_infoframe_from_display_mode(&frame,
1431 &hdmi->connector, mode);
9aaf880e 1432
def23aa7 1433 if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
d4ac4cb6 1434 frame.colorspace = HDMI_COLORSPACE_YUV444;
def23aa7 1435 else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
d4ac4cb6 1436 frame.colorspace = HDMI_COLORSPACE_YUV422;
ba9877e2
NA		 1437 else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
1438 frame.colorspace = HDMI_COLORSPACE_YUV420;
9aaf880e 1439 else
d4ac4cb6 1440 frame.colorspace = HDMI_COLORSPACE_RGB;
9aaf880e
FE		 1441
1442 /* Set up colorimetry */
def23aa7
NA		 1443 switch (hdmi->hdmi_data.enc_out_encoding) {
1444 case V4L2_YCBCR_ENC_601:
1445 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601)
1446 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1447 else
1448 frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
1449 frame.extended_colorimetry =
d4ac4cb6 1450 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
f40d6560 1451 break;
def23aa7
NA		 1452 case V4L2_YCBCR_ENC_709:
1453 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709)
1454 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1455 else
1456 frame.colorimetry = HDMI_COLORIMETRY_ITU_709;
1457 frame.extended_colorimetry =
d4ac4cb6 1458 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
def23aa7
NA		 1459 break;
1460 default: /* Carries no data */
1461 frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
1462 frame.extended_colorimetry =
1463 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1464 break;
9aaf880e
FE		 1465 }
1466
d4ac4cb6
RK		 1467 frame.scan_mode = HDMI_SCAN_MODE_NONE;
1468
1469 /*
1470 * The Designware IP uses a different byte format from standard
1471 * AVI info frames, though generally the bits are in the correct
1472 * bytes.
1473 */
1474
1475 /*
b0118e7d
JA		 1476 * AVI data byte 1 differences: Colorspace in bits 0,1 rather than 5,6,
1477 * scan info in bits 4,5 rather than 0,1 and active aspect present in
1478 * bit 6 rather than 4.
d4ac4cb6 1479 */
b0118e7d 1480 val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 3);
d4ac4cb6
RK		 1481 if (frame.active_aspect & 15)
1482 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT;
1483 if (frame.top_bar || frame.bottom_bar)
1484 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR;
1485 if (frame.left_bar || frame.right_bar)
1486 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR;
1487 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
1488
1489 /* AVI data byte 2 differences: none */
1490 val = ((frame.colorimetry & 0x3) << 6) |
1491 ((frame.picture_aspect & 0x3) << 4) |
1492 (frame.active_aspect & 0xf);
9aaf880e
FE		 1493 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
1494
d4ac4cb6
RK		 1495 /* AVI data byte 3 differences: none */
1496 val = ((frame.extended_colorimetry & 0x7) << 4) |
1497 ((frame.quantization_range & 0x3) << 2) |
1498 (frame.nups & 0x3);
1499 if (frame.itc)
1500 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID;
9aaf880e
FE		 1501 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
1502
d4ac4cb6
RK		 1503 /* AVI data byte 4 differences: none */
1504 val = frame.video_code & 0x7f;
1505 hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
9aaf880e
FE		 1506
1507 /* AVI Data Byte 5- set up input and output pixel repetition */
1508 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
1509 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
1510 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
1511 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
1512 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
1513 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
1514 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
1515
d4ac4cb6
RK		 1516 /*
1517 * AVI data byte 5 differences: content type in 0,1 rather than 4,5,
1518 * ycc range in bits 2,3 rather than 6,7
1519 */
1520 val = ((frame.ycc_quantization_range & 0x3) << 2) |
1521 (frame.content_type & 0x3);
9aaf880e
FE		 1522 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1523
1524 /* AVI Data Bytes 6-13 */
d4ac4cb6
RK		 1525 hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);
1526 hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1);
1527 hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);
1528 hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1);
1529 hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);
1530 hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1);
1531 hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);
1532 hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
9aaf880e
FE		 1533}
1534
9aa1eca0
NY		 1535static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi,
1536 struct drm_display_mode *mode)
1537{
1538 struct hdmi_vendor_infoframe frame;
1539 u8 buffer[10];
1540 ssize_t err;
1541
f1781e9b
VS		 1542 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame,
1543 &hdmi->connector,
1544 mode);
9aa1eca0
NY		 1545 if (err < 0)
1546 /*
1547 * Going into that statement does not means vendor infoframe
1548 * fails. It just informed us that vendor infoframe is not
1549 * needed for the selected mode. Only 4k or stereoscopic 3D
1550 * mode requires vendor infoframe. So just simply return.
1551 */
1552 return;
1553
1554 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
1555 if (err < 0) {
1556 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n",
1557 err);
1558 return;
1559 }
1560 hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
1561 HDMI_FC_DATAUTO0_VSD_MASK);
1562
1563 /* Set the length of HDMI vendor specific InfoFrame payload */
1564 hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE);
1565
1566 /* Set 24bit IEEE Registration Identifier */
1567 hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0);
1568 hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1);
1569 hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2);
1570
1571 /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */
1572 hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0);
1573 hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1);
1574
1575 if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF)
1576 hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2);
1577
1578 /* Packet frame interpolation */
1579 hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1);
1580
1581 /* Auto packets per frame and line spacing */
1582 hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2);
1583
1584 /* Configures the Frame Composer On RDRB mode */
1585 hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
1586 HDMI_FC_DATAUTO0_VSD_MASK);
1587}
1588
b21f4b65 1589static void hdmi_av_composer(struct dw_hdmi *hdmi,
9aaf880e
FE		 1590 const struct drm_display_mode *mode)
1591{
264fce6c
NA		 1592 u8 inv_val, bytes;
1593 struct drm_hdmi_info *hdmi_info = &hdmi->connector.display_info.hdmi;
9aaf880e
FE		 1594 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1595 int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
ba9877e2 1596 unsigned int vdisplay, hdisplay;
9aaf880e 1597
ba9877e2 1598 vmode->mtmdsclock = vmode->mpixelclock = mode->clock * 1000;
9aaf880e
FE		 1599
1600 dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1601
ba9877e2
NA		 1602 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
1603 vmode->mtmdsclock /= 2;
1604
9aaf880e 1605 /* Set up HDMI_FC_INVIDCONF */
264fce6c 1606 inv_val = (hdmi->hdmi_data.hdcp_enable ||
836f90f9
NA		 1607 (dw_hdmi_support_scdc(hdmi) &&
1608 (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK ||
1609 hdmi_info->scdc.scrambling.low_rates)) ?
9aaf880e
FE		 1610 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1611 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1612
b91eee8c 1613 inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
9aaf880e 1614 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
b91eee8c 1615 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW;
9aaf880e 1616
b91eee8c 1617 inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
9aaf880e 1618 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
b91eee8c 1619 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW;
9aaf880e
FE		 1620
1621 inv_val |= (vmode->mdataenablepolarity ?
1622 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1623 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1624
1625 if (hdmi->vic == 39)
1626 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1627 else
b91eee8c 1628 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
9aaf880e 1629 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
b91eee8c 1630 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
9aaf880e 1631
b91eee8c 1632 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
9aaf880e 1633 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
b91eee8c 1634 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
9aaf880e 1635
05b1342f
RK		 1636 inv_val |= hdmi->sink_is_hdmi ?
1637 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
1638 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE;
9aaf880e
FE		 1639
1640 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1641
ba9877e2
NA		 1642 hdisplay = mode->hdisplay;
1643 hblank = mode->htotal - mode->hdisplay;
1644 h_de_hs = mode->hsync_start - mode->hdisplay;
1645 hsync_len = mode->hsync_end - mode->hsync_start;
1646
1647 /*
1648 * When we're setting a YCbCr420 mode, we need
1649 * to adjust the horizontal timing to suit.
1650 */
1651 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) {
1652 hdisplay /= 2;
1653 hblank /= 2;
1654 h_de_hs /= 2;
1655 hsync_len /= 2;
1656 }
1657
e80b9f4e
RK		 1658 vdisplay = mode->vdisplay;
1659 vblank = mode->vtotal - mode->vdisplay;
1660 v_de_vs = mode->vsync_start - mode->vdisplay;
1661 vsync_len = mode->vsync_end - mode->vsync_start;
1662
1663 /*
1664 * When we're setting an interlaced mode, we need
1665 * to adjust the vertical timing to suit.
1666 */
1667 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1668 vdisplay /= 2;
1669 vblank /= 2;
1670 v_de_vs /= 2;
1671 vsync_len /= 2;
1672 }
1673
264fce6c 1674 /* Scrambling Control */
836f90f9 1675 if (dw_hdmi_support_scdc(hdmi)) {
ba9877e2 1676 if (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK ||
264fce6c
NA		 1677 hdmi_info->scdc.scrambling.low_rates) {
1678 /*
1679 * HDMI2.0 Specifies the following procedure:
1680 * After the Source Device has determined that
1681 * SCDC_Present is set (=1), the Source Device should
1682 * write the accurate Version of the Source Device
1683 * to the Source Version field in the SCDCS.
1684 * Source Devices compliant shall set the
1685 * Source Version = 1.
1686 */
1687 drm_scdc_readb(&hdmi->i2c->adap, SCDC_SINK_VERSION,
1688 &bytes);
1689 drm_scdc_writeb(&hdmi->i2c->adap, SCDC_SOURCE_VERSION,
1690 min_t(u8, bytes, SCDC_MIN_SOURCE_VERSION));
1691
1692 /* Enabled Scrambling in the Sink */
1693 drm_scdc_set_scrambling(&hdmi->i2c->adap, 1);
1694
1695 /*
1696 * To activate the scrambler feature, you must ensure
1697 * that the quasi-static configuration bit
1698 * fc_invidconf.HDCP_keepout is set at configuration
1699 * time, before the required mc_swrstzreq.tmdsswrst_req
1700 * reset request is issued.
1701 */
1702 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
1703 HDMI_MC_SWRSTZ);
1704 hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL);
1705 } else {
1706 hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL);
1707 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
1708 HDMI_MC_SWRSTZ);
1709 drm_scdc_set_scrambling(&hdmi->i2c->adap, 0);
1710 }
1711 }
1712
9aaf880e 1713 /* Set up horizontal active pixel width */
ba9877e2
NA		 1714 hdmi_writeb(hdmi, hdisplay >> 8, HDMI_FC_INHACTV1);
1715 hdmi_writeb(hdmi, hdisplay, HDMI_FC_INHACTV0);
9aaf880e
FE		 1716
1717 /* Set up vertical active lines */
e80b9f4e
RK		 1718 hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1);
1719 hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0);
9aaf880e
FE		 1720
1721 /* Set up horizontal blanking pixel region width */
9aaf880e
FE		 1722 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1723 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1724
1725 /* Set up vertical blanking pixel region width */
9aaf880e
FE		 1726 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1727
1728 /* Set up HSYNC active edge delay width (in pixel clks) */
9aaf880e
FE		 1729 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1730 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1731
1732 /* Set up VSYNC active edge delay (in lines) */
9aaf880e
FE		 1733 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1734
1735 /* Set up HSYNC active pulse width (in pixel clks) */
9aaf880e
FE		 1736 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1737 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1738
1739 /* Set up VSYNC active edge delay (in lines) */
9aaf880e
FE		 1740 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1741}
1742
9aaf880e 1743/* HDMI Initialization Step B.4 */
b21f4b65 1744static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
9aaf880e 1745{
9aaf880e
FE		 1746 /* control period minimum duration */
1747 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1748 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1749 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1750
1751 /* Set to fill TMDS data channels */
1752 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1753 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1754 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1755
1756 /* Enable pixel clock and tmds data path */
7cc4ab22
RK		 1757 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_HDCPCLK_DISABLE |
1758 HDMI_MC_CLKDIS_CSCCLK_DISABLE |
1759 HDMI_MC_CLKDIS_AUDCLK_DISABLE |
1760 HDMI_MC_CLKDIS_PREPCLK_DISABLE |
1761 HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1762 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1763 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
9aaf880e 1764
7cc4ab22
RK		 1765 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1766 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
9aaf880e
FE		 1767
1768 /* Enable csc path */
1769 if (is_color_space_conversion(hdmi)) {
7cc4ab22
RK		 1770 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1771 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
9aaf880e 1772 }
8b9e1c0d 1773
14247d7c
NA		 1774 /* Enable color space conversion if needed */
1775 if (is_color_space_conversion(hdmi))
8b9e1c0d
LP		 1776 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH,
1777 HDMI_MC_FLOWCTRL);
1778 else
1779 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS,
1780 HDMI_MC_FLOWCTRL);
9aaf880e
FE		 1781}
1782
9aaf880e 1783/* Workaround to clear the overflow condition */
b21f4b65 1784static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
9aaf880e 1785{
be41fc55
LP		 1786 unsigned int count;
1787 unsigned int i;
9aaf880e
FE		 1788 u8 val;
1789
be41fc55
LP		 1790 /*
1791 * Under some circumstances the Frame Composer arithmetic unit can miss
1792 * an FC register write due to being busy processing the previous one.
1793 * The issue can be worked around by issuing a TMDS software reset and
1794 * then write one of the FC registers several times.
1795 *
1796 * The number of iterations matters and depends on the HDMI TX revision
46d1b42b
JS		 1797 * (and possibly on the platform). So far i.MX6Q (v1.30a), i.MX6DL
1798 * (v1.31a) and multiple Allwinner SoCs (v1.32a) have been identified
1799 * as needing the workaround, with 4 iterations for v1.30a and 1
1800 * iteration for others.
9c305eb4
NA		 1801 * The Amlogic Meson GX SoCs (v2.01a) have been identified as needing
1802 * the workaround with a single iteration.
be41fc55 1803 */
9aaf880e 1804
be41fc55
LP		 1805 switch (hdmi->version) {
1806 case 0x130a:
1807 count = 4;
1808 break;
1809 case 0x131a:
46d1b42b 1810 case 0x132a:
9c305eb4 1811 case 0x201a:
c8c78ac2 1812 case 0x212a:
be41fc55
LP		 1813 count = 1;
1814 break;
1815 default:
9aaf880e
FE		 1816 return;
1817 }
1818
be41fc55
LP		 1819 /* TMDS software reset */
1820 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1821
1822 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
1823 for (i = 0; i < count; i++)
9aaf880e
FE		 1824 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1825}
1826
b21f4b65 1827static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
9aaf880e
FE		 1828{
1829 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1830 HDMI_IH_MUTE_FC_STAT2);
1831}
1832
b21f4b65 1833static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
9aaf880e
FE		 1834{
1835 int ret;
1836
1837 hdmi_disable_overflow_interrupts(hdmi);
1838
1839 hdmi->vic = drm_match_cea_mode(mode);
1840
1841 if (!hdmi->vic) {
1842 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
9aaf880e
FE		 1843 } else {
1844 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
9aaf880e
FE		 1845 }
1846
1847 if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
b5878339
AY		 1848 (hdmi->vic == 21) || (hdmi->vic == 22) ||
1849 (hdmi->vic == 2) || (hdmi->vic == 3) ||
1850 (hdmi->vic == 17) || (hdmi->vic == 18))
def23aa7 1851 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601;
9aaf880e 1852 else
def23aa7 1853 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709;
9aaf880e 1854
d10ca826 1855 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
9aaf880e
FE		 1856 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
1857
def23aa7 1858 /* TOFIX: Get input format from plat data or fallback to RGB888 */
e20c29aa 1859 if (hdmi->plat_data->input_bus_format)
def23aa7
NA		 1860 hdmi->hdmi_data.enc_in_bus_format =
1861 hdmi->plat_data->input_bus_format;
1862 else
1863 hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
1864
1865 /* TOFIX: Get input encoding from plat data or fallback to none */
e20c29aa 1866 if (hdmi->plat_data->input_bus_encoding)
def23aa7
NA		 1867 hdmi->hdmi_data.enc_in_encoding =
1868 hdmi->plat_data->input_bus_encoding;
1869 else
1870 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT;
9aaf880e 1871
def23aa7
NA		 1872 /* TOFIX: Default to RGB888 output format */
1873 hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
9aaf880e 1874
9aaf880e
FE		 1875 hdmi->hdmi_data.pix_repet_factor = 0;
1876 hdmi->hdmi_data.hdcp_enable = 0;
1877 hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
1878
1879 /* HDMI Initialization Step B.1 */
1880 hdmi_av_composer(hdmi, mode);
1881
1882 /* HDMI Initializateion Step B.2 */
f1585f6e 1883 ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data, &hdmi->previous_mode);
9aaf880e
FE		 1884 if (ret)
1885 return ret;
f1585f6e 1886 hdmi->phy.enabled = true;
9aaf880e
FE		 1887
1888 /* HDMI Initialization Step B.3 */
b21f4b65 1889 dw_hdmi_enable_video_path(hdmi);
9aaf880e 1890
f709ec07
RK		 1891 if (hdmi->sink_has_audio) {
1892 dev_dbg(hdmi->dev, "sink has audio support\n");
9aaf880e
FE		 1893
1894 /* HDMI Initialization Step E - Configure audio */
1895 hdmi_clk_regenerator_update_pixel_clock(hdmi);
57fbc055 1896 hdmi_enable_audio_clk(hdmi, true);
f709ec07
RK		 1897 }
1898
1899 /* not for DVI mode */
1900 if (hdmi->sink_is_hdmi) {
1901 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
9aaf880e
FE		 1902
1903 /* HDMI Initialization Step F - Configure AVI InfoFrame */
d4ac4cb6 1904 hdmi_config_AVI(hdmi, mode);
9aa1eca0 1905 hdmi_config_vendor_specific_infoframe(hdmi, mode);
05b1342f
RK		 1906 } else {
1907 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
9aaf880e
FE		 1908 }
1909
1910 hdmi_video_packetize(hdmi);
1911 hdmi_video_csc(hdmi);
1912 hdmi_video_sample(hdmi);
1913 hdmi_tx_hdcp_config(hdmi);
1914
b21f4b65 1915 dw_hdmi_clear_overflow(hdmi);
9aaf880e
FE		 1916
1917 return 0;
1918}
1919
a23d6265 1920static void dw_hdmi_setup_i2c(struct dw_hdmi *hdmi)
9aaf880e
FE		 1921{
1922 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
1923 HDMI_PHY_I2CM_INT_ADDR);
1924
1925 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
1926 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
1927 HDMI_PHY_I2CM_CTLINT_ADDR);
9aaf880e
FE		 1928}
1929
b21f4b65 1930static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
9aaf880e
FE		 1931{
1932 u8 ih_mute;
1933
1934 /*
1935 * Boot up defaults are:
1936 * HDMI_IH_MUTE = 0x03 (disabled)
1937 * HDMI_IH_MUTE_* = 0x00 (enabled)
1938 *
1939 * Disable top level interrupt bits in HDMI block
1940 */
1941 ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
1942 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1943 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
1944
1945 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1946
1947 /* by default mask all interrupts */
1948 hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
1949 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
1950 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
1951 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
1952 hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
1953 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
1954 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
1955 hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
1956 hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
1957 hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
1958 hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
1959 hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
9aaf880e
FE		 1960 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
1961 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
1962
1963 /* Disable interrupts in the IH_MUTE_* registers */
1964 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
1965 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
1966 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
1967 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
1968 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
1969 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
1970 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
1971 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
1972 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
1973 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
1974
1975 /* Enable top level interrupt bits in HDMI block */
1976 ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1977 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
1978 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1979}
1980
b21f4b65 1981static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
9aaf880e 1982{
381f05a7 1983 hdmi->bridge_is_on = true;
b21f4b65 1984 dw_hdmi_setup(hdmi, &hdmi->previous_mode);
9aaf880e
FE		 1985}
1986
b21f4b65 1987static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
9aaf880e 1988{
f1585f6e
LP		 1989 if (hdmi->phy.enabled) {
1990 hdmi->phy.ops->disable(hdmi, hdmi->phy.data);
1991 hdmi->phy.enabled = false;
1992 }
1993
381f05a7
RK		 1994 hdmi->bridge_is_on = false;
1995}
1996
1997static void dw_hdmi_update_power(struct dw_hdmi *hdmi)
1998{
1999 int force = hdmi->force;
2000
2001 if (hdmi->disabled) {
2002 force = DRM_FORCE_OFF;
2003 } else if (force == DRM_FORCE_UNSPECIFIED) {
aeac23bd 2004 if (hdmi->rxsense)
381f05a7
RK		 2005 force = DRM_FORCE_ON;
2006 else
2007 force = DRM_FORCE_OFF;
2008 }
2009
2010 if (force == DRM_FORCE_OFF) {
2011 if (hdmi->bridge_is_on)
2012 dw_hdmi_poweroff(hdmi);
2013 } else {
2014 if (!hdmi->bridge_is_on)
2015 dw_hdmi_poweron(hdmi);
2016 }
9aaf880e
FE		 2017}
2018
aeac23bd
RK		 2019/*
2020 * Adjust the detection of RXSENSE according to whether we have a forced
2021 * connection mode enabled, or whether we have been disabled. There is
2022 * no point processing RXSENSE interrupts if we have a forced connection
2023 * state, or DRM has us disabled.
2024 *
2025 * We also disable rxsense interrupts when we think we're disconnected
2026 * to avoid floating TDMS signals giving false rxsense interrupts.
2027 *
2028 * Note: we still need to listen for HPD interrupts even when DRM has us
2029 * disabled so that we can detect a connect event.
2030 */
2031static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi)
2032{
386d3299
NA		 2033 if (hdmi->phy.ops->update_hpd)
2034 hdmi->phy.ops->update_hpd(hdmi, hdmi->phy.data,
2035 hdmi->force, hdmi->disabled,
2036 hdmi->rxsense);
a23d6265
LP		 2037}
2038
b21f4b65
AY		 2039static enum drm_connector_status
2040dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
9aaf880e 2041{
b21f4b65 2042 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
d94905e0 2043 connector);
98dbeada 2044
381f05a7
RK		 2045 mutex_lock(&hdmi->mutex);
2046 hdmi->force = DRM_FORCE_UNSPECIFIED;
2047 dw_hdmi_update_power(hdmi);
aeac23bd 2048 dw_hdmi_update_phy_mask(hdmi);
381f05a7
RK		 2049 mutex_unlock(&hdmi->mutex);
2050
f1585f6e 2051 return hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data);
9aaf880e
FE		 2052}
2053
b21f4b65 2054static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
9aaf880e 2055{
b21f4b65 2056 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
9aaf880e
FE		 2057 connector);
2058 struct edid *edid;
6c7e66e6 2059 int ret = 0;
9aaf880e
FE		 2060
2061 if (!hdmi->ddc)
2062 return 0;
2063
2064 edid = drm_get_edid(connector, hdmi->ddc);
2065 if (edid) {
2066 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
2067 edid->width_cm, edid->height_cm);
2068
05b1342f 2069 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
f709ec07 2070 hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
c555f023 2071 drm_connector_update_edid_property(connector, edid);
e84b8d75 2072 cec_notifier_set_phys_addr_from_edid(hdmi->cec_notifier, edid);
9aaf880e
FE		 2073 ret = drm_add_edid_modes(connector, edid);
2074 kfree(edid);
2075 } else {
2076 dev_dbg(hdmi->dev, "failed to get edid\n");
2077 }
2078
6c7e66e6 2079 return ret;
9aaf880e
FE		 2080}
2081
381f05a7
RK		 2082static void dw_hdmi_connector_force(struct drm_connector *connector)
2083{
2084 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2085 connector);
2086
2087 mutex_lock(&hdmi->mutex);
2088 hdmi->force = connector->force;
2089 dw_hdmi_update_power(hdmi);
aeac23bd 2090 dw_hdmi_update_phy_mask(hdmi);
381f05a7
RK		 2091 mutex_unlock(&hdmi->mutex);
2092}
2093
dae91e4d 2094static const struct drm_connector_funcs dw_hdmi_connector_funcs = {
2c5b2ccc
MY		 2095 .fill_modes = drm_helper_probe_single_connector_modes,
2096 .detect = dw_hdmi_connector_detect,
fdd8326a 2097 .destroy = drm_connector_cleanup,
2c5b2ccc
MY		 2098 .force = dw_hdmi_connector_force,
2099 .reset = drm_atomic_helper_connector_reset,
2100 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
2101 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2102};
2103
dae91e4d 2104static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
b21f4b65 2105 .get_modes = dw_hdmi_connector_get_modes,
9aaf880e
FE		 2106};
2107
d2ae94ae
LP		 2108static int dw_hdmi_bridge_attach(struct drm_bridge *bridge)
2109{
2110 struct dw_hdmi *hdmi = bridge->driver_private;
2111 struct drm_encoder *encoder = bridge->encoder;
2112 struct drm_connector *connector = &hdmi->connector;
2113
2114 connector->interlace_allowed = 1;
2115 connector->polled = DRM_CONNECTOR_POLL_HPD;
2116
2117 drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs);
2118
2119 drm_connector_init(bridge->dev, connector, &dw_hdmi_connector_funcs,
2120 DRM_MODE_CONNECTOR_HDMIA);
2121
cde4c44d 2122 drm_connector_attach_encoder(connector, encoder);
d2ae94ae
LP		 2123
2124 return 0;
2125}
2126
b0febde7
JA		 2127static enum drm_mode_status
2128dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge,
2129 const struct drm_display_mode *mode)
6ce2ca58
RP		 2130{
2131 struct dw_hdmi *hdmi = bridge->driver_private;
2132 struct drm_connector *connector = &hdmi->connector;
b0febde7 2133 enum drm_mode_status mode_status = MODE_OK;
6ce2ca58 2134
b0febde7
JA		 2135 /* We don't support double-clocked modes */
2136 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
2137 return MODE_BAD;
2138
2139 if (hdmi->plat_data->mode_valid)
2140 mode_status = hdmi->plat_data->mode_valid(connector, mode);
2141
2142 return mode_status;
6ce2ca58
RP		 2143}
2144
fd30b38c 2145static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
63f8f3ba
LP		 2146 const struct drm_display_mode *orig_mode,
2147 const struct drm_display_mode *mode)
fd30b38c
LP		 2148{
2149 struct dw_hdmi *hdmi = bridge->driver_private;
2150
2151 mutex_lock(&hdmi->mutex);
2152
2153 /* Store the display mode for plugin/DKMS poweron events */
2154 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
2155
2156 mutex_unlock(&hdmi->mutex);
2157}
2158
2159static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
2160{
2161 struct dw_hdmi *hdmi = bridge->driver_private;
2162
2163 mutex_lock(&hdmi->mutex);
2164 hdmi->disabled = true;
2165 dw_hdmi_update_power(hdmi);
2166 dw_hdmi_update_phy_mask(hdmi);
2167 mutex_unlock(&hdmi->mutex);
2168}
2169
2170static void dw_hdmi_bridge_enable(struct drm_bridge *bridge)
2171{
2172 struct dw_hdmi *hdmi = bridge->driver_private;
2173
2174 mutex_lock(&hdmi->mutex);
2175 hdmi->disabled = false;
2176 dw_hdmi_update_power(hdmi);
2177 dw_hdmi_update_phy_mask(hdmi);
2178 mutex_unlock(&hdmi->mutex);
2179}
2180
dae91e4d 2181static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
d2ae94ae 2182 .attach = dw_hdmi_bridge_attach,
b21f4b65
AY		 2183 .enable = dw_hdmi_bridge_enable,
2184 .disable = dw_hdmi_bridge_disable,
b21f4b65 2185 .mode_set = dw_hdmi_bridge_mode_set,
b0febde7 2186 .mode_valid = dw_hdmi_bridge_mode_valid,
3d1b35a3
AY		 2187};
2188
3efc2fa3
VZ		 2189static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi)
2190{
2191 struct dw_hdmi_i2c *i2c = hdmi->i2c;
2192 unsigned int stat;
2193
2194 stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0);
2195 if (!stat)
2196 return IRQ_NONE;
2197
2198 hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0);
2199
2200 i2c->stat = stat;
2201
2202 complete(&i2c->cmp);
2203
2204 return IRQ_HANDLED;
2205}
2206
b21f4b65 2207static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
d94905e0 2208{
b21f4b65 2209 struct dw_hdmi *hdmi = dev_id;
d94905e0 2210 u8 intr_stat;
3efc2fa3
VZ		 2211 irqreturn_t ret = IRQ_NONE;
2212
2213 if (hdmi->i2c)
2214 ret = dw_hdmi_i2c_irq(hdmi);
d94905e0
RK		 2215
2216 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
3efc2fa3 2217 if (intr_stat) {
d94905e0 2218 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
3efc2fa3
VZ		 2219 return IRQ_WAKE_THREAD;
2220 }
d94905e0 2221
3efc2fa3 2222 return ret;
d94905e0
RK		 2223}
2224
c32048d9 2225void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense)
386d3299
NA		 2226{
2227 mutex_lock(&hdmi->mutex);
2228
2229 if (!hdmi->force) {
2230 /*
2231 * If the RX sense status indicates we're disconnected,
2232 * clear the software rxsense status.
2233 */
2234 if (!rx_sense)
2235 hdmi->rxsense = false;
2236
2237 /*
2238 * Only set the software rxsense status when both
2239 * rxsense and hpd indicates we're connected.
2240 * This avoids what seems to be bad behaviour in
2241 * at least iMX6S versions of the phy.
2242 */
2243 if (hpd)
2244 hdmi->rxsense = true;
2245
2246 dw_hdmi_update_power(hdmi);
2247 dw_hdmi_update_phy_mask(hdmi);
2248 }
2249 mutex_unlock(&hdmi->mutex);
2250}
386d3299
NA		 2251EXPORT_SYMBOL_GPL(dw_hdmi_setup_rx_sense);
2252
b21f4b65 2253static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
9aaf880e 2254{
b21f4b65 2255 struct dw_hdmi *hdmi = dev_id;
aeac23bd 2256 u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat;
9aaf880e
FE		 2257
2258 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
9aaf880e 2259 phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
aeac23bd
RK		 2260 phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0);
2261
2262 phy_pol_mask = 0;
2263 if (intr_stat & HDMI_IH_PHY_STAT0_HPD)
2264 phy_pol_mask |= HDMI_PHY_HPD;
2265 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0)
2266 phy_pol_mask |= HDMI_PHY_RX_SENSE0;
2267 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1)
2268 phy_pol_mask |= HDMI_PHY_RX_SENSE1;
2269 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2)
2270 phy_pol_mask |= HDMI_PHY_RX_SENSE2;
2271 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3)
2272 phy_pol_mask |= HDMI_PHY_RX_SENSE3;
2273
2274 if (phy_pol_mask)
2275 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0);
9aaf880e 2276
aeac23bd
RK		 2277 /*
2278 * RX sense tells us whether the TDMS transmitters are detecting
2279 * load - in other words, there's something listening on the
2280 * other end of the link. Use this to decide whether we should
2281 * power on the phy as HPD may be toggled by the sink to merely
2282 * ask the source to re-read the EDID.
2283 */
2284 if (intr_stat &
e84b8d75 2285 (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) {
c32048d9
NA		 2286 dw_hdmi_setup_rx_sense(hdmi,
2287 phy_stat & HDMI_PHY_HPD,
2288 phy_stat & HDMI_PHY_RX_SENSE);
aeac23bd 2289
e84b8d75
RK		 2290 if ((phy_stat & (HDMI_PHY_RX_SENSE | HDMI_PHY_HPD)) == 0)
2291 cec_notifier_set_phys_addr(hdmi->cec_notifier,
2292 CEC_PHYS_ADDR_INVALID);
2293 }
2294
aeac23bd
RK		 2295 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
2296 dev_dbg(hdmi->dev, "EVENT=%s\n",
2297 phy_int_pol & HDMI_PHY_HPD ? "plugin" : "plugout");
ba5d7e61
LP		 2298 if (hdmi->bridge.dev)
2299 drm_helper_hpd_irq_event(hdmi->bridge.dev);
9aaf880e
FE		 2300 }
2301
2302 hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
aeac23bd
RK		 2303 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
2304 HDMI_IH_MUTE_PHY_STAT0);
9aaf880e
FE		 2305
2306 return IRQ_HANDLED;
2307}
2308
faba6c3c
LP		 2309static const struct dw_hdmi_phy_data dw_hdmi_phys[] = {
2310 {
2311 .type = DW_HDMI_PHY_DWC_HDMI_TX_PHY,
2312 .name = "DWC HDMI TX PHY",
b0e583e5 2313 .gen = 1,
faba6c3c
LP		 2314 }, {
2315 .type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC,
2316 .name = "DWC MHL PHY + HEAC PHY",
b0e583e5 2317 .gen = 2,
faba6c3c 2318 .has_svsret = true,
2ef9dfed 2319 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
faba6c3c
LP		 2320 }, {
2321 .type = DW_HDMI_PHY_DWC_MHL_PHY,
2322 .name = "DWC MHL PHY",
b0e583e5 2323 .gen = 2,
faba6c3c 2324 .has_svsret = true,
2ef9dfed 2325 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
faba6c3c
LP		 2326 }, {
2327 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC,
2328 .name = "DWC HDMI 3D TX PHY + HEAC PHY",
b0e583e5 2329 .gen = 2,
2ef9dfed 2330 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
faba6c3c
LP		 2331 }, {
2332 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY,
2333 .name = "DWC HDMI 3D TX PHY",
b0e583e5 2334 .gen = 2,
2ef9dfed 2335 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
faba6c3c
LP		 2336 }, {
2337 .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY,
2338 .name = "DWC HDMI 2.0 TX PHY",
b0e583e5 2339 .gen = 2,
faba6c3c 2340 .has_svsret = true,
c93f6092 2341 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2ef9dfed
KB		 2342 }, {
2343 .type = DW_HDMI_PHY_VENDOR_PHY,
2344 .name = "Vendor PHY",
faba6c3c
LP		 2345 }
2346};
2347
2348static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi)
2349{
2350 unsigned int i;
2351 u8 phy_type;
2352
8faff374
HS		 2353 phy_type = hdmi->plat_data->phy_force_vendor ?
2354 DW_HDMI_PHY_VENDOR_PHY :
2355 hdmi_readb(hdmi, HDMI_CONFIG2_ID);
faba6c3c 2356
f1585f6e
LP		 2357 if (phy_type == DW_HDMI_PHY_VENDOR_PHY) {
2358 /* Vendor PHYs require support from the glue layer. */
2359 if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) {
2360 dev_err(hdmi->dev,
2361 "Vendor HDMI PHY not supported by glue layer\n");
2362 return -ENODEV;
2363 }
2364
2365 hdmi->phy.ops = hdmi->plat_data->phy_ops;
2366 hdmi->phy.data = hdmi->plat_data->phy_data;
2367 hdmi->phy.name = hdmi->plat_data->phy_name;
2368 return 0;
2369 }
2370
2371 /* Synopsys PHYs are handled internally. */
faba6c3c
LP		 2372 for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) {
2373 if (dw_hdmi_phys[i].type == phy_type) {
f1585f6e
LP		 2374 hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops;
2375 hdmi->phy.name = dw_hdmi_phys[i].name;
2376 hdmi->phy.data = (void *)&dw_hdmi_phys[i];
2ef9dfed
KB		 2377
2378 if (!dw_hdmi_phys[i].configure &&
2379 !hdmi->plat_data->configure_phy) {
2380 dev_err(hdmi->dev, "%s requires platform support\n",
2381 hdmi->phy.name);
2382 return -ENODEV;
2383 }
2384
faba6c3c
LP		 2385 return 0;
2386 }
2387 }
2388
f1585f6e 2389 dev_err(hdmi->dev, "Unsupported HDMI PHY type (%02x)\n", phy_type);
faba6c3c
LP		 2390 return -ENODEV;
2391}
2392
a616e63c
RK		 2393static void dw_hdmi_cec_enable(struct dw_hdmi *hdmi)
2394{
2395 mutex_lock(&hdmi->mutex);
2396 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CECCLK_DISABLE;
2397 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2398 mutex_unlock(&hdmi->mutex);
2399}
2400
2401static void dw_hdmi_cec_disable(struct dw_hdmi *hdmi)
2402{
2403 mutex_lock(&hdmi->mutex);
2404 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CECCLK_DISABLE;
2405 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2406 mutex_unlock(&hdmi->mutex);
2407}
2408
2409static const struct dw_hdmi_cec_ops dw_hdmi_cec_ops = {
2410 .write = hdmi_writeb,
2411 .read = hdmi_readb,
2412 .enable = dw_hdmi_cec_enable,
2413 .disable = dw_hdmi_cec_disable,
2414};
2415
80e2f979
NA		 2416static const struct regmap_config hdmi_regmap_8bit_config = {
2417 .reg_bits = 32,
2418 .val_bits = 8,
2419 .reg_stride = 1,
2420 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR,
2421};
2422
2423static const struct regmap_config hdmi_regmap_32bit_config = {
2424 .reg_bits = 32,
2425 .val_bits = 32,
2426 .reg_stride = 4,
2427 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR << 2,
2428};
2429
69497eb9
LP		 2430static struct dw_hdmi *
2431__dw_hdmi_probe(struct platform_device *pdev,
2432 const struct dw_hdmi_plat_data *plat_data)
9aaf880e 2433{
c608119d 2434 struct device *dev = &pdev->dev;
17b5001b 2435 struct device_node *np = dev->of_node;
7ed6c665 2436 struct platform_device_info pdevinfo;
9aaf880e 2437 struct device_node *ddc_node;
a616e63c 2438 struct dw_hdmi_cec_data cec;
b21f4b65 2439 struct dw_hdmi *hdmi;
80e2f979 2440 struct resource *iores = NULL;
c608119d 2441 int irq;
3d1b35a3 2442 int ret;
0cd9d142 2443 u32 val = 1;
0527e12e
LP		 2444 u8 prod_id0;
2445 u8 prod_id1;
2761ba6c 2446 u8 config0;
0c674948 2447 u8 config3;
9aaf880e 2448
17b5001b 2449 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
9aaf880e 2450 if (!hdmi)
69497eb9 2451 return ERR_PTR(-ENOMEM);
9aaf880e 2452
3d1b35a3 2453 hdmi->plat_data = plat_data;
17b5001b 2454 hdmi->dev = dev;
40678388 2455 hdmi->sample_rate = 48000;
b872a8e1 2456 hdmi->disabled = true;
aeac23bd
RK		 2457 hdmi->rxsense = true;
2458 hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE);
7cc4ab22 2459 hdmi->mc_clkdis = 0x7f;
9aaf880e 2460
b872a8e1 2461 mutex_init(&hdmi->mutex);
6bcf4953 2462 mutex_init(&hdmi->audio_mutex);
b90120a9 2463 spin_lock_init(&hdmi->audio_lock);
6bcf4953 2464
b5d45901 2465 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
9aaf880e 2466 if (ddc_node) {
9f04a1f2 2467 hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node);
c2c38488
AY		 2468 of_node_put(ddc_node);
2469 if (!hdmi->ddc) {
9aaf880e 2470 dev_dbg(hdmi->dev, "failed to read ddc node\n");
69497eb9 2471 return ERR_PTR(-EPROBE_DEFER);
c2c38488 2472 }
9aaf880e 2473
9aaf880e
FE		 2474 } else {
2475 dev_dbg(hdmi->dev, "no ddc property found\n");
2476 }
2477
80e2f979
NA		 2478 if (!plat_data->regm) {
2479 const struct regmap_config *reg_config;
2480
2481 of_property_read_u32(np, "reg-io-width", &val);
2482 switch (val) {
2483 case 4:
2484 reg_config = &hdmi_regmap_32bit_config;
2485 hdmi->reg_shift = 2;
2486 break;
2487 case 1:
2488 reg_config = &hdmi_regmap_8bit_config;
2489 break;
2490 default:
2491 dev_err(dev, "reg-io-width must be 1 or 4\n");
2492 return ERR_PTR(-EINVAL);
2493 }
2494
2495 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2496 hdmi->regs = devm_ioremap_resource(dev, iores);
2497 if (IS_ERR(hdmi->regs)) {
2498 ret = PTR_ERR(hdmi->regs);
2499 goto err_res;
2500 }
2501
2502 hdmi->regm = devm_regmap_init_mmio(dev, hdmi->regs, reg_config);
2503 if (IS_ERR(hdmi->regm)) {
2504 dev_err(dev, "Failed to configure regmap\n");
2505 ret = PTR_ERR(hdmi->regm);
2506 goto err_res;
2507 }
2508 } else {
2509 hdmi->regm = plat_data->regm;
9f04a1f2 2510 }
9aaf880e 2511
9aaf880e
FE		 2512 hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
2513 if (IS_ERR(hdmi->isfr_clk)) {
2514 ret = PTR_ERR(hdmi->isfr_clk);
b5878339 2515 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
9f04a1f2 2516 goto err_res;
9aaf880e
FE		 2517 }
2518
2519 ret = clk_prepare_enable(hdmi->isfr_clk);
2520 if (ret) {
b5878339 2521 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
9f04a1f2 2522 goto err_res;
9aaf880e
FE		 2523 }
2524
2525 hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
2526 if (IS_ERR(hdmi->iahb_clk)) {
2527 ret = PTR_ERR(hdmi->iahb_clk);
b5878339 2528 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
9aaf880e
FE		 2529 goto err_isfr;
2530 }
2531
2532 ret = clk_prepare_enable(hdmi->iahb_clk);
2533 if (ret) {
b5878339 2534 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
9aaf880e
FE		 2535 goto err_isfr;
2536 }
2537
ebe32c3e
PHH		 2538 hdmi->cec_clk = devm_clk_get(hdmi->dev, "cec");
2539 if (PTR_ERR(hdmi->cec_clk) == -ENOENT) {
2540 hdmi->cec_clk = NULL;
2541 } else if (IS_ERR(hdmi->cec_clk)) {
2542 ret = PTR_ERR(hdmi->cec_clk);
2543 if (ret != -EPROBE_DEFER)
2544 dev_err(hdmi->dev, "Cannot get HDMI cec clock: %d\n",
2545 ret);
2546
2547 hdmi->cec_clk = NULL;
2548 goto err_iahb;
2549 } else {
2550 ret = clk_prepare_enable(hdmi->cec_clk);
2551 if (ret) {
2552 dev_err(hdmi->dev, "Cannot enable HDMI cec clock: %d\n",
2553 ret);
2554 goto err_iahb;
2555 }
2556 }
2557
9aaf880e 2558 /* Product and revision IDs */
be41fc55
LP		 2559 hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8)
2560 | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0);
0527e12e
LP		 2561 prod_id0 = hdmi_readb(hdmi, HDMI_PRODUCT_ID0);
2562 prod_id1 = hdmi_readb(hdmi, HDMI_PRODUCT_ID1);
2563
2564 if (prod_id0 != HDMI_PRODUCT_ID0_HDMI_TX ||
2565 (prod_id1 & ~HDMI_PRODUCT_ID1_HDCP) != HDMI_PRODUCT_ID1_HDMI_TX) {
2566 dev_err(dev, "Unsupported HDMI controller (%04x:%02x:%02x)\n",
be41fc55 2567 hdmi->version, prod_id0, prod_id1);
0527e12e
LP		 2568 ret = -ENODEV;
2569 goto err_iahb;
2570 }
2571
faba6c3c
LP		 2572 ret = dw_hdmi_detect_phy(hdmi);
2573 if (ret < 0)
2574 goto err_iahb;
2575
2576 dev_info(dev, "Detected HDMI TX controller v%x.%03x %s HDCP (%s)\n",
be41fc55 2577 hdmi->version >> 12, hdmi->version & 0xfff,
faba6c3c 2578 prod_id1 & HDMI_PRODUCT_ID1_HDCP ? "with" : "without",
f1585f6e 2579 hdmi->phy.name);
9aaf880e
FE		 2580
2581 initialize_hdmi_ih_mutes(hdmi);
2582
c608119d 2583 irq = platform_get_irq(pdev, 0);
69497eb9
LP		 2584 if (irq < 0) {
2585 ret = irq;
c608119d 2586 goto err_iahb;
69497eb9 2587 }
c608119d 2588
639a202c
PZ		 2589 ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
2590 dw_hdmi_irq, IRQF_SHARED,
2591 dev_name(dev), hdmi);
2592 if (ret)
b33ef619 2593 goto err_iahb;
639a202c 2594
e84b8d75
RK		 2595 hdmi->cec_notifier = cec_notifier_get(dev);
2596 if (!hdmi->cec_notifier) {
2597 ret = -ENOMEM;
2598 goto err_iahb;
2599 }
2600
9aaf880e
FE		 2601 /*
2602 * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
2603 * N and cts values before enabling phy
2604 */
2605 hdmi_init_clk_regenerator(hdmi);
2606
3efc2fa3
VZ		 2607 /* If DDC bus is not specified, try to register HDMI I2C bus */
2608 if (!hdmi->ddc) {
2609 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi);
2610 if (IS_ERR(hdmi->ddc))
2611 hdmi->ddc = NULL;
2612 }
2613
69497eb9
LP		 2614 hdmi->bridge.driver_private = hdmi;
2615 hdmi->bridge.funcs = &dw_hdmi_bridge_funcs;
d5ad7843 2616#ifdef CONFIG_OF
69497eb9 2617 hdmi->bridge.of_node = pdev->dev.of_node;
d5ad7843 2618#endif
9aaf880e 2619
a23d6265 2620 dw_hdmi_setup_i2c(hdmi);
386d3299
NA		 2621 if (hdmi->phy.ops->setup_hpd)
2622 hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data);
9aaf880e 2623
7ed6c665
RK		 2624 memset(&pdevinfo, 0, sizeof(pdevinfo));
2625 pdevinfo.parent = dev;
2626 pdevinfo.id = PLATFORM_DEVID_AUTO;
2627
2761ba6c 2628 config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID);
0c674948 2629 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID);
2761ba6c 2630
80e2f979 2631 if (iores && config3 & HDMI_CONFIG3_AHBAUDDMA) {
2761ba6c
KM		 2632 struct dw_hdmi_audio_data audio;
2633
7ed6c665
RK		 2634 audio.phys = iores->start;
2635 audio.base = hdmi->regs;
2636 audio.irq = irq;
2637 audio.hdmi = hdmi;
f5ce4057 2638 audio.eld = hdmi->connector.eld;
a7d555d2
RP		 2639 hdmi->enable_audio = dw_hdmi_ahb_audio_enable;
2640 hdmi->disable_audio = dw_hdmi_ahb_audio_disable;
7ed6c665
RK		 2641
2642 pdevinfo.name = "dw-hdmi-ahb-audio";
2643 pdevinfo.data = &audio;
2644 pdevinfo.size_data = sizeof(audio);
2645 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2646 hdmi->audio = platform_device_register_full(&pdevinfo);
2761ba6c
KM		 2647 } else if (config0 & HDMI_CONFIG0_I2S) {
2648 struct dw_hdmi_i2s_audio_data audio;
2649
2650 audio.hdmi = hdmi;
2651 audio.write = hdmi_writeb;
2652 audio.read = hdmi_readb;
a7d555d2 2653 hdmi->enable_audio = dw_hdmi_i2s_audio_enable;
57fbc055 2654 hdmi->disable_audio = dw_hdmi_i2s_audio_disable;
2761ba6c
KM		 2655
2656 pdevinfo.name = "dw-hdmi-i2s-audio";
2657 pdevinfo.data = &audio;
2658 pdevinfo.size_data = sizeof(audio);
2659 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2660 hdmi->audio = platform_device_register_full(&pdevinfo);
7ed6c665
RK		 2661 }
2662
a616e63c
RK		 2663 if (config0 & HDMI_CONFIG0_CEC) {
2664 cec.hdmi = hdmi;
2665 cec.ops = &dw_hdmi_cec_ops;
2666 cec.irq = irq;
2667
2668 pdevinfo.name = "dw-hdmi-cec";
2669 pdevinfo.data = &cec;
2670 pdevinfo.size_data = sizeof(cec);
2671 pdevinfo.dma_mask = 0;
2672
2673 hdmi->cec = platform_device_register_full(&pdevinfo);
2674 }
2675
3efc2fa3
VZ		 2676 /* Reset HDMI DDC I2C master controller and mute I2CM interrupts */
2677 if (hdmi->i2c)
2678 dw_hdmi_i2c_init(hdmi);
2679
69497eb9 2680 return hdmi;
9aaf880e
FE		 2681
2682err_iahb:
3efc2fa3
VZ		 2683 if (hdmi->i2c) {
2684 i2c_del_adapter(&hdmi->i2c->adap);
2685 hdmi->ddc = NULL;
2686 }
2687
e84b8d75
RK		 2688 if (hdmi->cec_notifier)
2689 cec_notifier_put(hdmi->cec_notifier);
2690
9aaf880e 2691 clk_disable_unprepare(hdmi->iahb_clk);
ebe32c3e
PHH		 2692 if (hdmi->cec_clk)
2693 clk_disable_unprepare(hdmi->cec_clk);
9aaf880e
FE		 2694err_isfr:
2695 clk_disable_unprepare(hdmi->isfr_clk);
9f04a1f2
VZ		 2696err_res:
2697 i2c_put_adapter(hdmi->ddc);
9aaf880e 2698
69497eb9 2699 return ERR_PTR(ret);
9aaf880e
FE		 2700}
2701
69497eb9 2702static void __dw_hdmi_remove(struct dw_hdmi *hdmi)
9aaf880e 2703{
7ed6c665
RK		 2704 if (hdmi->audio && !IS_ERR(hdmi->audio))
2705 platform_device_unregister(hdmi->audio);
a616e63c
RK		 2706 if (!IS_ERR(hdmi->cec))
2707 platform_device_unregister(hdmi->cec);
7ed6c665 2708
d94905e0
RK		 2709 /* Disable all interrupts */
2710 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
2711
e383bf85
HV		 2712 if (hdmi->cec_notifier)
2713 cec_notifier_put(hdmi->cec_notifier);
2714
9aaf880e
FE		 2715 clk_disable_unprepare(hdmi->iahb_clk);
2716 clk_disable_unprepare(hdmi->isfr_clk);
ebe32c3e
PHH		 2717 if (hdmi->cec_clk)
2718 clk_disable_unprepare(hdmi->cec_clk);
3efc2fa3
VZ		 2719
2720 if (hdmi->i2c)
2721 i2c_del_adapter(&hdmi->i2c->adap);
2722 else
2723 i2c_put_adapter(hdmi->ddc);
17b5001b 2724}
69497eb9
LP		 2725
2726/* -----------------------------------------------------------------------------
2727 * Probe/remove API, used from platforms based on the DRM bridge API.
2728 */
eea034af
JS		 2729struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
2730 const struct dw_hdmi_plat_data *plat_data)
69497eb9
LP		 2731{
2732 struct dw_hdmi *hdmi;
69497eb9
LP		 2733
2734 hdmi = __dw_hdmi_probe(pdev, plat_data);
2735 if (IS_ERR(hdmi))
eea034af 2736 return hdmi;
69497eb9 2737
b678682e 2738 drm_bridge_add(&hdmi->bridge);
69497eb9 2739
eea034af 2740 return hdmi;
69497eb9
LP		 2741}
2742EXPORT_SYMBOL_GPL(dw_hdmi_probe);
2743
eea034af 2744void dw_hdmi_remove(struct dw_hdmi *hdmi)
69497eb9 2745{
69497eb9
LP		 2746 drm_bridge_remove(&hdmi->bridge);
2747
2748 __dw_hdmi_remove(hdmi);
2749}
2750EXPORT_SYMBOL_GPL(dw_hdmi_remove);
2751
2752/* -----------------------------------------------------------------------------
2753 * Bind/unbind API, used from platforms based on the component framework.
2754 */
eea034af
JS		 2755struct dw_hdmi *dw_hdmi_bind(struct platform_device *pdev,
2756 struct drm_encoder *encoder,
2757 const struct dw_hdmi_plat_data *plat_data)
69497eb9
LP		 2758{
2759 struct dw_hdmi *hdmi;
2760 int ret;
2761
2762 hdmi = __dw_hdmi_probe(pdev, plat_data);
2763 if (IS_ERR(hdmi))
eea034af 2764 return hdmi;
69497eb9
LP		 2765
2766 ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL);
2767 if (ret) {
eea034af 2768 dw_hdmi_remove(hdmi);
69497eb9 2769 DRM_ERROR("Failed to initialize bridge with drm\n");
eea034af 2770 return ERR_PTR(ret);
69497eb9
LP		 2771 }
2772
eea034af 2773 return hdmi;
69497eb9
LP		 2774}
2775EXPORT_SYMBOL_GPL(dw_hdmi_bind);
2776
eea034af 2777void dw_hdmi_unbind(struct dw_hdmi *hdmi)
69497eb9 2778{
69497eb9
LP		 2779 __dw_hdmi_remove(hdmi);
2780}
b21f4b65 2781EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
9aaf880e
FE		 2782
2783MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
3d1b35a3
AY		 2784MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
2785MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
3efc2fa3 2786MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>");
b21f4b65 2787MODULE_DESCRIPTION("DW HDMI transmitter driver");
9aaf880e 2788MODULE_LICENSE("GPL");
b21f4b65 2789MODULE_ALIAS("platform:dw-hdmi");
Linux 6.x block layer and io_uring tree(s)