Commit | Line | Data |
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bc1aee7f JS |
1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* | |
3 | * Copyright (c) 2016 MediaTek Inc. | |
4 | */ | |
5 | ||
6 | #include <linux/delay.h> | |
7 | #include <linux/err.h> | |
8 | #include <linux/gpio/consumer.h> | |
9 | #include <linux/i2c.h> | |
10 | #include <linux/module.h> | |
11 | #include <linux/of_graph.h> | |
826cff3f | 12 | #include <linux/pm_runtime.h> |
692d8db0 | 13 | #include <linux/regmap.h> |
bc1aee7f JS |
14 | #include <linux/regulator/consumer.h> |
15 | ||
da68386d TZ |
16 | #include <drm/display/drm_dp_aux_bus.h> |
17 | #include <drm/display/drm_dp_helper.h> | |
102e80d1 | 18 | #include <drm/drm_atomic_state_helper.h> |
bc1aee7f | 19 | #include <drm/drm_bridge.h> |
255490f9 | 20 | #include <drm/drm_edid.h> |
bc1aee7f JS |
21 | #include <drm/drm_mipi_dsi.h> |
22 | #include <drm/drm_of.h> | |
23 | #include <drm/drm_panel.h> | |
24 | #include <drm/drm_print.h> | |
25 | ||
13afcdd7 PC |
26 | #define PAGE0_AUXCH_CFG3 0x76 |
27 | #define AUXCH_CFG3_RESET 0xff | |
28 | #define PAGE0_SWAUX_ADDR_7_0 0x7d | |
29 | #define PAGE0_SWAUX_ADDR_15_8 0x7e | |
30 | #define PAGE0_SWAUX_ADDR_23_16 0x7f | |
31 | #define SWAUX_ADDR_MASK GENMASK(19, 0) | |
32 | #define PAGE0_SWAUX_LENGTH 0x80 | |
33 | #define SWAUX_LENGTH_MASK GENMASK(3, 0) | |
34 | #define SWAUX_NO_PAYLOAD BIT(7) | |
35 | #define PAGE0_SWAUX_WDATA 0x81 | |
36 | #define PAGE0_SWAUX_RDATA 0x82 | |
37 | #define PAGE0_SWAUX_CTRL 0x83 | |
38 | #define SWAUX_SEND BIT(0) | |
39 | #define PAGE0_SWAUX_STATUS 0x84 | |
40 | #define SWAUX_M_MASK GENMASK(4, 0) | |
41 | #define SWAUX_STATUS_MASK GENMASK(7, 5) | |
42 | #define SWAUX_STATUS_NACK (0x1 << 5) | |
43 | #define SWAUX_STATUS_DEFER (0x2 << 5) | |
44 | #define SWAUX_STATUS_ACKM (0x3 << 5) | |
45 | #define SWAUX_STATUS_INVALID (0x4 << 5) | |
46 | #define SWAUX_STATUS_I2C_NACK (0x5 << 5) | |
47 | #define SWAUX_STATUS_I2C_DEFER (0x6 << 5) | |
48 | #define SWAUX_STATUS_TIMEOUT (0x7 << 5) | |
49 | ||
bc1aee7f | 50 | #define PAGE2_GPIO_H 0xa7 |
28210a3f | 51 | #define PS_GPIO9 BIT(1) |
bc1aee7f | 52 | #define PAGE2_I2C_BYPASS 0xea |
28210a3f | 53 | #define I2C_BYPASS_EN 0xd0 |
bc1aee7f | 54 | #define PAGE2_MCS_EN 0xf3 |
28210a3f PC |
55 | #define MCS_EN BIT(0) |
56 | ||
bc1aee7f | 57 | #define PAGE3_SET_ADD 0xfe |
28210a3f PC |
58 | #define VDO_CTL_ADD 0x13 |
59 | #define VDO_DIS 0x18 | |
60 | #define VDO_EN 0x1c | |
61 | ||
62 | #define NUM_MIPI_LANES 4 | |
bc1aee7f | 63 | |
692d8db0 PC |
64 | #define COMMON_PS8640_REGMAP_CONFIG \ |
65 | .reg_bits = 8, \ | |
66 | .val_bits = 8, \ | |
67 | .cache_type = REGCACHE_NONE | |
68 | ||
bc1aee7f JS |
69 | /* |
70 | * PS8640 uses multiple addresses: | |
71 | * page[0]: for DP control | |
72 | * page[1]: for VIDEO Bridge | |
73 | * page[2]: for control top | |
74 | * page[3]: for DSI Link Control1 | |
75 | * page[4]: for MIPI Phy | |
76 | * page[5]: for VPLL | |
77 | * page[6]: for DSI Link Control2 | |
78 | * page[7]: for SPI ROM mapping | |
79 | */ | |
80 | enum page_addr_offset { | |
81 | PAGE0_DP_CNTL = 0, | |
82 | PAGE1_VDO_BDG, | |
83 | PAGE2_TOP_CNTL, | |
84 | PAGE3_DSI_CNTL1, | |
85 | PAGE4_MIPI_PHY, | |
86 | PAGE5_VPLL, | |
87 | PAGE6_DSI_CNTL2, | |
88 | PAGE7_SPI_CNTL, | |
89 | MAX_DEVS | |
90 | }; | |
91 | ||
92 | enum ps8640_vdo_control { | |
93 | DISABLE = VDO_DIS, | |
94 | ENABLE = VDO_EN, | |
95 | }; | |
96 | ||
97 | struct ps8640 { | |
98 | struct drm_bridge bridge; | |
99 | struct drm_bridge *panel_bridge; | |
13afcdd7 | 100 | struct drm_dp_aux aux; |
bc1aee7f JS |
101 | struct mipi_dsi_device *dsi; |
102 | struct i2c_client *page[MAX_DEVS]; | |
692d8db0 | 103 | struct regmap *regmap[MAX_DEVS]; |
bc1aee7f JS |
104 | struct regulator_bulk_data supplies[2]; |
105 | struct gpio_desc *gpio_reset; | |
106 | struct gpio_desc *gpio_powerdown; | |
9294914d | 107 | struct device_link *link; |
826cff3f | 108 | bool pre_enabled; |
cb8e30dd | 109 | bool need_post_hpd_delay; |
bc1aee7f JS |
110 | }; |
111 | ||
692d8db0 PC |
112 | static const struct regmap_config ps8640_regmap_config[] = { |
113 | [PAGE0_DP_CNTL] = { | |
114 | COMMON_PS8640_REGMAP_CONFIG, | |
115 | .max_register = 0xbf, | |
116 | }, | |
117 | [PAGE1_VDO_BDG] = { | |
118 | COMMON_PS8640_REGMAP_CONFIG, | |
119 | .max_register = 0xff, | |
120 | }, | |
121 | [PAGE2_TOP_CNTL] = { | |
122 | COMMON_PS8640_REGMAP_CONFIG, | |
123 | .max_register = 0xff, | |
124 | }, | |
125 | [PAGE3_DSI_CNTL1] = { | |
126 | COMMON_PS8640_REGMAP_CONFIG, | |
127 | .max_register = 0xff, | |
128 | }, | |
129 | [PAGE4_MIPI_PHY] = { | |
130 | COMMON_PS8640_REGMAP_CONFIG, | |
131 | .max_register = 0xff, | |
132 | }, | |
133 | [PAGE5_VPLL] = { | |
134 | COMMON_PS8640_REGMAP_CONFIG, | |
135 | .max_register = 0x7f, | |
136 | }, | |
137 | [PAGE6_DSI_CNTL2] = { | |
138 | COMMON_PS8640_REGMAP_CONFIG, | |
139 | .max_register = 0xff, | |
140 | }, | |
141 | [PAGE7_SPI_CNTL] = { | |
142 | COMMON_PS8640_REGMAP_CONFIG, | |
143 | .max_register = 0xff, | |
144 | }, | |
145 | }; | |
146 | ||
bc1aee7f JS |
147 | static inline struct ps8640 *bridge_to_ps8640(struct drm_bridge *e) |
148 | { | |
149 | return container_of(e, struct ps8640, bridge); | |
150 | } | |
151 | ||
13afcdd7 PC |
152 | static inline struct ps8640 *aux_to_ps8640(struct drm_dp_aux *aux) |
153 | { | |
154 | return container_of(aux, struct ps8640, aux); | |
155 | } | |
156 | ||
e9d9f958 PC |
157 | static bool ps8640_of_panel_on_aux_bus(struct device *dev) |
158 | { | |
159 | struct device_node *bus, *panel; | |
160 | ||
161 | bus = of_get_child_by_name(dev->of_node, "aux-bus"); | |
162 | if (!bus) | |
163 | return false; | |
164 | ||
165 | panel = of_get_child_by_name(bus, "panel"); | |
166 | of_node_put(bus); | |
167 | if (!panel) | |
168 | return false; | |
169 | of_node_put(panel); | |
170 | ||
171 | return true; | |
172 | } | |
173 | ||
f5aa7d46 | 174 | static int _ps8640_wait_hpd_asserted(struct ps8640 *ps_bridge, unsigned long wait_us) |
826cff3f PC |
175 | { |
176 | struct regmap *map = ps_bridge->regmap[PAGE2_TOP_CNTL]; | |
826cff3f | 177 | int status; |
cb8e30dd | 178 | int ret; |
826cff3f PC |
179 | |
180 | /* | |
181 | * Apparently something about the firmware in the chip signals that | |
182 | * HPD goes high by reporting GPIO9 as high (even though HPD isn't | |
183 | * actually connected to GPIO9). | |
184 | */ | |
cb8e30dd DA |
185 | ret = regmap_read_poll_timeout(map, PAGE2_GPIO_H, status, |
186 | status & PS_GPIO9, wait_us / 10, wait_us); | |
187 | ||
188 | /* | |
189 | * The first time we see HPD go high after a reset we delay an extra | |
190 | * 50 ms. The best guess is that the MCU is doing "stuff" during this | |
191 | * time (maybe talking to the panel) and we don't want to interrupt it. | |
192 | * | |
193 | * No locking is done around "need_post_hpd_delay". If we're here we | |
194 | * know we're holding a PM Runtime reference and the only other place | |
195 | * that touches this is PM Runtime resume. | |
196 | */ | |
197 | if (!ret && ps_bridge->need_post_hpd_delay) { | |
198 | ps_bridge->need_post_hpd_delay = false; | |
199 | msleep(50); | |
200 | } | |
201 | ||
202 | return ret; | |
f5aa7d46 | 203 | } |
826cff3f | 204 | |
f5aa7d46 DA |
205 | static int ps8640_wait_hpd_asserted(struct drm_dp_aux *aux, unsigned long wait_us) |
206 | { | |
207 | struct ps8640 *ps_bridge = aux_to_ps8640(aux); | |
208 | struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev; | |
209 | int ret; | |
210 | ||
211 | /* | |
212 | * Note that this function is called by code that has already powered | |
213 | * the panel. We have to power ourselves up but we don't need to worry | |
214 | * about powering the panel. | |
215 | */ | |
216 | pm_runtime_get_sync(dev); | |
217 | ret = _ps8640_wait_hpd_asserted(ps_bridge, wait_us); | |
218 | pm_runtime_mark_last_busy(dev); | |
219 | pm_runtime_put_autosuspend(dev); | |
826cff3f PC |
220 | |
221 | return ret; | |
222 | } | |
223 | ||
224 | static ssize_t ps8640_aux_transfer_msg(struct drm_dp_aux *aux, | |
225 | struct drm_dp_aux_msg *msg) | |
13afcdd7 PC |
226 | { |
227 | struct ps8640 *ps_bridge = aux_to_ps8640(aux); | |
228 | struct regmap *map = ps_bridge->regmap[PAGE0_DP_CNTL]; | |
229 | struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev; | |
230 | unsigned int len = msg->size; | |
231 | unsigned int data; | |
232 | unsigned int base; | |
233 | int ret; | |
234 | u8 request = msg->request & | |
235 | ~(DP_AUX_I2C_MOT | DP_AUX_I2C_WRITE_STATUS_UPDATE); | |
236 | u8 *buf = msg->buffer; | |
237 | u8 addr_len[PAGE0_SWAUX_LENGTH + 1 - PAGE0_SWAUX_ADDR_7_0]; | |
238 | u8 i; | |
239 | bool is_native_aux = false; | |
240 | ||
241 | if (len > DP_AUX_MAX_PAYLOAD_BYTES) | |
242 | return -EINVAL; | |
243 | ||
244 | if (msg->address & ~SWAUX_ADDR_MASK) | |
245 | return -EINVAL; | |
246 | ||
247 | switch (request) { | |
248 | case DP_AUX_NATIVE_WRITE: | |
249 | case DP_AUX_NATIVE_READ: | |
250 | is_native_aux = true; | |
251 | fallthrough; | |
252 | case DP_AUX_I2C_WRITE: | |
253 | case DP_AUX_I2C_READ: | |
254 | break; | |
255 | default: | |
256 | return -EINVAL; | |
257 | } | |
258 | ||
259 | ret = regmap_write(map, PAGE0_AUXCH_CFG3, AUXCH_CFG3_RESET); | |
260 | if (ret) { | |
261 | DRM_DEV_ERROR(dev, "failed to write PAGE0_AUXCH_CFG3: %d\n", | |
262 | ret); | |
263 | return ret; | |
264 | } | |
265 | ||
266 | /* Assume it's good */ | |
267 | msg->reply = 0; | |
268 | ||
269 | base = PAGE0_SWAUX_ADDR_7_0; | |
270 | addr_len[PAGE0_SWAUX_ADDR_7_0 - base] = msg->address; | |
271 | addr_len[PAGE0_SWAUX_ADDR_15_8 - base] = msg->address >> 8; | |
272 | addr_len[PAGE0_SWAUX_ADDR_23_16 - base] = (msg->address >> 16) | | |
273 | (msg->request << 4); | |
274 | addr_len[PAGE0_SWAUX_LENGTH - base] = (len == 0) ? SWAUX_NO_PAYLOAD : | |
275 | ((len - 1) & SWAUX_LENGTH_MASK); | |
276 | ||
277 | regmap_bulk_write(map, PAGE0_SWAUX_ADDR_7_0, addr_len, | |
278 | ARRAY_SIZE(addr_len)); | |
279 | ||
280 | if (len && (request == DP_AUX_NATIVE_WRITE || | |
281 | request == DP_AUX_I2C_WRITE)) { | |
282 | /* Write to the internal FIFO buffer */ | |
283 | for (i = 0; i < len; i++) { | |
284 | ret = regmap_write(map, PAGE0_SWAUX_WDATA, buf[i]); | |
285 | if (ret) { | |
286 | DRM_DEV_ERROR(dev, | |
287 | "failed to write WDATA: %d\n", | |
288 | ret); | |
289 | return ret; | |
290 | } | |
291 | } | |
292 | } | |
293 | ||
294 | regmap_write(map, PAGE0_SWAUX_CTRL, SWAUX_SEND); | |
295 | ||
296 | /* Zero delay loop because i2c transactions are slow already */ | |
297 | regmap_read_poll_timeout(map, PAGE0_SWAUX_CTRL, data, | |
298 | !(data & SWAUX_SEND), 0, 50 * 1000); | |
299 | ||
300 | regmap_read(map, PAGE0_SWAUX_STATUS, &data); | |
301 | if (ret) { | |
302 | DRM_DEV_ERROR(dev, "failed to read PAGE0_SWAUX_STATUS: %d\n", | |
303 | ret); | |
304 | return ret; | |
305 | } | |
306 | ||
307 | switch (data & SWAUX_STATUS_MASK) { | |
13afcdd7 PC |
308 | case SWAUX_STATUS_NACK: |
309 | case SWAUX_STATUS_I2C_NACK: | |
310 | /* | |
311 | * The programming guide is not clear about whether a I2C NACK | |
312 | * would trigger SWAUX_STATUS_NACK or SWAUX_STATUS_I2C_NACK. So | |
313 | * we handle both cases together. | |
314 | */ | |
315 | if (is_native_aux) | |
316 | msg->reply |= DP_AUX_NATIVE_REPLY_NACK; | |
317 | else | |
318 | msg->reply |= DP_AUX_I2C_REPLY_NACK; | |
319 | ||
320 | fallthrough; | |
321 | case SWAUX_STATUS_ACKM: | |
322 | len = data & SWAUX_M_MASK; | |
323 | break; | |
562d2dd8 JY |
324 | case SWAUX_STATUS_DEFER: |
325 | case SWAUX_STATUS_I2C_DEFER: | |
326 | if (is_native_aux) | |
327 | msg->reply |= DP_AUX_NATIVE_REPLY_DEFER; | |
328 | else | |
329 | msg->reply |= DP_AUX_I2C_REPLY_DEFER; | |
330 | len = data & SWAUX_M_MASK; | |
331 | break; | |
13afcdd7 PC |
332 | case SWAUX_STATUS_INVALID: |
333 | return -EOPNOTSUPP; | |
334 | case SWAUX_STATUS_TIMEOUT: | |
335 | return -ETIMEDOUT; | |
336 | } | |
337 | ||
338 | if (len && (request == DP_AUX_NATIVE_READ || | |
339 | request == DP_AUX_I2C_READ)) { | |
340 | /* Read from the internal FIFO buffer */ | |
341 | for (i = 0; i < len; i++) { | |
342 | ret = regmap_read(map, PAGE0_SWAUX_RDATA, &data); | |
343 | if (ret) { | |
344 | DRM_DEV_ERROR(dev, | |
345 | "failed to read RDATA: %d\n", | |
346 | ret); | |
347 | return ret; | |
348 | } | |
349 | ||
350 | buf[i] = data; | |
351 | } | |
352 | } | |
353 | ||
354 | return len; | |
355 | } | |
356 | ||
826cff3f PC |
357 | static ssize_t ps8640_aux_transfer(struct drm_dp_aux *aux, |
358 | struct drm_dp_aux_msg *msg) | |
359 | { | |
360 | struct ps8640 *ps_bridge = aux_to_ps8640(aux); | |
361 | struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev; | |
362 | int ret; | |
363 | ||
364 | pm_runtime_get_sync(dev); | |
f5aa7d46 | 365 | ret = ps8640_aux_transfer_msg(aux, msg); |
826cff3f PC |
366 | pm_runtime_mark_last_busy(dev); |
367 | pm_runtime_put_autosuspend(dev); | |
368 | ||
369 | return ret; | |
370 | } | |
371 | ||
372 | static void ps8640_bridge_vdo_control(struct ps8640 *ps_bridge, | |
373 | const enum ps8640_vdo_control ctrl) | |
bc1aee7f | 374 | { |
692d8db0 | 375 | struct regmap *map = ps_bridge->regmap[PAGE3_DSI_CNTL1]; |
826cff3f | 376 | struct device *dev = &ps_bridge->page[PAGE3_DSI_CNTL1]->dev; |
bc1aee7f JS |
377 | u8 vdo_ctrl_buf[] = { VDO_CTL_ADD, ctrl }; |
378 | int ret; | |
379 | ||
692d8db0 PC |
380 | ret = regmap_bulk_write(map, PAGE3_SET_ADD, |
381 | vdo_ctrl_buf, sizeof(vdo_ctrl_buf)); | |
382 | ||
826cff3f PC |
383 | if (ret < 0) |
384 | dev_err(dev, "failed to %sable VDO: %d\n", | |
385 | ctrl == ENABLE ? "en" : "dis", ret); | |
bc1aee7f JS |
386 | } |
387 | ||
826cff3f | 388 | static int __maybe_unused ps8640_resume(struct device *dev) |
bc1aee7f | 389 | { |
826cff3f PC |
390 | struct ps8640 *ps_bridge = dev_get_drvdata(dev); |
391 | int ret; | |
46f20630 | 392 | |
bc1aee7f JS |
393 | ret = regulator_bulk_enable(ARRAY_SIZE(ps_bridge->supplies), |
394 | ps_bridge->supplies); | |
395 | if (ret < 0) { | |
826cff3f PC |
396 | dev_err(dev, "cannot enable regulators %d\n", ret); |
397 | return ret; | |
bc1aee7f JS |
398 | } |
399 | ||
400 | gpiod_set_value(ps_bridge->gpio_powerdown, 0); | |
401 | gpiod_set_value(ps_bridge->gpio_reset, 1); | |
402 | usleep_range(2000, 2500); | |
403 | gpiod_set_value(ps_bridge->gpio_reset, 0); | |
55453c09 HYW |
404 | /* Double reset for T4 and T5 */ |
405 | msleep(50); | |
406 | gpiod_set_value(ps_bridge->gpio_reset, 1); | |
407 | msleep(50); | |
408 | gpiod_set_value(ps_bridge->gpio_reset, 0); | |
bc1aee7f | 409 | |
cb8e30dd DA |
410 | /* We just reset things, so we need a delay after the first HPD */ |
411 | ps_bridge->need_post_hpd_delay = true; | |
412 | ||
bc1aee7f | 413 | /* |
826cff3f PC |
414 | * Mystery 200 ms delay for the "MCU to be ready". It's unclear if |
415 | * this is truly necessary since the MCU will already signal that | |
416 | * things are "good to go" by signaling HPD on "gpio 9". See | |
f5aa7d46 DA |
417 | * _ps8640_wait_hpd_asserted(). For now we'll keep this mystery delay |
418 | * just in case. | |
bc1aee7f JS |
419 | */ |
420 | msleep(200); | |
421 | ||
826cff3f | 422 | return 0; |
bc1aee7f JS |
423 | } |
424 | ||
826cff3f | 425 | static int __maybe_unused ps8640_suspend(struct device *dev) |
bc1aee7f | 426 | { |
826cff3f | 427 | struct ps8640 *ps_bridge = dev_get_drvdata(dev); |
bc1aee7f JS |
428 | int ret; |
429 | ||
bc1aee7f JS |
430 | gpiod_set_value(ps_bridge->gpio_reset, 1); |
431 | gpiod_set_value(ps_bridge->gpio_powerdown, 1); | |
432 | ret = regulator_bulk_disable(ARRAY_SIZE(ps_bridge->supplies), | |
433 | ps_bridge->supplies); | |
434 | if (ret < 0) | |
826cff3f | 435 | dev_err(dev, "cannot disable regulators %d\n", ret); |
46f20630 | 436 | |
826cff3f | 437 | return ret; |
46f20630 EBS |
438 | } |
439 | ||
826cff3f PC |
440 | static const struct dev_pm_ops ps8640_pm_ops = { |
441 | SET_RUNTIME_PM_OPS(ps8640_suspend, ps8640_resume, NULL) | |
442 | SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, | |
443 | pm_runtime_force_resume) | |
444 | }; | |
445 | ||
102e80d1 SR |
446 | static void ps8640_atomic_pre_enable(struct drm_bridge *bridge, |
447 | struct drm_bridge_state *old_bridge_state) | |
46f20630 EBS |
448 | { |
449 | struct ps8640 *ps_bridge = bridge_to_ps8640(bridge); | |
826cff3f PC |
450 | struct regmap *map = ps_bridge->regmap[PAGE2_TOP_CNTL]; |
451 | struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev; | |
46f20630 EBS |
452 | int ret; |
453 | ||
826cff3f | 454 | pm_runtime_get_sync(dev); |
f5aa7d46 DA |
455 | ret = _ps8640_wait_hpd_asserted(ps_bridge, 200 * 1000); |
456 | if (ret < 0) | |
457 | dev_warn(dev, "HPD didn't go high: %d\n", ret); | |
46f20630 | 458 | |
826cff3f PC |
459 | /* |
460 | * The Manufacturer Command Set (MCS) is a device dependent interface | |
461 | * intended for factory programming of the display module default | |
462 | * parameters. Once the display module is configured, the MCS shall be | |
463 | * disabled by the manufacturer. Once disabled, all MCS commands are | |
464 | * ignored by the display interface. | |
465 | */ | |
466 | ||
467 | ret = regmap_update_bits(map, PAGE2_MCS_EN, MCS_EN, 0); | |
468 | if (ret < 0) | |
469 | dev_warn(dev, "failed write PAGE2_MCS_EN: %d\n", ret); | |
470 | ||
471 | /* Switch access edp panel's edid through i2c */ | |
472 | ret = regmap_write(map, PAGE2_I2C_BYPASS, I2C_BYPASS_EN); | |
46f20630 | 473 | if (ret < 0) |
826cff3f PC |
474 | dev_warn(dev, "failed write PAGE2_MCS_EN: %d\n", ret); |
475 | ||
476 | ps8640_bridge_vdo_control(ps_bridge, ENABLE); | |
477 | ||
478 | ps_bridge->pre_enabled = true; | |
46f20630 EBS |
479 | } |
480 | ||
102e80d1 SR |
481 | static void ps8640_atomic_post_disable(struct drm_bridge *bridge, |
482 | struct drm_bridge_state *old_bridge_state) | |
46f20630 EBS |
483 | { |
484 | struct ps8640 *ps_bridge = bridge_to_ps8640(bridge); | |
485 | ||
826cff3f PC |
486 | ps_bridge->pre_enabled = false; |
487 | ||
46f20630 | 488 | ps8640_bridge_vdo_control(ps_bridge, DISABLE); |
826cff3f | 489 | pm_runtime_put_sync_suspend(&ps_bridge->page[PAGE0_DP_CNTL]->dev); |
bc1aee7f JS |
490 | } |
491 | ||
a25b988f LP |
492 | static int ps8640_bridge_attach(struct drm_bridge *bridge, |
493 | enum drm_bridge_attach_flags flags) | |
bc1aee7f JS |
494 | { |
495 | struct ps8640 *ps_bridge = bridge_to_ps8640(bridge); | |
496 | struct device *dev = &ps_bridge->page[0]->dev; | |
bc1aee7f | 497 | int ret; |
812a65ba EBS |
498 | |
499 | if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) | |
500 | return -EINVAL; | |
501 | ||
f8378c04 | 502 | ps_bridge->aux.drm_dev = bridge->dev; |
13afcdd7 PC |
503 | ret = drm_dp_aux_register(&ps_bridge->aux); |
504 | if (ret) { | |
505 | dev_err(dev, "failed to register DP AUX channel: %d\n", ret); | |
fe93ae80 | 506 | return ret; |
13afcdd7 | 507 | } |
bc1aee7f | 508 | |
9294914d ADR |
509 | ps_bridge->link = device_link_add(bridge->dev->dev, dev, DL_FLAG_STATELESS); |
510 | if (!ps_bridge->link) { | |
511 | dev_err(dev, "failed to create device link"); | |
512 | ret = -EINVAL; | |
513 | goto err_devlink; | |
514 | } | |
515 | ||
bc1aee7f | 516 | /* Attach the panel-bridge to the dsi bridge */ |
9294914d ADR |
517 | ret = drm_bridge_attach(bridge->encoder, ps_bridge->panel_bridge, |
518 | &ps_bridge->bridge, flags); | |
519 | if (ret) | |
520 | goto err_bridge_attach; | |
521 | ||
522 | return 0; | |
523 | ||
524 | err_bridge_attach: | |
525 | device_link_del(ps_bridge->link); | |
526 | err_devlink: | |
527 | drm_dp_aux_unregister(&ps_bridge->aux); | |
528 | ||
529 | return ret; | |
bc1aee7f JS |
530 | } |
531 | ||
13afcdd7 PC |
532 | static void ps8640_bridge_detach(struct drm_bridge *bridge) |
533 | { | |
9294914d ADR |
534 | struct ps8640 *ps_bridge = bridge_to_ps8640(bridge); |
535 | ||
536 | drm_dp_aux_unregister(&ps_bridge->aux); | |
537 | if (ps_bridge->link) | |
538 | device_link_del(ps_bridge->link); | |
13afcdd7 PC |
539 | } |
540 | ||
d82c12ab EBS |
541 | static struct edid *ps8640_bridge_get_edid(struct drm_bridge *bridge, |
542 | struct drm_connector *connector) | |
543 | { | |
544 | struct ps8640 *ps_bridge = bridge_to_ps8640(bridge); | |
826cff3f | 545 | bool poweroff = !ps_bridge->pre_enabled; |
46f20630 EBS |
546 | struct edid *edid; |
547 | ||
548 | /* | |
549 | * When we end calling get_edid() triggered by an ioctl, i.e | |
550 | * | |
551 | * drm_mode_getconnector (ioctl) | |
552 | * -> drm_helper_probe_single_connector_modes | |
553 | * -> drm_bridge_connector_get_modes | |
554 | * -> ps8640_bridge_get_edid | |
555 | * | |
556 | * We need to make sure that what we need is enabled before reading | |
557 | * EDID, for this chip, we need to do a full poweron, otherwise it will | |
558 | * fail. | |
559 | */ | |
102e80d1 | 560 | drm_atomic_bridge_chain_pre_enable(bridge, connector->state->state); |
d82c12ab | 561 | |
46f20630 | 562 | edid = drm_get_edid(connector, |
d82c12ab | 563 | ps_bridge->page[PAGE0_DP_CNTL]->adapter); |
46f20630 EBS |
564 | |
565 | /* | |
566 | * If we call the get_edid() function without having enabled the chip | |
567 | * before, return the chip to its original power state. | |
568 | */ | |
569 | if (poweroff) | |
102e80d1 | 570 | drm_atomic_bridge_chain_post_disable(bridge, connector->state->state); |
46f20630 EBS |
571 | |
572 | return edid; | |
d82c12ab EBS |
573 | } |
574 | ||
826cff3f PC |
575 | static void ps8640_runtime_disable(void *data) |
576 | { | |
577 | pm_runtime_dont_use_autosuspend(data); | |
578 | pm_runtime_disable(data); | |
579 | } | |
580 | ||
bc1aee7f JS |
581 | static const struct drm_bridge_funcs ps8640_bridge_funcs = { |
582 | .attach = ps8640_bridge_attach, | |
13afcdd7 | 583 | .detach = ps8640_bridge_detach, |
d82c12ab | 584 | .get_edid = ps8640_bridge_get_edid, |
102e80d1 SR |
585 | .atomic_post_disable = ps8640_atomic_post_disable, |
586 | .atomic_pre_enable = ps8640_atomic_pre_enable, | |
587 | .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, | |
588 | .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, | |
589 | .atomic_reset = drm_atomic_helper_bridge_reset, | |
bc1aee7f JS |
590 | }; |
591 | ||
10e619f1 | 592 | static int ps8640_bridge_get_dsi_resources(struct device *dev, struct ps8640 *ps_bridge) |
7abbc26f MR |
593 | { |
594 | struct device_node *in_ep, *dsi_node; | |
595 | struct mipi_dsi_device *dsi; | |
596 | struct mipi_dsi_host *host; | |
7abbc26f MR |
597 | const struct mipi_dsi_device_info info = { .type = "ps8640", |
598 | .channel = 0, | |
599 | .node = NULL, | |
600 | }; | |
601 | ||
602 | /* port@0 is ps8640 dsi input port */ | |
603 | in_ep = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1); | |
604 | if (!in_ep) | |
605 | return -ENODEV; | |
606 | ||
607 | dsi_node = of_graph_get_remote_port_parent(in_ep); | |
608 | of_node_put(in_ep); | |
609 | if (!dsi_node) | |
610 | return -ENODEV; | |
611 | ||
612 | host = of_find_mipi_dsi_host_by_node(dsi_node); | |
613 | of_node_put(dsi_node); | |
614 | if (!host) | |
615 | return -EPROBE_DEFER; | |
616 | ||
617 | dsi = devm_mipi_dsi_device_register_full(dev, host, &info); | |
618 | if (IS_ERR(dsi)) { | |
619 | dev_err(dev, "failed to create dsi device\n"); | |
620 | return PTR_ERR(dsi); | |
621 | } | |
622 | ||
623 | ps_bridge->dsi = dsi; | |
624 | ||
625 | dsi->host = host; | |
626 | dsi->mode_flags = MIPI_DSI_MODE_VIDEO | | |
627 | MIPI_DSI_MODE_VIDEO_SYNC_PULSE; | |
628 | dsi->format = MIPI_DSI_FMT_RGB888; | |
629 | dsi->lanes = NUM_MIPI_LANES; | |
630 | ||
10e619f1 DA |
631 | return 0; |
632 | } | |
633 | ||
634 | static int ps8640_bridge_link_panel(struct drm_dp_aux *aux) | |
635 | { | |
636 | struct ps8640 *ps_bridge = aux_to_ps8640(aux); | |
637 | struct device *dev = aux->dev; | |
638 | struct device_node *np = dev->of_node; | |
639 | int ret; | |
640 | ||
641 | /* | |
642 | * NOTE about returning -EPROBE_DEFER from this function: if we | |
643 | * return an error (most relevant to -EPROBE_DEFER) it will only | |
644 | * be passed out to ps8640_probe() if it called this directly (AKA the | |
645 | * panel isn't under the "aux-bus" node). That should be fine because | |
646 | * if the panel is under "aux-bus" it's guaranteed to have probed by | |
647 | * the time this function has been called. | |
648 | */ | |
649 | ||
650 | /* port@1 is ps8640 output port */ | |
651 | ps_bridge->panel_bridge = devm_drm_of_get_bridge(dev, np, 1, 0); | |
652 | if (IS_ERR(ps_bridge->panel_bridge)) | |
653 | return PTR_ERR(ps_bridge->panel_bridge); | |
654 | ||
655 | ret = devm_drm_bridge_add(dev, &ps_bridge->bridge); | |
656 | if (ret) | |
657 | return ret; | |
658 | ||
659 | return devm_mipi_dsi_attach(dev, ps_bridge->dsi); | |
7abbc26f MR |
660 | } |
661 | ||
bc1aee7f JS |
662 | static int ps8640_probe(struct i2c_client *client) |
663 | { | |
664 | struct device *dev = &client->dev; | |
bc1aee7f | 665 | struct ps8640 *ps_bridge; |
bc1aee7f JS |
666 | int ret; |
667 | u32 i; | |
668 | ||
669 | ps_bridge = devm_kzalloc(dev, sizeof(*ps_bridge), GFP_KERNEL); | |
670 | if (!ps_bridge) | |
671 | return -ENOMEM; | |
672 | ||
fc94224c CYT |
673 | ps_bridge->supplies[0].supply = "vdd12"; |
674 | ps_bridge->supplies[1].supply = "vdd33"; | |
bc1aee7f JS |
675 | ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ps_bridge->supplies), |
676 | ps_bridge->supplies); | |
677 | if (ret) | |
678 | return ret; | |
679 | ||
680 | ps_bridge->gpio_powerdown = devm_gpiod_get(&client->dev, "powerdown", | |
681 | GPIOD_OUT_HIGH); | |
682 | if (IS_ERR(ps_bridge->gpio_powerdown)) | |
683 | return PTR_ERR(ps_bridge->gpio_powerdown); | |
684 | ||
685 | /* | |
686 | * Assert the reset to avoid the bridge being initialized prematurely | |
687 | */ | |
688 | ps_bridge->gpio_reset = devm_gpiod_get(&client->dev, "reset", | |
689 | GPIOD_OUT_HIGH); | |
690 | if (IS_ERR(ps_bridge->gpio_reset)) | |
691 | return PTR_ERR(ps_bridge->gpio_reset); | |
692 | ||
693 | ps_bridge->bridge.funcs = &ps8640_bridge_funcs; | |
694 | ps_bridge->bridge.of_node = dev->of_node; | |
d82c12ab | 695 | ps_bridge->bridge.type = DRM_MODE_CONNECTOR_eDP; |
bc1aee7f | 696 | |
e9d9f958 PC |
697 | /* |
698 | * In the device tree, if panel is listed under aux-bus of the bridge | |
699 | * node, panel driver should be able to retrieve EDID by itself using | |
700 | * aux-bus. So let's not set DRM_BRIDGE_OP_EDID here. | |
701 | */ | |
702 | if (!ps8640_of_panel_on_aux_bus(&client->dev)) | |
703 | ps_bridge->bridge.ops = DRM_BRIDGE_OP_EDID; | |
704 | ||
10e619f1 DA |
705 | /* |
706 | * Get MIPI DSI resources early. These can return -EPROBE_DEFER so | |
707 | * we want to get them out of the way sooner. | |
708 | */ | |
709 | ret = ps8640_bridge_get_dsi_resources(&client->dev, ps_bridge); | |
710 | if (ret) | |
711 | return ret; | |
712 | ||
bc1aee7f JS |
713 | ps_bridge->page[PAGE0_DP_CNTL] = client; |
714 | ||
692d8db0 PC |
715 | ps_bridge->regmap[PAGE0_DP_CNTL] = devm_regmap_init_i2c(client, ps8640_regmap_config); |
716 | if (IS_ERR(ps_bridge->regmap[PAGE0_DP_CNTL])) | |
717 | return PTR_ERR(ps_bridge->regmap[PAGE0_DP_CNTL]); | |
718 | ||
bc1aee7f JS |
719 | for (i = 1; i < ARRAY_SIZE(ps_bridge->page); i++) { |
720 | ps_bridge->page[i] = devm_i2c_new_dummy_device(&client->dev, | |
721 | client->adapter, | |
722 | client->addr + i); | |
692d8db0 | 723 | if (IS_ERR(ps_bridge->page[i])) |
bc1aee7f | 724 | return PTR_ERR(ps_bridge->page[i]); |
692d8db0 PC |
725 | |
726 | ps_bridge->regmap[i] = devm_regmap_init_i2c(ps_bridge->page[i], | |
727 | ps8640_regmap_config + i); | |
728 | if (IS_ERR(ps_bridge->regmap[i])) | |
729 | return PTR_ERR(ps_bridge->regmap[i]); | |
bc1aee7f JS |
730 | } |
731 | ||
732 | i2c_set_clientdata(client, ps_bridge); | |
733 | ||
13afcdd7 PC |
734 | ps_bridge->aux.name = "parade-ps8640-aux"; |
735 | ps_bridge->aux.dev = dev; | |
736 | ps_bridge->aux.transfer = ps8640_aux_transfer; | |
f5aa7d46 | 737 | ps_bridge->aux.wait_hpd_asserted = ps8640_wait_hpd_asserted; |
13afcdd7 PC |
738 | drm_dp_aux_init(&ps_bridge->aux); |
739 | ||
826cff3f PC |
740 | pm_runtime_enable(dev); |
741 | /* | |
742 | * Powering on ps8640 takes ~300ms. To avoid wasting time on power | |
b1d2751c | 743 | * cycling ps8640 too often, set autosuspend_delay to 2000ms to ensure |
826cff3f PC |
744 | * the bridge wouldn't suspend in between each _aux_transfer_msg() call |
745 | * during EDID read (~20ms in my experiment) and in between the last | |
746 | * _aux_transfer_msg() call during EDID read and the _pre_enable() call | |
747 | * (~100ms in my experiment). | |
748 | */ | |
b1d2751c | 749 | pm_runtime_set_autosuspend_delay(dev, 2000); |
826cff3f PC |
750 | pm_runtime_use_autosuspend(dev); |
751 | pm_suspend_ignore_children(dev, true); | |
752 | ret = devm_add_action_or_reset(dev, ps8640_runtime_disable, dev); | |
753 | if (ret) | |
754 | return ret; | |
755 | ||
10e619f1 | 756 | ret = devm_of_dp_aux_populate_bus(&ps_bridge->aux, ps8640_bridge_link_panel); |
e9d9f958 | 757 | |
10e619f1 DA |
758 | /* |
759 | * If devm_of_dp_aux_populate_bus() returns -ENODEV then it's up to | |
760 | * usa to call ps8640_bridge_link_panel() directly. NOTE: in this case | |
761 | * the function is allowed to -EPROBE_DEFER. | |
762 | */ | |
763 | if (ret == -ENODEV) | |
764 | return ps8640_bridge_link_panel(&ps_bridge->aux); | |
7abbc26f | 765 | |
7abbc26f | 766 | return ret; |
bc1aee7f JS |
767 | } |
768 | ||
bc1aee7f JS |
769 | static const struct of_device_id ps8640_match[] = { |
770 | { .compatible = "parade,ps8640" }, | |
771 | { } | |
772 | }; | |
773 | MODULE_DEVICE_TABLE(of, ps8640_match); | |
774 | ||
775 | static struct i2c_driver ps8640_driver = { | |
776 | .probe_new = ps8640_probe, | |
bc1aee7f JS |
777 | .driver = { |
778 | .name = "ps8640", | |
779 | .of_match_table = ps8640_match, | |
826cff3f | 780 | .pm = &ps8640_pm_ops, |
bc1aee7f JS |
781 | }, |
782 | }; | |
783 | module_i2c_driver(ps8640_driver); | |
784 | ||
785 | MODULE_AUTHOR("Jitao Shi <jitao.shi@mediatek.com>"); | |
786 | MODULE_AUTHOR("CK Hu <ck.hu@mediatek.com>"); | |
787 | MODULE_AUTHOR("Enric Balletbo i Serra <enric.balletbo@collabora.com>"); | |
788 | MODULE_DESCRIPTION("PARADE ps8640 DSI-eDP converter driver"); | |
789 | MODULE_LICENSE("GPL v2"); |