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drm: bridge/dw_hdmi: clean up phy configuration
[linux-2.6-block.git] / drivers / gpu / drm / bridge / dw_hdmi.c
CommitLineData
9aaf880e
FE		 1/*
2 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
b21f4b65 9 * Designware High-Definition Multimedia Interface (HDMI) driver
9aaf880e
FE		 10 *
11 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
12 */
b21f4b65 13#include <linux/module.h>
9aaf880e
FE		 14#include <linux/irq.h>
15#include <linux/delay.h>
16#include <linux/err.h>
17#include <linux/clk.h>
5a819ed6 18#include <linux/hdmi.h>
6bcf4953 19#include <linux/mutex.h>
9aaf880e
FE		 20#include <linux/of_device.h>
21
3d1b35a3 22#include <drm/drm_of.h>
9aaf880e
FE		 23#include <drm/drmP.h>
24#include <drm/drm_crtc_helper.h>
25#include <drm/drm_edid.h>
26#include <drm/drm_encoder_slave.h>
b21f4b65 27#include <drm/bridge/dw_hdmi.h>
9aaf880e 28
b21f4b65 29#include "dw_hdmi.h"
9aaf880e
FE		 30
31#define HDMI_EDID_LEN 512
32
33#define RGB 0
34#define YCBCR444 1
35#define YCBCR422_16BITS 2
36#define YCBCR422_8BITS 3
37#define XVYCC444 4
38
39enum hdmi_datamap {
40 RGB444_8B = 0x01,
41 RGB444_10B = 0x03,
42 RGB444_12B = 0x05,
43 RGB444_16B = 0x07,
44 YCbCr444_8B = 0x09,
45 YCbCr444_10B = 0x0B,
46 YCbCr444_12B = 0x0D,
47 YCbCr444_16B = 0x0F,
48 YCbCr422_8B = 0x16,
49 YCbCr422_10B = 0x14,
50 YCbCr422_12B = 0x12,
51};
52
9aaf880e
FE		 53static const u16 csc_coeff_default[3][4] = {
54 { 0x2000, 0x0000, 0x0000, 0x0000 },
55 { 0x0000, 0x2000, 0x0000, 0x0000 },
56 { 0x0000, 0x0000, 0x2000, 0x0000 }
57};
58
59static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
60 { 0x2000, 0x6926, 0x74fd, 0x010e },
61 { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
62 { 0x2000, 0x0000, 0x38b4, 0x7e3b }
63};
64
65static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
66 { 0x2000, 0x7106, 0x7a02, 0x00a7 },
67 { 0x2000, 0x3264, 0x0000, 0x7e6d },
68 { 0x2000, 0x0000, 0x3b61, 0x7e25 }
69};
70
71static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
72 { 0x2591, 0x1322, 0x074b, 0x0000 },
73 { 0x6535, 0x2000, 0x7acc, 0x0200 },
74 { 0x6acd, 0x7534, 0x2000, 0x0200 }
75};
76
77static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
78 { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
79 { 0x62f0, 0x2000, 0x7d11, 0x0200 },
80 { 0x6756, 0x78ab, 0x2000, 0x0200 }
81};
82
83struct hdmi_vmode {
84 bool mdvi;
85 bool mhsyncpolarity;
86 bool mvsyncpolarity;
87 bool minterlaced;
88 bool mdataenablepolarity;
89
90 unsigned int mpixelclock;
91 unsigned int mpixelrepetitioninput;
92 unsigned int mpixelrepetitionoutput;
93};
94
95struct hdmi_data_info {
96 unsigned int enc_in_format;
97 unsigned int enc_out_format;
98 unsigned int enc_color_depth;
99 unsigned int colorimetry;
100 unsigned int pix_repet_factor;
101 unsigned int hdcp_enable;
102 struct hdmi_vmode video_mode;
103};
104
b21f4b65 105struct dw_hdmi {
9aaf880e 106 struct drm_connector connector;
3d1b35a3
AY		 107 struct drm_encoder *encoder;
108 struct drm_bridge *bridge;
9aaf880e 109
b21f4b65 110 enum dw_hdmi_devtype dev_type;
9aaf880e
FE		 111 struct device *dev;
112 struct clk *isfr_clk;
113 struct clk *iahb_clk;
114
115 struct hdmi_data_info hdmi_data;
b21f4b65
AY		 116 const struct dw_hdmi_plat_data *plat_data;
117
9aaf880e
FE		 118 int vic;
119
120 u8 edid[HDMI_EDID_LEN];
121 bool cable_plugin;
122
123 bool phy_enabled;
124 struct drm_display_mode previous_mode;
125
126 struct regmap *regmap;
127 struct i2c_adapter *ddc;
128 void __iomem *regs;
129
6bcf4953 130 struct mutex audio_mutex;
9aaf880e
FE		 131 unsigned int sample_rate;
132 int ratio;
0cd9d142
AY		 133
134 void (*write)(struct dw_hdmi *hdmi, u8 val, int offset);
135 u8 (*read)(struct dw_hdmi *hdmi, int offset);
9aaf880e
FE		 136};
137
0cd9d142
AY		 138static void dw_hdmi_writel(struct dw_hdmi *hdmi, u8 val, int offset)
139{
140 writel(val, hdmi->regs + (offset << 2));
141}
142
143static u8 dw_hdmi_readl(struct dw_hdmi *hdmi, int offset)
144{
145 return readl(hdmi->regs + (offset << 2));
146}
147
148static void dw_hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
9aaf880e
FE		 149{
150 writeb(val, hdmi->regs + offset);
151}
152
0cd9d142 153static u8 dw_hdmi_readb(struct dw_hdmi *hdmi, int offset)
9aaf880e
FE		 154{
155 return readb(hdmi->regs + offset);
156}
157
0cd9d142
AY		 158static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
159{
160 hdmi->write(hdmi, val, offset);
161}
162
163static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
164{
165 return hdmi->read(hdmi, offset);
166}
167
b21f4b65 168static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
812bc615
RK		 169{
170 u8 val = hdmi_readb(hdmi, reg) & ~mask;
b44ab1b0 171
812bc615
RK		 172 val |= data & mask;
173 hdmi_writeb(hdmi, val, reg);
174}
175
b21f4b65 176static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
b5878339 177 u8 shift, u8 mask)
9aaf880e 178{
812bc615 179 hdmi_modb(hdmi, data << shift, mask, reg);
9aaf880e
FE		 180}
181
351e1354
RK		 182static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
183 unsigned int n)
9aaf880e 184{
622494a3
RK		 185 /* Must be set/cleared first */
186 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
9aaf880e
FE		 187
188 /* nshift factor = 0 */
812bc615 189 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
9aaf880e 190
9aaf880e
FE		 191 hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
192 HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
622494a3
RK		 193 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
194 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
195
196 hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
197 hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
198 hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
9aaf880e
FE		 199}
200
201static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk,
202 unsigned int ratio)
203{
204 unsigned int n = (128 * freq) / 1000;
205
206 switch (freq) {
207 case 32000:
208 if (pixel_clk == 25170000)
209 n = (ratio == 150) ? 9152 : 4576;
210 else if (pixel_clk == 27020000)
211 n = (ratio == 150) ? 8192 : 4096;
212 else if (pixel_clk == 74170000 || pixel_clk == 148350000)
213 n = 11648;
214 else
215 n = 4096;
216 break;
217
218 case 44100:
219 if (pixel_clk == 25170000)
220 n = 7007;
221 else if (pixel_clk == 74170000)
222 n = 17836;
223 else if (pixel_clk == 148350000)
224 n = (ratio == 150) ? 17836 : 8918;
225 else
226 n = 6272;
227 break;
228
229 case 48000:
230 if (pixel_clk == 25170000)
231 n = (ratio == 150) ? 9152 : 6864;
232 else if (pixel_clk == 27020000)
233 n = (ratio == 150) ? 8192 : 6144;
234 else if (pixel_clk == 74170000)
235 n = 11648;
236 else if (pixel_clk == 148350000)
237 n = (ratio == 150) ? 11648 : 5824;
238 else
239 n = 6144;
240 break;
241
242 case 88200:
243 n = hdmi_compute_n(44100, pixel_clk, ratio) * 2;
244 break;
245
246 case 96000:
247 n = hdmi_compute_n(48000, pixel_clk, ratio) * 2;
248 break;
249
250 case 176400:
251 n = hdmi_compute_n(44100, pixel_clk, ratio) * 4;
252 break;
253
254 case 192000:
255 n = hdmi_compute_n(48000, pixel_clk, ratio) * 4;
256 break;
257
258 default:
259 break;
260 }
261
262 return n;
263}
264
265static unsigned int hdmi_compute_cts(unsigned int freq, unsigned long pixel_clk,
266 unsigned int ratio)
267{
268 unsigned int cts = 0;
269
270 pr_debug("%s: freq: %d pixel_clk: %ld ratio: %d\n", __func__, freq,
271 pixel_clk, ratio);
272
273 switch (freq) {
274 case 32000:
275 if (pixel_clk == 297000000) {
276 cts = 222750;
277 break;
278 }
279 case 48000:
280 case 96000:
281 case 192000:
282 switch (pixel_clk) {
283 case 25200000:
284 case 27000000:
285 case 54000000:
286 case 74250000:
287 case 148500000:
288 cts = pixel_clk / 1000;
289 break;
290 case 297000000:
291 cts = 247500;
292 break;
293 /*
294 * All other TMDS clocks are not supported by
295 * DWC_hdmi_tx. The TMDS clocks divided or
296 * multiplied by 1,001 coefficients are not
297 * supported.
298 */
299 default:
300 break;
301 }
302 break;
303 case 44100:
304 case 88200:
305 case 176400:
306 switch (pixel_clk) {
307 case 25200000:
308 cts = 28000;
309 break;
310 case 27000000:
311 cts = 30000;
312 break;
313 case 54000000:
314 cts = 60000;
315 break;
316 case 74250000:
317 cts = 82500;
318 break;
319 case 148500000:
320 cts = 165000;
321 break;
322 case 297000000:
323 cts = 247500;
324 break;
325 default:
326 break;
327 }
328 break;
329 default:
330 break;
331 }
332 if (ratio == 100)
333 return cts;
7557b6e1 334 return (cts * ratio) / 100;
9aaf880e
FE		 335}
336
b21f4b65 337static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
b5878339 338 unsigned long pixel_clk)
9aaf880e
FE		 339{
340 unsigned int clk_n, clk_cts;
341
40678388 342 clk_n = hdmi_compute_n(hdmi->sample_rate, pixel_clk,
9aaf880e 343 hdmi->ratio);
40678388 344 clk_cts = hdmi_compute_cts(hdmi->sample_rate, pixel_clk,
9aaf880e
FE		 345 hdmi->ratio);
346
347 if (!clk_cts) {
348 dev_dbg(hdmi->dev, "%s: pixel clock not supported: %lu\n",
b5878339 349 __func__, pixel_clk);
9aaf880e
FE		 350 return;
351 }
352
353 dev_dbg(hdmi->dev, "%s: samplerate=%d ratio=%d pixelclk=%lu N=%d cts=%d\n",
354 __func__, hdmi->sample_rate, hdmi->ratio,
40678388 355 pixel_clk, clk_n, clk_cts);
9aaf880e 356
351e1354 357 hdmi_set_cts_n(hdmi, clk_cts, clk_n);
9aaf880e
FE		 358}
359
b21f4b65 360static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
9aaf880e 361{
6bcf4953 362 mutex_lock(&hdmi->audio_mutex);
40678388 363 hdmi_set_clk_regenerator(hdmi, 74250000);
6bcf4953 364 mutex_unlock(&hdmi->audio_mutex);
9aaf880e
FE		 365}
366
b21f4b65 367static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
9aaf880e 368{
6bcf4953 369 mutex_lock(&hdmi->audio_mutex);
40678388 370 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock);
6bcf4953 371 mutex_unlock(&hdmi->audio_mutex);
9aaf880e
FE		 372}
373
374/*
375 * this submodule is responsible for the video data synchronization.
376 * for example, for RGB 4:4:4 input, the data map is defined as
377 * pin{47~40} <==> R[7:0]
378 * pin{31~24} <==> G[7:0]
379 * pin{15~8} <==> B[7:0]
380 */
b21f4b65 381static void hdmi_video_sample(struct dw_hdmi *hdmi)
9aaf880e
FE		 382{
383 int color_format = 0;
384 u8 val;
385
386 if (hdmi->hdmi_data.enc_in_format == RGB) {
387 if (hdmi->hdmi_data.enc_color_depth == 8)
388 color_format = 0x01;
389 else if (hdmi->hdmi_data.enc_color_depth == 10)
390 color_format = 0x03;
391 else if (hdmi->hdmi_data.enc_color_depth == 12)
392 color_format = 0x05;
393 else if (hdmi->hdmi_data.enc_color_depth == 16)
394 color_format = 0x07;
395 else
396 return;
397 } else if (hdmi->hdmi_data.enc_in_format == YCBCR444) {
398 if (hdmi->hdmi_data.enc_color_depth == 8)
399 color_format = 0x09;
400 else if (hdmi->hdmi_data.enc_color_depth == 10)
401 color_format = 0x0B;
402 else if (hdmi->hdmi_data.enc_color_depth == 12)
403 color_format = 0x0D;
404 else if (hdmi->hdmi_data.enc_color_depth == 16)
405 color_format = 0x0F;
406 else
407 return;
408 } else if (hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) {
409 if (hdmi->hdmi_data.enc_color_depth == 8)
410 color_format = 0x16;
411 else if (hdmi->hdmi_data.enc_color_depth == 10)
412 color_format = 0x14;
413 else if (hdmi->hdmi_data.enc_color_depth == 12)
414 color_format = 0x12;
415 else
416 return;
417 }
418
419 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
420 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
421 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
422 hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
423
424 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
425 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
426 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
427 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
428 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
429 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
430 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
431 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
432 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
433 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
434 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
435}
436
b21f4b65 437static int is_color_space_conversion(struct dw_hdmi *hdmi)
9aaf880e 438{
ba92b225 439 return hdmi->hdmi_data.enc_in_format != hdmi->hdmi_data.enc_out_format;
9aaf880e
FE		 440}
441
b21f4b65 442static int is_color_space_decimation(struct dw_hdmi *hdmi)
9aaf880e 443{
ba92b225
FE		 444 if (hdmi->hdmi_data.enc_out_format != YCBCR422_8BITS)
445 return 0;
446 if (hdmi->hdmi_data.enc_in_format == RGB ||
447 hdmi->hdmi_data.enc_in_format == YCBCR444)
448 return 1;
449 return 0;
9aaf880e
FE		 450}
451
b21f4b65 452static int is_color_space_interpolation(struct dw_hdmi *hdmi)
9aaf880e 453{
ba92b225
FE		 454 if (hdmi->hdmi_data.enc_in_format != YCBCR422_8BITS)
455 return 0;
456 if (hdmi->hdmi_data.enc_out_format == RGB ||
457 hdmi->hdmi_data.enc_out_format == YCBCR444)
458 return 1;
459 return 0;
9aaf880e
FE		 460}
461
b21f4b65 462static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
9aaf880e
FE		 463{
464 const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
c082f9d7 465 unsigned i;
9aaf880e 466 u32 csc_scale = 1;
9aaf880e
FE		 467
468 if (is_color_space_conversion(hdmi)) {
469 if (hdmi->hdmi_data.enc_out_format == RGB) {
256a38b0
GK		 470 if (hdmi->hdmi_data.colorimetry ==
471 HDMI_COLORIMETRY_ITU_601)
9aaf880e
FE		 472 csc_coeff = &csc_coeff_rgb_out_eitu601;
473 else
474 csc_coeff = &csc_coeff_rgb_out_eitu709;
475 } else if (hdmi->hdmi_data.enc_in_format == RGB) {
256a38b0
GK		 476 if (hdmi->hdmi_data.colorimetry ==
477 HDMI_COLORIMETRY_ITU_601)
9aaf880e
FE		 478 csc_coeff = &csc_coeff_rgb_in_eitu601;
479 else
480 csc_coeff = &csc_coeff_rgb_in_eitu709;
481 csc_scale = 0;
482 }
483 }
484
c082f9d7
RK		 485 /* The CSC registers are sequential, alternating MSB then LSB */
486 for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
487 u16 coeff_a = (*csc_coeff)[0][i];
488 u16 coeff_b = (*csc_coeff)[1][i];
489 u16 coeff_c = (*csc_coeff)[2][i];
490
b5878339 491 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
c082f9d7
RK		 492 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
493 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
494 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
b5878339 495 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
c082f9d7
RK		 496 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
497 }
9aaf880e 498
812bc615
RK		 499 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
500 HDMI_CSC_SCALE);
9aaf880e
FE		 501}
502
b21f4b65 503static void hdmi_video_csc(struct dw_hdmi *hdmi)
9aaf880e
FE		 504{
505 int color_depth = 0;
506 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
507 int decimation = 0;
9aaf880e
FE		 508
509 /* YCC422 interpolation to 444 mode */
510 if (is_color_space_interpolation(hdmi))
511 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
512 else if (is_color_space_decimation(hdmi))
513 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
514
515 if (hdmi->hdmi_data.enc_color_depth == 8)
516 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
517 else if (hdmi->hdmi_data.enc_color_depth == 10)
518 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
519 else if (hdmi->hdmi_data.enc_color_depth == 12)
520 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
521 else if (hdmi->hdmi_data.enc_color_depth == 16)
522 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
523 else
524 return;
525
526 /* Configure the CSC registers */
527 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
812bc615
RK		 528 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
529 HDMI_CSC_SCALE);
9aaf880e 530
b21f4b65 531 dw_hdmi_update_csc_coeffs(hdmi);
9aaf880e
FE		 532}
533
534/*
535 * HDMI video packetizer is used to packetize the data.
536 * for example, if input is YCC422 mode or repeater is used,
537 * data should be repacked this module can be bypassed.
538 */
b21f4b65 539static void hdmi_video_packetize(struct dw_hdmi *hdmi)
9aaf880e
FE		 540{
541 unsigned int color_depth = 0;
542 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
543 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
544 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
bebdf664 545 u8 val, vp_conf;
9aaf880e 546
b5878339
AY		 547 if (hdmi_data->enc_out_format == RGB ||
548 hdmi_data->enc_out_format == YCBCR444) {
549 if (!hdmi_data->enc_color_depth) {
9aaf880e 550 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
b5878339 551 } else if (hdmi_data->enc_color_depth == 8) {
9aaf880e
FE		 552 color_depth = 4;
553 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
b5878339 554 } else if (hdmi_data->enc_color_depth == 10) {
9aaf880e 555 color_depth = 5;
b5878339 556 } else if (hdmi_data->enc_color_depth == 12) {
9aaf880e 557 color_depth = 6;
b5878339 558 } else if (hdmi_data->enc_color_depth == 16) {
9aaf880e 559 color_depth = 7;
b5878339 560 } else {
9aaf880e 561 return;
b5878339 562 }
9aaf880e
FE		 563 } else if (hdmi_data->enc_out_format == YCBCR422_8BITS) {
564 if (!hdmi_data->enc_color_depth ||
565 hdmi_data->enc_color_depth == 8)
566 remap_size = HDMI_VP_REMAP_YCC422_16bit;
567 else if (hdmi_data->enc_color_depth == 10)
568 remap_size = HDMI_VP_REMAP_YCC422_20bit;
569 else if (hdmi_data->enc_color_depth == 12)
570 remap_size = HDMI_VP_REMAP_YCC422_24bit;
571 else
572 return;
573 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
b5878339 574 } else {
9aaf880e 575 return;
b5878339 576 }
9aaf880e
FE		 577
578 /* set the packetizer registers */
579 val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
580 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
581 ((hdmi_data->pix_repet_factor <<
582 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
583 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
584 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
585
812bc615
RK		 586 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
587 HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
9aaf880e
FE		 588
589 /* Data from pixel repeater block */
590 if (hdmi_data->pix_repet_factor > 1) {
bebdf664
RK		 591 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
592 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
9aaf880e 593 } else { /* data from packetizer block */
bebdf664
RK		 594 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
595 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
9aaf880e
FE		 596 }
597
bebdf664
RK		 598 hdmi_modb(hdmi, vp_conf,
599 HDMI_VP_CONF_PR_EN_MASK |
600 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
601
812bc615
RK		 602 hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
603 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
9aaf880e
FE		 604
605 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
606
607 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
bebdf664
RK		 608 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
609 HDMI_VP_CONF_PP_EN_ENABLE |
610 HDMI_VP_CONF_YCC422_EN_DISABLE;
9aaf880e 611 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
bebdf664
RK		 612 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
613 HDMI_VP_CONF_PP_EN_DISABLE |
614 HDMI_VP_CONF_YCC422_EN_ENABLE;
9aaf880e 615 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
bebdf664
RK		 616 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
617 HDMI_VP_CONF_PP_EN_DISABLE |
618 HDMI_VP_CONF_YCC422_EN_DISABLE;
9aaf880e
FE		 619 } else {
620 return;
621 }
622
bebdf664
RK		 623 hdmi_modb(hdmi, vp_conf,
624 HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
625 HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
626
812bc615
RK		 627 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
628 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
629 HDMI_VP_STUFF_PP_STUFFING_MASK |
630 HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
9aaf880e 631
812bc615
RK		 632 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
633 HDMI_VP_CONF);
9aaf880e
FE		 634}
635
b21f4b65 636static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
b5878339 637 unsigned char bit)
9aaf880e 638{
812bc615
RK		 639 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
640 HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
9aaf880e
FE		 641}
642
b21f4b65 643static inline void hdmi_phy_test_enable(struct dw_hdmi *hdmi,
b5878339 644 unsigned char bit)
9aaf880e 645{
812bc615
RK		 646 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET,
647 HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0);
9aaf880e
FE		 648}
649
b21f4b65 650static inline void hdmi_phy_test_clock(struct dw_hdmi *hdmi,
b5878339 651 unsigned char bit)
9aaf880e 652{
812bc615
RK		 653 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET,
654 HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0);
9aaf880e
FE		 655}
656
b21f4b65 657static inline void hdmi_phy_test_din(struct dw_hdmi *hdmi,
b5878339 658 unsigned char bit)
9aaf880e
FE		 659{
660 hdmi_writeb(hdmi, bit, HDMI_PHY_TST1);
661}
662
b21f4b65 663static inline void hdmi_phy_test_dout(struct dw_hdmi *hdmi,
b5878339 664 unsigned char bit)
9aaf880e
FE		 665{
666 hdmi_writeb(hdmi, bit, HDMI_PHY_TST2);
667}
668
b21f4b65 669static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
9aaf880e 670{
a4d3b8b0
AY		 671 u32 val;
672
673 while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
9aaf880e
FE		 674 if (msec-- == 0)
675 return false;
0e6bcf3a 676 udelay(1000);
9aaf880e 677 }
a4d3b8b0
AY		 678 hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
679
9aaf880e
FE		 680 return true;
681}
682
b21f4b65 683static void __hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
b5878339 684 unsigned char addr)
9aaf880e
FE		 685{
686 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
687 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
688 hdmi_writeb(hdmi, (unsigned char)(data >> 8),
b5878339 689 HDMI_PHY_I2CM_DATAO_1_ADDR);
9aaf880e 690 hdmi_writeb(hdmi, (unsigned char)(data >> 0),
b5878339 691 HDMI_PHY_I2CM_DATAO_0_ADDR);
9aaf880e 692 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
b5878339 693 HDMI_PHY_I2CM_OPERATION_ADDR);
9aaf880e
FE		 694 hdmi_phy_wait_i2c_done(hdmi, 1000);
695}
696
b21f4b65 697static int hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
b5878339 698 unsigned char addr)
9aaf880e
FE		 699{
700 __hdmi_phy_i2c_write(hdmi, data, addr);
701 return 0;
702}
703
b21f4b65 704static void dw_hdmi_phy_enable_power(struct dw_hdmi *hdmi, u8 enable)
9aaf880e
FE		 705{
706 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
707 HDMI_PHY_CONF0_PDZ_OFFSET,
708 HDMI_PHY_CONF0_PDZ_MASK);
709}
710
b21f4b65 711static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
9aaf880e
FE		 712{
713 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
714 HDMI_PHY_CONF0_ENTMDS_OFFSET,
715 HDMI_PHY_CONF0_ENTMDS_MASK);
716}
717
d346c14e
AY		 718static void dw_hdmi_phy_enable_spare(struct dw_hdmi *hdmi, u8 enable)
719{
720 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
721 HDMI_PHY_CONF0_SPARECTRL_OFFSET,
722 HDMI_PHY_CONF0_SPARECTRL_MASK);
723}
724
b21f4b65 725static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
9aaf880e
FE		 726{
727 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
728 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
729 HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
730}
731
b21f4b65 732static void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
9aaf880e
FE		 733{
734 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
735 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
736 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
737}
738
b21f4b65 739static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
9aaf880e
FE		 740{
741 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
742 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
743 HDMI_PHY_CONF0_SELDATAENPOL_MASK);
744}
745
b21f4b65 746static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
9aaf880e
FE		 747{
748 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
749 HDMI_PHY_CONF0_SELDIPIF_OFFSET,
750 HDMI_PHY_CONF0_SELDIPIF_MASK);
751}
752
b21f4b65 753static int hdmi_phy_configure(struct dw_hdmi *hdmi, unsigned char prep,
9aaf880e
FE		 754 unsigned char res, int cscon)
755{
39cc1535 756 unsigned res_idx;
9aaf880e 757 u8 val, msec;
39cc1535
RK		 758 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
759 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
760 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
761 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
9aaf880e 762
9aaf880e
FE		 763 if (prep)
764 return -EINVAL;
3e46f152
RK		 765
766 switch (res) {
767 case 0: /* color resolution 0 is 8 bit colour depth */
768 case 8:
b21f4b65 769 res_idx = DW_HDMI_RES_8;
3e46f152
RK		 770 break;
771 case 10:
b21f4b65 772 res_idx = DW_HDMI_RES_10;
3e46f152
RK		 773 break;
774 case 12:
b21f4b65 775 res_idx = DW_HDMI_RES_12;
3e46f152
RK		 776 break;
777 default:
9aaf880e 778 return -EINVAL;
3e46f152 779 }
9aaf880e 780
39cc1535
RK		 781 /* PLL/MPLL Cfg - always match on final entry */
782 for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
783 if (hdmi->hdmi_data.video_mode.mpixelclock <=
784 mpll_config->mpixelclock)
785 break;
786
787 for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
788 if (hdmi->hdmi_data.video_mode.mpixelclock <=
789 curr_ctrl->mpixelclock)
790 break;
791
792 for (; phy_config->mpixelclock != ~0UL; phy_config++)
793 if (hdmi->hdmi_data.video_mode.mpixelclock <=
794 phy_config->mpixelclock)
795 break;
796
797 if (mpll_config->mpixelclock == ~0UL ||
798 curr_ctrl->mpixelclock == ~0UL ||
799 phy_config->mpixelclock == ~0UL) {
800 dev_err(hdmi->dev, "Pixel clock %d - unsupported by HDMI\n",
801 hdmi->hdmi_data.video_mode.mpixelclock);
802 return -EINVAL;
803 }
804
9aaf880e
FE		 805 /* Enable csc path */
806 if (cscon)
807 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH;
808 else
809 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS;
810
811 hdmi_writeb(hdmi, val, HDMI_MC_FLOWCTRL);
812
813 /* gen2 tx power off */
b21f4b65 814 dw_hdmi_phy_gen2_txpwron(hdmi, 0);
9aaf880e
FE		 815
816 /* gen2 pddq */
b21f4b65 817 dw_hdmi_phy_gen2_pddq(hdmi, 1);
9aaf880e
FE		 818
819 /* PHY reset */
820 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
821 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ);
822
823 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
824
825 hdmi_phy_test_clear(hdmi, 1);
826 hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
b5878339 827 HDMI_PHY_I2CM_SLAVE_ADDR);
9aaf880e
FE		 828 hdmi_phy_test_clear(hdmi, 0);
829
39cc1535
RK		 830 hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].cpce, 0x06);
831 hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].gmp, 0x15);
9aaf880e 832
3e46f152 833 /* CURRCTRL */
39cc1535 834 hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[res_idx], 0x10);
3e46f152 835
9aaf880e
FE		 836 hdmi_phy_i2c_write(hdmi, 0x0000, 0x13); /* PLLPHBYCTRL */
837 hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
aaa757a0 838
39cc1535
RK		 839 hdmi_phy_i2c_write(hdmi, phy_config->term, 0x19); /* TXTERM */
840 hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 0x09); /* CKSYMTXCTRL */
841 hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 0x0E); /* VLEVCTRL */
034705a4 842
9aaf880e
FE		 843 /* REMOVE CLK TERM */
844 hdmi_phy_i2c_write(hdmi, 0x8000, 0x05); /* CKCALCTRL */
845
b21f4b65 846 dw_hdmi_phy_enable_power(hdmi, 1);
9aaf880e
FE		 847
848 /* toggle TMDS enable */
b21f4b65
AY		 849 dw_hdmi_phy_enable_tmds(hdmi, 0);
850 dw_hdmi_phy_enable_tmds(hdmi, 1);
9aaf880e
FE		 851
852 /* gen2 tx power on */
b21f4b65
AY		 853 dw_hdmi_phy_gen2_txpwron(hdmi, 1);
854 dw_hdmi_phy_gen2_pddq(hdmi, 0);
9aaf880e 855
12b9f204
AY		 856 if (hdmi->dev_type == RK3288_HDMI)
857 dw_hdmi_phy_enable_spare(hdmi, 1);
858
9aaf880e
FE		 859 /*Wait for PHY PLL lock */
860 msec = 5;
861 do {
862 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
863 if (!val)
864 break;
865
866 if (msec == 0) {
867 dev_err(hdmi->dev, "PHY PLL not locked\n");
868 return -ETIMEDOUT;
869 }
870
871 udelay(1000);
872 msec--;
873 } while (1);
874
875 return 0;
876}
877
b21f4b65 878static int dw_hdmi_phy_init(struct dw_hdmi *hdmi)
9aaf880e
FE		 879{
880 int i, ret;
881 bool cscon = false;
882
883 /*check csc whether needed activated in HDMI mode */
884 cscon = (is_color_space_conversion(hdmi) &&
885 !hdmi->hdmi_data.video_mode.mdvi);
886
887 /* HDMI Phy spec says to do the phy initialization sequence twice */
888 for (i = 0; i < 2; i++) {
b21f4b65
AY		 889 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
890 dw_hdmi_phy_sel_interface_control(hdmi, 0);
891 dw_hdmi_phy_enable_tmds(hdmi, 0);
892 dw_hdmi_phy_enable_power(hdmi, 0);
9aaf880e
FE		 893
894 /* Enable CSC */
895 ret = hdmi_phy_configure(hdmi, 0, 8, cscon);
896 if (ret)
897 return ret;
898 }
899
900 hdmi->phy_enabled = true;
901 return 0;
902}
903
b21f4b65 904static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
9aaf880e 905{
812bc615 906 u8 de;
9aaf880e
FE		 907
908 if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
909 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
910 else
911 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
912
913 /* disable rx detect */
812bc615
RK		 914 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
915 HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
9aaf880e 916
812bc615 917 hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
9aaf880e 918
812bc615
RK		 919 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
920 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
9aaf880e
FE		 921}
922
b21f4b65 923static void hdmi_config_AVI(struct dw_hdmi *hdmi)
9aaf880e
FE		 924{
925 u8 val, pix_fmt, under_scan;
926 u8 act_ratio, coded_ratio, colorimetry, ext_colorimetry;
927 bool aspect_16_9;
928
929 aspect_16_9 = false; /* FIXME */
930
931 /* AVI Data Byte 1 */
932 if (hdmi->hdmi_data.enc_out_format == YCBCR444)
933 pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_YCBCR444;
934 else if (hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS)
935 pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_YCBCR422;
936 else
937 pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_RGB;
938
939 under_scan = HDMI_FC_AVICONF0_SCAN_INFO_NODATA;
940
941 /*
942 * Active format identification data is present in the AVI InfoFrame.
943 * Under scan info, no bar data
944 */
945 val = pix_fmt | under_scan |
946 HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT |
947 HDMI_FC_AVICONF0_BAR_DATA_NO_DATA;
948
949 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
950
951 /* AVI Data Byte 2 -Set the Aspect Ratio */
952 if (aspect_16_9) {
953 act_ratio = HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9;
954 coded_ratio = HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9;
955 } else {
956 act_ratio = HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3;
957 coded_ratio = HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3;
958 }
959
960 /* Set up colorimetry */
961 if (hdmi->hdmi_data.enc_out_format == XVYCC444) {
962 colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO;
5a819ed6 963 if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
9aaf880e
FE		 964 ext_colorimetry =
965 HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601;
5a819ed6 966 else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/
9aaf880e
FE		 967 ext_colorimetry =
968 HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709;
969 } else if (hdmi->hdmi_data.enc_out_format != RGB) {
5a819ed6 970 if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
9aaf880e 971 colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_SMPTE;
5a819ed6 972 else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/
9aaf880e
FE		 973 colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_ITUR;
974 ext_colorimetry = HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601;
975 } else { /* Carries no data */
976 colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA;
977 ext_colorimetry = HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601;
978 }
979
980 val = colorimetry | coded_ratio | act_ratio;
981 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
982
983 /* AVI Data Byte 3 */
984 val = HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA | ext_colorimetry |
985 HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT |
986 HDMI_FC_AVICONF2_SCALING_NONE;
987 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
988
989 /* AVI Data Byte 4 */
990 hdmi_writeb(hdmi, hdmi->vic, HDMI_FC_AVIVID);
991
992 /* AVI Data Byte 5- set up input and output pixel repetition */
993 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
994 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
995 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
996 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
997 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
998 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
999 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
1000
1001 /* IT Content and quantization range = don't care */
1002 val = HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS |
1003 HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED;
1004 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1005
1006 /* AVI Data Bytes 6-13 */
1007 hdmi_writeb(hdmi, 0, HDMI_FC_AVIETB0);
1008 hdmi_writeb(hdmi, 0, HDMI_FC_AVIETB1);
1009 hdmi_writeb(hdmi, 0, HDMI_FC_AVISBB0);
1010 hdmi_writeb(hdmi, 0, HDMI_FC_AVISBB1);
1011 hdmi_writeb(hdmi, 0, HDMI_FC_AVIELB0);
1012 hdmi_writeb(hdmi, 0, HDMI_FC_AVIELB1);
1013 hdmi_writeb(hdmi, 0, HDMI_FC_AVISRB0);
1014 hdmi_writeb(hdmi, 0, HDMI_FC_AVISRB1);
1015}
1016
b21f4b65 1017static void hdmi_av_composer(struct dw_hdmi *hdmi,
9aaf880e
FE		 1018 const struct drm_display_mode *mode)
1019{
1020 u8 inv_val;
1021 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1022 int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
1023
1024 vmode->mhsyncpolarity = !!(mode->flags & DRM_MODE_FLAG_PHSYNC);
1025 vmode->mvsyncpolarity = !!(mode->flags & DRM_MODE_FLAG_PVSYNC);
1026 vmode->minterlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
1027 vmode->mpixelclock = mode->clock * 1000;
1028
1029 dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1030
1031 /* Set up HDMI_FC_INVIDCONF */
1032 inv_val = (hdmi->hdmi_data.hdcp_enable ?
1033 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1034 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1035
1036 inv_val |= (vmode->mvsyncpolarity ?
1037 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
1038 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW);
1039
1040 inv_val |= (vmode->mhsyncpolarity ?
1041 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
1042 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW);
1043
1044 inv_val |= (vmode->mdataenablepolarity ?
1045 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1046 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1047
1048 if (hdmi->vic == 39)
1049 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1050 else
1051 inv_val |= (vmode->minterlaced ?
1052 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
1053 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW);
1054
1055 inv_val |= (vmode->minterlaced ?
1056 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
1057 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE);
1058
1059 inv_val |= (vmode->mdvi ?
1060 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE :
1061 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE);
1062
1063 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1064
1065 /* Set up horizontal active pixel width */
1066 hdmi_writeb(hdmi, mode->hdisplay >> 8, HDMI_FC_INHACTV1);
1067 hdmi_writeb(hdmi, mode->hdisplay, HDMI_FC_INHACTV0);
1068
1069 /* Set up vertical active lines */
1070 hdmi_writeb(hdmi, mode->vdisplay >> 8, HDMI_FC_INVACTV1);
1071 hdmi_writeb(hdmi, mode->vdisplay, HDMI_FC_INVACTV0);
1072
1073 /* Set up horizontal blanking pixel region width */
1074 hblank = mode->htotal - mode->hdisplay;
1075 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1076 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1077
1078 /* Set up vertical blanking pixel region width */
1079 vblank = mode->vtotal - mode->vdisplay;
1080 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1081
1082 /* Set up HSYNC active edge delay width (in pixel clks) */
1083 h_de_hs = mode->hsync_start - mode->hdisplay;
1084 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1085 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1086
1087 /* Set up VSYNC active edge delay (in lines) */
1088 v_de_vs = mode->vsync_start - mode->vdisplay;
1089 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1090
1091 /* Set up HSYNC active pulse width (in pixel clks) */
1092 hsync_len = mode->hsync_end - mode->hsync_start;
1093 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1094 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1095
1096 /* Set up VSYNC active edge delay (in lines) */
1097 vsync_len = mode->vsync_end - mode->vsync_start;
1098 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1099}
1100
b21f4b65 1101static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi)
9aaf880e
FE		 1102{
1103 if (!hdmi->phy_enabled)
1104 return;
1105
b21f4b65
AY		 1106 dw_hdmi_phy_enable_tmds(hdmi, 0);
1107 dw_hdmi_phy_enable_power(hdmi, 0);
9aaf880e
FE		 1108
1109 hdmi->phy_enabled = false;
1110}
1111
1112/* HDMI Initialization Step B.4 */
b21f4b65 1113static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
9aaf880e
FE		 1114{
1115 u8 clkdis;
1116
1117 /* control period minimum duration */
1118 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1119 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1120 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1121
1122 /* Set to fill TMDS data channels */
1123 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1124 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1125 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1126
1127 /* Enable pixel clock and tmds data path */
1128 clkdis = 0x7F;
1129 clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1130 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1131
1132 clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1133 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1134
1135 /* Enable csc path */
1136 if (is_color_space_conversion(hdmi)) {
1137 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1138 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1139 }
1140}
1141
b21f4b65 1142static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi)
9aaf880e 1143{
812bc615 1144 hdmi_modb(hdmi, 0, HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS);
9aaf880e
FE		 1145}
1146
1147/* Workaround to clear the overflow condition */
b21f4b65 1148static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
9aaf880e
FE		 1149{
1150 int count;
1151 u8 val;
1152
1153 /* TMDS software reset */
1154 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1155
1156 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
1157 if (hdmi->dev_type == IMX6DL_HDMI) {
1158 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1159 return;
1160 }
1161
1162 for (count = 0; count < 4; count++)
1163 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1164}
1165
b21f4b65 1166static void hdmi_enable_overflow_interrupts(struct dw_hdmi *hdmi)
9aaf880e
FE		 1167{
1168 hdmi_writeb(hdmi, 0, HDMI_FC_MASK2);
1169 hdmi_writeb(hdmi, 0, HDMI_IH_MUTE_FC_STAT2);
1170}
1171
b21f4b65 1172static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
9aaf880e
FE		 1173{
1174 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1175 HDMI_IH_MUTE_FC_STAT2);
1176}
1177
b21f4b65 1178static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
9aaf880e
FE		 1179{
1180 int ret;
1181
1182 hdmi_disable_overflow_interrupts(hdmi);
1183
1184 hdmi->vic = drm_match_cea_mode(mode);
1185
1186 if (!hdmi->vic) {
1187 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
1188 hdmi->hdmi_data.video_mode.mdvi = true;
1189 } else {
1190 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
1191 hdmi->hdmi_data.video_mode.mdvi = false;
1192 }
1193
1194 if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
b5878339
AY		 1195 (hdmi->vic == 21) || (hdmi->vic == 22) ||
1196 (hdmi->vic == 2) || (hdmi->vic == 3) ||
1197 (hdmi->vic == 17) || (hdmi->vic == 18))
5a819ed6 1198 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601;
9aaf880e 1199 else
5a819ed6 1200 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709;
9aaf880e
FE		 1201
1202 if ((hdmi->vic == 10) || (hdmi->vic == 11) ||
b5878339
AY		 1203 (hdmi->vic == 12) || (hdmi->vic == 13) ||
1204 (hdmi->vic == 14) || (hdmi->vic == 15) ||
1205 (hdmi->vic == 25) || (hdmi->vic == 26) ||
1206 (hdmi->vic == 27) || (hdmi->vic == 28) ||
1207 (hdmi->vic == 29) || (hdmi->vic == 30) ||
1208 (hdmi->vic == 35) || (hdmi->vic == 36) ||
1209 (hdmi->vic == 37) || (hdmi->vic == 38))
9aaf880e
FE		 1210 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 1;
1211 else
1212 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
1213
1214 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
1215
1216 /* TODO: Get input format from IPU (via FB driver interface) */
1217 hdmi->hdmi_data.enc_in_format = RGB;
1218
1219 hdmi->hdmi_data.enc_out_format = RGB;
1220
1221 hdmi->hdmi_data.enc_color_depth = 8;
1222 hdmi->hdmi_data.pix_repet_factor = 0;
1223 hdmi->hdmi_data.hdcp_enable = 0;
1224 hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
1225
1226 /* HDMI Initialization Step B.1 */
1227 hdmi_av_composer(hdmi, mode);
1228
1229 /* HDMI Initializateion Step B.2 */
b21f4b65 1230 ret = dw_hdmi_phy_init(hdmi);
9aaf880e
FE		 1231 if (ret)
1232 return ret;
1233
1234 /* HDMI Initialization Step B.3 */
b21f4b65 1235 dw_hdmi_enable_video_path(hdmi);
9aaf880e
FE		 1236
1237 /* not for DVI mode */
b5878339 1238 if (hdmi->hdmi_data.video_mode.mdvi) {
9aaf880e 1239 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
b5878339 1240 } else {
9aaf880e
FE		 1241 dev_dbg(hdmi->dev, "%s CEA mode\n", __func__);
1242
1243 /* HDMI Initialization Step E - Configure audio */
1244 hdmi_clk_regenerator_update_pixel_clock(hdmi);
1245 hdmi_enable_audio_clk(hdmi);
1246
1247 /* HDMI Initialization Step F - Configure AVI InfoFrame */
1248 hdmi_config_AVI(hdmi);
1249 }
1250
1251 hdmi_video_packetize(hdmi);
1252 hdmi_video_csc(hdmi);
1253 hdmi_video_sample(hdmi);
1254 hdmi_tx_hdcp_config(hdmi);
1255
b21f4b65 1256 dw_hdmi_clear_overflow(hdmi);
9aaf880e
FE		 1257 if (hdmi->cable_plugin && !hdmi->hdmi_data.video_mode.mdvi)
1258 hdmi_enable_overflow_interrupts(hdmi);
1259
1260 return 0;
1261}
1262
1263/* Wait until we are registered to enable interrupts */
b21f4b65 1264static int dw_hdmi_fb_registered(struct dw_hdmi *hdmi)
9aaf880e
FE		 1265{
1266 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
1267 HDMI_PHY_I2CM_INT_ADDR);
1268
1269 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
1270 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
1271 HDMI_PHY_I2CM_CTLINT_ADDR);
1272
1273 /* enable cable hot plug irq */
1274 hdmi_writeb(hdmi, (u8)~HDMI_PHY_HPD, HDMI_PHY_MASK0);
1275
1276 /* Clear Hotplug interrupts */
1277 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
1278
9aaf880e
FE		 1279 return 0;
1280}
1281
b21f4b65 1282static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
9aaf880e
FE		 1283{
1284 u8 ih_mute;
1285
1286 /*
1287 * Boot up defaults are:
1288 * HDMI_IH_MUTE = 0x03 (disabled)
1289 * HDMI_IH_MUTE_* = 0x00 (enabled)
1290 *
1291 * Disable top level interrupt bits in HDMI block
1292 */
1293 ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
1294 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1295 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
1296
1297 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1298
1299 /* by default mask all interrupts */
1300 hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
1301 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
1302 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
1303 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
1304 hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
1305 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
1306 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
1307 hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
1308 hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
1309 hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
1310 hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
1311 hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
1312 hdmi_writeb(hdmi, 0xff, HDMI_CEC_MASK);
1313 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
1314 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
1315
1316 /* Disable interrupts in the IH_MUTE_* registers */
1317 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
1318 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
1319 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
1320 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
1321 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
1322 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
1323 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
1324 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
1325 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
1326 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
1327
1328 /* Enable top level interrupt bits in HDMI block */
1329 ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1330 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
1331 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1332}
1333
b21f4b65 1334static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
9aaf880e 1335{
b21f4b65 1336 dw_hdmi_setup(hdmi, &hdmi->previous_mode);
9aaf880e
FE		 1337}
1338
b21f4b65 1339static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
9aaf880e 1340{
b21f4b65 1341 dw_hdmi_phy_disable(hdmi);
9aaf880e
FE		 1342}
1343
b21f4b65 1344static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
eb10d635
SL		 1345 struct drm_display_mode *orig_mode,
1346 struct drm_display_mode *mode)
3d1b35a3 1347{
b21f4b65 1348 struct dw_hdmi *hdmi = bridge->driver_private;
3d1b35a3 1349
b21f4b65 1350 dw_hdmi_setup(hdmi, mode);
3d1b35a3
AY		 1351
1352 /* Store the display mode for plugin/DKMS poweron events */
1353 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
1354}
1355
b21f4b65
AY		 1356static bool dw_hdmi_bridge_mode_fixup(struct drm_bridge *bridge,
1357 const struct drm_display_mode *mode,
1358 struct drm_display_mode *adjusted_mode)
3d1b35a3
AY		 1359{
1360 return true;
1361}
1362
b21f4b65 1363static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
3d1b35a3 1364{
b21f4b65 1365 struct dw_hdmi *hdmi = bridge->driver_private;
3d1b35a3 1366
b21f4b65 1367 dw_hdmi_poweroff(hdmi);
3d1b35a3
AY		 1368}
1369
b21f4b65 1370static void dw_hdmi_bridge_enable(struct drm_bridge *bridge)
3d1b35a3 1371{
b21f4b65 1372 struct dw_hdmi *hdmi = bridge->driver_private;
3d1b35a3 1373
b21f4b65 1374 dw_hdmi_poweron(hdmi);
3d1b35a3
AY		 1375}
1376
b21f4b65 1377static void dw_hdmi_bridge_nop(struct drm_bridge *bridge)
3d1b35a3
AY		 1378{
1379 /* do nothing */
1380}
1381
b21f4b65
AY		 1382static enum drm_connector_status
1383dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
9aaf880e 1384{
b21f4b65 1385 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
d94905e0 1386 connector);
98dbeada
RK		 1387
1388 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1389 connector_status_connected : connector_status_disconnected;
9aaf880e
FE		 1390}
1391
b21f4b65 1392static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
9aaf880e 1393{
b21f4b65 1394 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
9aaf880e
FE		 1395 connector);
1396 struct edid *edid;
1397 int ret;
1398
1399 if (!hdmi->ddc)
1400 return 0;
1401
1402 edid = drm_get_edid(connector, hdmi->ddc);
1403 if (edid) {
1404 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
1405 edid->width_cm, edid->height_cm);
1406
1407 drm_mode_connector_update_edid_property(connector, edid);
1408 ret = drm_add_edid_modes(connector, edid);
1409 kfree(edid);
1410 } else {
1411 dev_dbg(hdmi->dev, "failed to get edid\n");
1412 }
1413
1414 return 0;
1415}
1416
632d035b
AY		 1417static enum drm_mode_status
1418dw_hdmi_connector_mode_valid(struct drm_connector *connector,
1419 struct drm_display_mode *mode)
1420{
1421 struct dw_hdmi *hdmi = container_of(connector,
1422 struct dw_hdmi, connector);
1423 enum drm_mode_status mode_status = MODE_OK;
1424
1425 if (hdmi->plat_data->mode_valid)
1426 mode_status = hdmi->plat_data->mode_valid(connector, mode);
1427
1428 return mode_status;
1429}
1430
b21f4b65 1431static struct drm_encoder *dw_hdmi_connector_best_encoder(struct drm_connector
9aaf880e
FE		 1432 *connector)
1433{
b21f4b65 1434 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
9aaf880e
FE		 1435 connector);
1436
3d1b35a3 1437 return hdmi->encoder;
9aaf880e
FE		 1438}
1439
b21f4b65 1440static void dw_hdmi_connector_destroy(struct drm_connector *connector)
9aaf880e 1441{
3d1b35a3
AY		 1442 drm_connector_unregister(connector);
1443 drm_connector_cleanup(connector);
9aaf880e
FE		 1444}
1445
b21f4b65 1446static struct drm_connector_funcs dw_hdmi_connector_funcs = {
9aaf880e
FE		 1447 .dpms = drm_helper_connector_dpms,
1448 .fill_modes = drm_helper_probe_single_connector_modes,
b21f4b65
AY		 1449 .detect = dw_hdmi_connector_detect,
1450 .destroy = dw_hdmi_connector_destroy,
9aaf880e
FE		 1451};
1452
b21f4b65
AY		 1453static struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
1454 .get_modes = dw_hdmi_connector_get_modes,
632d035b 1455 .mode_valid = dw_hdmi_connector_mode_valid,
b21f4b65 1456 .best_encoder = dw_hdmi_connector_best_encoder,
9aaf880e
FE		 1457};
1458
b21f4b65
AY		 1459struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
1460 .enable = dw_hdmi_bridge_enable,
1461 .disable = dw_hdmi_bridge_disable,
1462 .pre_enable = dw_hdmi_bridge_nop,
1463 .post_disable = dw_hdmi_bridge_nop,
1464 .mode_set = dw_hdmi_bridge_mode_set,
1465 .mode_fixup = dw_hdmi_bridge_mode_fixup,
3d1b35a3
AY		 1466};
1467
b21f4b65 1468static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
d94905e0 1469{
b21f4b65 1470 struct dw_hdmi *hdmi = dev_id;
d94905e0
RK		 1471 u8 intr_stat;
1472
1473 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1474 if (intr_stat)
1475 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
1476
1477 return intr_stat ? IRQ_WAKE_THREAD : IRQ_NONE;
1478}
1479
b21f4b65 1480static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
9aaf880e 1481{
b21f4b65 1482 struct dw_hdmi *hdmi = dev_id;
9aaf880e
FE		 1483 u8 intr_stat;
1484 u8 phy_int_pol;
9aaf880e
FE		 1485
1486 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1487
1488 phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
1489
1490 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
1491 if (phy_int_pol & HDMI_PHY_HPD) {
1492 dev_dbg(hdmi->dev, "EVENT=plugin\n");
1493
812bc615 1494 hdmi_modb(hdmi, 0, HDMI_PHY_HPD, HDMI_PHY_POL0);
9aaf880e 1495
b21f4b65 1496 dw_hdmi_poweron(hdmi);
9aaf880e
FE		 1497 } else {
1498 dev_dbg(hdmi->dev, "EVENT=plugout\n");
1499
256a38b0 1500 hdmi_modb(hdmi, HDMI_PHY_HPD, HDMI_PHY_HPD,
b5878339 1501 HDMI_PHY_POL0);
9aaf880e 1502
b21f4b65 1503 dw_hdmi_poweroff(hdmi);
9aaf880e 1504 }
d94905e0 1505 drm_helper_hpd_irq_event(hdmi->connector.dev);
9aaf880e
FE		 1506 }
1507
1508 hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
d94905e0 1509 hdmi_writeb(hdmi, ~HDMI_IH_PHY_STAT0_HPD, HDMI_IH_MUTE_PHY_STAT0);
9aaf880e
FE		 1510
1511 return IRQ_HANDLED;
1512}
1513
b21f4b65 1514static int dw_hdmi_register(struct drm_device *drm, struct dw_hdmi *hdmi)
9aaf880e 1515{
3d1b35a3
AY		 1516 struct drm_encoder *encoder = hdmi->encoder;
1517 struct drm_bridge *bridge;
9aaf880e
FE		 1518 int ret;
1519
3d1b35a3
AY		 1520 bridge = devm_kzalloc(drm->dev, sizeof(*bridge), GFP_KERNEL);
1521 if (!bridge) {
1522 DRM_ERROR("Failed to allocate drm bridge\n");
1523 return -ENOMEM;
1524 }
9aaf880e 1525
3d1b35a3
AY		 1526 hdmi->bridge = bridge;
1527 bridge->driver_private = hdmi;
b5217bf4
FE		 1528 bridge->funcs = &dw_hdmi_bridge_funcs;
1529 ret = drm_bridge_attach(drm, bridge);
3d1b35a3
AY		 1530 if (ret) {
1531 DRM_ERROR("Failed to initialize bridge with drm\n");
1532 return -EINVAL;
1533 }
9aaf880e 1534
3d1b35a3
AY		 1535 encoder->bridge = bridge;
1536 hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
9aaf880e
FE		 1537
1538 drm_connector_helper_add(&hdmi->connector,
b21f4b65
AY		 1539 &dw_hdmi_connector_helper_funcs);
1540 drm_connector_init(drm, &hdmi->connector, &dw_hdmi_connector_funcs,
1b3f7675 1541 DRM_MODE_CONNECTOR_HDMIA);
9aaf880e 1542
3d1b35a3 1543 hdmi->connector.encoder = encoder;
9aaf880e 1544
3d1b35a3 1545 drm_mode_connector_attach_encoder(&hdmi->connector, encoder);
9aaf880e
FE		 1546
1547 return 0;
1548}
1549
b21f4b65 1550int dw_hdmi_bind(struct device *dev, struct device *master,
3d1b35a3
AY		 1551 void *data, struct drm_encoder *encoder,
1552 struct resource *iores, int irq,
1553 const struct dw_hdmi_plat_data *plat_data)
9aaf880e 1554{
1b3f7675 1555 struct drm_device *drm = data;
17b5001b 1556 struct device_node *np = dev->of_node;
9aaf880e 1557 struct device_node *ddc_node;
b21f4b65 1558 struct dw_hdmi *hdmi;
3d1b35a3 1559 int ret;
0cd9d142 1560 u32 val = 1;
9aaf880e 1561
17b5001b 1562 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
9aaf880e
FE		 1563 if (!hdmi)
1564 return -ENOMEM;
1565
3d1b35a3 1566 hdmi->plat_data = plat_data;
17b5001b 1567 hdmi->dev = dev;
3d1b35a3 1568 hdmi->dev_type = plat_data->dev_type;
40678388
RK		 1569 hdmi->sample_rate = 48000;
1570 hdmi->ratio = 100;
3d1b35a3 1571 hdmi->encoder = encoder;
9aaf880e 1572
6bcf4953
RK		 1573 mutex_init(&hdmi->audio_mutex);
1574
0cd9d142
AY		 1575 of_property_read_u32(np, "reg-io-width", &val);
1576
1577 switch (val) {
1578 case 4:
1579 hdmi->write = dw_hdmi_writel;
1580 hdmi->read = dw_hdmi_readl;
1581 break;
1582 case 1:
1583 hdmi->write = dw_hdmi_writeb;
1584 hdmi->read = dw_hdmi_readb;
1585 break;
1586 default:
1587 dev_err(dev, "reg-io-width must be 1 or 4\n");
1588 return -EINVAL;
1589 }
1590
b5d45901 1591 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
9aaf880e
FE		 1592 if (ddc_node) {
1593 hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
c2c38488
AY		 1594 of_node_put(ddc_node);
1595 if (!hdmi->ddc) {
9aaf880e 1596 dev_dbg(hdmi->dev, "failed to read ddc node\n");
c2c38488
AY		 1597 return -EPROBE_DEFER;
1598 }
9aaf880e 1599
9aaf880e
FE		 1600 } else {
1601 dev_dbg(hdmi->dev, "no ddc property found\n");
1602 }
1603
17b5001b 1604 hdmi->regs = devm_ioremap_resource(dev, iores);
9aaf880e
FE		 1605 if (IS_ERR(hdmi->regs))
1606 return PTR_ERR(hdmi->regs);
1607
9aaf880e
FE		 1608 hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
1609 if (IS_ERR(hdmi->isfr_clk)) {
1610 ret = PTR_ERR(hdmi->isfr_clk);
b5878339 1611 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
9aaf880e
FE		 1612 return ret;
1613 }
1614
1615 ret = clk_prepare_enable(hdmi->isfr_clk);
1616 if (ret) {
b5878339 1617 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
9aaf880e
FE		 1618 return ret;
1619 }
1620
1621 hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
1622 if (IS_ERR(hdmi->iahb_clk)) {
1623 ret = PTR_ERR(hdmi->iahb_clk);
b5878339 1624 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
9aaf880e
FE		 1625 goto err_isfr;
1626 }
1627
1628 ret = clk_prepare_enable(hdmi->iahb_clk);
1629 if (ret) {
b5878339 1630 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
9aaf880e
FE		 1631 goto err_isfr;
1632 }
1633
1634 /* Product and revision IDs */
17b5001b 1635 dev_info(dev,
b5878339
AY		 1636 "Detected HDMI controller 0x%x:0x%x:0x%x:0x%x\n",
1637 hdmi_readb(hdmi, HDMI_DESIGN_ID),
1638 hdmi_readb(hdmi, HDMI_REVISION_ID),
1639 hdmi_readb(hdmi, HDMI_PRODUCT_ID0),
1640 hdmi_readb(hdmi, HDMI_PRODUCT_ID1));
9aaf880e
FE		 1641
1642 initialize_hdmi_ih_mutes(hdmi);
1643
639a202c
PZ		 1644 ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
1645 dw_hdmi_irq, IRQF_SHARED,
1646 dev_name(dev), hdmi);
1647 if (ret)
b33ef619 1648 goto err_iahb;
639a202c 1649
9aaf880e
FE		 1650 /*
1651 * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
1652 * N and cts values before enabling phy
1653 */
1654 hdmi_init_clk_regenerator(hdmi);
1655
1656 /*
1657 * Configure registers related to HDMI interrupt
1658 * generation before registering IRQ.
1659 */
1660 hdmi_writeb(hdmi, HDMI_PHY_HPD, HDMI_PHY_POL0);
1661
1662 /* Clear Hotplug interrupts */
1663 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
1664
b21f4b65 1665 ret = dw_hdmi_fb_registered(hdmi);
9aaf880e
FE		 1666 if (ret)
1667 goto err_iahb;
1668
b21f4b65 1669 ret = dw_hdmi_register(drm, hdmi);
9aaf880e
FE		 1670 if (ret)
1671 goto err_iahb;
1672
d94905e0
RK		 1673 /* Unmute interrupts */
1674 hdmi_writeb(hdmi, ~HDMI_IH_PHY_STAT0_HPD, HDMI_IH_MUTE_PHY_STAT0);
9aaf880e 1675
17b5001b 1676 dev_set_drvdata(dev, hdmi);
9aaf880e
FE		 1677
1678 return 0;
1679
1680err_iahb:
1681 clk_disable_unprepare(hdmi->iahb_clk);
1682err_isfr:
1683 clk_disable_unprepare(hdmi->isfr_clk);
1684
1685 return ret;
1686}
b21f4b65 1687EXPORT_SYMBOL_GPL(dw_hdmi_bind);
9aaf880e 1688
b21f4b65 1689void dw_hdmi_unbind(struct device *dev, struct device *master, void *data)
9aaf880e 1690{
b21f4b65 1691 struct dw_hdmi *hdmi = dev_get_drvdata(dev);
9aaf880e 1692
d94905e0
RK		 1693 /* Disable all interrupts */
1694 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
1695
1b3f7675 1696 hdmi->connector.funcs->destroy(&hdmi->connector);
3d1b35a3 1697 hdmi->encoder->funcs->destroy(hdmi->encoder);
9aaf880e
FE		 1698
1699 clk_disable_unprepare(hdmi->iahb_clk);
1700 clk_disable_unprepare(hdmi->isfr_clk);
1701 i2c_put_adapter(hdmi->ddc);
17b5001b 1702}
b21f4b65 1703EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
9aaf880e
FE		 1704
1705MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
3d1b35a3
AY		 1706MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
1707MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
b21f4b65 1708MODULE_DESCRIPTION("DW HDMI transmitter driver");
9aaf880e 1709MODULE_LICENSE("GPL");
b21f4b65 1710MODULE_ALIAS("platform:dw-hdmi");
Linux 6.x block layer and io_uring tree(s)