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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/hid
[linux-2.6-block.git] / drivers / gpu / drm / bridge / dw_hdmi.c
CommitLineData
9aaf880e
FE		 1/*
2 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
b21f4b65 9 * Designware High-Definition Multimedia Interface (HDMI) driver
9aaf880e
FE		 10 *
11 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
12 */
b21f4b65 13#include <linux/module.h>
9aaf880e
FE		 14#include <linux/irq.h>
15#include <linux/delay.h>
16#include <linux/err.h>
17#include <linux/clk.h>
5a819ed6 18#include <linux/hdmi.h>
6bcf4953 19#include <linux/mutex.h>
9aaf880e 20#include <linux/of_device.h>
b90120a9 21#include <linux/spinlock.h>
9aaf880e 22
3d1b35a3 23#include <drm/drm_of.h>
9aaf880e
FE		 24#include <drm/drmP.h>
25#include <drm/drm_crtc_helper.h>
26#include <drm/drm_edid.h>
27#include <drm/drm_encoder_slave.h>
b21f4b65 28#include <drm/bridge/dw_hdmi.h>
9aaf880e 29
b21f4b65 30#include "dw_hdmi.h"
7ed6c665 31#include "dw_hdmi-audio.h"
9aaf880e
FE		 32
33#define HDMI_EDID_LEN 512
34
35#define RGB 0
36#define YCBCR444 1
37#define YCBCR422_16BITS 2
38#define YCBCR422_8BITS 3
39#define XVYCC444 4
40
41enum hdmi_datamap {
42 RGB444_8B = 0x01,
43 RGB444_10B = 0x03,
44 RGB444_12B = 0x05,
45 RGB444_16B = 0x07,
46 YCbCr444_8B = 0x09,
47 YCbCr444_10B = 0x0B,
48 YCbCr444_12B = 0x0D,
49 YCbCr444_16B = 0x0F,
50 YCbCr422_8B = 0x16,
51 YCbCr422_10B = 0x14,
52 YCbCr422_12B = 0x12,
53};
54
9aaf880e
FE		 55static const u16 csc_coeff_default[3][4] = {
56 { 0x2000, 0x0000, 0x0000, 0x0000 },
57 { 0x0000, 0x2000, 0x0000, 0x0000 },
58 { 0x0000, 0x0000, 0x2000, 0x0000 }
59};
60
61static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
62 { 0x2000, 0x6926, 0x74fd, 0x010e },
63 { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
64 { 0x2000, 0x0000, 0x38b4, 0x7e3b }
65};
66
67static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
68 { 0x2000, 0x7106, 0x7a02, 0x00a7 },
69 { 0x2000, 0x3264, 0x0000, 0x7e6d },
70 { 0x2000, 0x0000, 0x3b61, 0x7e25 }
71};
72
73static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
74 { 0x2591, 0x1322, 0x074b, 0x0000 },
75 { 0x6535, 0x2000, 0x7acc, 0x0200 },
76 { 0x6acd, 0x7534, 0x2000, 0x0200 }
77};
78
79static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
80 { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
81 { 0x62f0, 0x2000, 0x7d11, 0x0200 },
82 { 0x6756, 0x78ab, 0x2000, 0x0200 }
83};
84
85struct hdmi_vmode {
9aaf880e
FE		 86 bool mdataenablepolarity;
87
88 unsigned int mpixelclock;
89 unsigned int mpixelrepetitioninput;
90 unsigned int mpixelrepetitionoutput;
91};
92
93struct hdmi_data_info {
94 unsigned int enc_in_format;
95 unsigned int enc_out_format;
96 unsigned int enc_color_depth;
97 unsigned int colorimetry;
98 unsigned int pix_repet_factor;
99 unsigned int hdcp_enable;
100 struct hdmi_vmode video_mode;
101};
102
b21f4b65 103struct dw_hdmi {
9aaf880e 104 struct drm_connector connector;
3d1b35a3
AY		 105 struct drm_encoder *encoder;
106 struct drm_bridge *bridge;
9aaf880e 107
7ed6c665 108 struct platform_device *audio;
b21f4b65 109 enum dw_hdmi_devtype dev_type;
9aaf880e
FE		 110 struct device *dev;
111 struct clk *isfr_clk;
112 struct clk *iahb_clk;
113
114 struct hdmi_data_info hdmi_data;
b21f4b65
AY		 115 const struct dw_hdmi_plat_data *plat_data;
116
9aaf880e
FE		 117 int vic;
118
119 u8 edid[HDMI_EDID_LEN];
120 bool cable_plugin;
121
122 bool phy_enabled;
123 struct drm_display_mode previous_mode;
124
9aaf880e
FE		 125 struct i2c_adapter *ddc;
126 void __iomem *regs;
05b1342f 127 bool sink_is_hdmi;
f709ec07 128 bool sink_has_audio;
9aaf880e 129
b872a8e1 130 struct mutex mutex; /* for state below and previous_mode */
381f05a7 131 enum drm_connector_force force; /* mutex-protected force state */
b872a8e1 132 bool disabled; /* DRM has disabled our bridge */
381f05a7 133 bool bridge_is_on; /* indicates the bridge is on */
aeac23bd
RK		 134 bool rxsense; /* rxsense state */
135 u8 phy_mask; /* desired phy int mask settings */
b872a8e1 136
b90120a9 137 spinlock_t audio_lock;
6bcf4953 138 struct mutex audio_mutex;
9aaf880e 139 unsigned int sample_rate;
b90120a9
RK		 140 unsigned int audio_cts;
141 unsigned int audio_n;
142 bool audio_enable;
0cd9d142
AY		 143
144 void (*write)(struct dw_hdmi *hdmi, u8 val, int offset);
145 u8 (*read)(struct dw_hdmi *hdmi, int offset);
9aaf880e
FE		 146};
147
aeac23bd
RK		 148#define HDMI_IH_PHY_STAT0_RX_SENSE \
149 (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \
150 HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3)
151
152#define HDMI_PHY_RX_SENSE \
153 (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \
154 HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3)
155
0cd9d142
AY		 156static void dw_hdmi_writel(struct dw_hdmi *hdmi, u8 val, int offset)
157{
158 writel(val, hdmi->regs + (offset << 2));
159}
160
161static u8 dw_hdmi_readl(struct dw_hdmi *hdmi, int offset)
162{
163 return readl(hdmi->regs + (offset << 2));
164}
165
166static void dw_hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
9aaf880e
FE		 167{
168 writeb(val, hdmi->regs + offset);
169}
170
0cd9d142 171static u8 dw_hdmi_readb(struct dw_hdmi *hdmi, int offset)
9aaf880e
FE		 172{
173 return readb(hdmi->regs + offset);
174}
175
0cd9d142
AY		 176static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
177{
178 hdmi->write(hdmi, val, offset);
179}
180
181static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
182{
183 return hdmi->read(hdmi, offset);
184}
185
b21f4b65 186static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
812bc615
RK		 187{
188 u8 val = hdmi_readb(hdmi, reg) & ~mask;
b44ab1b0 189
812bc615
RK		 190 val |= data & mask;
191 hdmi_writeb(hdmi, val, reg);
192}
193
b21f4b65 194static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
b5878339 195 u8 shift, u8 mask)
9aaf880e 196{
812bc615 197 hdmi_modb(hdmi, data << shift, mask, reg);
9aaf880e
FE		 198}
199
351e1354
RK		 200static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
201 unsigned int n)
9aaf880e 202{
622494a3
RK		 203 /* Must be set/cleared first */
204 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
9aaf880e
FE		 205
206 /* nshift factor = 0 */
812bc615 207 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
9aaf880e 208
9aaf880e
FE		 209 hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
210 HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
622494a3
RK		 211 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
212 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
213
214 hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
215 hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
216 hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
9aaf880e
FE		 217}
218
b195fbdb 219static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk)
9aaf880e
FE		 220{
221 unsigned int n = (128 * freq) / 1000;
d0c96d16
RK		 222 unsigned int mult = 1;
223
224 while (freq > 48000) {
225 mult *= 2;
226 freq /= 2;
227 }
9aaf880e
FE		 228
229 switch (freq) {
230 case 32000:
426701d0 231 if (pixel_clk == 25175000)
b195fbdb 232 n = 4576;
426701d0 233 else if (pixel_clk == 27027000)
b195fbdb 234 n = 4096;
426701d0 235 else if (pixel_clk == 74176000 || pixel_clk == 148352000)
9aaf880e
FE		 236 n = 11648;
237 else
238 n = 4096;
d0c96d16 239 n *= mult;
9aaf880e
FE		 240 break;
241
242 case 44100:
426701d0 243 if (pixel_clk == 25175000)
9aaf880e 244 n = 7007;
426701d0 245 else if (pixel_clk == 74176000)
9aaf880e 246 n = 17836;
426701d0 247 else if (pixel_clk == 148352000)
b195fbdb 248 n = 8918;
9aaf880e
FE		 249 else
250 n = 6272;
d0c96d16 251 n *= mult;
9aaf880e
FE		 252 break;
253
254 case 48000:
426701d0 255 if (pixel_clk == 25175000)
b195fbdb 256 n = 6864;
426701d0 257 else if (pixel_clk == 27027000)
b195fbdb 258 n = 6144;
426701d0 259 else if (pixel_clk == 74176000)
9aaf880e 260 n = 11648;
426701d0 261 else if (pixel_clk == 148352000)
b195fbdb 262 n = 5824;
9aaf880e
FE		 263 else
264 n = 6144;
d0c96d16 265 n *= mult;
9aaf880e
FE		 266 break;
267
268 default:
269 break;
270 }
271
272 return n;
273}
274
b21f4b65 275static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
b195fbdb 276 unsigned long pixel_clk, unsigned int sample_rate)
9aaf880e 277{
dfbdaf50 278 unsigned long ftdms = pixel_clk;
f879b38f 279 unsigned int n, cts;
dfbdaf50 280 u64 tmp;
9aaf880e 281
b195fbdb 282 n = hdmi_compute_n(sample_rate, pixel_clk);
9aaf880e 283
dfbdaf50
RK		 284 /*
285 * Compute the CTS value from the N value. Note that CTS and N
286 * can be up to 20 bits in total, so we need 64-bit math. Also
287 * note that our TDMS clock is not fully accurate; it is accurate
288 * to kHz. This can introduce an unnecessary remainder in the
289 * calculation below, so we don't try to warn about that.
290 */
291 tmp = (u64)ftdms * n;
292 do_div(tmp, 128 * sample_rate);
293 cts = tmp;
294
295 dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
296 __func__, sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000,
297 n, cts);
9aaf880e 298
b90120a9
RK		 299 spin_lock_irq(&hdmi->audio_lock);
300 hdmi->audio_n = n;
301 hdmi->audio_cts = cts;
302 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
303 spin_unlock_irq(&hdmi->audio_lock);
9aaf880e
FE		 304}
305
b21f4b65 306static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
9aaf880e 307{
6bcf4953 308 mutex_lock(&hdmi->audio_mutex);
b195fbdb 309 hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate);
6bcf4953 310 mutex_unlock(&hdmi->audio_mutex);
9aaf880e
FE		 311}
312
b21f4b65 313static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
9aaf880e 314{
6bcf4953 315 mutex_lock(&hdmi->audio_mutex);
f879b38f 316 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
b195fbdb 317 hdmi->sample_rate);
6bcf4953 318 mutex_unlock(&hdmi->audio_mutex);
9aaf880e
FE		 319}
320
b5814fff
RK		 321void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
322{
323 mutex_lock(&hdmi->audio_mutex);
324 hdmi->sample_rate = rate;
325 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
b195fbdb 326 hdmi->sample_rate);
b5814fff
RK		 327 mutex_unlock(&hdmi->audio_mutex);
328}
329EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate);
330
b90120a9
RK		 331void dw_hdmi_audio_enable(struct dw_hdmi *hdmi)
332{
333 unsigned long flags;
334
335 spin_lock_irqsave(&hdmi->audio_lock, flags);
336 hdmi->audio_enable = true;
337 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
338 spin_unlock_irqrestore(&hdmi->audio_lock, flags);
339}
340EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable);
341
342void dw_hdmi_audio_disable(struct dw_hdmi *hdmi)
343{
344 unsigned long flags;
345
346 spin_lock_irqsave(&hdmi->audio_lock, flags);
347 hdmi->audio_enable = false;
348 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
349 spin_unlock_irqrestore(&hdmi->audio_lock, flags);
350}
351EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable);
352
9aaf880e
FE		 353/*
354 * this submodule is responsible for the video data synchronization.
355 * for example, for RGB 4:4:4 input, the data map is defined as
356 * pin{47~40} <==> R[7:0]
357 * pin{31~24} <==> G[7:0]
358 * pin{15~8} <==> B[7:0]
359 */
b21f4b65 360static void hdmi_video_sample(struct dw_hdmi *hdmi)
9aaf880e
FE		 361{
362 int color_format = 0;
363 u8 val;
364
365 if (hdmi->hdmi_data.enc_in_format == RGB) {
366 if (hdmi->hdmi_data.enc_color_depth == 8)
367 color_format = 0x01;
368 else if (hdmi->hdmi_data.enc_color_depth == 10)
369 color_format = 0x03;
370 else if (hdmi->hdmi_data.enc_color_depth == 12)
371 color_format = 0x05;
372 else if (hdmi->hdmi_data.enc_color_depth == 16)
373 color_format = 0x07;
374 else
375 return;
376 } else if (hdmi->hdmi_data.enc_in_format == YCBCR444) {
377 if (hdmi->hdmi_data.enc_color_depth == 8)
378 color_format = 0x09;
379 else if (hdmi->hdmi_data.enc_color_depth == 10)
380 color_format = 0x0B;
381 else if (hdmi->hdmi_data.enc_color_depth == 12)
382 color_format = 0x0D;
383 else if (hdmi->hdmi_data.enc_color_depth == 16)
384 color_format = 0x0F;
385 else
386 return;
387 } else if (hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) {
388 if (hdmi->hdmi_data.enc_color_depth == 8)
389 color_format = 0x16;
390 else if (hdmi->hdmi_data.enc_color_depth == 10)
391 color_format = 0x14;
392 else if (hdmi->hdmi_data.enc_color_depth == 12)
393 color_format = 0x12;
394 else
395 return;
396 }
397
398 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
399 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
400 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
401 hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
402
403 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
404 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
405 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
406 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
407 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
408 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
409 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
410 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
411 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
412 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
413 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
414}
415
b21f4b65 416static int is_color_space_conversion(struct dw_hdmi *hdmi)
9aaf880e 417{
ba92b225 418 return hdmi->hdmi_data.enc_in_format != hdmi->hdmi_data.enc_out_format;
9aaf880e
FE		 419}
420
b21f4b65 421static int is_color_space_decimation(struct dw_hdmi *hdmi)
9aaf880e 422{
ba92b225
FE		 423 if (hdmi->hdmi_data.enc_out_format != YCBCR422_8BITS)
424 return 0;
425 if (hdmi->hdmi_data.enc_in_format == RGB ||
426 hdmi->hdmi_data.enc_in_format == YCBCR444)
427 return 1;
428 return 0;
9aaf880e
FE		 429}
430
b21f4b65 431static int is_color_space_interpolation(struct dw_hdmi *hdmi)
9aaf880e 432{
ba92b225
FE		 433 if (hdmi->hdmi_data.enc_in_format != YCBCR422_8BITS)
434 return 0;
435 if (hdmi->hdmi_data.enc_out_format == RGB ||
436 hdmi->hdmi_data.enc_out_format == YCBCR444)
437 return 1;
438 return 0;
9aaf880e
FE		 439}
440
b21f4b65 441static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
9aaf880e
FE		 442{
443 const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
c082f9d7 444 unsigned i;
9aaf880e 445 u32 csc_scale = 1;
9aaf880e
FE		 446
447 if (is_color_space_conversion(hdmi)) {
448 if (hdmi->hdmi_data.enc_out_format == RGB) {
256a38b0
GK		 449 if (hdmi->hdmi_data.colorimetry ==
450 HDMI_COLORIMETRY_ITU_601)
9aaf880e
FE		 451 csc_coeff = &csc_coeff_rgb_out_eitu601;
452 else
453 csc_coeff = &csc_coeff_rgb_out_eitu709;
454 } else if (hdmi->hdmi_data.enc_in_format == RGB) {
256a38b0
GK		 455 if (hdmi->hdmi_data.colorimetry ==
456 HDMI_COLORIMETRY_ITU_601)
9aaf880e
FE		 457 csc_coeff = &csc_coeff_rgb_in_eitu601;
458 else
459 csc_coeff = &csc_coeff_rgb_in_eitu709;
460 csc_scale = 0;
461 }
462 }
463
c082f9d7
RK		 464 /* The CSC registers are sequential, alternating MSB then LSB */
465 for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
466 u16 coeff_a = (*csc_coeff)[0][i];
467 u16 coeff_b = (*csc_coeff)[1][i];
468 u16 coeff_c = (*csc_coeff)[2][i];
469
b5878339 470 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
c082f9d7
RK		 471 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
472 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
473 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
b5878339 474 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
c082f9d7
RK		 475 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
476 }
9aaf880e 477
812bc615
RK		 478 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
479 HDMI_CSC_SCALE);
9aaf880e
FE		 480}
481
b21f4b65 482static void hdmi_video_csc(struct dw_hdmi *hdmi)
9aaf880e
FE		 483{
484 int color_depth = 0;
485 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
486 int decimation = 0;
9aaf880e
FE		 487
488 /* YCC422 interpolation to 444 mode */
489 if (is_color_space_interpolation(hdmi))
490 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
491 else if (is_color_space_decimation(hdmi))
492 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
493
494 if (hdmi->hdmi_data.enc_color_depth == 8)
495 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
496 else if (hdmi->hdmi_data.enc_color_depth == 10)
497 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
498 else if (hdmi->hdmi_data.enc_color_depth == 12)
499 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
500 else if (hdmi->hdmi_data.enc_color_depth == 16)
501 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
502 else
503 return;
504
505 /* Configure the CSC registers */
506 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
812bc615
RK		 507 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
508 HDMI_CSC_SCALE);
9aaf880e 509
b21f4b65 510 dw_hdmi_update_csc_coeffs(hdmi);
9aaf880e
FE		 511}
512
513/*
514 * HDMI video packetizer is used to packetize the data.
515 * for example, if input is YCC422 mode or repeater is used,
516 * data should be repacked this module can be bypassed.
517 */
b21f4b65 518static void hdmi_video_packetize(struct dw_hdmi *hdmi)
9aaf880e
FE		 519{
520 unsigned int color_depth = 0;
521 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
522 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
523 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
bebdf664 524 u8 val, vp_conf;
9aaf880e 525
b5878339
AY		 526 if (hdmi_data->enc_out_format == RGB ||
527 hdmi_data->enc_out_format == YCBCR444) {
528 if (!hdmi_data->enc_color_depth) {
9aaf880e 529 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
b5878339 530 } else if (hdmi_data->enc_color_depth == 8) {
9aaf880e
FE		 531 color_depth = 4;
532 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
b5878339 533 } else if (hdmi_data->enc_color_depth == 10) {
9aaf880e 534 color_depth = 5;
b5878339 535 } else if (hdmi_data->enc_color_depth == 12) {
9aaf880e 536 color_depth = 6;
b5878339 537 } else if (hdmi_data->enc_color_depth == 16) {
9aaf880e 538 color_depth = 7;
b5878339 539 } else {
9aaf880e 540 return;
b5878339 541 }
9aaf880e
FE		 542 } else if (hdmi_data->enc_out_format == YCBCR422_8BITS) {
543 if (!hdmi_data->enc_color_depth ||
544 hdmi_data->enc_color_depth == 8)
545 remap_size = HDMI_VP_REMAP_YCC422_16bit;
546 else if (hdmi_data->enc_color_depth == 10)
547 remap_size = HDMI_VP_REMAP_YCC422_20bit;
548 else if (hdmi_data->enc_color_depth == 12)
549 remap_size = HDMI_VP_REMAP_YCC422_24bit;
550 else
551 return;
552 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
b5878339 553 } else {
9aaf880e 554 return;
b5878339 555 }
9aaf880e
FE		 556
557 /* set the packetizer registers */
558 val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
559 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
560 ((hdmi_data->pix_repet_factor <<
561 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
562 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
563 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
564
812bc615
RK		 565 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
566 HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
9aaf880e
FE		 567
568 /* Data from pixel repeater block */
569 if (hdmi_data->pix_repet_factor > 1) {
bebdf664
RK		 570 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
571 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
9aaf880e 572 } else { /* data from packetizer block */
bebdf664
RK		 573 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
574 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
9aaf880e
FE		 575 }
576
bebdf664
RK		 577 hdmi_modb(hdmi, vp_conf,
578 HDMI_VP_CONF_PR_EN_MASK |
579 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
580
812bc615
RK		 581 hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
582 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
9aaf880e
FE		 583
584 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
585
586 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
bebdf664
RK		 587 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
588 HDMI_VP_CONF_PP_EN_ENABLE |
589 HDMI_VP_CONF_YCC422_EN_DISABLE;
9aaf880e 590 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
bebdf664
RK		 591 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
592 HDMI_VP_CONF_PP_EN_DISABLE |
593 HDMI_VP_CONF_YCC422_EN_ENABLE;
9aaf880e 594 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
bebdf664
RK		 595 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
596 HDMI_VP_CONF_PP_EN_DISABLE |
597 HDMI_VP_CONF_YCC422_EN_DISABLE;
9aaf880e
FE		 598 } else {
599 return;
600 }
601
bebdf664
RK		 602 hdmi_modb(hdmi, vp_conf,
603 HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
604 HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
605
812bc615
RK		 606 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
607 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
608 HDMI_VP_STUFF_PP_STUFFING_MASK |
609 HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
9aaf880e 610
812bc615
RK		 611 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
612 HDMI_VP_CONF);
9aaf880e
FE		 613}
614
b21f4b65 615static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
b5878339 616 unsigned char bit)
9aaf880e 617{
812bc615
RK		 618 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
619 HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
9aaf880e
FE		 620}
621
b21f4b65 622static inline void hdmi_phy_test_enable(struct dw_hdmi *hdmi,
b5878339 623 unsigned char bit)
9aaf880e 624{
812bc615
RK		 625 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET,
626 HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0);
9aaf880e
FE		 627}
628
b21f4b65 629static inline void hdmi_phy_test_clock(struct dw_hdmi *hdmi,
b5878339 630 unsigned char bit)
9aaf880e 631{
812bc615
RK		 632 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET,
633 HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0);
9aaf880e
FE		 634}
635
b21f4b65 636static inline void hdmi_phy_test_din(struct dw_hdmi *hdmi,
b5878339 637 unsigned char bit)
9aaf880e
FE		 638{
639 hdmi_writeb(hdmi, bit, HDMI_PHY_TST1);
640}
641
b21f4b65 642static inline void hdmi_phy_test_dout(struct dw_hdmi *hdmi,
b5878339 643 unsigned char bit)
9aaf880e
FE		 644{
645 hdmi_writeb(hdmi, bit, HDMI_PHY_TST2);
646}
647
b21f4b65 648static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
9aaf880e 649{
a4d3b8b0
AY		 650 u32 val;
651
652 while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
9aaf880e
FE		 653 if (msec-- == 0)
654 return false;
0e6bcf3a 655 udelay(1000);
9aaf880e 656 }
a4d3b8b0
AY		 657 hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
658
9aaf880e
FE		 659 return true;
660}
661
b21f4b65 662static void __hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
b5878339 663 unsigned char addr)
9aaf880e
FE		 664{
665 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
666 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
667 hdmi_writeb(hdmi, (unsigned char)(data >> 8),
b5878339 668 HDMI_PHY_I2CM_DATAO_1_ADDR);
9aaf880e 669 hdmi_writeb(hdmi, (unsigned char)(data >> 0),
b5878339 670 HDMI_PHY_I2CM_DATAO_0_ADDR);
9aaf880e 671 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
b5878339 672 HDMI_PHY_I2CM_OPERATION_ADDR);
9aaf880e
FE		 673 hdmi_phy_wait_i2c_done(hdmi, 1000);
674}
675
b21f4b65 676static int hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
b5878339 677 unsigned char addr)
9aaf880e
FE		 678{
679 __hdmi_phy_i2c_write(hdmi, data, addr);
680 return 0;
681}
682
2fada109 683static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable)
9aaf880e 684{
2fada109 685 hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0,
9aaf880e
FE		 686 HDMI_PHY_CONF0_PDZ_OFFSET,
687 HDMI_PHY_CONF0_PDZ_MASK);
688}
689
b21f4b65 690static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
9aaf880e
FE		 691{
692 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
693 HDMI_PHY_CONF0_ENTMDS_OFFSET,
694 HDMI_PHY_CONF0_ENTMDS_MASK);
695}
696
d346c14e
AY		 697static void dw_hdmi_phy_enable_spare(struct dw_hdmi *hdmi, u8 enable)
698{
699 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
700 HDMI_PHY_CONF0_SPARECTRL_OFFSET,
701 HDMI_PHY_CONF0_SPARECTRL_MASK);
702}
703
b21f4b65 704static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
9aaf880e
FE		 705{
706 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
707 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
708 HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
709}
710
b21f4b65 711static void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
9aaf880e
FE		 712{
713 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
714 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
715 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
716}
717
b21f4b65 718static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
9aaf880e
FE		 719{
720 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
721 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
722 HDMI_PHY_CONF0_SELDATAENPOL_MASK);
723}
724
b21f4b65 725static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
9aaf880e
FE		 726{
727 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
728 HDMI_PHY_CONF0_SELDIPIF_OFFSET,
729 HDMI_PHY_CONF0_SELDIPIF_MASK);
730}
731
b21f4b65 732static int hdmi_phy_configure(struct dw_hdmi *hdmi, unsigned char prep,
9aaf880e
FE		 733 unsigned char res, int cscon)
734{
39cc1535 735 unsigned res_idx;
9aaf880e 736 u8 val, msec;
39cc1535
RK		 737 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
738 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
739 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
740 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
9aaf880e 741
9aaf880e
FE		 742 if (prep)
743 return -EINVAL;
3e46f152
RK		 744
745 switch (res) {
746 case 0: /* color resolution 0 is 8 bit colour depth */
747 case 8:
b21f4b65 748 res_idx = DW_HDMI_RES_8;
3e46f152
RK		 749 break;
750 case 10:
b21f4b65 751 res_idx = DW_HDMI_RES_10;
3e46f152
RK		 752 break;
753 case 12:
b21f4b65 754 res_idx = DW_HDMI_RES_12;
3e46f152
RK		 755 break;
756 default:
9aaf880e 757 return -EINVAL;
3e46f152 758 }
9aaf880e 759
39cc1535
RK		 760 /* PLL/MPLL Cfg - always match on final entry */
761 for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
762 if (hdmi->hdmi_data.video_mode.mpixelclock <=
763 mpll_config->mpixelclock)
764 break;
765
766 for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
767 if (hdmi->hdmi_data.video_mode.mpixelclock <=
768 curr_ctrl->mpixelclock)
769 break;
770
771 for (; phy_config->mpixelclock != ~0UL; phy_config++)
772 if (hdmi->hdmi_data.video_mode.mpixelclock <=
773 phy_config->mpixelclock)
774 break;
775
776 if (mpll_config->mpixelclock == ~0UL ||
777 curr_ctrl->mpixelclock == ~0UL ||
778 phy_config->mpixelclock == ~0UL) {
779 dev_err(hdmi->dev, "Pixel clock %d - unsupported by HDMI\n",
780 hdmi->hdmi_data.video_mode.mpixelclock);
781 return -EINVAL;
782 }
783
9aaf880e
FE		 784 /* Enable csc path */
785 if (cscon)
786 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH;
787 else
788 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS;
789
790 hdmi_writeb(hdmi, val, HDMI_MC_FLOWCTRL);
791
792 /* gen2 tx power off */
b21f4b65 793 dw_hdmi_phy_gen2_txpwron(hdmi, 0);
9aaf880e
FE		 794
795 /* gen2 pddq */
b21f4b65 796 dw_hdmi_phy_gen2_pddq(hdmi, 1);
9aaf880e
FE		 797
798 /* PHY reset */
799 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
800 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ);
801
802 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
803
804 hdmi_phy_test_clear(hdmi, 1);
805 hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
b5878339 806 HDMI_PHY_I2CM_SLAVE_ADDR);
9aaf880e
FE		 807 hdmi_phy_test_clear(hdmi, 0);
808
39cc1535
RK		 809 hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].cpce, 0x06);
810 hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].gmp, 0x15);
9aaf880e 811
3e46f152 812 /* CURRCTRL */
39cc1535 813 hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[res_idx], 0x10);
3e46f152 814
9aaf880e
FE		 815 hdmi_phy_i2c_write(hdmi, 0x0000, 0x13); /* PLLPHBYCTRL */
816 hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
aaa757a0 817
39cc1535
RK		 818 hdmi_phy_i2c_write(hdmi, phy_config->term, 0x19); /* TXTERM */
819 hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 0x09); /* CKSYMTXCTRL */
820 hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 0x0E); /* VLEVCTRL */
034705a4 821
9aaf880e
FE		 822 /* REMOVE CLK TERM */
823 hdmi_phy_i2c_write(hdmi, 0x8000, 0x05); /* CKCALCTRL */
824
2fada109 825 dw_hdmi_phy_enable_powerdown(hdmi, false);
9aaf880e
FE		 826
827 /* toggle TMDS enable */
b21f4b65
AY		 828 dw_hdmi_phy_enable_tmds(hdmi, 0);
829 dw_hdmi_phy_enable_tmds(hdmi, 1);
9aaf880e
FE		 830
831 /* gen2 tx power on */
b21f4b65
AY		 832 dw_hdmi_phy_gen2_txpwron(hdmi, 1);
833 dw_hdmi_phy_gen2_pddq(hdmi, 0);
9aaf880e 834
12b9f204
AY		 835 if (hdmi->dev_type == RK3288_HDMI)
836 dw_hdmi_phy_enable_spare(hdmi, 1);
837
9aaf880e
FE		 838 /*Wait for PHY PLL lock */
839 msec = 5;
840 do {
841 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
842 if (!val)
843 break;
844
845 if (msec == 0) {
846 dev_err(hdmi->dev, "PHY PLL not locked\n");
847 return -ETIMEDOUT;
848 }
849
850 udelay(1000);
851 msec--;
852 } while (1);
853
854 return 0;
855}
856
b21f4b65 857static int dw_hdmi_phy_init(struct dw_hdmi *hdmi)
9aaf880e
FE		 858{
859 int i, ret;
05b1342f 860 bool cscon;
9aaf880e
FE		 861
862 /*check csc whether needed activated in HDMI mode */
05b1342f 863 cscon = hdmi->sink_is_hdmi && is_color_space_conversion(hdmi);
9aaf880e
FE		 864
865 /* HDMI Phy spec says to do the phy initialization sequence twice */
866 for (i = 0; i < 2; i++) {
b21f4b65
AY		 867 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
868 dw_hdmi_phy_sel_interface_control(hdmi, 0);
869 dw_hdmi_phy_enable_tmds(hdmi, 0);
2fada109 870 dw_hdmi_phy_enable_powerdown(hdmi, true);
9aaf880e
FE		 871
872 /* Enable CSC */
873 ret = hdmi_phy_configure(hdmi, 0, 8, cscon);
874 if (ret)
875 return ret;
876 }
877
878 hdmi->phy_enabled = true;
879 return 0;
880}
881
b21f4b65 882static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
9aaf880e 883{
812bc615 884 u8 de;
9aaf880e
FE		 885
886 if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
887 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
888 else
889 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
890
891 /* disable rx detect */
812bc615
RK		 892 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
893 HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
9aaf880e 894
812bc615 895 hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
9aaf880e 896
812bc615
RK		 897 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
898 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
9aaf880e
FE		 899}
900
d4ac4cb6 901static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
9aaf880e 902{
d4ac4cb6
RK		 903 struct hdmi_avi_infoframe frame;
904 u8 val;
9aaf880e 905
d4ac4cb6
RK		 906 /* Initialise info frame from DRM mode */
907 drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
9aaf880e 908
9aaf880e 909 if (hdmi->hdmi_data.enc_out_format == YCBCR444)
d4ac4cb6 910 frame.colorspace = HDMI_COLORSPACE_YUV444;
9aaf880e 911 else if (hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS)
d4ac4cb6 912 frame.colorspace = HDMI_COLORSPACE_YUV422;
9aaf880e 913 else
d4ac4cb6 914 frame.colorspace = HDMI_COLORSPACE_RGB;
9aaf880e
FE		 915
916 /* Set up colorimetry */
917 if (hdmi->hdmi_data.enc_out_format == XVYCC444) {
d4ac4cb6 918 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
5a819ed6 919 if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
d4ac4cb6
RK		 920 frame.extended_colorimetry =
921 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
5a819ed6 922 else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/
d4ac4cb6
RK		 923 frame.extended_colorimetry =
924 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
9aaf880e 925 } else if (hdmi->hdmi_data.enc_out_format != RGB) {
d083c312 926 frame.colorimetry = hdmi->hdmi_data.colorimetry;
d4ac4cb6 927 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
9aaf880e 928 } else { /* Carries no data */
d4ac4cb6
RK		 929 frame.colorimetry = HDMI_COLORIMETRY_NONE;
930 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
9aaf880e
FE		 931 }
932
d4ac4cb6
RK		 933 frame.scan_mode = HDMI_SCAN_MODE_NONE;
934
935 /*
936 * The Designware IP uses a different byte format from standard
937 * AVI info frames, though generally the bits are in the correct
938 * bytes.
939 */
940
941 /*
942 * AVI data byte 1 differences: Colorspace in bits 4,5 rather than 5,6,
943 * active aspect present in bit 6 rather than 4.
944 */
945 val = (frame.colorspace & 3) << 4 | (frame.scan_mode & 0x3);
946 if (frame.active_aspect & 15)
947 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT;
948 if (frame.top_bar || frame.bottom_bar)
949 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR;
950 if (frame.left_bar || frame.right_bar)
951 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR;
952 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
953
954 /* AVI data byte 2 differences: none */
955 val = ((frame.colorimetry & 0x3) << 6) |
956 ((frame.picture_aspect & 0x3) << 4) |
957 (frame.active_aspect & 0xf);
9aaf880e
FE		 958 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
959
d4ac4cb6
RK		 960 /* AVI data byte 3 differences: none */
961 val = ((frame.extended_colorimetry & 0x7) << 4) |
962 ((frame.quantization_range & 0x3) << 2) |
963 (frame.nups & 0x3);
964 if (frame.itc)
965 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID;
9aaf880e
FE		 966 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
967
d4ac4cb6
RK		 968 /* AVI data byte 4 differences: none */
969 val = frame.video_code & 0x7f;
970 hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
9aaf880e
FE		 971
972 /* AVI Data Byte 5- set up input and output pixel repetition */
973 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
974 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
975 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
976 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
977 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
978 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
979 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
980
d4ac4cb6
RK		 981 /*
982 * AVI data byte 5 differences: content type in 0,1 rather than 4,5,
983 * ycc range in bits 2,3 rather than 6,7
984 */
985 val = ((frame.ycc_quantization_range & 0x3) << 2) |
986 (frame.content_type & 0x3);
9aaf880e
FE		 987 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
988
989 /* AVI Data Bytes 6-13 */
d4ac4cb6
RK		 990 hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);
991 hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1);
992 hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);
993 hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1);
994 hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);
995 hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1);
996 hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);
997 hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
9aaf880e
FE		 998}
999
b21f4b65 1000static void hdmi_av_composer(struct dw_hdmi *hdmi,
9aaf880e
FE		 1001 const struct drm_display_mode *mode)
1002{
1003 u8 inv_val;
1004 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1005 int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
e80b9f4e 1006 unsigned int vdisplay;
9aaf880e 1007
9aaf880e
FE		 1008 vmode->mpixelclock = mode->clock * 1000;
1009
1010 dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1011
1012 /* Set up HDMI_FC_INVIDCONF */
1013 inv_val = (hdmi->hdmi_data.hdcp_enable ?
1014 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1015 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1016
b91eee8c 1017 inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
9aaf880e 1018 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
b91eee8c 1019 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW;
9aaf880e 1020
b91eee8c 1021 inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
9aaf880e 1022 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
b91eee8c 1023 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW;
9aaf880e
FE		 1024
1025 inv_val |= (vmode->mdataenablepolarity ?
1026 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1027 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1028
1029 if (hdmi->vic == 39)
1030 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1031 else
b91eee8c 1032 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
9aaf880e 1033 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
b91eee8c 1034 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
9aaf880e 1035
b91eee8c 1036 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
9aaf880e 1037 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
b91eee8c 1038 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
9aaf880e 1039
05b1342f
RK		 1040 inv_val |= hdmi->sink_is_hdmi ?
1041 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
1042 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE;
9aaf880e
FE		 1043
1044 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1045
e80b9f4e
RK		 1046 vdisplay = mode->vdisplay;
1047 vblank = mode->vtotal - mode->vdisplay;
1048 v_de_vs = mode->vsync_start - mode->vdisplay;
1049 vsync_len = mode->vsync_end - mode->vsync_start;
1050
1051 /*
1052 * When we're setting an interlaced mode, we need
1053 * to adjust the vertical timing to suit.
1054 */
1055 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1056 vdisplay /= 2;
1057 vblank /= 2;
1058 v_de_vs /= 2;
1059 vsync_len /= 2;
1060 }
1061
9aaf880e
FE		 1062 /* Set up horizontal active pixel width */
1063 hdmi_writeb(hdmi, mode->hdisplay >> 8, HDMI_FC_INHACTV1);
1064 hdmi_writeb(hdmi, mode->hdisplay, HDMI_FC_INHACTV0);
1065
1066 /* Set up vertical active lines */
e80b9f4e
RK		 1067 hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1);
1068 hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0);
9aaf880e
FE		 1069
1070 /* Set up horizontal blanking pixel region width */
1071 hblank = mode->htotal - mode->hdisplay;
1072 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1073 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1074
1075 /* Set up vertical blanking pixel region width */
9aaf880e
FE		 1076 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1077
1078 /* Set up HSYNC active edge delay width (in pixel clks) */
1079 h_de_hs = mode->hsync_start - mode->hdisplay;
1080 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1081 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1082
1083 /* Set up VSYNC active edge delay (in lines) */
9aaf880e
FE		 1084 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1085
1086 /* Set up HSYNC active pulse width (in pixel clks) */
1087 hsync_len = mode->hsync_end - mode->hsync_start;
1088 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1089 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1090
1091 /* Set up VSYNC active edge delay (in lines) */
9aaf880e
FE		 1092 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1093}
1094
b21f4b65 1095static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi)
9aaf880e
FE		 1096{
1097 if (!hdmi->phy_enabled)
1098 return;
1099
b21f4b65 1100 dw_hdmi_phy_enable_tmds(hdmi, 0);
2fada109 1101 dw_hdmi_phy_enable_powerdown(hdmi, true);
9aaf880e
FE		 1102
1103 hdmi->phy_enabled = false;
1104}
1105
1106/* HDMI Initialization Step B.4 */
b21f4b65 1107static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
9aaf880e
FE		 1108{
1109 u8 clkdis;
1110
1111 /* control period minimum duration */
1112 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1113 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1114 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1115
1116 /* Set to fill TMDS data channels */
1117 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1118 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1119 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1120
1121 /* Enable pixel clock and tmds data path */
1122 clkdis = 0x7F;
1123 clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1124 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1125
1126 clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1127 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1128
1129 /* Enable csc path */
1130 if (is_color_space_conversion(hdmi)) {
1131 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1132 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1133 }
1134}
1135
b21f4b65 1136static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi)
9aaf880e 1137{
812bc615 1138 hdmi_modb(hdmi, 0, HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS);
9aaf880e
FE		 1139}
1140
1141/* Workaround to clear the overflow condition */
b21f4b65 1142static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
9aaf880e
FE		 1143{
1144 int count;
1145 u8 val;
1146
1147 /* TMDS software reset */
1148 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1149
1150 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
1151 if (hdmi->dev_type == IMX6DL_HDMI) {
1152 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1153 return;
1154 }
1155
1156 for (count = 0; count < 4; count++)
1157 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1158}
1159
b21f4b65 1160static void hdmi_enable_overflow_interrupts(struct dw_hdmi *hdmi)
9aaf880e
FE		 1161{
1162 hdmi_writeb(hdmi, 0, HDMI_FC_MASK2);
1163 hdmi_writeb(hdmi, 0, HDMI_IH_MUTE_FC_STAT2);
1164}
1165
b21f4b65 1166static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
9aaf880e
FE		 1167{
1168 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1169 HDMI_IH_MUTE_FC_STAT2);
1170}
1171
b21f4b65 1172static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
9aaf880e
FE		 1173{
1174 int ret;
1175
1176 hdmi_disable_overflow_interrupts(hdmi);
1177
1178 hdmi->vic = drm_match_cea_mode(mode);
1179
1180 if (!hdmi->vic) {
1181 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
9aaf880e
FE		 1182 } else {
1183 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
9aaf880e
FE		 1184 }
1185
1186 if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
b5878339
AY		 1187 (hdmi->vic == 21) || (hdmi->vic == 22) ||
1188 (hdmi->vic == 2) || (hdmi->vic == 3) ||
1189 (hdmi->vic == 17) || (hdmi->vic == 18))
5a819ed6 1190 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601;
9aaf880e 1191 else
5a819ed6 1192 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709;
9aaf880e 1193
d10ca826 1194 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
9aaf880e
FE		 1195 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
1196
1197 /* TODO: Get input format from IPU (via FB driver interface) */
1198 hdmi->hdmi_data.enc_in_format = RGB;
1199
1200 hdmi->hdmi_data.enc_out_format = RGB;
1201
1202 hdmi->hdmi_data.enc_color_depth = 8;
1203 hdmi->hdmi_data.pix_repet_factor = 0;
1204 hdmi->hdmi_data.hdcp_enable = 0;
1205 hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
1206
1207 /* HDMI Initialization Step B.1 */
1208 hdmi_av_composer(hdmi, mode);
1209
1210 /* HDMI Initializateion Step B.2 */
b21f4b65 1211 ret = dw_hdmi_phy_init(hdmi);
9aaf880e
FE		 1212 if (ret)
1213 return ret;
1214
1215 /* HDMI Initialization Step B.3 */
b21f4b65 1216 dw_hdmi_enable_video_path(hdmi);
9aaf880e 1217
f709ec07
RK		 1218 if (hdmi->sink_has_audio) {
1219 dev_dbg(hdmi->dev, "sink has audio support\n");
9aaf880e
FE		 1220
1221 /* HDMI Initialization Step E - Configure audio */
1222 hdmi_clk_regenerator_update_pixel_clock(hdmi);
1223 hdmi_enable_audio_clk(hdmi);
f709ec07
RK		 1224 }
1225
1226 /* not for DVI mode */
1227 if (hdmi->sink_is_hdmi) {
1228 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
9aaf880e
FE		 1229
1230 /* HDMI Initialization Step F - Configure AVI InfoFrame */
d4ac4cb6 1231 hdmi_config_AVI(hdmi, mode);
05b1342f
RK		 1232 } else {
1233 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
9aaf880e
FE		 1234 }
1235
1236 hdmi_video_packetize(hdmi);
1237 hdmi_video_csc(hdmi);
1238 hdmi_video_sample(hdmi);
1239 hdmi_tx_hdcp_config(hdmi);
1240
b21f4b65 1241 dw_hdmi_clear_overflow(hdmi);
05b1342f 1242 if (hdmi->cable_plugin && hdmi->sink_is_hdmi)
9aaf880e
FE		 1243 hdmi_enable_overflow_interrupts(hdmi);
1244
1245 return 0;
1246}
1247
1248/* Wait until we are registered to enable interrupts */
b21f4b65 1249static int dw_hdmi_fb_registered(struct dw_hdmi *hdmi)
9aaf880e
FE		 1250{
1251 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
1252 HDMI_PHY_I2CM_INT_ADDR);
1253
1254 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
1255 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
1256 HDMI_PHY_I2CM_CTLINT_ADDR);
1257
1258 /* enable cable hot plug irq */
aeac23bd 1259 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
9aaf880e
FE		 1260
1261 /* Clear Hotplug interrupts */
aeac23bd
RK		 1262 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1263 HDMI_IH_PHY_STAT0);
9aaf880e 1264
9aaf880e
FE		 1265 return 0;
1266}
1267
b21f4b65 1268static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
9aaf880e
FE		 1269{
1270 u8 ih_mute;
1271
1272 /*
1273 * Boot up defaults are:
1274 * HDMI_IH_MUTE = 0x03 (disabled)
1275 * HDMI_IH_MUTE_* = 0x00 (enabled)
1276 *
1277 * Disable top level interrupt bits in HDMI block
1278 */
1279 ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
1280 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1281 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
1282
1283 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1284
1285 /* by default mask all interrupts */
1286 hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
1287 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
1288 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
1289 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
1290 hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
1291 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
1292 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
1293 hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
1294 hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
1295 hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
1296 hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
1297 hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
1298 hdmi_writeb(hdmi, 0xff, HDMI_CEC_MASK);
1299 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
1300 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
1301
1302 /* Disable interrupts in the IH_MUTE_* registers */
1303 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
1304 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
1305 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
1306 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
1307 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
1308 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
1309 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
1310 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
1311 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
1312 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
1313
1314 /* Enable top level interrupt bits in HDMI block */
1315 ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1316 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
1317 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1318}
1319
b21f4b65 1320static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
9aaf880e 1321{
381f05a7 1322 hdmi->bridge_is_on = true;
b21f4b65 1323 dw_hdmi_setup(hdmi, &hdmi->previous_mode);
9aaf880e
FE		 1324}
1325
b21f4b65 1326static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
9aaf880e 1327{
b21f4b65 1328 dw_hdmi_phy_disable(hdmi);
381f05a7
RK		 1329 hdmi->bridge_is_on = false;
1330}
1331
1332static void dw_hdmi_update_power(struct dw_hdmi *hdmi)
1333{
1334 int force = hdmi->force;
1335
1336 if (hdmi->disabled) {
1337 force = DRM_FORCE_OFF;
1338 } else if (force == DRM_FORCE_UNSPECIFIED) {
aeac23bd 1339 if (hdmi->rxsense)
381f05a7
RK		 1340 force = DRM_FORCE_ON;
1341 else
1342 force = DRM_FORCE_OFF;
1343 }
1344
1345 if (force == DRM_FORCE_OFF) {
1346 if (hdmi->bridge_is_on)
1347 dw_hdmi_poweroff(hdmi);
1348 } else {
1349 if (!hdmi->bridge_is_on)
1350 dw_hdmi_poweron(hdmi);
1351 }
9aaf880e
FE		 1352}
1353
aeac23bd
RK		 1354/*
1355 * Adjust the detection of RXSENSE according to whether we have a forced
1356 * connection mode enabled, or whether we have been disabled. There is
1357 * no point processing RXSENSE interrupts if we have a forced connection
1358 * state, or DRM has us disabled.
1359 *
1360 * We also disable rxsense interrupts when we think we're disconnected
1361 * to avoid floating TDMS signals giving false rxsense interrupts.
1362 *
1363 * Note: we still need to listen for HPD interrupts even when DRM has us
1364 * disabled so that we can detect a connect event.
1365 */
1366static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi)
1367{
1368 u8 old_mask = hdmi->phy_mask;
1369
1370 if (hdmi->force || hdmi->disabled || !hdmi->rxsense)
1371 hdmi->phy_mask |= HDMI_PHY_RX_SENSE;
1372 else
1373 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE;
1374
1375 if (old_mask != hdmi->phy_mask)
1376 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1377}
1378
b21f4b65 1379static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
eb10d635
SL		 1380 struct drm_display_mode *orig_mode,
1381 struct drm_display_mode *mode)
3d1b35a3 1382{
b21f4b65 1383 struct dw_hdmi *hdmi = bridge->driver_private;
3d1b35a3 1384
b872a8e1 1385 mutex_lock(&hdmi->mutex);
3d1b35a3
AY		 1386
1387 /* Store the display mode for plugin/DKMS poweron events */
1388 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
b872a8e1
RK		 1389
1390 mutex_unlock(&hdmi->mutex);
3d1b35a3
AY		 1391}
1392
b21f4b65
AY		 1393static bool dw_hdmi_bridge_mode_fixup(struct drm_bridge *bridge,
1394 const struct drm_display_mode *mode,
1395 struct drm_display_mode *adjusted_mode)
3d1b35a3
AY		 1396{
1397 return true;
1398}
1399
b21f4b65 1400static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
3d1b35a3 1401{
b21f4b65 1402 struct dw_hdmi *hdmi = bridge->driver_private;
3d1b35a3 1403
b872a8e1
RK		 1404 mutex_lock(&hdmi->mutex);
1405 hdmi->disabled = true;
381f05a7 1406 dw_hdmi_update_power(hdmi);
aeac23bd 1407 dw_hdmi_update_phy_mask(hdmi);
b872a8e1 1408 mutex_unlock(&hdmi->mutex);
3d1b35a3
AY		 1409}
1410
b21f4b65 1411static void dw_hdmi_bridge_enable(struct drm_bridge *bridge)
3d1b35a3 1412{
b21f4b65 1413 struct dw_hdmi *hdmi = bridge->driver_private;
3d1b35a3 1414
b872a8e1 1415 mutex_lock(&hdmi->mutex);
b872a8e1 1416 hdmi->disabled = false;
381f05a7 1417 dw_hdmi_update_power(hdmi);
aeac23bd 1418 dw_hdmi_update_phy_mask(hdmi);
b872a8e1 1419 mutex_unlock(&hdmi->mutex);
3d1b35a3
AY		 1420}
1421
b21f4b65 1422static void dw_hdmi_bridge_nop(struct drm_bridge *bridge)
3d1b35a3
AY		 1423{
1424 /* do nothing */
1425}
1426
b21f4b65
AY		 1427static enum drm_connector_status
1428dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
9aaf880e 1429{
b21f4b65 1430 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
d94905e0 1431 connector);
98dbeada 1432
381f05a7
RK		 1433 mutex_lock(&hdmi->mutex);
1434 hdmi->force = DRM_FORCE_UNSPECIFIED;
1435 dw_hdmi_update_power(hdmi);
aeac23bd 1436 dw_hdmi_update_phy_mask(hdmi);
381f05a7
RK		 1437 mutex_unlock(&hdmi->mutex);
1438
98dbeada
RK		 1439 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1440 connector_status_connected : connector_status_disconnected;
9aaf880e
FE		 1441}
1442
b21f4b65 1443static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
9aaf880e 1444{
b21f4b65 1445 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
9aaf880e
FE		 1446 connector);
1447 struct edid *edid;
6c7e66e6 1448 int ret = 0;
9aaf880e
FE		 1449
1450 if (!hdmi->ddc)
1451 return 0;
1452
1453 edid = drm_get_edid(connector, hdmi->ddc);
1454 if (edid) {
1455 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
1456 edid->width_cm, edid->height_cm);
1457
05b1342f 1458 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
f709ec07 1459 hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
9aaf880e
FE		 1460 drm_mode_connector_update_edid_property(connector, edid);
1461 ret = drm_add_edid_modes(connector, edid);
f5ce4057
RK		 1462 /* Store the ELD */
1463 drm_edid_to_eld(connector, edid);
9aaf880e
FE		 1464 kfree(edid);
1465 } else {
1466 dev_dbg(hdmi->dev, "failed to get edid\n");
1467 }
1468
6c7e66e6 1469 return ret;
9aaf880e
FE		 1470}
1471
632d035b
AY		 1472static enum drm_mode_status
1473dw_hdmi_connector_mode_valid(struct drm_connector *connector,
1474 struct drm_display_mode *mode)
1475{
1476 struct dw_hdmi *hdmi = container_of(connector,
1477 struct dw_hdmi, connector);
1478 enum drm_mode_status mode_status = MODE_OK;
1479
8add4190
RK		 1480 /* We don't support double-clocked modes */
1481 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1482 return MODE_BAD;
1483
632d035b
AY		 1484 if (hdmi->plat_data->mode_valid)
1485 mode_status = hdmi->plat_data->mode_valid(connector, mode);
1486
1487 return mode_status;
1488}
1489
b21f4b65 1490static struct drm_encoder *dw_hdmi_connector_best_encoder(struct drm_connector
9aaf880e
FE		 1491 *connector)
1492{
b21f4b65 1493 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
9aaf880e
FE		 1494 connector);
1495
3d1b35a3 1496 return hdmi->encoder;
9aaf880e
FE		 1497}
1498
b21f4b65 1499static void dw_hdmi_connector_destroy(struct drm_connector *connector)
9aaf880e 1500{
3d1b35a3
AY		 1501 drm_connector_unregister(connector);
1502 drm_connector_cleanup(connector);
9aaf880e
FE		 1503}
1504
381f05a7
RK		 1505static void dw_hdmi_connector_force(struct drm_connector *connector)
1506{
1507 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1508 connector);
1509
1510 mutex_lock(&hdmi->mutex);
1511 hdmi->force = connector->force;
1512 dw_hdmi_update_power(hdmi);
aeac23bd 1513 dw_hdmi_update_phy_mask(hdmi);
381f05a7
RK		 1514 mutex_unlock(&hdmi->mutex);
1515}
1516
b21f4b65 1517static struct drm_connector_funcs dw_hdmi_connector_funcs = {
9aaf880e
FE		 1518 .dpms = drm_helper_connector_dpms,
1519 .fill_modes = drm_helper_probe_single_connector_modes,
b21f4b65
AY		 1520 .detect = dw_hdmi_connector_detect,
1521 .destroy = dw_hdmi_connector_destroy,
381f05a7 1522 .force = dw_hdmi_connector_force,
9aaf880e
FE		 1523};
1524
b21f4b65
AY		 1525static struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
1526 .get_modes = dw_hdmi_connector_get_modes,
632d035b 1527 .mode_valid = dw_hdmi_connector_mode_valid,
b21f4b65 1528 .best_encoder = dw_hdmi_connector_best_encoder,
9aaf880e
FE		 1529};
1530
cf88fca5 1531static struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
b21f4b65
AY		 1532 .enable = dw_hdmi_bridge_enable,
1533 .disable = dw_hdmi_bridge_disable,
1534 .pre_enable = dw_hdmi_bridge_nop,
1535 .post_disable = dw_hdmi_bridge_nop,
1536 .mode_set = dw_hdmi_bridge_mode_set,
1537 .mode_fixup = dw_hdmi_bridge_mode_fixup,
3d1b35a3
AY		 1538};
1539
b21f4b65 1540static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
d94905e0 1541{
b21f4b65 1542 struct dw_hdmi *hdmi = dev_id;
d94905e0
RK		 1543 u8 intr_stat;
1544
1545 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1546 if (intr_stat)
1547 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
1548
1549 return intr_stat ? IRQ_WAKE_THREAD : IRQ_NONE;
1550}
1551
b21f4b65 1552static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
9aaf880e 1553{
b21f4b65 1554 struct dw_hdmi *hdmi = dev_id;
aeac23bd 1555 u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat;
9aaf880e
FE		 1556
1557 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
9aaf880e 1558 phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
aeac23bd
RK		 1559 phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0);
1560
1561 phy_pol_mask = 0;
1562 if (intr_stat & HDMI_IH_PHY_STAT0_HPD)
1563 phy_pol_mask |= HDMI_PHY_HPD;
1564 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0)
1565 phy_pol_mask |= HDMI_PHY_RX_SENSE0;
1566 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1)
1567 phy_pol_mask |= HDMI_PHY_RX_SENSE1;
1568 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2)
1569 phy_pol_mask |= HDMI_PHY_RX_SENSE2;
1570 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3)
1571 phy_pol_mask |= HDMI_PHY_RX_SENSE3;
1572
1573 if (phy_pol_mask)
1574 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0);
9aaf880e 1575
aeac23bd
RK		 1576 /*
1577 * RX sense tells us whether the TDMS transmitters are detecting
1578 * load - in other words, there's something listening on the
1579 * other end of the link. Use this to decide whether we should
1580 * power on the phy as HPD may be toggled by the sink to merely
1581 * ask the source to re-read the EDID.
1582 */
1583 if (intr_stat &
1584 (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) {
b872a8e1 1585 mutex_lock(&hdmi->mutex);
aeac23bd
RK		 1586 if (!hdmi->disabled && !hdmi->force) {
1587 /*
1588 * If the RX sense status indicates we're disconnected,
1589 * clear the software rxsense status.
1590 */
1591 if (!(phy_stat & HDMI_PHY_RX_SENSE))
1592 hdmi->rxsense = false;
1593
1594 /*
1595 * Only set the software rxsense status when both
1596 * rxsense and hpd indicates we're connected.
1597 * This avoids what seems to be bad behaviour in
1598 * at least iMX6S versions of the phy.
1599 */
1600 if (phy_stat & HDMI_PHY_HPD)
1601 hdmi->rxsense = true;
1602
1603 dw_hdmi_update_power(hdmi);
1604 dw_hdmi_update_phy_mask(hdmi);
9aaf880e 1605 }
b872a8e1 1606 mutex_unlock(&hdmi->mutex);
aeac23bd
RK		 1607 }
1608
1609 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
1610 dev_dbg(hdmi->dev, "EVENT=%s\n",
1611 phy_int_pol & HDMI_PHY_HPD ? "plugin" : "plugout");
4b9bcaa7 1612 drm_helper_hpd_irq_event(hdmi->bridge->dev);
9aaf880e
FE		 1613 }
1614
1615 hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
aeac23bd
RK		 1616 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
1617 HDMI_IH_MUTE_PHY_STAT0);
9aaf880e
FE		 1618
1619 return IRQ_HANDLED;
1620}
1621
b21f4b65 1622static int dw_hdmi_register(struct drm_device *drm, struct dw_hdmi *hdmi)
9aaf880e 1623{
3d1b35a3
AY		 1624 struct drm_encoder *encoder = hdmi->encoder;
1625 struct drm_bridge *bridge;
9aaf880e
FE		 1626 int ret;
1627
3d1b35a3
AY		 1628 bridge = devm_kzalloc(drm->dev, sizeof(*bridge), GFP_KERNEL);
1629 if (!bridge) {
1630 DRM_ERROR("Failed to allocate drm bridge\n");
1631 return -ENOMEM;
1632 }
9aaf880e 1633
3d1b35a3
AY		 1634 hdmi->bridge = bridge;
1635 bridge->driver_private = hdmi;
b5217bf4
FE		 1636 bridge->funcs = &dw_hdmi_bridge_funcs;
1637 ret = drm_bridge_attach(drm, bridge);
3d1b35a3
AY		 1638 if (ret) {
1639 DRM_ERROR("Failed to initialize bridge with drm\n");
1640 return -EINVAL;
1641 }
9aaf880e 1642
3d1b35a3
AY		 1643 encoder->bridge = bridge;
1644 hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
9aaf880e
FE		 1645
1646 drm_connector_helper_add(&hdmi->connector,
b21f4b65
AY		 1647 &dw_hdmi_connector_helper_funcs);
1648 drm_connector_init(drm, &hdmi->connector, &dw_hdmi_connector_funcs,
1b3f7675 1649 DRM_MODE_CONNECTOR_HDMIA);
9aaf880e 1650
3d1b35a3 1651 hdmi->connector.encoder = encoder;
9aaf880e 1652
3d1b35a3 1653 drm_mode_connector_attach_encoder(&hdmi->connector, encoder);
9aaf880e
FE		 1654
1655 return 0;
1656}
1657
b21f4b65 1658int dw_hdmi_bind(struct device *dev, struct device *master,
3d1b35a3
AY		 1659 void *data, struct drm_encoder *encoder,
1660 struct resource *iores, int irq,
1661 const struct dw_hdmi_plat_data *plat_data)
9aaf880e 1662{
1b3f7675 1663 struct drm_device *drm = data;
17b5001b 1664 struct device_node *np = dev->of_node;
7ed6c665 1665 struct platform_device_info pdevinfo;
9aaf880e 1666 struct device_node *ddc_node;
7ed6c665 1667 struct dw_hdmi_audio_data audio;
b21f4b65 1668 struct dw_hdmi *hdmi;
3d1b35a3 1669 int ret;
0cd9d142 1670 u32 val = 1;
9aaf880e 1671
17b5001b 1672 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
9aaf880e
FE		 1673 if (!hdmi)
1674 return -ENOMEM;
1675
e80b9f4e
RK		 1676 hdmi->connector.interlace_allowed = 1;
1677
3d1b35a3 1678 hdmi->plat_data = plat_data;
17b5001b 1679 hdmi->dev = dev;
3d1b35a3 1680 hdmi->dev_type = plat_data->dev_type;
40678388 1681 hdmi->sample_rate = 48000;
3d1b35a3 1682 hdmi->encoder = encoder;
b872a8e1 1683 hdmi->disabled = true;
aeac23bd
RK		 1684 hdmi->rxsense = true;
1685 hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE);
9aaf880e 1686
b872a8e1 1687 mutex_init(&hdmi->mutex);
6bcf4953 1688 mutex_init(&hdmi->audio_mutex);
b90120a9 1689 spin_lock_init(&hdmi->audio_lock);
6bcf4953 1690
0cd9d142
AY		 1691 of_property_read_u32(np, "reg-io-width", &val);
1692
1693 switch (val) {
1694 case 4:
1695 hdmi->write = dw_hdmi_writel;
1696 hdmi->read = dw_hdmi_readl;
1697 break;
1698 case 1:
1699 hdmi->write = dw_hdmi_writeb;
1700 hdmi->read = dw_hdmi_readb;
1701 break;
1702 default:
1703 dev_err(dev, "reg-io-width must be 1 or 4\n");
1704 return -EINVAL;
1705 }
1706
b5d45901 1707 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
9aaf880e
FE		 1708 if (ddc_node) {
1709 hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
c2c38488
AY		 1710 of_node_put(ddc_node);
1711 if (!hdmi->ddc) {
9aaf880e 1712 dev_dbg(hdmi->dev, "failed to read ddc node\n");
c2c38488
AY		 1713 return -EPROBE_DEFER;
1714 }
9aaf880e 1715
9aaf880e
FE		 1716 } else {
1717 dev_dbg(hdmi->dev, "no ddc property found\n");
1718 }
1719
17b5001b 1720 hdmi->regs = devm_ioremap_resource(dev, iores);
9aaf880e
FE		 1721 if (IS_ERR(hdmi->regs))
1722 return PTR_ERR(hdmi->regs);
1723
9aaf880e
FE		 1724 hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
1725 if (IS_ERR(hdmi->isfr_clk)) {
1726 ret = PTR_ERR(hdmi->isfr_clk);
b5878339 1727 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
9aaf880e
FE		 1728 return ret;
1729 }
1730
1731 ret = clk_prepare_enable(hdmi->isfr_clk);
1732 if (ret) {
b5878339 1733 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
9aaf880e
FE		 1734 return ret;
1735 }
1736
1737 hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
1738 if (IS_ERR(hdmi->iahb_clk)) {
1739 ret = PTR_ERR(hdmi->iahb_clk);
b5878339 1740 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
9aaf880e
FE		 1741 goto err_isfr;
1742 }
1743
1744 ret = clk_prepare_enable(hdmi->iahb_clk);
1745 if (ret) {
b5878339 1746 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
9aaf880e
FE		 1747 goto err_isfr;
1748 }
1749
1750 /* Product and revision IDs */
17b5001b 1751 dev_info(dev,
b5878339
AY		 1752 "Detected HDMI controller 0x%x:0x%x:0x%x:0x%x\n",
1753 hdmi_readb(hdmi, HDMI_DESIGN_ID),
1754 hdmi_readb(hdmi, HDMI_REVISION_ID),
1755 hdmi_readb(hdmi, HDMI_PRODUCT_ID0),
1756 hdmi_readb(hdmi, HDMI_PRODUCT_ID1));
9aaf880e
FE		 1757
1758 initialize_hdmi_ih_mutes(hdmi);
1759
639a202c
PZ		 1760 ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
1761 dw_hdmi_irq, IRQF_SHARED,
1762 dev_name(dev), hdmi);
1763 if (ret)
b33ef619 1764 goto err_iahb;
639a202c 1765
9aaf880e
FE		 1766 /*
1767 * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
1768 * N and cts values before enabling phy
1769 */
1770 hdmi_init_clk_regenerator(hdmi);
1771
1772 /*
1773 * Configure registers related to HDMI interrupt
1774 * generation before registering IRQ.
1775 */
aeac23bd 1776 hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0);
9aaf880e
FE		 1777
1778 /* Clear Hotplug interrupts */
aeac23bd
RK		 1779 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1780 HDMI_IH_PHY_STAT0);
9aaf880e 1781
b21f4b65 1782 ret = dw_hdmi_fb_registered(hdmi);
9aaf880e
FE		 1783 if (ret)
1784 goto err_iahb;
1785
b21f4b65 1786 ret = dw_hdmi_register(drm, hdmi);
9aaf880e
FE		 1787 if (ret)
1788 goto err_iahb;
1789
d94905e0 1790 /* Unmute interrupts */
aeac23bd
RK		 1791 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
1792 HDMI_IH_MUTE_PHY_STAT0);
9aaf880e 1793
7ed6c665
RK		 1794 memset(&pdevinfo, 0, sizeof(pdevinfo));
1795 pdevinfo.parent = dev;
1796 pdevinfo.id = PLATFORM_DEVID_AUTO;
1797
1798 if (hdmi_readb(hdmi, HDMI_CONFIG1_ID) & HDMI_CONFIG1_AHB) {
1799 audio.phys = iores->start;
1800 audio.base = hdmi->regs;
1801 audio.irq = irq;
1802 audio.hdmi = hdmi;
f5ce4057 1803 audio.eld = hdmi->connector.eld;
7ed6c665
RK		 1804
1805 pdevinfo.name = "dw-hdmi-ahb-audio";
1806 pdevinfo.data = &audio;
1807 pdevinfo.size_data = sizeof(audio);
1808 pdevinfo.dma_mask = DMA_BIT_MASK(32);
1809 hdmi->audio = platform_device_register_full(&pdevinfo);
1810 }
1811
17b5001b 1812 dev_set_drvdata(dev, hdmi);
9aaf880e
FE		 1813
1814 return 0;
1815
1816err_iahb:
1817 clk_disable_unprepare(hdmi->iahb_clk);
1818err_isfr:
1819 clk_disable_unprepare(hdmi->isfr_clk);
1820
1821 return ret;
1822}
b21f4b65 1823EXPORT_SYMBOL_GPL(dw_hdmi_bind);
9aaf880e 1824
b21f4b65 1825void dw_hdmi_unbind(struct device *dev, struct device *master, void *data)
9aaf880e 1826{
b21f4b65 1827 struct dw_hdmi *hdmi = dev_get_drvdata(dev);
9aaf880e 1828
7ed6c665
RK		 1829 if (hdmi->audio && !IS_ERR(hdmi->audio))
1830 platform_device_unregister(hdmi->audio);
1831
d94905e0
RK		 1832 /* Disable all interrupts */
1833 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
1834
1b3f7675 1835 hdmi->connector.funcs->destroy(&hdmi->connector);
3d1b35a3 1836 hdmi->encoder->funcs->destroy(hdmi->encoder);
9aaf880e
FE		 1837
1838 clk_disable_unprepare(hdmi->iahb_clk);
1839 clk_disable_unprepare(hdmi->isfr_clk);
1840 i2c_put_adapter(hdmi->ddc);
17b5001b 1841}
b21f4b65 1842EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
9aaf880e
FE		 1843
1844MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
3d1b35a3
AY		 1845MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
1846MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
b21f4b65 1847MODULE_DESCRIPTION("DW HDMI transmitter driver");
9aaf880e 1848MODULE_LICENSE("GPL");
b21f4b65 1849MODULE_ALIAS("platform:dw-hdmi");
Linux 6.x block layer and io_uring tree(s)